* ========== Copyright Header Begin ==========================================
* OpenSPARC T2 Processor File: ncu_xir.s
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
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* ========== Copyright Header End ============================================
#define MAIN_PAGE_NUCLEUS_ALSO
#define MAIN_PAGE_HV_ALSO
#define My_External_Reset setx 0x200005000,%g7,%g1;add %g1,%o1,%g1;set 0x1,%g2;stb %g2,[%g1];done;
! Check that asi_xir_steering is correct
setx 0xffffffffffffffff,%g7,%g1
!! Need to disable some cores also
!setx 0xffffff0000ffffff,%g7,%g1
!stxa %g1,[ASI_CMP_CORE_ENABLE]%asi
setx 0x0006060000060606,%g7,%g1
! Check that XIR trap was not taken by thread yet
setx 0x8900000808,%g7,%g1
! Wait for threads to take the XIR trap
! Wait a little longer in case something else took an xir trap
! Check that RESET_GEN was cleared
setx 0x8900000808,%g7,%g1
! Get access to common cntrs
setx xir_cnt_access,%g7,%g1
/******************************************************
*******************************************************/
setx 0x00000000000000ff,%g7,%l1
/******************************************************
*******************************************************/
SECTION my_xir_trap_handler DATA_VA=0x200005000
Name = my_xir_trap_handler,
projects / OpenSPARC-T2-DV / blob