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* OpenSPARC T2 Processor File: n2_l2_fc_bank3_wayb_f_ldx.s
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#define H_HT0_Hw_Corrected_Error_0x63 My_Corrected_ECC_error_trap
#define H_HT0_Sw_Recoverable_Error_0x40 My_Corrected_ECC_error_trap
#define MAIN_PAGE_HV_ALSO
#define TEST_DATA 0x555555555555555
#define L2_ES_W1C_VALUE 0xc03ffff800000000
.global My_Corrected_ECC_error_trap
! Boot code does not provide TLB translation for IO address space
setx L2_ES_W1C_VALUE, %l0, %g4
! Now access L2 control and status registers
ldxa [%g0] ASI_LSU_CONTROL, %l0
! Remove the lower 2 bits (I-Cache and D-Cache enables)
stxa %l0, [%g0] ASI_LSU_CONTROL
! Write 1 to clear L2 Error status registers
set_L2_Directly_Mapped_Mode:
My_Corrected_ECC_error_trap:
projects / OpenSPARC-T2-DV / blob