* ========== Copyright Header Begin ==========================================
* OpenSPARC T2 Processor File: tcu_asm_ucb_accesses_fc_a.s
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
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* ========== Copyright Header End ============================================
#define MAIN_PAGE_HV_ALSO
#define L2_ENTRY_PA 0xa000000000
#define TEST_DATA0 0x5555555555555555
#define TEST_DATA1 0xaaaaaaaaaaaaaaaa
#define TEST_DATA2 0x4c3fdead4c3fbeef
#define TEST_DATA3 0xdead4c3fbeef4c3f
#define L2_ENTRY_PA0 0x2020000008
#define L2_ES_W1C_VALUE 0xc03ffff800000000
#define SPARC_ES_W1C_VALUE 0xefffffff
! Boot code does not provide TLB translation for IO address space
ldxa [%g0] ASI_LSU_CONTROL, %l0
stxa %l0, [%g0] ASI_LSU_CONTROL
set_L2_Directly_Mapped_Mode:
setx L2CS_PA0, %l6, %g1 ! Bit 1 in L2 Control Status Register
setx 0x2000aa00, %l0, %g2 ! bits [21:18] select way
setx TEST_DATA0, %l0, %g3
setx 0x302000c0, %l0, %g4 ! Mask for extracting [21:3]
stx %g0, [%g4] ! initialize mem addr where JTAG writes back
nop !$EV trig_pc_d(1, @VA(.MAIN.start_jtag_rd_bank0)) -> jtagRdWrL2(0x002000aa00, TEST_DATA0, 0x00302000c0, 0)
! from this point down to chkJtagWrBank0, added to diag, from copy of l2 diag
setx 0x8500000000, %g1, %g2 ! bits [3:0] RW
mov 0xf, %g5 !added to test regress sim item with '%g5 unexp range change message'
! These ldx do asm accesses to 0x85 MBIST mode csr
! These accesses occur during jtag tcu creg rds of DMU csr
! This tests simultaneous access across ucb between tcu & ncu
ldxa [%g0] ASI_LSU_CONTROL, %l0
stxa %l0, [%g0] ASI_LSU_CONTROL
/*******************************************************
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