* ========== Copyright Header Begin ==========================================
* OpenSPARC T2 Processor File: tso_n1_prod_cons_variation1_1.s
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
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* ========== Copyright Header End ============================================
#define global_cnt_reg %i0
setx addrA, tmp0, addrA_reg
setx addrB, tmp0, addrB_reg
setx result0, tmp0, result0_reg
setx result1, tmp0, result1_reg
setx ready0, tmp0, ready0_reg
setx ready1, tmp0, ready1_reg
setx finish_area, tmp0, finish_reg
set ITERATIONS, global_cnt_reg !
!=====================================================
st tmp3, [addrA_reg] ! store non-zero to A
loop01: ! wait for A to be zero again.
ld [finish_reg], test_reg ! check for end
!=========================================================
st tmp3, [addrB_reg] ! store non-zero to B
loop11: ! wait for B to be zero again
ld [finish_reg], test_reg ! check for an end
!=========================================================
!=========================================================
ld [finish_reg], test_reg ! check for an end
ld [addrB_reg], test_reg ! load B until set
ld [addrA_reg], test_reg ! read A and store it
st test_reg, [result0_reg] ! to result place.
st test_reg, [ready0_reg] ! flag ready
ld [finish_reg], test_reg ! check for an end
ld [ready0_reg], test_reg ! wait for ready to be cleared
!=========================================================
ld [finish_reg], test_reg ! check for an end
ld [addrA_reg], test_reg ! load A until set
ld [addrB_reg], test_reg ! load B and store it
st test_reg, [result1_reg] ! to result place
st test_reg, [ready1_reg] ! flag ready
ld [finish_reg], test_reg ! check for an end
ld [ready1_reg], test_reg ! wait for ready to be cleared
!=========================================================
ld [ready0_reg], test_reg ! wait for ready0
ld [ready1_reg], test_reg ! wait for ready1
ld [result0_reg], test_reg ! load the 2 results
ld [result1_reg], test2_reg
brnz test_reg, loop5_cont ! if non-zero-> new-> OK
brz test2_reg, bad_end ! if both 0 -> BAD!!!
st %g0, [result0_reg] ! clear results
st %g0, [addrA_reg] ! clear A and B
st %g0, [ready0_reg] ! clear the ready
mov 0x0, tmp3 ! check for end of test
st tmp3, [finish_reg] ! and flag it
brz global_cnt_reg, good_end
!=========================================================
!====================================================================================
!==========================
SECTION .MY_DATA0 TEXT_VA=0xf0100000, DATA_VA=0xd0100000
PA= ra2pa(0x1d0100000,0),
part_0_ctx_nonzero_tsb_config_0,
TTE_G=1, TTE_Context=0x44, TTE_V=1, TTE_Size=0, TTE_NFO=0,
TTE_IE=0, TTE_Soft2=0, TTE_Diag=0, TTE_Soft=0,
TTE_L=0, TTE_CP=1, TTE_CV=1, TTE_E=0, TTE_P=0, TTE_W=1
PA= ra2pa(0x1f0100000,0),
part_0_ctx_nonzero_tsb_config_0,
TTE_G=1, TTE_Context=0x44, TTE_V=1, TTE_Size=0, TTE_NFO=0,
TTE_IE=0, TTE_Soft2=0, TTE_Diag=0, TTE_Soft=0,
TTE_L=0, TTE_CP=1, TTE_CV=1, TTE_E=0, TTE_P=0, TTE_W=1
SECTION .MY_DATA1 TEXT_VA=0xf1110000, DATA_VA=0xd1110000
PA= ra2pa(0x1d1110000,0),
part_0_ctx_nonzero_tsb_config_1,
TTE_G=1, TTE_Context=0x44, TTE_V=1, TTE_Size=0, TTE_NFO=0,
TTE_IE=0, TTE_Soft2=0, TTE_Diag=0, TTE_Soft=0,
TTE_L=0, TTE_CP=1, TTE_CV=1, TTE_E=0, TTE_P=0, TTE_W=1
PA= ra2pa(0x1f1110000,0),
part_0_ctx_nonzero_tsb_config_1,
TTE_G=1, TTE_Context=0x44, TTE_V=1, TTE_Size=0, TTE_NFO=0,
TTE_IE=0, TTE_Soft2=0, TTE_Diag=0, TTE_Soft=0,
TTE_L=0, TTE_CP=1, TTE_CV=1, TTE_E=0, TTE_P=0, TTE_W=1