* ========== Copyright Header Begin ==========================================
* OpenSPARC T2 Processor File: FcNiu_Trap_Handler.s
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
* For the avoidance of doubt, and except that if any non-GPL license
* choice is available it will apply instead, Sun elects to use only
* the General Public License version 2 (GPLv2) at this time for any
* software where a choice of GPL license versions is made
* available with the language indicating that GPLv2 or any later version
* may be used, or where a choice of which version of the GPL is applied is
* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
* CA 95054 USA or visit www.sun.com if you need additional information or
* ========== Copyright Header End ============================================
/* ******************************************************************** */
/* NIU Tx DMA and Rx-DMA initialization for TRAPS */
/* ******************************************************************** */
setx MAC_ID, %g1, %o0 ! 1st Parameter
setx SetTxDMAActive_list, %g1, %o1 ! 2st parameter
nop ! $EV trig_pc_d(1, @VA(.MAIN.HTrap_NIU_TxDMAActivate)) -> NIU_TxDMAActivate (MAC_ID, TxDmaActive_list)
HTrap_NIU_AddTxChannels :
nop ! $EV trig_pc_d(1, @VA(.MAIN.HTrap_NIU_AddTxChannels)) -> NIU_AddTxChannels(MAC_ID, NIU_TxDmaNoUE)
ldxa [%g2]ASI_PRIMARY_LITTLE, %g5 ! Just for delay
HTrap_NIU_SetTxMaxBurst :
setx NIU_TxDmaNo, %g1, %o0 ! 1st parameter :
setx SetTxMaxBurst_Data, %g1, %o1 ! 2nd parameter
nop ! $EV trig_pc_d(1, @VA(.MAIN.HTrap_NIU_SetTxMaxBurst)) -> NIU_SetTxMaxBurst (MAC_ID, NIU_TxDmaNoUE, TxMaxBurst_Data)
ldxa [%g2]ASI_PRIMARY_LITTLE, %g5 ! Just for delay
setx NIU_TxDmaNo, %g1, %o0 ! 1st parameter :
nop ! $EV trig_pc_d(1, @VA(.MAIN.HTrap_NIU_InitTxDma)) -> NIU_InitTxDma (MAC_ID, NIU_TxDmaNoUE, NIU_Xlate_On)
ldxa [%g2]ASI_PRIMARY_LITTLE, %g5 ! Just for delay
HTrap_NIU_TxDma_Init_Done:
/* ******************************************************************** */
nop !$EV trig_pc_d(1, @VA(.MAIN.HTrap_NIU_RxInitDma)) -> NIU_InitRxDma(RXDMA_CHNL, RX_DESC_RING_LENGTH, RX_COMPL_RING_LEN,, RBR_CONFIG_B_DATA_UE, RX_INITIAL_KICK, NIU_Xlate_On)
setx 0x5, %g1, %g4 ! Delay for Vera to complete
ldxa [%g2]ASI_PRIMARY_LITTLE, %g5
brnz %g4, HTrap_delay_loop_Rx
setx RXDMA_CHNL, %g1, %o0
setx RX_DESC_RING_LENGTH, %g1, %o1
setx RX_COMPL_RING_LEN, %g1, %o2
setx RBR_CONFIG_B_DATA, %g1, %o3
setx RX_INITIAL_KICK, %g1, %o4
HTrap_NIU_RxDma_Init_Done:
/* ******************************************************************** */
/* ISR for kicking in Tx packets */
/* ******************************************************************** */
nop ! $EV trig_pc_d(1, @VA(.MAIN.HTrap_NIU_Tx_PktConfig)) -> pktGenConfig(MAC_ID, FRAME_TYPE, FRAME_CLASS, HTRAP_NIU_TX_PKT_LEN)
nop ! $EV trig_pc_d(1, @VA(.MAIN.HTrap_NIU_Tx_Gen_Packet)) -> TxPktGen(MAC_ID, NIU_TxDmaNoUE, HTRAP_NIU_TX_PKT_CNT)
HTrap_NIU_delay_loop_tmp:
ldxa [%g2]ASI_PRIMARY_LITTLE, %g5
brnz %g4, HTrap_NIU_delay_loop_tmp
setx 0x100000100, %g1, %g2 ! $EV trig_pc_d(1, @VA(.MAIN.HTrap_SetTxRingKick)) -> NIU_SetTxRingKick(MAC_ID, NIU_TxDmaNoUE)
setx NIU_TxDmaNo, %g1, %o0
ldxa [%g2]ASI_PRIMARY_LITTLE, %g3
setx TX_RING_KICK_Addr, %g1, %g2
stxa %g3, [%g2]ASI_PRIMARY_LITTLE
setx NIU_TxDmaNo, %g1, %o0
setx TX_CS_Data, %g1, %g3
setx TX_CS_Addr, %g1, %g2
stxa %g3, [%g2]ASI_PRIMARY_LITTLE
nop ! $EV trig_pc_d(1, @VA(.MAIN.test_passed_tx)) -> NIU_EXIT_chk(MAC_ID)
/* ******************************************************************** */
/* ISR for kicking in Rx packets */
/* ******************************************************************** */
nop !$EV trig_pc_d(1, @VA(.MAIN.HTrap_NIU_RxPkt_Conf)) -> NIU_RxPktConf(HTRAP_NIU_RXMAC_PKTCNT)
ldxa [%g2]ASI_PRIMARY_LITTLE, %g5 ! Just for Delay
setx HTRAP_NIU_RXMAC_PKTCNT, %g1, %g6 ! Packet count
HTrap_NIU_Rx_pktcnt_loop:
nop !$EV trig_pc_d(1, @VA(.MAIN.HTrap_NIU_Rx_pktcnt_loop)) -> NIU_RxGenPkt(MAC_ID, RXDMA_CHNL, 1, HTRAP_NIU_MAC_PKT_LEN, 1)
ldxa [%g2]ASI_PRIMARY_LITTLE, %g5 ! just for delay
brnz %g6, HTrap_NIU_Rx_pktcnt_loop
/* ******************************************************************** */
/* Setup NCU for NIU Traps */
/* ******************************************************************** */
xor %g7, 0x2, %g7 ! Reset interrupt enable
! Initially set all the Interrupt Management Registers
! Later will set all those not used to have a different vector number
setx INT_MAN, %g1, %g2 ! %g2 = INT_MAN reg. addr.
setx INT_MAN_COUNT, %g1, %g4 ! %g4 = INT_MAN reg. count value
set 1, %g5 ! %g5 = value to write to INT_MAN reg.
add %g2, INT_MAN_STEP, %g2
bne HTrap_NCU_Init_Man_loop
/* Initialize the NIU for TX DMA interrupt. */
NIU_TX_LD_IM0_INTR_ON_MARK( NIU_TxDmaNo, %g1, %g2, %g3, %g4, 0 )
or %g7, 0x2, %g7 ! Set interrupt enable
/* ******************************************************************** */
/* ******************************************************************** */
setx 0x300000000, %l2, %l6
! Clear the interrupt in the core
ldxa [%g0]ASI_SWVR_INTR_R, %l3
setx TX_CS, %g1, %g2 ! TX_CS, Tx DMA channel 0
ldxa [%g2]ASI_PRIMARY_LITTLE, %g1 ! Reset MK
setx LDGIMGN, %g1, %g2 ! logical device group 0
setx 0x80000001, %g1, %g3
stxa %g3, [%g2]ASI_PRIMARY_LITTLE
/* ******************************************************************** */