verif/diag/assembly/include/dmu_peu_regs.h

/*
* ========== Copyright Header Begin ==========================================
*
* OpenSPARC T2 Processor File: dmu_peu_regs.h
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
*
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
*
* For the avoidance of doubt, and except that if any non-GPL license
* choice is available it will apply instead, Sun elects to use only
* the General Public License version 2 (GPLv2) at this time for any
* software where a choice of GPL license versions is made
* available with the language indicating that GPLv2 or any later version
* may be used, or where a choice of which version of the GPL is applied is
* otherwise unspecified.
*
* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
* CA 95054 USA or visit www.sun.com if you need additional information or
* have any questions.
*
*
* ========== Copyright Header End ============================================
*/
!!
!! This file is generated by somePerson using the command:
!!  csr2assembly_reg_defines.pl /import/n2-svl-localdir2/somePerson/n2cdmspp/verif/env/dmu/vera/csrtool /import/n2-svl-localdir2/somePerson/n2cdmspp/verif/env/ilu_peu/vera/csrtool
!!

!! Register definitions from :/verif/env/dmu/vera/csrtool/cru_a.csr_define.vri 1.1


#define FIRE_DLC_CRU_CSR_A_DMC_DBG_SEL_A_REG_ADDR                mpeval(0x00653000 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_DLC_CRU_CSR_A_DMC_DBG_SEL_A_REG_WRITE_MASK          0x00000000000003ff
#define FIRE_DLC_CRU_CSR_A_DMC_DBG_SEL_A_REG_POR_VALUE           0x0000000000000000

#define FIRE_DLC_CRU_CSR_A_DMC_DBG_SEL_B_REG_ADDR                mpeval(0x00653008 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_DLC_CRU_CSR_A_DMC_DBG_SEL_B_REG_WRITE_MASK          0x00000000000003ff
#define FIRE_DLC_CRU_CSR_A_DMC_DBG_SEL_B_REG_POR_VALUE           0x0000000000000000

#define FIRE_DLC_CRU_CSR_A_DMC_PCIE_CFG_ADDR                     mpeval(0x00653100 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_DLC_CRU_CSR_A_DMC_PCIE_CFG_WRITE_MASK               0x00000000ff00ffff
#define FIRE_DLC_CRU_CSR_A_DMC_PCIE_CFG_POR_VALUE                0x0000000000000000


!! Register definitions from :/verif/env/dmu/vera/csrtool/csr_a.csr_define.vri 1.3


#define FIRE_DLC_MMU_CSR_A_CTL_ADDR                              mpeval(0x00640000 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_DLC_MMU_CSR_A_CTL_WRITE_MASK                        0x00000000000f170f
#define FIRE_DLC_MMU_CSR_A_CTL_POR_VALUE                         0x0000000000000000

#define FIRE_DLC_MMU_CSR_A_TSB_ADDR                              mpeval(0x00640008 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_DLC_MMU_CSR_A_TSB_WRITE_MASK                        0x0000007fffffe10f
#define FIRE_DLC_MMU_CSR_A_TSB_POR_VALUE                         0x0000000000000000

#define FIRE_DLC_MMU_CSR_A_FSH_ADDR                              mpeval(0x00640100 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_DLC_MMU_CSR_A_FSH_WRITE_MASK                        0x0000007fffffffc0
#define FIRE_DLC_MMU_CSR_A_FSH_POR_VALUE                         0x0000000000000000

#define FIRE_DLC_MMU_CSR_A_INV_ADDR                              mpeval(0x00640108 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_DLC_MMU_CSR_A_INV_WRITE_MASK                        0xffffffffffffffff
#define FIRE_DLC_MMU_CSR_A_INV_POR_VALUE                         0x0000000000000000

#define FIRE_DLC_MMU_CSR_A_LOG_ADDR                              mpeval(0x00641000 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_DLC_MMU_CSR_A_LOG_WRITE_MASK                        0x00000000001fffff
#define FIRE_DLC_MMU_CSR_A_LOG_POR_VALUE                         0x00000000001fffff

#define FIRE_DLC_MMU_CSR_A_INT_EN_ADDR                           mpeval(0x00641008 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_DLC_MMU_CSR_A_INT_EN_WRITE_MASK                     0x001fffff001fffff
#define FIRE_DLC_MMU_CSR_A_INT_EN_POR_VALUE                      0x0000000000000000

#define FIRE_DLC_MMU_CSR_A_EN_ERR_ADDR                           mpeval(0x00641010 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_DLC_MMU_CSR_A_EN_ERR_WRITE_MASK                     0x0000000000000000
#define FIRE_DLC_MMU_CSR_A_EN_ERR_POR_VALUE                      0x0000000000000000

#define FIRE_DLC_MMU_CSR_A_ERR_RW1C_ALIAS_ADDR                   mpeval(0x00641018 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_DLC_MMU_CSR_A_ERR_RW1C_ALIAS_WRITE_MASK             0x0000000000000000
#define FIRE_DLC_MMU_CSR_A_ERR_RW1C_ALIAS_POR_VALUE              0x0000000000000000

#define FIRE_DLC_MMU_CSR_A_ERR_RW1S_ALIAS_ADDR                   mpeval(0x00641020 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_DLC_MMU_CSR_A_ERR_RW1S_ALIAS_WRITE_MASK             0x001fffff001fffff
#define FIRE_DLC_MMU_CSR_A_ERR_RW1S_ALIAS_POR_VALUE              0x0000000000000000

#define FIRE_DLC_MMU_CSR_A_FLTA_ADDR                             mpeval(0x00641028 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_DLC_MMU_CSR_A_FLTA_WRITE_MASK                       0xfffffffffffffffc
#define FIRE_DLC_MMU_CSR_A_FLTA_POR_VALUE                        0x0000000000000000

#define FIRE_DLC_MMU_CSR_A_FLTS_ADDR                             mpeval(0x00641030 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_DLC_MMU_CSR_A_FLTS_WRITE_MASK                       0x000001ff007fffff
#define FIRE_DLC_MMU_CSR_A_FLTS_POR_VALUE                        0x0000000000000000

#define FIRE_DLC_MMU_CSR_A_PRFC_ADDR                             mpeval(0x00642000 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_DLC_MMU_CSR_A_PRFC_WRITE_MASK                       0x000000000000ffff
#define FIRE_DLC_MMU_CSR_A_PRFC_POR_VALUE                        0x0000000000000000

#define FIRE_DLC_MMU_CSR_A_PRF0_ADDR                             mpeval(0x00642008 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_DLC_MMU_CSR_A_PRF0_WRITE_MASK                       0xffffffffffffffff
#define FIRE_DLC_MMU_CSR_A_PRF0_POR_VALUE                        0x0000000000000000

#define FIRE_DLC_MMU_CSR_A_PRF1_ADDR                             mpeval(0x00642010 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_DLC_MMU_CSR_A_PRF1_WRITE_MASK                       0xffffffffffffffff
#define FIRE_DLC_MMU_CSR_A_PRF1_POR_VALUE                        0x0000000000000000

#define FIRE_DLC_MMU_CSR_A_VTB_ADDR                              mpeval(0x00646000 + N2_DMU_PEU_BASE_ADDR)
!! This register maps to a ram with a depth of: 64
#define FIRE_DLC_MMU_CSR_A_VTB_WRITE_MASK                        0x01fffffffffff801
#define FIRE_DLC_MMU_CSR_A_VTB_POR_VALUE                         0x0000000000000000

#define FIRE_DLC_MMU_CSR_A_PTB_ADDR                              mpeval(0x00647000 + N2_DMU_PEU_BASE_ADDR)
!! This register maps to a ram with a depth of: 64
#define FIRE_DLC_MMU_CSR_A_PTB_WRITE_MASK                        0x0000007fffffffc1
#define FIRE_DLC_MMU_CSR_A_PTB_POR_VALUE                         0x0000000000000000

#define FIRE_DLC_MMU_CSR_A_TDB_ADDR                              mpeval(0x00648000 + N2_DMU_PEU_BASE_ADDR)
!! This register maps to a ram with a depth of: 512
#define FIRE_DLC_MMU_CSR_A_TDB_WRITE_MASK                        0xfffff07fffffe03f
!! contains x #define FIRE_DLC_MMU_CSR_A_TDB_POR_VALUE           0xxxxxxxxxxxxxxxxxxxxx00000xxxxxxxxxxxxxxxxxxxxxxxxxx0000000xxxxxx

#define FIRE_DLC_MMU_CSR_A_DEV2IOTSB_ADDR                        mpeval(0x00649000 + N2_DMU_PEU_BASE_ADDR)
!! This register maps to a ram with a depth of: 16
#define FIRE_DLC_MMU_CSR_A_DEV2IOTSB_WRITE_MASK                  0x1f1f1f1f1f1f1f1f
#define FIRE_DLC_MMU_CSR_A_DEV2IOTSB_POR_VALUE                   0x0000000000000000

#define FIRE_DLC_MMU_CSR_A_IOTSBDESC_ADDR                        mpeval(0x00649100 + N2_DMU_PEU_BASE_ADDR)
!! This register maps to a ram with a depth of: 32
#define FIRE_DLC_MMU_CSR_A_IOTSBDESC_WRITE_MASK                  0x8fffffffffffffff
#define FIRE_DLC_MMU_CSR_A_IOTSBDESC_POR_VALUE                   0x0000000000000000


!! Register definitions from :/verif/env/dmu/vera/csrtool/eqs_a.csr_define.vri 1.1


#define FIRE_DLC_IMU_EQS_CSR_A_EQ_BASE_ADDRESS_ADDR              mpeval(0x00610000 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_DLC_IMU_EQS_CSR_A_EQ_BASE_ADDRESS_WRITE_MASK        0xfffffffffff80000
#define FIRE_DLC_IMU_EQS_CSR_A_EQ_BASE_ADDRESS_POR_VALUE         0x0000000000000000

#define FIRE_DLC_IMU_EQS_CSR_A_EQ_CTRL_SET_ADDR                  mpeval(0x00611000 + N2_DMU_PEU_BASE_ADDR)
!! This register maps to a ram with a depth of: 36
#define FIRE_DLC_IMU_EQS_CSR_A_EQ_CTRL_SET_WRITE_MASK            0x0200100000000000
#define FIRE_DLC_IMU_EQS_CSR_A_EQ_CTRL_SET_POR_VALUE             0x0000000000000000

#define FIRE_DLC_IMU_EQS_CSR_A_EQ_CTRL_CLR_ADDR                  mpeval(0x00611200 + N2_DMU_PEU_BASE_ADDR)
!! This register maps to a ram with a depth of: 36
#define FIRE_DLC_IMU_EQS_CSR_A_EQ_CTRL_CLR_WRITE_MASK            0x0200900000000000
#define FIRE_DLC_IMU_EQS_CSR_A_EQ_CTRL_CLR_POR_VALUE             0x0000000000000000

#define FIRE_DLC_IMU_EQS_CSR_A_EQ_STATE_ADDR                     mpeval(0x00611400 + N2_DMU_PEU_BASE_ADDR)
!! This register maps to a ram with a depth of: 36
#define FIRE_DLC_IMU_EQS_CSR_A_EQ_STATE_WRITE_MASK               0x0000000000000000
#define FIRE_DLC_IMU_EQS_CSR_A_EQ_STATE_POR_VALUE                0x0000000000000001

#define FIRE_DLC_IMU_EQS_CSR_A_EQ_TAIL_ADDR                      mpeval(0x00611600 + N2_DMU_PEU_BASE_ADDR)
!! This register maps to a ram with a depth of: 36
#define FIRE_DLC_IMU_EQS_CSR_A_EQ_TAIL_WRITE_MASK                0x000000000000007f
#define FIRE_DLC_IMU_EQS_CSR_A_EQ_TAIL_POR_VALUE                 0x0000000000000000

#define FIRE_DLC_IMU_EQS_CSR_A_EQ_HEAD_ADDR                      mpeval(0x00611800 + N2_DMU_PEU_BASE_ADDR)
!! This register maps to a ram with a depth of: 36
#define FIRE_DLC_IMU_EQS_CSR_A_EQ_HEAD_WRITE_MASK                0x000000000000007f
#define FIRE_DLC_IMU_EQS_CSR_A_EQ_HEAD_POR_VALUE                 0x0000000000000000


!! Register definitions from :/verif/env/dmu/vera/csrtool/ics_a.csr_define.vri 1.3


#define FIRE_DLC_IMU_ICS_CSR_A_IMU_ERROR_LOG_EN_REG_ADDR         mpeval(0x00631000 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_DLC_IMU_ICS_CSR_A_IMU_ERROR_LOG_EN_REG_WRITE_MASK   0x0000000000007fff
#define FIRE_DLC_IMU_ICS_CSR_A_IMU_ERROR_LOG_EN_REG_POR_VALUE    0x0000000000007fff

#define FIRE_DLC_IMU_ICS_CSR_A_IMU_INT_EN_REG_ADDR               mpeval(0x00631008 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_DLC_IMU_ICS_CSR_A_IMU_INT_EN_REG_WRITE_MASK         0x00007fff00007fff
#define FIRE_DLC_IMU_ICS_CSR_A_IMU_INT_EN_REG_POR_VALUE          0x0000000000000000

#define FIRE_DLC_IMU_ICS_CSR_A_IMU_ENABLED_ERROR_STATUS_REG_ADDR  mpeval(0x00631010 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_DLC_IMU_ICS_CSR_A_IMU_ENABLED_ERROR_STATUS_REG_WRITE_MASK  0x0000000000000000
#define FIRE_DLC_IMU_ICS_CSR_A_IMU_ENABLED_ERROR_STATUS_REG_POR_VALUE  0x0000000000000000

#define FIRE_DLC_IMU_ICS_CSR_A_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_ADDR  mpeval(0x00631018 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_DLC_IMU_ICS_CSR_A_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_WRITE_MASK  0x0000000000000000
#define FIRE_DLC_IMU_ICS_CSR_A_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_POR_VALUE  0x0000000000000000

#define FIRE_DLC_IMU_ICS_CSR_A_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_ADDR  mpeval(0x00631020 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_DLC_IMU_ICS_CSR_A_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_WRITE_MASK  0x00007fff00007fff
#define FIRE_DLC_IMU_ICS_CSR_A_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_POR_VALUE  0x0000000000000000

#define FIRE_DLC_IMU_ICS_CSR_A_IMU_RDS_ERROR_LOG_REG_ADDR        mpeval(0x00631028 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_DLC_IMU_ICS_CSR_A_IMU_RDS_ERROR_LOG_REG_WRITE_MASK  0xffffffffffffffff
#define FIRE_DLC_IMU_ICS_CSR_A_IMU_RDS_ERROR_LOG_REG_POR_VALUE   0x0000000000000000

#define FIRE_DLC_IMU_ICS_CSR_A_IMU_SCS_ERROR_LOG_REG_ADDR        mpeval(0x00631030 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_DLC_IMU_ICS_CSR_A_IMU_SCS_ERROR_LOG_REG_WRITE_MASK  0xffffffffffff003f
#define FIRE_DLC_IMU_ICS_CSR_A_IMU_SCS_ERROR_LOG_REG_POR_VALUE   0x0000000000000000

#define FIRE_DLC_IMU_ICS_CSR_A_IMU_EQS_ERROR_LOG_REG_ADDR        mpeval(0x00631038 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_DLC_IMU_ICS_CSR_A_IMU_EQS_ERROR_LOG_REG_WRITE_MASK  0x000000000000003f
#define FIRE_DLC_IMU_ICS_CSR_A_IMU_EQS_ERROR_LOG_REG_POR_VALUE   0x0000000000000000

#define FIRE_DLC_IMU_ICS_CSR_A_DMC_INTERRUPT_MASK_REG_ADDR       mpeval(0x00631800 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_DLC_IMU_ICS_CSR_A_DMC_INTERRUPT_MASK_REG_WRITE_MASK  0xc000000000000003
#define FIRE_DLC_IMU_ICS_CSR_A_DMC_INTERRUPT_MASK_REG_POR_VALUE  0x0000000000000000

#define FIRE_DLC_IMU_ICS_CSR_A_DMC_INTERRUPT_STATUS_REG_ADDR     mpeval(0x00631808 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_DLC_IMU_ICS_CSR_A_DMC_INTERRUPT_STATUS_REG_WRITE_MASK  0x0000000000000000
#define FIRE_DLC_IMU_ICS_CSR_A_DMC_INTERRUPT_STATUS_REG_POR_VALUE  0x0000000000000000

#define FIRE_DLC_IMU_ICS_CSR_A_IMU_PERF_CNTRL_ADDR               mpeval(0x00632000 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_DLC_IMU_ICS_CSR_A_IMU_PERF_CNTRL_WRITE_MASK         0x000000000000ffff
#define FIRE_DLC_IMU_ICS_CSR_A_IMU_PERF_CNTRL_POR_VALUE          0x0000000000000000

#define FIRE_DLC_IMU_ICS_CSR_A_IMU_PERF_CNT0_ADDR                mpeval(0x00632008 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_DLC_IMU_ICS_CSR_A_IMU_PERF_CNT0_WRITE_MASK          0xffffffffffffffff
#define FIRE_DLC_IMU_ICS_CSR_A_IMU_PERF_CNT0_POR_VALUE           0x0000000000000000

#define FIRE_DLC_IMU_ICS_CSR_A_IMU_PERF_CNT1_ADDR                mpeval(0x00632010 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_DLC_IMU_ICS_CSR_A_IMU_PERF_CNT1_WRITE_MASK          0xffffffffffffffff
#define FIRE_DLC_IMU_ICS_CSR_A_IMU_PERF_CNT1_POR_VALUE           0x0000000000000000

#define FIRE_DLC_IMU_ICS_CSR_A_MSI_32_ADDR_REG_ADDR              mpeval(0x00634000 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_DLC_IMU_ICS_CSR_A_MSI_32_ADDR_REG_WRITE_MASK        0x00000000ffff0000
#define FIRE_DLC_IMU_ICS_CSR_A_MSI_32_ADDR_REG_POR_VALUE         0x0000000000000000

#define FIRE_DLC_IMU_ICS_CSR_A_MSI_64_ADDR_REG_ADDR              mpeval(0x00634008 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_DLC_IMU_ICS_CSR_A_MSI_64_ADDR_REG_WRITE_MASK        0xffffffffffff0000
#define FIRE_DLC_IMU_ICS_CSR_A_MSI_64_ADDR_REG_POR_VALUE         0x0000000000000000

#define FIRE_DLC_IMU_ICS_CSR_A_MEM_64_PCIE_OFFSET_REG_ADDR       mpeval(0x00634018 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_DLC_IMU_ICS_CSR_A_MEM_64_PCIE_OFFSET_REG_WRITE_MASK  0xffffffffffffffff
#define FIRE_DLC_IMU_ICS_CSR_A_MEM_64_PCIE_OFFSET_REG_POR_VALUE  0x0000000000000000


!! Register definitions from :/verif/env/dmu/vera/csrtool/intx_a.csr_define.vri 1.1


#define FIRE_DLC_IMU_RDS_INTX_CSR_A_INTX_STATUS_REG_ADDR         mpeval(0x0060b000 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_DLC_IMU_RDS_INTX_CSR_A_INTX_STATUS_REG_WRITE_MASK   0x0000000000000000
#define FIRE_DLC_IMU_RDS_INTX_CSR_A_INTX_STATUS_REG_POR_VALUE    0x0000000000000000

#define FIRE_DLC_IMU_RDS_INTX_CSR_A_INT_A_INT_CLR_REG_ADDR       mpeval(0x0060b008 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_DLC_IMU_RDS_INTX_CSR_A_INT_A_INT_CLR_REG_WRITE_MASK  0x0000000000000000
#define FIRE_DLC_IMU_RDS_INTX_CSR_A_INT_A_INT_CLR_REG_POR_VALUE  0x0000000000000000

#define FIRE_DLC_IMU_RDS_INTX_CSR_A_INT_B_INT_CLR_REG_ADDR       mpeval(0x0060b010 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_DLC_IMU_RDS_INTX_CSR_A_INT_B_INT_CLR_REG_WRITE_MASK  0x0000000000000000
#define FIRE_DLC_IMU_RDS_INTX_CSR_A_INT_B_INT_CLR_REG_POR_VALUE  0x0000000000000000

#define FIRE_DLC_IMU_RDS_INTX_CSR_A_INT_C_INT_CLR_REG_ADDR       mpeval(0x0060b018 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_DLC_IMU_RDS_INTX_CSR_A_INT_C_INT_CLR_REG_WRITE_MASK  0x0000000000000000
#define FIRE_DLC_IMU_RDS_INTX_CSR_A_INT_C_INT_CLR_REG_POR_VALUE  0x0000000000000000

#define FIRE_DLC_IMU_RDS_INTX_CSR_A_INT_D_INT_CLR_REG_ADDR       mpeval(0x0060b020 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_DLC_IMU_RDS_INTX_CSR_A_INT_D_INT_CLR_REG_WRITE_MASK  0x0000000000000000
#define FIRE_DLC_IMU_RDS_INTX_CSR_A_INT_D_INT_CLR_REG_POR_VALUE  0x0000000000000000


!! Register definitions from :/verif/env/dmu/vera/csrtool/iss_a.csr_define.vri 1.1


#define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_20_ADDR         mpeval(0x006010a0 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_20_WRITE_MASK   0x80000000fe0003c0
#define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_20_POR_VALUE    0x0000000000000000

#define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_21_ADDR         mpeval(0x006010a8 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_21_WRITE_MASK   0x80000000fe0003c0
#define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_21_POR_VALUE    0x0000000000000000

#define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_22_ADDR         mpeval(0x006010b0 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_22_WRITE_MASK   0x80000000fe0003c0
#define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_22_POR_VALUE    0x0000000000000000

#define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_23_ADDR         mpeval(0x006010b8 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_23_WRITE_MASK   0x80000000fe0003c0
#define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_23_POR_VALUE    0x0000000000000000

#define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_24_ADDR         mpeval(0x006010c0 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_24_WRITE_MASK   0x80000000fe0003c0
#define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_24_POR_VALUE    0x0000000000000000

#define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_25_ADDR         mpeval(0x006010c8 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_25_WRITE_MASK   0x80000000fe0003c0
#define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_25_POR_VALUE    0x0000000000000000

#define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_26_ADDR         mpeval(0x006010d0 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_26_WRITE_MASK   0x80000000fe0003c0
#define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_26_POR_VALUE    0x0000000000000000

#define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_27_ADDR         mpeval(0x006010d8 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_27_WRITE_MASK   0x80000000fe0003c0
#define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_27_POR_VALUE    0x0000000000000000

#define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_28_ADDR         mpeval(0x006010e0 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_28_WRITE_MASK   0x80000000fe0003c0
#define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_28_POR_VALUE    0x0000000000000000

#define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_29_ADDR         mpeval(0x006010e8 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_29_WRITE_MASK   0x80000000fe0003c0
#define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_29_POR_VALUE    0x0000000000000000

#define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_30_ADDR         mpeval(0x006010f0 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_30_WRITE_MASK   0x80000000fe0003c0
#define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_30_POR_VALUE    0x0000000000000000

#define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_31_ADDR         mpeval(0x006010f8 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_31_WRITE_MASK   0x80000000fe0003c0
#define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_31_POR_VALUE    0x0000000000000000

#define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_32_ADDR         mpeval(0x00601100 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_32_WRITE_MASK   0x80000000fe0003c0
#define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_32_POR_VALUE    0x0000000000000000

#define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_33_ADDR         mpeval(0x00601108 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_33_WRITE_MASK   0x80000000fe0003c0
#define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_33_POR_VALUE    0x0000000000000000

#define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_34_ADDR         mpeval(0x00601110 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_34_WRITE_MASK   0x80000000fe0003c0
#define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_34_POR_VALUE    0x0000000000000000

#define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_35_ADDR         mpeval(0x00601118 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_35_WRITE_MASK   0x80000000fe0003c0
#define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_35_POR_VALUE    0x0000000000000000

#define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_36_ADDR         mpeval(0x00601120 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_36_WRITE_MASK   0x80000000fe0003c0
#define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_36_POR_VALUE    0x0000000000000000

#define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_37_ADDR         mpeval(0x00601128 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_37_WRITE_MASK   0x80000000fe0003c0
#define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_37_POR_VALUE    0x0000000000000000

#define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_38_ADDR         mpeval(0x00601130 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_38_WRITE_MASK   0x80000000fe0003c0
#define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_38_POR_VALUE    0x0000000000000000

#define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_39_ADDR         mpeval(0x00601138 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_39_WRITE_MASK   0x80000000fe0003c0
#define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_39_POR_VALUE    0x0000000000000000

#define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_40_ADDR         mpeval(0x00601140 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_40_WRITE_MASK   0x80000000fe0003c0
#define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_40_POR_VALUE    0x0000000000000000

#define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_41_ADDR         mpeval(0x00601148 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_41_WRITE_MASK   0x80000000fe0003c0
#define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_41_POR_VALUE    0x0000000000000000

#define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_42_ADDR         mpeval(0x00601150 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_42_WRITE_MASK   0x80000000fe0003c0
#define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_42_POR_VALUE    0x0000000000000000

#define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_43_ADDR         mpeval(0x00601158 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_43_WRITE_MASK   0x80000000fe0003c0
#define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_43_POR_VALUE    0x0000000000000000

#define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_44_ADDR         mpeval(0x00601160 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_44_WRITE_MASK   0x80000000fe0003c0
#define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_44_POR_VALUE    0x0000000000000000

#define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_45_ADDR         mpeval(0x00601168 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_45_WRITE_MASK   0x80000000fe0003c0
#define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_45_POR_VALUE    0x0000000000000000

#define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_46_ADDR         mpeval(0x00601170 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_46_WRITE_MASK   0x80000000fe0003c0
#define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_46_POR_VALUE    0x0000000000000000

#define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_47_ADDR         mpeval(0x00601178 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_47_WRITE_MASK   0x80000000fe0003c0
#define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_47_POR_VALUE    0x0000000000000000

#define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_48_ADDR         mpeval(0x00601180 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_48_WRITE_MASK   0x80000000fe0003c0
#define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_48_POR_VALUE    0x0000000000000000

#define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_49_ADDR         mpeval(0x00601188 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_49_WRITE_MASK   0x80000000fe0003c0
#define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_49_POR_VALUE    0x0000000000000000

#define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_50_ADDR         mpeval(0x00601190 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_50_WRITE_MASK   0x80000000fe0003c0
#define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_50_POR_VALUE    0x0000000000000000

#define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_51_ADDR         mpeval(0x00601198 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_51_WRITE_MASK   0x80000000fe0003c0
#define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_51_POR_VALUE    0x0000000000000000

#define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_52_ADDR         mpeval(0x006011a0 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_52_WRITE_MASK   0x80000000fe0003c0
#define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_52_POR_VALUE    0x0000000000000000

#define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_53_ADDR         mpeval(0x006011a8 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_53_WRITE_MASK   0x80000000fe0003c0
#define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_53_POR_VALUE    0x0000000000000000

#define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_54_ADDR         mpeval(0x006011b0 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_54_WRITE_MASK   0x80000000fe0003c0
#define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_54_POR_VALUE    0x0000000000000000

#define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_55_ADDR         mpeval(0x006011b8 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_55_WRITE_MASK   0x80000000fe0003c0
#define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_55_POR_VALUE    0x0000000000000000

#define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_56_ADDR         mpeval(0x006011c0 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_56_WRITE_MASK   0x80000000fe0003c0
#define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_56_POR_VALUE    0x0000000000000000

#define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_57_ADDR         mpeval(0x006011c8 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_57_WRITE_MASK   0x80000000fe0003c0
#define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_57_POR_VALUE    0x0000000000000000

#define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_58_ADDR         mpeval(0x006011d0 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_58_WRITE_MASK   0x80000000fe0003c0
#define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_58_POR_VALUE    0x0000000000000000

#define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_59_ADDR         mpeval(0x006011d8 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_59_WRITE_MASK   0x80000000fe0003c0
#define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_59_POR_VALUE    0x0000000000000000

#define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_62_ADDR         mpeval(0x006011f0 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_62_WRITE_MASK   0x80000000fe0003c0
#define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_62_POR_VALUE    0x0000000000000000

#define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_63_ADDR         mpeval(0x006011f8 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_63_WRITE_MASK   0x80000000fe0003c0
#define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_63_POR_VALUE    0x0000000000000000

#define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_20_ADDR               mpeval(0x006014a0 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_20_WRITE_MASK         0x0000000000000003
#define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_20_POR_VALUE          0x0000000000000000

#define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_21_ADDR               mpeval(0x006014a8 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_21_WRITE_MASK         0x0000000000000003
#define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_21_POR_VALUE          0x0000000000000000

#define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_22_ADDR               mpeval(0x006014b0 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_22_WRITE_MASK         0x0000000000000003
#define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_22_POR_VALUE          0x0000000000000000

#define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_23_ADDR               mpeval(0x006014b8 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_23_WRITE_MASK         0x0000000000000003
#define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_23_POR_VALUE          0x0000000000000000

#define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_24_ADDR               mpeval(0x006014c0 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_24_WRITE_MASK         0x0000000000000003
#define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_24_POR_VALUE          0x0000000000000000

#define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_25_ADDR               mpeval(0x006014c8 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_25_WRITE_MASK         0x0000000000000003
#define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_25_POR_VALUE          0x0000000000000000

#define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_26_ADDR               mpeval(0x006014d0 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_26_WRITE_MASK         0x0000000000000003
#define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_26_POR_VALUE          0x0000000000000000

#define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_27_ADDR               mpeval(0x006014d8 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_27_WRITE_MASK         0x0000000000000003
#define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_27_POR_VALUE          0x0000000000000000

#define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_28_ADDR               mpeval(0x006014e0 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_28_WRITE_MASK         0x0000000000000003
#define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_28_POR_VALUE          0x0000000000000000

#define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_29_ADDR               mpeval(0x006014e8 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_29_WRITE_MASK         0x0000000000000003
#define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_29_POR_VALUE          0x0000000000000000

#define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_30_ADDR               mpeval(0x006014f0 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_30_WRITE_MASK         0x0000000000000003
#define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_30_POR_VALUE          0x0000000000000000

#define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_31_ADDR               mpeval(0x006014f8 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_31_WRITE_MASK         0x0000000000000003
#define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_31_POR_VALUE          0x0000000000000000

#define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_32_ADDR               mpeval(0x00601500 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_32_WRITE_MASK         0x0000000000000003
#define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_32_POR_VALUE          0x0000000000000000

#define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_33_ADDR               mpeval(0x00601508 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_33_WRITE_MASK         0x0000000000000003
#define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_33_POR_VALUE          0x0000000000000000

#define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_34_ADDR               mpeval(0x00601510 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_34_WRITE_MASK         0x0000000000000003
#define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_34_POR_VALUE          0x0000000000000000

#define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_35_ADDR               mpeval(0x00601518 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_35_WRITE_MASK         0x0000000000000003
#define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_35_POR_VALUE          0x0000000000000000

#define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_36_ADDR               mpeval(0x00601520 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_36_WRITE_MASK         0x0000000000000003
#define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_36_POR_VALUE          0x0000000000000000

#define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_37_ADDR               mpeval(0x00601528 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_37_WRITE_MASK         0x0000000000000003
#define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_37_POR_VALUE          0x0000000000000000

#define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_38_ADDR               mpeval(0x00601530 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_38_WRITE_MASK         0x0000000000000003
#define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_38_POR_VALUE          0x0000000000000000

#define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_39_ADDR               mpeval(0x00601538 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_39_WRITE_MASK         0x0000000000000003
#define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_39_POR_VALUE          0x0000000000000000

#define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_40_ADDR               mpeval(0x00601540 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_40_WRITE_MASK         0x0000000000000003
#define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_40_POR_VALUE          0x0000000000000000

#define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_41_ADDR               mpeval(0x00601548 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_41_WRITE_MASK         0x0000000000000003
#define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_41_POR_VALUE          0x0000000000000000

#define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_42_ADDR               mpeval(0x00601550 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_42_WRITE_MASK         0x0000000000000003
#define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_42_POR_VALUE          0x0000000000000000

#define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_43_ADDR               mpeval(0x00601558 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_43_WRITE_MASK         0x0000000000000003
#define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_43_POR_VALUE          0x0000000000000000

#define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_44_ADDR               mpeval(0x00601560 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_44_WRITE_MASK         0x0000000000000003
#define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_44_POR_VALUE          0x0000000000000000

#define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_45_ADDR               mpeval(0x00601568 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_45_WRITE_MASK         0x0000000000000003
#define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_45_POR_VALUE          0x0000000000000000

#define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_46_ADDR               mpeval(0x00601570 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_46_WRITE_MASK         0x0000000000000003
#define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_46_POR_VALUE          0x0000000000000000

#define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_47_ADDR               mpeval(0x00601578 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_47_WRITE_MASK         0x0000000000000003
#define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_47_POR_VALUE          0x0000000000000000

#define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_48_ADDR               mpeval(0x00601580 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_48_WRITE_MASK         0x0000000000000003
#define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_48_POR_VALUE          0x0000000000000000

#define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_49_ADDR               mpeval(0x00601588 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_49_WRITE_MASK         0x0000000000000003
#define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_49_POR_VALUE          0x0000000000000000

#define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_50_ADDR               mpeval(0x00601590 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_50_WRITE_MASK         0x0000000000000003
#define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_50_POR_VALUE          0x0000000000000000

#define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_51_ADDR               mpeval(0x00601598 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_51_WRITE_MASK         0x0000000000000003
#define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_51_POR_VALUE          0x0000000000000000

#define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_52_ADDR               mpeval(0x006015a0 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_52_WRITE_MASK         0x0000000000000003
#define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_52_POR_VALUE          0x0000000000000000

#define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_53_ADDR               mpeval(0x006015a8 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_53_WRITE_MASK         0x0000000000000003
#define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_53_POR_VALUE          0x0000000000000000

#define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_54_ADDR               mpeval(0x006015b0 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_54_WRITE_MASK         0x0000000000000003
#define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_54_POR_VALUE          0x0000000000000000

#define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_55_ADDR               mpeval(0x006015b8 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_55_WRITE_MASK         0x0000000000000003
#define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_55_POR_VALUE          0x0000000000000000

#define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_56_ADDR               mpeval(0x006015c0 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_56_WRITE_MASK         0x0000000000000003
#define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_56_POR_VALUE          0x0000000000000000

#define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_57_ADDR               mpeval(0x006015c8 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_57_WRITE_MASK         0x0000000000000003
#define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_57_POR_VALUE          0x0000000000000000

#define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_58_ADDR               mpeval(0x006015d0 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_58_WRITE_MASK         0x0000000000000003
#define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_58_POR_VALUE          0x0000000000000000

#define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_59_ADDR               mpeval(0x006015d8 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_59_WRITE_MASK         0x0000000000000003
#define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_59_POR_VALUE          0x0000000000000000

#define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_62_ADDR               mpeval(0x006015f0 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_62_WRITE_MASK         0x0000000000000003
#define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_62_POR_VALUE          0x0000000000000000

#define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_63_ADDR               mpeval(0x006015f8 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_63_WRITE_MASK         0x0000000000000003
#define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_63_POR_VALUE          0x0000000000000000

#define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_RETRY_TIMER_ADDR        mpeval(0x00601a00 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_RETRY_TIMER_WRITE_MASK  0x0000000001ffffff
#define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_RETRY_TIMER_POR_VALUE   0x0000000000000000

#define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_STATE_STATUS_1_ADDR     mpeval(0x00601a10 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_STATE_STATUS_1_WRITE_MASK  0x0000000000000000
#define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_STATE_STATUS_1_POR_VALUE  0x0000000000000000

#define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_STATE_STATUS_2_ADDR     mpeval(0x00601a18 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_STATE_STATUS_2_WRITE_MASK  0x0000000000000000
#define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_STATE_STATUS_2_POR_VALUE  0x0000000000000000


!! Register definitions from :/verif/env/dmu/vera/csrtool/mess_a.csr_define.vri 1.1


#define FIRE_DLC_IMU_RDS_MESS_CSR_A_ERR_COR_MAPPING_ADDR         mpeval(0x00630000 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_DLC_IMU_RDS_MESS_CSR_A_ERR_COR_MAPPING_WRITE_MASK   0x800000000000003f
#define FIRE_DLC_IMU_RDS_MESS_CSR_A_ERR_COR_MAPPING_POR_VALUE    0x0000000000000000

#define FIRE_DLC_IMU_RDS_MESS_CSR_A_ERR_NONFATAL_MAPPING_ADDR    mpeval(0x00630008 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_DLC_IMU_RDS_MESS_CSR_A_ERR_NONFATAL_MAPPING_WRITE_MASK  0x800000000000003f
#define FIRE_DLC_IMU_RDS_MESS_CSR_A_ERR_NONFATAL_MAPPING_POR_VALUE  0x0000000000000000

#define FIRE_DLC_IMU_RDS_MESS_CSR_A_ERR_FATAL_MAPPING_ADDR       mpeval(0x00630010 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_DLC_IMU_RDS_MESS_CSR_A_ERR_FATAL_MAPPING_WRITE_MASK  0x800000000000003f
#define FIRE_DLC_IMU_RDS_MESS_CSR_A_ERR_FATAL_MAPPING_POR_VALUE  0x0000000000000000

#define FIRE_DLC_IMU_RDS_MESS_CSR_A_PM_PME_MAPPING_ADDR          mpeval(0x00630018 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_DLC_IMU_RDS_MESS_CSR_A_PM_PME_MAPPING_WRITE_MASK    0x800000000000003f
#define FIRE_DLC_IMU_RDS_MESS_CSR_A_PM_PME_MAPPING_POR_VALUE     0x0000000000000000

#define FIRE_DLC_IMU_RDS_MESS_CSR_A_PME_TO_ACK_MAPPING_ADDR      mpeval(0x00630020 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_DLC_IMU_RDS_MESS_CSR_A_PME_TO_ACK_MAPPING_WRITE_MASK  0x800000000000003f
#define FIRE_DLC_IMU_RDS_MESS_CSR_A_PME_TO_ACK_MAPPING_POR_VALUE  0x0000000000000000


!! Register definitions from :/verif/env/dmu/vera/csrtool/msi_a.csr_define.vri 1.1


#define FIRE_DLC_IMU_RDS_MSI_CSR_A_MSI_MAPPING_ADDR              mpeval(0x00620000 + N2_DMU_PEU_BASE_ADDR)
!! This register maps to a ram with a depth of: 256
#define FIRE_DLC_IMU_RDS_MSI_CSR_A_MSI_MAPPING_WRITE_MASK        0x800000000000003f
#define FIRE_DLC_IMU_RDS_MSI_CSR_A_MSI_MAPPING_POR_VALUE         0x0000000000000000

#define FIRE_DLC_IMU_RDS_MSI_CSR_A_MSI_CLEAR_REG_RW1C_ALIAS_ADDR  mpeval(0x00628000 + N2_DMU_PEU_BASE_ADDR)
!! This register maps to a ram with a depth of: 256
#define FIRE_DLC_IMU_RDS_MSI_CSR_A_MSI_CLEAR_REG_RW1C_ALIAS_WRITE_MASK  0x0000000000000000
#define FIRE_DLC_IMU_RDS_MSI_CSR_A_MSI_CLEAR_REG_RW1C_ALIAS_POR_VALUE  0x0000000000000000

#define FIRE_DLC_IMU_RDS_MSI_CSR_A_MSI_CLEAR_REG_RW1S_ALIAS_ADDR  mpeval(0x00628800 + N2_DMU_PEU_BASE_ADDR)
!! This register maps to a ram with a depth of: 256
#define FIRE_DLC_IMU_RDS_MSI_CSR_A_MSI_CLEAR_REG_RW1S_ALIAS_WRITE_MASK  0x4000000000000000
#define FIRE_DLC_IMU_RDS_MSI_CSR_A_MSI_CLEAR_REG_RW1S_ALIAS_POR_VALUE  0x0000000000000000

#define FIRE_DLC_IMU_RDS_MSI_CSR_A_INT_MONDO_DATA_0_REG_ADDR     mpeval(0x0062c000 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_DLC_IMU_RDS_MSI_CSR_A_INT_MONDO_DATA_0_REG_WRITE_MASK  0xffffffffffffffc0
#define FIRE_DLC_IMU_RDS_MSI_CSR_A_INT_MONDO_DATA_0_REG_POR_VALUE  0x0000000000000000

#define FIRE_DLC_IMU_RDS_MSI_CSR_A_INT_MONDO_DATA_1_REG_ADDR     mpeval(0x0062c008 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_DLC_IMU_RDS_MSI_CSR_A_INT_MONDO_DATA_1_REG_WRITE_MASK  0xffffffffffffffff
#define FIRE_DLC_IMU_RDS_MSI_CSR_A_INT_MONDO_DATA_1_REG_POR_VALUE  0x0000000000000000


!! Register definitions from :/verif/env/dmu/vera/csrtool/psb_a.csr_define.vri 1.2


#define FIRE_DLC_PSB_CSR_A_PSB_DMA_ADDR                          mpeval(0x00660000 + N2_DMU_PEU_BASE_ADDR)
!! This register maps to a ram with a depth of: 32
#define FIRE_DLC_PSB_CSR_A_PSB_DMA_WRITE_MASK                    0x0000000000000000
#define FIRE_DLC_PSB_CSR_A_PSB_DMA_POR_VALUE                     0x0000000000000000

#define FIRE_DLC_PSB_CSR_A_PSB_PIO_ADDR                          mpeval(0x00664000 + N2_DMU_PEU_BASE_ADDR)
!! This register maps to a ram with a depth of: 16
#define FIRE_DLC_PSB_CSR_A_PSB_PIO_WRITE_MASK                    0x0000000000000000
#define FIRE_DLC_PSB_CSR_A_PSB_PIO_POR_VALUE                     0x0000000000000000


!! Register definitions from :/verif/env/dmu/vera/csrtool/tsb_a.csr_define.vri 1.2


#define FIRE_DLC_TSB_CSR_A_TSB_DMA_ADDR                          mpeval(0x00670000 + N2_DMU_PEU_BASE_ADDR)
!! This register maps to a ram with a depth of: 32
#define FIRE_DLC_TSB_CSR_A_TSB_DMA_WRITE_MASK                    0x0000000000000000
#define FIRE_DLC_TSB_CSR_A_TSB_DMA_POR_VALUE                     0x0000000000000000

#define FIRE_DLC_TSB_CSR_A_TSB_STS_ADDR                          mpeval(0x00670100 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_DLC_TSB_CSR_A_TSB_STS_WRITE_MASK                    0x0000000000000000
#define FIRE_DLC_TSB_CSR_A_TSB_STS_POR_VALUE                     0x0000000000000001


!! Register definitions from :/verif/env/ilu_peu/vera/csrtool/cib_a.csr_define.vri 1.8


#define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_EN_ADDR                   mpeval(0x00651000 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_EN_WRITE_MASK             0x00000000000000f0
#define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_EN_POR_VALUE              0x00000000000000f0

#define FIRE_DLC_ILU_CIB_CSR_A_ILU_INT_EN_ADDR                   mpeval(0x00651008 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_DLC_ILU_CIB_CSR_A_ILU_INT_EN_WRITE_MASK             0x000000f0000000f0
#define FIRE_DLC_ILU_CIB_CSR_A_ILU_INT_EN_POR_VALUE              0x0000000000000000

#define FIRE_DLC_ILU_CIB_CSR_A_ILU_EN_ERR_ADDR                   mpeval(0x00651010 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_DLC_ILU_CIB_CSR_A_ILU_EN_ERR_WRITE_MASK             0x0000000000000000
#define FIRE_DLC_ILU_CIB_CSR_A_ILU_EN_ERR_POR_VALUE              0x0000000000000000

#define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1C_ALIAS_ADDR       mpeval(0x00651018 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1C_ALIAS_WRITE_MASK  0x0000000000000000
#define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1C_ALIAS_POR_VALUE  0x0000000000000000

#define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_ADDR       mpeval(0x00651020 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_WRITE_MASK  0x000000f0000000f0
#define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_POR_VALUE  0x0000000000000000

#define FIRE_DLC_ILU_CIB_CSR_A_PEC_INT_EN_ADDR                   mpeval(0x00651800 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_DLC_ILU_CIB_CSR_A_PEC_INT_EN_WRITE_MASK             0x800000000000000f
#define FIRE_DLC_ILU_CIB_CSR_A_PEC_INT_EN_POR_VALUE              0x0000000000000000

#define FIRE_DLC_ILU_CIB_CSR_A_PEC_EN_ERR_ADDR                   mpeval(0x00651808 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_DLC_ILU_CIB_CSR_A_PEC_EN_ERR_WRITE_MASK             0x0000000000000000
#define FIRE_DLC_ILU_CIB_CSR_A_PEC_EN_ERR_POR_VALUE              0x0000000000000000

#define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ADDR                  mpeval(0x00652000 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_WRITE_MASK            0x00000003ffffff3c
#define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_POR_VALUE             0x00000003ffff0000


!! Register definitions from :/verif/env/ilu_peu/vera/csrtool/tlr_a.csr_define.vri 1.16


#define FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_CTL_ADDR                  mpeval(0x00680000 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_CTL_WRITE_MASK            0x00000000ff17ffff
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_CTL_POR_VALUE             0x0000000000000101

#define FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_STS_ADDR                  mpeval(0x00680008 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_STS_WRITE_MASK            0x0000000000000100
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_STS_POR_VALUE             0x0000000000000001

#define FIRE_PLC_TLU_CTB_TLR_CSR_A_TRN_OFF_ADDR                  mpeval(0x00680010 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_TRN_OFF_WRITE_MASK            0x0000000000000001
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_TRN_OFF_POR_VALUE             0x0000000000000000

#define FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_ICI_ADDR                  mpeval(0x00680018 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_ICI_WRITE_MASK            0x000000ff000fffff
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_ICI_POR_VALUE             0x00000010000200c0

#define FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_DIAG_ADDR                 mpeval(0x00680100 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_DIAG_WRITE_MASK           0x0f00ffffffffff03
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_DIAG_POR_VALUE            0x0000000000000000

#define FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_ECC_ADDR                  mpeval(0x00680200 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_ECC_WRITE_MASK            0x0000000000000000
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_ECC_POR_VALUE             0x0000000000000000

#define FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_ECL_ADDR                  mpeval(0x00680208 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_ECL_WRITE_MASK            0x0000000000000000
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_ECL_POR_VALUE             0x0000000000000000

#define FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_ERB_ADDR                  mpeval(0x00680210 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_ERB_WRITE_MASK            0x0000000000000000
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_ERB_POR_VALUE             0x0000000000001000

#define FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_ICA_ADDR                  mpeval(0x00680218 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_ICA_WRITE_MASK            0x0000000000000000
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_ICA_POR_VALUE             0x00000010000200c0

#define FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_ICR_ADDR                  mpeval(0x00680220 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_ICR_WRITE_MASK            0x0000000000000000
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_ICR_POR_VALUE             0x0000000000000000

#define FIRE_PLC_TLU_CTB_TLR_CSR_A_OE_LOG_ADDR                   mpeval(0x00681000 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_OE_LOG_WRITE_MASK             0x0000000000ffffff
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_OE_LOG_POR_VALUE              0x0000000000ffffff

#define FIRE_PLC_TLU_CTB_TLR_CSR_A_OE_INT_EN_ADDR                mpeval(0x00681008 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_OE_INT_EN_WRITE_MASK          0x00ffffff00ffffff
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_OE_INT_EN_POR_VALUE           0x0000000000000000

#define FIRE_PLC_TLU_CTB_TLR_CSR_A_OE_EN_ERR_ADDR                mpeval(0x00681010 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_OE_EN_ERR_WRITE_MASK          0x0000000000000000
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_OE_EN_ERR_POR_VALUE           0x0000000000000000

#define FIRE_PLC_TLU_CTB_TLR_CSR_A_OE_ERR_RW1C_ALIAS_ADDR        mpeval(0x00681018 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_OE_ERR_RW1C_ALIAS_WRITE_MASK  0x0000000000000000
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_OE_ERR_RW1C_ALIAS_POR_VALUE   0x0000000000000000

#define FIRE_PLC_TLU_CTB_TLR_CSR_A_OE_ERR_RW1S_ALIAS_ADDR        mpeval(0x00681020 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_OE_ERR_RW1S_ALIAS_WRITE_MASK  0x00ffffff00ffffff
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_OE_ERR_RW1S_ALIAS_POR_VALUE   0x0000000000000000

#define FIRE_PLC_TLU_CTB_TLR_CSR_A_ROE_HDR1_ADDR                 mpeval(0x00681028 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_ROE_HDR1_WRITE_MASK           0xffffffffffffffff
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_ROE_HDR1_POR_VALUE            0x0000000000000000

#define FIRE_PLC_TLU_CTB_TLR_CSR_A_ROE_HDR2_ADDR                 mpeval(0x00681030 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_ROE_HDR2_WRITE_MASK           0xffffffffffffffff
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_ROE_HDR2_POR_VALUE            0x0000000000000000

#define FIRE_PLC_TLU_CTB_TLR_CSR_A_TOE_HDR1_ADDR                 mpeval(0x00681038 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_TOE_HDR1_WRITE_MASK           0xffffffffffffffff
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_TOE_HDR1_POR_VALUE            0x0000000000000000

#define FIRE_PLC_TLU_CTB_TLR_CSR_A_TOE_HDR2_ADDR                 mpeval(0x00681040 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_TOE_HDR2_WRITE_MASK           0xffffffffffffffff
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_TOE_HDR2_POR_VALUE            0x0000000000000000

#define FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_PRFC_ADDR                 mpeval(0x00682000 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_PRFC_WRITE_MASK           0x000000000003ffff
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_PRFC_POR_VALUE            0x0000000000000000

#define FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_PRF0_ADDR                 mpeval(0x00682008 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_PRF0_WRITE_MASK           0xffffffffffffffff
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_PRF0_POR_VALUE            0x0000000000000000

#define FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_PRF1_ADDR                 mpeval(0x00682010 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_PRF1_WRITE_MASK           0xffffffffffffffff
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_PRF1_POR_VALUE            0x0000000000000000

#define FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_PRF2_ADDR                 mpeval(0x00682018 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_PRF2_WRITE_MASK           0x00000000ffffffff
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_PRF2_POR_VALUE            0x0000000000000000

#define FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_DBG_SEL_A_ADDR            mpeval(0x00683000 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_DBG_SEL_A_WRITE_MASK      0x00000000000001ff
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_DBG_SEL_A_POR_VALUE       0x0000000000000000

#define FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_DBG_SEL_B_ADDR            mpeval(0x00683008 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_DBG_SEL_B_WRITE_MASK      0x00000000000001ff
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_DBG_SEL_B_POR_VALUE       0x0000000000000000

#define FIRE_PLC_TLU_CTB_TLR_CSR_A_DEV_CAP_ADDR                  mpeval(0x00690000 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_DEV_CAP_WRITE_MASK            0x0000000000000000
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_DEV_CAP_POR_VALUE             0x0000000000000002

#define FIRE_PLC_TLU_CTB_TLR_CSR_A_DEV_CTL_ADDR                  mpeval(0x00690008 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_DEV_CTL_WRITE_MASK            0x00000000000000e0
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_DEV_CTL_POR_VALUE             0x0000000000000000

#define FIRE_PLC_TLU_CTB_TLR_CSR_A_DEV_STS_ADDR                  mpeval(0x00690010 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_DEV_STS_WRITE_MASK            0x0000000000000000
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_DEV_STS_POR_VALUE             0x0000000000000000

#define FIRE_PLC_TLU_CTB_TLR_CSR_A_LNK_CAP_ADDR                  mpeval(0x00690018 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_LNK_CAP_WRITE_MASK            0x0000000000000000
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_LNK_CAP_POR_VALUE             0x0000000000014c81

#define FIRE_PLC_TLU_CTB_TLR_CSR_A_LNK_CTL_ADDR                  mpeval(0x00690020 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_LNK_CTL_WRITE_MASK            0x00000000000000f3
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_LNK_CTL_POR_VALUE             0x0000000000000000

#define FIRE_PLC_TLU_CTB_TLR_CSR_A_LNK_STS_ADDR                  mpeval(0x00690028 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_LNK_STS_WRITE_MASK            0x0000000000000000
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_LNK_STS_POR_VALUE             0x0000000000000000

#define FIRE_PLC_TLU_CTB_TLR_CSR_A_SLT_CAP_ADDR                  mpeval(0x00690030 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_SLT_CAP_WRITE_MASK            0x000000000001ff80
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_SLT_CAP_POR_VALUE             0x0000000000000000

#define FIRE_PLC_TLU_CTB_TLR_CSR_A_UE_LOG_ADDR                   mpeval(0x00691000 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_UE_LOG_WRITE_MASK             0x00000000001fffff
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_UE_LOG_POR_VALUE              0x000000000017f011

#define FIRE_PLC_TLU_CTB_TLR_CSR_A_UE_INT_EN_ADDR                mpeval(0x00691008 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_UE_INT_EN_WRITE_MASK          0x001fffff001fffff
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_UE_INT_EN_POR_VALUE           0x0000000000000000

#define FIRE_PLC_TLU_CTB_TLR_CSR_A_UE_EN_ERR_ADDR                mpeval(0x00691010 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_UE_EN_ERR_WRITE_MASK          0x0000000000000000
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_UE_EN_ERR_POR_VALUE           0x0000000000000000

#define FIRE_PLC_TLU_CTB_TLR_CSR_A_UE_ERR_RW1C_ALIAS_ADDR        mpeval(0x00691018 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_UE_ERR_RW1C_ALIAS_WRITE_MASK  0x0000000000000000
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_UE_ERR_RW1C_ALIAS_POR_VALUE   0x0000000000000000

#define FIRE_PLC_TLU_CTB_TLR_CSR_A_UE_ERR_RW1S_ALIAS_ADDR        mpeval(0x00691020 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_UE_ERR_RW1S_ALIAS_WRITE_MASK  0x0017f0110017f011
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_UE_ERR_RW1S_ALIAS_POR_VALUE   0x0000000000000000

#define FIRE_PLC_TLU_CTB_TLR_CSR_A_RUE_HDR1_ADDR                 mpeval(0x00691028 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_RUE_HDR1_WRITE_MASK           0xffffffffffffffff
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_RUE_HDR1_POR_VALUE            0x0000000000000000

#define FIRE_PLC_TLU_CTB_TLR_CSR_A_RUE_HDR2_ADDR                 mpeval(0x00691030 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_RUE_HDR2_WRITE_MASK           0xffffffffffffffff
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_RUE_HDR2_POR_VALUE            0x0000000000000000

#define FIRE_PLC_TLU_CTB_TLR_CSR_A_TUE_HDR1_ADDR                 mpeval(0x00691038 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_TUE_HDR1_WRITE_MASK           0xffffffffffffffff
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_TUE_HDR1_POR_VALUE            0x0000000000000000

#define FIRE_PLC_TLU_CTB_TLR_CSR_A_TUE_HDR2_ADDR                 mpeval(0x00691040 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_TUE_HDR2_WRITE_MASK           0xffffffffffffffff
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_TUE_HDR2_POR_VALUE            0x0000000000000000

#define FIRE_PLC_TLU_CTB_TLR_CSR_A_CE_LOG_ADDR                   mpeval(0x006a1000 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_CE_LOG_WRITE_MASK             0x0000000000001fff
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_CE_LOG_POR_VALUE              0x00000000000011c1

#define FIRE_PLC_TLU_CTB_TLR_CSR_A_CE_INT_EN_ADDR                mpeval(0x006a1008 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_CE_INT_EN_WRITE_MASK          0x00001fff00001fff
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_CE_INT_EN_POR_VALUE           0x0000000000000000

#define FIRE_PLC_TLU_CTB_TLR_CSR_A_CE_EN_ERR_ADDR                mpeval(0x006a1010 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_CE_EN_ERR_WRITE_MASK          0x0000000000000000
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_CE_EN_ERR_POR_VALUE           0x0000000000000000

#define FIRE_PLC_TLU_CTB_TLR_CSR_A_CE_ERR_RW1C_ALIAS_ADDR        mpeval(0x006a1018 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_CE_ERR_RW1C_ALIAS_WRITE_MASK  0x0000000000000000
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_CE_ERR_RW1C_ALIAS_POR_VALUE   0x0000000000000000

#define FIRE_PLC_TLU_CTB_TLR_CSR_A_CE_ERR_RW1S_ALIAS_ADDR        mpeval(0x006a1020 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_CE_ERR_RW1S_ALIAS_WRITE_MASK  0x000011c1000011c1
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_CE_ERR_RW1S_ALIAS_POR_VALUE   0x0000000000000000

#define FIRE_PLC_TLU_CTB_TLR_CSR_A_PEU_DLPL_SERDES_REV_ADDR      mpeval(0x006e2000 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_PEU_DLPL_SERDES_REV_WRITE_MASK  0x0000000000000000
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_PEU_DLPL_SERDES_REV_POR_VALUE  0x0000000000000000

#define FIRE_PLC_TLU_CTB_TLR_CSR_A_ACKNAK_THRESH_ADDR            mpeval(0x006e2008 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_ACKNAK_THRESH_WRITE_MASK      0x000000000000ffff
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_ACKNAK_THRESH_POR_VALUE       0x0000000000000043

#define FIRE_PLC_TLU_CTB_TLR_CSR_A_ACKNAK_TIMER_ADDR             mpeval(0x006e2010 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_ACKNAK_TIMER_WRITE_MASK       0x0000000000000000
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_ACKNAK_TIMER_POR_VALUE        0x0000000000000000

#define FIRE_PLC_TLU_CTB_TLR_CSR_A_REPLAY_TIM_THRESH_ADDR        mpeval(0x006e2018 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_REPLAY_TIM_THRESH_WRITE_MASK  0x000000000000ffff
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_REPLAY_TIM_THRESH_POR_VALUE   0x00000000000000fc

#define FIRE_PLC_TLU_CTB_TLR_CSR_A_REPLAY_TIMER_ADDR             mpeval(0x006e2020 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_REPLAY_TIMER_WRITE_MASK       0x0000000000000000
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_REPLAY_TIMER_POR_VALUE        0x0000000000000000

#define FIRE_PLC_TLU_CTB_TLR_CSR_A_VEN_DLLP_MSG_ADDR             mpeval(0x006e2040 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_VEN_DLLP_MSG_WRITE_MASK       0x00000000ffffffff
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_VEN_DLLP_MSG_POR_VALUE        0x0000000000000000

#define FIRE_PLC_TLU_CTB_TLR_CSR_A_FORCE_LTSSM_ADDR              mpeval(0x006e2050 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_FORCE_LTSSM_WRITE_MASK        0x000000000000011f
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_FORCE_LTSSM_POR_VALUE         0x0000000000000000

#define FIRE_PLC_TLU_CTB_TLR_CSR_A_LINK_CFG_ADDR                 mpeval(0x006e2058 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_LINK_CFG_WRITE_MASK           0x000000000000ff1f
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_LINK_CFG_POR_VALUE            0x0000000000000101

#define FIRE_PLC_TLU_CTB_TLR_CSR_A_LINK_CTL_ADDR                 mpeval(0x006e2060 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_LINK_CTL_WRITE_MASK           0x00000000ffff3f1e
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_LINK_CTL_POR_VALUE            0x00000000001b0800

#define FIRE_PLC_TLU_CTB_TLR_CSR_A_LANE_SKEW_ADDR                mpeval(0x006e2068 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_LANE_SKEW_WRITE_MASK          0x0000000003ffffff
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_LANE_SKEW_POR_VALUE           0x0000000000000000

#define FIRE_PLC_TLU_CTB_TLR_CSR_A_SYMBOL_NUM_ADDR               mpeval(0x006e2070 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_SYMBOL_NUM_WRITE_MASK         0x00000000000077ff
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_SYMBOL_NUM_POR_VALUE          0x00000000000033aa

#define FIRE_PLC_TLU_CTB_TLR_CSR_A_SYMBOL_TIMER_ADDR             mpeval(0x006e2078 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_SYMBOL_TIMER_WRITE_MASK       0x00000000000007ff
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_SYMBOL_TIMER_POR_VALUE        0x0000000000000500

#define FIRE_PLC_TLU_CTB_TLR_CSR_A_CORE_STATUS_ADDR              mpeval(0x006e2100 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_CORE_STATUS_WRITE_MASK        0x0000000000000000
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_CORE_STATUS_POR_VALUE         0x0000000000000000

#define FIRE_PLC_TLU_CTB_TLR_CSR_A_EVENT_ERR_LOG_EN_ADDR         mpeval(0x006e2108 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_EVENT_ERR_LOG_EN_WRITE_MASK   0x00000000ff03ffff
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_EVENT_ERR_LOG_EN_POR_VALUE    0x000000000f03ffff

#define FIRE_PLC_TLU_CTB_TLR_CSR_A_EVENT_ERR_INT_EN_ADDR         mpeval(0x006e2110 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_EVENT_ERR_INT_EN_WRITE_MASK   0x00000000ff03ffff
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_EVENT_ERR_INT_EN_POR_VALUE    0x0000000000000000

#define FIRE_PLC_TLU_CTB_TLR_CSR_A_EVENT_ERR_INT_STS_ADDR        mpeval(0x006e2118 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_EVENT_ERR_INT_STS_WRITE_MASK  0x0000000000000000
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_EVENT_ERR_INT_STS_POR_VALUE   0x0000000000000000

#define FIRE_PLC_TLU_CTB_TLR_CSR_A_EVENT_ERR_STS_CLR_RW1C_ALIAS_ADDR  mpeval(0x006e2120 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_EVENT_ERR_STS_CLR_RW1C_ALIAS_WRITE_MASK  0x0000000000000000
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_EVENT_ERR_STS_CLR_RW1C_ALIAS_POR_VALUE  0x0000000000000000

#define FIRE_PLC_TLU_CTB_TLR_CSR_A_EVENT_ERR_STS_CLR_RW1S_ALIAS_ADDR  mpeval(0x006e2128 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_EVENT_ERR_STS_CLR_RW1S_ALIAS_WRITE_MASK  0x00000000ff03ffff
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_EVENT_ERR_STS_CLR_RW1S_ALIAS_POR_VALUE  0x0000000000000000

#define FIRE_PLC_TLU_CTB_TLR_CSR_A_LNK_BIT_ERR_CNT_1_ADDR        mpeval(0x006e2130 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_LNK_BIT_ERR_CNT_1_WRITE_MASK  0x8000000000000000
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_LNK_BIT_ERR_CNT_1_POR_VALUE   0x0000000000000000

#define FIRE_PLC_TLU_CTB_TLR_CSR_A_LNK_BIT_ERR_CNT_2_ADDR        mpeval(0x006e2138 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_LNK_BIT_ERR_CNT_2_WRITE_MASK  0x0000000000000000
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_LNK_BIT_ERR_CNT_2_POR_VALUE   0x0000000000000000

#define FIRE_PLC_TLU_CTB_TLR_CSR_A_SERDES_PLL_ADDR               mpeval(0x006e2200 + N2_DMU_PEU_BASE_ADDR)
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_SERDES_PLL_WRITE_MASK         0x00000000000000ff
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_SERDES_PLL_POR_VALUE          0x0000000000000001

#define FIRE_PLC_TLU_CTB_TLR_CSR_A_SERDES_RECEIVER_LANE_CTL_ADDR  mpeval(0x006e2300 + N2_DMU_PEU_BASE_ADDR)
!! This register maps to a ram with a depth of: 8
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_SERDES_RECEIVER_LANE_CTL_WRITE_MASK  0x000000000000ffff
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_SERDES_RECEIVER_LANE_CTL_POR_VALUE  0x0000000000000552

#define FIRE_PLC_TLU_CTB_TLR_CSR_A_SERDES_RECEIVER_LANE_STATUS_ADDR  mpeval(0x006e2380 + N2_DMU_PEU_BASE_ADDR)
!! This register maps to a ram with a depth of: 8
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_SERDES_RECEIVER_LANE_STATUS_WRITE_MASK  0x0000000000000000
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_SERDES_RECEIVER_LANE_STATUS_POR_VALUE  0x0000000000000000

#define FIRE_PLC_TLU_CTB_TLR_CSR_A_SERDES_XMITTER_LANE_CTL_ADDR  mpeval(0x006e2400 + N2_DMU_PEU_BASE_ADDR)
!! This register maps to a ram with a depth of: 8
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_SERDES_XMITTER_LANE_CTL_WRITE_MASK  0x00000000000007ff
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_SERDES_XMITTER_LANE_CTL_POR_VALUE  0x00000000000001ec

#define FIRE_PLC_TLU_CTB_TLR_CSR_A_SERDES_XMITTER_LANE_STATUS_ADDR  mpeval(0x006e2480 + N2_DMU_PEU_BASE_ADDR)
!! This register maps to a ram with a depth of: 8
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_SERDES_XMITTER_LANE_STATUS_WRITE_MASK  0x0000000000000000
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_SERDES_XMITTER_LANE_STATUS_POR_VALUE  0x0000000000000000

#define FIRE_PLC_TLU_CTB_TLR_CSR_A_SERDES_MACRO_TEST_CFG_ADDR    mpeval(0x006e2500 + N2_DMU_PEU_BASE_ADDR)
!! This register maps to a ram with a depth of: 2
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_SERDES_MACRO_TEST_CFG_WRITE_MASK  0x0000000000007fff
#define FIRE_PLC_TLU_CTB_TLR_CSR_A_SERDES_MACRO_TEST_CFG_POR_VALUE  0x0000000000000003