* ========== Copyright Header Begin ==========================================
* OpenSPARC T2 Processor File: interrupt0x60_handler.s
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
* For the avoidance of doubt, and except that if any non-GPL license
* choice is available it will apply instead, Sun elects to use only
* the General Public License version 2 (GPLv2) at this time for any
* software where a choice of GPL license versions is made
* available with the language indicating that GPLv2 or any later version
* may be used, or where a choice of which version of the GPL is applied is
* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
* CA 95054 USA or visit www.sun.com if you need additional information or
* ========== Copyright Header End ============================================
#include "bobo_defines.h"
mov %g7, %o7 ! Restore %o7
ldxa [%g0] ASI_INTR_ID, %g1 ! Get the thread number
ldxa [%g0] ASI_INTR_R, %g2 ! Get the interrupt vector number
setx intr0x60_ivn_to_ig, %g4, %g3
#ifdef INTR0x60_NIU_TX_IV_0
cmp %g4, INTR0x60_IG_NIU_TX
be intr0x60_handle_niu_tx
#endif /* INTR0x60_NIU_TX_IV_0 */
#ifdef INTR0x60_NIU_RX_IV_0
cmp %g4, INTR0x60_IG_NIU_RX
be intr0x60_handle_niu_rx
#endif /* INTR0x60_NIU_RX_IV_0 */
#endif /* INTR0x60_MONDO_IV */
#if (INTR0x60_SSI_ERR_IV != INTR0x60_BAD_IV)
cmp %g4, INTR0x60_IG_SSI_ERR
be intr0x60_handle_ssi_err
#endif /* (INTR0x60_SSI_ERR_IV != INTR0x60_BAD_IV) */
#if (INTR0x60_SSI_INT_IV != INTR0x60_BAD_IV)
cmp %g4, INTR0x60_IG_SSI_INT
be intr0x60_handle_ssi_int
#endif /* (INTR0x60_SSI_INT_IV != INTR0x60_BAD_IV) */
/* If we get here, we got an unexpected vector number */
!$EV trig_pc_d(1, @VA(.HTRAPS.intr0x60_bad_ivn)) -> printf("ERROR: Bad interrupt vector number",*,1)
/************************************************************************/
/* Handle cross-call interrupts */
!$EV trig_pc_d(1, @VA(.HTRAPS.intr0x60_handle_cc)) -> printf("INFO: Cross-call interrupt received",*,1)
#ifndef INTR0x60_CC_DEST_ALL
/* Make sure that this thread is allowed to receive cross-calls */
setx intr0x60_handle_cc_thread_table, %g5, %g4
brz %g4, intr0x60_handle_cc_bad_thread
#endif /* INTR0x60_CC_DEST_ALL */
/* Include any extra cross-call handler from the user */
/* The code can assume that %g1 is the thread and %g2 is the vector */
#ifdef INTR0x60_CC_EXTRA_HANDLER
intr0x60_handle_cc_extra_handler:
INTR0x60_CC_EXTRA_HANDLER
#endif /* INTR0x60_CC_EXTRA_HANDLER */
intr0x60_handle_cc_retry:
/* Retry the instruction that was trapped */
#ifndef INTR0x60_CC_DEST_ALL
intr0x60_handle_cc_bad_thread:
!$EV trig_pc_d(1, @VA(.HTRAPS.intr0x60_handle_cc_bad_thread)) -> printf("ERROR: Cross-call received on unexpected thread",*,1)
intr0x60_handle_cc_thread_table:
#if defined(INTR0x60_CC_DEST_0)
#if defined(INTR0x60_CC_DEST_1)
#if defined(INTR0x60_CC_DEST_2)
#if defined(INTR0x60_CC_DEST_3)
#if defined(INTR0x60_CC_DEST_4)
#if defined(INTR0x60_CC_DEST_5)
#if defined(INTR0x60_CC_DEST_6)
#if defined(INTR0x60_CC_DEST_7)
#if defined(INTR0x60_CC_DEST_8)
#if defined(INTR0x60_CC_DEST_9)
#if defined(INTR0x60_CC_DEST_10)
#if defined(INTR0x60_CC_DEST_11)
#if defined(INTR0x60_CC_DEST_12)
#if defined(INTR0x60_CC_DEST_13)
#if defined(INTR0x60_CC_DEST_14)
#if defined(INTR0x60_CC_DEST_15)
#if defined(INTR0x60_CC_DEST_16)
#if defined(INTR0x60_CC_DEST_17)
#if defined(INTR0x60_CC_DEST_18)
#if defined(INTR0x60_CC_DEST_19)
#if defined(INTR0x60_CC_DEST_20)
#if defined(INTR0x60_CC_DEST_21)
#if defined(INTR0x60_CC_DEST_22)
#if defined(INTR0x60_CC_DEST_23)
#if defined(INTR0x60_CC_DEST_24)
#if defined(INTR0x60_CC_DEST_25)
#if defined(INTR0x60_CC_DEST_26)
#if defined(INTR0x60_CC_DEST_27)
#if defined(INTR0x60_CC_DEST_28)
#if defined(INTR0x60_CC_DEST_29)
#if defined(INTR0x60_CC_DEST_30)
#if defined(INTR0x60_CC_DEST_31)
#if defined(INTR0x60_CC_DEST_32)
#if defined(INTR0x60_CC_DEST_33)
#if defined(INTR0x60_CC_DEST_34)
#if defined(INTR0x60_CC_DEST_35)
#if defined(INTR0x60_CC_DEST_36)
#if defined(INTR0x60_CC_DEST_37)
#if defined(INTR0x60_CC_DEST_38)
#if defined(INTR0x60_CC_DEST_39)
#if defined(INTR0x60_CC_DEST_40)
#if defined(INTR0x60_CC_DEST_41)
#if defined(INTR0x60_CC_DEST_42)
#if defined(INTR0x60_CC_DEST_43)
#if defined(INTR0x60_CC_DEST_44)
#if defined(INTR0x60_CC_DEST_45)
#if defined(INTR0x60_CC_DEST_46)
#if defined(INTR0x60_CC_DEST_47)
#if defined(INTR0x60_CC_DEST_48)
#if defined(INTR0x60_CC_DEST_49)
#if defined(INTR0x60_CC_DEST_50)
#if defined(INTR0x60_CC_DEST_51)
#if defined(INTR0x60_CC_DEST_52)
#if defined(INTR0x60_CC_DEST_53)
#if defined(INTR0x60_CC_DEST_54)
#if defined(INTR0x60_CC_DEST_55)
#if defined(INTR0x60_CC_DEST_56)
#if defined(INTR0x60_CC_DEST_57)
#if defined(INTR0x60_CC_DEST_58)
#if defined(INTR0x60_CC_DEST_59)
#if defined(INTR0x60_CC_DEST_60)
#if defined(INTR0x60_CC_DEST_61)
#if defined(INTR0x60_CC_DEST_62)
#if defined(INTR0x60_CC_DEST_63)
#endif /* INTR0x60_CC_DEST_ALL */
#ifdef INTR0x60_NIU_TX_IV_0
/************************************************************************/
/* Handle NIU TX interrupts */
!$EV trig_pc_d(1, @VA(.HTRAPS.intr0x60_handle_niu_tx)) -> printf("INFO: NIU TX interrupt received",*,1)
/* Make sure that this thread is the right one for this NIU interrupt */
#ifdef INTR0x60_NIU_TX_IV_0
intr0x60_handle_niu_tx_check_thread_0:
cmp %g2, INTR0x60_NIU_TX_IV_0
cmp %g7, INTR0x60_NIU_TX_THREAD_0
cmp %g1, INTR0x60_NIU_TX_THREAD_0
bnz intr0x60_handle_niu_tx_bad_thread
best_set_reg(INTR0x60_NIU_TX_DMA_0, %g7, %g3)
ba intr0x60_handle_niu_tx_good_thread
#endif /* INTR0x60_NIU_TX_IV_0 */
#ifdef INTR0x60_NIU_TX_IV_1
intr0x60_handle_niu_tx_check_thread_1:
cmp %g2, INTR0x60_NIU_TX_IV_1
cmp %g7, INTR0x60_NIU_TX_THREAD_1
cmp %g1, INTR0x60_NIU_TX_THREAD_1
bnz intr0x60_handle_niu_tx_bad_thread
best_set_reg(INTR0x60_NIU_TX_DMA_1, %g7, %g3)
ba intr0x60_handle_niu_tx_good_thread
#endif /* INTR0x60_NIU_TX_IV_1 */
#ifdef INTR0x60_NIU_TX_IV_2
intr0x60_handle_niu_tx_check_thread_2:
cmp %g2, INTR0x60_NIU_TX_IV_2
cmp %g7, INTR0x60_NIU_TX_THREAD_2
cmp %g1, INTR0x60_NIU_TX_THREAD_2
bnz intr0x60_handle_niu_tx_bad_thread
best_set_reg(INTR0x60_NIU_TX_DMA_2, %g7, %g3)
ba intr0x60_handle_niu_tx_good_thread
#endif /* INTR0x60_NIU_TX_IV_2 */
#ifdef INTR0x60_NIU_TX_IV_3
intr0x60_handle_niu_tx_check_thread_3:
cmp %g2, INTR0x60_NIU_TX_IV_3
cmp %g7, INTR0x60_NIU_TX_THREAD_3
cmp %g1, INTR0x60_NIU_TX_THREAD_3
bnz intr0x60_handle_niu_tx_bad_thread
best_set_reg(INTR0x60_NIU_TX_DMA_3, %g7, %g3)
ba intr0x60_handle_niu_tx_good_thread
#endif /* INTR0x60_NIU_TX_IV_3 */
#ifdef INTR0x60_NIU_TX_IV_4
intr0x60_handle_niu_tx_check_thread_4:
cmp %g2, INTR0x60_NIU_TX_IV_4
cmp %g7, INTR0x60_NIU_TX_THREAD_4
cmp %g1, INTR0x60_NIU_TX_THREAD_4
bnz intr0x60_handle_niu_tx_bad_thread
best_set_reg(INTR0x60_NIU_TX_DMA_4, %g7, %g3)
ba intr0x60_handle_niu_tx_good_thread
#endif /* INTR0x60_NIU_TX_IV_4 */
#ifdef INTR0x60_NIU_TX_IV_5
intr0x60_handle_niu_tx_check_thread_5:
cmp %g2, INTR0x60_NIU_TX_IV_5
cmp %g7, INTR0x60_NIU_TX_THREAD_5
cmp %g1, INTR0x60_NIU_TX_THREAD_5
bnz intr0x60_handle_niu_tx_bad_thread
best_set_reg(INTR0x60_NIU_TX_DMA_5, %g7, %g3)
ba intr0x60_handle_niu_tx_good_thread
#endif /* INTR0x60_NIU_TX_IV_5 */
#ifdef INTR0x60_NIU_TX_IV_6
intr0x60_handle_niu_tx_check_thread_6:
cmp %g2, INTR0x60_NIU_TX_IV_6
cmp %g7, INTR0x60_NIU_TX_THREAD_6
cmp %g1, INTR0x60_NIU_TX_THREAD_6
bnz intr0x60_handle_niu_tx_bad_thread
best_set_reg(INTR0x60_NIU_TX_DMA_6, %g7, %g3)
ba intr0x60_handle_niu_tx_good_thread
#endif /* INTR0x60_NIU_TX_IV_6 */
#ifdef INTR0x60_NIU_TX_IV_7
intr0x60_handle_niu_tx_check_thread_7:
cmp %g2, INTR0x60_NIU_TX_IV_7
cmp %g7, INTR0x60_NIU_TX_THREAD_7
cmp %g1, INTR0x60_NIU_TX_THREAD_7
bnz intr0x60_handle_niu_tx_bad_thread
best_set_reg(INTR0x60_NIU_TX_DMA_7, %g7, %g3)
ba intr0x60_handle_niu_tx_good_thread
#endif /* INTR0x60_NIU_TX_IV_7 */
#ifdef INTR0x60_NIU_TX_IV_8
intr0x60_handle_niu_tx_check_thread_8:
cmp %g2, INTR0x60_NIU_TX_IV_8
cmp %g7, INTR0x60_NIU_TX_THREAD_8
cmp %g1, INTR0x60_NIU_TX_THREAD_8
bnz intr0x60_handle_niu_tx_bad_thread
best_set_reg(INTR0x60_NIU_TX_DMA_8, %g7, %g3)
ba intr0x60_handle_niu_tx_good_thread
#endif /* INTR0x60_NIU_TX_IV_8 */
#ifdef INTR0x60_NIU_TX_IV_9
intr0x60_handle_niu_tx_check_thread_9:
cmp %g2, INTR0x60_NIU_TX_IV_9
cmp %g7, INTR0x60_NIU_TX_THREAD_9
cmp %g1, INTR0x60_NIU_TX_THREAD_9
bnz intr0x60_handle_niu_tx_bad_thread
best_set_reg(INTR0x60_NIU_TX_DMA_9, %g7, %g3)
ba intr0x60_handle_niu_tx_good_thread
#endif /* INTR0x60_NIU_TX_IV_9 */
#ifdef INTR0x60_NIU_TX_IV_10
intr0x60_handle_niu_tx_check_thread_10:
cmp %g2, INTR0x60_NIU_TX_IV_10
cmp %g7, INTR0x60_NIU_TX_THREAD_10
cmp %g1, INTR0x60_NIU_TX_THREAD_10
bnz intr0x60_handle_niu_tx_bad_thread
best_set_reg(INTR0x60_NIU_TX_DMA_10, %g7, %g3)
ba intr0x60_handle_niu_tx_good_thread
#endif /* INTR0x60_NIU_TX_IV_10 */
#ifdef INTR0x60_NIU_TX_IV_11
intr0x60_handle_niu_tx_check_thread_11:
cmp %g2, INTR0x60_NIU_TX_IV_11
cmp %g7, INTR0x60_NIU_TX_THREAD_11
cmp %g1, INTR0x60_NIU_TX_THREAD_11
bnz intr0x60_handle_niu_tx_bad_thread
best_set_reg(INTR0x60_NIU_TX_DMA_11, %g7, %g3)
ba intr0x60_handle_niu_tx_good_thread
#endif /* INTR0x60_NIU_TX_IV_11 */
#ifdef INTR0x60_NIU_TX_IV_12
intr0x60_handle_niu_tx_check_thread_12:
cmp %g2, INTR0x60_NIU_TX_IV_12
cmp %g7, INTR0x60_NIU_TX_THREAD_12
cmp %g1, INTR0x60_NIU_TX_THREAD_12
bnz intr0x60_handle_niu_tx_bad_thread
best_set_reg(INTR0x60_NIU_TX_DMA_12, %g7, %g3)
ba intr0x60_handle_niu_tx_good_thread
#endif /* INTR0x60_NIU_TX_IV_12 */
#ifdef INTR0x60_NIU_TX_IV_13
intr0x60_handle_niu_tx_check_thread_13:
cmp %g2, INTR0x60_NIU_TX_IV_13
cmp %g7, INTR0x60_NIU_TX_THREAD_13
cmp %g1, INTR0x60_NIU_TX_THREAD_13
bnz intr0x60_handle_niu_tx_bad_thread
best_set_reg(INTR0x60_NIU_TX_DMA_13, %g7, %g3)
ba intr0x60_handle_niu_tx_good_thread
#endif /* INTR0x60_NIU_TX_IV_13 */
#ifdef INTR0x60_NIU_TX_IV_14
intr0x60_handle_niu_tx_check_thread_14:
cmp %g2, INTR0x60_NIU_TX_IV_14
cmp %g7, INTR0x60_NIU_TX_THREAD_14
cmp %g1, INTR0x60_NIU_TX_THREAD_14
bnz intr0x60_handle_niu_tx_bad_thread
best_set_reg(INTR0x60_NIU_TX_DMA_14, %g7, %g3)
ba intr0x60_handle_niu_tx_good_thread
#endif /* INTR0x60_NIU_TX_IV_14 */
#ifdef INTR0x60_NIU_TX_IV_15
intr0x60_handle_niu_tx_check_thread_15:
cmp %g2, INTR0x60_NIU_TX_IV_15
cmp %g7, INTR0x60_NIU_TX_THREAD_15
cmp %g1, INTR0x60_NIU_TX_THREAD_15
bnz intr0x60_handle_niu_tx_bad_thread
best_set_reg(INTR0x60_NIU_TX_DMA_15, %g7, %g3)
ba intr0x60_handle_niu_tx_good_thread
#endif /* INTR0x60_NIU_TX_IV_15 */
/* If we get here, we have an unknown vector */
intr0x60_handle_niu_tx_bad_vector:
!$EV trig_pc_d(1, @VA(.HTRAPS.intr0x60_handle_niu_tx_bad_vector)) -> printf("interrupt0x60_handler.s ERROR: intr0x60_iv_to_ig said this is an NIU TX interrupt, but it is not defined in INTR0x60_NIU_TX_IV_x",*,1)
/* If we get here, we know we have the right thread for this vector */
intr0x60_handle_niu_tx_good_thread:
/* Clear the source of the interrupt */
! Re-enable the interrupt in the transmit DMA channel
best_set_reg(TX_CS, %g7, %g4) ! TX_CS
best_set_reg(TDMC_STEP, %g7, %g5)
mulx %g5, %g3, %g5 ! %g3 is the DMA TX channel
ldxa [%g4]ASI_PRIMARY_LITTLE, %g0 ! Reset MK
! Re-enable the interrupt in the NIU
best_set_reg(LDGIMGN, %g7, %g4) ! LDGIMGN
best_set_reg(LDGIMGN_STEP, %g7, %g5)
best_set_reg(0x80000001, %g7, %g5)
stxa %g5, [%g4]ASI_PRIMARY_LITTLE
/* Include any extra NIU handler from the user */
/* The code can assume that %g1 is the thread, %g2 is the vector,
* and %g3 is the TX DMA channel */
#ifdef INTR0x60_NIU_TX_EXTRA_HANDLER
intr0x60_handle_niu_tx_extra_handler:
INTR0x60_NIU_TX_EXTRA_HANDLER
#endif /* INTR0x60_NIU_TX_EXTRA_HANDLER */
intr0x60_handle_niu_tx_retry:
/* Retry the instruction that was trapped */
intr0x60_handle_niu_tx_bad_thread:
!$EV trig_pc_d(1, @VA(.HTRAPS.intr0x60_handle_niu_tx_bad_thread)) -> printf("ERROR: NIU TX interrupt received on unexpected thread",*,1)
#endif /* INTR0x60_NIU_TX_IV_0 */
#ifdef INTR0x60_NIU_RX_IV_0
/************************************************************************/
/* Handle NIU RX interrupts */
!$EV trig_pc_d(1, @VA(.HTRAPS.intr0x60_handle_niu_rx)) -> printf("INFO: NIU RX interrupt received",*,1)
/* Make sure that this thread is the right one for this NIU interrupt */
#ifdef INTR0x60_NIU_RX_IV_0
intr0x60_handle_niu_rx_check_thread_0:
cmp %g2, INTR0x60_NIU_RX_IV_0
cmp %g7, INTR0x60_NIU_RX_THREAD_0
cmp %g1, INTR0x60_NIU_RX_THREAD_0
bnz intr0x60_handle_niu_rx_bad_thread
best_set_reg(INTR0x60_NIU_RX_DMA_0, %g7, %g3)
ba intr0x60_handle_niu_rx_good_thread
#endif /* INTR0x60_NIU_RX_IV_0 */
#ifdef INTR0x60_NIU_RX_IV_1
intr0x60_handle_niu_rx_check_thread_1:
cmp %g2, INTR0x60_NIU_RX_IV_1
cmp %g7, INTR0x60_NIU_RX_THREAD_1
cmp %g1, INTR0x60_NIU_RX_THREAD_1
bnz intr0x60_handle_niu_rx_bad_thread
best_set_reg(INTR0x60_NIU_RX_DMA_1, %g7, %g3)
ba intr0x60_handle_niu_rx_good_thread
#endif /* INTR0x60_NIU_RX_IV_1 */
#ifdef INTR0x60_NIU_RX_IV_2
intr0x60_handle_niu_rx_check_thread_2:
cmp %g2, INTR0x60_NIU_RX_IV_2
cmp %g7, INTR0x60_NIU_RX_THREAD_2
cmp %g1, INTR0x60_NIU_RX_THREAD_2
bnz intr0x60_handle_niu_rx_bad_thread
best_set_reg(INTR0x60_NIU_RX_DMA_2, %g7, %g3)
ba intr0x60_handle_niu_rx_good_thread
#endif /* INTR0x60_NIU_RX_IV_2 */
#ifdef INTR0x60_NIU_RX_IV_3
intr0x60_handle_niu_rx_check_thread_3:
cmp %g2, INTR0x60_NIU_RX_IV_3
cmp %g7, INTR0x60_NIU_RX_THREAD_3
cmp %g1, INTR0x60_NIU_RX_THREAD_3
bnz intr0x60_handle_niu_rx_bad_thread
best_set_reg(INTR0x60_NIU_RX_DMA_3, %g7, %g3)
ba intr0x60_handle_niu_rx_good_thread
#endif /* INTR0x60_NIU_RX_IV_3 */
#ifdef INTR0x60_NIU_RX_IV_4
intr0x60_handle_niu_rx_check_thread_4:
cmp %g2, INTR0x60_NIU_RX_IV_4
cmp %g7, INTR0x60_NIU_RX_THREAD_4
cmp %g1, INTR0x60_NIU_RX_THREAD_4
bnz intr0x60_handle_niu_rx_bad_thread
best_set_reg(INTR0x60_NIU_RX_DMA_4, %g7, %g3)
ba intr0x60_handle_niu_rx_good_thread
#endif /* INTR0x60_NIU_RX_IV_4 */
#ifdef INTR0x60_NIU_RX_IV_5
intr0x60_handle_niu_rx_check_thread_5:
cmp %g2, INTR0x60_NIU_RX_IV_5
cmp %g7, INTR0x60_NIU_RX_THREAD_5
cmp %g1, INTR0x60_NIU_RX_THREAD_5
bnz intr0x60_handle_niu_rx_bad_thread
best_set_reg(INTR0x60_NIU_RX_DMA_5, %g7, %g3)
ba intr0x60_handle_niu_rx_good_thread
#endif /* INTR0x60_NIU_RX_IV_5 */
#ifdef INTR0x60_NIU_RX_IV_6
intr0x60_handle_niu_rx_check_thread_6:
cmp %g2, INTR0x60_NIU_RX_IV_6
cmp %g7, INTR0x60_NIU_RX_THREAD_6
cmp %g1, INTR0x60_NIU_RX_THREAD_6
bnz intr0x60_handle_niu_rx_bad_thread
best_set_reg(INTR0x60_NIU_RX_DMA_6, %g7, %g3)
ba intr0x60_handle_niu_rx_good_thread
#endif /* INTR0x60_NIU_RX_IV_6 */
#ifdef INTR0x60_NIU_RX_IV_7
intr0x60_handle_niu_rx_check_thread_7:
cmp %g2, INTR0x60_NIU_RX_IV_7
cmp %g7, INTR0x60_NIU_RX_THREAD_7
cmp %g1, INTR0x60_NIU_RX_THREAD_7
bnz intr0x60_handle_niu_rx_bad_thread
best_set_reg(INTR0x60_NIU_RX_DMA_7, %g7, %g3)
ba intr0x60_handle_niu_rx_good_thread
#endif /* INTR0x60_NIU_RX_IV_7 */
#ifdef INTR0x60_NIU_RX_IV_8
intr0x60_handle_niu_rx_check_thread_8:
cmp %g2, INTR0x60_NIU_RX_IV_8
cmp %g7, INTR0x60_NIU_RX_THREAD_8
cmp %g1, INTR0x60_NIU_RX_THREAD_8
bnz intr0x60_handle_niu_rx_bad_thread
best_set_reg(INTR0x60_NIU_RX_DMA_8, %g7, %g3)
ba intr0x60_handle_niu_rx_good_thread
#endif /* INTR0x60_NIU_RX_IV_8 */
#ifdef INTR0x60_NIU_RX_IV_9
intr0x60_handle_niu_rx_check_thread_9:
cmp %g2, INTR0x60_NIU_RX_IV_9
cmp %g7, INTR0x60_NIU_RX_THREAD_9
cmp %g1, INTR0x60_NIU_RX_THREAD_9
bnz intr0x60_handle_niu_rx_bad_thread
best_set_reg(INTR0x60_NIU_RX_DMA_9, %g7, %g3)
ba intr0x60_handle_niu_rx_good_thread
#endif /* INTR0x60_NIU_RX_IV_9 */
#ifdef INTR0x60_NIU_RX_IV_10
intr0x60_handle_niu_rx_check_thread_10:
cmp %g2, INTR0x60_NIU_RX_IV_10
cmp %g7, INTR0x60_NIU_RX_THREAD_10
cmp %g1, INTR0x60_NIU_RX_THREAD_10
bnz intr0x60_handle_niu_rx_bad_thread
best_set_reg(INTR0x60_NIU_RX_DMA_10, %g7, %g3)
ba intr0x60_handle_niu_rx_good_thread
#endif /* INTR0x60_NIU_RX_IV_10 */
#ifdef INTR0x60_NIU_RX_IV_11
intr0x60_handle_niu_rx_check_thread_11:
cmp %g2, INTR0x60_NIU_RX_IV_11
cmp %g7, INTR0x60_NIU_RX_THREAD_11
cmp %g1, INTR0x60_NIU_RX_THREAD_11
bnz intr0x60_handle_niu_rx_bad_thread
best_set_reg(INTR0x60_NIU_RX_DMA_11, %g7, %g3)
ba intr0x60_handle_niu_rx_good_thread
#endif /* INTR0x60_NIU_RX_IV_11 */
#ifdef INTR0x60_NIU_RX_IV_12
intr0x60_handle_niu_rx_check_thread_12:
cmp %g2, INTR0x60_NIU_RX_IV_12
cmp %g7, INTR0x60_NIU_RX_THREAD_12
cmp %g1, INTR0x60_NIU_RX_THREAD_12
bnz intr0x60_handle_niu_rx_bad_thread
best_set_reg(INTR0x60_NIU_RX_DMA_12, %g7, %g3)
ba intr0x60_handle_niu_rx_good_thread
#endif /* INTR0x60_NIU_RX_IV_12 */
#ifdef INTR0x60_NIU_RX_IV_13
intr0x60_handle_niu_rx_check_thread_13:
cmp %g2, INTR0x60_NIU_RX_IV_13
cmp %g7, INTR0x60_NIU_RX_THREAD_13
cmp %g1, INTR0x60_NIU_RX_THREAD_13
bnz intr0x60_handle_niu_rx_bad_thread
best_set_reg(INTR0x60_NIU_RX_DMA_13, %g7, %g3)
ba intr0x60_handle_niu_rx_good_thread
#endif /* INTR0x60_NIU_RX_IV_13 */
#ifdef INTR0x60_NIU_RX_IV_14
intr0x60_handle_niu_rx_check_thread_14:
cmp %g2, INTR0x60_NIU_RX_IV_14
cmp %g7, INTR0x60_NIU_RX_THREAD_14
cmp %g1, INTR0x60_NIU_RX_THREAD_14
bnz intr0x60_handle_niu_rx_bad_thread
best_set_reg(INTR0x60_NIU_RX_DMA_14, %g7, %g3)
ba intr0x60_handle_niu_rx_good_thread
#endif /* INTR0x60_NIU_RX_IV_14 */
#ifdef INTR0x60_NIU_RX_IV_15
intr0x60_handle_niu_rx_check_thread_15:
cmp %g2, INTR0x60_NIU_RX_IV_15
cmp %g7, INTR0x60_NIU_RX_THREAD_15
cmp %g1, INTR0x60_NIU_RX_THREAD_15
bnz intr0x60_handle_niu_rx_bad_thread
best_set_reg(INTR0x60_NIU_RX_DMA_15, %g7, %g3)
ba intr0x60_handle_niu_rx_good_thread
#endif /* INTR0x60_NIU_RX_IV_15 */
/* If we get here, we have an unknown vector */
intr0x60_handle_niu_rx_bad_vector:
!$EV trig_pc_d(1, @VA(.HTRAPS.intr0x60_handle_niu_rx_bad_vector)) -> printf("interrupt0x60_handler.s ERROR: intr0x60_iv_to_ig said this is an NIU RX interrupt, but it is not defined in INTR0x60_NIU_RX_IV_x",*,1)
/* If we get here, we know we have the right thread for this vector */
intr0x60_handle_niu_rx_good_thread:
/* Clear the source of the interrupt */
best_set_reg(RX_DMA_CTL_STAT, %g7, %g4)
mulx %g3, RX_DMA_CTL_STAT_STEP, %g7 ! %g3 is the DMA RX channel
add %g4, %g7, %g4 ! Addr of RX DMA Ctl/stat for this channel
intr0x60_handle_niu_rx_get_rx_dma_ctl_stat:
ldxa [%g4]ASI_PRIMARY_LITTLE, %g5 ! Get status
sllx %g7, 32, %g7 ! Mask for clear-on-reset error bits
brz %g7, intr0x60_handle_niu_rx_nonfatal
intr0x60_handle_niu_rx_fatal_error:
#ifdef INTR0x60_NIU_RX_FATAL_HANDLER
INTR0x60_NIU_RX_FATAL_HANDLER
#else /* INTR0x60_NIU_RX_FATAL_HANDLER */
#ifdef INTR0x60_NIU_RX_CLEAR_FATAL_FOR_TSOTOOL
/* This code does what is needed for tsotool NIU RX fatal error interrupts */
best_set_reg(RXDMA_CFIG1, %g7, %g4)
mulx %g3, RX_DMA_CTL_STAT_STEP, %g7 ! %g3 is the DMA RX channel
intr0x60_handle_niu_rx_fatal_error_disable_dma_channel:
stxa %g0, [%g4]ASI_PRIMARY_LITTLE
sllx %g7, 30, %g7 ! RST bit in RXDMA_CFIG1
intr0x60_handle_niu_rx_fatal_error_reset_dma_channel:
stxa %g7, [%g4]ASI_PRIMARY_LITTLE
srlx %g7, 1, %g7 ! QST bit in RXDMA_CFIG1
intr0x60_handle_niu_rx_fatal_error_wait_for_dma_channel:
ldxa [%g4]ASI_PRIMARY_LITTLE, %g5 ! Get the status
beq intr0x60_handle_niu_rx_fatal_error_enable_intr_for_dma_channel
brnz %g6, intr0x60_handle_niu_rx_fatal_error_wait_for_dma_channel
intr0x60_handle_niu_rx_fatal_error_timeout_wait_for_dma_channel:
!$EV trig_pc_d(1, @VA(.HTRAPS.intr0x60_handle_niu_rx_fatal_error_timeout_wait_for_dma_channel)) -> printf("ERROR: NIU RX interrupt received for fatal error and DMA channel reset never completed",*,1)
intr0x60_handle_niu_rx_fatal_error_enable_intr_for_dma_channel:
best_set_reg(RX_DMA_ENT_MSK, %g7, %g5)
mulx %g3, RX_DMA_CTL_STAT_STEP, %g7 ! %g3 is the DMA RX channel
stxa %g0, [%g5]ASI_PRIMARY_LITTLE
ba intr0x60_handle_niu_rx_reenable_ldg
#else /* INTR0x60_NIU_RX_CLEAR_FATAL_FOR_TSOTOOL */
!$EV trig_pc_d(1, @VA(.HTRAPS.intr0x60_handle_niu_rx_fatal_error)) -> printf("ERROR: NIU RX interrupt received for fatal error",*,1)
#endif /* INTR0x60_NIU_RX_CLEAR_FATAL_FOR_TSOTOOL */
#endif /* INTR0x60_NIU_RX_FATAL_HANDLER */
intr0x60_handle_niu_rx_nonfatal:
best_set_reg(0xffffffffffff0000, %g7, %g6)
and %g5, %g6, %g5 ! Only preserve error bits, for RW1C
best_set_reg(RCR_STAT_A, %g7, %g6)
mulx %g3, RX_DMA_CTL_STAT_STEP, %g7 ! %g3 is the DMA RX channel
intr0x60_handle_niu_rx_get_rcr_stat_a:
ldxa [%g6]ASI_PRIMARY_LITTLE, %g6 ! Get the number of pkts received
best_set_reg(THRES_INT, %g7, %g5) ! Bit to enable mailbox (MEX in PRM)
intr0x60_handle_niu_rx_reset_rx_dma_ctl_stat:
stxa %g6, [%g4]ASI_PRIMARY_LITTLE ! RW1C on RCRTHRES, RCRTO, etc., plus
! set MEX, decrement QLEN by pkt read
intr0x60_handle_niu_rx_reenable_ldg:
! Re-enable the interrupt in the NIU LDG
best_set_reg(LDGIMGN, %g7, %g4) ! LDGIMGN
best_set_reg(LDGIMGN_STEP, %g7, %g5)
best_set_reg(0x80000001, %g7, %g5)
stxa %g5, [%g4]ASI_PRIMARY_LITTLE ! Arm LDGI, set timer to 1
/* Include any extra NIU handler from the user */
/* The code can assume that %g1 is the thread, %g2 is the vector,
* and %g3 is the RX DMA channel */
#ifdef INTR0x60_NIU_RX_EXTRA_HANDLER
intr0x60_handle_niu_rx_extra_handler:
INTR0x60_NIU_RX_EXTRA_HANDLER
#endif /* INTR0x60_NIU_RX_EXTRA_HANDLER */
intr0x60_handle_niu_rx_retry:
/* Retry the instruction that was trapped */
intr0x60_handle_niu_rx_bad_thread:
!$EV trig_pc_d(1, @VA(.HTRAPS.intr0x60_handle_niu_rx_bad_thread)) -> printf("ERROR: NIU RX interrupt received on unexpected thread",*,1)
#endif /* INTR0x60_NIU_RX_IV_0 */
/************************************************************************/
/* Handle PIU interrupts */
!$EV trig_pc_d(1, @VA(.HTRAPS.intr0x60_handle_piu)) -> printf("INFO: PIU interrupt received",*,1)
#ifndef INTR0x60_DO_NOT_READ_ADATA1
/* To reach coverage goals, do a dummy read from ADATA1 */
best_set_reg(MONDO_INT_ADATA1, %g4, %g3)
#endif /* INTR0x60_DO_NOT_READ_ADATA1 */
best_set_reg(MONDO_INT_ADATA0, %g4, %g3)
and %g3, 0x3f, %g3 /* WIP: Mask to get INO */
be intr0x60_handle_piu_inta
#endif /* INTR0x60_MONDO_20_V */
be intr0x60_handle_piu_intb
#endif /* INTR0x60_MONDO_21_V */
be intr0x60_handle_piu_intc
#endif /* INTR0x60_MONDO_22_V */
be intr0x60_handle_piu_intd
#endif /* INTR0x60_MONDO_23_V */
#ifdef INTR0x60_MSI_0_NUM
intr0x60_handle_piu_check_msi_0:
cmp %g3, mpeval(INTR0x60_MSI_0_EQN+24)
be intr0x60_handle_piu_msi_0
#endif /* INTR0x60_MSI_0_NUM */
#ifdef INTR0x60_MSI_1_NUM
intr0x60_handle_piu_check_msi_1:
cmp %g3, mpeval(INTR0x60_MSI_1_EQN+24)
be intr0x60_handle_piu_msi_1
#endif /* INTR0x60_MSI_1_NUM */
#ifdef INTR0x60_MSI_2_NUM
intr0x60_handle_piu_check_msi_2:
cmp %g3, mpeval(INTR0x60_MSI_2_EQN+24)
be intr0x60_handle_piu_msi_2
#endif /* INTR0x60_MSI_2_NUM */
#ifdef INTR0x60_MSI_3_NUM
intr0x60_handle_piu_check_msi_3:
cmp %g3, mpeval(INTR0x60_MSI_3_EQN+24)
be intr0x60_handle_piu_msi_3
#endif /* INTR0x60_MSI_3_NUM */
#ifdef INTR0x60_MSI_4_NUM
intr0x60_handle_piu_check_msi_4:
cmp %g3, mpeval(INTR0x60_MSI_4_EQN+24)
be intr0x60_handle_piu_msi_4
#endif /* INTR0x60_MSI_4_NUM */
#ifdef INTR0x60_MSI_5_NUM
intr0x60_handle_piu_check_msi_5:
cmp %g3, mpeval(INTR0x60_MSI_5_EQN+24)
be intr0x60_handle_piu_msi_5
#endif /* INTR0x60_MSI_5_NUM */
#ifdef INTR0x60_MSI_6_NUM
intr0x60_handle_piu_check_msi_6:
cmp %g3, mpeval(INTR0x60_MSI_6_EQN+24)
be intr0x60_handle_piu_msi_6
#endif /* INTR0x60_MSI_6_NUM */
#ifdef INTR0x60_MSI_7_NUM
intr0x60_handle_piu_check_msi_7:
cmp %g3, mpeval(INTR0x60_MSI_7_EQN+24)
be intr0x60_handle_piu_msi_7
#endif /* INTR0x60_MSI_7_NUM */
#ifdef INTR0x60_PM_PME_EQN
intr0x60_handle_piu_check_pm_pme:
cmp %g3, mpeval(INTR0x60_PM_PME_EQN+24)
be intr0x60_handle_piu_pm_pme
#endif /* INTR0x60_PM_PME_EQN */
#ifdef INTR0x60_PME_TO_ACK_EQN
intr0x60_handle_piu_check_pme_to_ack:
cmp %g3, mpeval(INTR0x60_PME_TO_ACK_EQN+24)
be intr0x60_handle_piu_pme_to_ack
#endif /* INTR0x60_PME_TO_ACK_EQN */
/* If we get here, we got an unexpected INO */
!$EV trig_pc_d(1, @VA(.HTRAPS.intr0x60_bad_mondo_INO)) -> printf("ERROR: Bad mondo INO",*,1)
/************ Handle INTA ***********/
intr0x60_handle_piu_inta:
/* Check whether this thread matches this INO */
cmp %g7/*tid*/, INTR0x60_MONDO_20_THREAD
cmp %g1/*tid*/, INTR0x60_MONDO_20_THREAD
bne intr0x60_handle_piu_bad_thread
/* Clear the interrupt */
intr0x60_handle_piu_inta_deassert:
! Offset accesses by PCIE_MEM64_OFFSET since
! BAR is set that way. Physical addresses generated via TSB
! have this offset so mimic that when accessing directly, as here.
best_set_reg(mpeval(N2_PCIE_BASE_ADDR
+ MEM64_OFFSET_BASE_REG_DATA
+ BOBO_INTR_VECT_STATUS_OFFSET), %g7, %g4)
! Offset accesses by PCIE_MEM64_OFFSET since
! BAR is set that way. Physical addresses generated via TSB
! have this offset so mimic that when accessing directly, as here.
best_set_reg(mpeval(N2_PCIE_BASE_ADDR
+ MEM64_OFFSET_BASE_REG_DATA
+ (INTR0x60_MONDO_20_DMAEPT_ENGINE << 8)
+ DMAEPT_INTERRUPT_ACK), %g7, %g4)
best_set_reg(DMAEPT_INTERRUPT_ACK_INTA, %g7, %g5)
#else /* FC_NO_PEU_VERA */
! $EV trig_pc_d(1, @VA(.HTRAPS.intr0x60_handle_piu_inta_deassert)) -> EnablePCIeIgCmd ("INTA", 0, 0, "DEASSERT", 1, *, 1 )
#endif /* FC_NO_PEU_VERA */
/* Loop on the INTX Status Register until the deassert message
* has arrived and been processed. */
best_set_reg(PCI_E_INTX_STATUS_ADDR, %g5, %g4)
best_set_reg(INTR0x60_INTX_DEASSERT_TIMEOUT, %g5, %g6)
intr0x60_handle_piu_inta_deassert_loop:
brz %g6, intr0x60_handle_piu_inta_deassert_timeout
and %g3, 8, %g3 ! 8 == bit for INTA
brnz %g3, intr0x60_handle_piu_inta_deassert_loop
intr0x60_handle_piu_inta_clear:
best_set_reg(PCI_E_INT_A_CLEAR_ADDR, %g5, %g4)
best_set_reg(mpeval(PCI_E_INT_CLEAR_ADDR+0*PCI_E_INT_CLEAR_STEP), %g5, %g4)
best_set_reg(MONDO_INT_ABUSY, %g5, %g4)
/* Include any extra INTA handler from the user */
/* The code can assume that %g1 is the thread and %g2 is the vector */
#ifdef INTR0x60_INTA_EXTRA_HANDLER
intr0x60_handle_inta_extra_handler:
INTR0x60_INTA_EXTRA_HANDLER
#endif /* INTR0x60_INTA_EXTRA_HANDLER */
intr0x60_handle_piu_inta_retry:
/* Retry the instruction that was trapped */
#endif /* INTR0x60_MONDO_20_V */
/* If we get here, the interrupt status bit didn't deassert */
intr0x60_handle_piu_inta_deassert_timeout:
!$EV trig_pc_d(1, @VA(.HTRAPS.intr0x60_handle_piu_inta_deassert_timeout)) -> printf("ERROR: INTA status bit did not deassert within INTR0x60_INTX_DEASSERT_TIMEOUT iterations",*,1)
/************ Handle INTB ***********/
intr0x60_handle_piu_intb:
/* Check whether this thread matches this INO */
cmp %g7/*tid*/, INTR0x60_MONDO_21_THREAD
cmp %g1/*tid*/, INTR0x60_MONDO_21_THREAD
bne intr0x60_handle_piu_bad_thread
/* Clear the interrupt */
intr0x60_handle_piu_intb_deassert:
! Offset accesses by PCIE_MEM64_OFFSET since
! BAR is set that way. Physical addresses generated via TSB
! have this offset so mimic that when accessing directly, as here.
best_set_reg(mpeval(N2_PCIE_BASE_ADDR
+ MEM64_OFFSET_BASE_REG_DATA
+ BOBO_INTR_VECT_STATUS_OFFSET), %g7, %g4)
! Offset accesses by PCIE_MEM64_OFFSET since
! BAR is set that way. Physical addresses generated via TSB
! have this offset so mimic that when accessing directly, as here.
best_set_reg(mpeval(N2_PCIE_BASE_ADDR
+ MEM64_OFFSET_BASE_REG_DATA
+ (INTR0x60_MONDO_21_DMAEPT_ENGINE << 8)
+ DMAEPT_INTERRUPT_ACK), %g7, %g4)
best_set_reg(DMAEPT_INTERRUPT_ACK_INTB, %g7, %g5)
#else /* FC_NO_PEU_VERA */
! $EV trig_pc_d(1, @VA(.HTRAPS.intr0x60_handle_piu_intb_deassert)) -> EnablePCIeIgCmd ("INTB", 0, 0, "DEASSERT", 1, *, 1 )
#endif /* FC_NO_PEU_VERA */
/* Loop on the INTX Status Register until the deassert message
* has arrived and been processed. */
best_set_reg(PCI_E_INTX_STATUS_ADDR, %g5, %g4)
best_set_reg(INTR0x60_INTX_DEASSERT_TIMEOUT, %g5, %g6)
intr0x60_handle_piu_intb_deassert_loop:
brz %g6, intr0x60_handle_piu_intb_deassert_timeout
and %g3, 4, %g3 ! 4 == bit for INTB
brnz %g3, intr0x60_handle_piu_intb_deassert_loop
intr0x60_handle_piu_intb_clear:
best_set_reg(PCI_E_INT_B_CLEAR_ADDR, %g5, %g4)
best_set_reg(mpeval(PCI_E_INT_CLEAR_ADDR+1*PCI_E_INT_CLEAR_STEP), %g5, %g4)
best_set_reg(MONDO_INT_ABUSY, %g5, %g4)
/* Include any extra INTB handler from the user */
/* The code can assume that %g1 is the thread and %g2 is the vector */
#ifdef INTR0x60_INTB_EXTRA_HANDLER
intr0x60_handle_intb_extra_handler:
INTR0x60_INTB_EXTRA_HANDLER
#endif /* INTR0x60_INTB_EXTRA_HANDLER */
intr0x60_handle_piu_intb_retry:
/* Retry the instruction that was trapped */
#endif /* INTR0x60_MONDO_21_V */
/* If we get here, the interrupt status bit didn't deassert */
intr0x60_handle_piu_intb_deassert_timeout:
!$EV trig_pc_d(1, @VA(.HTRAPS.intr0x60_handle_piu_intb_deassert_timeout)) -> printf("ERROR: INTB status bit did not deassert within INTR0x60_INTX_DEASSERT_TIMEOUT iterations",*,1)
/************ Handle INTC ***********/
intr0x60_handle_piu_intc:
/* Check whether this thread matches this INO */
cmp %g7/*tid*/, INTR0x60_MONDO_22_THREAD
cmp %g1/*tid*/, INTR0x60_MONDO_22_THREAD
bne intr0x60_handle_piu_bad_thread
/* Clear the interrupt */
intr0x60_handle_piu_intc_deassert:
! Offset accesses by PCIE_MEM64_OFFSET since
! BAR is set that way. Physical addresses generated via TSB
! have this offset so mimic that when accessing directly, as here.
best_set_reg(mpeval(N2_PCIE_BASE_ADDR
+ MEM64_OFFSET_BASE_REG_DATA
+ BOBO_INTR_VECT_STATUS_OFFSET), %g7, %g4)
! Offset accesses by PCIE_MEM64_OFFSET since
! BAR is set that way. Physical addresses generated via TSB
! have this offset so mimic that when accessing directly, as here.
best_set_reg(mpeval(N2_PCIE_BASE_ADDR
+ MEM64_OFFSET_BASE_REG_DATA
+ (INTR0x60_MONDO_22_DMAEPT_ENGINE << 8)
+ DMAEPT_INTERRUPT_ACK), %g7, %g4)
best_set_reg(DMAEPT_INTERRUPT_ACK_INTC, %g7, %g5)
#else /* FC_NO_PEU_VERA */
! $EV trig_pc_d(1, @VA(.HTRAPS.intr0x60_handle_piu_intc_deassert)) -> EnablePCIeIgCmd ("INTC", 0, 0, "DEASSERT", 1, *, 1 )
#endif /* FC_NO_PEU_VERA */
/* Loop on the INTX Status Register until the deassert message
* has arrived and been processed. */
best_set_reg(PCI_E_INTX_STATUS_ADDR, %g5, %g4)
best_set_reg(INTR0x60_INTX_DEASSERT_TIMEOUT, %g5, %g6)
intr0x60_handle_piu_intc_deassert_loop:
brz %g6, intr0x60_handle_piu_intc_deassert_timeout
and %g3, 2, %g3 ! 2 == bit for INTC
brnz %g3, intr0x60_handle_piu_intc_deassert_loop
intr0x60_handle_piu_intc_clear:
best_set_reg(PCI_E_INT_C_CLEAR_ADDR, %g5, %g4)
best_set_reg(mpeval(PCI_E_INT_CLEAR_ADDR+2*PCI_E_INT_CLEAR_STEP), %g5, %g4)
best_set_reg(MONDO_INT_ABUSY, %g5, %g4)
/* Include any extra INTC handler from the user */
/* The code can assume that %g1 is the thread and %g2 is the vector */
#ifdef INTR0x60_INTC_EXTRA_HANDLER
intr0x60_handle_intc_extra_handler:
INTR0x60_INTC_EXTRA_HANDLER
#endif /* INTR0x60_INTC_EXTRA_HANDLER */
intr0x60_handle_piu_intc_retry:
/* Retry the instruction that was trapped */
#endif /* INTR0x60_MONDO_22_V */
/* If we get here, the interrupt status bit didn't deassert */
intr0x60_handle_piu_intc_deassert_timeout:
!$EV trig_pc_d(1, @VA(.HTRAPS.intr0x60_handle_piu_intc_deassert_timeout)) -> printf("ERROR: INTC status bit did not deassert within INTR0x60_INTX_DEASSERT_TIMEOUT iterations",*,1)
/************ Handle INTD ***********/
intr0x60_handle_piu_intd:
/* Check whether this thread matches this INO */
cmp %g7/*tid*/, INTR0x60_MONDO_23_THREAD
cmp %g1/*tid*/, INTR0x60_MONDO_23_THREAD
bne intr0x60_handle_piu_bad_thread
/* Clear the interrupt */
intr0x60_handle_piu_intd_deassert:
! Offset accesses by PCIE_MEM64_OFFSET since
! BAR is set that way. Physical addresses generated via TSB
! have this offset so mimic that when accessing directly, as here.
best_set_reg(mpeval(N2_PCIE_BASE_ADDR
+ MEM64_OFFSET_BASE_REG_DATA
+ BOBO_INTR_VECT_STATUS_OFFSET), %g7, %g4)
! Offset accesses by PCIE_MEM64_OFFSET since
! BAR is set that way. Physical addresses generated via TSB
! have this offset so mimic that when accessing directly, as here.
best_set_reg(mpeval(N2_PCIE_BASE_ADDR
+ MEM64_OFFSET_BASE_REG_DATA
+ (INTR0x60_MONDO_23_DMAEPT_ENGINE << 8)
+ DMAEPT_INTERRUPT_ACK), %g7, %g4)
best_set_reg(DMAEPT_INTERRUPT_ACK_INTD, %g7, %g5)
#else /* FC_NO_PEU_VERA */
! $EV trig_pc_d(1, @VA(.HTRAPS.intr0x60_handle_piu_intd_deassert)) -> EnablePCIeIgCmd ("INTD", 0, 0, "DEASSERT", 1, *, 1 )
#endif /* FC_NO_PEU_VERA */
/* Loop on the INTX Status Register until the deassert message
* has arrived and been processed. */
best_set_reg(PCI_E_INTX_STATUS_ADDR, %g5, %g4)
best_set_reg(INTR0x60_INTX_DEASSERT_TIMEOUT, %g5, %g6)
intr0x60_handle_piu_intd_deassert_loop:
brz %g6, intr0x60_handle_piu_intd_deassert_timeout
and %g3, 1, %g3 ! 1 == bit for INTD
brnz %g3, intr0x60_handle_piu_intd_deassert_loop
intr0x60_handle_piu_intd_clear:
best_set_reg(PCI_E_INT_D_CLEAR_ADDR, %g5, %g4)
best_set_reg(mpeval(PCI_E_INT_CLEAR_ADDR+3*PCI_E_INT_CLEAR_STEP), %g5, %g4)
best_set_reg(MONDO_INT_ABUSY, %g5, %g4)
/* Include any extra INTD handler from the user */
/* The code can assume that %g1 is the thread and %g2 is the vector */
#ifdef INTR0x60_INTD_EXTRA_HANDLER
intr0x60_handle_intd_extra_handler:
INTR0x60_INTD_EXTRA_HANDLER
#endif /* INTR0x60_INTD_EXTRA_HANDLER */
intr0x60_handle_piu_intd_retry:
/* Retry the instruction that was trapped */
#endif /* INTR0x60_MONDO_23_V */
/* If we get here, the interrupt status bit didn't deassert */
intr0x60_handle_piu_intd_deassert_timeout:
!$EV trig_pc_d(1, @VA(.HTRAPS.intr0x60_handle_piu_intd_deassert_timeout)) -> printf("ERROR: INTD status bit did not deassert within INTR0x60_INTX_DEASSERT_TIMEOUT iterations",*,1)
#ifdef INTR0x60_MSI_0_NUM
/************ Handle MSI 0 ***********/
intr0x60_handle_piu_msi_0:
!WIP: /* Check whether this thread matches this INO */
!WIP: cmp %g1/*tid*/, INTR0x60_MONDO_XXX_THREAD
!WIP: bne intr0x60_handle_piu_bad_thread
/* Clear the interrupt */
intr0x60_handle_piu_msi_0_clear_eqwr:
sllx %g4, 62, %g4 ! EQWR_N is bit 62
best_set_reg(mpeval(PCI_E_MSI_CLEAR_ADDR
+PCI_E_MSI_CLEAR_STEP*INTR0x60_MSI_0_NUM),
stx %g4, [%g5] ! clear EQWR in MSI map reg.
intr0x60_handle_piu_msi_0_disable_eq:
sllx %g4, 44, %g4 ! DIS is bit 44
best_set_reg(mpeval(PCI_E_EV_QUE_CTL_CLEAR_ADDR
+PCI_E_EV_QUE_CTL_CLEAR_STEP*INTR0x60_MSI_0_EQN),
! Set Event Queue Head = Event Queue Tail
intr0x60_handle_piu_msi_0_reset_eq_head:
best_set_reg(mpeval(PCI_E_EV_QUE_TAIL_ADDR
+PCI_E_EV_QUE_TAIL_STEP*INTR0x60_MSI_0_EQN),
best_set_reg(mpeval(PCI_E_EV_QUE_HEAD_ADDR
+PCI_E_EV_QUE_HEAD_STEP*INTR0x60_MSI_0_EQN),
intr0x60_handle_piu_msi_0_clear_int:
best_set_reg(mpeval(PCI_E_INT_CLEAR_ADDR
+(4+INTR0x60_MSI_0_EQN)*PCI_E_INT_CLEAR_STEP),
/* Include any extra MSI handler from the user that needs to be
* executed while the mondo busy flag is still asserted. */
/* The code can assume that %g1 is the thread,
#ifdef INTR0x60_MSI_0_EXTRA_HANDLER_WHILE_BUSY
intr0x60_handle_msi_0_extra_handler_while_busy:
INTR0x60_MSI_0_EXTRA_HANDLER_WHILE_BUSY
#endif /* INTR0x60_MSI_0_EXTRA_HANDLER_WHILE_BUSY */
intr0x60_handle_piu_msi_0_clear_mondo_busy:
best_set_reg(MONDO_INT_ABUSY, %g5, %g4)
/* Include any extra MSI handler from the user that needs to be
* executed while the event queue is disabled. */
/* The code can assume that %g1 is the thread,
#ifdef INTR0x60_MSI_EXTRA_HANDLER_WHILE_EQ_DISABLED
intr0x60_handle_msi_extra_handler_while_eq_disabled_0:
INTR0x60_MSI_EXTRA_HANDLER_WHILE_EQ_DISABLED
#endif /* INTR0x60_MSI_EXTRA_HANDLER_WHILE_EQ_DISABLED */
intr0x60_handle_piu_msi_0_enable_eq:
sllx %g4, 44, %g4 ! EN is bit 44
best_set_reg(mpeval(PCI_E_EV_QUE_CTL_SET_ADDR
+PCI_E_EV_QUE_CTL_SET_STEP*INTR0x60_MSI_0_EQN),
ba intr0x60_handle_msi_extra_handler
#endif /* INTR0x60_MSI_0_NUM */
#ifdef INTR0x60_MSI_1_NUM
/************ Handle MSI 1 ***********/
intr0x60_handle_piu_msi_1:
!WIP: /* Check whether this thread matches this INO */
!WIP: cmp %g1/*tid*/, INTR0x60_MONDO_XXX_THREAD
!WIP: bne intr0x60_handle_piu_bad_thread
/* Clear the interrupt */
intr0x60_handle_piu_msi_1_clear_eqwr:
sllx %g4, 62, %g4 ! EQWR_N is bit 62
best_set_reg(mpeval(PCI_E_MSI_CLEAR_ADDR
+PCI_E_MSI_CLEAR_STEP*INTR0x60_MSI_1_NUM),
stx %g4, [%g5] ! clear EQWR in MSI map reg.
intr0x60_handle_piu_msi_1_disable_eq:
sllx %g4, 44, %g4 ! DIS is bit 44
best_set_reg(mpeval(PCI_E_EV_QUE_CTL_CLEAR_ADDR
+PCI_E_EV_QUE_CTL_CLEAR_STEP*INTR0x60_MSI_1_EQN),
! Set Event Queue Head = Event Queue Tail
intr0x60_handle_piu_msi_1_reset_eq_head:
best_set_reg(mpeval(PCI_E_EV_QUE_TAIL_ADDR
+PCI_E_EV_QUE_TAIL_STEP*INTR0x60_MSI_1_EQN),
best_set_reg(mpeval(PCI_E_EV_QUE_HEAD_ADDR
+PCI_E_EV_QUE_HEAD_STEP*INTR0x60_MSI_1_EQN),
intr0x60_handle_piu_msi_1_clear_int:
best_set_reg(mpeval(PCI_E_INT_CLEAR_ADDR
+(4+INTR0x60_MSI_1_EQN)*PCI_E_INT_CLEAR_STEP),
/* Include any extra MSI handler from the user that needs to be
* executed while the mondo busy flag is still asserted. */
/* The code can assume that %g1 is the thread,
#ifdef INTR0x60_MSI_1_EXTRA_HANDLER_WHILE_BUSY
intr0x60_handle_msi_1_extra_handler_while_busy:
INTR0x60_MSI_1_EXTRA_HANDLER_WHILE_BUSY
#endif /* INTR0x60_MSI_1_EXTRA_HANDLER_WHILE_BUSY */
intr0x60_handle_piu_msi_1_clear_mondo_busy:
best_set_reg(MONDO_INT_ABUSY, %g5, %g4)
/* Include any extra MSI handler from the user that needs to be
* executed while the event queue is disabled. */
/* The code can assume that %g1 is the thread,
#ifdef INTR0x60_MSI_EXTRA_HANDLER_WHILE_EQ_DISABLED
intr0x60_handle_msi_extra_handler_while_eq_disabled_1:
INTR0x60_MSI_EXTRA_HANDLER_WHILE_EQ_DISABLED
#endif /* INTR0x60_MSI_EXTRA_HANDLER_WHILE_EQ_DISABLED */
intr0x60_handle_piu_msi_1_enable_eq:
sllx %g4, 44, %g4 ! EN is bit 44
best_set_reg(mpeval(PCI_E_EV_QUE_CTL_SET_ADDR
+PCI_E_EV_QUE_CTL_SET_STEP*INTR0x60_MSI_1_EQN),
ba intr0x60_handle_msi_extra_handler
#endif /* INTR0x60_MSI_1_NUM */
#ifdef INTR0x60_MSI_2_NUM
/************ Handle MSI 2 ***********/
intr0x60_handle_piu_msi_2:
!WIP: /* Check whether this thread matches this INO */
!WIP: cmp %g1/*tid*/, INTR0x60_MONDO_XXX_THREAD
!WIP: bne intr0x60_handle_piu_bad_thread
/* Clear the interrupt */
intr0x60_handle_piu_msi_2_clear_eqwr:
sllx %g4, 62, %g4 ! EQWR_N is bit 62
best_set_reg(mpeval(PCI_E_MSI_CLEAR_ADDR
+PCI_E_MSI_CLEAR_STEP*INTR0x60_MSI_2_NUM),
stx %g4, [%g5] ! clear EQWR in MSI map reg.
intr0x60_handle_piu_msi_2_disable_eq:
sllx %g4, 44, %g4 ! DIS is bit 44
best_set_reg(mpeval(PCI_E_EV_QUE_CTL_CLEAR_ADDR
+PCI_E_EV_QUE_CTL_CLEAR_STEP*INTR0x60_MSI_2_EQN),
! Set Event Queue Head = Event Queue Tail
intr0x60_handle_piu_msi_2_reset_eq_head:
best_set_reg(mpeval(PCI_E_EV_QUE_TAIL_ADDR
+PCI_E_EV_QUE_TAIL_STEP*INTR0x60_MSI_2_EQN),
best_set_reg(mpeval(PCI_E_EV_QUE_HEAD_ADDR
+PCI_E_EV_QUE_HEAD_STEP*INTR0x60_MSI_2_EQN),
intr0x60_handle_piu_msi_2_clear_int:
best_set_reg(mpeval(PCI_E_INT_CLEAR_ADDR
+(4+INTR0x60_MSI_2_EQN)*PCI_E_INT_CLEAR_STEP),
/* Include any extra MSI handler from the user that needs to be
* executed while the mondo busy flag is still asserted. */
/* The code can assume that %g1 is the thread,
#ifdef INTR0x60_MSI_2_EXTRA_HANDLER_WHILE_BUSY
intr0x60_handle_msi_2_extra_handler_while_busy:
INTR0x60_MSI_2_EXTRA_HANDLER_WHILE_BUSY
#endif /* INTR0x60_MSI_2_EXTRA_HANDLER_WHILE_BUSY */
intr0x60_handle_piu_msi_2_clear_mondo_busy:
best_set_reg(MONDO_INT_ABUSY, %g5, %g4)
/* Include any extra MSI handler from the user that needs to be
* executed while the event queue is disabled. */
/* The code can assume that %g1 is the thread,
#ifdef INTR0x60_MSI_EXTRA_HANDLER_WHILE_EQ_DISABLED
intr0x60_handle_msi_extra_handler_while_eq_disabled_2:
INTR0x60_MSI_EXTRA_HANDLER_WHILE_EQ_DISABLED
#endif /* INTR0x60_MSI_EXTRA_HANDLER_WHILE_EQ_DISABLED */
intr0x60_handle_piu_msi_2_enable_eq:
sllx %g4, 44, %g4 ! EN is bit 44
best_set_reg(mpeval(PCI_E_EV_QUE_CTL_SET_ADDR
+PCI_E_EV_QUE_CTL_SET_STEP*INTR0x60_MSI_2_EQN),
ba intr0x60_handle_msi_extra_handler
#endif /* INTR0x60_MSI_2_NUM */
#ifdef INTR0x60_MSI_3_NUM
/************ Handle MSI 3 ***********/
intr0x60_handle_piu_msi_3:
!WIP: /* Check whether this thread matches this INO */
!WIP: cmp %g1/*tid*/, INTR0x60_MONDO_XXX_THREAD
!WIP: bne intr0x60_handle_piu_bad_thread
/* Clear the interrupt */
intr0x60_handle_piu_msi_3_clear_eqwr:
sllx %g4, 62, %g4 ! EQWR_N is bit 62
best_set_reg(mpeval(PCI_E_MSI_CLEAR_ADDR
+PCI_E_MSI_CLEAR_STEP*INTR0x60_MSI_3_NUM),
stx %g4, [%g5] ! clear EQWR in MSI map reg.
intr0x60_handle_piu_msi_3_disable_eq:
sllx %g4, 44, %g4 ! DIS is bit 44
best_set_reg(mpeval(PCI_E_EV_QUE_CTL_CLEAR_ADDR
+PCI_E_EV_QUE_CTL_CLEAR_STEP*INTR0x60_MSI_3_EQN),
! Set Event Queue Head = Event Queue Tail
intr0x60_handle_piu_msi_3_reset_eq_head:
best_set_reg(mpeval(PCI_E_EV_QUE_TAIL_ADDR
+PCI_E_EV_QUE_TAIL_STEP*INTR0x60_MSI_3_EQN),
best_set_reg(mpeval(PCI_E_EV_QUE_HEAD_ADDR
+PCI_E_EV_QUE_HEAD_STEP*INTR0x60_MSI_3_EQN),
intr0x60_handle_piu_msi_3_clear_int:
best_set_reg(mpeval(PCI_E_INT_CLEAR_ADDR
+(4+INTR0x60_MSI_3_EQN)*PCI_E_INT_CLEAR_STEP),
/* Include any extra MSI handler from the user that needs to be
* executed while the mondo busy flag is still asserted. */
/* The code can assume that %g1 is the thread,
#ifdef INTR0x60_MSI_3_EXTRA_HANDLER_WHILE_BUSY
intr0x60_handle_msi_3_extra_handler_while_busy:
INTR0x60_MSI_3_EXTRA_HANDLER_WHILE_BUSY
#endif /* INTR0x60_MSI_3_EXTRA_HANDLER_WHILE_BUSY */
intr0x60_handle_piu_msi_3_clear_mondo_busy:
best_set_reg(MONDO_INT_ABUSY, %g5, %g4)
/* Include any extra MSI handler from the user that needs to be
* executed while the event queue is disabled. */
/* The code can assume that %g1 is the thread,
#ifdef INTR0x60_MSI_EXTRA_HANDLER_WHILE_EQ_DISABLED
intr0x60_handle_msi_extra_handler_while_eq_disabled_3:
INTR0x60_MSI_EXTRA_HANDLER_WHILE_EQ_DISABLED
#endif /* INTR0x60_MSI_EXTRA_HANDLER_WHILE_EQ_DISABLED */
intr0x60_handle_piu_msi_3_enable_eq:
sllx %g4, 44, %g4 ! EN is bit 44
best_set_reg(mpeval(PCI_E_EV_QUE_CTL_SET_ADDR
+PCI_E_EV_QUE_CTL_SET_STEP*INTR0x60_MSI_3_EQN),
ba intr0x60_handle_msi_extra_handler
#endif /* INTR0x60_MSI_3_NUM */
#ifdef INTR0x60_MSI_4_NUM
/************ Handle MSI 4 ***********/
intr0x60_handle_piu_msi_4:
!WIP: /* Check whether this thread matches this INO */
!WIP: cmp %g1/*tid*/, INTR0x60_MONDO_XXX_THREAD
!WIP: bne intr0x60_handle_piu_bad_thread
/* Clear the interrupt */
intr0x60_handle_piu_msi_4_clear_eqwr:
sllx %g4, 62, %g4 ! EQWR_N is bit 62
best_set_reg(mpeval(PCI_E_MSI_CLEAR_ADDR
+PCI_E_MSI_CLEAR_STEP*INTR0x60_MSI_4_NUM),
stx %g4, [%g5] ! clear EQWR in MSI map reg.
intr0x60_handle_piu_msi_4_disable_eq:
sllx %g4, 44, %g4 ! DIS is bit 44
best_set_reg(mpeval(PCI_E_EV_QUE_CTL_CLEAR_ADDR
+PCI_E_EV_QUE_CTL_CLEAR_STEP*INTR0x60_MSI_4_EQN),
! Set Event Queue Head = Event Queue Tail
intr0x60_handle_piu_msi_4_reset_eq_head:
best_set_reg(mpeval(PCI_E_EV_QUE_TAIL_ADDR
+PCI_E_EV_QUE_TAIL_STEP*INTR0x60_MSI_4_EQN),
best_set_reg(mpeval(PCI_E_EV_QUE_HEAD_ADDR
+PCI_E_EV_QUE_HEAD_STEP*INTR0x60_MSI_4_EQN),
intr0x60_handle_piu_msi_4_clear_int:
best_set_reg(mpeval(PCI_E_INT_CLEAR_ADDR
+(4+INTR0x60_MSI_4_EQN)*PCI_E_INT_CLEAR_STEP),
/* Include any extra MSI handler from the user that needs to be
* executed while the mondo busy flag is still asserted. */
/* The code can assume that %g1 is the thread,
#ifdef INTR0x60_MSI_4_EXTRA_HANDLER_WHILE_BUSY
intr0x60_handle_msi_4_extra_handler_while_busy:
INTR0x60_MSI_4_EXTRA_HANDLER_WHILE_BUSY
#endif /* INTR0x60_MSI_4_EXTRA_HANDLER_WHILE_BUSY */
intr0x60_handle_piu_msi_4_clear_mondo_busy:
best_set_reg(MONDO_INT_ABUSY, %g5, %g4)
/* Include any extra MSI handler from the user that needs to be
* executed while the event queue is disabled. */
/* The code can assume that %g1 is the thread,
#ifdef INTR0x60_MSI_EXTRA_HANDLER_WHILE_EQ_DISABLED
intr0x60_handle_msi_extra_handler_while_eq_disabled_4:
INTR0x60_MSI_EXTRA_HANDLER_WHILE_EQ_DISABLED
#endif /* INTR0x60_MSI_EXTRA_HANDLER_WHILE_EQ_DISABLED */
intr0x60_handle_piu_msi_4_enable_eq:
sllx %g4, 44, %g4 ! EN is bit 44
best_set_reg(mpeval(PCI_E_EV_QUE_CTL_SET_ADDR
+PCI_E_EV_QUE_CTL_SET_STEP*INTR0x60_MSI_4_EQN),
ba intr0x60_handle_msi_extra_handler
#endif /* INTR0x60_MSI_4_NUM */
#ifdef INTR0x60_MSI_5_NUM
/************ Handle MSI 5 ***********/
intr0x60_handle_piu_msi_5:
!WIP: /* Check whether this thread matches this INO */
!WIP: cmp %g1/*tid*/, INTR0x60_MONDO_XXX_THREAD
!WIP: bne intr0x60_handle_piu_bad_thread
/* Clear the interrupt */
intr0x60_handle_piu_msi_5_clear_eqwr:
sllx %g4, 62, %g4 ! EQWR_N is bit 62
best_set_reg(mpeval(PCI_E_MSI_CLEAR_ADDR
+PCI_E_MSI_CLEAR_STEP*INTR0x60_MSI_5_NUM),
stx %g4, [%g5] ! clear EQWR in MSI map reg.
intr0x60_handle_piu_msi_5_disable_eq:
sllx %g4, 44, %g4 ! DIS is bit 44
best_set_reg(mpeval(PCI_E_EV_QUE_CTL_CLEAR_ADDR
+PCI_E_EV_QUE_CTL_CLEAR_STEP*INTR0x60_MSI_5_EQN),
! Set Event Queue Head = Event Queue Tail
intr0x60_handle_piu_msi_5_reset_eq_head:
best_set_reg(mpeval(PCI_E_EV_QUE_TAIL_ADDR
+PCI_E_EV_QUE_TAIL_STEP*INTR0x60_MSI_5_EQN),
best_set_reg(mpeval(PCI_E_EV_QUE_HEAD_ADDR
+PCI_E_EV_QUE_HEAD_STEP*INTR0x60_MSI_5_EQN),
intr0x60_handle_piu_msi_5_clear_int:
best_set_reg(mpeval(PCI_E_INT_CLEAR_ADDR
+(4+INTR0x60_MSI_5_EQN)*PCI_E_INT_CLEAR_STEP),
/* Include any extra MSI handler from the user that needs to be
* executed while the mondo busy flag is still asserted. */
/* The code can assume that %g1 is the thread,
#ifdef INTR0x60_MSI_5_EXTRA_HANDLER_WHILE_BUSY
intr0x60_handle_msi_5_extra_handler_while_busy:
INTR0x60_MSI_5_EXTRA_HANDLER_WHILE_BUSY
#endif /* INTR0x60_MSI_5_EXTRA_HANDLER_WHILE_BUSY */
intr0x60_handle_piu_msi_5_clear_mondo_busy:
best_set_reg(MONDO_INT_ABUSY, %g5, %g4)
/* Include any extra MSI handler from the user that needs to be
* executed while the event queue is disabled. */
/* The code can assume that %g1 is the thread,
#ifdef INTR0x60_MSI_EXTRA_HANDLER_WHILE_EQ_DISABLED
intr0x60_handle_msi_extra_handler_while_eq_disabled_5:
INTR0x60_MSI_EXTRA_HANDLER_WHILE_EQ_DISABLED
#endif /* INTR0x60_MSI_EXTRA_HANDLER_WHILE_EQ_DISABLED */
intr0x60_handle_piu_msi_5_enable_eq:
sllx %g4, 44, %g4 ! EN is bit 44
best_set_reg(mpeval(PCI_E_EV_QUE_CTL_SET_ADDR
+PCI_E_EV_QUE_CTL_SET_STEP*INTR0x60_MSI_5_EQN),
ba intr0x60_handle_msi_extra_handler
#endif /* INTR0x60_MSI_5_NUM */
#ifdef INTR0x60_MSI_6_NUM
/************ Handle MSI 6 ***********/
intr0x60_handle_piu_msi_6:
!WIP: /* Check whether this thread matches this INO */
!WIP: cmp %g1/*tid*/, INTR0x60_MONDO_XXX_THREAD
!WIP: bne intr0x60_handle_piu_bad_thread
/* Clear the interrupt */
intr0x60_handle_piu_msi_6_clear_eqwr:
sllx %g4, 62, %g4 ! EQWR_N is bit 62
best_set_reg(mpeval(PCI_E_MSI_CLEAR_ADDR
+PCI_E_MSI_CLEAR_STEP*INTR0x60_MSI_6_NUM),
stx %g4, [%g5] ! clear EQWR in MSI map reg.
intr0x60_handle_piu_msi_6_disable_eq:
sllx %g4, 44, %g4 ! DIS is bit 44
best_set_reg(mpeval(PCI_E_EV_QUE_CTL_CLEAR_ADDR
+PCI_E_EV_QUE_CTL_CLEAR_STEP*INTR0x60_MSI_6_EQN),
! Set Event Queue Head = Event Queue Tail
intr0x60_handle_piu_msi_6_reset_eq_head:
best_set_reg(mpeval(PCI_E_EV_QUE_TAIL_ADDR
+PCI_E_EV_QUE_TAIL_STEP*INTR0x60_MSI_6_EQN),
best_set_reg(mpeval(PCI_E_EV_QUE_HEAD_ADDR
+PCI_E_EV_QUE_HEAD_STEP*INTR0x60_MSI_6_EQN),
intr0x60_handle_piu_msi_6_clear_int:
best_set_reg(mpeval(PCI_E_INT_CLEAR_ADDR
+(4+INTR0x60_MSI_6_EQN)*PCI_E_INT_CLEAR_STEP),
/* Include any extra MSI handler from the user that needs to be
* executed while the mondo busy flag is still asserted. */
/* The code can assume that %g1 is the thread,
#ifdef INTR0x60_MSI_6_EXTRA_HANDLER_WHILE_BUSY
intr0x60_handle_msi_6_extra_handler_while_busy:
INTR0x60_MSI_6_EXTRA_HANDLER_WHILE_BUSY
#endif /* INTR0x60_MSI_6_EXTRA_HANDLER_WHILE_BUSY */
intr0x60_handle_piu_msi_6_clear_mondo_busy:
best_set_reg(MONDO_INT_ABUSY, %g5, %g4)
/* Include any extra MSI handler from the user that needs to be
* executed while the event queue is disabled. */
/* The code can assume that %g1 is the thread,
#ifdef INTR0x60_MSI_EXTRA_HANDLER_WHILE_EQ_DISABLED
intr0x60_handle_msi_extra_handler_while_eq_disabled_6:
INTR0x60_MSI_EXTRA_HANDLER_WHILE_EQ_DISABLED
#endif /* INTR0x60_MSI_EXTRA_HANDLER_WHILE_EQ_DISABLED */
intr0x60_handle_piu_msi_6_enable_eq:
sllx %g4, 44, %g4 ! EN is bit 44
best_set_reg(mpeval(PCI_E_EV_QUE_CTL_SET_ADDR
+PCI_E_EV_QUE_CTL_SET_STEP*INTR0x60_MSI_6_EQN),
ba intr0x60_handle_msi_extra_handler
#endif /* INTR0x60_MSI_6_NUM */
#ifdef INTR0x60_MSI_7_NUM
/************ Handle MSI 7 ***********/
intr0x60_handle_piu_msi_7:
!WIP: /* Check whether this thread matches this INO */
!WIP: cmp %g1/*tid*/, INTR0x60_MONDO_XXX_THREAD
!WIP: bne intr0x60_handle_piu_bad_thread
/* Clear the interrupt */
intr0x60_handle_piu_msi_7_clear_eqwr:
sllx %g4, 62, %g4 ! EQWR_N is bit 62
best_set_reg(mpeval(PCI_E_MSI_CLEAR_ADDR
+PCI_E_MSI_CLEAR_STEP*INTR0x60_MSI_7_NUM),
stx %g4, [%g5] ! clear EQWR in MSI map reg.
intr0x60_handle_piu_msi_7_disable_eq:
sllx %g4, 44, %g4 ! DIS is bit 44
best_set_reg(mpeval(PCI_E_EV_QUE_CTL_CLEAR_ADDR
+PCI_E_EV_QUE_CTL_CLEAR_STEP*INTR0x60_MSI_7_EQN),
! Set Event Queue Head = Event Queue Tail
intr0x60_handle_piu_msi_7_reset_eq_head:
best_set_reg(mpeval(PCI_E_EV_QUE_TAIL_ADDR
+PCI_E_EV_QUE_TAIL_STEP*INTR0x60_MSI_7_EQN),
best_set_reg(mpeval(PCI_E_EV_QUE_HEAD_ADDR
+PCI_E_EV_QUE_HEAD_STEP*INTR0x60_MSI_7_EQN),
intr0x60_handle_piu_msi_7_clear_int:
best_set_reg(mpeval(PCI_E_INT_CLEAR_ADDR
+(4+INTR0x60_MSI_7_EQN)*PCI_E_INT_CLEAR_STEP),
/* Include any extra MSI handler from the user that needs to be
* executed while the mondo busy flag is still asserted. */
/* The code can assume that %g1 is the thread,
#ifdef INTR0x60_MSI_7_EXTRA_HANDLER_WHILE_BUSY
intr0x60_handle_msi_7_extra_handler_while_busy:
INTR0x60_MSI_7_EXTRA_HANDLER_WHILE_BUSY
#endif /* INTR0x60_MSI_7_EXTRA_HANDLER_WHILE_BUSY */
intr0x60_handle_piu_msi_7_clear_mondo_busy:
best_set_reg(MONDO_INT_ABUSY, %g5, %g4)
/* Include any extra MSI handler from the user that needs to be
* executed while the event queue is disabled. */
/* The code can assume that %g1 is the thread,
#ifdef INTR0x60_MSI_EXTRA_HANDLER_WHILE_EQ_DISABLED
intr0x60_handle_msi_extra_handler_while_eq_disabled_7:
INTR0x60_MSI_EXTRA_HANDLER_WHILE_EQ_DISABLED
#endif /* INTR0x60_MSI_EXTRA_HANDLER_WHILE_EQ_DISABLED */
intr0x60_handle_piu_msi_7_enable_eq:
sllx %g4, 44, %g4 ! EN is bit 44
best_set_reg(mpeval(PCI_E_EV_QUE_CTL_SET_ADDR
+PCI_E_EV_QUE_CTL_SET_STEP*INTR0x60_MSI_7_EQN),
ba intr0x60_handle_msi_extra_handler
#endif /* INTR0x60_MSI_7_NUM */
/* Include any extra MSI handler from the user */
/* The code can assume that %g1 is the thread,
intr0x60_handle_msi_extra_handler:
#ifdef INTR0x60_MSI_EXTRA_HANDLER
INTR0x60_MSI_EXTRA_HANDLER
#endif /* INTR0x60_MSI_EXTRA_HANDLER */
intr0x60_handle_piu_msi_retry:
/* Retry the instruction that was trapped */
#ifdef INTR0x60_PM_PME_EQN
/************ Handle PM_PME ***********/
intr0x60_handle_piu_pm_pme:
!WIP: /* Check whether this thread matches this INO */
!WIP: cmp %g1/*tid*/, INTR0x60_MONDO_XXX_THREAD
!WIP: bne intr0x60_handle_piu_bad_thread
/* Clear the interrupt */
intr0x60_handle_piu_pm_pme_disable_eq:
sllx %g4, 44, %g4 ! DIS is bit 44
best_set_reg(mpeval(PCI_E_EV_QUE_CTL_CLEAR_ADDR
+PCI_E_EV_QUE_CTL_CLEAR_STEP*INTR0x60_PM_PME_EQN),
! Set Event Queue Head = Event Queue Tail
intr0x60_handle_piu_pm_pme_reset_eq_head:
best_set_reg(mpeval(PCI_E_EV_QUE_TAIL_ADDR
+PCI_E_EV_QUE_TAIL_STEP*INTR0x60_PM_PME_EQN),
best_set_reg(mpeval(PCI_E_EV_QUE_HEAD_ADDR
+PCI_E_EV_QUE_HEAD_STEP*INTR0x60_PM_PME_EQN),
intr0x60_handle_piu_pm_pme_clear_int:
best_set_reg(mpeval(PCI_E_INT_CLEAR_ADDR
+(4+INTR0x60_PM_PME_EQN)*PCI_E_INT_CLEAR_STEP),
intr0x60_handle_piu_pm_pme_clear_mondo_busy:
best_set_reg(MONDO_INT_ABUSY, %g5, %g4)
/* Include any extra PM_PME handler from the user that needs to be
* executed while the event queue is disabled. */
/* The code can assume that %g1 is the thread,
#ifdef INTR0x60_PM_PME_EXTRA_HANDLER_WHILE_EQ_DISABLED
intr0x60_handle_pm_pme_extra_handler_while_eq_disabled:
INTR0x60_PM_PME_EXTRA_HANDLER_WHILE_EQ_DISABLED
#endif /* INTR0x60_PM_PME_EXTRA_HANDLER_WHILE_EQ_DISABLED */
intr0x60_handle_piu_pm_pme_enable_eq:
sllx %g4, 44, %g4 ! EN is bit 44
best_set_reg(mpeval(PCI_E_EV_QUE_CTL_SET_ADDR
+PCI_E_EV_QUE_CTL_SET_STEP*INTR0x60_PM_PME_EQN),
/* Include any extra PM_PME handler from the user */
/* The code can assume that %g1 is the thread,
intr0x60_handle_pm_pme_extra_handler:
#ifdef INTR0x60_PM_PME_EXTRA_HANDLER
INTR0x60_PM_PME_EXTRA_HANDLER
#endif /* INTR0x60_PM_PME_EXTRA_HANDLER */
intr0x60_handle_piu_pm_pme_retry:
/* Retry the instruction that was trapped */
#endif /* INTR0x60_PM_PME_EQN */
#ifdef INTR0x60_PME_TO_ACK_EQN
/************ Handle PME_TO_ACK ***********/
intr0x60_handle_piu_pme_to_ack:
!WIP: /* Check whether this thread matches this INO */
!WIP: cmp %g1/*tid*/, INTR0x60_MONDO_XXX_THREAD
!WIP: bne intr0x60_handle_piu_bad_thread
/* Clear the interrupt */
intr0x60_handle_piu_pme_to_ack_disable_eq:
sllx %g4, 44, %g4 ! DIS is bit 44
best_set_reg(mpeval(PCI_E_EV_QUE_CTL_CLEAR_ADDR
+PCI_E_EV_QUE_CTL_CLEAR_STEP*INTR0x60_PME_TO_ACK_EQN),
! Set Event Queue Head = Event Queue Tail
intr0x60_handle_piu_pme_to_ack_reset_eq_head:
best_set_reg(mpeval(PCI_E_EV_QUE_TAIL_ADDR
+PCI_E_EV_QUE_TAIL_STEP*INTR0x60_PME_TO_ACK_EQN),
best_set_reg(mpeval(PCI_E_EV_QUE_HEAD_ADDR
+PCI_E_EV_QUE_HEAD_STEP*INTR0x60_PME_TO_ACK_EQN),
intr0x60_handle_piu_pme_to_ack_clear_int:
best_set_reg(mpeval(PCI_E_INT_CLEAR_ADDR
+(4+INTR0x60_PME_TO_ACK_EQN)*PCI_E_INT_CLEAR_STEP),
intr0x60_handle_piu_pme_to_ack_clear_mondo_busy:
best_set_reg(MONDO_INT_ABUSY, %g5, %g4)
/* Include any extra PME_TO_ACK handler from the user that needs to be
* executed while the event queue is disabled. */
/* The code can assume that %g1 is the thread,
#ifdef INTR0x60_PME_TO_ACK_EXTRA_HANDLER_WHILE_EQ_DISABLED
intr0x60_handle_pme_to_ack_extra_handler_while_eq_disabled:
INTR0x60_PME_TO_ACK_EXTRA_HANDLER_WHILE_EQ_DISABLED
#endif /* INTR0x60_PME_TO_ACK_EXTRA_HANDLER_WHILE_EQ_DISABLED */
intr0x60_handle_piu_pme_to_ack_enable_eq:
sllx %g4, 44, %g4 ! EN is bit 44
best_set_reg(mpeval(PCI_E_EV_QUE_CTL_SET_ADDR
+PCI_E_EV_QUE_CTL_SET_STEP*INTR0x60_PME_TO_ACK_EQN),
/* Include any extra PME_TO_ACK handler from the user */
/* The code can assume that %g1 is the thread,
intr0x60_handle_pme_to_ack_extra_handler:
#ifdef INTR0x60_PME_TO_ACK_EXTRA_HANDLER
INTR0x60_PME_TO_ACK_EXTRA_HANDLER
#endif /* INTR0x60_PME_TO_ACK_EXTRA_HANDLER */
intr0x60_handle_piu_pme_to_ack_retry:
/* Retry the instruction that was trapped */
#endif /* INTR0x60_PME_TO_ACK_EQN */
intr0x60_handle_piu_bad_thread:
!$EV trig_pc_d(1, @VA(.HTRAPS.intr0x60_handle_piu_bad_thread)) -> printf("ERROR: Mondo delivered to wrong thread",*,1)
#endif /* INTR0x60_MONDO_IV */
#if (INTR0x60_SSI_ERR_IV != INTR0x60_BAD_IV)
/************************************************************************/
/* Handle SSI parity error interrupts */
!$EV trig_pc_d(1, @VA(.HTRAPS.intr0x60_handle_ssi_err)) -> printf("INFO: SSI parity error interrupt received",*,1)
/* Make sure that this thread is the right one */
best_set_reg(INTR0x60_SSI_ERR_THREAD, %g7, %g4)
bne intr0x60_handle_ssi_err_bad_thread
/* Include any extra SSI parity error handler from the user */
/* The code can assume that %g1 is the thread and %g2 is the vector */
#ifdef INTR0x60_SSI_ERR_EXTRA_HANDLER
intr0x60_handle_ssi_err_extra_handler:
INTR0x60_SSI_ERR_EXTRA_HANDLER
#endif /* INTR0x60_SSI_ERR_EXTRA_HANDLER */
intr0x60_handle_ssi_err_retry:
/* Retry the instruction that was trapped */
intr0x60_handle_ssi_err_bad_thread:
!$EV trig_pc_d(1, @VA(.HTRAPS.intr0x60_handle_ssi_err_bad_thread)) -> printf("ERROR: SSI parity error interrupt received on unexpected thread",*,1)
#endif /* (INTR0x60_SSI_ERR_IV != INTR0x60_BAD_IV) */
#if (INTR0x60_SSI_INT_IV != INTR0x60_BAD_IV)
/************************************************************************/
/* Handle SSI_EXT_INT_L interrupts */
!$EV trig_pc_d(1, @VA(.HTRAPS.intr0x60_handle_ssi_int)) -> printf("INFO: SSI_EXT_INT_L interrupt received",*,1)
/* Make sure that this thread is the right one */
best_set_reg(INTR0x60_SSI_INT_THREAD, %g7, %g4)
bne intr0x60_handle_ssi_int_bad_thread
/* Include any extra SSI_EXT_INT_L handler from the user */
/* The code can assume that %g1 is the thread and %g2 is the vector */
#ifdef INTR0x60_SSI_INT_EXTRA_HANDLER
intr0x60_handle_ssi_int_extra_handler:
INTR0x60_SSI_INT_EXTRA_HANDLER
#endif /* INTR0x60_SSI_INT_EXTRA_HANDLER */
intr0x60_handle_ssi_int_retry:
/* Retry the instruction that was trapped */
intr0x60_handle_ssi_int_bad_thread:
!$EV trig_pc_d(1, @VA(.HTRAPS.intr0x60_handle_ssi_int_bad_thread)) -> printf("ERROR: SSI_EXT_INT_L interrupt received on unexpected thread",*,1)
#endif /* (INTR0x60_SSI_INT_IV != INTR0x60_BAD_IV) */
* Need to have some tables to identify the source of the interrupt
* and whether it is expected for this thread.
* intr0x60_ivn_to_ig has one byte per interrupt vector number (0-63),
* which indicates the interrupt group, encoded as
#define INTR0x60_CC_IV_0_CHECK (INTR0x60_CC_IV_0 == `$1')
#define INTR0x60_CC_IV_0_CHECK (0)
#define INTR0x60_CC_IV_1_CHECK (INTR0x60_CC_IV_1 == `$1')
#define INTR0x60_CC_IV_1_CHECK (0)
#define INTR0x60_CC_IV_2_CHECK (INTR0x60_CC_IV_2 == `$1')
#define INTR0x60_CC_IV_2_CHECK (0)
#define INTR0x60_CC_IV_3_CHECK (INTR0x60_CC_IV_3 == `$1')
#define INTR0x60_CC_IV_3_CHECK (0)
#define INTR0x60_CC_IV_4_CHECK (INTR0x60_CC_IV_4 == `$1')
#define INTR0x60_CC_IV_4_CHECK (0)
#define INTR0x60_CC_IV_5_CHECK (INTR0x60_CC_IV_5 == `$1')
#define INTR0x60_CC_IV_5_CHECK (0)
#define INTR0x60_CC_IV_6_CHECK (INTR0x60_CC_IV_6 == `$1')
#define INTR0x60_CC_IV_6_CHECK (0)
#define INTR0x60_CC_IV_7_CHECK (INTR0x60_CC_IV_7 == `$1')
#define INTR0x60_CC_IV_7_CHECK (0)
#define INTR0x60_CC_IV_8_CHECK (INTR0x60_CC_IV_8 == `$1')
#define INTR0x60_CC_IV_8_CHECK (0)
#define INTR0x60_CC_IV_9_CHECK (INTR0x60_CC_IV_9 == `$1')
#define INTR0x60_CC_IV_9_CHECK (0)
#define INTR0x60_CC_IV_10_CHECK (INTR0x60_CC_IV_10 == `$1')
#define INTR0x60_CC_IV_10_CHECK (0)
#define INTR0x60_CC_IV_11_CHECK (INTR0x60_CC_IV_11 == `$1')
#define INTR0x60_CC_IV_11_CHECK (0)
#define INTR0x60_CC_IV_12_CHECK (INTR0x60_CC_IV_12 == `$1')
#define INTR0x60_CC_IV_12_CHECK (0)
#define INTR0x60_CC_IV_13_CHECK (INTR0x60_CC_IV_13 == `$1')
#define INTR0x60_CC_IV_13_CHECK (0)
#define INTR0x60_CC_IV_14_CHECK (INTR0x60_CC_IV_14 == `$1')
#define INTR0x60_CC_IV_14_CHECK (0)
#define INTR0x60_CC_IV_15_CHECK (INTR0x60_CC_IV_15 == `$1')
#define INTR0x60_CC_IV_15_CHECK (0)
#define INTR0x60_CC_IV_16_CHECK (INTR0x60_CC_IV_16 == `$1')
#define INTR0x60_CC_IV_16_CHECK (0)
#define INTR0x60_CC_IV_17_CHECK (INTR0x60_CC_IV_17 == `$1')
#define INTR0x60_CC_IV_17_CHECK (0)
#define INTR0x60_CC_IV_18_CHECK (INTR0x60_CC_IV_18 == `$1')
#define INTR0x60_CC_IV_18_CHECK (0)
#define INTR0x60_CC_IV_19_CHECK (INTR0x60_CC_IV_19 == `$1')
#define INTR0x60_CC_IV_19_CHECK (0)
#define INTR0x60_CC_IV_20_CHECK (INTR0x60_CC_IV_20 == `$1')
#define INTR0x60_CC_IV_20_CHECK (0)
#define INTR0x60_CC_IV_21_CHECK (INTR0x60_CC_IV_21 == `$1')
#define INTR0x60_CC_IV_21_CHECK (0)
#define INTR0x60_CC_IV_22_CHECK (INTR0x60_CC_IV_22 == `$1')
#define INTR0x60_CC_IV_22_CHECK (0)
#define INTR0x60_CC_IV_23_CHECK (INTR0x60_CC_IV_23 == `$1')
#define INTR0x60_CC_IV_23_CHECK (0)
#define INTR0x60_CC_IV_24_CHECK (INTR0x60_CC_IV_24 == `$1')
#define INTR0x60_CC_IV_24_CHECK (0)
#define INTR0x60_CC_IV_25_CHECK (INTR0x60_CC_IV_25 == `$1')
#define INTR0x60_CC_IV_25_CHECK (0)
#define INTR0x60_CC_IV_26_CHECK (INTR0x60_CC_IV_26 == `$1')
#define INTR0x60_CC_IV_26_CHECK (0)
#define INTR0x60_CC_IV_27_CHECK (INTR0x60_CC_IV_27 == `$1')
#define INTR0x60_CC_IV_27_CHECK (0)
#define INTR0x60_CC_IV_28_CHECK (INTR0x60_CC_IV_28 == `$1')
#define INTR0x60_CC_IV_28_CHECK (0)
#define INTR0x60_CC_IV_29_CHECK (INTR0x60_CC_IV_29 == `$1')
#define INTR0x60_CC_IV_29_CHECK (0)
#define INTR0x60_CC_IV_30_CHECK (INTR0x60_CC_IV_30 == `$1')
#define INTR0x60_CC_IV_30_CHECK (0)
#define INTR0x60_CC_IV_31_CHECK (INTR0x60_CC_IV_31 == `$1')
#define INTR0x60_CC_IV_31_CHECK (0)
#define INTR0x60_CC_IV_32_CHECK (INTR0x60_CC_IV_32 == `$1')
#define INTR0x60_CC_IV_32_CHECK (0)
#define INTR0x60_CC_IV_33_CHECK (INTR0x60_CC_IV_33 == `$1')
#define INTR0x60_CC_IV_33_CHECK (0)
#define INTR0x60_CC_IV_34_CHECK (INTR0x60_CC_IV_34 == `$1')
#define INTR0x60_CC_IV_34_CHECK (0)
#define INTR0x60_CC_IV_35_CHECK (INTR0x60_CC_IV_35 == `$1')
#define INTR0x60_CC_IV_35_CHECK (0)
#define INTR0x60_CC_IV_36_CHECK (INTR0x60_CC_IV_36 == `$1')
#define INTR0x60_CC_IV_36_CHECK (0)
#define INTR0x60_CC_IV_37_CHECK (INTR0x60_CC_IV_37 == `$1')
#define INTR0x60_CC_IV_37_CHECK (0)
#define INTR0x60_CC_IV_38_CHECK (INTR0x60_CC_IV_38 == `$1')
#define INTR0x60_CC_IV_38_CHECK (0)
#define INTR0x60_CC_IV_39_CHECK (INTR0x60_CC_IV_39 == `$1')
#define INTR0x60_CC_IV_39_CHECK (0)
#define INTR0x60_CC_IV_40_CHECK (INTR0x60_CC_IV_40 == `$1')
#define INTR0x60_CC_IV_40_CHECK (0)
#define INTR0x60_CC_IV_41_CHECK (INTR0x60_CC_IV_41 == `$1')
#define INTR0x60_CC_IV_41_CHECK (0)
#define INTR0x60_CC_IV_42_CHECK (INTR0x60_CC_IV_42 == `$1')
#define INTR0x60_CC_IV_42_CHECK (0)
#define INTR0x60_CC_IV_43_CHECK (INTR0x60_CC_IV_43 == `$1')
#define INTR0x60_CC_IV_43_CHECK (0)
#define INTR0x60_CC_IV_44_CHECK (INTR0x60_CC_IV_44 == `$1')
#define INTR0x60_CC_IV_44_CHECK (0)
#define INTR0x60_CC_IV_45_CHECK (INTR0x60_CC_IV_45 == `$1')
#define INTR0x60_CC_IV_45_CHECK (0)
#define INTR0x60_CC_IV_46_CHECK (INTR0x60_CC_IV_46 == `$1')
#define INTR0x60_CC_IV_46_CHECK (0)
#define INTR0x60_CC_IV_47_CHECK (INTR0x60_CC_IV_47 == `$1')
#define INTR0x60_CC_IV_47_CHECK (0)
#ifdef INTR0x60_NIU_RX_IV_0
#define INTR0x60_NIU_RX_IV_0_CHECK (INTR0x60_NIU_RX_IV_0 == `$1')
#define INTR0x60_NIU_RX_IV_0_CHECK (0)
#ifdef INTR0x60_NIU_RX_IV_1
#define INTR0x60_NIU_RX_IV_1_CHECK (INTR0x60_NIU_RX_IV_1 == `$1')
#define INTR0x60_NIU_RX_IV_1_CHECK (0)
#ifdef INTR0x60_NIU_RX_IV_2
#define INTR0x60_NIU_RX_IV_2_CHECK (INTR0x60_NIU_RX_IV_2 == `$1')
#define INTR0x60_NIU_RX_IV_2_CHECK (0)
#ifdef INTR0x60_NIU_RX_IV_3
#define INTR0x60_NIU_RX_IV_3_CHECK (INTR0x60_NIU_RX_IV_3 == `$1')
#define INTR0x60_NIU_RX_IV_3_CHECK (0)
#ifdef INTR0x60_NIU_RX_IV_4
#define INTR0x60_NIU_RX_IV_4_CHECK (INTR0x60_NIU_RX_IV_4 == `$1')
#define INTR0x60_NIU_RX_IV_4_CHECK (0)
#ifdef INTR0x60_NIU_RX_IV_5
#define INTR0x60_NIU_RX_IV_5_CHECK (INTR0x60_NIU_RX_IV_5 == `$1')
#define INTR0x60_NIU_RX_IV_5_CHECK (0)
#ifdef INTR0x60_NIU_RX_IV_6
#define INTR0x60_NIU_RX_IV_6_CHECK (INTR0x60_NIU_RX_IV_6 == `$1')
#define INTR0x60_NIU_RX_IV_6_CHECK (0)
#ifdef INTR0x60_NIU_RX_IV_7
#define INTR0x60_NIU_RX_IV_7_CHECK (INTR0x60_NIU_RX_IV_7 == `$1')
#define INTR0x60_NIU_RX_IV_7_CHECK (0)
#ifdef INTR0x60_NIU_RX_IV_8
#define INTR0x60_NIU_RX_IV_8_CHECK (INTR0x60_NIU_RX_IV_8 == `$1')
#define INTR0x60_NIU_RX_IV_8_CHECK (0)
#ifdef INTR0x60_NIU_RX_IV_9
#define INTR0x60_NIU_RX_IV_9_CHECK (INTR0x60_NIU_RX_IV_9 == `$1')
#define INTR0x60_NIU_RX_IV_9_CHECK (0)
#ifdef INTR0x60_NIU_RX_IV_10
#define INTR0x60_NIU_RX_IV_10_CHECK (INTR0x60_NIU_RX_IV_10 == `$1')
#define INTR0x60_NIU_RX_IV_10_CHECK (0)
#ifdef INTR0x60_NIU_RX_IV_11
#define INTR0x60_NIU_RX_IV_11_CHECK (INTR0x60_NIU_RX_IV_11 == `$1')
#define INTR0x60_NIU_RX_IV_11_CHECK (0)
#ifdef INTR0x60_NIU_RX_IV_12
#define INTR0x60_NIU_RX_IV_12_CHECK (INTR0x60_NIU_RX_IV_12 == `$1')
#define INTR0x60_NIU_RX_IV_12_CHECK (0)
#ifdef INTR0x60_NIU_RX_IV_13
#define INTR0x60_NIU_RX_IV_13_CHECK (INTR0x60_NIU_RX_IV_13 == `$1')
#define INTR0x60_NIU_RX_IV_13_CHECK (0)
#ifdef INTR0x60_NIU_RX_IV_14
#define INTR0x60_NIU_RX_IV_14_CHECK (INTR0x60_NIU_RX_IV_14 == `$1')
#define INTR0x60_NIU_RX_IV_14_CHECK (0)
#ifdef INTR0x60_NIU_RX_IV_15
#define INTR0x60_NIU_RX_IV_15_CHECK (INTR0x60_NIU_RX_IV_15 == `$1')
#define INTR0x60_NIU_RX_IV_15_CHECK (0)
#ifdef INTR0x60_NIU_TX_IV_0
#define INTR0x60_NIU_TX_IV_0_CHECK (INTR0x60_NIU_TX_IV_0 == `$1')
#define INTR0x60_NIU_TX_IV_0_CHECK (0)
#ifdef INTR0x60_NIU_TX_IV_1
#define INTR0x60_NIU_TX_IV_1_CHECK (INTR0x60_NIU_TX_IV_1 == `$1')
#define INTR0x60_NIU_TX_IV_1_CHECK (0)
#ifdef INTR0x60_NIU_TX_IV_2
#define INTR0x60_NIU_TX_IV_2_CHECK (INTR0x60_NIU_TX_IV_2 == `$1')
#define INTR0x60_NIU_TX_IV_2_CHECK (0)
#ifdef INTR0x60_NIU_TX_IV_3
#define INTR0x60_NIU_TX_IV_3_CHECK (INTR0x60_NIU_TX_IV_3 == `$1')
#define INTR0x60_NIU_TX_IV_3_CHECK (0)
#ifdef INTR0x60_NIU_TX_IV_4
#define INTR0x60_NIU_TX_IV_4_CHECK (INTR0x60_NIU_TX_IV_4 == `$1')
#define INTR0x60_NIU_TX_IV_4_CHECK (0)
#ifdef INTR0x60_NIU_TX_IV_5
#define INTR0x60_NIU_TX_IV_5_CHECK (INTR0x60_NIU_TX_IV_5 == `$1')
#define INTR0x60_NIU_TX_IV_5_CHECK (0)
#ifdef INTR0x60_NIU_TX_IV_6
#define INTR0x60_NIU_TX_IV_6_CHECK (INTR0x60_NIU_TX_IV_6 == `$1')
#define INTR0x60_NIU_TX_IV_6_CHECK (0)
#ifdef INTR0x60_NIU_TX_IV_7
#define INTR0x60_NIU_TX_IV_7_CHECK (INTR0x60_NIU_TX_IV_7 == `$1')
#define INTR0x60_NIU_TX_IV_7_CHECK (0)
#ifdef INTR0x60_NIU_TX_IV_8
#define INTR0x60_NIU_TX_IV_8_CHECK (INTR0x60_NIU_TX_IV_8 == `$1')
#define INTR0x60_NIU_TX_IV_8_CHECK (0)
#ifdef INTR0x60_NIU_TX_IV_9
#define INTR0x60_NIU_TX_IV_9_CHECK (INTR0x60_NIU_TX_IV_9 == `$1')
#define INTR0x60_NIU_TX_IV_9_CHECK (0)
#ifdef INTR0x60_NIU_TX_IV_10
#define INTR0x60_NIU_TX_IV_10_CHECK (INTR0x60_NIU_TX_IV_10 == `$1')
#define INTR0x60_NIU_TX_IV_10_CHECK (0)
#ifdef INTR0x60_NIU_TX_IV_11
#define INTR0x60_NIU_TX_IV_11_CHECK (INTR0x60_NIU_TX_IV_11 == `$1')
#define INTR0x60_NIU_TX_IV_11_CHECK (0)
#ifdef INTR0x60_NIU_TX_IV_12
#define INTR0x60_NIU_TX_IV_12_CHECK (INTR0x60_NIU_TX_IV_12 == `$1')
#define INTR0x60_NIU_TX_IV_12_CHECK (0)
#ifdef INTR0x60_NIU_TX_IV_13
#define INTR0x60_NIU_TX_IV_13_CHECK (INTR0x60_NIU_TX_IV_13 == `$1')
#define INTR0x60_NIU_TX_IV_13_CHECK (0)
#ifdef INTR0x60_NIU_TX_IV_14
#define INTR0x60_NIU_TX_IV_14_CHECK (INTR0x60_NIU_TX_IV_14 == `$1')
#define INTR0x60_NIU_TX_IV_14_CHECK (0)
#ifdef INTR0x60_NIU_TX_IV_15
#define INTR0x60_NIU_TX_IV_15_CHECK (INTR0x60_NIU_TX_IV_15 == `$1')
#define INTR0x60_NIU_TX_IV_15_CHECK (0)
#if (INTR0x60_SSI_ERR_IV != INTR0x60_BAD_IV)
#define INTR0x60_SSI_ERR_IV_CHECK (INTR0x60_SSI_ERR_IV == `$1')
#define INTR0x60_SSI_ERR_IV_CHECK (0)
#if (INTR0x60_SSI_INT_IV != INTR0x60_BAD_IV)
#define INTR0x60_SSI_INT_IV_CHECK (INTR0x60_SSI_INT_IV == `$1')
#define INTR0x60_SSI_INT_IV_CHECK (0)
#define INTR0x60_MONDO_IV_CHECK (INTR0x60_MONDO_IV == `$1')
#define INTR0x60_MONDO_IV_CHECK (0)
/* Note: Need to put INTR0x60_IG_* names on a separate line
* because the *_CHECK macros may contain a half-quote which
* would prevent cpp from doing the macro replacement */
define(`INTR0x60_IVN_TO_IG',
`ifelse(eval( INTR0x60_CC_IV_0_CHECK
|| INTR0x60_CC_IV_1_CHECK
|| INTR0x60_CC_IV_2_CHECK
|| INTR0x60_CC_IV_3_CHECK
|| INTR0x60_CC_IV_4_CHECK
|| INTR0x60_CC_IV_5_CHECK
|| INTR0x60_CC_IV_6_CHECK
|| INTR0x60_CC_IV_7_CHECK
|| INTR0x60_CC_IV_8_CHECK
|| INTR0x60_CC_IV_9_CHECK
|| INTR0x60_CC_IV_10_CHECK
|| INTR0x60_CC_IV_11_CHECK
|| INTR0x60_CC_IV_12_CHECK
|| INTR0x60_CC_IV_13_CHECK
|| INTR0x60_CC_IV_14_CHECK
|| INTR0x60_CC_IV_15_CHECK
|| INTR0x60_CC_IV_16_CHECK
|| INTR0x60_CC_IV_17_CHECK
|| INTR0x60_CC_IV_18_CHECK
|| INTR0x60_CC_IV_19_CHECK
|| INTR0x60_CC_IV_20_CHECK
|| INTR0x60_CC_IV_21_CHECK
|| INTR0x60_CC_IV_22_CHECK
|| INTR0x60_CC_IV_23_CHECK
|| INTR0x60_CC_IV_24_CHECK
|| INTR0x60_CC_IV_25_CHECK
|| INTR0x60_CC_IV_26_CHECK
|| INTR0x60_CC_IV_27_CHECK
|| INTR0x60_CC_IV_28_CHECK
|| INTR0x60_CC_IV_29_CHECK
|| INTR0x60_CC_IV_30_CHECK
|| INTR0x60_CC_IV_31_CHECK
|| INTR0x60_CC_IV_32_CHECK
|| INTR0x60_CC_IV_33_CHECK
|| INTR0x60_CC_IV_34_CHECK
|| INTR0x60_CC_IV_35_CHECK
|| INTR0x60_CC_IV_36_CHECK
|| INTR0x60_CC_IV_37_CHECK
|| INTR0x60_CC_IV_38_CHECK
|| INTR0x60_CC_IV_39_CHECK
|| INTR0x60_CC_IV_40_CHECK
|| INTR0x60_CC_IV_41_CHECK
|| INTR0x60_CC_IV_42_CHECK
|| INTR0x60_CC_IV_43_CHECK
|| INTR0x60_CC_IV_44_CHECK
|| INTR0x60_CC_IV_45_CHECK
|| INTR0x60_CC_IV_46_CHECK
|| INTR0x60_CC_IV_47_CHECK), 1,
eval( INTR0x60_SSI_ERR_IV_CHECK ), 1,
eval( INTR0x60_SSI_INT_IV_CHECK ), 1,
eval( INTR0x60_MONDO_IV_CHECK ), 1,
eval( INTR0x60_NIU_RX_IV_0_CHECK
|| INTR0x60_NIU_RX_IV_1_CHECK
|| INTR0x60_NIU_RX_IV_2_CHECK
|| INTR0x60_NIU_RX_IV_3_CHECK
|| INTR0x60_NIU_RX_IV_4_CHECK
|| INTR0x60_NIU_RX_IV_5_CHECK
|| INTR0x60_NIU_RX_IV_6_CHECK
|| INTR0x60_NIU_RX_IV_7_CHECK
|| INTR0x60_NIU_RX_IV_8_CHECK
|| INTR0x60_NIU_RX_IV_9_CHECK
|| INTR0x60_NIU_RX_IV_10_CHECK
|| INTR0x60_NIU_RX_IV_11_CHECK
|| INTR0x60_NIU_RX_IV_12_CHECK
|| INTR0x60_NIU_RX_IV_13_CHECK
|| INTR0x60_NIU_RX_IV_14_CHECK
|| INTR0x60_NIU_RX_IV_15_CHECK), 1,
eval( INTR0x60_NIU_TX_IV_0_CHECK
|| INTR0x60_NIU_TX_IV_1_CHECK
|| INTR0x60_NIU_TX_IV_2_CHECK
|| INTR0x60_NIU_TX_IV_3_CHECK
|| INTR0x60_NIU_TX_IV_4_CHECK
|| INTR0x60_NIU_TX_IV_5_CHECK
|| INTR0x60_NIU_TX_IV_6_CHECK
|| INTR0x60_NIU_TX_IV_7_CHECK
|| INTR0x60_NIU_TX_IV_8_CHECK
|| INTR0x60_NIU_TX_IV_9_CHECK
|| INTR0x60_NIU_TX_IV_10_CHECK
|| INTR0x60_NIU_TX_IV_11_CHECK
|| INTR0x60_NIU_TX_IV_12_CHECK
|| INTR0x60_NIU_TX_IV_13_CHECK
|| INTR0x60_NIU_TX_IV_14_CHECK
|| INTR0x60_NIU_TX_IV_15_CHECK), 1,
.byte INTR0x60_IVN_TO_IG(0)
.byte INTR0x60_IVN_TO_IG(1)
.byte INTR0x60_IVN_TO_IG(2)
.byte INTR0x60_IVN_TO_IG(3)
.byte INTR0x60_IVN_TO_IG(4)
.byte INTR0x60_IVN_TO_IG(5)
.byte INTR0x60_IVN_TO_IG(6)
.byte INTR0x60_IVN_TO_IG(7)
.byte INTR0x60_IVN_TO_IG(8)
.byte INTR0x60_IVN_TO_IG(9)
.byte INTR0x60_IVN_TO_IG(10)
.byte INTR0x60_IVN_TO_IG(11)
.byte INTR0x60_IVN_TO_IG(12)
.byte INTR0x60_IVN_TO_IG(13)
.byte INTR0x60_IVN_TO_IG(14)
.byte INTR0x60_IVN_TO_IG(15)
.byte INTR0x60_IVN_TO_IG(16)
.byte INTR0x60_IVN_TO_IG(17)
.byte INTR0x60_IVN_TO_IG(18)
.byte INTR0x60_IVN_TO_IG(19)
.byte INTR0x60_IVN_TO_IG(20)
.byte INTR0x60_IVN_TO_IG(21)
.byte INTR0x60_IVN_TO_IG(22)
.byte INTR0x60_IVN_TO_IG(23)
.byte INTR0x60_IVN_TO_IG(24)
.byte INTR0x60_IVN_TO_IG(25)
.byte INTR0x60_IVN_TO_IG(26)
.byte INTR0x60_IVN_TO_IG(27)
.byte INTR0x60_IVN_TO_IG(28)
.byte INTR0x60_IVN_TO_IG(29)
.byte INTR0x60_IVN_TO_IG(30)
.byte INTR0x60_IVN_TO_IG(31)
.byte INTR0x60_IVN_TO_IG(32)
.byte INTR0x60_IVN_TO_IG(33)
.byte INTR0x60_IVN_TO_IG(34)
.byte INTR0x60_IVN_TO_IG(35)
.byte INTR0x60_IVN_TO_IG(36)
.byte INTR0x60_IVN_TO_IG(37)
.byte INTR0x60_IVN_TO_IG(38)
.byte INTR0x60_IVN_TO_IG(39)
.byte INTR0x60_IVN_TO_IG(40)
.byte INTR0x60_IVN_TO_IG(41)
.byte INTR0x60_IVN_TO_IG(42)
.byte INTR0x60_IVN_TO_IG(43)
.byte INTR0x60_IVN_TO_IG(44)
.byte INTR0x60_IVN_TO_IG(45)
.byte INTR0x60_IVN_TO_IG(46)
.byte INTR0x60_IVN_TO_IG(47)
.byte INTR0x60_IVN_TO_IG(48)
.byte INTR0x60_IVN_TO_IG(49)
.byte INTR0x60_IVN_TO_IG(50)
.byte INTR0x60_IVN_TO_IG(51)
.byte INTR0x60_IVN_TO_IG(52)
.byte INTR0x60_IVN_TO_IG(53)
.byte INTR0x60_IVN_TO_IG(54)
.byte INTR0x60_IVN_TO_IG(55)
.byte INTR0x60_IVN_TO_IG(56)
.byte INTR0x60_IVN_TO_IG(57)
.byte INTR0x60_IVN_TO_IG(58)
.byte INTR0x60_IVN_TO_IG(59)
.byte INTR0x60_IVN_TO_IG(60)
.byte INTR0x60_IVN_TO_IG(61)
.byte INTR0x60_IVN_TO_IG(62)
.byte INTR0x60_IVN_TO_IG(63)
undefine(`INTR0x60_IVN_TO_IG')dnl
projects / OpenSPARC-T2-DV / blob