* ========== Copyright Header Begin ==========================================
* OpenSPARC T2 Processor File: old_boot.s
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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* ========== Copyright Header End ============================================
SECTION .RED TEXT_VA = 0xfffffffff0000000
! Nothing appears in position 0
! Clean out %g1 and reset CCR
! Making room for boot sequence longer than 7 instructions
Externally_Initiated_Reset:
Software_Initiated_Reset:
ldxa [%g0] ASI_LSU_CONTROL, %g6
! Set lsu_control_reg.im (bit 2 in ASI 0x45, VA 0x0)
#endif /* ACTIVATE_ITLB */
stxa %g6, [%g0] ASI_LSU_CONTROL
! Reset trap level to not be MAXTL
! Reset Global level to 0
! Set up Partition IDs for each thread
! For MT MMU diags to work. Set partition ID
wr %g0, ASI_CORE_ID, %asi
ldxa [ASI_CORE_ID_VA] %asi, %g1
mov ASI_PARTITION_ID_VAL, %g2
stxa %g1, [%g2] ASI_PARTITION_ID
stxa %g2, [%g0] ASI_LSU_CONTROL
! Power Management - set full power throttle mode ..
stxa %g2, [%g0] ASI_SPARC_PWR_MGMT
! Set translation for HTBA trap table
! Write it to itlb_tag_access register
stxa %i0, [%i1 + %g0] 0x50
! Field V NFO L PA IE E CP P W Size
! Bit 63 62 61 39:13 12 11 10 8 6 2:0
! First set valid and locked bits
setx 0xA000000000000000, %l1, %i2
setx 0x000000FFFFFFE000, %l1, %i5
! Write it to itlb_data_in register
stxa %i2, [%i3 + %g0] 0x54
! Set translation for tl>0 portion of HTBA trap table
! Write it to itlb_tag_access register
stxa %i0, [%i1 + %g0] 0x50
! Field V NFO L PA IE E CP P W Size
! Bit 63 62 61 39:13 12 11 10 8 6 2:0
! First set valid and locked bits
! Also set page size large enough to cover whole table (bits 14 to 0)
! Need page size of 64 KB (2**16)
setx 0xA000000000000000, %l1, %i2
!setx 0xA000000000000001, %l1, %i2
setx 0x000000FFFFFFE000, %l1, %i5
! Write it to itlb_data_in register
stxa %i2, [%i3 + %g0] 0x54
! Use "-midas_args=-DENABLE_ITLB" on the command line to activate ITLB
! Now activate translation
! Reset HPSTATE.ENB (bit 11)
! Set lsu_control_reg.im (bit 2 in ASI 0x45, VA 0x0)
ldxa [%g0] ASI_LSU_CONTROL, %i6
stxa %i6, [%g0] ASI_LSU_CONTROL
! Use "-midas_args=-DENABLE_DTLB" on the command line to activate DTLB
! Now activate translation
! Reset HPSTATE.ENB (bit 11)
! Set lsu_control_reg.dm (bit 3 in ASI 0x45, VA 0x0)
ldxa [%g0] ASI_LSU_CONTROL, %i6
stxa %i6, [%g0] ASI_LSU_CONTROL
! $ NO EV trig_pc_d(1,@VA(.RED.end_of_boot)) -> marker(bootEnd, *, 1)
setx DIAG_TEXT_AREA, %g1, %g2
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
SECTION .HTRAPTABLE TEXT_VA = HTBA
hexternally_initiated_reset:
hsoftware_initiatied_reset:
hinstruction_access_exception:
hinstruction_access_MMU_miss:
hinstruction_access_error:
hinternal_processor_error:
lddf_mem_address_not_aligned:
stdf_mem_address_not_aligned:
hfast_instruction_access_MMU_miss:
! Assume context of 0 for now
! First get missing VA from itlb_tag_access
ldxa [%g1 + %g0] 0x50, %g4
! Field V NFO L PA IE E CP P W Size
! Bit 63 62 61 39:13 12 11 10 8 6 2:0
! Now set up PA [39:13] only
! Write it to itlb_data_in register
stxa %g2, [%g3 + %g0] 0x54
hfast_data_access_MMU_miss:
! Assume context of 0 for now
! First get missing VA from dtlb_tag_access
ldxa [%g1 + %g0] 0x58, %g4
! Field V NFO L PA IE E CP P W Size
! Bit 63 62 61 39:13 12 11 10 8 6 2:0
! Set cacheable in physical and writable bit
! Now set up PA [39:13] only
! Write it to dtlb_data_in register
stxa %g2, [%g3 + %g0] 0x5C
! Function to read thread ID from the
! Thread Status register.
! Value is returned in %o1.
wr %g0, ASI_CORE_ID, %asi
ldxa [ASI_CORE_ID_VA] %asi, %o1
wr %g0, %g1, %asi ! restore %asi
! Function to read thread ID from the
! Thread Status register.
! Value is returned in %o1.
wr %g0, ASI_CORE_ID, %asi
ldxa [ASI_CORE_ID_VA] %asi, %o1
wr %g0, %g1, %asi ! restore %asi
hinterrupt_vector_trap_tl_gt_0:
hfast_instruction_access_MMU_miss_tl_gt_0:
ba hfast_instruction_access_MMU_miss
SECTION .MAIN TEXT_VA = DIAG_TEXT_AREA, DATA_VA=DIAG_DATA_AREA
projects / OpenSPARC-T2-DV / blob