verif/diag/assembly/include/peu_init_dtm.h

/*
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*
* OpenSPARC T2 Processor File: peu_init_dtm.h
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! Per DH suggestion, before any PIO access to PCI-E addr space, need to setup
! Base and Mask registers in NCU.  Copied the code below from ./peu_init.h
!       - AT, 02/28/06

#include "peu_defines.h"
#include "dmu_peu_regs.h"

!
! Set up the Base and Mask registers in the NCU to enable PIO reads and writes
!
        setx    MEM32_OFFSET_BASE_REG_ADDR, %g2, %g3            ! 0x8000002000
        setx    MEM32_OFFSET_BASE_REG_DATA, %g2, %g4
        stx     %g4, [%g3]

        !setx    MEM32_OFFSET_MASK_REG_ADDR, %g2, %g3           ! 0x8000002008
        setx    MEM32_OFFSET_MASK_REG_DATA, %g2, %g4
        stx     %g4, [%g3 + 0x8]

        !setx    MEM64_OFFSET_BASE_REG_ADDR, %g2, %g3           ! 0x8000002010
        setx    MEM64_OFFSET_BASE_REG_DATA, %g2, %g4
        stx     %g4, [%g3 + 0x10]

        !setx    MEM64_OFFSET_MASK_REG_ADDR, %g2, %g3           ! 0x8000002018
        setx    MEM64_OFFSET_MASK_REG_DATA, %g2, %g4
        stx     %g4, [%g3 + 0x18]

        !setx    IOCFG_OFFSET_BASE_REG_ADDR, %g2, %g3           ! 0x8000002020
        setx    IOCFG_OFFSET_BASE_REG_DATA, %g2, %g4
        stx     %g4, [%g3 + 0x20]

        !setx    IOCFG_OFFSET_MASK_REG_ADDR, %g2, %g3           ! 0x8000002028
        setx    IOCFG_OFFSET_MASK_REG_DATA, %g2, %g4
        stx     %g4, [%g3 + 0x28]

        ! Load the PCIE MEM64 OFFSET Register (and pio deadlock mode bits)

        setx    FIRE_DLC_IMU_ICS_CSR_A_MEM_64_PCIE_OFFSET_REG_ADDR, %g2, %g3
#ifndef PEU_PIO_MODE
#define PCIE_MEM64_OFFSET_PLUS_PIO_MODE   PCIE_MEM64_OFFSET
#else
#define PCIE_MEM64_OFFSET_PLUS_PIO_MODE   mpeval(PCIE_MEM64_OFFSET | (PEU_PIO_MODE & 3))
#endif
        setx    PCIE_MEM64_OFFSET_PLUS_PIO_MODE, %g2, %g4
        stx     %g4, [%g3]

!       ! enable bypass in IOMMU

!       setx    FIRE_DLC_MMU_CSR_A_CTL_ADDR, %g2, %g3
!       mov     FIRE_DLC_MMU_CSR_A_CTL__BYPASS_EN, %g4
!       stx     %g4, [%g3]