Initial commit of OpenSPARC T2 design and verification files.

[OpenSPARC-T2-DV] / verif / diag / assembly / include / tlu_custom_intr_handlers.s

/*
* ========== Copyright Header Begin ==========================================
* 
* OpenSPARC T2 Processor File: tlu_custom_intr_handlers.s
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
*
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
*
* For the avoidance of doubt, and except that if any non-GPL license 
* choice is available it will apply instead, Sun elects to use only 
* the General Public License version 2 (GPLv2) at this time for any 
* software where a choice of GPL license versions is made 
* available with the language indicating that GPLv2 or any later version 
* may be used, or where a choice of which version of the GPL is applied is 
* otherwise unspecified. 
*
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* CA 95054 USA or visit www.sun.com if you need additional information or 
* have any questions. 
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* ========== Copyright Header End ============================================
*/
#ifndef INT_HANDLER_RAND4_1
#define INT_HANDLER_RAND4_1 retry; nop; nop; nop
#endif
#ifndef INT_HANDLER_RAND7_1
#define INT_HANDLER_RAND7_1  retry; nop; nop; nop ; nop; nop; nop
#endif
#ifndef INT_HANDLER_RAND4_2
#define INT_HANDLER_RAND4_2 retry; nop; nop; nop
#endif
#ifndef INT_HANDLER_RAND7_2
#define INT_HANDLER_RAND7_2 retry; nop; nop; nop ; nop; nop; nop
#endif
#ifndef INT_HANDLER_RAND4_3
#define INT_HANDLER_RAND4_3 retry; nop; nop; nop
#endif
#ifndef INT_HANDLER_RAND7_3
#define INT_HANDLER_RAND7_3 retry; nop; nop; nop ; nop; nop; nop
#endif
#define H_HT0_Externally_Initiated_Reset_0x03
#define SUN_H_HT0_Externally_Initiated_Reset_0x03 \
   ldxa    [%g0] ASI_LSU_CTL_REG, %g1; \
   set cregs_lsu_ctl_reg_r64, %g1; \
   stxa    %g1, [%g0] ASI_LSU_CTL_REG; \
   retry;nop

#define My_External_Reset \
   ldxa    [%g0] ASI_LSU_CTL_REG, %l5; \
   set cregs_lsu_ctl_reg_r64, %l5; \
   stxa    %l5, [%g0] ASI_LSU_CTL_REG; \
   retry;nop
   
!!!!! SPU Interrupt Handlers

#define H_HT0_Control_Word_Queue_Interrupt_0x3c
#define My_HT0_Control_Word_Queue_Interrupt_0x3c \
       INT_HANDLER_RAND7_1 ;\
       retry ; 

#define H_HT0_Modular_Arithmetic_Interrupt_0x3d
#define My_H_HT0_Modular_Arithmetic_Interrupt_0x3d \
       INT_HANDLER_RAND7_2 ;\
       retry ; 


!!!!! HW interrupt handlers

#define H_HT0_Interrupt_0x60
#define My_HT0_Interrupt_0x60 \
   ldxa    [%g0] ASI_SWVR_INTR_RECEIVE, %g5 ;\
   ldxa    [%g0] ASI_SWVR_INTR_R, %g4 ;\
   ldxa    [%g0] ASI_SWVR_INTR_RECEIVE, %g3 ;\
   INT_HANDLER_RAND4_1 ;\
   retry;

!!!!! Queue interrupt handler


#define H_T0_Cpu_Mondo_Trap_0x7c
#define My_T0_Cpu_Mondo_Trap_0x7c \
       mov     0x3c8, %g3; \
       ldxa    [%g3] 0x25, %g5; \
       mov     0x3c0, %g3; \
       stxa    %g5, [%g3] 0x25; \
       retry; \
       nop; \
       nop; \
       nop
       
#define H_T0_Dev_Mondo_Trap_0x7d
#define My_T0_Dev_Mondo_Trap_0x7d \
       mov     0x3d8, %g3; \
       ldxa    [%g3] 0x25, %g5; \
       mov     0x3d0, %g3; \
       stxa    %g5, [%g3] 0x25; \
       retry; \
       nop; \
       nop; \
       nop
       
#define H_T0_Resumable_Error_0x7e
#define My_T0_Resumable_Error_0x7e \
       mov     0x3e8, %g3; \
       ldxa    [%g3] 0x25, %g5; \
       mov     0x3e0, %g3; \
       stxa    %g5, [%g3] 0x25; \
       retry; \
       nop; \
       nop; \
       nop

#define H_T1_Cpu_Mondo_Trap_0x7c
#define My_T1_Cpu_Mondo_Trap_0x7c \
       mov     0x3c8, %g3; \
       ldxa    [%g3] 0x25, %g5; \
       mov     0x3c0, %g3; \
       stxa    %g5, [%g3] 0x25; \
       retry; \
       nop; \
       nop; \
       nop
       
#define H_T1_Dev_Mondo_Trap_0x7d
#define My_T1_Dev_Mondo_Trap_0x7d \
       mov     0x3d8, %g3; \
       ldxa    [%g3] 0x25, %g5; \
       mov     0x3d0, %g3; \
       stxa    %g5, [%g3] 0x25; \
       retry; \
       nop; \
       nop; \
       nop
       
#define H_T1_Resumable_Error_0x7e
#define My_T1_Resumable_Error_0x7e \
       mov     0x3e8, %g3; \
       ldxa    [%g3] 0x25, %g5; \
       mov     0x3e0, %g3; \
       stxa    %g5, [%g3] 0x25; \
       retry; \
       nop; \
       nop; \
       nop

#define H_HT0_Reserved_0x7c
#define SUN_H_HT0_Reserved_0x7c \
       mov     0x3c8, %g3; \
       ldxa    [%g3] 0x25, %g5; \
       mov     0x3c0, %g3; \
       stxa    %g5, [%g3] 0x25; \
       retry; \
       nop; \
       nop; \
       nop
       
#define H_HT0_Reserved_0x7d
#define SUN_H_HT0_Reserved_0x7d \
       mov     0x3d8, %g3; \
       ldxa    [%g3] 0x25, %g5; \
       mov     0x3d0, %g3; \
       stxa    %g5, [%g3] 0x25; \
       retry; \
       nop; \
       nop; \
       nop
       
#define H_HT0_Reserved_0x7e
#define SUN_H_HT0_Reserved_0x7e \
       mov     0x3e8, %g3; \
       ldxa    [%g3] 0x25, %g5; \
       mov     0x3e0, %g3; \
       stxa    %g5, [%g3] 0x25; \
       retry; \
       nop; \
       nop; \
       nop


!!!!! Hstick-match trap handler


#define H_T0_Reserved_0x5e
#define My_T0_Reserved_0x5e \
       rdhpr   %hintp, %g3; \
       wrhpr   %g3, %g3, %hintp; \
       retry; \
       nop; \
       nop; \
       nop; \
       nop; \
       nop

#define H_HT0_Hstick_Match_0x5e
#define My_HT0_Hstick_Match_0x5e \
       rdhpr   %hintp, %g3; \
       wrhpr   %g3, %g3, %hintp; \
       retry; \
       nop; \
       nop; \
       nop; \
       nop; \
       nop

#define H_T0_Reserved_0x5e
#define My_T0_Reserved_0x5e \
       rdhpr   %hintp, %g3; \
       wrhpr   %g3, %g3, %hintp; \
       retry; \
       nop; \
       nop; \
       nop; \
       nop; \
       nop

#define H_T1_Reserved_0x5e
#define My_T1_Reserved_0x5e \
       rdhpr   %hintp, %g3; \
       wrhpr   %g3, %g3, %hintp; \
       retry; \
       nop; \
       nop; \
       nop; \
       nop; \
       nop


!!!!! SW interuupt handlers


#define H_T0_Interrupt_Level_14_0x4e
#define My_T0_Interrupt_Level_14_0x4e \
       rd      %softint, %g3; \
       sethi   %hi(0x14000), %g3; \
       or      %g3, 0x1, %g3; \
       wr      %g3, %g0, %clear_softint; \
   rd %tick, %g3 ;\
       retry; \

#define H_T0_Interrupt_Level_1_0x41
#define My_T0_Interrupt_Level_1_0x41 \
       rd      %softint, %g3; \
       or      %g0, 0x2, %g3; \
       wr      %g3, %g0, %clear_softint; \
       retry; \
       nop; \
       nop; \
       nop; \
       nop

#define H_T0_Interrupt_Level_2_0x42
#define My_T0_Interrupt_Level_2_0x42 \
       rd      %softint, %g3; \
       or      %g0, 0x4, %g3; \
       wr      %g3, %g0, %clear_softint; \
       retry; \
       nop; \
       nop; \
       nop; \
       nop

#define H_T0_Interrupt_Level_3_0x43
#define My_T0_Interrupt_Level_3_0x43 \
       rd      %softint, %g3; \
       or      %g0, 0x8, %g3; \
       wr      %g3, %g0, %clear_softint; \
       retry; \
       nop; \
       nop; \
       nop; \
       nop

#define H_T0_Interrupt_Level_4_0x44
#define My_T0_Interrupt_Level_4_0x44 \
       rd      %softint, %g3; \
       or      %g0, 0x10, %g3; \
       wr      %g3, %g0, %clear_softint; \
       retry; \
       nop; \
       nop; \
       nop; \
       nop

#define H_T0_Interrupt_Level_5_0x45
#define My_T0_Interrupt_Level_5_0x45 \
       rd      %softint, %g3; \
       or      %g0, 0x20, %g3; \
       wr      %g3, %g0, %clear_softint; \
       retry; \
       nop; \
       nop; \
       nop; \
       nop

#define H_T0_Interrupt_Level_6_0x46
#define My_T0_Interrupt_Level_6_0x46 \
       rd      %softint, %g3; \
       or      %g0, 0x40, %g3; \
       wr      %g3, %g0, %clear_softint; \
       retry; \
       nop; \
       nop; \
       nop; \
       nop

#define H_T0_Interrupt_Level_7_0x47
#define My_T0_Interrupt_Level_7_0x47 \
       rd      %softint, %g3; \
       or      %g0, 0x80, %g3; \
       wr      %g3, %g0, %clear_softint; \
       retry; \
       nop; \
       nop; \
       nop; \
       nop

#define H_T0_Interrupt_Level_8_0x48
#define My_T0_Interrupt_Level_8_0x48 \
       rd      %softint, %g3; \
       or      %g0, 0x100, %g3; \
       wr      %g3, %g0, %clear_softint; \
       retry; \
       nop; \
       nop; \
       nop; \
       nop

#define H_T0_Interrupt_Level_9_0x49
#define My_T0_Interrupt_Level_9_0x49 \
       rd      %softint, %g3; \
       or      %g0, 0x200, %g3; \
       wr      %g3, %g0, %clear_softint; \
       retry; \
       nop; \
       nop; \
       nop; \
       nop

#define H_T0_Interrupt_Level_10_0x4a
#define My_T0_Interrupt_Level_10_0x4a \
       rd      %softint, %g3; \
       or      %g0, 0x400, %g3; \
       wr      %g3, %g0, %clear_softint; \
       retry; \
       nop; \
       nop; \
       nop; \
       nop

#define H_T0_Interrupt_Level_11_0x4b
#define My_T0_Interrupt_Level_11_0x4b \
       rd      %softint, %g3; \
       or      %g0, 0x800, %g3; \
       wr      %g3, %g0, %clear_softint; \
       retry; \
       nop; \
       nop; \
       nop; \
       nop

#define H_T0_Interrupt_Level_12_0x4c
#define My_T0_Interrupt_Level_12_0x4c \
       rd      %softint, %g3; \
       sethi   %hi(0x1000), %g3; \
       wr      %g3, %g0, %clear_softint; \
       retry; \
       nop; \
       nop; \
       nop; \
       nop

#define H_T0_Interrupt_Level_13_0x4d
#define My_T0_Interrupt_Level_13_0x4d \
       rd      %softint, %g3; \
       sethi   %hi(0x2000), %g3; \
       wr      %g3, %g0, %clear_softint; \
       retry; \
       nop; \
       nop; \
       nop; \
       nop

#define H_T0_Interrupt_Level_15_0x4f
#define My_T0_Interrupt_Level_15_0x4f \
      sethi   %hi(0x8000), %g3; \
      wr  %g3, %g0, %clear_softint; \
      wr %g0, %g0, %pic;\
      sethi %hi(0x80040000), %g2;\
      rd %pcr, %g3;\
      andn %g3, %g2, %g3;\
      wr %g3, %g0, %pcr;\
      retry; 

#define H_T1_Interrupt_Level_14_0x4e
#define My_T1_Interrupt_Level_14_0x4e \
       rd      %softint, %g3; \
       sethi   %hi(0x14000), %g3; \
       or      %g3, 0x1, %g3; \
       wr      %g3, %g0, %clear_softint; \
   rd %tick, %g3 ;\
       retry; \

#define H_T1_Interrupt_Level_1_0x41
#define My_T1_Interrupt_Level_1_0x41 \
       rd      %softint, %g3; \
       or      %g0, 0x2, %g3; \
       wr      %g3, %g0, %clear_softint; \
       retry; \
       nop; \
       nop; \
       nop; \
       nop

#define H_T1_Interrupt_Level_2_0x42
#define My_T1_Interrupt_Level_2_0x42 \
       rd      %softint, %g3; \
       or      %g0, 0x4, %g3; \
       wr      %g3, %g0, %clear_softint; \
       retry; \
       nop; \
       nop; \
       nop; \
       nop

#define H_T1_Interrupt_Level_3_0x43
#define My_T1_Interrupt_Level_3_0x43 \
       rd      %softint, %g3; \
       or      %g0, 0x8, %g3; \
       wr      %g3, %g0, %clear_softint; \
       retry; \
       nop; \
       nop; \
       nop; \
       nop

#define H_T1_Interrupt_Level_4_0x44
#define My_T1_Interrupt_Level_4_0x44 \
       rd      %softint, %g3; \
       or      %g0, 0x10, %g3; \
       wr      %g3, %g0, %clear_softint; \
       retry; \
       nop; \
       nop; \
       nop; \
       nop

#define H_T1_Interrupt_Level_5_0x45
#define My_T1_Interrupt_Level_5_0x45 \
       rd      %softint, %g3; \
       or      %g0, 0x20, %g3; \
       wr      %g3, %g0, %clear_softint; \
       retry; \
       nop; \
       nop; \
       nop; \
       nop

#define H_T1_Interrupt_Level_6_0x46
#define My_T1_Interrupt_Level_6_0x46 \
       rd      %softint, %g3; \
       or      %g0, 0x40, %g3; \
       wr      %g3, %g0, %clear_softint; \
       retry; \
       nop; \
       nop; \
       nop; \
       nop

#define H_T1_Interrupt_Level_7_0x47
#define My_T1_Interrupt_Level_7_0x47 \
       rd      %softint, %g3; \
       or      %g0, 0x80, %g3; \
       wr      %g3, %g0, %clear_softint; \
       retry; \
       nop; \
       nop; \
       nop; \
       nop

#define H_T1_Interrupt_Level_8_0x48
#define My_T1_Interrupt_Level_8_0x48 \
       rd      %softint, %g3; \
       or      %g0, 0x100, %g3; \
       wr      %g3, %g0, %clear_softint; \
       retry; \
       nop; \
       nop; \
       nop; \
       nop

#define H_T1_Interrupt_Level_9_0x49
#define My_T1_Interrupt_Level_9_0x49 \
       rd      %softint, %g3; \
       or      %g0, 0x200, %g3; \
       wr      %g3, %g0, %clear_softint; \
       retry; \
       nop; \
       nop; \
       nop; \
       nop

#define H_T1_Interrupt_Level_10_0x4a
#define My_T1_Interrupt_Level_10_0x4a \
       rd      %softint, %g3; \
       or      %g0, 0x400, %g3; \
       wr      %g3, %g0, %clear_softint; \
       retry; \
       nop; \
       nop; \
       nop; \
       nop

#define H_T1_Interrupt_Level_11_0x4b
#define My_T1_Interrupt_Level_11_0x4b \
       rd      %softint, %g3; \
       or      %g0, 0x800, %g3; \
       wr      %g3, %g0, %clear_softint; \
       retry; \
       nop; \
       nop; \
       nop; \
       nop

#define H_T1_Interrupt_Level_12_0x4c
#define My_T1_Interrupt_Level_12_0x4c \
       rd      %softint, %g3; \
       sethi   %hi(0x1000), %g3; \
       wr      %g3, %g0, %clear_softint; \
       retry; \
       nop; \
       nop; \
       nop; \
       nop

#define H_T1_Interrupt_Level_13_0x4d
#define My_T1_Interrupt_Level_13_0x4d \
       rd      %softint, %g3; \
       sethi   %hi(0x2000), %g3; \
       wr      %g3, %g0, %clear_softint; \
       retry; \
       nop; \
       nop; \
       nop; \
       nop

#define H_T1_Interrupt_Level_15_0x4f
#define My_T1_Interrupt_Level_15_0x4f \
      sethi   %hi(0x8000), %g3; \
      wr  %g3, %g0, %clear_softint; \
      wr %g0, %g0, %pic;\
      sethi %hi(0x80040000), %g2;\
      rd %pcr, %g3;\
      andn %g3, %g2, %g3;\
      wr %g3, %g0, %pcr;\
      retry; 

#define H_HT0_Interrupt_Level_14_0x4e
#define My_HT0_Interrupt_Level_14_0x4e \
       rd      %softint, %g3; \
       sethi   %hi(0x14000), %g3; \
       or      %g3, 0x1, %g3; \
       wr      %g3, %g0, %clear_softint; \
   rd %tick, %g3 ;\
   sub %g3, 0x80, %g3;\
   wrpr %g3, %g0, %tick;\
       retry; \

#define H_HT0_Interrupt_Level_1_0x41
#define My_HT0_Interrupt_Level_1_0x41 \
       rd      %softint, %g3; \
       or      %g0, 0x2, %g3; \
       wr      %g3, %g0, %clear_softint; \
       retry; \
       nop; \
       nop; \
       nop; \
       nop

#define H_HT0_Interrupt_Level_2_0x42
#define My_HT0_Interrupt_Level_2_0x42 \
       rd      %softint, %g3; \
       or      %g0, 0x4, %g3; \
       wr      %g3, %g0, %clear_softint; \
       retry; \
       nop; \
       nop; \
       nop; \
       nop

#define H_HT0_Interrupt_Level_3_0x43
#define My_HT0_Interrupt_Level_3_0x43 \
       rd      %softint, %g3; \
       or      %g0, 0x8, %g3; \
       wr      %g3, %g0, %clear_softint; \
       retry; \
       nop; \
       nop; \
       nop; \
       nop

#define H_HT0_Interrupt_Level_4_0x44
#define My_HT0_Interrupt_Level_4_0x44 \
       rd      %softint, %g3; \
       or      %g0, 0x10, %g3; \
       wr      %g3, %g0, %clear_softint; \
       retry; \
       nop; \
       nop; \
       nop; \
       nop

#define H_HT0_Interrupt_Level_5_0x45
#define My_HT0_Interrupt_Level_5_0x45 \
       rd      %softint, %g3; \
       or      %g0, 0x20, %g3; \
       wr      %g3, %g0, %clear_softint; \
       retry; \
       nop; \
       nop; \
       nop; \
       nop

#define H_HT0_Interrupt_Level_6_0x46
#define My_HT0_Interrupt_Level_6_0x46 \
       rd      %softint, %g3; \
       or      %g0, 0x40, %g3; \
       wr      %g3, %g0, %clear_softint; \
       retry; \
       nop; \
       nop; \
       nop; \
       nop

#define H_HT0_Interrupt_Level_7_0x47
#define My_HT0_Interrupt_Level_7_0x47 \
       rd      %softint, %g3; \
       or      %g0, 0x80, %g3; \
       wr      %g3, %g0, %clear_softint; \
       retry; \
       nop; \
       nop; \
       nop; \
       nop

#define H_HT0_Interrupt_Level_8_0x48
#define My_HT0_Interrupt_Level_8_0x48 \
       rd      %softint, %g3; \
       or      %g0, 0x100, %g3; \
       wr      %g3, %g0, %clear_softint; \
       retry; \
       nop; \
       nop; \
       nop; \
       nop

#define H_HT0_Interrupt_Level_9_0x49
#define My_HT0_Interrupt_Level_9_0x49 \
       rd      %softint, %g3; \
       or      %g0, 0x200, %g3; \
       wr      %g3, %g0, %clear_softint; \
       retry; \
       nop; \
       nop; \
       nop; \
       nop

#define H_HT0_Interrupt_Level_10_0x4a
#define My_HT0_Interrupt_Level_10_0x4a \
       rd      %softint, %g3; \
       or      %g0, 0x400, %g3; \
       wr      %g3, %g0, %clear_softint; \
       retry; \
       nop; \
       nop; \
       nop; \
       nop

#define H_HT0_Interrupt_Level_11_0x4b
#define My_HT0_Interrupt_Level_11_0x4b \
       rd      %softint, %g3; \
       or      %g0, 0x800, %g3; \
       wr      %g3, %g0, %clear_softint; \
       retry; \
       nop; \
       nop; \
       nop; \
       nop

#define H_HT0_Interrupt_Level_12_0x4c
#define My_HT0_Interrupt_Level_12_0x4c \
       rd      %softint, %g3; \
       sethi   %hi(0x1000), %g3; \
       wr      %g3, %g0, %clear_softint; \
       retry; \
       nop; \
       nop; \
       nop; \
       nop

#define H_HT0_Interrupt_Level_13_0x4d
#define My_HT0_Interrupt_Level_13_0x4d \
       rd      %softint, %g3; \
       sethi   %hi(0x2000), %g3; \
       wr      %g3, %g0, %clear_softint; \
       retry; \
       nop; \
       nop; \
       nop; \
       nop

#define H_HT0_Interrupt_Level_15_0x4f
#define My_HT0_Interrupt_Level_15_0x4f \
      sethi   %hi(0x8000), %g3; \
      wr  %g3, %g0, %clear_softint; \
      wr %g0, %g0, %pic;\
      sethi %hi(0x80040000), %g2;\
      rd %pcr, %g3;\
      andn %g3, %g2, %g3;\
      wr %g3, %g0, %pcr;\
      retry; 


!!!!!!!!!!!!!!!!!!!!!! END of all handlers !!!!!!!!!!!!!!!!!!!