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* OpenSPARC T2 Processor File: isa3_mmu_htw_3.s
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#define PART0_Z_HWTEN_0 1
#define PART0_Z_HWTEN_1 1
#define PART0_Z_HWTEN_2 1
#define PART0_Z_HWTEN_3 1
#define PART0_NZ_HWTEN_0 1
#define PART0_NZ_HWTEN_1 1
#define PART0_NZ_HWTEN_2 1
#define PART0_NZ_HWTEN_3 1
!!! RANOTPA = 1, so RA -> PA translation enabled
#define PART0_Z_RANOTPA_0 1
#define PART0_Z_RANOTPA_1 1
#define PART0_Z_RANOTPA_2 1
#define PART0_Z_RANOTPA_3 1
#define PART0_NZ_RANOTPA_0 1
#define PART0_NZ_RANOTPA_1 1
#define PART0_NZ_RANOTPA_2 1
#define PART0_NZ_RANOTPA_3 1
/************************************************************************
************************************************************************/
! Set translation for miss handler
!setx DIAG_DATA_AREA, %l1, %i4
!! Zero out lower 13 bits
!! Write it to dtlb_tag_access register
!stxa %i0, [%i1 + %g0] 0x58
!! Create tte_data in %i2
!! Field V NFO L PA IE E CP P W Size
!! Bit 63 62 61 39:13 12 11 10 8 6 2:0
!! First set valid and locked bits
!setx 0xA000000000000000, %l1, %i2
!setx 0x000000FFFFFFE000, %l1, %i5
!! Write it to dtlb_data_in register
!! ASI 0x5C, address with bit 10 set (for sun4v)
!stxa %i2, [%i3 + %g0] 0x5C
!! Assume context of 0 for now
!! Zero out lower 13 bits
!! Write it to itlb_tag_access register
!stxa %i0, [%i1 + %g0] 0x50
!! Create tte_data in %i2
!! Field V NFO L PA IE E CP P W Size
!! Bit 63 62 61 39:13 12 11 10 8 6 2:0
!setx 0x8000000000000000, %l1, %i2
!setx 0x000000FFFFFFE000, %l1, %i5
!! Write it to itlb_data_in register
!! ASI 0x54, address with bit 10 set (for sun4v)
!stxa %i2, [%i3 + %g0] 0x54
! Now activate translation
! Reset HPSTATE.ENB (bit 11)
!! Set lsu_control_reg.dm (bit 3 in ASI 0x45, VA 0x0)
!stxa %i6, [%g0 + %g0] 0x45
! Fetch and execute some stuff...
setx MAIN_BASE_DATA_VA, %i1, %l7
EXIT_GOOD /* test finish */
/************************************************************************
************************************************************************/