verif/diag/assembly/peu/PCIeDMARdAdr32.s

/*
* ========== Copyright Header Begin ==========================================
*
* OpenSPARC T2 Processor File: PCIeDMARdAdr32.s
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
*
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
*
* For the avoidance of doubt, and except that if any non-GPL license
* choice is available it will apply instead, Sun elects to use only
* the General Public License version 2 (GPLv2) at this time for any
* software where a choice of GPL license versions is made
* available with the language indicating that GPLv2 or any later version
* may be used, or where a choice of which version of the GPL is applied is
* otherwise unspecified.
*
* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
* CA 95054 USA or visit www.sun.com if you need additional information or
* have any questions.
*
*
* ========== Copyright Header End ============================================
*/
#define ENABLE_PCIE_LINK_TRAINING
#define ENABLE_PCIE_MPS_512
#define MAIN_PAGE_HV_ALSO

#include "hboot.s"
#include "peu_defines.h"

#define MEM32_WR_ADDR              mpeval(N2_PCIE_BASE_ADDR + MEM32_OFFSET_BASE_REG_DATA)

#define DMA_DATA_ADDR              0x007f0000

#define DMA_ADDR_1                 mpeval(DMA_DATA_ADDR + 0*256, 16, 16)
#define DMA_ADDR_2                 mpeval(DMA_DATA_ADDR + 1*256, 16, 16)

#define IOMMU_TTE_ADDR             0x40000000

! Bit 8 = Page Size: 0=8KB, 1=64KB;  Bits 3:0 = TSB Table size: 6=64k entries
#define MMU_TSB_CNTRL_REG_DATA     mpeval(IOMMU_TTE_ADDR | 0x100 | 6)


/************************************************************************
   Test case code start
 ************************************************************************/
.text
.global main

main:
        ta T_CHANGE_HPRIV
        nop

! enable SUN4U translation in the IOMMU

        setx    FIRE_DLC_MMU_CSR_A_CTL_ADDR, %g1, %g2
        setx    0x00301, %g1, %g3       ! 9:8 11 = Cache enabled, 0: 1 = translation enabled
        stx     %g3, [%g2]
        ldx     [%g2], %g3

! load address of the TSB table, and the page size (64KB)

        setx    FIRE_DLC_MMU_CSR_A_TSB_ADDR, %g1, %g2
        setx    MMU_TSB_CNTRL_REG_DATA, %g1, %g3
        stx     %g3, [%g2]
        ldx     [%g2], %g3

! Trigger some DMA Reads of various lengths

Xmt1:   nop         ! $EV trig_pc_d(1, @VA(.MAIN.Xmt1)) -> EnablePCIeIgCmd ("DMARD", DMA_ADDR_1, DMA_ADDR_2, "64'h1", 1 )
        nop
        nop
Xmt2:   nop         ! $EV trig_pc_d(1, @VA(.MAIN.Xmt2)) -> EnablePCIeIgCmd ("DMARD", DMA_ADDR_1, DMA_ADDR_2, "64'h2", 1 )
        nop
        nop
Xmt3:   nop         ! $EV trig_pc_d(1, @VA(.MAIN.Xmt3)) -> EnablePCIeIgCmd ("DMARD", DMA_ADDR_1, DMA_ADDR_2, "64'h3", 1 )
        nop
        nop
Xmt4:   nop         ! $EV trig_pc_d(1, @VA(.MAIN.Xmt4)) -> EnablePCIeIgCmd ("DMARD", DMA_ADDR_1, DMA_ADDR_2, "64'h4", 1 )
        nop
        nop
Xmt5:   nop         ! $EV trig_pc_d(1, @VA(.MAIN.Xmt5)) -> EnablePCIeIgCmd ("DMARD", DMA_ADDR_1, DMA_ADDR_2, "64'h3f", 1 )
        nop
        nop
Xmt6:   nop         ! $EV trig_pc_d(1, @VA(.MAIN.Xmt6)) -> EnablePCIeIgCmd ("DMARD", DMA_ADDR_1, DMA_ADDR_2, "64'h40", 1 )
        nop
        nop
Xmt7:   nop         ! $EV trig_pc_d(1, @VA(.MAIN.Xmt7)) -> EnablePCIeIgCmd ("DMARD", DMA_ADDR_1, DMA_ADDR_2, "64'h41", 1 )
        nop
        nop
Xmt8:   nop         ! $EV trig_pc_d(1, @VA(.MAIN.Xmt8)) -> EnablePCIeIgCmd ("DMARD", DMA_ADDR_1, DMA_ADDR_2, "64'h7f", 1 )
        nop
        nop
Xmt9:   nop         ! $EV trig_pc_d(1, @VA(.MAIN.Xmt9)) -> EnablePCIeIgCmd ("DMARD", DMA_ADDR_1, DMA_ADDR_2, "64'h80", 1 )
        nop
        nop
Xmt10:  nop         ! $EV trig_pc_d(1, @VA(.MAIN.Xmt10)) -> EnablePCIeIgCmd ("DMARD", DMA_ADDR_1, DMA_ADDR_2, "64'h81", 1 )
        nop
        nop
Xmt11:  nop         ! $EV trig_pc_d(1, @VA(.MAIN.Xmt11)) -> EnablePCIeIgCmd ("DMARD", DMA_ADDR_1, DMA_ADDR_2, "64'hff", 1 )
        nop
        nop
Xmt12:  nop         ! $EV trig_pc_d(1, @VA(.MAIN.Xmt12)) -> EnablePCIeIgCmd ("DMARD", DMA_ADDR_1, DMA_ADDR_2, "64'h100", 1 )
        nop
        nop
Xmt13:  nop         ! $EV trig_pc_d(1, @VA(.MAIN.Xmt13)) -> EnablePCIeIgCmd ("DMARD", DMA_ADDR_1, DMA_ADDR_2, "64'h101", 1 )
        nop
        nop
Xmt14:  nop         ! $EV trig_pc_d(1, @VA(.MAIN.Xmt14)) -> EnablePCIeIgCmd ("DMARD", DMA_ADDR_1, DMA_ADDR_2, "64'h1ff", 1 )
        nop
        nop
Xmt15:  nop         ! $EV trig_pc_d(1, @VA(.MAIN.Xmt15)) -> EnablePCIeIgCmd ("DMARD", DMA_ADDR_1, DMA_ADDR_2, "64'h200", 1 )
        nop
        nop
Xmt16:  nop         ! $EV trig_pc_d(1, @VA(.MAIN.Xmt16)) -> EnablePCIeIgCmd ("DMARD", DMA_ADDR_1, DMA_ADDR_2, "64'h400", 1 )
        nop
        nop
Xmt17:  nop         ! $EV trig_pc_d(1, @VA(.MAIN.Xmt17)) -> EnablePCIeIgCmd ("DMARD", DMA_ADDR_1, DMA_ADDR_2, "64'h800", 1 )
        nop
        nop
Xmt18:  nop         ! $EV trig_pc_d(1, @VA(.MAIN.Xmt18)) -> EnablePCIeIgCmd ("DMARD", DMA_ADDR_1, DMA_ADDR_2, "64'h1000", 1 )
        nop
        nop
        nop

        ! select a MEM32 address in PCI address range and transmit the command to NCU

        setx    MEM32_WR_ADDR, %g1, %g2
        setx    0x040, %g1, %g4         ! loop 64 times

delay_loop:
        stx     %g2, [%g2]              ! MEM32 PIO Write
        ldx     [%g2], %l0              ! MEM32 PIO READ
        add     %g2, 8, %g2             ! increment PIO  address

        dec     %g4                     ! decrement counter
        brnz    %g4, delay_loop         ! loop if not zero
        nop


test_passed:
        EXIT_GOOD

test_failed:
        EXIT_BAD


/************************************************************************
   Test case data start. Need to set up known data to check on DMA completions
************************************************************************/

SECTION       .DATA DATA_VA=DMA_DATA_ADDR
attr_data {
      Name = .DATA,
      hypervisor,
      compressimage
}
.data
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/************************************************************************
   IOMMU TTE start
        TTE Format:
63:     48 DEV KEY      - set to 0
47:     39 reserved     - set to 0
38:     13 DATA PA      - set to VA for VA=RA
12:     7  DATA_SOFT    - set to 0
6:      5  reserved     - set to 0
5:      3  FNM MASK     - set to 0
2:      2  KEY VALID    - set to 0
1:      1  DATA_W       - set to 1
0:      0  DATA_V       - set to 1
************************************************************************/

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        .xword 0x00000000008e0003
        .xword 0x00000000008f0003


/************************************************************************/