* ========== Copyright Header Begin ==========================================
* OpenSPARC T2 Processor File: spc_isa2mt_fail_fc_9.s
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
* For the avoidance of doubt, and except that if any non-GPL license
* choice is available it will apply instead, Sun elects to use only
* the General Public License version 2 (GPLv2) at this time for any
* software where a choice of GPL license versions is made
* available with the language indicating that GPLv2 or any later version
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* CA 95054 USA or visit www.sun.com if you need additional information or
* ========== Copyright Header End ============================================
.ident "FOCUSCASE: focus.pm,v 1.1 2003/04/23 17:53:39 somePerson Exp somePerson $ ./spc_basic_isa2.pl FOCUS_SEED=508719961"
.ident "BY somePerson ON Mon Aug 4 10:32:26 CDT 2003"
.ident "Using Instruction Hash for Focus :$Id: spc_isa2mt_fail_fc_9.s,v 1.3 2007/07/05 22:02:07 drp Exp $"
/************************************************************************
************************************************************************/
setx DIAG_DATA_AREA, %g1, %g3
!# Initialize registers ..
INIT_TH_FP_REG(%l7, %f0, 0x55555555aaaaaaaa)
INIT_TH_FP_REG(%l7, %f2, 0xaaaaaaaa55555555)
INIT_TH_FP_REG(%l7, %f4, 0xfedcba9876543210)
INIT_TH_FP_REG(%l7, %f6, 0x0123456789abcdef)
INIT_TH_FP_REG(%l7, %f8, 0x55aa55aaff00ff00)
INIT_TH_FP_REG(%l7, %f10, 0x1111111111111111)
INIT_TH_FP_REG(%l7, %f12, 0x8888888888888888)
INIT_TH_FP_REG(%l7, %f14, 0xfedcba9876543210)
!# Execute some ALU ops ..
setx 0x34400001400, %l0, %l1
faligndata %f10, %f14, %f6
setx 0x34400001400, %l0, %l1
setx 0x34400001400, %l0, %l1
fmul8x16au %f11, %f7, %f0
setx 0x34400001400, %l0, %l1
tsubcctv %g4, 0x0D26, %i6
fmul8sux16 %f12, %f14, %f10
setx 0x34400001400, %l0, %l1
setx 0x34400001400, %l0, %l1
tsubcctv %g7, 0x05BC, %o5
setx 0x34400001400, %l0, %l1
setx 0x34400001400, %l0, %l1
fmul8ulx16 %f10, %f8, %f2
taddcctv %o2, 0x0AEE, %i2
tsubcctv %l6, 0x186C, %i7
setx 0x34400001400, %l0, %l1
fmuld8sux16 %f4, %f4, %f14
fmuld8ulx16 %f4, %f11, %f0
taddcctv %o0, 0x123C, %o5
setx 0x34400001400, %l0, %l1
setx 0x34400001400, %l0, %l1
setx 0x34400001400, %l0, %l1
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
!# Initialize registers ..
INIT_TH_FP_REG(%l7, %f0, 0x55555555aaaaaaaa)
INIT_TH_FP_REG(%l7, %f2, 0xaaaaaaaa55555555)
INIT_TH_FP_REG(%l7, %f4, 0xfedcba9876543210)
INIT_TH_FP_REG(%l7, %f6, 0x0123456789abcdef)
INIT_TH_FP_REG(%l7, %f8, 0x55aa55aaff00ff00)
INIT_TH_FP_REG(%l7, %f10, 0x1111111111111111)
INIT_TH_FP_REG(%l7, %f12, 0x8888888888888888)
INIT_TH_FP_REG(%l7, %f14, 0xfedcba9876543210)
!# Execute some ALU ops ..
setx 0x34400001400, %l0, %l1
fandnot2s %f14, %f15, %f9
tsubcctv %g5, 0x0BF1, %l5
fmovsleu %xcc, %f12, %f13
fmul8sux16 %f14, %f14, %f4
fmuld8ulx16 %f3, %f8, %f0
fmul8x16al %f14, %f15, %f14
fmovrdgez %o2, %f14, %f12
fmul8x16au %f0, %f8, %f10
fmuld8sux16 %f5, %f1, %f4
fandnot1s %f10, %f9, %f13
setx 0x34400001400, %l0, %l1
faligndata %f14, %f8, %f2
fmovsneg %xcc, %f11, %f11
fmovsleu %icc, %f10, %f12
fmul8sux16 %f10, %f10, %f4
fmul8sux16 %f0, %f10, %f6
setx 0x34400001400, %l0, %l1
fmul8x16au %f3, %f6, %f14
fandnot2s %f11, %f12, %f13
faligndata %f2, %f12, %f0
setx 0x34400001400, %l0, %l1
fmovrdgez %l2, %f14, %f10
fmul8x16al %f15, %f10, %f6
fmul8x16al %f4, %f9, %f12
fmul8sux16 %f14, %f2, %f6
fpadd32s %f14, %f12, %f13
fmuld8sux16 %f3, %f3, %f12
faligndata %f10, %f0, %f4
fmuld8ulx16 %f11, %f7, %f2
fandnot1s %f1, %f13, %f11
fmuld8sux16 %f6, %f4, %f0
fmuld8ulx16 %f10, %f14, %f12
fmul8x16au %f9, %f6, %f10
faligndata %f14, %f6, %f10
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
!# Initialize registers ..
INIT_TH_FP_REG(%l7, %f0, 0x55555555aaaaaaaa)
INIT_TH_FP_REG(%l7, %f2, 0xaaaaaaaa55555555)
INIT_TH_FP_REG(%l7, %f4, 0xfedcba9876543210)
INIT_TH_FP_REG(%l7, %f6, 0x0123456789abcdef)
INIT_TH_FP_REG(%l7, %f8, 0x55aa55aaff00ff00)
INIT_TH_FP_REG(%l7, %f10, 0x1111111111111111)
INIT_TH_FP_REG(%l7, %f12, 0x8888888888888888)
INIT_TH_FP_REG(%l7, %f14, 0xfedcba9876543210)
!# Execute some ALU ops ..
fmul8x16al %f2, %f2, %f14
fmul8ulx16 %f10, %f2, %f4
setx 0x34400001400, %l0, %l1
fmul8ulx16 %f2, %f0, %f10
fmul8sux16 %f8, %f12, %f2
setx 0x34400001400, %l0, %l1
faligndata %f10, %f12, %f14
fmuld8ulx16 %f15, %f9, %f8
fmovsleu %icc, %f10, %f12
fandnot1s %f14, %f15, %f7
fmuld8ulx16 %f13, %f15, %f8
fmul8ulx16 %f8, %f12, %f2
tsubcctv %l6, 0x1EFA, %i7
fmovrsgez %i3, %f15, %f13
fmuld8sux16 %f10, %f11, %f6
faligndata %f12, %f14, %f8
setx 0x34400001400, %l0, %l1
setx 0x34400001400, %l0, %l1
setx 0x34400001400, %l0, %l1
tsubcctv %i7, 0x10E1, %g4
setx 0x34400001400, %l0, %l1
fandnot1s %f1, %f10, %f14
setx 0x34400001400, %l0, %l1
faligndata %f12, %f12, %f4
fmul8x16au %f11, %f5, %f6
fmuld8ulx16 %f8, %f12, %f14
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
!# Initialize registers ..
INIT_TH_FP_REG(%l7, %f0, 0x55555555aaaaaaaa)
INIT_TH_FP_REG(%l7, %f2, 0xaaaaaaaa55555555)
INIT_TH_FP_REG(%l7, %f4, 0xfedcba9876543210)
INIT_TH_FP_REG(%l7, %f6, 0x0123456789abcdef)
INIT_TH_FP_REG(%l7, %f8, 0x55aa55aaff00ff00)
INIT_TH_FP_REG(%l7, %f10, 0x1111111111111111)
INIT_TH_FP_REG(%l7, %f12, 0x8888888888888888)
INIT_TH_FP_REG(%l7, %f14, 0xfedcba9876543210)
!# Execute some ALU ops ..
fmovdleu %xcc, %f14, %f13
fmuld8ulx16 %f15, %f12, %f12
fmul8ulx16 %f0, %f12, %f12
fmul8x16al %f8, %f12, %f0
fmul8ulx16 %f4, %f6, %f10
faligndata %f10, %f12, %f12
fpadd32s %f13, %f12, %f14
taddcctv %l4, 0x09F9, %i6
fmovdpos %icc, %f12, %f12
fmovsneg %icc, %f13, %f13
fmuld8ulx16 %f3, %f1, %f10
fmovspos %xcc, %f12, %f12
setx 0x34400001400, %l0, %l1
faligndata %f14, %f14, %f4
fmuld8sux16 %f1, %f5, %f10
fmovrdlez %o7, %f10, %f12
fandnot2s %f14, %f1, %f13
fmovdpos %xcc, %f15, %f10
fmul8x16au %f15, %f7, %f0
fmul8x16al %f13, %f5, %f10
fmul8x16au %f13, %f4, %f10
fmul8x16au %f12, %f12, %f2
setx 0x34400001400, %l0, %l1
fmuld8sux16 %f6, %f2, %f14
fandnot2 %f10, %f10, %f12
setx 0x34400001400, %l0, %l1
fmuld8sux16 %f0, %f12, %f0
fmuld8sux16 %f2, %f5, %f0
fmul8x16al %f4, %f14, %f2
faligndata %f12, %f14, %f2
setx 0x34400001400, %l0, %l1
fmuld8sux16 %f6, %f4, %f4
fmuld8sux16 %f0, %f5, %f0
fandnot2s %f11, %f3, %f11
faligndata %f12, %f14, %f8
setx 0x34400001400, %l0, %l1
setx 0x34400001400, %l0, %l1
fmuld8sux16 %f5, %f3, %f10
setx 0x34400001400, %l0, %l1
fandnot2s %f12, %f6, %f11
setx 0x34400001400, %l0, %l1
fmuld8ulx16 %f11, %f15, %f10
setx 0x34400001400, %l0, %l1
fornot1s %f15, %f15, %f14
fmuld8ulx16 %f5, %f9, %f6
fandnot2s %f14, %f9, %f14
fmul8sux16 %f14, %f6, %f8
fpsub32s %f12, %f15, %f11
fmul8x16au %f15, %f4, %f0
fmul8x16al %f3, %f10, %f4
fmul8ulx16 %f10, %f10, %f12
fmul8x16al %f8, %f6, %f14
fmul8ulx16 %f14, %f14, %f4
faligndata %f2, %f14, %f0
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
!# Initialize registers ..
INIT_TH_FP_REG(%l7, %f0, 0x55555555aaaaaaaa)
INIT_TH_FP_REG(%l7, %f2, 0xaaaaaaaa55555555)
INIT_TH_FP_REG(%l7, %f4, 0xfedcba9876543210)
INIT_TH_FP_REG(%l7, %f6, 0x0123456789abcdef)
INIT_TH_FP_REG(%l7, %f8, 0x55aa55aaff00ff00)
INIT_TH_FP_REG(%l7, %f10, 0x1111111111111111)
INIT_TH_FP_REG(%l7, %f12, 0x8888888888888888)
INIT_TH_FP_REG(%l7, %f14, 0xfedcba9876543210)
!# Execute some ALU ops ..
setx 0x34400001400, %l0, %l1
setx 0x34400001400, %l0, %l1
setx 0x34400001400, %l0, %l1
setx 0x34400001400, %l0, %l1
fornot2s %f10, %f14, %f15
setx 0x34400001400, %l0, %l1
setx 0x34400001400, %l0, %l1
setx 0x34400001400, %l0, %l1
setx 0x34400001400, %l0, %l1
fmuld8ulx16 %f3, %f2, %f6
setx 0x34400001400, %l0, %l1
setx 0x34400001400, %l0, %l1
setx 0x34400001400, %l0, %l1
setx 0x34400001400, %l0, %l1
fmuld8sux16 %f1, %f15, %f2
taddcctv %o6, 0x0F89, %i7
fmul8sux16 %f8, %f0, %f12
setx 0x34400001400, %l0, %l1
setx 0x34400001400, %l0, %l1
taddcctv %i2, 0x06F1, %i4
setx 0x34400001400, %l0, %l1
fmovsneg %xcc, %f15, %f13
setx 0x34400001400, %l0, %l1
setx 0x34400001400, %l0, %l1
setx 0x34400001400, %l0, %l1
fmuld8ulx16 %f13, %f14, %f12
bneg,a,pn %icc, loop_1035
setx 0x34400001400, %l0, %l1
fpadd32s %f11, %f12, %f15
setx 0x34400001400, %l0, %l1
fmul8ulx16 %f0, %f8, %f12
setx 0x34400001400, %l0, %l1
fmul8x16au %f14, %f6, %f10
setx 0x34400001400, %l0, %l1
fmul8x16al %f3, %f10, %f6
setx 0x34400001400, %l0, %l1
setx 0x34400001400, %l0, %l1
setx 0x34400001400, %l0, %l1
setx 0x34400001400, %l0, %l1
setx 0x34400001400, %l0, %l1
bneg,a,pt %xcc, loop_1202
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
!# Initialize registers ..
INIT_TH_FP_REG(%l7, %f0, 0x55555555aaaaaaaa)
INIT_TH_FP_REG(%l7, %f2, 0xaaaaaaaa55555555)
INIT_TH_FP_REG(%l7, %f4, 0xfedcba9876543210)
INIT_TH_FP_REG(%l7, %f6, 0x0123456789abcdef)
INIT_TH_FP_REG(%l7, %f8, 0x55aa55aaff00ff00)
INIT_TH_FP_REG(%l7, %f10, 0x1111111111111111)
INIT_TH_FP_REG(%l7, %f12, 0x8888888888888888)
INIT_TH_FP_REG(%l7, %f14, 0xfedcba9876543210)
!# Execute some ALU ops ..
fmul8ulx16 %f0, %f8, %f14
fmul8x16au %f8, %f13, %f4
tsubcctv %g5, 0x1ADE, %l6
setx 0x34400001400, %l0, %l1
fmul8sux16 %f8, %f14, %f10
bleu,a,pn %icc, loop_1230
fmuld8ulx16 %f10, %f9, %f4
tsubcctv %l2, 0x108A, %l3
setx 0x34400001400, %l0, %l1
setx 0x34400001400, %l0, %l1
fmul8x16au %f11, %f1, %f14
fmul8ulx16 %f10, %f6, %f12
taddcctv %o4, 0x1143, %i2
fandnot2s %f11, %f15, %f3
faligndata %f10, %f0, %f12
fandnot1s %f7, %f14, %f10
tsubcctv %i6, 0x1A99, %i1
setx 0x34400001400, %l0, %l1
setx 0x34400001400, %l0, %l1
fmuld8ulx16 %f4, %f6, %f0
setx 0x34400001400, %l0, %l1
setx 0x34400001400, %l0, %l1
taddcctv %l2, 0x0120, %g5
fmul8ulx16 %f0, %f6, %f14
taddcctv %l4, 0x1372, %i3
fmuld8sux16 %f1, %f7, %f10
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
!# Initialize registers ..
INIT_TH_FP_REG(%l7, %f0, 0x55555555aaaaaaaa)
INIT_TH_FP_REG(%l7, %f2, 0xaaaaaaaa55555555)
INIT_TH_FP_REG(%l7, %f4, 0xfedcba9876543210)
INIT_TH_FP_REG(%l7, %f6, 0x0123456789abcdef)
INIT_TH_FP_REG(%l7, %f8, 0x55aa55aaff00ff00)
INIT_TH_FP_REG(%l7, %f10, 0x1111111111111111)
INIT_TH_FP_REG(%l7, %f12, 0x8888888888888888)
INIT_TH_FP_REG(%l7, %f14, 0xfedcba9876543210)
!# Execute some ALU ops ..
setx 0x34400001400, %l0, %l1
setx 0x34400001400, %l0, %l1
setx 0x34400001400, %l0, %l1
fmul8ulx16 %f4, %f10, %f2
faligndata %f6, %f6, %f14
fmuld8ulx16 %f12, %f4, %f0
setx 0x34400001400, %l0, %l1
faligndata %f10, %f14, %f8
bpos,a,pt %xcc, loop_1393
setx 0x34400001400, %l0, %l1
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
!# Initialize registers ..
INIT_TH_FP_REG(%l7, %f0, 0x55555555aaaaaaaa)
INIT_TH_FP_REG(%l7, %f2, 0xaaaaaaaa55555555)
INIT_TH_FP_REG(%l7, %f4, 0xfedcba9876543210)
INIT_TH_FP_REG(%l7, %f6, 0x0123456789abcdef)
INIT_TH_FP_REG(%l7, %f8, 0x55aa55aaff00ff00)
INIT_TH_FP_REG(%l7, %f10, 0x1111111111111111)
INIT_TH_FP_REG(%l7, %f12, 0x8888888888888888)
INIT_TH_FP_REG(%l7, %f14, 0xfedcba9876543210)
!# Execute some ALU ops ..
bpos,a,pt %xcc, loop_1414
setx 0x34400001400, %l0, %l1
bleu,a,pt %icc, loop_1453
setx 0x34400001400, %l0, %l1
fmul8ulx16 %f14, %f0, %f14
setx 0x34400001400, %l0, %l1
fmuld8ulx16 %f13, %f15, %f2
fmuld8ulx16 %f3, %f15, %f6
fmul8x16au %f13, %f2, %f2
setx 0x34400001400, %l0, %l1
fmul8x16al %f6, %f7, %f14
setx 0x34400001400, %l0, %l1
setx 0x34400001400, %l0, %l1
fmul8x16au %f1, %f12, %f12
setx 0x34400001400, %l0, %l1
setx 0x34400001400, %l0, %l1
setx 0x34400001400, %l0, %l1
setx 0x34400001400, %l0, %l1
setx 0x34400001400, %l0, %l1
fmul8x16al %f14, %f7, %f0
setx 0x34400001400, %l0, %l1
setx 0x34400001400, %l0, %l1
setx 0x34400001400, %l0, %l1
fmul8x16al %f10, %f4, %f4
fmul8ulx16 %f10, %f8, %f4
fmovdpos %icc, %f12, %f10
setx 0x34400001400, %l0, %l1
fmuld8sux16 %f9, %f4, %f6
bpos,a,pt %icc, loop_1615
fmuld8sux16 %f7, %f13, %f12
setx 0x34400001400, %l0, %l1
setx 0x34400001400, %l0, %l1
taddcctv %o3, 0x1CE2, %i3
setx 0x34400001400, %l0, %l1
faligndata %f12, %f4, %f14
fmovsneg %xcc, %f13, %f11
setx 0x34400001400, %l0, %l1
setx 0x34400001400, %l0, %l1
setx 0x34400001400, %l0, %l1
fandnot2s %f15, %f7, %f14
bpos,a,pn %icc, loop_1705
setx 0x34400001400, %l0, %l1
bleu,a,pt %icc, loop_1723
bneg,a,pn %xcc, loop_1729
fmul8x16al %f15, %f14, %f0
setx 0x34400001400, %l0, %l1
fmovdneg %icc, %f11, %f15
fmovsleu %xcc, %f10, %f12
faligndata %f2, %f12, %f14
fandnot1s %f15, %f12, %f15
setx 0x34400001400, %l0, %l1
setx 0x34400001400, %l0, %l1
fmuld8sux16 %f13, %f12, %f4
setx 0x34400001400, %l0, %l1
setx 0x34400001400, %l0, %l1
fmovsleu %xcc, %f13, %f14
fmuld8sux16 %f4, %f4, %f10
bleu,a,pn %icc, loop_1831
setx 0x34400001400, %l0, %l1
fmul8sux16 %f2, %f12, %f10
fmul8sux16 %f14, %f6, %f12
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
EXIT_GOOD /* test finish */
/************************************************************************
************************************************************************/