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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / diag / assembly / uarch / lsu / diag / n2_tso_8talias_8t_1.s
/*
* ========== Copyright Header Begin ==========================================
*
* OpenSPARC T2 Processor File: n2_tso_8talias_8t_1.s
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
*
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
* For the avoidance of doubt, and except that if any non-GPL license
* choice is available it will apply instead, Sun elects to use only
* the General Public License version 2 (GPLv2) at this time for any
* software where a choice of GPL license versions is made
* available with the language indicating that GPLv2 or any later version
* may be used, or where a choice of which version of the GPL is applied is
* otherwise unspecified.
*
* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
* CA 95054 USA or visit www.sun.com if you need additional information or
* have any questions.
*
*
* ========== Copyright Header End ============================================
*/
#define N_CPUS 8
#define REGION_MAPPED_SIZE_RTL 8192
#define REGION_SIZE_RTL (64 * 1024)
#define RESULTS_BUF_SIZE_PER_CPU_RTL 1024
#define PRIVATE_DATA_AREA_PER_CPU_RTL 64
#define ALIGN_PAGE_8K .align 8192
#define ALIGN_PAGE_64K .align 65536
#define ALIGN_PAGE_512K .align 524288
#define ALIGN_PAGE_4M .align 4194304
#define USER_PAGE_CUSTOM_MAP
SECTION .MY_HYP_SEC TEXT_VA = 0x1100150000
attr_text {
Name=.MY_HYP_SEC,
hypervisor
}
.text
.global intr0x60_custom_trap
intr0x60_custom_trap:
ldxa [%g0] 0x72, %g2;
ldxa [%g0] 0x74, %g1;
retry;
.global intr0x190_custom_trap
intr0x190_custom_trap:
.global intr0x190_custom_trap
intr0x190_custom_trap:
#ifdef SJM
! programming the JBI - not quite rrugho
!=====================
!setx 0x0000000006040012, %g1, %g2
!setx 0x8503000010, %g1, %g3
!stx %g2, [%g3]
!!=====================
!setx 0x0000000000000003, %g1, %g2
!setx 0x8500000100, %g1, %g3
!stx %g2, [%g3]
!!=====================
!setx 0x0000000000000000, %g1, %g2
!setx 0x9800000000, %g1, %g3
!stx %g2, [%g3]
!!=====================
!setx 0x0000000000000000, %g1, %g2
!setx 0x9800000400, %g1, %g3
!stx %g2, [%g3]
!!=====================
!setx 0x0000000000000003, %g1, %g2
!setx 0x8500000108, %g1, %g3
!stx %g2, [%g3]
!!=====================
!setx 0x0000000000000101, %g1, %g2
!setx 0x9800000008, %g1, %g3
!stx %g2, [%g3]
!!=====================
!setx 0x0000000000000000, %g1, %g2
!setx 0x9800000408, %g1, %g3
!stx %g2, [%g3]
!!=====================
!setx 0x0000000000000003, %g1, %g2
!setx 0x8500000110, %g1, %g3
!stx %g2, [%g3]
!!=====================
!setx 0x0000000000000202, %g1, %g2
!setx 0x9800000010, %g1, %g3
!stx %g2, [%g3]
!!=====================
!setx 0x0000000000000000, %g1, %g2
!setx 0x9800000410, %g1, %g3
!stx %g2, [%g3]
!!=====================
!setx 0x0000000000000003, %g1, %g2
!setx 0x8500000118, %g1, %g3
!stx %g2, [%g3]
!!=====================
!setx 0x0000000000000303, %g1, %g2
!setx 0x9800000018, %g1, %g3
!stx %g2, [%g3]
!!=====================
!setx 0x0000000000000000, %g1, %g2
!setx 0x9800000418, %g1, %g3
!stx %g2, [%g3]
!!=====================
!setx 0x0000000000000003, %g1, %g2
!setx 0x8500000120, %g1, %g3
!stx %g2, [%g3]
!!=====================
!setx 0x0000000000000404, %g1, %g2
!setx 0x9800000020, %g1, %g3
!stx %g2, [%g3]
!!=====================
!setx 0x0000000000000000, %g1, %g2
!setx 0x9800000420, %g1, %g3
!stx %g2, [%g3]
!!=====================
!setx 0x0000000000000003, %g1, %g2
!setx 0x8500000128, %g1, %g3
!stx %g2, [%g3]
!!=====================
!setx 0x0000000000000505, %g1, %g2
!setx 0x9800000028, %g1, %g3
!stx %g2, [%g3]
!!=====================
!setx 0x0000000000000000, %g1, %g2
!setx 0x9800000428, %g1, %g3
!stx %g2, [%g3]
!!=====================
!setx 0x0000000000000003, %g1, %g2
!setx 0x8500000130, %g1, %g3
!stx %g2, [%g3]
!!=====================
!setx 0x0000000000000606, %g1, %g2
!setx 0x9800000030, %g1, %g3
!stx %g2, [%g3]
!!=====================
!setx 0x0000000000000000, %g1, %g2
!setx 0x9800000430, %g1, %g3
!stx %g2, [%g3]
!!=====================
!setx 0x0000000000000003, %g1, %g2
!setx 0x8500000138, %g1, %g3
!stx %g2, [%g3]
!!=====================
!setx 0x0000000000000707, %g1, %g2
!setx 0x9800000038, %g1, %g3
!stx %g2, [%g3]
!!=====================
!setx 0x0000000000000000, %g1, %g2
!setx 0x9800000438, %g1, %g3
!stx %g2, [%g3]
!!=====================
!setx 0x0000000000000003, %g1, %g2
!setx 0x8500000140, %g1, %g3
!stx %g2, [%g3]
!!=====================
!setx 0x0000000000000808, %g1, %g2
!setx 0x9800000040, %g1, %g3
!stx %g2, [%g3]
!!=====================
!setx 0x0000000000000000, %g1, %g2
!setx 0x9800000440, %g1, %g3
!stx %g2, [%g3]
!!=====================
!setx 0x0000000000000003, %g1, %g2
!setx 0x8500000148, %g1, %g3
!stx %g2, [%g3]
!!=====================
!setx 0x0000000000000909, %g1, %g2
!setx 0x9800000048, %g1, %g3
!stx %g2, [%g3]
!!=====================
!setx 0x0000000000000000, %g1, %g2
!setx 0x9800000448, %g1, %g3
!stx %g2, [%g3]
!!=====================
!setx 0x0000000000000003, %g1, %g2
!setx 0x8500000150, %g1, %g3
!stx %g2, [%g3]
!!=====================
!setx 0x0000000000000a0a, %g1, %g2
!setx 0x9800000050, %g1, %g3
!stx %g2, [%g3]
!!=====================
!setx 0x0000000000000000, %g1, %g2
!setx 0x9800000450, %g1, %g3
!stx %g2, [%g3]
!!=====================
!setx 0x0000000000000003, %g1, %g2
!setx 0x8500000158, %g1, %g3
!stx %g2, [%g3]
!!=====================
!setx 0x0000000000000b0b, %g1, %g2
!setx 0x9800000058, %g1, %g3
!stx %g2, [%g3]
!!=====================
!setx 0x0000000000000000, %g1, %g2
!setx 0x9800000458, %g1, %g3
!stx %g2, [%g3]
!!=====================
!setx 0x0000000000000003, %g1, %g2
!setx 0x8500000160, %g1, %g3
!stx %g2, [%g3]
!!=====================
!setx 0x0000000000000c0c, %g1, %g2
!setx 0x9800000060, %g1, %g3
!stx %g2, [%g3]
!!=====================
!setx 0x0000000000000000, %g1, %g2
!setx 0x9800000460, %g1, %g3
!stx %g2, [%g3]
!!=====================
!setx 0x0000000000000003, %g1, %g2
!setx 0x8500000168, %g1, %g3
!stx %g2, [%g3]
!!=====================
!setx 0x0000000000000d0d, %g1, %g2
!setx 0x9800000068, %g1, %g3
!stx %g2, [%g3]
!!=====================
!setx 0x0000000000000000, %g1, %g2
!setx 0x9800000468, %g1, %g3
!stx %g2, [%g3]
!!=====================
!setx 0x0000000000000003, %g1, %g2
!setx 0x8500000170, %g1, %g3
!stx %g2, [%g3]
!!=====================
!setx 0x0000000000000e0e, %g1, %g2
!setx 0x9800000070, %g1, %g3
!stx %g2, [%g3]
!!=====================
!setx 0x0000000000000000, %g1, %g2
!setx 0x9800000470, %g1, %g3
!stx %g2, [%g3]
!!=====================
!setx 0x0000000000000003, %g1, %g2
!setx 0x8500000178, %g1, %g3
!stx %g2, [%g3]
!!=====================
!setx 0x0000000000000f0f, %g1, %g2
!setx 0x9800000078, %g1, %g3
!stx %g2, [%g3]
!!=====================
!setx 0x0000000000000000, %g1, %g2
!setx 0x9800000478, %g1, %g3
!stx %g2, [%g3]
!!=====================
!setx 0x000000000000007f, %g1, %g2
!setx 0x8503000008, %g1, %g3
!stx %g2, [%g3]
!!=====================
!setx 0x0000000000001010, %g1, %g2
!setx 0x9800000080, %g1, %g3
!stx %g2, [%g3]
!!=====================
!setx 0x0000000000000000, %g1, %g2
!setx 0x9800000480, %g1, %g3
!stx %g2, [%g3]
!!=====================
!setx 0x0000000000001111, %g1, %g2
!setx 0x9800000088, %g1, %g3
!stx %g2, [%g3]
!!=====================
!setx 0x0000000000000000, %g1, %g2
!setx 0x9800000488, %g1, %g3
!stx %g2, [%g3]
!!=====================
!setx 0x0000000000000000, %g1, %g2
!setx 0x9300000c00, %g1, %g3
!stx %g2, [%g3]
!!=====================
!setx 0x0000000000000000, %g1, %g2
!setx 0x9300000e20, %g1, %g3
!stx %g2, [%g3]
!!=====================
!setx 0x0000000000000000, %g1, %g2
!setx 0x9300000e28, %g1, %g3
!stx %g2, [%g3]
!!=====================
!setx 0x0000000000000000, %g1, %g2
!setx 0x9300000e38, %g1, %g3
!stx %g2, [%g3]
!!=====================
!setx 0x0000000000000008, %g1, %g2
!setx 0x8503000018, %g1, %g3
!stx %g2, [%g3]
!!=====================
!setx 0x0000000000000000, %g1, %g2
!setx 0x9800000828, %g1, %g3
!stx %g2, [%g3]
!!=====================
!setx 0x0000000000000000, %g1, %g2
!setx 0x8503000028, %g1, %g3
!stx %g2, [%g3]
!!=====================
!setx 0x0000000000000001, %g1, %g2
!setx 0x8503000020, %g1, %g3
!stx %g2, [%g3]
!!=====================
/***********************************************************************
Disable L2 Cache Visibility Port
***********************************************************************/
setx 0x0000000000000000, %g1, %g2
setx 0x9800001800, %g1, %g3
stx %g2, [%g3]
!=====================
setx 0x0000000000000000, %g1, %g2
setx 0x9800001820, %g1, %g3
stx %g2, [%g3]
!=====================
setx 0x0000000000000000, %g1, %g2
setx 0x9800001828, %g1, %g3
stx %g2, [%g3]
!=====================
setx 0x0000000000000000, %g1, %g2
setx 0x9800001830, %g1, %g3
stx %g2, [%g3]
!=====================
setx 0x0000000000000000, %g1, %g2
setx 0x9800001838, %g1, %g3
stx %g2, [%g3]
!=====================
setx 0x0000000000000000, %g1, %g2
setx 0x9800001840, %g1, %g3
stx %g2, [%g3]
!=====================
/***********************************************************************
Disable IOBridge Visibility Ports
***********************************************************************/
setx 0x0000000000000000, %g1, %g2
setx 0x9800001000, %g1, %g3
stx %g2, [%g3]
!=====================
setx 0x0000000000000000, %g1, %g2
setx 0x9800002000, %g1, %g3
stx %g2, [%g3]
!=====================
setx 0x0000000000000000, %g1, %g2
setx 0x9800002008, %g1, %g3
stx %g2, [%g3]
!=====================
setx 0x0000000000000000, %g1, %g2
setx 0x9800002100, %g1, %g3
stx %g2, [%g3]
!=====================
setx 0x0000000000000000, %g1, %g2
setx 0x9800002140, %g1, %g3
stx %g2, [%g3]
!=====================
setx 0x0000000000000000, %g1, %g2
setx 0x9800002160, %g1, %g3
stx %g2, [%g3]
!=====================
setx 0x0000000000000000, %g1, %g2
setx 0x9800002180, %g1, %g3
stx %g2, [%g3]
!=====================
setx 0x0000000000000000, %g1, %g2
setx 0x98000021a0, %g1, %g3
stx %g2, [%g3]
!=====================
setx 0x0000000000000000, %g1, %g2
setx 0x9800002148, %g1, %g3
stx %g2, [%g3]
!=====================
setx 0x0000000000000000, %g1, %g2
setx 0x9800002168, %g1, %g3
stx %g2, [%g3]
!=====================
setx 0x0000000000000000, %g1, %g2
setx 0x9800002188, %g1, %g3
stx %g2, [%g3]
!=====================
setx 0x0000000000000000, %g1, %g2
setx 0x98000021a8, %g1, %g3
stx %g2, [%g3]
!=====================
setx 0x0000000000000000, %g1, %g2
setx 0x9800002150, %g1, %g3
stx %g2, [%g3]
!=====================
setx 0x0000000000000000, %g1, %g2
setx 0x9800002170, %g1, %g3
stx %g2, [%g3]
!=====================
setx 0x0000000000000000, %g1, %g2
setx 0x9800002190, %g1, %g3
stx %g2, [%g3]
!=====================
setx 0x0000000000000000, %g1, %g2
setx 0x98000021b0, %g1, %g3
stx %g2, [%g3]
!=====================
/***********************************************************************
Configure jbi controller
***********************************************************************/
setx 0x03fb303e00000001, %g1, %g2
setx 0x8000000000, %g1, %g3
stx %g2, [%g3]
!=====================
setx 0x000000007033fe0f, %g1, %g2
setx 0x8000000008, %g1, %g3
stx %g2, [%g3]
!=====================
setx 0x0000003fc0000000, %g1, %g2
setx 0x80000100a0, %g1, %g3
stx %g2, [%g3]
!=====================
setx 0x00000000fe0003ff, %g1, %g2
setx 0x8000004100, %g1, %g3
stx %g2, [%g3]
!=====================
/***********************************************************************
IOSYNC cycles to start sjm
***********************************************************************/
setx 0xdeadbeefdeadbeef, %g1, %g2
setx 0xcf00beef00, %g1, %g3
stx %g2, [%g3]
!=====================
setx 0xdeadbeefdeadbeef, %g1, %g2
setx 0xef00beef00, %g1, %g3
stx %g2, [%g3]
!=============================
done;
#else
#ifdef DC_ON_OFF
and %i0, 0x1, %i0
brz %i0, on
nop
mov 0xd, %i0
ba finish_dc_on_off
stxa %l0, [%g0] 0x45 /* turn D-cache off */
on:
mov 0xf, %i0
stxa %i0, [%g0] 0x45 /* turn D-cache back on */
finish_dc_on_off:
done
#else
stxa %i0, [%g0] 0x73;
done;
#endif
#endif
!============================================================================
#define ENABLE_T0_Fp_exception_ieee_754_0x21
#define ENABLE_T0_Fp_exception_other_0x22
#define ENABLE_T0_Fp_disabled_0x20
#define ENABLE_T0_Illegal_instruction_0x10
#define ENABLE_T1_Illegal_instruction_0x10
#define ENABLE_HT0_Illegal_instruction_0x10
#define ENABLE_HT1_Illegal_instruction_0x10
#define ENABLE_T0_Clean_Window_0x24
#define H_T0_Trap_Instruction_0
#define My_T0_Trap_Instruction_0 \
ta 0x90; \
done;
#define H_HT0_HTrap_Instruction_0 intr0x190_custom_trap
#ifdef SJM
#define My_HT0_HTrap_Instruction_0 \
setx intr0x190_custom_trap, %g1, %g2; \
jmp %g2; nop
#else
#define My_HT0_HTrap_Instruction_0 \
stxa %i0, [%g0] 0x73; \
done;
#endif
#define H_HT0_Interrupt_0x60 intr0x60_custom_trap
#define My_HT0_Interrupt_0x60 \
ldxa [%g0] 0x72, %g2; \
ldxa [%g0] 0x74, %g1; \
retry;
#define THREAD_COUNT 8
#define THREAD_STRIDE 1
#include "hboot.s"
!try later:
! stxa %l6, [$8] (0x22 | ($2 & 0x9)) ! ASI is randomly set
!===========
define(BST_INIT, `
add $6, ($7 & 0xfff0), $8 ! 4-byte align the offset
stxa %l6, [$8] 0x22 ! ASI is randomly set
')
!try later:
!ldda [$8] (0x22 | ($2 & 0x9)), %l6 ! ASI is randomly set
!===========
define(BLD_INIT, `
add $6, ($7 & 0xfff0), $8 ! 4-byte align the offset
ldda [$8] 0x22, %l6 ! ASI is randomly set
')
define(CHECK_PROC_ID,`
check_cpu_id:
wr %g0, 0x4, %fprs /* make sure fef is 1 */
mov THREAD_STRIDE, %l2
th_fork(thread,%l0)
thread_0:
#ifdef SJM
ta 0x30
#endif
mov 0, %g1
udivx %g1, %l2, %g1
ba entry_point; nop
thread_1:
mov 1, %g1
udivx %g1, %l2, %g1
ba entry_point; nop
thread_2:
mov 2, %g1
udivx %g1, %l2, %g1
ba entry_point; nop
thread_3:
mov 3, %g1
udivx %g1, %l2, %g1
ba entry_point; nop
thread_4:
mov 4, %g1
udivx %g1, %l2, %g1
ba entry_point; nop
thread_5:
mov 5, %g1
udivx %g1, %l2, %g1
ba entry_point; nop
thread_6:
mov 6, %g1
udivx %g1, %l2, %g1
ba entry_point; nop
thread_7:
mov 7, %g1
udivx %g1, %l2, %g1
ba entry_point; nop
thread_8:
mov 8, %g1
udivx %g1, %l2, %g1
ba entry_point; nop
thread_9:
mov 9, %g1
udivx %g1, %l2, %g1
ba entry_point; nop
thread_10:
mov 10, %g1
udivx %g1, %l2, %g1
ba entry_point; nop
thread_11:
mov 11, %g1
udivx %g1, %l2, %g1
ba entry_point; nop
thread_12:
mov 12, %g1
udivx %g1, %l2, %g1
ba entry_point; nop
thread_13:
mov 13, %g1
udivx %g1, %l2, %g1
ba entry_point; nop
thread_14:
mov 14, %g1
udivx %g1, %l2, %g1
ba entry_point; nop
thread_15:
mov 15, %g1
udivx %g1, %l2, %g1
ba entry_point; nop
thread_16:
mov 16, %g1
udivx %g1, %l2, %g1
ba entry_point; nop
thread_17:
mov 17, %g1
udivx %g1, %l2, %g1
ba entry_point; nop
thread_18:
mov 18, %g1
udivx %g1, %l2, %g1
ba entry_point; nop
thread_19:
mov 19, %g1
udivx %g1, %l2, %g1
ba entry_point; nop
thread_20:
mov 20, %g1
udivx %g1, %l2, %g1
ba entry_point; nop
thread_21:
mov 21, %g1
udivx %g1, %l2, %g1
ba entry_point; nop
thread_22:
mov 22, %g1
udivx %g1, %l2, %g1
ba entry_point; nop
thread_23:
mov 23, %g1
udivx %g1, %l2, %g1
ba entry_point; nop
thread_24:
mov 24, %g1
udivx %g1, %l2, %g1
ba entry_point; nop
thread_25:
mov 25, %g1
udivx %g1, %l2, %g1
ba entry_point; nop
thread_26:
mov 26, %g1
udivx %g1, %l2, %g1
ba entry_point; nop
thread_27:
mov 27, %g1
udivx %g1, %l2, %g1
ba entry_point; nop
thread_28:
mov 28, %g1
udivx %g1, %l2, %g1
ba entry_point; nop
thread_29:
mov 29, %g1
udivx %g1, %l2, %g1
ba entry_point; nop
thread_30:
mov 30, %g1
udivx %g1, %l2, %g1
ba entry_point; nop
thread_31:
mov 31, %g1
udivx %g1, %l2, %g1
ba entry_point; nop
thread_32:
mov 32, %g1
udivx %g1, %l2, %g1
ba entry_point; nop
thread_33:
mov 33, %g1
udivx %g1, %l2, %g1
ba entry_point; nop
thread_34:
mov 34, %g1
udivx %g1, %l2, %g1
ba entry_point; nop
thread_35:
mov 35, %g1
udivx %g1, %l2, %g1
ba entry_point; nop
thread_36:
mov 36, %g1
udivx %g1, %l2, %g1
ba entry_point; nop
thread_37:
mov 37, %g1
udivx %g1, %l2, %g1
ba entry_point; nop
thread_38:
mov 38, %g1
udivx %g1, %l2, %g1
ba entry_point; nop
thread_39:
mov 39, %g1
udivx %g1, %l2, %g1
ba entry_point; nop
thread_40:
mov 40, %g1
udivx %g1, %l2, %g1
ba entry_point; nop
thread_41:
mov 41, %g1
udivx %g1, %l2, %g1
ba entry_point; nop
thread_42:
mov 42, %g1
udivx %g1, %l2, %g1
ba entry_point; nop
thread_43:
mov 43, %g1
udivx %g1, %l2, %g1
ba entry_point; nop
thread_44:
mov 44, %g1
udivx %g1, %l2, %g1
ba entry_point; nop
thread_45:
mov 45, %g1
udivx %g1, %l2, %g1
ba entry_point; nop
thread_46:
mov 46, %g1
udivx %g1, %l2, %g1
ba entry_point; nop
thread_47:
mov 47, %g1
udivx %g1, %l2, %g1
ba entry_point; nop
thread_48:
mov 48, %g1
udivx %g1, %l2, %g1
ba entry_point; nop
thread_49:
mov 49, %g1
udivx %g1, %l2, %g1
ba entry_point; nop
thread_50:
mov 50, %g1
udivx %g1, %l2, %g1
ba entry_point; nop
thread_51:
mov 51, %g1
udivx %g1, %l2, %g1
ba entry_point; nop
thread_52:
mov 52, %g1
udivx %g1, %l2, %g1
ba entry_point; nop
thread_53:
mov 53, %g1
udivx %g1, %l2, %g1
ba entry_point; nop
thread_54:
mov 54, %g1
udivx %g1, %l2, %g1
ba entry_point; nop
thread_55:
mov 55, %g1
udivx %g1, %l2, %g1
ba entry_point; nop
thread_56:
mov 56, %g1
udivx %g1, %l2, %g1
ba entry_point; nop
thread_57:
mov 57, %g1
udivx %g1, %l2, %g1
ba entry_point; nop
thread_58:
mov 58, %g1
udivx %g1, %l2, %g1
ba entry_point; nop
thread_59:
mov 59, %g1
udivx %g1, %l2, %g1
ba entry_point; nop
thread_60:
mov 60, %g1
udivx %g1, %l2, %g1
ba entry_point; nop
thread_61:
mov 61, %g1
udivx %g1, %l2, %g1
ba entry_point; nop
thread_62:
mov 62, %g1
udivx %g1, %l2, %g1
ba entry_point; nop
thread_63:
mov 63, %g1
udivx %g1, %l2, %g1
ba entry_point; nop
entry_point:
#ifdef RTGPRIV
ta T_CHANGE_PRIV
#endif
')
! --- Common Macro Definitions ---
!
! macros will be instantiated with these arguments
! macro_name(P#, rand#, my_cpu#, PA_val, VA_val, VA_reg, VA_offset, \
! tmp_reg0, tmp_reg1, tmp_reg2, tmp_reg3)
!
! P# - Pid, just in case one needs unique number
! rand# - random number
! my_cpu# - CPU id
! PA_val - shared memory physisal address value
! VA_val - shared memory virtual address value
! VA_reg - register containing VA region base address
! VA_offset - VA_reg + VA_offset will give correct VA address value
! tmp_reg0-tmp_reg3 - integer registers for arbitrary use within the macro
! tmp_reg0 & tmp_reg1 are even-odd register pair
!
! VA_val may be incorrect since VA will be determined at compile time by assembler
! and may not available at diag generation time, but VA_reg+VA_offset is valid
!
! ex. SAMPLE(1, 1249, 0, 0x43400100, 0x100, %i1, 0x100, %l6, %l7, %o5, %l3)
!
! Sample macro 1:
! load unsigned byte from the given shared addr into tmp_reg1
! the given shared addr is 4-byte aligned and we will randomly
! pick one byte from the 4 bytes.
!
! define(SAMPLE, `
! ldub [$6+$7+($2 mod 4)], $8
! ')
!
! Can also use C-like macro definition format.
!
! Sample macro 2:
! issue an "ldda" instruction to the randomly picked shared location
! (aligned it to 16-byte boundary first) with a random ASI value among
! 0x22, 0x23, 0x2a, and 0x2b (utilizing the provided "rand" value).
!
! #define BLD_INIT(Pid, rand, my_cpu, PA_val, \
! VA_val, VA_reg, VA_offset, \
! tmp_reg0, tmp_reg1, tmp_reg2, tmp_reg3) \
! add VA_reg, (VA_offset & 0xfff0), tmp_reg3; \
! ldda [tmp_reg2] (0x22 | (rand & 0x9)), tmp_reg0;
!
! ---
! Macro NOPTRAIN
! Train of NOPs
#define NOPTRAIN(Pid, rand, my_cpu, PA_val, VA_val, VA_reg, VA_offset, tmp_reg1, tmp_reg2, tmp_reg3, tmp_reg4) \
nop;\
nop;\
nop;\
nop;
! Macro STTRAIN4
! Train of total 4 of UW stores.
! Note: doesn't use shared addresses
#define STTRAIN4(Pid, rand, my_cpu, PA_val, VA_val, VA_reg, VA_offset, tmp_reg1, tmp_reg2, tmp_reg3, tmp_reg4) \
set 5120, tmp_reg1; \
add %i0, tmp_reg1, tmp_reg1; \
set rand, tmp_reg2; \
stw tmp_reg2, [tmp_reg1]; \
stw tmp_reg2, [tmp_reg1+4]; \
stw tmp_reg2, [tmp_reg1+8]; \
stw tmp_reg2, [tmp_reg1+16];
! Macro STTRAIN8
! Train of total 8 of UW stores
#define STTRAIN8(Pid, rand, my_cpu, PA_val, VA_val, VA_reg, VA_offset, tmp_reg1, tmp_reg2, tmp_reg3, tmp_reg4) \
set 5120, tmp_reg1; \
add %i0, tmp_reg1, tmp_reg1; \
set rand, tmp_reg2; \
add tmp_reg2, rand % 4096, tmp_reg3; \
stw tmp_reg2, [tmp_reg1]; \
stw tmp_reg2, [tmp_reg1+4]; \
stw tmp_reg2, [tmp_reg1+8]; \
stw tmp_reg2, [tmp_reg1+12]; \
stw tmp_reg3, [tmp_reg1+4]; \
stw tmp_reg3, [tmp_reg1+12]; \
stw tmp_reg3, [tmp_reg1]; \
stw tmp_reg3, [tmp_reg1+8];
! Macro LDTRAIN4
! Train of total 4 of UW Loads
! Note the values of those loads inside the macro will not be analized,
! even though the accesses are [possibly] made to the shared locations
#define LDTRAIN4(Pid, rand, my_cpu, PA_val, VA_val, VA_reg, VA_offset, tmp_reg1, tmp_reg2, tmp_reg3, tmp_reg4) \
ld [%i0], tmp_reg1; \
ld [%i1+4], tmp_reg1; \
ld [%i2+8], tmp_reg1; \
ld [%i3+12], tmp_reg1;
! Macro LDTRAIN8
#define LDTRAIN8(Pid, rand, my_cpu, PA_val, VA_val, VA_reg, VA_offset, tmp_reg1, tmp_reg2, tmp_reg3, tmp_reg4) \
ld [%i3], tmp_reg1; \
ld [%i2+4], tmp_reg1; \
ld [%i1+8], tmp_reg2; \
ld [%i0+12], tmp_reg2; \
ld [%i3+4], tmp_reg3; \
ld [%i2], tmp_reg3; \
ld [%i1+12], tmp_reg4; \
ld [%i0+8], tmp_reg4;
! Macro PREFETCHTRAIN4
#define PREFETCHTRAIN4(Pid, rand, my_cpu, PA_val, VA_val, VA_reg, VA_offset, tmp_reg1, tmp_reg2, tmp_reg3, tmp_reg4) \
prefetch [%i0+4], 0; \
prefetch [%i1+12], 0; \
prefetch [%i2+8], 0; \
prefetch [%i3], 0;
! Macro PREFETCHTRAIN8
#define PREFETCHTRAIN8(Pid, rand, my_cpu, PA_val, VA_val, VA_reg, VA_offset, tmp_reg1, tmp_reg2, tmp_reg3, tmp_reg4) \
prefetch [%i3], 0; \
prefetch [%i2+4], 0; \
prefetch [%i1+8], 0; \
prefetch [%i0+12], 0; \
prefetch [%i3+4], 1; \
prefetch [%i2], 1; \
prefetch [%i1+12], 1; \
prefetch [%i0+8], 1;
! Macro CASTRAIN4
! This is an interesting macro that will probably create the write congessions
! access to the shared locations (offsets from bases have to be adjusted)
! the values of the locations are not changed, so it should not affect analysis
#define CASTRAIN4(Pid, rand, my_cpu, PA_val, VA_val, VA_reg, VA_offset, tmp_reg1, tmp_reg2, tmp_reg3, tmp_reg4) \
set 128, tmp_reg1;\
add %i0, tmp_reg1, tmp_reg1;\
set 256, tmp_reg2;\
add %i1, tmp_reg2, tmp_reg2;\
ld [tmp_reg1], tmp_reg3;\
ld [tmp_reg2], tmp_reg4;\
cas [tmp_reg1], tmp_reg3, tmp_reg3;\
cas [tmp_reg1], tmp_reg3, tmp_reg3;\
cas [tmp_reg2], tmp_reg4, tmp_reg4;\
cas [tmp_reg2], tmp_reg4, tmp_reg4;
#define ASI_BLOCK(Pid, rand, my_cpu, PA_val, VA_val, VA_reg, VA_offset, tmp_reg0, tmp_reg1, tmp_reg2, tmp_reg3) \
setx 0x060, tmp_reg1, tmp_reg2; \
stxa %g0, [tmp_reg2] 0x38;
define(EN_INTERRUPTS,`
nop
')
define(DIS_INTERRUPTS,`
nop
')
define(CHECK_DISPATCH_STATUS,`
nop
')
define(CHECK_RECEIVE_STATUS,`
nop
')
define(WRITE_INTR_DATA_REGS,`
nop
')
define(INTR_SET_DISPATCH_VECTOR,`
add %g0, $3, $4
sllx $4, 8, $5 ! DEST ID
add %g0, $2, $4 ! VECTOR NUMBER
or $5, $4, $5
mov %i0, $4
mov $5, %i0
ta 0x30
mov $4, %i0
')
define(DSPCH_INTERRUPT,`
nop
')
#define REGION0_ALIAS3_O 0x0
#define REGION1_ALIAS3_O 0x10000
#define REGION2_ALIAS3_O 0x20000
#define REGION3_ALIAS3_O 0x30000
#define REGION4_ALIAS3_O 0x40000
#define REGION5_ALIAS3_O 0x50000
#define REGION6_ALIAS3_O 0x60000
#define REGION7_ALIAS3_O 0x70000
#define REPLACEMENT0_ALIAS3_O 0x80000
#define REGION0_ALIAS2_O 0xc0000
#define REGION1_ALIAS2_O 0xd0000
#define REGION2_ALIAS2_O 0xe0000
#define REGION3_ALIAS2_O 0xf0000
#define REGION4_ALIAS2_O 0x100000
#define REGION5_ALIAS2_O 0x110000
#define REGION6_ALIAS2_O 0x120000
#define REGION7_ALIAS2_O 0x130000
#define REPLACEMENT0_ALIAS2_O 0x140000
#define REGION0_ALIAS1_O 0x180000
#define REGION1_ALIAS1_O 0x190000
#define REGION2_ALIAS1_O 0x1a0000
#define REGION3_ALIAS1_O 0x1b0000
#define REGION4_ALIAS1_O 0x1c0000
#define REGION5_ALIAS1_O 0x1d0000
#define REGION6_ALIAS1_O 0x1e0000
#define REGION7_ALIAS1_O 0x1f0000
#define REPLACEMENT0_ALIAS1_O 0x200000
#define REGION0_ALIAS0_O 0x240000
#define REGION1_ALIAS0_O 0x250000
#define REGION2_ALIAS0_O 0x260000
#define REGION3_ALIAS0_O 0x270000
#define REGION4_ALIAS0_O 0x280000
#define REGION5_ALIAS0_O 0x290000
#define REGION6_ALIAS0_O 0x2a0000
#define REGION7_ALIAS0_O 0x2b0000
#define REPLACEMENT0_ALIAS0_O 0x2c0000
#define USER_PAGE_CUSTOM_MAP
SECTION .MAIN TEXT_VA=0x1000000
attr_text {
Name = .MAIN,
VA=0x1000000,
RA=0x130000000,
PA=ra2pa(0x130000000,0),
part_0_ctx_nonzero_tsb_config_1,
TTE_X=1,
TTE_G=1,
TTE_Context=PCONTEXT,
TTE_V=1,
TTE_Size=0,
TTE_SIZE_PTR=0,
TTE_NFO=0,
TTE_IE=0,
TTE_Soft2=0,
TTE_Diag=0,
TTE_Soft=0,
TTE_L=0,
TTE_CP=1,
TTE_CV=1,
TTE_E=0,
TTE_P=0,
TTE_W=0
}
SECTION tsotool_unshared_data DATA_VA=0x21400000
attr_data {
Name = tsotool_unshared_data,
VA=0x21400000,
RA=0x21400000,
PA=ra2pa(0x21400000,0),
part_0_ctx_nonzero_tsb_config_0,
TTE_G=1,
TTE_Context=PCONTEXT,
TTE_V=1,
TTE_Size=0,
TTE_SIZE_PTR=0,
TTE_NFO=0,
TTE_IE=0,
TTE_Soft2=0,
TTE_Diag=0,
TTE_Soft=0,
TTE_L=0,
TTE_CP=1,
TTE_CV=1,
TTE_E=0,
TTE_P=0,
TTE_W=1
}
SECTION region0_alias3_4 DATA_VA=0x6000000
attr_data {
Name = region0_alias3_4,
VA=0x6000000,
RA=0x43000000,
PA=ra2pa(0x43000000,0),
part_0_ctx_nonzero_tsb_config_0,
TTE_G=0,
TTE_Context=PCONTEXT,
TTE_V=1,
TTE_Size=0,
TTE_SIZE_PTR=0,
TTE_NFO=0,
TTE_IE=0,
TTE_Soft2=0,
TTE_Diag=0,
TTE_Soft=0,
TTE_L=0,
TTE_CP=1,
TTE_CV=0,
TTE_E=0,
TTE_P=0,
TTE_W=1,
tsbonly
}
.data
.skip 1024
SECTION region1_alias3_4 DATA_VA=0x6010000
attr_data {
Name = region1_alias3_4,
VA=0x6010000,
RA=0x43800000,
PA=ra2pa(0x43800000,0),
part_0_ctx_nonzero_tsb_config_0,
TTE_G=0,
TTE_Context=PCONTEXT,
TTE_V=1,
TTE_Size=0,
TTE_SIZE_PTR=0,
TTE_NFO=0,
TTE_IE=0,
TTE_Soft2=0,
TTE_Diag=0,
TTE_Soft=0,
TTE_L=0,
TTE_CP=1,
TTE_CV=1,
TTE_E=0,
TTE_P=0,
TTE_W=1,
tsbonly
}
.data
.skip 1024
SECTION region2_alias3_4 DATA_VA=0x6020000
attr_data {
Name = region2_alias3_4,
VA=0x6020000,
RA=0x44000000,
PA=ra2pa(0x44000000,0),
part_0_ctx_nonzero_tsb_config_0,
TTE_G=0,
TTE_Context=PCONTEXT,
TTE_V=1,
TTE_Size=0,
TTE_SIZE_PTR=0,
TTE_NFO=0,
TTE_IE=0,
TTE_Soft2=0,
TTE_Diag=0,
TTE_Soft=0,
TTE_L=0,
TTE_CP=1,
TTE_CV=1,
TTE_E=0,
TTE_P=0,
TTE_W=1,
tsbonly
}
.data
.skip 1024
SECTION region3_alias3_4 DATA_VA=0x6030000
attr_data {
Name = region3_alias3_4,
VA=0x6030000,
RA=0x44800000,
PA=ra2pa(0x44800000,0),
part_0_ctx_nonzero_tsb_config_0,
TTE_G=0,
TTE_Context=PCONTEXT,
TTE_V=1,
TTE_Size=0,
TTE_SIZE_PTR=0,
TTE_NFO=0,
TTE_IE=0,
TTE_Soft2=0,
TTE_Diag=0,
TTE_Soft=0,
TTE_L=0,
TTE_CP=1,
TTE_CV=1,
TTE_E=0,
TTE_P=0,
TTE_W=1,
tsbonly
}
.data
.skip 1024
SECTION region4_alias3_4 DATA_VA=0x6040000
attr_data {
Name = region4_alias3_4,
VA=0x6040000,
RA=0x45000000,
PA=ra2pa(0x45000000,0),
part_0_ctx_nonzero_tsb_config_0,
TTE_G=0,
TTE_Context=PCONTEXT,
TTE_V=1,
TTE_Size=0,
TTE_SIZE_PTR=0,
TTE_NFO=0,
TTE_IE=0,
TTE_Soft2=0,
TTE_Diag=0,
TTE_Soft=0,
TTE_L=0,
TTE_CP=1,
TTE_CV=1,
TTE_E=0,
TTE_P=0,
TTE_W=1,
tsbonly
}
.data
.skip 1024
SECTION region5_alias3_4 DATA_VA=0x6050000
attr_data {
Name = region5_alias3_4,
VA=0x6050000,
RA=0x45800000,
PA=ra2pa(0x45800000,0),
part_0_ctx_nonzero_tsb_config_0,
TTE_G=0,
TTE_Context=PCONTEXT,
TTE_V=1,
TTE_Size=0,
TTE_SIZE_PTR=0,
TTE_NFO=0,
TTE_IE=0,
TTE_Soft2=0,
TTE_Diag=0,
TTE_Soft=0,
TTE_L=0,
TTE_CP=1,
TTE_CV=1,
TTE_E=0,
TTE_P=0,
TTE_W=1,
tsbonly
}
.data
.skip 1024
SECTION region6_alias3_4 DATA_VA=0x6060000
attr_data {
Name = region6_alias3_4,
VA=0x6060000,
RA=0x46000000,
PA=ra2pa(0x46000000,0),
part_0_ctx_nonzero_tsb_config_0,
TTE_G=0,
TTE_Context=PCONTEXT,
TTE_V=1,
TTE_Size=0,
TTE_SIZE_PTR=0,
TTE_NFO=0,
TTE_IE=0,
TTE_Soft2=0,
TTE_Diag=0,
TTE_Soft=0,
TTE_L=0,
TTE_CP=1,
TTE_CV=1,
TTE_E=0,
TTE_P=0,
TTE_W=1,
tsbonly
}
.data
.skip 1024
SECTION region7_alias3_4 DATA_VA=0x6070000
attr_data {
Name = region7_alias3_4,
VA=0x6070000,
RA=0x46800000,
PA=ra2pa(0x46800000,0),
part_0_ctx_nonzero_tsb_config_0,
TTE_G=0,
TTE_Context=PCONTEXT,
TTE_V=1,
TTE_Size=0,
TTE_SIZE_PTR=0,
TTE_NFO=0,
TTE_IE=0,
TTE_Soft2=0,
TTE_Diag=0,
TTE_Soft=0,
TTE_L=0,
TTE_CP=1,
TTE_CV=1,
TTE_E=0,
TTE_P=0,
TTE_W=1,
tsbonly
}
.data
.skip 1024
SECTION replacement0_alias3_4 DATA_VA=0x6080000
attr_data {
Name = replacement0_alias3_4,
VA=0x6080000,
RA=0x47000000,
PA=ra2pa(0x47000000,0),
part_0_ctx_nonzero_tsb_config_0,
TTE_G=0,
TTE_Context=PCONTEXT,
TTE_V=1,
TTE_Size=0,
TTE_SIZE_PTR=0,
TTE_NFO=0,
TTE_IE=0,
TTE_Soft2=0,
TTE_Diag=0,
TTE_Soft=0,
TTE_L=0,
TTE_CP=1,
TTE_CV=1,
TTE_E=0,
TTE_P=0,
TTE_W=1,
tsbonly
}
.data
.skip 1024
SECTION replacement1_alias3_4 DATA_VA=0x6090000
attr_data {
Name = replacement1_alias3_4,
VA=0x6090000,
RA=0x47800000,
PA=ra2pa(0x47800000,0),
part_0_ctx_nonzero_tsb_config_0,
TTE_G=0,
TTE_Context=PCONTEXT,
TTE_V=1,
TTE_Size=0,
TTE_SIZE_PTR=0,
TTE_NFO=0,
TTE_IE=0,
TTE_Soft2=0,
TTE_Diag=0,
TTE_Soft=0,
TTE_L=0,
TTE_CP=1,
TTE_CV=1,
TTE_E=0,
TTE_P=0,
TTE_W=1,
tsbonly
}
.data
.skip 1024
SECTION replacement2_alias3_4 DATA_VA=0x60a0000
attr_data {
Name = replacement2_alias3_4,
VA=0x60a0000,
RA=0x48000000,
PA=ra2pa(0x48000000,0),
part_0_ctx_nonzero_tsb_config_0,
TTE_G=0,
TTE_Context=PCONTEXT,
TTE_V=1,
TTE_Size=0,
TTE_SIZE_PTR=0,
TTE_NFO=0,
TTE_IE=0,
TTE_Soft2=0,
TTE_Diag=0,
TTE_Soft=0,
TTE_L=0,
TTE_CP=1,
TTE_CV=1,
TTE_E=0,
TTE_P=0,
TTE_W=1,
tsbonly
}
.data
.skip 1024
SECTION replacement3_alias3_4 DATA_VA=0x60b0000
attr_data {
Name = replacement3_alias3_4,
VA=0x60b0000,
RA=0x48800000,
PA=ra2pa(0x48800000,0),
part_0_ctx_nonzero_tsb_config_0,
TTE_G=0,
TTE_Context=PCONTEXT,
TTE_V=1,
TTE_Size=0,
TTE_SIZE_PTR=0,
TTE_NFO=0,
TTE_IE=0,
TTE_Soft2=0,
TTE_Diag=0,
TTE_Soft=0,
TTE_L=0,
TTE_CP=1,
TTE_CV=1,
TTE_E=0,
TTE_P=0,
TTE_W=1,
tsbonly
}
.data
.skip 1024
SECTION region0_alias2_4 DATA_VA=0x60c0000
attr_data {
Name = region0_alias2_4,
VA=0x60c0000,
RA=0x43000000,
PA=ra2pa(0x43000000,0),
part_0_ctx_nonzero_tsb_config_0,
TTE_G=0,
TTE_Context=PCONTEXT,
TTE_V=1,
TTE_Size=0,
TTE_SIZE_PTR=0,
TTE_NFO=0,
TTE_IE=0,
TTE_Soft2=0,
TTE_Diag=0,
TTE_Soft=0,
TTE_L=0,
TTE_CP=1,
TTE_CV=0,
TTE_E=0,
TTE_P=0,
TTE_W=1,
tsbonly
}
.data
.skip 1024
SECTION region1_alias2_4 DATA_VA=0x60d0000
attr_data {
Name = region1_alias2_4,
VA=0x60d0000,
RA=0x43800000,
PA=ra2pa(0x43800000,0),
part_0_ctx_nonzero_tsb_config_0,
TTE_G=0,
TTE_Context=PCONTEXT,
TTE_V=1,
TTE_Size=0,
TTE_SIZE_PTR=0,
TTE_NFO=0,
TTE_IE=0,
TTE_Soft2=0,
TTE_Diag=0,
TTE_Soft=0,
TTE_L=0,
TTE_CP=1,
TTE_CV=1,
TTE_E=0,
TTE_P=0,
TTE_W=1,
tsbonly
}
.data
.skip 1024
SECTION region2_alias2_4 DATA_VA=0x60e0000
attr_data {
Name = region2_alias2_4,
VA=0x60e0000,
RA=0x44000000,
PA=ra2pa(0x44000000,0),
part_0_ctx_nonzero_tsb_config_0,
TTE_G=0,
TTE_Context=PCONTEXT,
TTE_V=1,
TTE_Size=0,
TTE_SIZE_PTR=0,
TTE_NFO=0,
TTE_IE=0,
TTE_Soft2=0,
TTE_Diag=0,
TTE_Soft=0,
TTE_L=0,
TTE_CP=1,
TTE_CV=1,
TTE_E=0,
TTE_P=0,
TTE_W=1,
tsbonly
}
.data
.skip 1024
SECTION region3_alias2_4 DATA_VA=0x60f0000
attr_data {
Name = region3_alias2_4,
VA=0x60f0000,
RA=0x44800000,
PA=ra2pa(0x44800000,0),
part_0_ctx_nonzero_tsb_config_0,
TTE_G=0,
TTE_Context=PCONTEXT,
TTE_V=1,
TTE_Size=0,
TTE_SIZE_PTR=0,
TTE_NFO=0,
TTE_IE=0,
TTE_Soft2=0,
TTE_Diag=0,
TTE_Soft=0,
TTE_L=0,
TTE_CP=1,
TTE_CV=1,
TTE_E=0,
TTE_P=0,
TTE_W=1,
tsbonly
}
.data
.skip 1024
SECTION region4_alias2_4 DATA_VA=0x6100000
attr_data {
Name = region4_alias2_4,
VA=0x6100000,
RA=0x45000000,
PA=ra2pa(0x45000000,0),
part_0_ctx_nonzero_tsb_config_0,
TTE_G=0,
TTE_Context=PCONTEXT,
TTE_V=1,
TTE_Size=0,
TTE_SIZE_PTR=0,
TTE_NFO=0,
TTE_IE=0,
TTE_Soft2=0,
TTE_Diag=0,
TTE_Soft=0,
TTE_L=0,
TTE_CP=1,
TTE_CV=1,
TTE_E=0,
TTE_P=0,
TTE_W=1,
tsbonly
}
.data
.skip 1024
SECTION region5_alias2_4 DATA_VA=0x6110000
attr_data {
Name = region5_alias2_4,
VA=0x6110000,
RA=0x45800000,
PA=ra2pa(0x45800000,0),
part_0_ctx_nonzero_tsb_config_0,
TTE_G=0,
TTE_Context=PCONTEXT,
TTE_V=1,
TTE_Size=0,
TTE_SIZE_PTR=0,
TTE_NFO=0,
TTE_IE=0,
TTE_Soft2=0,
TTE_Diag=0,
TTE_Soft=0,
TTE_L=0,
TTE_CP=1,
TTE_CV=1,
TTE_E=0,
TTE_P=0,
TTE_W=1,
tsbonly
}
.data
.skip 1024
SECTION region6_alias2_4 DATA_VA=0x6120000
attr_data {
Name = region6_alias2_4,
VA=0x6120000,
RA=0x46000000,
PA=ra2pa(0x46000000,0),
part_0_ctx_nonzero_tsb_config_0,
TTE_G=0,
TTE_Context=PCONTEXT,
TTE_V=1,
TTE_Size=0,
TTE_SIZE_PTR=0,
TTE_NFO=0,
TTE_IE=0,
TTE_Soft2=0,
TTE_Diag=0,
TTE_Soft=0,
TTE_L=0,
TTE_CP=1,
TTE_CV=1,
TTE_E=0,
TTE_P=0,
TTE_W=1,
tsbonly
}
.data
.skip 1024
SECTION region7_alias2_4 DATA_VA=0x6130000
attr_data {
Name = region7_alias2_4,
VA=0x6130000,
RA=0x46800000,
PA=ra2pa(0x46800000,0),
part_0_ctx_nonzero_tsb_config_0,
TTE_G=0,
TTE_Context=PCONTEXT,
TTE_V=1,
TTE_Size=0,
TTE_SIZE_PTR=0,
TTE_NFO=0,
TTE_IE=0,
TTE_Soft2=0,
TTE_Diag=0,
TTE_Soft=0,
TTE_L=0,
TTE_CP=1,
TTE_CV=1,
TTE_E=0,
TTE_P=0,
TTE_W=1,
tsbonly
}
.data
.skip 1024
SECTION replacement0_alias2_4 DATA_VA=0x6140000
attr_data {
Name = replacement0_alias2_4,
VA=0x6140000,
RA=0x47000000,
PA=ra2pa(0x47000000,0),
part_0_ctx_nonzero_tsb_config_0,
TTE_G=0,
TTE_Context=PCONTEXT,
TTE_V=1,
TTE_Size=0,
TTE_SIZE_PTR=0,
TTE_NFO=0,
TTE_IE=0,
TTE_Soft2=0,
TTE_Diag=0,
TTE_Soft=0,
TTE_L=0,
TTE_CP=1,
TTE_CV=1,
TTE_E=0,
TTE_P=0,
TTE_W=1,
tsbonly
}
.data
.skip 1024
SECTION replacement1_alias2_4 DATA_VA=0x6150000
attr_data {
Name = replacement1_alias2_4,
VA=0x6150000,
RA=0x47800000,
PA=ra2pa(0x47800000,0),
part_0_ctx_nonzero_tsb_config_0,
TTE_G=0,
TTE_Context=PCONTEXT,
TTE_V=1,
TTE_Size=0,
TTE_SIZE_PTR=0,
TTE_NFO=0,
TTE_IE=0,
TTE_Soft2=0,
TTE_Diag=0,
TTE_Soft=0,
TTE_L=0,
TTE_CP=1,
TTE_CV=1,
TTE_E=0,
TTE_P=0,
TTE_W=1,
tsbonly
}
.data
.skip 1024
SECTION replacement2_alias2_4 DATA_VA=0x6160000
attr_data {
Name = replacement2_alias2_4,
VA=0x6160000,
RA=0x48000000,
PA=ra2pa(0x48000000,0),
part_0_ctx_nonzero_tsb_config_0,
TTE_G=0,
TTE_Context=PCONTEXT,
TTE_V=1,
TTE_Size=0,
TTE_SIZE_PTR=0,
TTE_NFO=0,
TTE_IE=0,
TTE_Soft2=0,
TTE_Diag=0,
TTE_Soft=0,
TTE_L=0,
TTE_CP=1,
TTE_CV=1,
TTE_E=0,
TTE_P=0,
TTE_W=1,
tsbonly
}
.data
.skip 1024
SECTION replacement3_alias2_4 DATA_VA=0x6170000
attr_data {
Name = replacement3_alias2_4,
VA=0x6170000,
RA=0x48800000,
PA=ra2pa(0x48800000,0),
part_0_ctx_nonzero_tsb_config_0,
TTE_G=0,
TTE_Context=PCONTEXT,
TTE_V=1,
TTE_Size=0,
TTE_SIZE_PTR=0,
TTE_NFO=0,
TTE_IE=0,
TTE_Soft2=0,
TTE_Diag=0,
TTE_Soft=0,
TTE_L=0,
TTE_CP=1,
TTE_CV=1,
TTE_E=0,
TTE_P=0,
TTE_W=1,
tsbonly
}
.data
.skip 1024
SECTION region0_alias1_4 DATA_VA=0x6180000
attr_data {
Name = region0_alias1_4,
VA=0x6180000,
RA=0x43000000,
PA=ra2pa(0x43000000,0),
part_0_ctx_nonzero_tsb_config_0,
TTE_G=0,
TTE_Context=PCONTEXT,
TTE_V=1,
TTE_Size=0,
TTE_SIZE_PTR=0,
TTE_NFO=0,
TTE_IE=0,
TTE_Soft2=0,
TTE_Diag=0,
TTE_Soft=0,
TTE_L=0,
TTE_CP=1,
TTE_CV=0,
TTE_E=0,
TTE_P=0,
TTE_W=1,
tsbonly
}
.data
.skip 1024
SECTION region1_alias1_4 DATA_VA=0x6190000
attr_data {
Name = region1_alias1_4,
VA=0x6190000,
RA=0x43800000,
PA=ra2pa(0x43800000,0),
part_0_ctx_nonzero_tsb_config_0,
TTE_G=0,
TTE_Context=PCONTEXT,
TTE_V=1,
TTE_Size=0,
TTE_SIZE_PTR=0,
TTE_NFO=0,
TTE_IE=0,
TTE_Soft2=0,
TTE_Diag=0,
TTE_Soft=0,
TTE_L=0,
TTE_CP=1,
TTE_CV=1,
TTE_E=0,
TTE_P=0,
TTE_W=1,
tsbonly
}
.data
.skip 1024
SECTION region2_alias1_4 DATA_VA=0x61a0000
attr_data {
Name = region2_alias1_4,
VA=0x61a0000,
RA=0x44000000,
PA=ra2pa(0x44000000,0),
part_0_ctx_nonzero_tsb_config_0,
TTE_G=0,
TTE_Context=PCONTEXT,
TTE_V=1,
TTE_Size=0,
TTE_SIZE_PTR=0,
TTE_NFO=0,
TTE_IE=0,
TTE_Soft2=0,
TTE_Diag=0,
TTE_Soft=0,
TTE_L=0,
TTE_CP=1,
TTE_CV=1,
TTE_E=0,
TTE_P=0,
TTE_W=1,
tsbonly
}
.data
.skip 1024
SECTION region3_alias1_4 DATA_VA=0x61b0000
attr_data {
Name = region3_alias1_4,
VA=0x61b0000,
RA=0x44800000,
PA=ra2pa(0x44800000,0),
part_0_ctx_nonzero_tsb_config_0,
TTE_G=0,
TTE_Context=PCONTEXT,
TTE_V=1,
TTE_Size=0,
TTE_SIZE_PTR=0,
TTE_NFO=0,
TTE_IE=0,
TTE_Soft2=0,
TTE_Diag=0,
TTE_Soft=0,
TTE_L=0,
TTE_CP=1,
TTE_CV=1,
TTE_E=0,
TTE_P=0,
TTE_W=1,
tsbonly
}
.data
.skip 1024
SECTION region4_alias1_4 DATA_VA=0x61c0000
attr_data {
Name = region4_alias1_4,
VA=0x61c0000,
RA=0x45000000,
PA=ra2pa(0x45000000,0),
part_0_ctx_nonzero_tsb_config_0,
TTE_G=0,
TTE_Context=PCONTEXT,
TTE_V=1,
TTE_Size=0,
TTE_SIZE_PTR=0,
TTE_NFO=0,
TTE_IE=0,
TTE_Soft2=0,
TTE_Diag=0,
TTE_Soft=0,
TTE_L=0,
TTE_CP=1,
TTE_CV=1,
TTE_E=0,
TTE_P=0,
TTE_W=1,
tsbonly
}
.data
.skip 1024
SECTION region5_alias1_4 DATA_VA=0x61d0000
attr_data {
Name = region5_alias1_4,
VA=0x61d0000,
RA=0x45800000,
PA=ra2pa(0x45800000,0),
part_0_ctx_nonzero_tsb_config_0,
TTE_G=0,
TTE_Context=PCONTEXT,
TTE_V=1,
TTE_Size=0,
TTE_SIZE_PTR=0,
TTE_NFO=0,
TTE_IE=0,
TTE_Soft2=0,
TTE_Diag=0,
TTE_Soft=0,
TTE_L=0,
TTE_CP=1,
TTE_CV=1,
TTE_E=0,
TTE_P=0,
TTE_W=1,
tsbonly
}
.data
.skip 1024
SECTION region6_alias1_4 DATA_VA=0x61e0000
attr_data {
Name = region6_alias1_4,
VA=0x61e0000,
RA=0x46000000,
PA=ra2pa(0x46000000,0),
part_0_ctx_nonzero_tsb_config_0,
TTE_G=0,
TTE_Context=PCONTEXT,
TTE_V=1,
TTE_Size=0,
TTE_SIZE_PTR=0,
TTE_NFO=0,
TTE_IE=0,
TTE_Soft2=0,
TTE_Diag=0,
TTE_Soft=0,
TTE_L=0,
TTE_CP=1,
TTE_CV=1,
TTE_E=0,
TTE_P=0,
TTE_W=1,
tsbonly
}
.data
.skip 1024
SECTION region7_alias1_4 DATA_VA=0x61f0000
attr_data {
Name = region7_alias1_4,
VA=0x61f0000,
RA=0x46800000,
PA=ra2pa(0x46800000,0),
part_0_ctx_nonzero_tsb_config_0,
TTE_G=0,
TTE_Context=PCONTEXT,
TTE_V=1,
TTE_Size=0,
TTE_SIZE_PTR=0,
TTE_NFO=0,
TTE_IE=0,
TTE_Soft2=0,
TTE_Diag=0,
TTE_Soft=0,
TTE_L=0,
TTE_CP=1,
TTE_CV=1,
TTE_E=0,
TTE_P=0,
TTE_W=1,
tsbonly
}
.data
.skip 1024
SECTION replacement0_alias1_4 DATA_VA=0x6200000
attr_data {
Name = replacement0_alias1_4,
VA=0x6200000,
RA=0x47000000,
PA=ra2pa(0x47000000,0),
part_0_ctx_nonzero_tsb_config_0,
TTE_G=0,
TTE_Context=PCONTEXT,
TTE_V=1,
TTE_Size=0,
TTE_SIZE_PTR=0,
TTE_NFO=0,
TTE_IE=0,
TTE_Soft2=0,
TTE_Diag=0,
TTE_Soft=0,
TTE_L=0,
TTE_CP=1,
TTE_CV=1,
TTE_E=0,
TTE_P=0,
TTE_W=1,
tsbonly
}
.data
.skip 1024
SECTION replacement1_alias1_4 DATA_VA=0x6210000
attr_data {
Name = replacement1_alias1_4,
VA=0x6210000,
RA=0x47800000,
PA=ra2pa(0x47800000,0),
part_0_ctx_nonzero_tsb_config_0,
TTE_G=0,
TTE_Context=PCONTEXT,
TTE_V=1,
TTE_Size=0,
TTE_SIZE_PTR=0,
TTE_NFO=0,
TTE_IE=0,
TTE_Soft2=0,
TTE_Diag=0,
TTE_Soft=0,
TTE_L=0,
TTE_CP=1,
TTE_CV=1,
TTE_E=0,
TTE_P=0,
TTE_W=1,
tsbonly
}
.data
.skip 1024
SECTION replacement2_alias1_4 DATA_VA=0x6220000
attr_data {
Name = replacement2_alias1_4,
VA=0x6220000,
RA=0x48000000,
PA=ra2pa(0x48000000,0),
part_0_ctx_nonzero_tsb_config_0,
TTE_G=0,
TTE_Context=PCONTEXT,
TTE_V=1,
TTE_Size=0,
TTE_SIZE_PTR=0,
TTE_NFO=0,
TTE_IE=0,
TTE_Soft2=0,
TTE_Diag=0,
TTE_Soft=0,
TTE_L=0,
TTE_CP=1,
TTE_CV=1,
TTE_E=0,
TTE_P=0,
TTE_W=1,
tsbonly
}
.data
.skip 1024
SECTION replacement3_alias1_4 DATA_VA=0x6230000
attr_data {
Name = replacement3_alias1_4,
VA=0x6230000,
RA=0x48800000,
PA=ra2pa(0x48800000,0),
part_0_ctx_nonzero_tsb_config_0,
TTE_G=0,
TTE_Context=PCONTEXT,
TTE_V=1,
TTE_Size=0,
TTE_SIZE_PTR=0,
TTE_NFO=0,
TTE_IE=0,
TTE_Soft2=0,
TTE_Diag=0,
TTE_Soft=0,
TTE_L=0,
TTE_CP=1,
TTE_CV=1,
TTE_E=0,
TTE_P=0,
TTE_W=1,
tsbonly
}
.data
.skip 1024
SECTION region0_alias0 DATA_VA=0x6240000
attr_data {
Name = region0_alias0,
VA=0x6240000,
RA=0x43000000,
PA=ra2pa(0x43000000,0),
part_0_ctx_nonzero_tsb_config_0,
TTE_G=0,
TTE_Context=PCONTEXT,
TTE_V=1,
TTE_Size=0,
TTE_SIZE_PTR=0,
TTE_NFO=0,
TTE_IE=0,
TTE_Soft2=0,
TTE_Diag=0,
TTE_Soft=0,
TTE_L=0,
TTE_CP=1,
TTE_CV=0,
TTE_E=0,
TTE_P=0,
TTE_W=1
}
SECTION region1_alias0 DATA_VA=0x6250000
attr_data {
Name = region1_alias0,
VA=0x6250000,
RA=0x43800000,
PA=ra2pa(0x43800000,0),
part_0_ctx_nonzero_tsb_config_0,
TTE_G=0,
TTE_Context=PCONTEXT,
TTE_V=1,
TTE_Size=0,
TTE_SIZE_PTR=0,
TTE_NFO=0,
TTE_IE=0,
TTE_Soft2=0,
TTE_Diag=0,
TTE_Soft=0,
TTE_L=0,
TTE_CP=1,
TTE_CV=1,
TTE_E=0,
TTE_P=0,
TTE_W=1
}
SECTION region2_alias0 DATA_VA=0x6260000
attr_data {
Name = region2_alias0,
VA=0x6260000,
RA=0x44000000,
PA=ra2pa(0x44000000,0),
part_0_ctx_nonzero_tsb_config_0,
TTE_G=0,
TTE_Context=PCONTEXT,
TTE_V=1,
TTE_Size=0,
TTE_SIZE_PTR=0,
TTE_NFO=0,
TTE_IE=0,
TTE_Soft2=0,
TTE_Diag=0,
TTE_Soft=0,
TTE_L=0,
TTE_CP=1,
TTE_CV=1,
TTE_E=0,
TTE_P=0,
TTE_W=1
}
SECTION region3_alias0 DATA_VA=0x6270000
attr_data {
Name = region3_alias0,
VA=0x6270000,
RA=0x44800000,
PA=ra2pa(0x44800000,0),
part_0_ctx_nonzero_tsb_config_0,
TTE_G=0,
TTE_Context=PCONTEXT,
TTE_V=1,
TTE_Size=0,
TTE_SIZE_PTR=0,
TTE_NFO=0,
TTE_IE=0,
TTE_Soft2=0,
TTE_Diag=0,
TTE_Soft=0,
TTE_L=0,
TTE_CP=1,
TTE_CV=1,
TTE_E=0,
TTE_P=0,
TTE_W=1
}
SECTION region4_alias0 DATA_VA=0x6280000
attr_data {
Name = region4_alias0,
VA=0x6280000,
RA=0x45000000,
PA=ra2pa(0x45000000,0),
part_0_ctx_nonzero_tsb_config_0,
TTE_G=0,
TTE_Context=PCONTEXT,
TTE_V=1,
TTE_Size=0,
TTE_SIZE_PTR=0,
TTE_NFO=0,
TTE_IE=0,
TTE_Soft2=0,
TTE_Diag=0,
TTE_Soft=0,
TTE_L=0,
TTE_CP=1,
TTE_CV=1,
TTE_E=0,
TTE_P=0,
TTE_W=1
}
SECTION region5_alias0 DATA_VA=0x6290000
attr_data {
Name = region5_alias0,
VA=0x6290000,
RA=0x45800000,
PA=ra2pa(0x45800000,0),
part_0_ctx_nonzero_tsb_config_0,
TTE_G=0,
TTE_Context=PCONTEXT,
TTE_V=1,
TTE_Size=0,
TTE_SIZE_PTR=0,
TTE_NFO=0,
TTE_IE=0,
TTE_Soft2=0,
TTE_Diag=0,
TTE_Soft=0,
TTE_L=0,
TTE_CP=1,
TTE_CV=1,
TTE_E=0,
TTE_P=0,
TTE_W=1
}
SECTION region6_alias0 DATA_VA=0x62a0000
attr_data {
Name = region6_alias0,
VA=0x62a0000,
RA=0x46000000,
PA=ra2pa(0x46000000,0),
part_0_ctx_nonzero_tsb_config_0,
TTE_G=0,
TTE_Context=PCONTEXT,
TTE_V=1,
TTE_Size=0,
TTE_SIZE_PTR=0,
TTE_NFO=0,
TTE_IE=0,
TTE_Soft2=0,
TTE_Diag=0,
TTE_Soft=0,
TTE_L=0,
TTE_CP=1,
TTE_CV=1,
TTE_E=0,
TTE_P=0,
TTE_W=1
}
SECTION region7_alias0 DATA_VA=0x62b0000
attr_data {
Name = region7_alias0,
VA=0x62b0000,
RA=0x46800000,
PA=ra2pa(0x46800000,0),
part_0_ctx_nonzero_tsb_config_0,
TTE_G=0,
TTE_Context=PCONTEXT,
TTE_V=1,
TTE_Size=0,
TTE_SIZE_PTR=0,
TTE_NFO=0,
TTE_IE=0,
TTE_Soft2=0,
TTE_Diag=0,
TTE_Soft=0,
TTE_L=0,
TTE_CP=1,
TTE_CV=1,
TTE_E=0,
TTE_P=0,
TTE_W=1
}
SECTION replacement0_alias0 DATA_VA=0x62c0000
attr_data {
Name = replacement0_alias0,
VA=0x62c0000,
RA=0x47000000,
PA=ra2pa(0x47000000,0),
part_0_ctx_nonzero_tsb_config_0,
TTE_G=0,
TTE_Context=PCONTEXT,
TTE_V=1,
TTE_Size=0,
TTE_SIZE_PTR=0,
TTE_NFO=0,
TTE_IE=0,
TTE_Soft2=0,
TTE_Diag=0,
TTE_Soft=0,
TTE_L=0,
TTE_CP=1,
TTE_CV=1,
TTE_E=0,
TTE_P=0,
TTE_W=1
}
SECTION replacement1_alias0 DATA_VA=0x62d0000
attr_data {
Name = replacement1_alias0,
VA=0x62d0000,
RA=0x47800000,
PA=ra2pa(0x47800000,0),
part_0_ctx_nonzero_tsb_config_0,
TTE_G=0,
TTE_Context=PCONTEXT,
TTE_V=1,
TTE_Size=0,
TTE_SIZE_PTR=0,
TTE_NFO=0,
TTE_IE=0,
TTE_Soft2=0,
TTE_Diag=0,
TTE_Soft=0,
TTE_L=0,
TTE_CP=1,
TTE_CV=1,
TTE_E=0,
TTE_P=0,
TTE_W=1
}
SECTION replacement2_alias0 DATA_VA=0x62e0000
attr_data {
Name = replacement2_alias0,
VA=0x62e0000,
RA=0x48000000,
PA=ra2pa(0x48000000,0),
part_0_ctx_nonzero_tsb_config_0,
TTE_G=0,
TTE_Context=PCONTEXT,
TTE_V=1,
TTE_Size=0,
TTE_SIZE_PTR=0,
TTE_NFO=0,
TTE_IE=0,
TTE_Soft2=0,
TTE_Diag=0,
TTE_Soft=0,
TTE_L=0,
TTE_CP=1,
TTE_CV=1,
TTE_E=0,
TTE_P=0,
TTE_W=1
}
SECTION replacement3_alias0 DATA_VA=0x62f0000
attr_data {
Name = replacement3_alias0,
VA=0x62f0000,
RA=0x48800000,
PA=ra2pa(0x48800000,0),
part_0_ctx_nonzero_tsb_config_0,
TTE_G=0,
TTE_Context=PCONTEXT,
TTE_V=1,
TTE_Size=0,
TTE_SIZE_PTR=0,
TTE_NFO=0,
TTE_IE=0,
TTE_Soft2=0,
TTE_Diag=0,
TTE_Soft=0,
TTE_L=0,
TTE_CP=1,
TTE_CV=1,
TTE_E=0,
TTE_P=0,
TTE_W=1
}
SECTION region0_alias3_0 DATA_VA=0x6000000
attr_data {
Name = region0_alias3_0,
VA=0x6000000,
RA=0x43000000,
PA=ra2pa(0x43000000,0),
part_0_ctx_zero_tsb_config_0,
TTE_G=0,
TTE_Context=0,
TTE_V=1,
TTE_Size=0,
TTE_SIZE_PTR=0,
TTE_NFO=0,
TTE_IE=0,
TTE_Soft2=0,
TTE_Diag=0,
TTE_Soft=0,
TTE_L=0,
TTE_CP=1,
TTE_CV=0,
TTE_E=0,
TTE_P=0,
TTE_W=1,
tsbonly
}
.data
.skip 1024
SECTION region1_alias3_0 DATA_VA=0x6010000
attr_data {
Name = region1_alias3_0,
VA=0x6010000,
RA=0x43800000,
PA=ra2pa(0x43800000,0),
part_0_ctx_zero_tsb_config_0,
TTE_G=0,
TTE_Context=0,
TTE_V=1,
TTE_Size=0,
TTE_SIZE_PTR=0,
TTE_NFO=0,
TTE_IE=0,
TTE_Soft2=0,
TTE_Diag=0,
TTE_Soft=0,
TTE_L=0,
TTE_CP=1,
TTE_CV=1,
TTE_E=0,
TTE_P=0,
TTE_W=1,
tsbonly
}
.data
.skip 1024
SECTION region2_alias3_0 DATA_VA=0x6020000
attr_data {
Name = region2_alias3_0,
VA=0x6020000,
RA=0x44000000,
PA=ra2pa(0x44000000,0),
part_0_ctx_zero_tsb_config_0,
TTE_G=0,
TTE_Context=0,
TTE_V=1,
TTE_Size=0,
TTE_SIZE_PTR=0,
TTE_NFO=0,
TTE_IE=0,
TTE_Soft2=0,
TTE_Diag=0,
TTE_Soft=0,
TTE_L=0,
TTE_CP=1,
TTE_CV=1,
TTE_E=0,
TTE_P=0,
TTE_W=1,
tsbonly
}
.data
.skip 1024
SECTION region3_alias3_0 DATA_VA=0x6030000
attr_data {
Name = region3_alias3_0,
VA=0x6030000,
RA=0x44800000,
PA=ra2pa(0x44800000,0),
part_0_ctx_zero_tsb_config_0,
TTE_G=0,
TTE_Context=0,
TTE_V=1,
TTE_Size=0,
TTE_SIZE_PTR=0,
TTE_NFO=0,
TTE_IE=0,
TTE_Soft2=0,
TTE_Diag=0,
TTE_Soft=0,
TTE_L=0,
TTE_CP=1,
TTE_CV=1,
TTE_E=0,
TTE_P=0,
TTE_W=1,
tsbonly
}
.data
.skip 1024
SECTION region4_alias3_0 DATA_VA=0x6040000
attr_data {
Name = region4_alias3_0,
VA=0x6040000,
RA=0x45000000,
PA=ra2pa(0x45000000,0),
part_0_ctx_zero_tsb_config_0,
TTE_G=0,
TTE_Context=0,
TTE_V=1,
TTE_Size=0,
TTE_SIZE_PTR=0,
TTE_NFO=0,
TTE_IE=0,
TTE_Soft2=0,
TTE_Diag=0,
TTE_Soft=0,
TTE_L=0,
TTE_CP=1,
TTE_CV=1,
TTE_E=0,
TTE_P=0,
TTE_W=1,
tsbonly
}
.data
.skip 1024
SECTION region5_alias3_0 DATA_VA=0x6050000
attr_data {
Name = region5_alias3_0,
VA=0x6050000,
RA=0x45800000,
PA=ra2pa(0x45800000,0),
part_0_ctx_zero_tsb_config_0,
TTE_G=0,
TTE_Context=0,
TTE_V=1,
TTE_Size=0,
TTE_SIZE_PTR=0,
TTE_NFO=0,
TTE_IE=0,
TTE_Soft2=0,
TTE_Diag=0,
TTE_Soft=0,
TTE_L=0,
TTE_CP=1,
TTE_CV=1,
TTE_E=0,
TTE_P=0,
TTE_W=1,
tsbonly
}
.data
.skip 1024
SECTION region6_alias3_0 DATA_VA=0x6060000
attr_data {
Name = region6_alias3_0,
VA=0x6060000,
RA=0x46000000,
PA=ra2pa(0x46000000,0),
part_0_ctx_zero_tsb_config_0,
TTE_G=0,
TTE_Context=0,
TTE_V=1,
TTE_Size=0,
TTE_SIZE_PTR=0,
TTE_NFO=0,
TTE_IE=0,
TTE_Soft2=0,
TTE_Diag=0,
TTE_Soft=0,
TTE_L=0,
TTE_CP=1,
TTE_CV=1,
TTE_E=0,
TTE_P=0,
TTE_W=1,
tsbonly
}
.data
.skip 1024
SECTION region7_alias3_0 DATA_VA=0x6070000
attr_data {
Name = region7_alias3_0,
VA=0x6070000,
RA=0x46800000,
PA=ra2pa(0x46800000,0),
part_0_ctx_zero_tsb_config_0,
TTE_G=0,
TTE_Context=0,
TTE_V=1,
TTE_Size=0,
TTE_SIZE_PTR=0,
TTE_NFO=0,
TTE_IE=0,
TTE_Soft2=0,
TTE_Diag=0,
TTE_Soft=0,
TTE_L=0,
TTE_CP=1,
TTE_CV=1,
TTE_E=0,
TTE_P=0,
TTE_W=1,
tsbonly
}
.data
.skip 1024
SECTION replacement0_alias3_0 DATA_VA=0x6080000
attr_data {
Name = replacement0_alias3_0,
VA=0x6080000,
RA=0x47000000,
PA=ra2pa(0x47000000,0),
part_0_ctx_zero_tsb_config_0,
TTE_G=0,
TTE_Context=0,
TTE_V=1,
TTE_Size=0,
TTE_SIZE_PTR=0,
TTE_NFO=0,
TTE_IE=0,
TTE_Soft2=0,
TTE_Diag=0,
TTE_Soft=0,
TTE_L=0,
TTE_CP=1,
TTE_CV=1,
TTE_E=0,
TTE_P=0,
TTE_W=1,
tsbonly
}
.data
.skip 1024
SECTION replacement1_alias3_0 DATA_VA=0x6090000
attr_data {
Name = replacement1_alias3_0,
VA=0x6090000,
RA=0x47800000,
PA=ra2pa(0x47800000,0),
part_0_ctx_zero_tsb_config_0,
TTE_G=0,
TTE_Context=0,
TTE_V=1,
TTE_Size=0,
TTE_SIZE_PTR=0,
TTE_NFO=0,
TTE_IE=0,
TTE_Soft2=0,
TTE_Diag=0,
TTE_Soft=0,
TTE_L=0,
TTE_CP=1,
TTE_CV=1,
TTE_E=0,
TTE_P=0,
TTE_W=1,
tsbonly
}
.data
.skip 1024
SECTION replacement2_alias3_0 DATA_VA=0x60a0000
attr_data {
Name = replacement2_alias3_0,
VA=0x60a0000,
RA=0x48000000,
PA=ra2pa(0x48000000,0),
part_0_ctx_zero_tsb_config_0,
TTE_G=0,
TTE_Context=0,
TTE_V=1,
TTE_Size=0,
TTE_SIZE_PTR=0,
TTE_NFO=0,
TTE_IE=0,
TTE_Soft2=0,
TTE_Diag=0,
TTE_Soft=0,
TTE_L=0,
TTE_CP=1,
TTE_CV=1,
TTE_E=0,
TTE_P=0,
TTE_W=1,
tsbonly
}
.data
.skip 1024
SECTION replacement3_alias3_0 DATA_VA=0x60b0000
attr_data {
Name = replacement3_alias3_0,
VA=0x60b0000,
RA=0x48800000,
PA=ra2pa(0x48800000,0),
part_0_ctx_zero_tsb_config_0,
TTE_G=0,
TTE_Context=0,
TTE_V=1,
TTE_Size=0,
TTE_SIZE_PTR=0,
TTE_NFO=0,
TTE_IE=0,
TTE_Soft2=0,
TTE_Diag=0,
TTE_Soft=0,
TTE_L=0,
TTE_CP=1,
TTE_CV=1,
TTE_E=0,
TTE_P=0,
TTE_W=1,
tsbonly
}
.data
.skip 1024
SECTION region0_alias2_0 DATA_VA=0x60c0000
attr_data {
Name = region0_alias2_0,
VA=0x60c0000,
RA=0x43000000,
PA=ra2pa(0x43000000,0),
part_0_ctx_zero_tsb_config_0,
TTE_G=0,
TTE_Context=0,
TTE_V=1,
TTE_Size=0,
TTE_SIZE_PTR=0,
TTE_NFO=0,
TTE_IE=0,
TTE_Soft2=0,
TTE_Diag=0,
TTE_Soft=0,
TTE_L=0,
TTE_CP=1,
TTE_CV=0,
TTE_E=0,
TTE_P=0,
TTE_W=1,
tsbonly
}
.data
.skip 1024
SECTION region1_alias2_0 DATA_VA=0x60d0000
attr_data {
Name = region1_alias2_0,
VA=0x60d0000,
RA=0x43800000,
PA=ra2pa(0x43800000,0),
part_0_ctx_zero_tsb_config_0,
TTE_G=0,
TTE_Context=0,
TTE_V=1,
TTE_Size=0,
TTE_SIZE_PTR=0,
TTE_NFO=0,
TTE_IE=0,
TTE_Soft2=0,
TTE_Diag=0,
TTE_Soft=0,
TTE_L=0,
TTE_CP=1,
TTE_CV=1,
TTE_E=0,
TTE_P=0,
TTE_W=1,
tsbonly
}
.data
.skip 1024
SECTION region2_alias2_0 DATA_VA=0x60e0000
attr_data {
Name = region2_alias2_0,
VA=0x60e0000,
RA=0x44000000,
PA=ra2pa(0x44000000,0),
part_0_ctx_zero_tsb_config_0,
TTE_G=0,
TTE_Context=0,
TTE_V=1,
TTE_Size=0,
TTE_SIZE_PTR=0,
TTE_NFO=0,
TTE_IE=0,
TTE_Soft2=0,
TTE_Diag=0,
TTE_Soft=0,
TTE_L=0,
TTE_CP=1,
TTE_CV=1,
TTE_E=0,
TTE_P=0,
TTE_W=1,
tsbonly
}
.data
.skip 1024
SECTION region3_alias2_0 DATA_VA=0x60f0000
attr_data {
Name = region3_alias2_0,
VA=0x60f0000,
RA=0x44800000,
PA=ra2pa(0x44800000,0),
part_0_ctx_zero_tsb_config_0,
TTE_G=0,
TTE_Context=0,
TTE_V=1,
TTE_Size=0,
TTE_SIZE_PTR=0,
TTE_NFO=0,
TTE_IE=0,
TTE_Soft2=0,
TTE_Diag=0,
TTE_Soft=0,
TTE_L=0,
TTE_CP=1,
TTE_CV=1,
TTE_E=0,
TTE_P=0,
TTE_W=1,
tsbonly
}
.data
.skip 1024
SECTION region4_alias2_0 DATA_VA=0x6100000
attr_data {
Name = region4_alias2_0,
VA=0x6100000,
RA=0x45000000,
PA=ra2pa(0x45000000,0),
part_0_ctx_zero_tsb_config_0,
TTE_G=0,
TTE_Context=0,
TTE_V=1,
TTE_Size=0,
TTE_SIZE_PTR=0,
TTE_NFO=0,
TTE_IE=0,
TTE_Soft2=0,
TTE_Diag=0,
TTE_Soft=0,
TTE_L=0,
TTE_CP=1,
TTE_CV=1,
TTE_E=0,
TTE_P=0,
TTE_W=1,
tsbonly
}
.data
.skip 1024
SECTION region5_alias2_0 DATA_VA=0x6110000
attr_data {
Name = region5_alias2_0,
VA=0x6110000,
RA=0x45800000,
PA=ra2pa(0x45800000,0),
part_0_ctx_zero_tsb_config_0,
TTE_G=0,
TTE_Context=0,
TTE_V=1,
TTE_Size=0,
TTE_SIZE_PTR=0,
TTE_NFO=0,
TTE_IE=0,
TTE_Soft2=0,
TTE_Diag=0,
TTE_Soft=0,
TTE_L=0,
TTE_CP=1,
TTE_CV=1,
TTE_E=0,
TTE_P=0,
TTE_W=1,
tsbonly
}
.data
.skip 1024
SECTION region6_alias2_0 DATA_VA=0x6120000
attr_data {
Name = region6_alias2_0,
VA=0x6120000,
RA=0x46000000,
PA=ra2pa(0x46000000,0),
part_0_ctx_zero_tsb_config_0,
TTE_G=0,
TTE_Context=0,
TTE_V=1,
TTE_Size=0,
TTE_SIZE_PTR=0,
TTE_NFO=0,
TTE_IE=0,
TTE_Soft2=0,
TTE_Diag=0,
TTE_Soft=0,
TTE_L=0,
TTE_CP=1,
TTE_CV=1,
TTE_E=0,
TTE_P=0,
TTE_W=1,
tsbonly
}
.data
.skip 1024
SECTION region7_alias2_0 DATA_VA=0x6130000
attr_data {
Name = region7_alias2_0,
VA=0x6130000,
RA=0x46800000,
PA=ra2pa(0x46800000,0),
part_0_ctx_zero_tsb_config_0,
TTE_G=0,
TTE_Context=0,
TTE_V=1,
TTE_Size=0,
TTE_SIZE_PTR=0,
TTE_NFO=0,
TTE_IE=0,
TTE_Soft2=0,
TTE_Diag=0,
TTE_Soft=0,
TTE_L=0,
TTE_CP=1,
TTE_CV=1,
TTE_E=0,
TTE_P=0,
TTE_W=1,
tsbonly
}
.data
.skip 1024
SECTION replacement0_alias2_0 DATA_VA=0x6140000
attr_data {
Name = replacement0_alias2_0,
VA=0x6140000,
RA=0x47000000,
PA=ra2pa(0x47000000,0),
part_0_ctx_zero_tsb_config_0,
TTE_G=0,
TTE_Context=0,
TTE_V=1,
TTE_Size=0,
TTE_SIZE_PTR=0,
TTE_NFO=0,
TTE_IE=0,
TTE_Soft2=0,
TTE_Diag=0,
TTE_Soft=0,
TTE_L=0,
TTE_CP=1,
TTE_CV=1,
TTE_E=0,
TTE_P=0,
TTE_W=1,
tsbonly
}
.data
.skip 1024
SECTION replacement1_alias2_0 DATA_VA=0x6150000
attr_data {
Name = replacement1_alias2_0,
VA=0x6150000,
RA=0x47800000,
PA=ra2pa(0x47800000,0),
part_0_ctx_zero_tsb_config_0,
TTE_G=0,
TTE_Context=0,
TTE_V=1,
TTE_Size=0,
TTE_SIZE_PTR=0,
TTE_NFO=0,
TTE_IE=0,
TTE_Soft2=0,
TTE_Diag=0,
TTE_Soft=0,
TTE_L=0,
TTE_CP=1,
TTE_CV=1,
TTE_E=0,
TTE_P=0,
TTE_W=1,
tsbonly
}
.data
.skip 1024
SECTION replacement2_alias2_0 DATA_VA=0x6160000
attr_data {
Name = replacement2_alias2_0,
VA=0x6160000,
RA=0x48000000,
PA=ra2pa(0x48000000,0),
part_0_ctx_zero_tsb_config_0,
TTE_G=0,
TTE_Context=0,
TTE_V=1,
TTE_Size=0,
TTE_SIZE_PTR=0,
TTE_NFO=0,
TTE_IE=0,
TTE_Soft2=0,
TTE_Diag=0,
TTE_Soft=0,
TTE_L=0,
TTE_CP=1,
TTE_CV=1,
TTE_E=0,
TTE_P=0,
TTE_W=1,
tsbonly
}
.data
.skip 1024
SECTION replacement3_alias2_0 DATA_VA=0x6170000
attr_data {
Name = replacement3_alias2_0,
VA=0x6170000,
RA=0x48800000,
PA=ra2pa(0x48800000,0),
part_0_ctx_zero_tsb_config_0,
TTE_G=0,
TTE_Context=0,
TTE_V=1,
TTE_Size=0,
TTE_SIZE_PTR=0,
TTE_NFO=0,
TTE_IE=0,
TTE_Soft2=0,
TTE_Diag=0,
TTE_Soft=0,
TTE_L=0,
TTE_CP=1,
TTE_CV=1,
TTE_E=0,
TTE_P=0,
TTE_W=1,
tsbonly
}
.data
.skip 1024
SECTION region0_alias1_0 DATA_VA=0x6180000
attr_data {
Name = region0_alias1_0,
VA=0x6180000,
RA=0x43000000,
PA=ra2pa(0x43000000,0),
part_0_ctx_zero_tsb_config_0,
TTE_G=0,
TTE_Context=0,
TTE_V=1,
TTE_Size=0,
TTE_SIZE_PTR=0,
TTE_NFO=0,
TTE_IE=0,
TTE_Soft2=0,
TTE_Diag=0,
TTE_Soft=0,
TTE_L=0,
TTE_CP=1,
TTE_CV=0,
TTE_E=0,
TTE_P=0,
TTE_W=1,
tsbonly
}
.data
.skip 1024
SECTION region1_alias1_0 DATA_VA=0x6190000
attr_data {
Name = region1_alias1_0,
VA=0x6190000,
RA=0x43800000,
PA=ra2pa(0x43800000,0),
part_0_ctx_zero_tsb_config_0,
TTE_G=0,
TTE_Context=0,
TTE_V=1,
TTE_Size=0,
TTE_SIZE_PTR=0,
TTE_NFO=0,
TTE_IE=0,
TTE_Soft2=0,
TTE_Diag=0,
TTE_Soft=0,
TTE_L=0,
TTE_CP=1,
TTE_CV=1,
TTE_E=0,
TTE_P=0,
TTE_W=1,
tsbonly
}
.data
.skip 1024
SECTION region2_alias1_0 DATA_VA=0x61a0000
attr_data {
Name = region2_alias1_0,
VA=0x61a0000,
RA=0x44000000,
PA=ra2pa(0x44000000,0),
part_0_ctx_zero_tsb_config_0,
TTE_G=0,
TTE_Context=0,
TTE_V=1,
TTE_Size=0,
TTE_SIZE_PTR=0,
TTE_NFO=0,
TTE_IE=0,
TTE_Soft2=0,
TTE_Diag=0,
TTE_Soft=0,
TTE_L=0,
TTE_CP=1,
TTE_CV=1,
TTE_E=0,
TTE_P=0,
TTE_W=1,
tsbonly
}
.data
.skip 1024
SECTION region3_alias1_0 DATA_VA=0x61b0000
attr_data {
Name = region3_alias1_0,
VA=0x61b0000,
RA=0x44800000,
PA=ra2pa(0x44800000,0),
part_0_ctx_zero_tsb_config_0,
TTE_G=0,
TTE_Context=0,
TTE_V=1,
TTE_Size=0,
TTE_SIZE_PTR=0,
TTE_NFO=0,
TTE_IE=0,
TTE_Soft2=0,
TTE_Diag=0,
TTE_Soft=0,
TTE_L=0,
TTE_CP=1,
TTE_CV=1,
TTE_E=0,
TTE_P=0,
TTE_W=1,
tsbonly
}
.data
.skip 1024
SECTION region4_alias1_0 DATA_VA=0x61c0000
attr_data {
Name = region4_alias1_0,
VA=0x61c0000,
RA=0x45000000,
PA=ra2pa(0x45000000,0),
part_0_ctx_zero_tsb_config_0,
TTE_G=0,
TTE_Context=0,
TTE_V=1,
TTE_Size=0,
TTE_SIZE_PTR=0,
TTE_NFO=0,
TTE_IE=0,
TTE_Soft2=0,
TTE_Diag=0,
TTE_Soft=0,
TTE_L=0,
TTE_CP=1,
TTE_CV=1,
TTE_E=0,
TTE_P=0,
TTE_W=1,
tsbonly
}
.data
.skip 1024
SECTION region5_alias1_0 DATA_VA=0x61d0000
attr_data {
Name = region5_alias1_0,
VA=0x61d0000,
RA=0x45800000,
PA=ra2pa(0x45800000,0),
part_0_ctx_zero_tsb_config_0,
TTE_G=0,
TTE_Context=0,
TTE_V=1,
TTE_Size=0,
TTE_SIZE_PTR=0,
TTE_NFO=0,
TTE_IE=0,
TTE_Soft2=0,
TTE_Diag=0,
TTE_Soft=0,
TTE_L=0,
TTE_CP=1,
TTE_CV=1,
TTE_E=0,
TTE_P=0,
TTE_W=1,
tsbonly
}
.data
.skip 1024
SECTION region6_alias1_0 DATA_VA=0x61e0000
attr_data {
Name = region6_alias1_0,
VA=0x61e0000,
RA=0x46000000,
PA=ra2pa(0x46000000,0),
part_0_ctx_zero_tsb_config_0,
TTE_G=0,
TTE_Context=0,
TTE_V=1,
TTE_Size=0,
TTE_SIZE_PTR=0,
TTE_NFO=0,
TTE_IE=0,
TTE_Soft2=0,
TTE_Diag=0,
TTE_Soft=0,
TTE_L=0,
TTE_CP=1,
TTE_CV=1,
TTE_E=0,
TTE_P=0,
TTE_W=1,
tsbonly
}
.data
.skip 1024
SECTION region7_alias1_0 DATA_VA=0x61f0000
attr_data {
Name = region7_alias1_0,
VA=0x61f0000,
RA=0x46800000,
PA=ra2pa(0x46800000,0),
part_0_ctx_zero_tsb_config_0,
TTE_G=0,
TTE_Context=0,
TTE_V=1,
TTE_Size=0,
TTE_SIZE_PTR=0,
TTE_NFO=0,
TTE_IE=0,
TTE_Soft2=0,
TTE_Diag=0,
TTE_Soft=0,
TTE_L=0,
TTE_CP=1,
TTE_CV=1,
TTE_E=0,
TTE_P=0,
TTE_W=1,
tsbonly
}
.data
.skip 1024
SECTION replacement0_alias1_0 DATA_VA=0x6200000
attr_data {
Name = replacement0_alias1_0,
VA=0x6200000,
RA=0x47000000,
PA=ra2pa(0x47000000,0),
part_0_ctx_zero_tsb_config_0,
TTE_G=0,
TTE_Context=0,
TTE_V=1,
TTE_Size=0,
TTE_SIZE_PTR=0,
TTE_NFO=0,
TTE_IE=0,
TTE_Soft2=0,
TTE_Diag=0,
TTE_Soft=0,
TTE_L=0,
TTE_CP=1,
TTE_CV=1,
TTE_E=0,
TTE_P=0,
TTE_W=1,
tsbonly
}
.data
.skip 1024
SECTION replacement1_alias1_0 DATA_VA=0x6210000
attr_data {
Name = replacement1_alias1_0,
VA=0x6210000,
RA=0x47800000,
PA=ra2pa(0x47800000,0),
part_0_ctx_zero_tsb_config_0,
TTE_G=0,
TTE_Context=0,
TTE_V=1,
TTE_Size=0,
TTE_SIZE_PTR=0,
TTE_NFO=0,
TTE_IE=0,
TTE_Soft2=0,
TTE_Diag=0,
TTE_Soft=0,
TTE_L=0,
TTE_CP=1,
TTE_CV=1,
TTE_E=0,
TTE_P=0,
TTE_W=1,
tsbonly
}
.data
.skip 1024
SECTION replacement2_alias1_0 DATA_VA=0x6220000
attr_data {
Name = replacement2_alias1_0,
VA=0x6220000,
RA=0x48000000,
PA=ra2pa(0x48000000,0),
part_0_ctx_zero_tsb_config_0,
TTE_G=0,
TTE_Context=0,
TTE_V=1,
TTE_Size=0,
TTE_SIZE_PTR=0,
TTE_NFO=0,
TTE_IE=0,
TTE_Soft2=0,
TTE_Diag=0,
TTE_Soft=0,
TTE_L=0,
TTE_CP=1,
TTE_CV=1,
TTE_E=0,
TTE_P=0,
TTE_W=1,
tsbonly
}
.data
.skip 1024
SECTION replacement3_alias1_0 DATA_VA=0x6230000
attr_data {
Name = replacement3_alias1_0,
VA=0x6230000,
RA=0x48800000,
PA=ra2pa(0x48800000,0),
part_0_ctx_zero_tsb_config_0,
TTE_G=0,
TTE_Context=0,
TTE_V=1,
TTE_Size=0,
TTE_SIZE_PTR=0,
TTE_NFO=0,
TTE_IE=0,
TTE_Soft2=0,
TTE_Diag=0,
TTE_Soft=0,
TTE_L=0,
TTE_CP=1,
TTE_CV=1,
TTE_E=0,
TTE_P=0,
TTE_W=1,
tsbonly
}
.data
.skip 1024
SECTION region0_alias0_0 DATA_VA=0x6240000
attr_data {
Name = region0_alias0_0,
VA=0x6240000,
RA=0x43000000,
PA=ra2pa(0x43000000,0),
part_0_ctx_zero_tsb_config_0,
TTE_G=0,
TTE_Context=0,
TTE_V=1,
TTE_Size=0,
TTE_SIZE_PTR=0,
TTE_NFO=0,
TTE_IE=0,
TTE_Soft2=0,
TTE_Diag=0,
TTE_Soft=0,
TTE_L=0,
TTE_CP=1,
TTE_CV=0,
TTE_E=0,
TTE_P=0,
TTE_W=1,
tsbonly
}
.data
.skip 1024
SECTION region1_alias0_0 DATA_VA=0x6250000
attr_data {
Name = region1_alias0_0,
VA=0x6250000,
RA=0x43800000,
PA=ra2pa(0x43800000,0),
part_0_ctx_zero_tsb_config_0,
TTE_G=0,
TTE_Context=0,
TTE_V=1,
TTE_Size=0,
TTE_SIZE_PTR=0,
TTE_NFO=0,
TTE_IE=0,
TTE_Soft2=0,
TTE_Diag=0,
TTE_Soft=0,
TTE_L=0,
TTE_CP=1,
TTE_CV=1,
TTE_E=0,
TTE_P=0,
TTE_W=1,
tsbonly
}
.data
.skip 1024
SECTION region2_alias0_0 DATA_VA=0x6260000
attr_data {
Name = region2_alias0_0,
VA=0x6260000,
RA=0x44000000,
PA=ra2pa(0x44000000,0),
part_0_ctx_zero_tsb_config_0,
TTE_G=0,
TTE_Context=0,
TTE_V=1,
TTE_Size=0,
TTE_SIZE_PTR=0,
TTE_NFO=0,
TTE_IE=0,
TTE_Soft2=0,
TTE_Diag=0,
TTE_Soft=0,
TTE_L=0,
TTE_CP=1,
TTE_CV=1,
TTE_E=0,
TTE_P=0,
TTE_W=1,
tsbonly
}
.data
.skip 1024
SECTION region3_alias0_0 DATA_VA=0x6270000
attr_data {
Name = region3_alias0_0,
VA=0x6270000,
RA=0x44800000,
PA=ra2pa(0x44800000,0),
part_0_ctx_zero_tsb_config_0,
TTE_G=0,
TTE_Context=0,
TTE_V=1,
TTE_Size=0,
TTE_SIZE_PTR=0,
TTE_NFO=0,
TTE_IE=0,
TTE_Soft2=0,
TTE_Diag=0,
TTE_Soft=0,
TTE_L=0,
TTE_CP=1,
TTE_CV=1,
TTE_E=0,
TTE_P=0,
TTE_W=1,
tsbonly
}
.data
.skip 1024
SECTION region4_alias0_0 DATA_VA=0x6280000
attr_data {
Name = region4_alias0_0,
VA=0x6280000,
RA=0x45000000,
PA=ra2pa(0x45000000,0),
part_0_ctx_zero_tsb_config_0,
TTE_G=0,
TTE_Context=0,
TTE_V=1,
TTE_Size=0,
TTE_SIZE_PTR=0,
TTE_NFO=0,
TTE_IE=0,
TTE_Soft2=0,
TTE_Diag=0,
TTE_Soft=0,
TTE_L=0,
TTE_CP=1,
TTE_CV=1,
TTE_E=0,
TTE_P=0,
TTE_W=1,
tsbonly
}
.data
.skip 1024
SECTION region5_alias0_0 DATA_VA=0x6290000
attr_data {
Name = region5_alias0_0,
VA=0x6290000,
RA=0x45800000,
PA=ra2pa(0x45800000,0),
part_0_ctx_zero_tsb_config_0,
TTE_G=0,
TTE_Context=0,
TTE_V=1,
TTE_Size=0,
TTE_SIZE_PTR=0,
TTE_NFO=0,
TTE_IE=0,
TTE_Soft2=0,
TTE_Diag=0,
TTE_Soft=0,
TTE_L=0,
TTE_CP=1,
TTE_CV=1,
TTE_E=0,
TTE_P=0,
TTE_W=1,
tsbonly
}
.data
.skip 1024
SECTION region6_alias0_0 DATA_VA=0x62a0000
attr_data {
Name = region6_alias0_0,
VA=0x62a0000,
RA=0x46000000,
PA=ra2pa(0x46000000,0),
part_0_ctx_zero_tsb_config_0,
TTE_G=0,
TTE_Context=0,
TTE_V=1,
TTE_Size=0,
TTE_SIZE_PTR=0,
TTE_NFO=0,
TTE_IE=0,
TTE_Soft2=0,
TTE_Diag=0,
TTE_Soft=0,
TTE_L=0,
TTE_CP=1,
TTE_CV=1,
TTE_E=0,
TTE_P=0,
TTE_W=1,
tsbonly
}
.data
.skip 1024
SECTION region7_alias0_0 DATA_VA=0x62b0000
attr_data {
Name = region7_alias0_0,
VA=0x62b0000,
RA=0x46800000,
PA=ra2pa(0x46800000,0),
part_0_ctx_zero_tsb_config_0,
TTE_G=0,
TTE_Context=0,
TTE_V=1,
TTE_Size=0,
TTE_SIZE_PTR=0,
TTE_NFO=0,
TTE_IE=0,
TTE_Soft2=0,
TTE_Diag=0,
TTE_Soft=0,
TTE_L=0,
TTE_CP=1,
TTE_CV=1,
TTE_E=0,
TTE_P=0,
TTE_W=1,
tsbonly
}
.data
.skip 1024
SECTION replacement0_alias0_0 DATA_VA=0x62c0000
attr_data {
Name = replacement0_alias0_0,
VA=0x62c0000,
RA=0x47000000,
PA=ra2pa(0x47000000,0),
part_0_ctx_zero_tsb_config_0,
TTE_G=0,
TTE_Context=0,
TTE_V=1,
TTE_Size=0,
TTE_SIZE_PTR=0,
TTE_NFO=0,
TTE_IE=0,
TTE_Soft2=0,
TTE_Diag=0,
TTE_Soft=0,
TTE_L=0,
TTE_CP=1,
TTE_CV=1,
TTE_E=0,
TTE_P=0,
TTE_W=1,
tsbonly
}
.data
.skip 1024
SECTION replacement1_alias0_0 DATA_VA=0x62d0000
attr_data {
Name = replacement1_alias0_0,
VA=0x62d0000,
RA=0x47800000,
PA=ra2pa(0x47800000,0),
part_0_ctx_zero_tsb_config_0,
TTE_G=0,
TTE_Context=0,
TTE_V=1,
TTE_Size=0,
TTE_SIZE_PTR=0,
TTE_NFO=0,
TTE_IE=0,
TTE_Soft2=0,
TTE_Diag=0,
TTE_Soft=0,
TTE_L=0,
TTE_CP=1,
TTE_CV=1,
TTE_E=0,
TTE_P=0,
TTE_W=1,
tsbonly
}
.data
.skip 1024
SECTION replacement2_alias0_0 DATA_VA=0x62e0000
attr_data {
Name = replacement2_alias0_0,
VA=0x62e0000,
RA=0x48000000,
PA=ra2pa(0x48000000,0),
part_0_ctx_zero_tsb_config_0,
TTE_G=0,
TTE_Context=0,
TTE_V=1,
TTE_Size=0,
TTE_SIZE_PTR=0,
TTE_NFO=0,
TTE_IE=0,
TTE_Soft2=0,
TTE_Diag=0,
TTE_Soft=0,
TTE_L=0,
TTE_CP=1,
TTE_CV=1,
TTE_E=0,
TTE_P=0,
TTE_W=1,
tsbonly
}
.data
.skip 1024
SECTION replacement3_alias0_0 DATA_VA=0x62f0000
attr_data {
Name = replacement3_alias0_0,
VA=0x62f0000,
RA=0x48800000,
PA=ra2pa(0x48800000,0),
part_0_ctx_zero_tsb_config_0,
TTE_G=0,
TTE_Context=0,
TTE_V=1,
TTE_Size=0,
TTE_SIZE_PTR=0,
TTE_NFO=0,
TTE_IE=0,
TTE_Soft2=0,
TTE_Diag=0,
TTE_Soft=0,
TTE_L=0,
TTE_CP=1,
TTE_CV=1,
TTE_E=0,
TTE_P=0,
TTE_W=1,
tsbonly
}
.data
.skip 1024
!------------------------------------------------------------------------
SECTION tsotool_unshared_data
.global tsotool_unshared_data_start
.global res_buf_fp_p_0
.global res_buf_int_p_0
.global private_data_p0
.global stack_top_p0:
.global res_buf_fp_p_1
.global res_buf_int_p_1
.global private_data_p1
.global stack_top_p1:
.global res_buf_fp_p_2
.global res_buf_int_p_2
.global private_data_p2
.global stack_top_p2:
.global res_buf_fp_p_3
.global res_buf_int_p_3
.global private_data_p3
.global stack_top_p3:
.global res_buf_fp_p_4
.global res_buf_int_p_4
.global private_data_p4
.global stack_top_p4:
.global res_buf_fp_p_5
.global res_buf_int_p_5
.global private_data_p5
.global stack_top_p5:
.global res_buf_fp_p_6
.global res_buf_int_p_6
.global private_data_p6
.global stack_top_p6:
.global res_buf_fp_p_7
.global res_buf_int_p_7
.global private_data_p7
.global stack_top_p7:
.data
ALIGN_PAGE_512K
tsotool_unshared_data_start:
!-- label names of res_buf must match with extract_loads_m64.pl --
.align 64 ! for self bcopy()
res_buf_fp_p_0:
.skip RESULTS_BUF_SIZE_PER_CPU_RTL/2
.align 64 ! for self bcopy()
res_buf_int_p_0:
.skip RESULTS_BUF_SIZE_PER_CPU_RTL/2
.align 64 ! for self bcopy()
res_buf_fp_p_1:
.skip RESULTS_BUF_SIZE_PER_CPU_RTL/2
.align 64 ! for self bcopy()
res_buf_int_p_1:
.skip RESULTS_BUF_SIZE_PER_CPU_RTL/2
.align 64 ! for self bcopy()
res_buf_fp_p_2:
.skip RESULTS_BUF_SIZE_PER_CPU_RTL/2
.align 64 ! for self bcopy()
res_buf_int_p_2:
.skip RESULTS_BUF_SIZE_PER_CPU_RTL/2
.align 64 ! for self bcopy()
res_buf_fp_p_3:
.skip RESULTS_BUF_SIZE_PER_CPU_RTL/2
.align 64 ! for self bcopy()
res_buf_int_p_3:
.skip RESULTS_BUF_SIZE_PER_CPU_RTL/2
.align 64 ! for self bcopy()
res_buf_fp_p_4:
.skip RESULTS_BUF_SIZE_PER_CPU_RTL/2
.align 64 ! for self bcopy()
res_buf_int_p_4:
.skip RESULTS_BUF_SIZE_PER_CPU_RTL/2
.align 64 ! for self bcopy()
res_buf_fp_p_5:
.skip RESULTS_BUF_SIZE_PER_CPU_RTL/2
.align 64 ! for self bcopy()
res_buf_int_p_5:
.skip RESULTS_BUF_SIZE_PER_CPU_RTL/2
.align 64 ! for self bcopy()
res_buf_fp_p_6:
.skip RESULTS_BUF_SIZE_PER_CPU_RTL/2
.align 64 ! for self bcopy()
res_buf_int_p_6:
.skip RESULTS_BUF_SIZE_PER_CPU_RTL/2
.align 64 ! for self bcopy()
res_buf_fp_p_7:
.skip RESULTS_BUF_SIZE_PER_CPU_RTL/2
.align 64 ! for self bcopy()
res_buf_int_p_7:
.skip RESULTS_BUF_SIZE_PER_CPU_RTL/2
private_data_p0:
.skip PRIVATE_DATA_AREA_PER_CPU_RTL
private_data_p1:
.skip PRIVATE_DATA_AREA_PER_CPU_RTL
private_data_p2:
.skip PRIVATE_DATA_AREA_PER_CPU_RTL
private_data_p3:
.skip PRIVATE_DATA_AREA_PER_CPU_RTL
private_data_p4:
.skip PRIVATE_DATA_AREA_PER_CPU_RTL
private_data_p5:
.skip PRIVATE_DATA_AREA_PER_CPU_RTL
private_data_p6:
.skip PRIVATE_DATA_AREA_PER_CPU_RTL
private_data_p7:
.skip PRIVATE_DATA_AREA_PER_CPU_RTL
stack_top_p0:
.skip 2048
stack_top_p1:
.skip 2048
stack_top_p2:
.skip 2048
stack_top_p3:
.skip 2048
stack_top_p4:
.skip 2048
stack_top_p5:
.skip 2048
stack_top_p6:
.skip 2048
stack_top_p7:
.skip 2048
tsotool_unshared_data_end:
ALIGN_PAGE_512K
! to prevent VAs from running over from this section into shared regions
!------------------------------------------------------------------------
.seg "data"
! 8 shared memory regions, 3 alias(es) each (Alias 0 is normal VA)
SECTION region0_alias0
.global REGION0_ALIAS0_START
.data
ALIGN_PAGE_8K
REGION0_ALIAS0_START:
.skip REGION_MAPPED_SIZE_RTL
REGION0_ALIAS0_END:
.skip REGION_SIZE_RTL-REGION_MAPPED_SIZE_RTL
SECTION region1_alias0
.global REGION1_ALIAS0_START
.data
ALIGN_PAGE_8K
REGION1_ALIAS0_START:
.skip REGION_MAPPED_SIZE_RTL
REGION1_ALIAS0_END:
.skip REGION_SIZE_RTL-REGION_MAPPED_SIZE_RTL
SECTION region2_alias0
.global REGION2_ALIAS0_START
.data
ALIGN_PAGE_8K
REGION2_ALIAS0_START:
.skip REGION_MAPPED_SIZE_RTL
REGION2_ALIAS0_END:
.skip REGION_SIZE_RTL-REGION_MAPPED_SIZE_RTL
SECTION region3_alias0
.global REGION3_ALIAS0_START
.data
ALIGN_PAGE_8K
REGION3_ALIAS0_START:
.skip REGION_MAPPED_SIZE_RTL
REGION3_ALIAS0_END:
.skip REGION_SIZE_RTL-REGION_MAPPED_SIZE_RTL
SECTION region4_alias0
.global REGION4_ALIAS0_START
.data
ALIGN_PAGE_8K
REGION4_ALIAS0_START:
.skip REGION_MAPPED_SIZE_RTL
REGION4_ALIAS0_END:
.skip REGION_SIZE_RTL-REGION_MAPPED_SIZE_RTL
SECTION region5_alias0
.global REGION5_ALIAS0_START
.data
ALIGN_PAGE_8K
REGION5_ALIAS0_START:
.skip REGION_MAPPED_SIZE_RTL
REGION5_ALIAS0_END:
.skip REGION_SIZE_RTL-REGION_MAPPED_SIZE_RTL
SECTION region6_alias0
.global REGION6_ALIAS0_START
.data
ALIGN_PAGE_8K
REGION6_ALIAS0_START:
.skip REGION_MAPPED_SIZE_RTL
REGION6_ALIAS0_END:
.skip REGION_SIZE_RTL-REGION_MAPPED_SIZE_RTL
SECTION region7_alias0
.global REGION7_ALIAS0_START
.data
ALIGN_PAGE_8K
REGION7_ALIAS0_START:
.skip REGION_MAPPED_SIZE_RTL
REGION7_ALIAS0_END:
.skip REGION_SIZE_RTL-REGION_MAPPED_SIZE_RTL
SECTION replacement0_alias0
.global REPLACEMENT0_ALIAS0_START
.data
ALIGN_PAGE_8K
REPLACEMENT0_ALIAS0_START:
.skip REGION_MAPPED_SIZE_RTL
REPLACEMENT0_ALIAS0_END:
.skip REGION_SIZE_RTL-REGION_MAPPED_SIZE_RTL
SECTION replacement1_alias0
.global REPLACEMENT1_ALIAS0_START
.data
ALIGN_PAGE_8K
REPLACEMENT1_ALIAS0_START:
.skip REGION_MAPPED_SIZE_RTL
REPLACEMENT1_ALIAS0_END:
.skip REGION_SIZE_RTL-REGION_MAPPED_SIZE_RTL
SECTION replacement2_alias0
.global REPLACEMENT2_ALIAS0_START
.data
ALIGN_PAGE_8K
REPLACEMENT2_ALIAS0_START:
.skip REGION_MAPPED_SIZE_RTL
REPLACEMENT2_ALIAS0_END:
.skip REGION_SIZE_RTL-REGION_MAPPED_SIZE_RTL
SECTION replacement3_alias0
.global REPLACEMENT3_ALIAS0_START
.data
ALIGN_PAGE_8K
REPLACEMENT3_ALIAS0_START:
.skip REGION_MAPPED_SIZE_RTL
REPLACEMENT3_ALIAS0_END:
.skip REGION_SIZE_RTL-REGION_MAPPED_SIZE_RTL
.seg "text"
ALIGN_PAGE_8K
local_trap_handlers_start:
.align 64
extern_interrupt_handler:
stxa %g0, [%g0]ASI_INTR_RECEIVE
retry
local_trap_handlers_end:
SECTION .MAIN
.global main
.global tsotool_text_start
.text
ALIGN_PAGE_64K
user_text_start:
ba main
nop
user_text_end:
ALIGN_PAGE_64K
tsotool_text_start:
main:
mov 0, %o0
mov 0, %o1
CHECK_PROC_ID
! at this point, g1 should have CPU id (0, 1, 2, ...)
set REGION0_ALIAS0_START, %o0 ! shared address 0
set REGION1_ALIAS0_START, %o1 ! shared address 1
set REGION2_ALIAS0_START, %o2 ! shared address 2
set REGION3_ALIAS0_START, %o3 ! shared address 3
cmp %g1, 0x7
be setup_p7
nop
cmp %g1, 0x6
be setup_p6
nop
cmp %g1, 0x5
be setup_p5
nop
cmp %g1, 0x4
be setup_p4
nop
cmp %g1, 0x3
be setup_p3
nop
cmp %g1, 0x2
be setup_p2
nop
cmp %g1, 0x1
be setup_p1
nop
cmp %g1, 0x0
be setup_p0
nop
EXIT_BAD ! Should never reach here
nop
setup_p0:
setx stack_top_p0, %g1, %l1
add %l1, 1024, %sp
setx res_buf_fp_p_0, %g1, %o4
setx private_data_p0, %g1, %o5
setx func0, %g1, %l4
call %l4
nop
EXIT_GOOD
nop
setup_p1:
setx stack_top_p1, %g1, %l1
add %l1, 1024, %sp
setx res_buf_fp_p_1, %g1, %o4
setx private_data_p1, %g1, %o5
setx func1, %g1, %l4
call %l4
nop
EXIT_GOOD
nop
setup_p2:
setx stack_top_p2, %g1, %l1
add %l1, 1024, %sp
setx res_buf_fp_p_2, %g1, %o4
setx private_data_p2, %g1, %o5
setx func2, %g1, %l4
call %l4
nop
EXIT_GOOD
nop
setup_p3:
setx stack_top_p3, %g1, %l1
add %l1, 1024, %sp
setx res_buf_fp_p_3, %g1, %o4
setx private_data_p3, %g1, %o5
setx func3, %g1, %l4
call %l4
nop
EXIT_GOOD
nop
setup_p4:
setx stack_top_p4, %g1, %l1
add %l1, 1024, %sp
setx res_buf_fp_p_4, %g1, %o4
setx private_data_p4, %g1, %o5
setx func4, %g1, %l4
call %l4
nop
EXIT_GOOD
nop
setup_p5:
setx stack_top_p5, %g1, %l1
add %l1, 1024, %sp
setx res_buf_fp_p_5, %g1, %o4
setx private_data_p5, %g1, %o5
setx func5, %g1, %l4
call %l4
nop
EXIT_GOOD
nop
setup_p6:
setx stack_top_p6, %g1, %l1
add %l1, 1024, %sp
setx res_buf_fp_p_6, %g1, %o4
setx private_data_p6, %g1, %o5
setx func6, %g1, %l4
call %l4
nop
EXIT_GOOD
nop
setup_p7:
setx stack_top_p7, %g1, %l1
add %l1, 1024, %sp
setx res_buf_fp_p_7, %g1, %o4
setx private_data_p7, %g1, %o5
setx func7, %g1, %l4
call %l4
nop
EXIT_GOOD
nop
#define NO_REAL_CPUS_MINUS_1 7
!-----------------
! register usage:
! %i0 %i1 : base registers for first 2 regions
! %i2 %i3 : cache registers for 8 regions
! %i4 fixed pointer to per-cpu results area
! %l1 moving pointer to per-cpu FP results area
! %o7 moving pointer to per-cpu integer results area
! %i5 pointer to per-cpu private area
! %l0 holds lfsr, used as source of random bits
! %l2 loop count register
! %f16 running counter for unique fp store values
! %f17 holds increment value for fp counter
! %l4 running counter for unique integer store values (increment value is always 1)
! %l5 move-to register for load values (simulation only)
! %f30 move-to register for FP values (simulation only)
! %l3 %l6 %l7 %o5 : 4 temporary registers
! %o0 %o1 %o2 %o3 %o4 : 5 integer results buffer registers
! %f0-f15 FP results buffer registers
! %f32-f47 FP block load/store registers
func0:
! 1000 (dynamic) instruction sequence begins
save %sp, -192, %sp
! Force %i0-%i3 to be 64-byte aligned
add %i0, 63, %i0
andn %i0, 63, %i0
add %i1, 63, %i1
andn %i1, 63, %i1
add %i2, 63, %i2
andn %i2, 63, %i2
add %i3, 63, %i3
andn %i3, 63, %i3
add %i4, 63, %i4
andn %i4, 63, %i4
add %i5, 63, %i5
andn %i5, 63, %i5
! Initialize pointer to FP load results area
mov %i4, %l1
! Initialize pointer to integer load results area
sethi %hi(0x80000), %o7
or %o7, %lo(0x80000), %o7
add %o7, %l1, %o7
! Initialize %f0-%f62 to 0xdeadbee0deadbee1
sethi %hi(0xdeadbee0), %l6
or %l6, %lo(0xdeadbee0), %l6
stw %l6, [%i5]
sethi %hi(0xdeadbee1), %l6
or %l6, %lo(0xdeadbee1), %l6
stw %l6, [%i5+4]
ldd [%i5], %f0
fmovd %f0, %f2
fmovd %f0, %f4
fmovd %f0, %f6
fmovd %f0, %f8
fmovd %f0, %f10
fmovd %f0, %f12
fmovd %f0, %f14
fmovd %f0, %f16
fmovd %f0, %f18
fmovd %f0, %f20
fmovd %f0, %f22
fmovd %f0, %f24
fmovd %f0, %f26
fmovd %f0, %f28
fmovd %f0, %f30
fmovd %f0, %f32
fmovd %f0, %f34
fmovd %f0, %f36
fmovd %f0, %f38
fmovd %f0, %f40
fmovd %f0, %f42
fmovd %f0, %f44
fmovd %f0, %f46
fmovd %f0, %f48
fmovd %f0, %f50
fmovd %f0, %f52
fmovd %f0, %f54
fmovd %f0, %f56
fmovd %f0, %f58
fmovd %f0, %f60
fmovd %f0, %f62
! Signature for extract_loads script to start extracting load values for this stream
sethi %hi(0x00deade1), %l6
or %l6, %lo(0x00deade1), %l6
stw %l6, [%i5]
ld [%i5], %f16
! Initialize running integer counter in register %l4
sethi %hi(0x1), %l4
or %l4, %lo(0x1), %l4
! Initialize running FP counter in register %f16
sethi %hi(0x3f800001), %l6
or %l6, %lo(0x3f800001), %l6
stw %l6, [%i5]
ld [%i5], %f16
! Initialize FP counter increment value in register %f17 (constant)
sethi %hi(0x34000000), %l6
or %l6, %lo(0x34000000), %l6
stw %l6, [%i5]
ld [%i5], %f17
! Initialize LFSR to 0x3caf^4
sethi %hi(0x3caf), %l0
or %l0, %lo(0x3caf), %l0
mulx %l0, %l0, %l0
mulx %l0, %l0, %l0
BEGIN_NODES0: ! Test instruction sequence for CPU 0 begins
P1: !_BLD [30] (FP) (Loop entry) (Loop exit) (CBR)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_0:
wr %g0, 0xf0, %asi
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET1
nop
RET1:
! lfsr step begin
srlx %l0, 1, %o5
xnor %o5, %l0, %o5
sllx %o5, 63, %o5
or %o5, %l0, %l0
srlx %l0, 1, %l0
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_0_0:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_0
nop
P2: !_BLD [3] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_1:
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i0 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P3: !_LD [9] (Int)
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4: !_LD [0] (Int) (Loop exit) (LE)
wr %g0, 0x88, %asi
lduwa [%i0 + 0] %asi, %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_0_1:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_1
nop
P5: !_LD [22] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_2:
sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P6: !_LD [14] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_0_2:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_2
nop
P7: !_LD [16] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_3:
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
ld [%i3 + 0], %f0
! 1 addresses covered
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
loop_exit_0_3:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_3
nop
P8: !_BLD [9] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_4:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_0_4:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_4
nop
P9: !_NOP (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_5:
nop
P10: !_BLD [24] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_0_5:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_5
nop
P11: !_DWLD [16] (Int) (Loop entry) (Loop exit) (Branch target of P230)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_6:
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
ldx [%i2 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_0_6:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_6
nop
ba P12
nop
TARGET230:
ba RET230
nop
P12: !_DWLD [13] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_7:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
P13: !_BLD [29] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_0_7:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_7
nop
P14: !_CAS [23] (maybe <- 0x1) (Int) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_8:
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i3
sub %i0, %i3, %i3
add %i3, 32, %l3
lduw [%l3], %o0
mov %o0, %o5
! move %o5(lower) -> %o0(upper)
sllx %o5, 32, %o0
mov %l4, %l7
cas [%l3], %o5, %l7
! move %l7(lower) -> %o0(lower)
srl %l7, 0, %o5
or %o5, %o0, %o0
add %l4, 1, %l4
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_0_8:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_8
nop
P15: !_BLD [11] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_9:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_0_9:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_9
nop
P16: !_BLD [8] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_10:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P17: !_LD [5] (Int) (Branch target of P451)
lduw [%i1 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
ba P18
nop
TARGET451:
ba RET451
nop
P18: !_LD [21] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_0_10:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_10
nop
P19: !_LD [3] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_11:
lduw [%i0 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P20: !_LD [3] (Int) (Loop exit)
lduw [%i0 + 32], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_0_11:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_11
nop
P21: !_BLD [10] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_12:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P22: !_BLD [23] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f32
membar #Sync
! 4 addresses covered
fmovd %f32, %f4
fmovd %f34, %f18
fmovs %f19, %f6
fmovd %f40, %f18
fmovs %f18, %f7
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovd %f4, %f30
fmovd %f6, %f30
!--
loop_exit_0_12:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_12
nop
P23: !_CASX [24] (maybe <- 0x2) (Int) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_13:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
sub %i0, %i3, %i3
ldx [%i3], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
mov %o0, %l3
sllx %l4, 32, %o1
add %l4, 1, %l4
or %l4, %o1, %o1
casx [%i3], %l3, %o1
! move %o1(upper) -> %o1(upper)
! move %o1(lower) -> %o1(lower)
add %l4, 1, %l4
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_0_13:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_13
nop
P24: !_BST [24] (maybe <- 0x3f800001) (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_14:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i2
sub %i0, %i2, %i2
! preparing store val #0, next val will be in f32
fmovs %f16, %f20
fadds %f16, %f17, %f16
! preparing store val #1, next val will be in f33
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #2, next val will be in f35
fmovd %f20, %f32
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #3, next val will be in f40
fmovd %f20, %f34
fmovs %f16, %f20
fadds %f16, %f17, %f16
fmovd %f20, %f40
membar #Sync
stda %f32, [%i2 + 0 ] %asi
membar #Sync
P25: !_LD [29] (Int)
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P26: !_LD [11] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 32], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_0_14:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_14
nop
P27: !_LD [25] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_15:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P28: !_LD [1] (Int) (Loop exit)
lduw [%i0 + 4], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_0_15:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_15
nop
P29: !_ST [11] (maybe <- 0x4) (Int) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_16:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i2
sub %i0, %i2, %i2
stw %l4, [%i2 + 32 ]
add %l4, 1, %l4
loop_exit_0_16:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_16
nop
P30: !_DWLD [19] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_17:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 32], %o0
! move %o0(upper) -> %o0(upper)
P31: !_LD [19] (Int) (Loop exit)
lduw [%i3 + 32], %l6
! move %l6(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_0_17:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_17
nop
P32: !_LD [3] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_18:
lduw [%i0 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P33: !_LD [8] (FP) (Branch target of P292)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i2
sub %i0, %i2, %i2
ld [%i2 + 0], %f0
! 1 addresses covered
ba P34
nop
TARGET292:
ba RET292
nop
P34: !_LD [15] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
loop_exit_0_18:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_18
nop
P35: !_SWAP [6] (maybe <- 0x5) (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_19:
mov %l4, %o0
swap [%i1 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
add %l4, 1, %l4
P36: !_BLD [28] (FP)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P37: !_LD [0] (Int) (Loop exit)
lduw [%i0 + 0], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_0_19:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_19
nop
P38: !_BLD [27] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_20:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P39: !_BLD [1] (FP) (Loop exit)
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i0 + 0] %asi, %f32
membar #Sync
! 4 addresses covered
fmovd %f32, %f4
fmovd %f34, %f18
fmovs %f19, %f6
fmovd %f40, %f18
fmovs %f18, %f7
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovd %f4, %f30
fmovd %f6, %f30
!--
loop_exit_0_20:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_20
nop
P40: !_BLD [18] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_21:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P41: !_DWLD [17] (Int) (Loop exit)
ldx [%i2 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_0_21:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_21
nop
P42: !_BLD [11] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_22:
wr %g0, 0xf0, %asi
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P43: !_BLD [14] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f32
membar #Sync
! 4 addresses covered
fmovd %f32, %f4
fmovd %f34, %f18
fmovs %f19, %f6
fmovd %f40, %f18
fmovs %f18, %f7
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovd %f4, %f30
fmovd %f6, %f30
!--
loop_exit_0_22:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_22
nop
P44: !_DWLD [23] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_23:
sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
ldx [%i3 + 32], %o0
! move %o0(upper) -> %o0(upper)
P45: !_DWLD [24] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 0], %l6
! move %l6(upper) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
srlx %l6, 32, %l3
or %l3, %o0, %o0
! move %l6(lower) -> %o1(upper)
sllx %l6, 32, %o1
P46: !_LD [10] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %l3
! move %l3(lower) -> %o1(lower)
or %l3, %o1, %o1
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_0_23:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_23
nop
P47: !_LD [21] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_24:
sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P48: !_LD [8] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_0_24:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_24
nop
P49: !_BLD [3] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_25:
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i0 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_0_25:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_25
nop
P50: !_BLD [24] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_26:
wr %g0, 0xf0, %asi
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P51: !_ST [5] (maybe <- 0x6) (Int) (Loop exit)
stw %l4, [%i1 + 4 ]
add %l4, 1, %l4
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_0_26:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_26
nop
P52: !_DWLD [2] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_27:
ldx [%i0 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P53: !_LD [4] (Int) (Loop exit)
lduw [%i1 + 0], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_0_27:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_27
nop
P54: !_DWLD [9] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_28:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
P55: !_DWLD [31] (FP) (Loop exit) (CBR)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
sub %i0, %i2, %i2
ldd [%i2 + 32], %f0
! 1 addresses covered
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET55
nop
RET55:
! lfsr step begin
srlx %l0, 1, %o5
xnor %o5, %l0, %o5
sllx %o5, 63, %o5
or %o5, %l0, %l0
srlx %l0, 1, %l0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
loop_exit_0_28:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_28
nop
P56: !_CASX [25] (maybe <- 0x7) (Int) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_29:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
sub %i0, %i3, %i3
ldx [%i3], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
mov %o0, %l7
sllx %l4, 32, %o1
add %l4, 1, %l4
or %l4, %o1, %o1
casx [%i3], %l7, %o1
! move %o1(upper) -> %o1(upper)
! move %o1(lower) -> %o1(lower)
add %l4, 1, %l4
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_0_29:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_29
nop
P57: !_LD [4] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_30:
lduw [%i1 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P58: !_BSTC [24] (maybe <- 0x3f800005) (FP)
wr %g0, 0xe0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i2
sub %i0, %i2, %i2
! preparing store val #0, next val will be in f32
fmovs %f16, %f20
fadds %f16, %f17, %f16
! preparing store val #1, next val will be in f33
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #2, next val will be in f35
fmovd %f20, %f32
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #3, next val will be in f40
fmovd %f20, %f34
fmovs %f16, %f20
fadds %f16, %f17, %f16
fmovd %f20, %f40
membar #Sync
stda %f32, [%i2 + 0 ] %asi
membar #Sync
P59: !_LD [29] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 4], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_0_30:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_30
nop
P60: !_LD [27] (Int) (Loop entry) (Branch target of P520)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_31:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
ba P61
nop
TARGET520:
ba RET520
nop
P61: !_LD [19] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_0_31:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_31
nop
P62: !_LD [23] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_32:
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P63: !_CAS [21] (maybe <- 0x9) (Int) (LE)
! Change single-word-level endianess (big endian <-> little endian)
sethi %hi(0xff00ff00), %l7
or %l7, %lo(0xff00ff00), %l7
and %l4, %l7, %l6
srl %l6, 8, %l6
sll %l4, 8, %o5
and %o5, %l7, %o5
or %o5, %l6, %o5
srl %o5, 16, %l6
sll %o5, 16, %o5
srl %o5, 0, %o5
or %o5, %l6, %o5
wr %g0, 0x88, %asi
add %i2, 4, %l7
lduwa [%l7] %asi, %l3
mov %l3, %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
mov %o5, %o1
casa [%l7] %asi, %l6, %o1
! move %o1(lower) -> %o1(upper)
sllx %o1, 32, %o1
add %l4, 1, %l4
P64: !_LD [4] (Int) (Loop exit)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 4
sethi %hi(0xc0000), %l6
sub %i1, %l6, %i1
lduw [%i1 + 0], %o5
! move %o5(lower) -> %o1(lower)
or %o5, %o1, %o1
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
sethi %hi(0xc0000), %l3
add %i1, %l3, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_0_32:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_32
nop
P65: !_DWLD [6] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_33:
ldx [%i1 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P66: !_LD [26] (Int) (Loop exit)
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 12], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_0_33:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_33
nop
P67: !_DWLD [24] (Int) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_34:
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
ldx [%i2 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_0_34:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_34
nop
P68: !_BLD [21] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_35:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_0_35:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_35
nop
P69: !_BLD [23] (FP) (Loop entry) (Branch target of P389)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_36:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
ba P70
nop
TARGET389:
ba RET389
nop
P70: !_LD [29] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P71: !_LD [21] (Int) (Loop exit)
lduw [%i2 + 4], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_0_36:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_36
nop
P72: !_LD [17] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_37:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P73: !_LD [28] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_0_37:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_37
nop
P74: !_LD [3] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_38:
lduw [%i0 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P75: !_LD [8] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 0], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_0_38:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_38
nop
P76: !_DWLD [7] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_39:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 7
sethi %hi(0xc0000), %l7
sub %i1, %l7, %i1
ldx [%i1 + 32], %o0
! move %o0(upper) -> %o0(upper)
P77: !_LD [1] (Int) (Loop exit) (CBR)
lduw [%i0 + 4], %l7
! move %l7(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %l7, %o0, %o0
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET77
nop
RET77:
! lfsr step begin
srlx %l0, 1, %o5
xnor %o5, %l0, %o5
sllx %o5, 63, %o5
or %o5, %l0, %l0
srlx %l0, 1, %l0
!---- flushing int results buffer----
mov %o0, %l5
sethi %hi(0xc0000), %l3
add %i1, %l3, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_0_39:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_39
nop
P78: !_CAS [28] (maybe <- 0xa) (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_40:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3], %o0
mov %o0, %l7
! move %l7(lower) -> %o0(upper)
sllx %l7, 32, %o0
mov %l4, %l6
cas [%i3], %l7, %l6
! move %l6(lower) -> %o0(lower)
srl %l6, 0, %l7
or %l7, %o0, %o0
add %l4, 1, %l4
P79: !_DWLD [8] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 0], %o1
! move %o1(upper) -> %o1(upper)
! move %o1(lower) -> %o1(lower)
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_0_40:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_40
nop
P80: !_MEMBAR (Int) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_41:
membar #StoreLoad
loop_exit_0_41:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_41
nop
P81: !_BLD [16] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_42:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_0_42:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_42
nop
P82: !_DWLD [25] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_43:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
P83: !_BLD [23] (FP) (Loop exit) (Branch target of P434)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_0_43:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_43
nop
ba P84
nop
TARGET434:
ba RET434
nop
P84: !_LD [5] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_44:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 5
sethi %hi(0xc0000), %l3
sub %i1, %l3, %i1
lduw [%i1 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P85: !_BLD [30] (FP)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P86: !_LD [9] (Int) (Loop exit)
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 4], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
sethi %hi(0xc0000), %l7
add %i1, %l7, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_0_44:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_44
nop
P87: !_LD [27] (Int) (Loop entry) (LE)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_45:
wr %g0, 0x88, %asi
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduwa [%i2 + 32] %asi, %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P88: !_DWLD [3] (FP)
ldd [%i0 + 32], %f0
! 1 addresses covered
P89: !_LD [27] (Int) (Loop exit)
lduw [%i2 + 32], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
loop_exit_0_45:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_45
nop
P90: !_LD [4] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_46:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 4
sethi %hi(0xc0000), %l6
sub %i1, %l6, %i1
lduw [%i1 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P91: !_LD [22] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
sethi %hi(0xc0000), %l7
add %i1, %l7, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_0_46:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_46
nop
P92: !_BLD [11] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_47:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_0_47:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_47
nop
P93: !_LD [25] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_48:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P94: !_LD [14] (Int) (Loop exit)
sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 12], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_0_48:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_48
nop
P95: !_LD [23] (FP) (Loop entry) (Branch target of P239)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_49:
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
sub %i0, %i3, %i3
ld [%i3 + 32], %f0
! 1 addresses covered
ba P96
nop
TARGET239:
ba RET239
nop
P96: !_DWLD [7] (FP) (Loop exit)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 7
sethi %hi(0xc0000), %o5
sub %i1, %o5, %i1
ldd [%i1 + 32], %f18
! 1 addresses covered
fmovs %f18, %f1
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
!--
sethi %hi(0xc0000), %l3
add %i1, %l3, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_0_49:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_49
nop
P97: !_NOP (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_50:
nop
P98: !_PREFETCH [7] (Int) (Loop exit)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 7
sethi %hi(0xc0000), %l6
sub %i1, %l6, %i1
prefetch [%i1 + 32], 1
sethi %hi(0xc0000), %l7
add %i1, %l7, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_0_50:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_50
nop
P99: !_BLD [26] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_51:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P100: !_CASX [7] (maybe <- 0xb) (Int) (Loop exit) (Branch target of P571)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 7
sethi %hi(0xc0000), %o5
sub %i1, %o5, %i1
add %i1, 32, %l6
ldx [%l6], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
mov %o0, %l3
sllx %l4, 32, %o1
casx [%l6], %l3, %o1
! move %o1(upper) -> %o1(upper)
! move %o1(lower) -> %o1(lower)
add %l4, 1, %l4
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
sethi %hi(0xc0000), %l3
add %i1, %l3, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_0_51:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_51
nop
ba P101
nop
TARGET571:
ba RET571
nop
P101: !_LD [26] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_52:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P102: !_DWLD [3] (Int) (Loop exit)
ldx [%i0 + 32], %l6
! move %l6(upper) -> %o0(lower)
srlx %l6, 32, %l3
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_0_52:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_52
nop
P103: !_DWLD [13] (Int) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_53:
sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
ldx [%i2 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_0_53:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_53
nop
P104: !_LD [15] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_54:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P105: !_LD [4] (Int) (Loop exit)
lduw [%i1 + 0], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_0_54:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_54
nop
P106: !_DWLD [5] (Int) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_55:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 5
sethi %hi(0xc0000), %l3
sub %i1, %l3, %i1
ldx [%i1 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
sethi %hi(0xc0000), %o5
add %i1, %o5, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_0_55:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_55
nop
P107: !_BLD [1] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_56:
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i0 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_0_56:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_56
nop
P108: !_LD [18] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_57:
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P109: !_DWLD [15] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 32], %l6
! move %l6(upper) -> %o0(lower)
srlx %l6, 32, %l3
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_0_57:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_57
nop
P110: !_BLD [15] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_58:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_0_58:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_58
nop
P111: !_BLD [21] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_59:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_0_59:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_59
nop
P112: !_DWLD [15] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_60:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 32], %o0
! move %o0(upper) -> %o0(upper)
P113: !_LD [6] (Int) (Loop exit) (CBR)
lduw [%i1 + 12], %l7
! move %l7(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %l7, %o0, %o0
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET113
nop
RET113:
! lfsr step begin
srlx %l0, 1, %o5
xnor %o5, %l0, %o5
sllx %o5, 63, %o5
or %o5, %l0, %l0
srlx %l0, 1, %l0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_0_60:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_60
nop
P114: !_LD [4] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_61:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 4
sethi %hi(0xc0000), %l6
sub %i1, %l6, %i1
lduw [%i1 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P115: !_LD [13] (Int) (Loop exit) (LE)
wr %g0, 0x88, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduwa [%i3 + 4] %asi, %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
sethi %hi(0xc0000), %l7
add %i1, %l7, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_0_61:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_61
nop
P116: !_PREFETCH [18] (Int) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_62:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
sub %i0, %i2, %i2
prefetch [%i2 + 12], 1
loop_exit_0_62:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_62
nop
P117: !_LD [31] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_63:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i3
sub %i0, %i3, %i3
ld [%i3 + 32], %f0
! 1 addresses covered
P118: !_LD [5] (Int)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 5
sethi %hi(0xc0000), %l6
sub %i1, %l6, %i1
lduw [%i1 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P119: !_LD [23] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 32], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
sethi %hi(0xc0000), %l7
add %i1, %l7, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_0_63:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_63
nop
P120: !_DWLD [17] (Int) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_64:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_0_64:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_64
nop
P121: !_LD [10] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_65:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i2
sub %i0, %i2, %i2
ld [%i2 + 12], %f0
! 1 addresses covered
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
loop_exit_0_65:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_65
nop
P122: !_BLD [8] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_66:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P123: !_BLD [26] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f32
membar #Sync
! 4 addresses covered
fmovd %f32, %f4
fmovd %f34, %f18
fmovs %f19, %f6
fmovd %f40, %f18
fmovs %f18, %f7
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovd %f4, %f30
fmovd %f6, %f30
!--
loop_exit_0_66:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_66
nop
P124: !_LD [30] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_67:
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P125: !_LD [28] (Int) (Loop exit)
lduw [%i3 + 0], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_0_67:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_67
nop
P126: !_BLD [23] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_68:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P127: !_DWLD [31] (Int)
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
ldx [%i3 + 32], %o0
! move %o0(upper) -> %o0(upper)
P128: !_LD [4] (Int) (Loop exit)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 4
sethi %hi(0xc0000), %o5
sub %i1, %o5, %i1
lduw [%i1 + 0], %l6
! move %l6(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
sethi %hi(0xc0000), %l7
add %i1, %l7, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_0_68:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_68
nop
P129: !_DWLD [15] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_69:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 32], %o0
! move %o0(upper) -> %o0(upper)
P130: !_DWLD [26] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 8], %o5
! move %o5(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
srl %o5, 0, %l7
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_0_69:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_69
nop
P131: !_BSTC [22] (maybe <- 0x3f800009) (FP) (Loop entry) (CBR)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_70:
wr %g0, 0xe0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i2
sub %i0, %i2, %i2
! preparing store val #0, next val will be in f32
fmovs %f16, %f20
fadds %f16, %f17, %f16
! preparing store val #1, next val will be in f33
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #2, next val will be in f35
fmovd %f20, %f32
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #3, next val will be in f40
fmovd %f20, %f34
fmovs %f16, %f20
fadds %f16, %f17, %f16
fmovd %f20, %f40
membar #Sync
stda %f32, [%i2 + 0 ] %asi
membar #Sync
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET131
nop
RET131:
! lfsr step begin
srlx %l0, 1, %l3
xnor %l3, %l0, %l3
sllx %l3, 63, %l3
or %l3, %l0, %l0
srlx %l0, 1, %l0
P132: !_BLD [7] (FP) (Loop exit)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 7
sethi %hi(0xc0000), %l6
sub %i1, %l6, %i1
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
sethi %hi(0xc0000), %l7
add %i1, %l7, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_0_70:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_70
nop
P133: !_BLD [18] (FP) (Loop entry) (Branch target of P502)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_71:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
ba P134
nop
TARGET502:
ba RET502
nop
P134: !_DWLD [17] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_0_71:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_71
nop
P135: !_BLD [6] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_72:
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_0_72:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_72
nop
P136: !_DWLD [16] (Int) (Loop entry) (Loop exit) (LE)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_73:
wr %g0, 0x88, %asi
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
ldxa [%i3 + 0] %asi, %l7
! move %l7(lower) -> %o0(upper)
sllx %l7, 32, %o0
! move %l7(upper) -> %o0(lower)
srlx %l7, 32, %l6
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_0_73:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_73
nop
P137: !_DWLD [7] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_74:
ldx [%i1 + 32], %o0
! move %o0(upper) -> %o0(upper)
P138: !_LD [27] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 32], %l3
! move %l3(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_0_74:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_74
nop
P139: !_LD [2] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_75:
lduw [%i0 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P140: !_LD [10] (FP) (CBR)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i3
sub %i0, %i3, %i3
ld [%i3 + 12], %f0
! 1 addresses covered
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET140
nop
RET140:
! lfsr step begin
srlx %l0, 1, %l6
xnor %l6, %l0, %l6
sllx %l6, 63, %l6
or %l6, %l0, %l0
srlx %l0, 1, %l0
P141: !_LD [10] (Int) (Loop exit)
lduw [%i3 + 12], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
loop_exit_0_75:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_75
nop
P142: !_LD [10] (Int) (Loop entry) (LE)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_76:
wr %g0, 0x88, %asi
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduwa [%i2 + 12] %asi, %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P143: !_LD [8] (Int) (Loop exit)
lduw [%i2 + 0], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_0_76:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_76
nop
P144: !_BLD [26] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_77:
wr %g0, 0xf0, %asi
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P145: !_BLD [22] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f32
membar #Sync
! 4 addresses covered
fmovd %f32, %f4
fmovd %f34, %f18
fmovs %f19, %f6
fmovd %f40, %f18
fmovs %f18, %f7
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovd %f4, %f30
fmovd %f6, %f30
!--
loop_exit_0_77:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_77
nop
P146: !_BLD [22] (FP) (Loop entry) (CBR)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_78:
wr %g0, 0xf0, %asi
sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET146
nop
RET146:
! lfsr step begin
srlx %l0, 1, %l7
xnor %l7, %l0, %l7
sllx %l7, 63, %l7
or %l7, %l0, %l0
srlx %l0, 1, %l0
P147: !_LD [12] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P148: !_LD [14] (Int) (Loop exit)
sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 12], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_0_78:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_78
nop
P149: !_SWAP [3] (maybe <- 0xc) (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_79:
mov %l4, %o0
swap [%i0 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
add %l4, 1, %l4
P150: !_DWLD [18] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 8], %l7
! move %l7(lower) -> %o0(lower)
srl %l7, 0, %l6
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_0_79:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_79
nop
P151: !_CAS [5] (maybe <- 0xd) (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_80:
add %i1, 4, %l6
lduw [%l6], %o0
mov %o0, %l3
! move %l3(lower) -> %o0(upper)
sllx %l3, 32, %o0
mov %l4, %o5
cas [%l6], %l3, %o5
! move %o5(lower) -> %o0(lower)
srl %o5, 0, %l3
or %l3, %o0, %o0
add %l4, 1, %l4
P152: !_BLD [3] (FP) (Loop exit) (Branch target of P247)
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i0 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_0_80:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_80
nop
ba P153
nop
TARGET247:
ba RET247
nop
P153: !_LD [28] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_81:
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P154: !_LD [5] (Int) (Loop exit)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 5
sethi %hi(0xc0000), %l3
sub %i1, %l3, %i1
lduw [%i1 + 4], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
sethi %hi(0xc0000), %o5
add %i1, %o5, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_0_81:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_81
nop
P155: !_CASX [31] (maybe <- 0xe) (Int) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_82:
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
add %i2, 32, %l6
ldx [%l6], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
mov %o0, %l3
sllx %l4, 32, %o1
casx [%l6], %l3, %o1
! move %o1(upper) -> %o1(upper)
! move %o1(lower) -> %o1(lower)
add %l4, 1, %l4
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_0_82:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_82
nop
P156: !_DWLD [20] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_83:
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
P157: !_BLD [21] (FP) (Loop exit)
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_0_83:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_83
nop
P158: !_LD [25] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_84:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P159: !_LD [2] (Int) (Loop exit)
lduw [%i0 + 12], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_0_84:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_84
nop
P160: !_CASX [15] (maybe <- 0xf) (Int) (Loop entry) (Loop exit) (LE) (CBR)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_85:
! Change single-word-level endianess (big endian <-> little endian)
sethi %hi(0xff00ff00), %l6
or %l6, %lo(0xff00ff00), %l6
and %l4, %l6, %l3
srl %l3, 8, %l3
sll %l4, 8, %l7
and %l7, %l6, %l7
or %l7, %l3, %l7
srl %l7, 16, %l3
sll %l7, 16, %l7
srl %l7, 0, %l7
or %l7, %l3, %l7
wr %g0, 0x88, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i3
sub %i0, %i3, %i3
add %i3, 32, %l6
ldxa [%l6] %asi, %o5
! move %o5(lower) -> %o0(upper)
sllx %o5, 32, %o0
! move %o5(upper) -> %o0(lower)
srlx %o5, 32, %l3
or %l3, %o0, %o0
mov %o5, %l3
mov %l7, %o5
casxa [%l6] %asi, %l3, %o5
! move %o5(lower) -> %o1(upper)
sllx %o5, 32, %o1
! move %o5(upper) -> %o1(lower)
srlx %o5, 32, %l3
or %l3, %o1, %o1
add %l4, 1, %l4
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET160
nop
RET160:
! lfsr step begin
srlx %l0, 1, %l3
xnor %l3, %l0, %l3
sllx %l3, 63, %l3
or %l3, %l0, %l0
srlx %l0, 1, %l0
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_0_85:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_85
nop
P161: !_DWLD [25] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_86:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
P162: !_BLD [6] (FP) (Loop exit)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 6
sethi %hi(0xc0000), %l3
sub %i1, %l3, %i1
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
sethi %hi(0xc0000), %l6
add %i1, %l6, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_0_86:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_86
nop
P163: !_CASX [27] (maybe <- 0x10) (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_87:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
sub %i0, %i3, %i3
add %i3, 32, %o5
ldx [%o5], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
mov %o0, %l7
sllx %l4, 32, %o1
casx [%o5], %l7, %o1
! move %o1(upper) -> %o1(upper)
! move %o1(lower) -> %o1(lower)
add %l4, 1, %l4
P164: !_BLD [12] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_0_87:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_87
nop
P165: !_DWLD [8] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_88:
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
ldx [%i3 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
P166: !_BLD [2] (FP) (Loop exit) (Branch target of P406)
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i0 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_0_88:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_88
nop
ba P167
nop
TARGET406:
ba RET406
nop
P167: !_BLD [24] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_89:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_0_89:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_89
nop
P168: !_LD [25] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_90:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P169: !_BLD [15] (FP)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P170: !_LD [30] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_0_90:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_90
nop
P171: !_LD [13] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_91:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P172: !_LD [30] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_0_91:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_91
nop
P173: !_DWLD [31] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_92:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 32], %o0
! move %o0(upper) -> %o0(upper)
P174: !_LD [29] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 4], %l7
! move %l7(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_0_92:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_92
nop
P175: !_LD [19] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_93:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P176: !_DWLD [28] (Int)
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
ldx [%i3 + 0], %l3
! move %l3(upper) -> %o0(lower)
srlx %l3, 32, %o5
or %o5, %o0, %o0
! move %l3(lower) -> %o1(upper)
sllx %l3, 32, %o1
P177: !_LD [2] (Int) (Loop exit)
lduw [%i0 + 12], %l7
! move %l7(lower) -> %o1(lower)
or %l7, %o1, %o1
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_0_93:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_93
nop
P178: !_LD [1] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_94:
lduw [%i0 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P179: !_LD [19] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 32], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_0_94:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_94
nop
P180: !_DWLD [26] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_95:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P181: !_LD [15] (Int) (Loop exit) (CBR)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 32], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET181
nop
RET181:
! lfsr step begin
srlx %l0, 1, %o5
xnor %o5, %l0, %o5
sllx %o5, 63, %o5
or %o5, %l0, %l0
srlx %l0, 1, %l0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_0_95:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_95
nop
P182: !_LD [24] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_96:
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P183: !_LD [6] (Int) (Loop exit)
lduw [%i1 + 12], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_0_96:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_96
nop
P184: !_DWLD [16] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_97:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
P185: !_LD [3] (Int)
lduw [%i0 + 32], %o1
! move %o1(lower) -> %o1(upper)
sllx %o1, 32, %o1
P186: !_LD [20] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %l7
! move %l7(lower) -> %o1(lower)
or %l7, %o1, %o1
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_0_97:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_97
nop
P187: !_LD [1] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_98:
lduw [%i0 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P188: !_LD [21] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_0_98:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_98
nop
P189: !_BLD [4] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_99:
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_0_99:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_99
nop
P190: !_LD [13] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_100:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P191: !_LD [10] (Int) (Loop exit)
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 12], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_0_100:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_100
nop
P192: !_BLD [20] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_101:
wr %g0, 0xf0, %asi
sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_0_101:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_101
nop
P193: !_NOP (Int) (Loop entry) (Branch target of P181)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_102:
nop
ba P194
nop
TARGET181:
ba RET181
nop
P194: !_BLD [22] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_0_102:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_102
nop
P195: !_BLD [0] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_103:
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i0 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P196: !_LD [29] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P197: !_LD [10] (Int) (Loop exit)
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 12], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_0_103:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_103
nop
P198: !_DWLD [5] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_104:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 5
sethi %hi(0xc0000), %o5
sub %i1, %o5, %i1
ldx [%i1 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
P199: !_LD [13] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 4], %o1
! move %o1(lower) -> %o1(upper)
sllx %o1, 32, %o1
P200: !_LD [30] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %l7
! move %l7(lower) -> %o1(lower)
or %l7, %o1, %o1
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
sethi %hi(0xc0000), %o5
add %i1, %o5, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_0_104:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_104
nop
P201: !_BLD [3] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_105:
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i0 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_0_105:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_105
nop
P202: !_DWLD [5] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_106:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 5
sethi %hi(0xc0000), %l6
sub %i1, %l6, %i1
ldx [%i1 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
P203: !_NOP (Int) (Loop exit)
nop
!---- flushing int results buffer----
mov %o0, %l5
sethi %hi(0xc0000), %l3
add %i1, %l3, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_0_106:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_106
nop
P204: !_CASX [20] (maybe <- 0x11) (Int) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_107:
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
sub %i0, %i3, %i3
ldx [%i3], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
mov %o0, %l7
sllx %l4, 32, %o1
add %l4, 1, %l4
or %l4, %o1, %o1
casx [%i3], %l7, %o1
! move %o1(upper) -> %o1(upper)
! move %o1(lower) -> %o1(lower)
add %l4, 1, %l4
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_0_107:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_107
nop
P205: !_DWLD [28] (Int) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_108:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_0_108:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_108
nop
P206: !_BLD [18] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_109:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P207: !_BLD [7] (FP) (Loop exit)
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f32
membar #Sync
! 4 addresses covered
fmovd %f32, %f4
fmovd %f34, %f18
fmovs %f19, %f6
fmovd %f40, %f18
fmovs %f18, %f7
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovd %f4, %f30
fmovd %f6, %f30
!--
loop_exit_0_109:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_109
nop
P208: !_BLD [2] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_110:
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i0 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_0_110:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_110
nop
P209: !_LD [31] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_111:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P210: !_LD [16] (Int) (Loop exit)
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 0], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_0_111:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_111
nop
P211: !_DWLD [3] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_112:
ldx [%i0 + 32], %o0
! move %o0(upper) -> %o0(upper)
P212: !_LD [9] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %l3
! move %l3(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_0_112:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_112
nop
P213: !_DWLD [19] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_113:
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
ldx [%i3 + 32], %o0
! move %o0(upper) -> %o0(upper)
P214: !_LD [16] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 0], %l7
! move %l7(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_0_113:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_113
nop
P215: !_DWLD [13] (Int) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_114:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_0_114:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_114
nop
P216: !_BLD [12] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_115:
wr %g0, 0xf0, %asi
sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P217: !_BLD [7] (FP) (Loop exit)
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f32
membar #Sync
! 4 addresses covered
fmovd %f32, %f4
fmovd %f34, %f18
fmovs %f19, %f6
fmovd %f40, %f18
fmovs %f18, %f7
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovd %f4, %f30
fmovd %f6, %f30
!--
loop_exit_0_115:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_115
nop
P218: !_BLD [6] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_116:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 6
sethi %hi(0xc0000), %l6
sub %i1, %l6, %i1
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
sethi %hi(0xc0000), %l7
add %i1, %l7, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_0_116:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_116
nop
P219: !_DWST [5] (maybe <- 0x13) (Int) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_117:
sllx %l4, 32, %o5
add %l4, 1, %l4
or %o5, %l4, %o5
stx %o5, [%i1 + 0]
add %l4, 1, %l4
loop_exit_0_117:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_117
nop
P220: !_LD [21] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_118:
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P221: !_CASX [12] (maybe <- 0x15) (Int)
sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
ldx [%i2], %l6
! move %l6(upper) -> %o0(lower)
srlx %l6, 32, %l7
or %l7, %o0, %o0
! move %l6(lower) -> %o1(upper)
sllx %l6, 32, %o1
mov %l6, %l7
sllx %l4, 32, %l6
add %l4, 1, %l4
or %l4, %l6, %l6
casx [%i2], %l7, %l6
! move %l6(upper) -> %o1(lower)
srlx %l6, 32, %l7
or %l7, %o1, %o1
! move %l6(lower) -> %o2(upper)
sllx %l6, 32, %o2
add %l4, 1, %l4
P222: !_LD [5] (Int) (Loop exit)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 5
sethi %hi(0xc0000), %l7
sub %i1, %l7, %i1
lduw [%i1 + 4], %l3
! move %l3(lower) -> %o2(lower)
or %l3, %o2, %o2
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
mov %o2, %l5
sethi %hi(0xc0000), %l6
add %i1, %l6, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_0_118:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_118
nop
P223: !_DWLD [5] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_119:
ldx [%i1 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
P224: !_BLD [30] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_0_119:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_119
nop
P225: !_DWLD [0] (Int) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_120:
ldx [%i0 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_0_120:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_120
nop
P226: !_DWLD [1] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_121:
ldx [%i0 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
P227: !_DWLD [23] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 32], %o1
! move %o1(upper) -> %o1(upper)
P228: !_LD [28] (Int) (Loop exit)
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 0], %l3
! move %l3(lower) -> %o1(lower)
srlx %o1, 32, %o1
sllx %o1, 32, %o1
or %l3, %o1, %o1
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_0_121:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_121
nop
P229: !_DWLD [1] (Int) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_122:
ldx [%i0 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_0_122:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_122
nop
P230: !_CAS [11] (maybe <- 0x17) (Int) (Loop entry) (CBR)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_123:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
sub %i0, %i2, %i2
add %i2, 32, %o5
lduw [%o5], %o0
mov %o0, %l7
! move %l7(lower) -> %o0(upper)
sllx %l7, 32, %o0
mov %l4, %l6
cas [%o5], %l7, %l6
! move %l6(lower) -> %o0(lower)
srl %l6, 0, %l7
or %l7, %o0, %o0
add %l4, 1, %l4
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET230
nop
RET230:
! lfsr step begin
srlx %l0, 1, %l7
xnor %l7, %l0, %l7
sllx %l7, 63, %l7
or %l7, %l0, %l0
srlx %l0, 1, %l0
P231: !_DWLD [9] (Int) (Loop exit) (Branch target of P540)
ldx [%i2 + 0], %o1
! move %o1(upper) -> %o1(upper)
! move %o1(lower) -> %o1(lower)
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_0_123:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_123
nop
ba P232
nop
TARGET540:
ba RET540
nop
P232: !_LD [6] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_124:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 6
sethi %hi(0xc0000), %l7
sub %i1, %l7, %i1
lduw [%i1 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P233: !_DWLD [17] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 0], %l7
! move %l7(upper) -> %o0(lower)
srlx %l7, 32, %l6
or %l6, %o0, %o0
! move %l7(lower) -> %o1(upper)
sllx %l7, 32, %o1
P234: !_LD [4] (Int) (Loop exit)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #2
!Logical addr: 4
sethi %hi(0xc0000), %o5
sub %i1, %o5, %i1
lduw [%i1 + 0], %l6
! move %l6(lower) -> %o1(lower)
or %l6, %o1, %o1
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
sethi %hi(0x180000), %l7
add %i1, %l7, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_0_124:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_124
nop
P235: !_LD [25] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_125:
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P236: !_BLD [6] (FP)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 6
sethi %hi(0xc0000), %l6
sub %i1, %l6, %i1
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P237: !_LD [1] (Int) (Loop exit)
lduw [%i0 + 4], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
sethi %hi(0xc0000), %l3
add %i1, %l3, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_0_125:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_125
nop
P238: !_BLD [12] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_126:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P239: !_DWLD [5] (Int) (Loop exit) (CBR)
ldx [%i1 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET239
nop
RET239:
! lfsr step begin
srlx %l0, 1, %l3
xnor %l3, %l0, %l3
sllx %l3, 63, %l3
or %l3, %l0, %l0
srlx %l0, 1, %l0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_0_126:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_126
nop
P240: !_LD [24] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_127:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P241: !_LD [12] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_0_127:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_127
nop
P242: !_PREFETCH [8] (Int) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_128:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i2
sub %i0, %i2, %i2
prefetch [%i2 + 0], 1
loop_exit_0_128:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_128
nop
P243: !_DWST [29] (maybe <- 0x18) (Int) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_129:
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
sllx %l4, 32, %l7
add %l4, 1, %l4
or %l7, %l4, %l7
stx %l7, [%i3 + 0]
add %l4, 1, %l4
loop_exit_0_129:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_129
nop
P244: !_REPLACEMENT [20] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_130:
sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS3_O), %i2
sub %i0, %i2, %i2
sethi %hi(0x10000), %o5
ld [%i2+0], %l6
st %l6, [%i2+0]
add %i2, %o5, %l3
ld [%l3+0], %l6
st %l6, [%l3+0]
add %l3, %o5, %l3
ld [%l3+0], %l6
st %l6, [%l3+0]
add %l3, %o5, %l3
ld [%l3+0], %l6
st %l6, [%l3+0]
P245: !_BLD [6] (FP) (Loop exit)
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_0_130:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_130
nop
P246: !_LD [4] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_131:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 4
sethi %hi(0xc0000), %o5
sub %i1, %o5, %i1
lduw [%i1 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P247: !_LD [16] (Int) (Loop exit) (CBR)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET247
nop
RET247:
! lfsr step begin
srlx %l0, 1, %l3
xnor %l3, %l0, %l3
sllx %l3, 63, %l3
or %l3, %l0, %l0
srlx %l0, 1, %l0
!---- flushing int results buffer----
mov %o0, %l5
sethi %hi(0xc0000), %l6
add %i1, %l6, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_0_131:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_131
nop
P248: !_REPLACEMENT [15] (Int) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_132:
sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS1_O), %i2
sub %i0, %i2, %i2
sethi %hi(0x10000), %o5
ld [%i2+32], %l6
st %l6, [%i2+32]
add %i2, %o5, %l3
ld [%l3+32], %l6
st %l6, [%l3+32]
add %l3, %o5, %l3
ld [%l3+32], %l6
st %l6, [%l3+32]
add %l3, %o5, %l3
ld [%l3+32], %l6
st %l6, [%l3+32]
loop_exit_0_132:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_132
nop
P249: !_MEMBAR (Int) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_133:
membar #StoreLoad
loop_exit_0_133:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_133
nop
P250: !_LD [17] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_134:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P251: !_BLD [19] (FP)
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P252: !_LD [7] (Int) (Loop exit)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 7
sethi %hi(0xc0000), %o5
sub %i1, %o5, %i1
lduw [%i1 + 32], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
sethi %hi(0xc0000), %l7
add %i1, %l7, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_0_134:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_134
nop
P253: !_DWLD [7] (Int) (Loop entry) (Branch target of P568)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_135:
ldx [%i1 + 32], %o0
! move %o0(upper) -> %o0(upper)
ba P254
nop
TARGET568:
ba RET568
nop
P254: !_BLD [15] (FP)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P255: !_LD [2] (Int) (Loop exit)
lduw [%i0 + 12], %o5
! move %o5(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_0_135:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_135
nop
P256: !_LD [14] (Int) (Loop entry) (CBR)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_136:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET256
nop
RET256:
! lfsr step begin
srlx %l0, 1, %l3
xnor %l3, %l0, %l3
sllx %l3, 63, %l3
or %l3, %l0, %l0
srlx %l0, 1, %l0
P257: !_BLD [16] (FP)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P258: !_LD [31] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_0_136:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_136
nop
P259: !_ST [3] (maybe <- 0x1a) (Int) (Loop entry) (LE)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_137:
wr %g0, 0x88, %asi
! Change single-word-level endianess (big endian <-> little endian)
sethi %hi(0xff00ff00), %l7
or %l7, %lo(0xff00ff00), %l7
and %l4, %l7, %o5
srl %o5, 8, %o5
sll %l4, 8, %l6
and %l6, %l7, %l6
or %l6, %o5, %l6
srl %l6, 16, %o5
sll %l6, 16, %l6
srl %l6, 0, %l6
or %l6, %o5, %l6
stwa %l6, [%i0 + 32] %asi
add %l4, 1, %l4
P260: !_LD [17] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P261: !_LD [10] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_0_137:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_137
nop
P262: !_DWLD [7] (Int) (Loop entry) (Branch target of P1)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_138:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 7
sethi %hi(0xc0000), %l7
sub %i1, %l7, %i1
ldx [%i1 + 32], %o0
! move %o0(upper) -> %o0(upper)
ba P263
nop
TARGET1:
ba RET1
nop
P263: !_LD [31] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 32], %l7
! move %l7(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
sethi %hi(0xc0000), %o5
add %i1, %o5, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_0_138:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_138
nop
P264: !_MEMBAR (Int) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_139:
membar #StoreLoad
loop_exit_0_139:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_139
nop
P265: !_DWLD [4] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_140:
ldx [%i1 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
P266: !_BLD [15] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_0_140:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_140
nop
P267: !_DWST [25] (maybe <- 0x1b) (Int) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_141:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
sub %i0, %i2, %i2
sllx %l4, 32, %l7
add %l4, 1, %l4
or %l7, %l4, %l7
stx %l7, [%i2 + 0]
add %l4, 1, %l4
loop_exit_0_141:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_141
nop
P268: !_MEMBAR (Int) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_142:
membar #StoreLoad
loop_exit_0_142:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_142
nop
P269: !_LD [27] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_143:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P270: !_LD [1] (FP)
ld [%i0 + 4], %f0
! 1 addresses covered
P271: !_LD [14] (Int) (Loop exit)
sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 12], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
loop_exit_0_143:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_143
nop
P272: !_DWLD [0] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_144:
ldx [%i0 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
P273: !_LD [2] (FP) (Loop exit)
ld [%i0 + 12], %f0
! 1 addresses covered
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
loop_exit_0_144:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_144
nop
P274: !_DWLD [14] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_145:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P275: !_LD [28] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 0], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_0_145:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_145
nop
P276: !_DWLD [29] (Int) (Loop entry) (Loop exit) (CBR)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_146:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET276
nop
RET276:
! lfsr step begin
srlx %l0, 1, %o5
xnor %o5, %l0, %o5
sllx %o5, 63, %o5
or %o5, %l0, %l0
srlx %l0, 1, %l0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_0_146:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_146
nop
P277: !_LD [31] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_147:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P278: !_DWLD [17] (Int) (CBR)
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
ldx [%i3 + 0], %l6
! move %l6(upper) -> %o0(lower)
srlx %l6, 32, %l3
or %l3, %o0, %o0
! move %l6(lower) -> %o1(upper)
sllx %l6, 32, %o1
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET278
nop
RET278:
! lfsr step begin
srlx %l0, 1, %l7
xnor %l7, %l0, %l7
sllx %l7, 63, %l7
or %l7, %l0, %l0
srlx %l0, 1, %l0
P279: !_LD [26] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %l3
! move %l3(lower) -> %o1(lower)
or %l3, %o1, %o1
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_0_147:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_147
nop
P280: !_LD [9] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_148:
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P281: !_REPLACEMENT [28] (Int)
sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS2_O), %i2
sub %i0, %i2, %i2
sethi %hi(0x10000), %l6
ld [%i2+0], %o5
st %o5, [%i2+0]
add %i2, %l6, %l7
ld [%l7+0], %o5
st %o5, [%l7+0]
add %l7, %l6, %l7
ld [%l7+0], %o5
st %o5, [%l7+0]
add %l7, %l6, %l7
ld [%l7+0], %o5
st %o5, [%l7+0]
P282: !_LD [2] (Int) (Loop exit)
lduw [%i0 + 12], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_0_148:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_148
nop
P283: !_BLD [11] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_149:
wr %g0, 0xf0, %asi
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P284: !_DWLD [20] (Int) (Loop exit)
sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
ldx [%i2 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_0_149:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_149
nop
P285: !_DWLD [14] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_150:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P286: !_REPLACEMENT [2] (Int)
sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
sethi %hi(0x10000), %o5
ld [%i2+12], %l6
st %l6, [%i2+12]
add %i2, %o5, %l3
ld [%l3+12], %l6
st %l6, [%l3+12]
add %l3, %o5, %l3
ld [%l3+12], %l6
st %l6, [%l3+12]
add %l3, %o5, %l3
ld [%l3+12], %l6
st %l6, [%l3+12]
P287: !_LD [6] (Int) (Loop exit) (LE)
wr %g0, 0x88, %asi
lduwa [%i1 + 12] %asi, %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_0_150:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_150
nop
P288: !_LD [10] (Int) (Loop entry) (Branch target of P348)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_151:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
ba P289
nop
TARGET348:
ba RET348
nop
P289: !_LD [26] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_0_151:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_151
nop
P290: !_DWLD [11] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_152:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 32], %o0
! move %o0(upper) -> %o0(upper)
P291: !_LD [5] (Int) (Loop exit) (LE)
wr %g0, 0x88, %asi
lduwa [%i1 + 4] %asi, %o5
! move %o5(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_0_152:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_152
nop
P292: !_DWLD [29] (Int) (Loop entry) (Loop exit) (CBR)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_153:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET292
nop
RET292:
! lfsr step begin
srlx %l0, 1, %l3
xnor %l3, %l0, %l3
sllx %l3, 63, %l3
or %l3, %l0, %l0
srlx %l0, 1, %l0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_0_153:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_153
nop
P293: !_CASX [20] (maybe <- 0x1d) (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_154:
sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
ldx [%i3], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
mov %o0, %l7
sllx %l4, 32, %o1
add %l4, 1, %l4
or %l4, %o1, %o1
casx [%i3], %l7, %o1
! move %o1(upper) -> %o1(upper)
! move %o1(lower) -> %o1(lower)
add %l4, 1, %l4
P294: !_LD [20] (FP) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i2
sub %i0, %i2, %i2
ld [%i2 + 0], %f0
! 1 addresses covered
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
loop_exit_0_154:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_154
nop
P295: !_BLD [10] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_155:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_0_155:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_155
nop
P296: !_BLD [2] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_156:
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i0 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_0_156:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_156
nop
P297: !_BLD [4] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_157:
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P298: !_DWLD [29] (Int) (Loop exit)
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
ldx [%i2 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_0_157:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_157
nop
P299: !_NOP (Int) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_158:
nop
loop_exit_0_158:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_158
nop
P300: !_DWLD [23] (Int) (Loop entry) (Branch target of P160)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_159:
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 32], %o0
! move %o0(upper) -> %o0(upper)
ba P301
nop
TARGET160:
ba RET160
nop
P301: !_BLD [29] (FP)
wr %g0, 0xf0, %asi
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P302: !_LD [28] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %l6
! move %l6(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_0_159:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_159
nop
P303: !_DWLD [15] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_160:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i2
sub %i0, %i2, %i2
ldd [%i2 + 32], %f0
! 1 addresses covered
P304: !_ST [20] (maybe <- 0x1f) (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i3
sub %i0, %i3, %i3
stw %l4, [%i3 + 0 ]
add %l4, 1, %l4
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
loop_exit_0_160:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_160
nop
P305: !_BLD [26] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_161:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P306: !_LD [26] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P307: !_LD [6] (Int) (Loop exit)
lduw [%i1 + 12], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_0_161:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_161
nop
P308: !_CAS [18] (maybe <- 0x20) (Int) (Loop entry) (CBR)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_162:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
sub %i0, %i2, %i2
add %i2, 12, %l3
lduw [%l3], %o0
mov %o0, %o5
! move %o5(lower) -> %o0(upper)
sllx %o5, 32, %o0
mov %l4, %l7
cas [%l3], %o5, %l7
! move %l7(lower) -> %o0(lower)
srl %l7, 0, %o5
or %o5, %o0, %o0
add %l4, 1, %l4
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET308
nop
RET308:
! lfsr step begin
srlx %l0, 1, %o5
xnor %o5, %l0, %o5
sllx %o5, 63, %o5
or %o5, %l0, %l0
srlx %l0, 1, %l0
P309: !_FLUSHI [30] (Int) (Loop exit)
flush %g0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_0_162:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_162
nop
P310: !_LD [29] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_163:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i3
sub %i0, %i3, %i3
ld [%i3 + 4], %f0
! 1 addresses covered
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
loop_exit_0_163:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_163
nop
P311: !_BLD [28] (FP) (Loop entry) (Branch target of P131)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_164:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
ba P312
nop
TARGET131:
ba RET131
nop
P312: !_DWLD [8] (Int) (Loop exit) (LE)
wr %g0, 0x88, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i3
sub %i0, %i3, %i3
ldxa [%i3 + 0] %asi, %l6
! move %l6(lower) -> %o0(upper)
sllx %l6, 32, %o0
! move %l6(upper) -> %o0(lower)
srlx %l6, 32, %l3
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_0_164:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_164
nop
P313: !_BLD [20] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_165:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_0_165:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_165
nop
P314: !_DWLD [2] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_166:
ldd [%i0 + 8], %f0
! 1 addresses covered
fmovs %f1, %f0
P315: !_BLD [17] (FP) (Loop exit) (CBR)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f32
membar #Sync
! 4 addresses covered
fmovd %f32, %f18
fmovs %f18, %f1
fmovs %f19, %f2
fmovd %f34, %f18
fmovs %f19, %f3
fmovd %f40, %f4
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET315
nop
RET315:
! lfsr step begin
srlx %l0, 1, %l6
xnor %l6, %l0, %l6
sllx %l6, 63, %l6
or %l6, %l0, %l0
srlx %l0, 1, %l0
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovs %f4, %f30
!--
loop_exit_0_166:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_166
nop
P316: !_LD [10] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_167:
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P317: !_LD [5] (Int) (Loop exit)
lduw [%i1 + 4], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_0_167:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_167
nop
P318: !_LD [10] (Int) (Loop entry) (Branch target of P637)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_168:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
ba P319
nop
TARGET637:
ba RET637
nop
P319: !_LD [20] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 0], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_0_168:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_168
nop
P320: !_DWLD [22] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_169:
sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
ldx [%i3 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P321: !_LD [18] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_0_169:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_169
nop
P322: !_DWLD [5] (Int) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_170:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 5
sethi %hi(0xc0000), %l6
sub %i1, %l6, %i1
ldx [%i1 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
sethi %hi(0xc0000), %l3
add %i1, %l3, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_0_170:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_170
nop
P323: !_LD [3] (FP) (Loop entry) (Loop exit) (Branch target of P488)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_171:
ld [%i0 + 32], %f0
! 1 addresses covered
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
loop_exit_0_171:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_171
nop
ba P324
nop
TARGET488:
ba RET488
nop
P324: !_DWLD [28] (Int) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_172:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_0_172:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_172
nop
P325: !_LD [21] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_173:
sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P326: !_LD [10] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_0_173:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_173
nop
P327: !_PREFETCH [10] (Int) (Loop entry) (Loop exit) (Branch target of P528)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_174:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
sub %i0, %i2, %i2
prefetch [%i2 + 12], 1
loop_exit_0_174:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_174
nop
ba P328
nop
TARGET528:
ba RET528
nop
P328: !_LD [18] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_175:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P329: !_BLD [29] (FP)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P330: !_LD [19] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_0_175:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_175
nop
P331: !_BLD [10] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_176:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_0_176:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_176
nop
P332: !_LD [17] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_177:
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
ld [%i3 + 4], %f0
! 1 addresses covered
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
loop_exit_0_177:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_177
nop
P333: !_LD [15] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_178:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P334: !_LD [4] (Int) (Loop exit)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 4
sethi %hi(0xc0000), %l6
sub %i1, %l6, %i1
lduw [%i1 + 0], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
sethi %hi(0xc0000), %l3
add %i1, %l3, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_0_178:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_178
nop
P335: !_LD [17] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_179:
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P336: !_DWLD [19] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 32], %l6
! move %l6(upper) -> %o0(lower)
srlx %l6, 32, %l3
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_0_179:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_179
nop
P337: !_BLD [25] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_180:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_0_180:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_180
nop
P338: !_BLD [27] (FP) (Loop entry) (Loop exit) (Branch target of P447)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_181:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_0_181:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_181
nop
ba P339
nop
TARGET447:
ba RET447
nop
P339: !_DWLD [2] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_182:
ldx [%i0 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P340: !_LD [8] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_0_182:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_182
nop
P341: !_BLD [13] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_183:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P342: !_BLD [27] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f32
membar #Sync
! 4 addresses covered
fmovd %f32, %f4
fmovd %f34, %f18
fmovs %f19, %f6
fmovd %f40, %f18
fmovs %f18, %f7
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovd %f4, %f30
fmovd %f6, %f30
!--
loop_exit_0_183:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_183
nop
P343: !_NOP (Int) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_184:
nop
loop_exit_0_184:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_184
nop
P344: !_BLD [9] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_185:
wr %g0, 0xf0, %asi
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_0_185:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_185
nop
P345: !_LD [16] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_186:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P346: !_LD [27] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 32], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_0_186:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_186
nop
P347: !_BST [19] (maybe <- 0x3f80000d) (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_187:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
sub %i0, %i3, %i3
! preparing store val #0, next val will be in f32
fmovs %f16, %f20
fadds %f16, %f17, %f16
! preparing store val #1, next val will be in f33
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #2, next val will be in f35
fmovd %f20, %f32
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #3, next val will be in f40
fmovd %f20, %f34
fmovs %f16, %f20
fadds %f16, %f17, %f16
fmovd %f20, %f40
membar #Sync
stda %f32, [%i3 + 0 ] %asi
membar #Sync
loop_exit_0_187:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_187
nop
P348: !_DWLD [0] (Int) (Loop entry) (Loop exit) (CBR)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_188:
ldx [%i0 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET348
nop
RET348:
! lfsr step begin
srlx %l0, 1, %l7
xnor %l7, %l0, %l7
sllx %l7, 63, %l7
or %l7, %l0, %l0
srlx %l0, 1, %l0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_0_188:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_188
nop
P349: !_BLD [26] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_189:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P350: !_DWLD [28] (Int) (Loop exit)
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
ldx [%i3 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_0_189:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_189
nop
P351: !_LD [5] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_190:
lduw [%i1 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P352: !_BLD [6] (FP)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 6
sethi %hi(0xc0000), %l7
sub %i1, %l7, %i1
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P353: !_LD [28] (Int) (Loop exit)
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 0], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
sethi %hi(0xc0000), %l6
add %i1, %l6, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_0_190:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_190
nop
P354: !_BLD [18] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_191:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P355: !_BST [10] (maybe <- 0x3f800011) (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
! preparing store val #0, next val will be in f32
fmovs %f16, %f20
fadds %f16, %f17, %f16
! preparing store val #1, next val will be in f33
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #2, next val will be in f35
fmovd %f20, %f32
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #3, next val will be in f40
fmovd %f20, %f34
fmovs %f16, %f20
fadds %f16, %f17, %f16
fmovd %f20, %f40
membar #Sync
stda %f32, [%i2 + 0 ] %asi
membar #Sync
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_0_191:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_191
nop
P356: !_DWLD [6] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_192:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 6
sethi %hi(0xc0000), %o5
sub %i1, %o5, %i1
ldx [%i1 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P357: !_LD [24] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
sethi %hi(0xc0000), %l3
add %i1, %l3, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_0_192:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_192
nop
P358: !_ST [21] (maybe <- 0x21) (Int) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_193:
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i2
sub %i0, %i2, %i2
stw %l4, [%i2 + 4 ]
add %l4, 1, %l4
loop_exit_0_193:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_193
nop
P359: !_LD [12] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_194:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P360: !_REPLACEMENT [30] (Int)
sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS3_O), %i2
sub %i0, %i2, %i2
sethi %hi(0x10000), %l6
ld [%i2+12], %o5
st %o5, [%i2+12]
add %i2, %l6, %l7
ld [%l7+12], %o5
st %o5, [%l7+12]
add %l7, %l6, %l7
ld [%l7+12], %o5
st %o5, [%l7+12]
add %l7, %l6, %l7
ld [%l7+12], %o5
st %o5, [%l7+12]
P361: !_LD [11] (Int) (Loop exit)
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 32], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_0_194:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_194
nop
P362: !_BLD [2] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_195:
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i0 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_0_195:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_195
nop
P363: !_SWAP [11] (maybe <- 0x22) (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_196:
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
mov %l4, %o0
swap [%i2 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
add %l4, 1, %l4
P364: !_DWLD [7] (Int) (Loop exit)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 7
sethi %hi(0xc0000), %l3
sub %i1, %l3, %i1
ldx [%i1 + 32], %l7
! move %l7(upper) -> %o0(lower)
srlx %l7, 32, %l6
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
sethi %hi(0xc0000), %o5
add %i1, %o5, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_0_196:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_196
nop
P365: !_MEMBAR (Int) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_197:
membar #StoreLoad
loop_exit_0_197:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_197
nop
P366: !_BLD [21] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_198:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P367: !_DWLD [12] (Int) (Loop exit) (Branch target of P424)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_0_198:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_198
nop
ba P368
nop
TARGET424:
ba RET424
nop
P368: !_BLD [17] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_199:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_0_199:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_199
nop
P369: !_LD [10] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_200:
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P370: !_LD [23] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_0_200:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_200
nop
P371: !_BST [11] (maybe <- 0x3f800015) (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_201:
wr %g0, 0xf0, %asi
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
! preparing store val #0, next val will be in f32
fmovs %f16, %f20
fadds %f16, %f17, %f16
! preparing store val #1, next val will be in f33
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #2, next val will be in f35
fmovd %f20, %f32
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #3, next val will be in f40
fmovd %f20, %f34
fmovs %f16, %f20
fadds %f16, %f17, %f16
fmovd %f20, %f40
membar #Sync
stda %f32, [%i2 + 0 ] %asi
membar #Sync
loop_exit_0_201:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_201
nop
P372: !_MEMBAR (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_202:
membar #StoreLoad
P373: !_LD [22] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P374: !_LD [20] (Int) (Loop exit)
sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 0], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_0_202:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_202
nop
P375: !_BLD [18] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_203:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P376: !_DWLD [31] (FP) (Loop exit) (Branch target of P552)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
sub %i0, %i2, %i2
ldd [%i2 + 32], %f4
! 1 addresses covered
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovs %f4, %f30
!--
loop_exit_0_203:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_203
nop
ba P377
nop
TARGET552:
ba RET552
nop
P377: !_DWLD [1] (Int) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_204:
ldx [%i0 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_0_204:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_204
nop
P378: !_BLD [5] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_205:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 5
sethi %hi(0xc0000), %l6
sub %i1, %l6, %i1
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P379: !_DWLD [1] (Int) (Loop exit) (CBR)
ldx [%i0 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET379
nop
RET379:
! lfsr step begin
srlx %l0, 1, %l3
xnor %l3, %l0, %l3
sllx %l3, 63, %l3
or %l3, %l0, %l0
srlx %l0, 1, %l0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
sethi %hi(0xc0000), %l6
add %i1, %l6, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_0_205:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_205
nop
P380: !_LD [10] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_206:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P381: !_LD [22] (Int) (Loop exit)
sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 12], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_0_206:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_206
nop
P382: !_BLD [15] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_207:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_0_207:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_207
nop
P383: !_BLD [7] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_208:
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_0_208:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_208
nop
P384: !_BLD [29] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_209:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P385: !_LD [17] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P386: !_LD [18] (Int) (Loop exit)
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 12], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_0_209:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_209
nop
P387: !_BLD [3] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_210:
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i0 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_0_210:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_210
nop
P388: !_LD [31] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_211:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P389: !_LD [9] (Int) (Loop exit) (CBR)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET389
nop
RET389:
! lfsr step begin
srlx %l0, 1, %l3
xnor %l3, %l0, %l3
sllx %l3, 63, %l3
or %l3, %l0, %l0
srlx %l0, 1, %l0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_0_211:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_211
nop
P390: !_BLD [21] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_212:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_0_212:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_212
nop
P391: !_LD [29] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_213:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P392: !_LD [22] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_0_213:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_213
nop
P393: !_DWLD [2] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_214:
ldd [%i0 + 8], %f0
! 1 addresses covered
fmovs %f1, %f0
P394: !_LD [1] (Int)
lduw [%i0 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P395: !_LD [7] (Int) (Loop exit)
lduw [%i1 + 32], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
loop_exit_0_214:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_214
nop
P396: !_PREFETCH [18] (Int) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_215:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
sub %i0, %i2, %i2
prefetch [%i2 + 12], 1
loop_exit_0_215:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_215
nop
P397: !_LD [10] (Int) (Loop entry) (Branch target of P379)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_216:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
ba P398
nop
TARGET379:
ba RET379
nop
P398: !_LD [10] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_0_216:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_216
nop
P399: !_BLD [7] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_217:
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_0_217:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_217
nop
P400: !_LD [25] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_218:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P401: !_LD [3] (FP)
ld [%i0 + 32], %f0
! 1 addresses covered
P402: !_LD [22] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
loop_exit_0_218:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_218
nop
P403: !_DWLD [9] (Int) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_219:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_0_219:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_219
nop
P404: !_LD [19] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_220:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P405: !_LD [18] (Int) (Loop exit)
lduw [%i2 + 12], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_0_220:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_220
nop
P406: !_LD [26] (FP) (Loop entry) (Loop exit) (CBR)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_221:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i3
sub %i0, %i3, %i3
ld [%i3 + 12], %f0
! 1 addresses covered
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET406
nop
RET406:
! lfsr step begin
srlx %l0, 1, %l7
xnor %l7, %l0, %l7
sllx %l7, 63, %l7
or %l7, %l0, %l0
srlx %l0, 1, %l0
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
loop_exit_0_221:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_221
nop
P407: !_LD [13] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_222:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P408: !_DWLD [22] (Int) (Loop exit)
sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
ldx [%i3 + 8], %l3
! move %l3(lower) -> %o0(lower)
srl %l3, 0, %o5
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_0_222:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_222
nop
P409: !_DWLD [26] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_223:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i2
sub %i0, %i2, %i2
ldd [%i2 + 8], %f0
! 1 addresses covered
fmovs %f1, %f0
P410: !_DWLD [4] (Int) (Loop exit)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 4
sethi %hi(0xc0000), %l7
sub %i1, %l7, %i1
ldx [%i1 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
sethi %hi(0xc0000), %l6
add %i1, %l6, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_0_223:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_223
nop
P411: !_BLD [5] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_224:
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_0_224:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_224
nop
P412: !_DWLD [22] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_225:
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P413: !_LD [7] (Int) (Loop exit)
lduw [%i1 + 32], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_0_225:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_225
nop
P414: !_LD [16] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_226:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i2
sub %i0, %i2, %i2
ld [%i2 + 0], %f0
! 1 addresses covered
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
loop_exit_0_226:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_226
nop
P415: !_LD [6] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_227:
lduw [%i1 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P416: !_LD [28] (Int) (Loop exit)
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 0], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_0_227:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_227
nop
P417: !_LD [11] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_228:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P418: !_LD [3] (Int) (Loop exit)
lduw [%i0 + 32], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_0_228:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_228
nop
P419: !_DWLD [22] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_229:
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P420: !_LD [26] (Int) (Loop exit)
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 12], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_0_229:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_229
nop
P421: !_DWLD [24] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_230:
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
ldx [%i3 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
P422: !_BLD [28] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_0_230:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_230
nop
P423: !_BLD [25] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_231:
wr %g0, 0xf0, %asi
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_0_231:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_231
nop
P424: !_BLD [3] (FP) (Loop entry) (Loop exit) (CBR)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_232:
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i0 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET424
nop
RET424:
! lfsr step begin
srlx %l0, 1, %o5
xnor %o5, %l0, %o5
sllx %o5, 63, %o5
or %o5, %l0, %l0
srlx %l0, 1, %l0
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_0_232:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_232
nop
P425: !_LD [29] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_233:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P426: !_LD [29] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 4], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_0_233:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_233
nop
P427: !_BST [12] (maybe <- 0x3f800019) (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_234:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i2
sub %i0, %i2, %i2
! preparing store val #0, next val will be in f32
fmovs %f16, %f20
fadds %f16, %f17, %f16
! preparing store val #1, next val will be in f33
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #2, next val will be in f35
fmovd %f20, %f32
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #3, next val will be in f40
fmovd %f20, %f34
fmovs %f16, %f20
fadds %f16, %f17, %f16
fmovd %f20, %f40
membar #Sync
stda %f32, [%i2 + 0 ] %asi
membar #Sync
P428: !_LD [4] (Int)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 4
sethi %hi(0xc0000), %l7
sub %i1, %l7, %i1
lduw [%i1 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P429: !_LD [16] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
sethi %hi(0xc0000), %o5
add %i1, %o5, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_0_234:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_234
nop
P430: !_LD [8] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_235:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i2
sub %i0, %i2, %i2
ld [%i2 + 0], %f0
! 1 addresses covered
P431: !_LD [5] (Int)
lduw [%i1 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P432: !_LD [8] (Int) (Loop exit)
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 0], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
loop_exit_0_235:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_235
nop
P433: !_BLD [25] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_236:
wr %g0, 0xf0, %asi
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P434: !_DWLD [9] (Int) (Loop exit) (CBR)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET434
nop
RET434:
! lfsr step begin
srlx %l0, 1, %l7
xnor %l7, %l0, %l7
sllx %l7, 63, %l7
or %l7, %l0, %l0
srlx %l0, 1, %l0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_0_236:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_236
nop
P435: !_BLD [11] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_237:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P436: !_LD [9] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P437: !_LD [13] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_0_237:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_237
nop
P438: !_ST [22] (maybe <- 0x23) (Int) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_238:
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
sub %i0, %i3, %i3
stw %l4, [%i3 + 12 ]
add %l4, 1, %l4
loop_exit_0_238:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_238
nop
P439: !_LD [13] (FP) (Loop entry) (Branch target of P276)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_239:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i2
sub %i0, %i2, %i2
ld [%i2 + 4], %f0
! 1 addresses covered
ba P440
nop
TARGET276:
ba RET276
nop
P440: !_PREFETCH [14] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i3
sub %i0, %i3, %i3
prefetch [%i3 + 12], 1
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
loop_exit_0_239:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_239
nop
P441: !_LD [2] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_240:
lduw [%i0 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P442: !_ST [9] (maybe <- 0x3f80001d) (FP)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i2
sub %i0, %i2, %i2
! preparing store val #0, next val will be in f20
fmovs %f16, %f20
fadds %f16, %f17, %f16
st %f20, [%i2 + 4 ]
P443: !_LD [15] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_0_240:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_240
nop
P444: !_ST [13] (maybe <- 0x24) (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_241:
sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
stw %l4, [%i2 + 4 ]
add %l4, 1, %l4
P445: !_NOP (Int) (Loop exit)
nop
loop_exit_0_241:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_241
nop
P446: !_BLD [18] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_242:
wr %g0, 0xf0, %asi
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_0_242:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_242
nop
P447: !_BLD [10] (FP) (Loop entry) (Loop exit) (CBR)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_243:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET447
nop
RET447:
! lfsr step begin
srlx %l0, 1, %l6
xnor %l6, %l0, %l6
sllx %l6, 63, %l6
or %l6, %l0, %l0
srlx %l0, 1, %l0
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_0_243:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_243
nop
P448: !_DWLD [19] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_244:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 32], %o0
! move %o0(upper) -> %o0(upper)
P449: !_LD [3] (Int) (Loop exit)
lduw [%i0 + 32], %o5
! move %o5(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_0_244:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_244
nop
P450: !_LD [28] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_245:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P451: !_BLD [7] (FP) (CBR)
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET451
nop
RET451:
! lfsr step begin
srlx %l0, 1, %l3
xnor %l3, %l0, %l3
sllx %l3, 63, %l3
or %l3, %l0, %l0
srlx %l0, 1, %l0
P452: !_LD [12] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_0_245:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_245
nop
P453: !_DWLD [23] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_246:
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 32], %o0
! move %o0(upper) -> %o0(upper)
P454: !_LD [9] (Int) (Loop exit)
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 4], %l6
! move %l6(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_0_246:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_246
nop
P455: !_LD [7] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_247:
lduw [%i1 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P456: !_LD [7] (Int) (Loop exit)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 7
sethi %hi(0xc0000), %l6
sub %i1, %l6, %i1
lduw [%i1 + 32], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
sethi %hi(0xc0000), %l3
add %i1, %l3, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_0_247:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_247
nop
P457: !_BLD [11] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_248:
wr %g0, 0xf0, %asi
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P458: !_BLD [5] (FP) (Loop exit)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 5
sethi %hi(0xc0000), %l6
sub %i1, %l6, %i1
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f32
membar #Sync
! 4 addresses covered
fmovd %f32, %f4
fmovd %f34, %f18
fmovs %f19, %f6
fmovd %f40, %f18
fmovs %f18, %f7
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovd %f4, %f30
fmovd %f6, %f30
!--
sethi %hi(0xc0000), %l7
add %i1, %l7, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_0_248:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_248
nop
P459: !_BLD [14] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_249:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_0_249:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_249
nop
P460: !_BLD [25] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_250:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P461: !_BLD [13] (FP) (Loop exit) (Branch target of P564)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f32
membar #Sync
! 4 addresses covered
fmovd %f32, %f4
fmovd %f34, %f18
fmovs %f19, %f6
fmovd %f40, %f18
fmovs %f18, %f7
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovd %f4, %f30
fmovd %f6, %f30
!--
loop_exit_0_250:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_250
nop
ba P462
nop
TARGET564:
ba RET564
nop
P462: !_BLD [26] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_251:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P463: !_BLD [29] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f32
membar #Sync
! 4 addresses covered
fmovd %f32, %f4
fmovd %f34, %f18
fmovs %f19, %f6
fmovd %f40, %f18
fmovs %f18, %f7
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovd %f4, %f30
fmovd %f6, %f30
!--
loop_exit_0_251:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_251
nop
P464: !_BLD [12] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_252:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P465: !_BLD [30] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f32
membar #Sync
! 4 addresses covered
fmovd %f32, %f4
fmovd %f34, %f18
fmovs %f19, %f6
fmovd %f40, %f18
fmovs %f18, %f7
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovd %f4, %f30
fmovd %f6, %f30
!--
loop_exit_0_252:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_252
nop
P466: !_BLD [0] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_253:
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i0 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_0_253:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_253
nop
P467: !_DWLD [10] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_254:
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
ldd [%i2 + 8], %f0
! 1 addresses covered
fmovs %f1, %f0
P468: !_DWLD [29] (Int) (Loop exit)
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
ldx [%i3 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
loop_exit_0_254:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_254
nop
P469: !_DWLD [20] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_255:
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
P470: !_BLD [20] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_0_255:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_255
nop
P471: !_BLD [3] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_256:
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i0 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P472: !_LD [25] (Int) (Branch target of P308)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
ba P473
nop
TARGET308:
ba RET308
nop
P473: !_LD [30] (Int) (Loop exit) (LE)
wr %g0, 0x88, %asi
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduwa [%i3 + 12] %asi, %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_0_256:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_256
nop
P474: !_BLD [20] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_257:
wr %g0, 0xf0, %asi
sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_0_257:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_257
nop
P475: !_BLD [2] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_258:
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i0 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_0_258:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_258
nop
P476: !_BLD [19] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_259:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_0_259:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_259
nop
P477: !_BLD [28] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_260:
wr %g0, 0xf0, %asi
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_0_260:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_260
nop
P478: !_LD [24] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_261:
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P479: !_DWST [17] (maybe <- 0x25) (Int)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i2
sub %i0, %i2, %i2
sllx %l4, 32, %o5
add %l4, 1, %l4
or %o5, %l4, %o5
stx %o5, [%i2 + 0]
add %l4, 1, %l4
P480: !_LD [26] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_0_261:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_261
nop
P481: !_DWLD [5] (Int) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_262:
ldx [%i1 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_0_262:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_262
nop
P482: !_BLD [3] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_263:
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i0 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P483: !_DWLD [23] (FP) (Loop exit)
sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
ldd [%i2 + 32], %f4
! 1 addresses covered
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovs %f4, %f30
!--
loop_exit_0_263:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_263
nop
P484: !_DWLD [17] (Int) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_264:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_0_264:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_264
nop
P485: !_DWLD [27] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_265:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
sub %i0, %i2, %i2
ldd [%i2 + 32], %f0
! 1 addresses covered
P486: !_CAS [31] (maybe <- 0x27) (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
sub %i0, %i3, %i3
add %i3, 32, %l6
lduw [%l6], %o0
mov %o0, %l3
! move %l3(lower) -> %o0(upper)
sllx %l3, 32, %o0
mov %l4, %o5
cas [%l6], %l3, %o5
! move %o5(lower) -> %o0(lower)
srl %o5, 0, %l3
or %l3, %o0, %o0
add %l4, 1, %l4
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
loop_exit_0_265:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_265
nop
P487: !_LD [10] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_266:
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P488: !_BLD [30] (FP) (CBR)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET488
nop
RET488:
! lfsr step begin
srlx %l0, 1, %l3
xnor %l3, %l0, %l3
sllx %l3, 63, %l3
or %l3, %l0, %l0
srlx %l0, 1, %l0
P489: !_LD [14] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_0_266:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_266
nop
P490: !_BLD [8] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_267:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_0_267:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_267
nop
P491: !_BLD [17] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_268:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P492: !_BST [29] (maybe <- 0x3f80001e) (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i3
sub %i0, %i3, %i3
! preparing store val #0, next val will be in f32
fmovs %f16, %f20
fadds %f16, %f17, %f16
! preparing store val #1, next val will be in f33
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #2, next val will be in f35
fmovd %f20, %f32
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #3, next val will be in f40
fmovd %f20, %f34
fmovs %f16, %f20
fadds %f16, %f17, %f16
fmovd %f20, %f40
membar #Sync
stda %f32, [%i3 + 0 ] %asi
membar #Sync
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_0_268:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_268
nop
P493: !_DWLD [25] (Int) (Loop entry) (LE) (Branch target of P315)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_269:
wr %g0, 0x88, %asi
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
sub %i0, %i2, %i2
ldxa [%i2 + 0] %asi, %l3
! move %l3(lower) -> %o0(upper)
sllx %l3, 32, %o0
! move %l3(upper) -> %o0(lower)
srlx %l3, 32, %o5
or %o5, %o0, %o0
ba P494
nop
TARGET315:
ba RET315
nop
P494: !_CASX [21] (maybe <- 0x28) (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i3
sub %i0, %i3, %i3
ldx [%i3], %o1
! move %o1(upper) -> %o1(upper)
! move %o1(lower) -> %o1(lower)
mov %o1, %l7
sllx %l4, 32, %o2
add %l4, 1, %l4
or %l4, %o2, %o2
casx [%i3], %l7, %o2
! move %o2(upper) -> %o2(upper)
! move %o2(lower) -> %o2(lower)
add %l4, 1, %l4
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
mov %o2, %l5
loop_exit_0_269:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_269
nop
P495: !_DWLD [11] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_270:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 32], %o0
! move %o0(upper) -> %o0(upper)
P496: !_LD [25] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 4], %o5
! move %o5(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_0_270:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_270
nop
P497: !_LD [29] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_271:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P498: !_LD [2] (Int) (Loop exit)
lduw [%i0 + 12], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_0_271:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_271
nop
P499: !_LD [13] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_272:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P500: !_LD [27] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 32], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_0_272:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_272
nop
P501: !_BLD [8] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_273:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_0_273:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_273
nop
P502: !_DWLD [30] (Int) (Loop entry) (CBR)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_274:
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
ldx [%i2 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET502
nop
RET502:
! lfsr step begin
srlx %l0, 1, %l6
xnor %l6, %l0, %l6
sllx %l6, 63, %l6
or %l6, %l0, %l0
srlx %l0, 1, %l0
P503: !_LD [11] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_0_274:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_274
nop
P504: !_BLD [7] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_275:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 7
sethi %hi(0xc0000), %l6
sub %i1, %l6, %i1
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P505: !_DWLD [30] (Int)
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
ldx [%i2 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P506: !_LD [4] (Int) (Loop exit)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #2
!Logical addr: 4
sethi %hi(0xc0000), %l3
sub %i1, %l3, %i1
lduw [%i1 + 0], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
sethi %hi(0x180000), %o5
add %i1, %o5, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_0_275:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_275
nop
P507: !_LD [23] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_276:
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P508: !_BLD [24] (FP)
wr %g0, 0xf0, %asi
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P509: !_LD [3] (Int) (Loop exit)
lduw [%i0 + 32], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_0_276:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_276
nop
P510: !_DWLD [22] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_277:
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P511: !_BLD [12] (FP)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P512: !_LD [18] (Int) (Loop exit) (LE)
wr %g0, 0x88, %asi
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduwa [%i3 + 12] %asi, %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_0_277:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_277
nop
P513: !_LD [28] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_278:
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P514: !_LD [15] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_0_278:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_278
nop
P515: !_LD [25] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_279:
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
ld [%i2 + 4], %f0
! 1 addresses covered
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
loop_exit_0_279:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_279
nop
P516: !_BLD [15] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_280:
wr %g0, 0xf0, %asi
sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_0_280:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_280
nop
P517: !_BLD [10] (FP) (Loop entry) (Branch target of P554)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_281:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
ba P518
nop
TARGET554:
ba RET554
nop
P518: !_DWLD [0] (Int) (Loop exit)
ldx [%i0 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_0_281:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_281
nop
P519: !_DWLD [13] (Int) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_282:
sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
ldx [%i3 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_0_282:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_282
nop
P520: !_BLD [11] (FP) (Loop entry) (Loop exit) (CBR)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_283:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET520
nop
RET520:
! lfsr step begin
srlx %l0, 1, %l7
xnor %l7, %l0, %l7
sllx %l7, 63, %l7
or %l7, %l0, %l0
srlx %l0, 1, %l0
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_0_283:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_283
nop
P521: !_LD [22] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_284:
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P522: !_LD [14] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_0_284:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_284
nop
P523: !_BLD [19] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_285:
wr %g0, 0xf0, %asi
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_0_285:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_285
nop
P524: !_DWLD [13] (Int) (Loop entry) (Branch target of P113)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_286:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
ba P525
nop
TARGET113:
ba RET113
nop
P525: !_BLD [25] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_0_286:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_286
nop
P526: !_LD [31] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_287:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P527: !_DWLD [10] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 8], %o5
! move %o5(lower) -> %o0(lower)
srl %o5, 0, %l7
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_0_287:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_287
nop
P528: !_DWST [17] (maybe <- 0x2a) (Int) (Loop entry) (Loop exit) (CBR)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_288:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
sub %i0, %i2, %i2
sllx %l4, 32, %l7
add %l4, 1, %l4
or %l7, %l4, %l7
stx %l7, [%i2 + 0]
add %l4, 1, %l4
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET528
nop
RET528:
! lfsr step begin
srlx %l0, 1, %l6
xnor %l6, %l0, %l6
sllx %l6, 63, %l6
or %l6, %l0, %l0
srlx %l0, 1, %l0
loop_exit_0_288:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_288
nop
P529: !_LD [31] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_289:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P530: !_LD [2] (Int) (Loop exit)
lduw [%i0 + 12], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_0_289:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_289
nop
P531: !_ST [24] (maybe <- 0x2c) (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_290:
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
stw %l4, [%i2 + 0 ]
add %l4, 1, %l4
P532: !_BLD [7] (FP) (Loop exit)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 7
sethi %hi(0xc0000), %l3
sub %i1, %l3, %i1
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
sethi %hi(0xc0000), %l6
add %i1, %l6, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_0_290:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_290
nop
P533: !_LD [22] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_291:
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P534: !_LD [31] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 32], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_0_291:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_291
nop
P535: !_CAS [22] (maybe <- 0x2d) (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_292:
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
sub %i0, %i3, %i3
add %i3, 12, %l6
lduw [%l6], %o0
mov %o0, %l3
! move %l3(lower) -> %o0(upper)
sllx %l3, 32, %o0
mov %l4, %o5
cas [%l6], %l3, %o5
! move %o5(lower) -> %o0(lower)
srl %o5, 0, %l3
or %l3, %o0, %o0
add %l4, 1, %l4
P536: !_LD [3] (Int)
lduw [%i0 + 32], %o1
! move %o1(lower) -> %o1(upper)
sllx %o1, 32, %o1
P537: !_LD [15] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 32], %l3
! move %l3(lower) -> %o1(lower)
or %l3, %o1, %o1
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_0_292:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_292
nop
P538: !_DWLD [15] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_293:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 32], %o0
! move %o0(upper) -> %o0(upper)
P539: !_LD [29] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %l7
! move %l7(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_0_293:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_293
nop
P540: !_ST [29] (maybe <- 0x2e) (Int) (Loop entry) (Loop exit) (CBR)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_294:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i3
sub %i0, %i3, %i3
stw %l4, [%i3 + 4 ]
add %l4, 1, %l4
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET540
nop
RET540:
! lfsr step begin
srlx %l0, 1, %l3
xnor %l3, %l0, %l3
sllx %l3, 63, %l3
or %l3, %l0, %l0
srlx %l0, 1, %l0
loop_exit_0_294:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_294
nop
P541: !_LD [10] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_295:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P542: !_LD [11] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_0_295:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_295
nop
P543: !_PREFETCH [5] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_296:
prefetch [%i1 + 4], 1
P544: !_FLUSHI [26] (Int) (Loop exit)
flush %g0
loop_exit_0_296:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_296
nop
P545: !_SWAP [17] (maybe <- 0x2f) (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_297:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
sub %i0, %i2, %i2
mov %l4, %o0
swap [%i2 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
add %l4, 1, %l4
P546: !_BLD [9] (FP)
wr %g0, 0xf0, %asi
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P547: !_LD [28] (Int) (Loop exit) (LE)
wr %g0, 0x88, %asi
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduwa [%i2 + 0] %asi, %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_0_297:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_297
nop
P548: !_DWLD [7] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_298:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 7
sethi %hi(0xc0000), %l6
sub %i1, %l6, %i1
ldx [%i1 + 32], %o0
! move %o0(upper) -> %o0(upper)
P549: !_DWLD [11] (Int) (Loop exit)
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
ldx [%i3 + 32], %l6
! move %l6(upper) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
srlx %l6, 32, %l3
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
sethi %hi(0xc0000), %l7
add %i1, %l7, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_0_298:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_298
nop
P550: !_BLD [12] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_299:
wr %g0, 0xf0, %asi
sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P551: !_DWLD [8] (FP) (Loop exit)
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
ldd [%i3 + 0], %f4
! 2 addresses covered
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovd %f4, %f30
!--
loop_exit_0_299:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_299
nop
P552: !_DWLD [31] (Int) (Loop entry) (CBR)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_300:
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
ldx [%i2 + 32], %o0
! move %o0(upper) -> %o0(upper)
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET552
nop
RET552:
! lfsr step begin
srlx %l0, 1, %l3
xnor %l3, %l0, %l3
sllx %l3, 63, %l3
or %l3, %l0, %l0
srlx %l0, 1, %l0
P553: !_LD [4] (Int) (Loop exit)
lduw [%i1 + 0], %l7
! move %l7(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_0_300:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_300
nop
P554: !_ST [25] (maybe <- 0x30) (Int) (Loop entry) (Loop exit) (CBR)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_301:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i3
sub %i0, %i3, %i3
stw %l4, [%i3 + 4 ]
add %l4, 1, %l4
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET554
nop
RET554:
! lfsr step begin
srlx %l0, 1, %l3
xnor %l3, %l0, %l3
sllx %l3, 63, %l3
or %l3, %l0, %l0
srlx %l0, 1, %l0
loop_exit_0_301:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_301
nop
P555: !_DWLD [15] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_302:
sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
ldx [%i2 + 32], %o0
! move %o0(upper) -> %o0(upper)
P556: !_LD [24] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %l7
! move %l7(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_0_302:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_302
nop
P557: !_CAS [20] (maybe <- 0x31) (Int) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_303:
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2], %o0
mov %o0, %l3
! move %l3(lower) -> %o0(upper)
sllx %l3, 32, %o0
mov %l4, %o5
cas [%i2], %l3, %o5
! move %o5(lower) -> %o0(lower)
srl %o5, 0, %l3
or %l3, %o0, %o0
add %l4, 1, %l4
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_0_303:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_303
nop
P558: !_BLD [11] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_304:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P559: !_DWLD [13] (Int) (Loop exit) (Branch target of P140)
sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
ldx [%i2 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_0_304:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_304
nop
ba P560
nop
TARGET140:
ba RET140
nop
P560: !_BLD [6] (FP) (Loop entry) (Branch target of P278)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_305:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 6
sethi %hi(0xc0000), %l6
sub %i1, %l6, %i1
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
ba P561
nop
TARGET278:
ba RET278
nop
P561: !_BLD [2] (FP) (Loop exit)
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i0 + 0] %asi, %f32
membar #Sync
! 4 addresses covered
fmovd %f32, %f4
fmovd %f34, %f18
fmovs %f19, %f6
fmovd %f40, %f18
fmovs %f18, %f7
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovd %f4, %f30
fmovd %f6, %f30
!--
sethi %hi(0xc0000), %l7
add %i1, %l7, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_0_305:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_305
nop
P562: !_LD [4] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_306:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 4
sethi %hi(0xc0000), %o5
sub %i1, %o5, %i1
lduw [%i1 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P563: !_LD [8] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
sethi %hi(0xc0000), %l3
add %i1, %l3, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_0_306:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_306
nop
P564: !_BLD [3] (FP) (Loop entry) (Loop exit) (CBR)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_307:
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i0 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET564
nop
RET564:
! lfsr step begin
srlx %l0, 1, %l7
xnor %l7, %l0, %l7
sllx %l7, 63, %l7
or %l7, %l0, %l0
srlx %l0, 1, %l0
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_0_307:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_307
nop
P565: !_LD [0] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_308:
lduw [%i0 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P566: !_LD [23] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 32], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_0_308:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_308
nop
P567: !_BLD [11] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_309:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_0_309:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_309
nop
P568: !_LD [23] (Int) (Loop entry) (LE) (CBR)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_310:
wr %g0, 0x88, %asi
sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduwa [%i2 + 32] %asi, %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET568
nop
RET568:
! lfsr step begin
srlx %l0, 1, %l7
xnor %l7, %l0, %l7
sllx %l7, 63, %l7
or %l7, %l0, %l0
srlx %l0, 1, %l0
P569: !_PREFETCH [6] (Int)
prefetch [%i1 + 12], 1
P570: !_LD [21] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 4], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_0_310:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_310
nop
P571: !_BLD [4] (FP) (Loop entry) (CBR)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_311:
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET571
nop
RET571:
! lfsr step begin
srlx %l0, 1, %o5
xnor %o5, %l0, %o5
sllx %o5, 63, %o5
or %o5, %l0, %l0
srlx %l0, 1, %l0
P572: !_DWLD [4] (Int) (Loop exit)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 4
sethi %hi(0xc0000), %l3
sub %i1, %l3, %i1
ldx [%i1 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
sethi %hi(0xc0000), %o5
add %i1, %o5, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_0_311:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_311
nop
P573: !_LD [8] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_312:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P574: !_LD [24] (Int) (Loop exit)
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 0], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_0_312:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_312
nop
P575: !_CASX [11] (maybe <- 0x32) (Int) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_313:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i2
sub %i0, %i2, %i2
add %i2, 32, %o5
ldx [%o5], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
mov %o0, %l7
sllx %l4, 32, %o1
casx [%o5], %l7, %o1
! move %o1(upper) -> %o1(upper)
! move %o1(lower) -> %o1(lower)
add %l4, 1, %l4
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_0_313:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_313
nop
P576: !_BLD [19] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_314:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_0_314:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_314
nop
P577: !_LD [5] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_315:
lduw [%i1 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P578: !_LD [3] (Int) (Loop exit)
lduw [%i0 + 32], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_0_315:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_315
nop
P579: !_NOP (Int) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_316:
nop
loop_exit_0_316:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_316
nop
P580: !_DWLD [26] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_317:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P581: !_DWLD [24] (Int)
ldx [%i2 + 0], %l3
! move %l3(upper) -> %o0(lower)
srlx %l3, 32, %o5
or %o5, %o0, %o0
! move %l3(lower) -> %o1(upper)
sllx %l3, 32, %o1
P582: !_LD [9] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 4], %o5
! move %o5(lower) -> %o1(lower)
or %o5, %o1, %o1
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_0_317:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_317
nop
P583: !_DWLD [7] (Int) (Loop entry) (LE)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_318:
wr %g0, 0x88, %asi
ldxa [%i1 + 32] %asi, %l7
! move %l7(lower) -> %o0(upper)
sllx %l7, 32, %o0
P584: !_BLD [4] (FP)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 4
sethi %hi(0xc0000), %o5
sub %i1, %o5, %i1
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P585: !_LD [19] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 32], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
sethi %hi(0xc0000), %l7
add %i1, %l7, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_0_318:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_318
nop
P586: !_LD [8] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_319:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P587: !_LD [16] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 0], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_0_319:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_319
nop
P588: !_LD [2] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_320:
lduw [%i0 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P589: !_DWLD [9] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 0], %l6
! move %l6(upper) -> %o0(lower)
srlx %l6, 32, %l3
or %l3, %o0, %o0
! move %l6(lower) -> %o1(upper)
sllx %l6, 32, %o1
P590: !_LD [19] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 32], %l3
! move %l3(lower) -> %o1(lower)
or %l3, %o1, %o1
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_0_320:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_320
nop
P591: !_BLD [20] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_321:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P592: !_LD [11] (Int)
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P593: !_LD [4] (Int) (Loop exit)
lduw [%i1 + 0], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_0_321:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_321
nop
P594: !_BLD [26] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_322:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_0_322:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_322
nop
P595: !_BLD [15] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_323:
wr %g0, 0xf0, %asi
sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_0_323:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_323
nop
P596: !_REPLACEMENT [2] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_324:
sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS3_O), %i3
sub %i0, %i3, %i3
sethi %hi(0x10000), %l3
ld [%i3+12], %l7
st %l7, [%i3+12]
add %i3, %l3, %l6
ld [%l6+12], %l7
st %l7, [%l6+12]
add %l6, %l3, %l6
ld [%l6+12], %l7
st %l7, [%l6+12]
add %l6, %l3, %l6
ld [%l6+12], %l7
st %l7, [%l6+12]
P597: !_DWLD [4] (Int) (Loop exit)
ldx [%i1 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_0_324:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_324
nop
P598: !_LD [28] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_325:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P599: !_LD [9] (Int) (Loop exit)
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 4], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_0_325:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_325
nop
P600: !_BLD [7] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_326:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 7
sethi %hi(0xc0000), %l3
sub %i1, %l3, %i1
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
sethi %hi(0xc0000), %l6
add %i1, %l6, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_0_326:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_326
nop
P601: !_NOP (Int) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_327:
nop
loop_exit_0_327:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_327
nop
P602: !_DWLD [15] (Int) (Loop entry) (Branch target of P77)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_328:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 32], %o0
! move %o0(upper) -> %o0(upper)
ba P603
nop
TARGET77:
ba RET77
nop
P603: !_LD [28] (Int) (Loop exit) (LE)
wr %g0, 0x88, %asi
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduwa [%i3 + 0] %asi, %o5
! move %o5(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_0_328:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_328
nop
P604: !_BLD [14] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_329:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P605: !_LD [0] (Int)
lduw [%i0 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P606: !_LD [21] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 4], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_0_329:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_329
nop
P607: !_BLD [7] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_330:
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P608: !_DWLD [27] (FP) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i2
sub %i0, %i2, %i2
ldd [%i2 + 32], %f4
! 1 addresses covered
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovs %f4, %f30
!--
loop_exit_0_330:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_330
nop
P609: !_BLD [19] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_331:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P610: !_LD [12] (FP) (Loop exit) (Branch target of P55)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i2
sub %i0, %i2, %i2
ld [%i2 + 0], %f4
! 1 addresses covered
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovs %f4, %f30
!--
loop_exit_0_331:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_331
nop
ba P611
nop
TARGET55:
ba RET55
nop
P611: !_DWLD [5] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_332:
ldx [%i1 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
P612: !_LD [10] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %o1
! move %o1(lower) -> %o1(upper)
sllx %o1, 32, %o1
P613: !_LD [6] (Int) (Loop exit) (LE)
wr %g0, 0x88, %asi
lduwa [%i1 + 12] %asi, %l7
! move %l7(lower) -> %o1(lower)
or %l7, %o1, %o1
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_0_332:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_332
nop
P614: !_BSTC [8] (maybe <- 0x3f800022) (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_333:
wr %g0, 0xe0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
sub %i0, %i2, %i2
! preparing store val #0, next val will be in f32
fmovs %f16, %f20
fadds %f16, %f17, %f16
! preparing store val #1, next val will be in f33
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #2, next val will be in f35
fmovd %f20, %f32
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #3, next val will be in f40
fmovd %f20, %f34
fmovs %f16, %f20
fadds %f16, %f17, %f16
fmovd %f20, %f40
membar #Sync
stda %f32, [%i2 + 0 ] %asi
membar #Sync
P615: !_BLD [29] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_0_333:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_333
nop
P616: !_CASX [18] (maybe <- 0x33) (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_334:
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
add %i2, 8, %o5
ldx [%o5], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
mov %o0, %l7
mov %l4, %o1
casx [%o5], %l7, %o1
! move %o1(upper) -> %o1(upper)
! move %o1(lower) -> %o1(lower)
add %l4, 1, %l4
P617: !_DWLD [0] (Int) (Loop exit) (LE)
wr %g0, 0x88, %asi
ldxa [%i0 + 0] %asi, %o5
! move %o5(lower) -> %o2(upper)
sllx %o5, 32, %o2
! move %o5(upper) -> %o2(lower)
srlx %o5, 32, %l7
or %l7, %o2, %o2
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
mov %o2, %l5
loop_exit_0_334:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_334
nop
P618: !_DWLD [15] (Int) (Loop entry) (LE)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_335:
wr %g0, 0x88, %asi
sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
ldxa [%i3 + 32] %asi, %o5
! move %o5(lower) -> %o0(upper)
sllx %o5, 32, %o0
P619: !_LD [19] (Int) (Loop exit)
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 32], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_0_335:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_335
nop
P620: !_DWLD [12] (Int) (Loop entry) (LE)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_336:
wr %g0, 0x88, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i3
sub %i0, %i3, %i3
ldxa [%i3 + 0] %asi, %l6
! move %l6(lower) -> %o0(upper)
sllx %l6, 32, %o0
! move %l6(upper) -> %o0(lower)
srlx %l6, 32, %l3
or %l3, %o0, %o0
P621: !_LD [13] (Int)
lduw [%i3 + 4], %o1
! move %o1(lower) -> %o1(upper)
sllx %o1, 32, %o1
P622: !_LD [28] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 0], %l7
! move %l7(lower) -> %o1(lower)
or %l7, %o1, %o1
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_0_336:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_336
nop
P623: !_REPLACEMENT [11] (Int) (Loop entry) (Loop exit) (Branch target of P146)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_337:
sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS1_O), %i3
sub %i0, %i3, %i3
sethi %hi(0x10000), %l3
ld [%i3+32], %l7
st %l7, [%i3+32]
add %i3, %l3, %l6
ld [%l6+32], %l7
st %l7, [%l6+32]
add %l6, %l3, %l6
ld [%l6+32], %l7
st %l7, [%l6+32]
add %l6, %l3, %l6
ld [%l6+32], %l7
st %l7, [%l6+32]
loop_exit_0_337:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_337
nop
ba P624
nop
TARGET146:
ba RET146
nop
P624: !_LD [0] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_338:
lduw [%i0 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P625: !_BLD [9] (FP)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P626: !_LD [15] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_0_338:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_338
nop
P627: !_DWLD [13] (Int) (Loop entry) (LE)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_339:
wr %g0, 0x88, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i2
sub %i0, %i2, %i2
ldxa [%i2 + 0] %asi, %l3
! move %l3(lower) -> %o0(upper)
sllx %l3, 32, %o0
! move %l3(upper) -> %o0(lower)
srlx %l3, 32, %o5
or %o5, %o0, %o0
P628: !_LD [27] (Int)
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 32], %o1
! move %o1(lower) -> %o1(upper)
sllx %o1, 32, %o1
P629: !_LD [30] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %l6
! move %l6(lower) -> %o1(lower)
or %l6, %o1, %o1
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_0_339:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_339
nop
P630: !_LD [17] (FP) (Loop entry) (Loop exit) (Branch target of P256)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_340:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
sub %i0, %i3, %i3
ld [%i3 + 4], %f0
! 1 addresses covered
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
loop_exit_0_340:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_340
nop
ba P631
nop
TARGET256:
ba RET256
nop
P631: !_DWLD [4] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_341:
ldx [%i1 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
P632: !_BLD [8] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_0_341:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_341
nop
P633: !_SWAP [7] (maybe <- 0x34) (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_342:
mov %l4, %o0
swap [%i1 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
add %l4, 1, %l4
P634: !_LD [31] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_0_342:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_342
nop
P635: !_LD [13] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_343:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P636: !_BLD [1] (FP)
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i0 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P637: !_LD [27] (Int) (Loop exit) (CBR)
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 32], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET637
nop
RET637:
! lfsr step begin
srlx %l0, 1, %l6
xnor %l6, %l0, %l6
sllx %l6, 63, %l6
or %l6, %l0, %l0
srlx %l0, 1, %l0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_0_343:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_343
nop
P638: !_BSTC [24] (maybe <- 0x3f800026) (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_344:
wr %g0, 0xe0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
sub %i0, %i2, %i2
! preparing store val #0, next val will be in f32
fmovs %f16, %f20
fadds %f16, %f17, %f16
! preparing store val #1, next val will be in f33
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #2, next val will be in f35
fmovd %f20, %f32
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #3, next val will be in f40
fmovd %f20, %f34
fmovs %f16, %f20
fadds %f16, %f17, %f16
fmovd %f20, %f40
membar #Sync
stda %f32, [%i2 + 0 ] %asi
membar #Sync
P639: !_FLUSHI [3] (Int) (Loop exit)
flush %g0
loop_exit_0_344:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_344
nop
P640: !_BLD [27] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_345:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P641: !_BLD [14] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f32
membar #Sync
! 4 addresses covered
fmovd %f32, %f4
fmovd %f34, %f18
fmovs %f19, %f6
fmovd %f40, %f18
fmovs %f18, %f7
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovd %f4, %f30
fmovd %f6, %f30
!--
loop_exit_0_345:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_345
nop
P642: !_DWLD [27] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_346:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 32], %o0
! move %o0(upper) -> %o0(upper)
P643: !_LD [10] (FP)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i2
sub %i0, %i2, %i2
ld [%i2 + 12], %f0
! 1 addresses covered
P644: !_LD [25] (Int) (Loop exit)
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 4], %o5
! move %o5(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
loop_exit_0_346:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_346
nop
P645: !_DWLD [15] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_347:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 32], %o0
! move %o0(upper) -> %o0(upper)
P646: !_DWLD [10] (Int) (Loop exit)
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
ldx [%i3 + 8], %l6
! move %l6(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
srl %l6, 0, %l3
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_0_347:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_347
nop
P647: !_DWLD [14] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_348:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i2
sub %i0, %i2, %i2
ldd [%i2 + 8], %f0
! 1 addresses covered
fmovs %f1, %f0
P648: !_BLD [22] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f32
membar #Sync
! 4 addresses covered
fmovd %f32, %f18
fmovs %f18, %f1
fmovs %f19, %f2
fmovd %f34, %f18
fmovs %f19, %f3
fmovd %f40, %f4
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovs %f4, %f30
!--
loop_exit_0_348:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_348
nop
P649: !_DWST [28] (maybe <- 0x35) (Int) (Loop entry) (LE)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_349:
wr %g0, 0x88, %asi
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i2
sub %i0, %i2, %i2
sllx %l4, 32, %l6
add %l4, 1, %l4
or %l6, %l4, %l7
! Change double-word-level endianess (big endian <-> little endian)
sethi %hi(0xff00ff00), %o5
or %o5, %lo(0xff00ff00), %o5
sllx %o5, 32, %l6
or %o5, %l6, %o5
and %l7, %o5, %l6
srlx %l6, 8, %l6
sllx %l7, 8, %l7
and %l7, %o5, %l7
or %l7, %l6, %l7
sethi %hi(0xffff0000), %o5
srlx %l7, 16, %l6
andn %l6, %o5, %l6
andn %l7, %o5, %l7
sllx %l7, 16, %l7
or %l7, %l6, %l7
srlx %l7, 32, %l6
sllx %l7, 32, %l7
or %l7, %l6, %l6
stxa %l6, [%i2 + 0 ] %asi
add %l4, 1, %l4
P650: !_BLD [29] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_0_349:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_349
nop
P651: !_LD [3] (Int) (Loop entry) (LE)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_0_350:
wr %g0, 0x88, %asi
lduwa [%i0 + 32] %asi, %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P652: !_LD [14] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_0_350:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_350
nop
P653: !_BLD [25] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_351:
wr %g0, 0xf0, %asi
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P654: !_BLD [13] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f32
membar #Sync
! 4 addresses covered
fmovd %f32, %f4
fmovd %f34, %f18
fmovs %f19, %f6
fmovd %f40, %f18
fmovs %f18, %f7
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovd %f4, %f30
fmovd %f6, %f30
!--
loop_exit_0_351:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_351
nop
P655: !_DWLD [5] (Int) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_352:
ldx [%i1 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_0_352:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_352
nop
P656: !_LD [25] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_0_353:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P657: !_BLD [22] (FP)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P658: !_LD [0] (Int) (Loop exit)
lduw [%i0 + 0], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_0_353:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_0_353
nop
P659: !_MEMBAR (Int)
membar #StoreLoad
END_NODES0: ! Test instruction sequence for CPU 0 ends
sethi %hi(0xdead0e0f), %l3
or %l3, %lo(0xdead0e0f), %l3
! move %l3(lower) -> %o0(upper)
sllx %l3, 32, %o0
stw %l3, [%i5]
ld [%i5], %f0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
restore
retl
nop
!-----------------
! register usage:
! %i0 %i1 : base registers for first 2 regions
! %i2 %i3 : cache registers for 8 regions
! %i4 fixed pointer to per-cpu results area
! %l1 moving pointer to per-cpu FP results area
! %o7 moving pointer to per-cpu integer results area
! %i5 pointer to per-cpu private area
! %l0 holds lfsr, used as source of random bits
! %l2 loop count register
! %f16 running counter for unique fp store values
! %f17 holds increment value for fp counter
! %l4 running counter for unique integer store values (increment value is always 1)
! %l5 move-to register for load values (simulation only)
! %f30 move-to register for FP values (simulation only)
! %l3 %l6 %l7 %o5 : 4 temporary registers
! %o0 %o1 %o2 %o3 %o4 : 5 integer results buffer registers
! %f0-f15 FP results buffer registers
! %f32-f47 FP block load/store registers
func1:
! 1000 (dynamic) instruction sequence begins
save %sp, -192, %sp
! Force %i0-%i3 to be 64-byte aligned
add %i0, 63, %i0
andn %i0, 63, %i0
add %i1, 63, %i1
andn %i1, 63, %i1
add %i2, 63, %i2
andn %i2, 63, %i2
add %i3, 63, %i3
andn %i3, 63, %i3
add %i4, 63, %i4
andn %i4, 63, %i4
add %i5, 63, %i5
andn %i5, 63, %i5
! Initialize pointer to FP load results area
mov %i4, %l1
! Initialize pointer to integer load results area
sethi %hi(0x80000), %o7
or %o7, %lo(0x80000), %o7
add %o7, %l1, %o7
! Initialize %f0-%f62 to 0xdeadbee0deadbee1
sethi %hi(0xdeadbee0), %o5
or %o5, %lo(0xdeadbee0), %o5
stw %o5, [%i5]
sethi %hi(0xdeadbee1), %o5
or %o5, %lo(0xdeadbee1), %o5
stw %o5, [%i5+4]
ldd [%i5], %f0
fmovd %f0, %f2
fmovd %f0, %f4
fmovd %f0, %f6
fmovd %f0, %f8
fmovd %f0, %f10
fmovd %f0, %f12
fmovd %f0, %f14
fmovd %f0, %f16
fmovd %f0, %f18
fmovd %f0, %f20
fmovd %f0, %f22
fmovd %f0, %f24
fmovd %f0, %f26
fmovd %f0, %f28
fmovd %f0, %f30
fmovd %f0, %f32
fmovd %f0, %f34
fmovd %f0, %f36
fmovd %f0, %f38
fmovd %f0, %f40
fmovd %f0, %f42
fmovd %f0, %f44
fmovd %f0, %f46
fmovd %f0, %f48
fmovd %f0, %f50
fmovd %f0, %f52
fmovd %f0, %f54
fmovd %f0, %f56
fmovd %f0, %f58
fmovd %f0, %f60
fmovd %f0, %f62
! Signature for extract_loads script to start extracting load values for this stream
sethi %hi(0x01deade1), %o5
or %o5, %lo(0x01deade1), %o5
stw %o5, [%i5]
ld [%i5], %f16
! Initialize running integer counter in register %l4
sethi %hi(0x800001), %l4
or %l4, %lo(0x800001), %l4
! Initialize running FP counter in register %f16
sethi %hi(0x40000001), %o5
or %o5, %lo(0x40000001), %o5
stw %o5, [%i5]
ld [%i5], %f16
! Initialize FP counter increment value in register %f17 (constant)
sethi %hi(0x34800000), %o5
or %o5, %lo(0x34800000), %o5
stw %o5, [%i5]
ld [%i5], %f17
! Initialize LFSR to 0x228b^4
sethi %hi(0x228b), %l0
or %l0, %lo(0x228b), %l0
mulx %l0, %l0, %l0
mulx %l0, %l0, %l0
BEGIN_NODES1: ! Test instruction sequence for CPU 1 begins
P660: !_BLD [2] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_0:
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i0 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_1_0:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_0
nop
P661: !_LD [24] (Int) (Loop entry) (Branch target of P989)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_1:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
ba P662
nop
TARGET989:
ba RET989
nop
P662: !_LD [20] (Int) (Loop exit) (CBR)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 0], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET662
nop
RET662:
! lfsr step begin
srlx %l0, 1, %o5
xnor %o5, %l0, %o5
sllx %o5, 63, %o5
or %o5, %l0, %l0
srlx %l0, 1, %l0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_1_1:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_1
nop
P663: !_BLD [16] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_2:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P664: !_LD [18] (Int)
lduw [%i3 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P665: !_LD [13] (Int) (Loop exit) (Branch target of P983)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_1_2:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_2
nop
ba P666
nop
TARGET983:
ba RET983
nop
P666: !_REPLACEMENT [30] (Int) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_3:
sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS2_O), %i3
sub %i0, %i3, %i3
sethi %hi(0x10000), %l3
ld [%i3+12], %l7
st %l7, [%i3+12]
add %i3, %l3, %l6
ld [%l6+12], %l7
st %l7, [%l6+12]
add %l6, %l3, %l6
ld [%l6+12], %l7
st %l7, [%l6+12]
add %l6, %l3, %l6
ld [%l6+12], %l7
st %l7, [%l6+12]
loop_exit_1_3:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_3
nop
P667: !_DWLD [3] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_4:
ldx [%i0 + 32], %o0
! move %o0(upper) -> %o0(upper)
P668: !_LD [12] (Int) (Loop exit) (Branch target of P831)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 0], %l3
! move %l3(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_1_4:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_4
nop
ba P669
nop
TARGET831:
ba RET831
nop
P669: !_SWAP [17] (maybe <- 0x800001) (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_5:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
sub %i0, %i3, %i3
mov %l4, %o0
swap [%i3 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
add %l4, 1, %l4
P670: !_LD [9] (Int) (Loop exit)
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 4], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_1_5:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_5
nop
P671: !_DWLD [11] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_6:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 32], %o0
! move %o0(upper) -> %o0(upper)
P672: !_LD [2] (Int) (Loop exit)
lduw [%i0 + 12], %l6
! move %l6(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_1_6:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_6
nop
P673: !_CASX [28] (maybe <- 0x800002) (Int) (Loop entry) (Loop exit) (LE)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_7:
sllx %l4, 32, %l6
add %l4, 1, %l4
or %l4, %l6, %l6
! Change double-word-level endianess (big endian <-> little endian)
sethi %hi(0xff00ff00), %l3
or %l3, %lo(0xff00ff00), %l3
sllx %l3, 32, %l7
or %l3, %l7, %l3
and %l6, %l3, %l7
srlx %l7, 8, %l7
sllx %l6, 8, %l6
and %l6, %l3, %l6
or %l6, %l7, %l6
sethi %hi(0xffff0000), %l3
srlx %l6, 16, %l7
andn %l7, %l3, %l7
andn %l6, %l3, %l6
sllx %l6, 16, %l6
or %l6, %l7, %l6
srlx %l6, 32, %l7
sllx %l6, 32, %l6
or %l6, %l7, %l7
wr %g0, 0x88, %asi
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
sub %i0, %i2, %i2
ldxa [%i2] %asi, %o5
! move %o5(lower) -> %o0(upper)
sllx %o5, 32, %o0
! move %o5(upper) -> %o0(lower)
srlx %o5, 32, %l3
or %l3, %o0, %o0
mov %o5, %l3
mov %l7, %o5
casxa [%i2] %asi, %l3, %o5
! move %o5(lower) -> %o1(upper)
sllx %o5, 32, %o1
! move %o5(upper) -> %o1(lower)
srlx %o5, 32, %l3
or %l3, %o1, %o1
add %l4, 1, %l4
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_1_7:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_7
nop
P674: !_BLD [0] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_8:
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i0 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P675: !_FLUSHI [1] (Int) (Loop exit) (CBR)
flush %g0
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET675
nop
RET675:
! lfsr step begin
srlx %l0, 1, %l7
xnor %l7, %l0, %l7
sllx %l7, 63, %l7
or %l7, %l0, %l0
srlx %l0, 1, %l0
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_1_8:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_8
nop
P676: !_DWST [20] (maybe <- 0x800004) (Int) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_9:
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i3
sub %i0, %i3, %i3
sllx %l4, 32, %l3
add %l4, 1, %l4
or %l3, %l4, %l3
stx %l3, [%i3 + 0]
add %l4, 1, %l4
loop_exit_1_9:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_9
nop
P677: !_BLD [17] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_10:
wr %g0, 0xf0, %asi
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P678: !_DWLD [3] (Int)
ldx [%i0 + 32], %o0
! move %o0(upper) -> %o0(upper)
P679: !_LD [28] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %l6
! move %l6(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_1_10:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_10
nop
P680: !_LD [14] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_11:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P681: !_LD [23] (Int) (Loop exit)
sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 32], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_1_11:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_11
nop
P682: !_BST [21] (maybe <- 0x40000001) (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_12:
wr %g0, 0xf0, %asi
sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
! preparing store val #0, next val will be in f32
fmovs %f16, %f20
fadds %f16, %f17, %f16
! preparing store val #1, next val will be in f33
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #2, next val will be in f35
fmovd %f20, %f32
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #3, next val will be in f40
fmovd %f20, %f34
fmovs %f16, %f20
fadds %f16, %f17, %f16
fmovd %f20, %f40
membar #Sync
stda %f32, [%i2 + 0 ] %asi
membar #Sync
P683: !_DWLD [22] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P684: !_LD [12] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 0], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_1_12:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_12
nop
P685: !_LD [31] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_13:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P686: !_LD [30] (Int) (Loop exit)
lduw [%i3 + 12], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_1_13:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_13
nop
P687: !_LD [26] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_14:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i2
sub %i0, %i2, %i2
ld [%i2 + 12], %f0
! 1 addresses covered
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
loop_exit_1_14:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_14
nop
P688: !_BLD [14] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_15:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P689: !_LD [12] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P690: !_LD [2] (Int) (Loop exit)
lduw [%i0 + 12], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_1_15:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_15
nop
P691: !_BLD [19] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_16:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_1_16:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_16
nop
P692: !_LD [8] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_17:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P693: !_LD [2] (Int) (Loop exit)
lduw [%i0 + 12], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_1_17:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_17
nop
P694: !_BST [18] (maybe <- 0x40000005) (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_18:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
sub %i0, %i3, %i3
! preparing store val #0, next val will be in f32
fmovs %f16, %f20
fadds %f16, %f17, %f16
! preparing store val #1, next val will be in f33
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #2, next val will be in f35
fmovd %f20, %f32
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #3, next val will be in f40
fmovd %f20, %f34
fmovs %f16, %f20
fadds %f16, %f17, %f16
fmovd %f20, %f40
membar #Sync
stda %f32, [%i3 + 0 ] %asi
membar #Sync
loop_exit_1_18:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_18
nop
P695: !_DWST [16] (maybe <- 0x800006) (Int) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_19:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i2
sub %i0, %i2, %i2
sllx %l4, 32, %l6
add %l4, 1, %l4
or %l6, %l4, %l6
stx %l6, [%i2 + 0]
add %l4, 1, %l4
loop_exit_1_19:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_19
nop
P696: !_LD [2] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_20:
lduw [%i0 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P697: !_PREFETCH [9] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
sub %i0, %i3, %i3
prefetch [%i3 + 4], 1
P698: !_LD [0] (Int) (Loop exit)
lduw [%i0 + 0], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_1_20:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_20
nop
P699: !_BLD [24] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_21:
wr %g0, 0xf0, %asi
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P700: !_DWLD [6] (Int)
ldx [%i1 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P701: !_LD [24] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_1_21:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_21
nop
P702: !_DWLD [26] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_22:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P703: !_LD [20] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_1_22:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_22
nop
P704: !_BLD [13] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_23:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P705: !_LD [29] (Int)
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P706: !_LD [5] (Int) (Loop exit)
lduw [%i1 + 4], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_1_23:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_23
nop
P707: !_LD [14] (Int) (Loop entry) (LE) (CBR)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_24:
wr %g0, 0x88, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduwa [%i2 + 12] %asi, %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET707
nop
RET707:
! lfsr step begin
srlx %l0, 1, %l6
xnor %l6, %l0, %l6
sllx %l6, 63, %l6
or %l6, %l0, %l0
srlx %l0, 1, %l0
P708: !_BLD [18] (FP)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P709: !_LD [5] (Int) (Loop exit)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 5
sethi %hi(0xc0000), %l7
sub %i1, %l7, %i1
lduw [%i1 + 4], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
sethi %hi(0xc0000), %l6
add %i1, %l6, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_1_24:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_24
nop
P710: !_DWLD [18] (Int) (Loop entry) (Branch target of P1301)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_25:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
ba P711
nop
TARGET1301:
ba RET1301
nop
P711: !_LD [23] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_1_25:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_25
nop
P712: !_BLD [26] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_26:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P713: !_LD [18] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P714: !_LD [2] (Int) (Loop exit)
lduw [%i0 + 12], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_1_26:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_26
nop
P715: !_BLD [26] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_27:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P716: !_LD [20] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P717: !_LD [10] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_1_27:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_27
nop
P718: !_SWAP [22] (maybe <- 0x800008) (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_28:
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i3
sub %i0, %i3, %i3
mov %l4, %o0
swap [%i3 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
add %l4, 1, %l4
P719: !_DWLD [4] (Int)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 4
sethi %hi(0xc0000), %l3
sub %i1, %l3, %i1
ldx [%i1 + 0], %l7
! move %l7(upper) -> %o0(lower)
srlx %l7, 32, %l6
or %l6, %o0, %o0
! move %l7(lower) -> %o1(upper)
sllx %l7, 32, %o1
P720: !_LD [1] (Int) (Loop exit)
lduw [%i0 + 4], %l3
! move %l3(lower) -> %o1(lower)
or %l3, %o1, %o1
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
sethi %hi(0xc0000), %l6
add %i1, %l6, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_1_28:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_28
nop
P721: !_DWLD [4] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_29:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 4
sethi %hi(0xc0000), %l7
sub %i1, %l7, %i1
ldd [%i1 + 0], %f0
! 2 addresses covered
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
!--
sethi %hi(0xc0000), %o5
add %i1, %o5, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_1_29:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_29
nop
P722: !_LD [21] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_30:
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P723: !_LD [2] (Int) (Loop exit) (LE)
wr %g0, 0x88, %asi
lduwa [%i0 + 12] %asi, %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_1_30:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_30
nop
P724: !_DWLD [11] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_31:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i3
sub %i0, %i3, %i3
ldd [%i3 + 32], %f0
! 1 addresses covered
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
loop_exit_1_31:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_31
nop
P725: !_DWLD [29] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_32:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
sub %i0, %i2, %i2
ldd [%i2 + 0], %f0
! 2 addresses covered
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
!--
loop_exit_1_32:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_32
nop
P726: !_LD [31] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_33:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P727: !_BLD [9] (FP)
wr %g0, 0xf0, %asi
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P728: !_LD [19] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_1_33:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_33
nop
P729: !_LD [8] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_34:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P730: !_DWLD [27] (Int) (Loop exit) (Branch target of P1116)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 32], %o5
! move %o5(upper) -> %o0(lower)
srlx %o5, 32, %l7
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_1_34:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_34
nop
ba P731
nop
TARGET1116:
ba RET1116
nop
P731: !_CASX [4] (maybe <- 0x800009) (Int) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_35:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 4
sethi %hi(0xc0000), %l6
sub %i1, %l6, %i1
ldx [%i1], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
mov %o0, %l7
sllx %l4, 32, %o1
add %l4, 1, %l4
or %l4, %o1, %o1
casx [%i1], %l7, %o1
! move %o1(upper) -> %o1(upper)
! move %o1(lower) -> %o1(lower)
add %l4, 1, %l4
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
sethi %hi(0xc0000), %l7
add %i1, %l7, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_1_35:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_35
nop
P732: !_ST [31] (maybe <- 0x80000b) (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_36:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
sub %i0, %i2, %i2
stw %l4, [%i2 + 32 ]
add %l4, 1, %l4
P733: !_CAS [25] (maybe <- 0x80000c) (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i3
sub %i0, %i3, %i3
add %i3, 4, %l3
lduw [%l3], %o0
mov %o0, %o5
! move %o5(lower) -> %o0(upper)
sllx %o5, 32, %o0
mov %l4, %l7
cas [%l3], %o5, %l7
! move %l7(lower) -> %o0(lower)
srl %l7, 0, %o5
or %o5, %o0, %o0
add %l4, 1, %l4
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_1_36:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_36
nop
P734: !_LD [3] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_37:
lduw [%i0 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P735: !_LD [27] (Int) (Loop exit)
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 32], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_1_37:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_37
nop
P736: !_SWAP [18] (maybe <- 0x80000d) (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_38:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
sub %i0, %i3, %i3
mov %l4, %o0
swap [%i3 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
add %l4, 1, %l4
P737: !_BLD [27] (FP)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P738: !_LD [14] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_1_38:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_38
nop
P739: !_DWLD [5] (Int) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_39:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 5
sethi %hi(0xc0000), %l6
sub %i1, %l6, %i1
ldx [%i1 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
sethi %hi(0xc0000), %l3
add %i1, %l3, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_1_39:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_39
nop
P740: !_BLD [5] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_40:
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_1_40:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_40
nop
P741: !_BLD [27] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_41:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_1_41:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_41
nop
P742: !_DWST [6] (maybe <- 0x80000e) (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_42:
mov %l4, %l3
stx %l3, [%i1 + 8]
add %l4, 1, %l4
P743: !_LD [15] (Int)
sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P744: !_LD [15] (Int) (Loop exit) (LE)
wr %g0, 0x88, %asi
lduwa [%i3 + 32] %asi, %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_1_42:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_42
nop
P745: !_LD [25] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_43:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P746: !_LD [2] (Int) (Loop exit)
lduw [%i0 + 12], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_1_43:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_43
nop
P747: !_DWLD [26] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_44:
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
ldx [%i3 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P748: !_DWLD [18] (FP)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i2
sub %i0, %i2, %i2
ldd [%i2 + 8], %f0
! 1 addresses covered
fmovs %f1, %f0
P749: !_LD [11] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
loop_exit_1_44:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_44
nop
P750: !_LD [31] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_45:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P751: !_LD [4] (Int) (Loop exit)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 4
sethi %hi(0xc0000), %l3
sub %i1, %l3, %i1
lduw [%i1 + 0], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
sethi %hi(0xc0000), %o5
add %i1, %o5, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_1_45:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_45
nop
P752: !_DWLD [22] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_46:
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i3
sub %i0, %i3, %i3
ldd [%i3 + 8], %f0
! 1 addresses covered
fmovs %f1, %f0
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
loop_exit_1_46:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_46
nop
P753: !_DWLD [15] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_47:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 32], %o0
! move %o0(upper) -> %o0(upper)
P754: !_LD [21] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 4], %l6
! move %l6(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_1_47:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_47
nop
P755: !_LD [29] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_48:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P756: !_LD [27] (Int) (Loop exit) (Branch target of P837)
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 32], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_1_48:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_48
nop
ba P757
nop
TARGET837:
ba RET837
nop
P757: !_LD [26] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_49:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P758: !_LD [2] (Int) (Loop exit)
lduw [%i0 + 12], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_1_49:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_49
nop
P759: !_BLD [8] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_50:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_1_50:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_50
nop
P760: !_MEMBAR (Int) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_51:
membar #StoreLoad
loop_exit_1_51:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_51
nop
P761: !_DWLD [27] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_52:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 32], %o0
! move %o0(upper) -> %o0(upper)
P762: !_LD [1] (Int) (Loop exit)
lduw [%i0 + 4], %l7
! move %l7(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_1_52:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_52
nop
P763: !_LD [23] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_53:
sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P764: !_LD [15] (Int) (Loop exit) (LE)
wr %g0, 0x88, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduwa [%i2 + 32] %asi, %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_1_53:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_53
nop
P765: !_LD [21] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_54:
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P766: !_DWLD [6] (Int) (Loop exit)
ldx [%i1 + 8], %l7
! move %l7(lower) -> %o0(lower)
srl %l7, 0, %l6
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_1_54:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_54
nop
P767: !_BLD [28] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_55:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_1_55:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_55
nop
P768: !_LD [24] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_56:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P769: !_LD [29] (Int) (Loop exit)
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 4], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_1_56:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_56
nop
P770: !_LD [23] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_57:
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i3
sub %i0, %i3, %i3
ld [%i3 + 32], %f0
! 1 addresses covered
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
loop_exit_1_57:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_57
nop
P771: !_DWLD [5] (Int) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_58:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 5
sethi %hi(0xc0000), %l6
sub %i1, %l6, %i1
ldx [%i1 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
sethi %hi(0xc0000), %l3
add %i1, %l3, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_1_58:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_58
nop
P772: !_BLD [8] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_59:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P773: !_BLD [27] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f32
membar #Sync
! 4 addresses covered
fmovd %f32, %f4
fmovd %f34, %f18
fmovs %f19, %f6
fmovd %f40, %f18
fmovs %f18, %f7
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovd %f4, %f30
fmovd %f6, %f30
!--
loop_exit_1_59:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_59
nop
P774: !_DWLD [22] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_60:
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P775: !_LD [7] (Int) (Loop exit)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 7
sethi %hi(0xc0000), %l6
sub %i1, %l6, %i1
lduw [%i1 + 32], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
sethi %hi(0xc0000), %l3
add %i1, %l3, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_1_60:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_60
nop
P776: !_BSTC [3] (maybe <- 0x40000009) (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_61:
wr %g0, 0xe0, %asi
! preparing store val #0, next val will be in f32
fmovs %f16, %f20
fadds %f16, %f17, %f16
! preparing store val #1, next val will be in f33
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #2, next val will be in f35
fmovd %f20, %f32
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #3, next val will be in f40
fmovd %f20, %f34
fmovs %f16, %f20
fadds %f16, %f17, %f16
fmovd %f20, %f40
membar #Sync
stda %f32, [%i0 + 0 ] %asi
membar #Sync
loop_exit_1_61:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_61
nop
P777: !_DWLD [30] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_62:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P778: !_LD [6] (Int) (Loop exit) (CBR)
lduw [%i1 + 12], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET778
nop
RET778:
! lfsr step begin
srlx %l0, 1, %l7
xnor %l7, %l0, %l7
sllx %l7, 63, %l7
or %l7, %l0, %l0
srlx %l0, 1, %l0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_1_62:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_62
nop
P779: !_DWLD [6] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_63:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 6
sethi %hi(0xc0000), %l3
sub %i1, %l3, %i1
ldx [%i1 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P780: !_LD [14] (Int) (Loop exit) (Branch target of P1283)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
sethi %hi(0xc0000), %l6
add %i1, %l6, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_1_63:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_63
nop
ba P781
nop
TARGET1283:
ba RET1283
nop
P781: !_BLD [24] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_64:
wr %g0, 0xf0, %asi
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_1_64:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_64
nop
P782: !_LD [26] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_65:
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P783: !_PREFETCH [19] (Int)
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
prefetch [%i3 + 32], 1
P784: !_LD [4] (Int) (Loop exit)
lduw [%i1 + 0], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_1_65:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_65
nop
P785: !_DWLD [26] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_66:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P786: !_CAS [12] (maybe <- 0x80000f) (Int)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3], %l3
mov %l3, %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
mov %l4, %o1
cas [%i3], %l6, %o1
! move %o1(lower) -> %o1(upper)
sllx %o1, 32, %o1
add %l4, 1, %l4
P787: !_LD [30] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %o5
! move %o5(lower) -> %o1(lower)
or %o5, %o1, %o1
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_1_66:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_66
nop
P788: !_DWLD [3] (FP) (Loop entry) (CBR) (Branch target of P707)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_67:
ldd [%i0 + 32], %f0
! 1 addresses covered
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET788
nop
RET788:
! lfsr step begin
srlx %l0, 1, %l6
xnor %l6, %l0, %l6
sllx %l6, 63, %l6
or %l6, %l0, %l0
srlx %l0, 1, %l0
ba P789
nop
TARGET707:
ba RET707
nop
P789: !_BLD [3] (FP) (Loop exit)
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i0 + 0] %asi, %f32
membar #Sync
! 4 addresses covered
fmovd %f32, %f18
fmovs %f18, %f1
fmovs %f19, %f2
fmovd %f34, %f18
fmovs %f19, %f3
fmovd %f40, %f4
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovs %f4, %f30
!--
loop_exit_1_67:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_67
nop
P790: !_LD [2] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_68:
lduw [%i0 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P791: !_LD [23] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_1_68:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_68
nop
P792: !_BLD [7] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_69:
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_1_69:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_69
nop
P793: !_NOP (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_70:
nop
P794: !_BST [3] (maybe <- 0x4000000d) (FP) (Loop exit)
wr %g0, 0xf0, %asi
! preparing store val #0, next val will be in f32
fmovs %f16, %f20
fadds %f16, %f17, %f16
! preparing store val #1, next val will be in f33
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #2, next val will be in f35
fmovd %f20, %f32
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #3, next val will be in f40
fmovd %f20, %f34
fmovs %f16, %f20
fadds %f16, %f17, %f16
fmovd %f20, %f40
membar #Sync
stda %f32, [%i0 + 0 ] %asi
membar #Sync
loop_exit_1_70:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_70
nop
P795: !_DWLD [2] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_71:
ldx [%i0 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P796: !_BLD [3] (FP)
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i0 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P797: !_LD [17] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_1_71:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_71
nop
P798: !_BLD [17] (FP) (Loop entry) (CBR)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_72:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET798
nop
RET798:
! lfsr step begin
srlx %l0, 1, %o5
xnor %o5, %l0, %o5
sllx %o5, 63, %o5
or %o5, %l0, %l0
srlx %l0, 1, %l0
P799: !_LD [16] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P800: !_LD [17] (Int) (Loop exit)
lduw [%i2 + 4], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_1_72:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_72
nop
P801: !_BLD [8] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_73:
wr %g0, 0xf0, %asi
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P802: !_BLD [19] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f32
membar #Sync
! 4 addresses covered
fmovd %f32, %f4
fmovd %f34, %f18
fmovs %f19, %f6
fmovd %f40, %f18
fmovs %f18, %f7
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovd %f4, %f30
fmovd %f6, %f30
!--
loop_exit_1_73:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_73
nop
P803: !_BLD [15] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_74:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_1_74:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_74
nop
P804: !_BLD [4] (FP) (Loop entry) (Loop exit) (Branch target of P1054)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_75:
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_1_75:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_75
nop
ba P805
nop
TARGET1054:
ba RET1054
nop
P805: !_DWLD [4] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_76:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 4
sethi %hi(0xc0000), %o5
sub %i1, %o5, %i1
ldx [%i1 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
P806: !_DWLD [17] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 0], %o1
! move %o1(upper) -> %o1(upper)
! move %o1(lower) -> %o1(lower)
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
sethi %hi(0xc0000), %l3
add %i1, %l3, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_1_76:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_76
nop
P807: !_BLD [14] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_77:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_1_77:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_77
nop
P808: !_FLUSHI [7] (Int) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_78:
flush %g0
loop_exit_1_78:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_78
nop
P809: !_DWLD [18] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_79:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P810: !_DWST [10] (maybe <- 0x800010) (Int) (CBR)
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
mov %l4, %o5
stx %o5, [%i3 + 8]
add %l4, 1, %l4
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET810
nop
RET810:
! lfsr step begin
srlx %l0, 1, %l7
xnor %l7, %l0, %l7
sllx %l7, 63, %l7
or %l7, %l0, %l0
srlx %l0, 1, %l0
P811: !_LD [9] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_1_79:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_79
nop
P812: !_BLD [6] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_80:
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P813: !_CASX [29] (maybe <- 0x800011) (Int) (Loop exit) (LE)
sllx %l4, 32, %l6
add %l4, 1, %l4
or %l4, %l6, %l6
! Change double-word-level endianess (big endian <-> little endian)
sethi %hi(0xff00ff00), %l3
or %l3, %lo(0xff00ff00), %l3
sllx %l3, 32, %l7
or %l3, %l7, %l3
and %l6, %l3, %l7
srlx %l7, 8, %l7
sllx %l6, 8, %l6
and %l6, %l3, %l6
or %l6, %l7, %l6
sethi %hi(0xffff0000), %l3
srlx %l6, 16, %l7
andn %l7, %l3, %l7
andn %l6, %l3, %l6
sllx %l6, 16, %l6
or %l6, %l7, %l6
srlx %l6, 32, %l7
sllx %l6, 32, %l6
or %l6, %l7, %l7
wr %g0, 0x88, %asi
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i3
sub %i0, %i3, %i3
ldxa [%i3] %asi, %o5
! move %o5(lower) -> %o0(upper)
sllx %o5, 32, %o0
! move %o5(upper) -> %o0(lower)
srlx %o5, 32, %l3
or %l3, %o0, %o0
mov %o5, %l3
mov %l7, %o5
casxa [%i3] %asi, %l3, %o5
! move %o5(lower) -> %o1(upper)
sllx %o5, 32, %o1
! move %o5(upper) -> %o1(lower)
srlx %o5, 32, %l3
or %l3, %o1, %o1
add %l4, 1, %l4
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_1_80:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_80
nop
P814: !_BLD [17] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_81:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P815: !_BLD [16] (FP) (Loop exit) (Branch target of P1057)
wr %g0, 0xf0, %asi
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f32
membar #Sync
! 4 addresses covered
fmovd %f32, %f4
fmovd %f34, %f18
fmovs %f19, %f6
fmovd %f40, %f18
fmovs %f18, %f7
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovd %f4, %f30
fmovd %f6, %f30
!--
loop_exit_1_81:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_81
nop
ba P816
nop
TARGET1057:
ba RET1057
nop
P816: !_BLD [2] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_82:
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i0 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_1_82:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_82
nop
P817: !_BSTC [12] (maybe <- 0x40000011) (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_83:
wr %g0, 0xe0, %asi
sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
! preparing store val #0, next val will be in f32
fmovs %f16, %f20
fadds %f16, %f17, %f16
! preparing store val #1, next val will be in f33
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #2, next val will be in f35
fmovd %f20, %f32
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #3, next val will be in f40
fmovd %f20, %f34
fmovs %f16, %f20
fadds %f16, %f17, %f16
fmovd %f20, %f40
membar #Sync
stda %f32, [%i2 + 0 ] %asi
membar #Sync
loop_exit_1_83:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_83
nop
P818: !_DWLD [13] (Int) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_84:
sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
ldx [%i3 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_1_84:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_84
nop
P819: !_BLD [20] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_85:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P820: !_BLD [29] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f32
membar #Sync
! 4 addresses covered
fmovd %f32, %f4
fmovd %f34, %f18
fmovs %f19, %f6
fmovd %f40, %f18
fmovs %f18, %f7
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovd %f4, %f30
fmovd %f6, %f30
!--
loop_exit_1_85:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_85
nop
P821: !_LD [21] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_86:
sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P822: !_CASX [13] (maybe <- 0x800013) (Int)
sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
ldx [%i3], %l3
! move %l3(upper) -> %o0(lower)
srlx %l3, 32, %l6
or %l6, %o0, %o0
! move %l3(lower) -> %o1(upper)
sllx %l3, 32, %o1
mov %l3, %l6
sllx %l4, 32, %l3
add %l4, 1, %l4
or %l4, %l3, %l3
casx [%i3], %l6, %l3
! move %l3(upper) -> %o1(lower)
srlx %l3, 32, %l6
or %l6, %o1, %o1
! move %l3(lower) -> %o2(upper)
sllx %l3, 32, %o2
add %l4, 1, %l4
P823: !_LD [8] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 0], %o5
! move %o5(lower) -> %o2(lower)
or %o5, %o2, %o2
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
mov %o2, %l5
loop_exit_1_86:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_86
nop
P824: !_LD [17] (Int) (Loop entry) (CBR)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_87:
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET824
nop
RET824:
! lfsr step begin
srlx %l0, 1, %o5
xnor %o5, %l0, %o5
sllx %o5, 63, %o5
or %o5, %l0, %l0
srlx %l0, 1, %l0
P825: !_SWAP [28] (maybe <- 0x800015) (Int) (Loop exit)
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
mov %l4, %o5
swap [%i2 + 0], %o5
! move %o5(lower) -> %o0(lower)
srl %o5, 0, %l6
or %l6, %o0, %o0
add %l4, 1, %l4
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_1_87:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_87
nop
P826: !_DWLD [6] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_88:
ldx [%i1 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P827: !_DWLD [12] (FP)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i3
sub %i0, %i3, %i3
ldd [%i3 + 0], %f0
! 2 addresses covered
P828: !_LD [3] (Int) (Loop exit)
lduw [%i0 + 32], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
!--
loop_exit_1_88:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_88
nop
P829: !_DWLD [2] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_89:
ldd [%i0 + 8], %f0
! 1 addresses covered
fmovs %f1, %f0
P830: !_REPLACEMENT [25] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS3_O), %i2
sub %i0, %i2, %i2
sethi %hi(0x10000), %l3
ld [%i2+4], %l7
st %l7, [%i2+4]
add %i2, %l3, %l6
ld [%l6+4], %l7
st %l7, [%l6+4]
add %l6, %l3, %l6
ld [%l6+4], %l7
st %l7, [%l6+4]
add %l6, %l3, %l6
ld [%l6+4], %l7
st %l7, [%l6+4]
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
loop_exit_1_89:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_89
nop
P831: !_DWLD [15] (Int) (Loop entry) (CBR)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_90:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 32], %o0
! move %o0(upper) -> %o0(upper)
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET831
nop
RET831:
! lfsr step begin
srlx %l0, 1, %o5
xnor %o5, %l0, %o5
sllx %o5, 63, %o5
or %o5, %l0, %l0
srlx %l0, 1, %l0
P832: !_LD [8] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 0], %l6
! move %l6(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_1_90:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_90
nop
P833: !_DWLD [17] (Int) (Loop entry) (Branch target of P839)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_91:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
ba P834
nop
TARGET839:
ba RET839
nop
P834: !_LD [24] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 0], %o1
! move %o1(lower) -> %o1(upper)
sllx %o1, 32, %o1
P835: !_LD [17] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 4], %l7
! move %l7(lower) -> %o1(lower)
or %l7, %o1, %o1
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_1_91:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_91
nop
P836: !_BLD [12] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_92:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P837: !_LD [21] (Int) (CBR) (Branch target of P1042)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET837
nop
RET837:
! lfsr step begin
srlx %l0, 1, %o5
xnor %o5, %l0, %o5
sllx %o5, 63, %o5
or %o5, %l0, %l0
srlx %l0, 1, %l0
ba P838
nop
TARGET1042:
ba RET1042
nop
P838: !_LD [14] (Int) (Loop exit)
lduw [%i2 + 12], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_1_92:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_92
nop
P839: !_BLD [22] (FP) (Loop entry) (Loop exit) (CBR)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_93:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET839
nop
RET839:
! lfsr step begin
srlx %l0, 1, %l3
xnor %l3, %l0, %l3
sllx %l3, 63, %l3
or %l3, %l0, %l0
srlx %l0, 1, %l0
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_1_93:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_93
nop
P840: !_BST [22] (maybe <- 0x40000015) (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_94:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
sub %i0, %i3, %i3
! preparing store val #0, next val will be in f32
fmovs %f16, %f20
fadds %f16, %f17, %f16
! preparing store val #1, next val will be in f33
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #2, next val will be in f35
fmovd %f20, %f32
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #3, next val will be in f40
fmovd %f20, %f34
fmovs %f16, %f20
fadds %f16, %f17, %f16
fmovd %f20, %f40
membar #Sync
stda %f32, [%i3 + 0 ] %asi
membar #Sync
loop_exit_1_94:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_94
nop
P841: !_LD [6] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_95:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 6
sethi %hi(0xc0000), %l7
sub %i1, %l7, %i1
lduw [%i1 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P842: !_LD [4] (Int) (Loop exit)
lduw [%i1 + 0], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
sethi %hi(0xc0000), %o5
add %i1, %o5, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_1_95:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_95
nop
P843: !_REPLACEMENT [15] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_96:
sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS3_O), %i2
sub %i0, %i2, %i2
sethi %hi(0x10000), %l6
ld [%i2+32], %o5
st %o5, [%i2+32]
add %i2, %l6, %l7
ld [%l7+32], %o5
st %o5, [%l7+32]
add %l7, %l6, %l7
ld [%l7+32], %o5
st %o5, [%l7+32]
add %l7, %l6, %l7
ld [%l7+32], %o5
st %o5, [%l7+32]
P844: !_BLD [29] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_1_96:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_96
nop
P845: !_DWLD [16] (Int) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_97:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_1_97:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_97
nop
P846: !_DWLD [6] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_98:
ldd [%i1 + 8], %f0
! 1 addresses covered
fmovs %f1, %f0
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
loop_exit_1_98:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_98
nop
P847: !_BLD [12] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_99:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_1_99:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_99
nop
P848: !_LD [3] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_100:
ld [%i0 + 32], %f0
! 1 addresses covered
P849: !_DWLD [31] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 32], %o0
! move %o0(upper) -> %o0(upper)
P850: !_LD [1] (Int) (Loop exit)
lduw [%i0 + 4], %l3
! move %l3(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
loop_exit_1_100:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_100
nop
P851: !_LD [25] (Int) (Loop entry) (CBR)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_101:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET851
nop
RET851:
! lfsr step begin
srlx %l0, 1, %l6
xnor %l6, %l0, %l6
sllx %l6, 63, %l6
or %l6, %l0, %l0
srlx %l0, 1, %l0
P852: !_LD [25] (Int) (Loop exit)
lduw [%i3 + 4], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_1_101:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_101
nop
P853: !_DWLD [5] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_102:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 5
sethi %hi(0xc0000), %l6
sub %i1, %l6, %i1
ldx [%i1 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
P854: !_DWLD [29] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 0], %o1
! move %o1(upper) -> %o1(upper)
! move %o1(lower) -> %o1(lower)
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
sethi %hi(0xc0000), %l7
add %i1, %l7, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_1_102:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_102
nop
P855: !_PREFETCH [1] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_103:
prefetch [%i0 + 4], 1
P856: !_NOP (Int) (Loop exit)
nop
loop_exit_1_103:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_103
nop
P857: !_LD [21] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_104:
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P858: !_LD [19] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 32], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_1_104:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_104
nop
P859: !_CASX [3] (maybe <- 0x800016) (Int) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_105:
add %i0, 32, %l6
ldx [%l6], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
mov %o0, %l3
sllx %l4, 32, %o1
casx [%l6], %l3, %o1
! move %o1(upper) -> %o1(upper)
! move %o1(lower) -> %o1(lower)
add %l4, 1, %l4
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_1_105:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_105
nop
P860: !_BLD [21] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_106:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_1_106:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_106
nop
P861: !_DWLD [6] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_107:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 6
sethi %hi(0xc0000), %l7
sub %i1, %l7, %i1
ldx [%i1 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P862: !_LD [4] (Int) (Loop exit)
lduw [%i1 + 0], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
sethi %hi(0xc0000), %o5
add %i1, %o5, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_1_107:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_107
nop
P863: !_LD [0] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_108:
lduw [%i0 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P864: !_LD [5] (Int) (Loop exit)
lduw [%i1 + 4], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_1_108:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_108
nop
P865: !_BLD [29] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_109:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_1_109:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_109
nop
P866: !_DWLD [3] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_110:
ldx [%i0 + 32], %o0
! move %o0(upper) -> %o0(upper)
P867: !_LD [24] (Int) (Loop exit) (LE) (CBR) (Branch target of P662)
wr %g0, 0x88, %asi
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduwa [%i3 + 0] %asi, %l3
! move %l3(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %l3, %o0, %o0
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET867
nop
RET867:
! lfsr step begin
srlx %l0, 1, %l6
xnor %l6, %l0, %l6
sllx %l6, 63, %l6
or %l6, %l0, %l0
srlx %l0, 1, %l0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_1_110:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_110
nop
ba P868
nop
TARGET662:
ba RET662
nop
P868: !_DWLD [14] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_111:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P869: !_BLD [9] (FP)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P870: !_LD [23] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 32], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_1_111:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_111
nop
P871: !_LD [0] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_112:
lduw [%i0 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P872: !_BLD [1] (FP)
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i0 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P873: !_LD [7] (Int) (Loop exit)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 7
sethi %hi(0xc0000), %l3
sub %i1, %l3, %i1
lduw [%i1 + 32], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
sethi %hi(0xc0000), %o5
add %i1, %o5, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_1_112:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_112
nop
P874: !_LD [0] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_113:
lduw [%i0 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P875: !_LD [16] (Int) (Loop exit)
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 0], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_1_113:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_113
nop
P876: !_BLD [24] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_114:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_1_114:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_114
nop
P877: !_BLD [8] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_115:
wr %g0, 0xf0, %asi
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_1_115:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_115
nop
P878: !_BLD [26] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_116:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P879: !_LD [12] (Int) (CBR)
sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET879
nop
RET879:
! lfsr step begin
srlx %l0, 1, %l3
xnor %l3, %l0, %l3
sllx %l3, 63, %l3
or %l3, %l0, %l0
srlx %l0, 1, %l0
P880: !_LD [16] (Int) (Loop exit)
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 0], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_1_116:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_116
nop
P881: !_LD [16] (Int) (Loop entry) (LE)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_117:
wr %g0, 0x88, %asi
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduwa [%i3 + 0] %asi, %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P882: !_BLD [14] (FP)
wr %g0, 0xf0, %asi
sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P883: !_LD [23] (Int) (Loop exit)
sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 32], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_1_117:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_117
nop
P884: !_DWLD [16] (Int) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_118:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_1_118:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_118
nop
P885: !_BLD [31] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_119:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P886: !_CAS [20] (maybe <- 0x800017) (Int) (Loop exit)
sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2], %o0
mov %o0, %o5
! move %o5(lower) -> %o0(upper)
sllx %o5, 32, %o0
mov %l4, %l7
cas [%i2], %o5, %l7
! move %l7(lower) -> %o0(lower)
srl %l7, 0, %o5
or %o5, %o0, %o0
add %l4, 1, %l4
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_1_119:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_119
nop
P887: !_BLD [1] (FP) (Loop entry) (Loop exit) (CBR)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_120:
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i0 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET887
nop
RET887:
! lfsr step begin
srlx %l0, 1, %l6
xnor %l6, %l0, %l6
sllx %l6, 63, %l6
or %l6, %l0, %l0
srlx %l0, 1, %l0
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_1_120:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_120
nop
P888: !_BLD [6] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_121:
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_1_121:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_121
nop
P889: !_BLD [24] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_122:
wr %g0, 0xf0, %asi
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_1_122:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_122
nop
P890: !_PREFETCH [15] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_123:
sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
prefetch [%i2 + 32], 1
P891: !_DWLD [31] (Int)
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
ldx [%i3 + 32], %o0
! move %o0(upper) -> %o0(upper)
P892: !_LD [1] (Int) (Loop exit)
lduw [%i0 + 4], %l7
! move %l7(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_1_123:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_123
nop
P893: !_LD [28] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_124:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P894: !_BLD [2] (FP)
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i0 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P895: !_LD [29] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 4], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_1_124:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_124
nop
P896: !_LD [2] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_125:
lduw [%i0 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P897: !_LD [1] (Int) (Loop exit)
lduw [%i0 + 4], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_1_125:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_125
nop
P898: !_DWLD [13] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_126:
sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
ldx [%i2 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
P899: !_BLD [23] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_1_126:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_126
nop
P900: !_BLD [8] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_127:
wr %g0, 0xf0, %asi
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_1_127:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_127
nop
P901: !_DWLD [2] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_128:
ldd [%i0 + 8], %f0
! 1 addresses covered
fmovs %f1, %f0
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
loop_exit_1_128:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_128
nop
P902: !_DWST [19] (maybe <- 0x800018) (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_129:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
sub %i0, %i3, %i3
mov %l4, %l3
sllx %l3, 32, %l3
stx %l3, [%i3 + 32 ]
add %l4, 1, %l4
P903: !_LD [16] (FP) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i2
sub %i0, %i2, %i2
ld [%i2 + 0], %f0
! 1 addresses covered
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
loop_exit_1_129:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_129
nop
P904: !_LD [30] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_130:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i3
sub %i0, %i3, %i3
ld [%i3 + 12], %f0
! 1 addresses covered
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
loop_exit_1_130:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_130
nop
P905: !_LD [30] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_131:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i2
sub %i0, %i2, %i2
ld [%i2 + 12], %f0
! 1 addresses covered
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
loop_exit_1_131:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_131
nop
P906: !_DWLD [1] (Int) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_132:
ldx [%i0 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_1_132:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_132
nop
P907: !_DWLD [2] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_133:
ldx [%i0 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P908: !_LD [19] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_1_133:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_133
nop
P909: !_BLD [28] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_134:
wr %g0, 0xf0, %asi
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P910: !_BLD [14] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f32
membar #Sync
! 4 addresses covered
fmovd %f32, %f4
fmovd %f34, %f18
fmovs %f19, %f6
fmovd %f40, %f18
fmovs %f18, %f7
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovd %f4, %f30
fmovd %f6, %f30
!--
loop_exit_1_134:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_134
nop
P911: !_LD [22] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_135:
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P912: !_LD [0] (Int) (Loop exit)
lduw [%i0 + 0], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_1_135:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_135
nop
P913: !_BLD [5] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_136:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 5
sethi %hi(0xc0000), %l6
sub %i1, %l6, %i1
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
sethi %hi(0xc0000), %l7
add %i1, %l7, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_1_136:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_136
nop
P914: !_BLD [20] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_137:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P915: !_DWST [12] (maybe <- 0x800019) (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i2
sub %i0, %i2, %i2
sllx %l4, 32, %l3
add %l4, 1, %l4
or %l3, %l4, %l3
stx %l3, [%i2 + 0]
add %l4, 1, %l4
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_1_137:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_137
nop
P916: !_LD [25] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_138:
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P917: !_BLD [7] (FP)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 7
sethi %hi(0xc0000), %l7
sub %i1, %l7, %i1
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P918: !_LD [20] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 0], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
sethi %hi(0xc0000), %l6
add %i1, %l6, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_1_138:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_138
nop
P919: !_LD [13] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_139:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P920: !_LD [29] (Int) (Loop exit)
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 4], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_1_139:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_139
nop
P921: !_DWLD [7] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_140:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 7
sethi %hi(0xc0000), %l3
sub %i1, %l3, %i1
ldx [%i1 + 32], %o0
! move %o0(upper) -> %o0(upper)
P922: !_LD [23] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %l3
! move %l3(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
sethi %hi(0xc0000), %l6
add %i1, %l6, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_1_140:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_140
nop
P923: !_BLD [22] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_141:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P924: !_DWLD [18] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P925: !_LD [2] (Int) (Loop exit)
lduw [%i0 + 12], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_1_141:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_141
nop
P926: !_NOP (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_142:
nop
P927: !_BLD [9] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_1_142:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_142
nop
P928: !_DWLD [21] (Int) (Loop entry) (Loop exit) (LE)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_143:
wr %g0, 0x88, %asi
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i3
sub %i0, %i3, %i3
ldxa [%i3 + 0] %asi, %l3
! move %l3(lower) -> %o0(upper)
sllx %l3, 32, %o0
! move %l3(upper) -> %o0(lower)
srlx %l3, 32, %o5
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_1_143:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_143
nop
P929: !_LD [14] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_144:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P930: !_BLD [5] (FP)
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P931: !_LD [11] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_1_144:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_144
nop
P932: !_LD [27] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_145:
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P933: !_LD [16] (Int) (Loop exit) (Branch target of P887)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_1_145:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_145
nop
ba P934
nop
TARGET887:
ba RET887
nop
P934: !_LD [19] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_146:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P935: !_DWLD [2] (Int) (Loop exit)
ldx [%i0 + 8], %o5
! move %o5(lower) -> %o0(lower)
srl %o5, 0, %l7
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_1_146:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_146
nop
P936: !_LD [30] (Int) (Loop entry) (LE)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_147:
wr %g0, 0x88, %asi
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduwa [%i3 + 12] %asi, %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P937: !_LD [28] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 0], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_1_147:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_147
nop
P938: !_DWLD [17] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_148:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
P939: !_BLD [2] (FP) (Loop exit)
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i0 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_1_148:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_148
nop
P940: !_BLD [21] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_149:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P941: !_DWLD [27] (Int) (Branch target of P1101)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 32], %o0
! move %o0(upper) -> %o0(upper)
ba P942
nop
TARGET1101:
ba RET1101
nop
P942: !_LD [17] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %o5
! move %o5(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_1_149:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_149
nop
P943: !_LD [24] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_150:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P944: !_LD [31] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 32], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_1_150:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_150
nop
P945: !_BLD [8] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_151:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P946: !_BSTC [8] (maybe <- 0x40000019) (FP) (Loop exit)
wr %g0, 0xe0, %asi
! preparing store val #0, next val will be in f32
fmovs %f16, %f20
fadds %f16, %f17, %f16
! preparing store val #1, next val will be in f33
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #2, next val will be in f35
fmovd %f20, %f32
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #3, next val will be in f40
fmovd %f20, %f34
fmovs %f16, %f20
fadds %f16, %f17, %f16
fmovd %f20, %f40
membar #Sync
stda %f32, [%i3 + 0 ] %asi
membar #Sync
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_1_151:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_151
nop
P947: !_DWLD [8] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_152:
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
ldx [%i2 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
P948: !_DWLD [5] (Int) (Loop exit)
ldx [%i1 + 0], %o1
! move %o1(upper) -> %o1(upper)
! move %o1(lower) -> %o1(lower)
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_1_152:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_152
nop
P949: !_BLD [14] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_153:
wr %g0, 0xf0, %asi
sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P950: !_BLD [1] (FP) (Loop exit)
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i0 + 0] %asi, %f32
membar #Sync
! 4 addresses covered
fmovd %f32, %f4
fmovd %f34, %f18
fmovs %f19, %f6
fmovd %f40, %f18
fmovs %f18, %f7
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovd %f4, %f30
fmovd %f6, %f30
!--
loop_exit_1_153:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_153
nop
P951: !_REPLACEMENT [9] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_154:
sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
sethi %hi(0x10000), %l6
ld [%i2+4], %o5
st %o5, [%i2+4]
add %i2, %l6, %l7
ld [%l7+4], %o5
st %o5, [%l7+4]
add %l7, %l6, %l7
ld [%l7+4], %o5
st %o5, [%l7+4]
add %l7, %l6, %l7
ld [%l7+4], %o5
st %o5, [%l7+4]
P952: !_DWLD [0] (FP) (Loop exit)
ldd [%i0 + 0], %f0
! 2 addresses covered
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
!--
loop_exit_1_154:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_154
nop
P953: !_CAS [2] (maybe <- 0x80001b) (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_155:
add %i0, 12, %o5
lduw [%o5], %o0
mov %o0, %l7
! move %l7(lower) -> %o0(upper)
sllx %l7, 32, %o0
mov %l4, %l6
cas [%o5], %l7, %l6
! move %l6(lower) -> %o0(lower)
srl %l6, 0, %l7
or %l7, %o0, %o0
add %l4, 1, %l4
P954: !_DWLD [31] (Int) (Branch target of P788)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 32], %o1
! move %o1(upper) -> %o1(upper)
ba P955
nop
TARGET788:
ba RET788
nop
P955: !_LD [4] (Int) (Loop exit)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 4
sethi %hi(0xc0000), %l3
sub %i1, %l3, %i1
lduw [%i1 + 0], %l7
! move %l7(lower) -> %o1(lower)
srlx %o1, 32, %o1
sllx %o1, 32, %o1
or %l7, %o1, %o1
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
sethi %hi(0xc0000), %o5
add %i1, %o5, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_1_155:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_155
nop
P956: !_BLD [10] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_156:
wr %g0, 0xf0, %asi
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P957: !_SWAP [27] (maybe <- 0x80001c) (Int)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i3
sub %i0, %i3, %i3
mov %l4, %o0
swap [%i3 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
add %l4, 1, %l4
P958: !_LD [24] (Int) (Loop exit)
lduw [%i3 + 0], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_1_156:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_156
nop
P959: !_DWLD [15] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_157:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 32], %o0
! move %o0(upper) -> %o0(upper)
P960: !_BLD [24] (FP) (CBR)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET960
nop
RET960:
! lfsr step begin
srlx %l0, 1, %l7
xnor %l7, %l0, %l7
sllx %l7, 63, %l7
or %l7, %l0, %l0
srlx %l0, 1, %l0
P961: !_LD [24] (Int) (Loop exit)
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 0], %l6
! move %l6(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_1_157:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_157
nop
P962: !_LD [10] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_158:
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P963: !_LD [5] (Int) (Loop exit)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 5
sethi %hi(0xc0000), %l6
sub %i1, %l6, %i1
lduw [%i1 + 4], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
sethi %hi(0xc0000), %l3
add %i1, %l3, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_1_158:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_158
nop
P964: !_BLD [20] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_159:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P965: !_DWLD [2] (Int)
ldx [%i0 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P966: !_LD [19] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_1_159:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_159
nop
P967: !_DWLD [14] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_160:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P968: !_LD [13] (Int) (Loop exit)
lduw [%i2 + 4], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_1_160:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_160
nop
P969: !_DWLD [11] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_161:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 32], %o0
! move %o0(upper) -> %o0(upper)
P970: !_DWLD [6] (Int) (Loop exit)
ldx [%i1 + 8], %l6
! move %l6(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
srl %l6, 0, %l3
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_1_161:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_161
nop
P971: !_DWLD [16] (Int) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_162:
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
ldx [%i2 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_1_162:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_162
nop
P972: !_BLD [2] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_163:
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i0 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P973: !_DWLD [30] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P974: !_LD [13] (Int) (Loop exit) (Branch target of P1090)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_1_163:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_163
nop
ba P975
nop
TARGET1090:
ba RET1090
nop
P975: !_BLD [6] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_164:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 6
sethi %hi(0xc0000), %l6
sub %i1, %l6, %i1
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P976: !_LD [13] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P977: !_LD [20] (Int) (Loop exit)
sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 0], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
sethi %hi(0xc0000), %o5
add %i1, %o5, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_1_164:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_164
nop
P978: !_BLD [31] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_165:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P979: !_LD [29] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P980: !_LD [20] (Int) (Loop exit)
sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 0], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_1_165:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_165
nop
P981: !_DWLD [29] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_166:
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
ldd [%i2 + 0], %f0
! 2 addresses covered
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
!--
loop_exit_1_166:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_166
nop
P982: !_DWLD [4] (Int) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_167:
ldx [%i1 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_1_167:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_167
nop
P983: !_DWLD [23] (Int) (Loop entry) (CBR)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_168:
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 32], %o0
! move %o0(upper) -> %o0(upper)
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET983
nop
RET983:
! lfsr step begin
srlx %l0, 1, %l7
xnor %l7, %l0, %l7
sllx %l7, 63, %l7
or %l7, %l0, %l0
srlx %l0, 1, %l0
P984: !_LD [17] (FP)
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
ld [%i2 + 4], %f0
! 1 addresses covered
P985: !_LD [15] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %l6
! move %l6(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
loop_exit_1_168:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_168
nop
P986: !_LD [29] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_169:
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
ld [%i2 + 4], %f0
! 1 addresses covered
P987: !_DWLD [21] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
loop_exit_1_169:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_169
nop
P988: !_PREFETCH [2] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_170:
prefetch [%i0 + 12], 1
P989: !_LD [16] (Int) (CBR)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET989
nop
RET989:
! lfsr step begin
srlx %l0, 1, %l7
xnor %l7, %l0, %l7
sllx %l7, 63, %l7
or %l7, %l0, %l0
srlx %l0, 1, %l0
P990: !_LD [24] (Int) (Loop exit)
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 0], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_1_170:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_170
nop
P991: !_LD [12] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_171:
sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P992: !_LD [29] (FP)
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
ld [%i3 + 4], %f0
! 1 addresses covered
P993: !_LD [8] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 0], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
loop_exit_1_171:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_171
nop
P994: !_BLD [7] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_172:
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_1_172:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_172
nop
P995: !_BSTC [20] (maybe <- 0x4000001d) (FP) (Loop entry) (CBR)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_173:
wr %g0, 0xe0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i3
sub %i0, %i3, %i3
! preparing store val #0, next val will be in f32
fmovs %f16, %f20
fadds %f16, %f17, %f16
! preparing store val #1, next val will be in f33
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #2, next val will be in f35
fmovd %f20, %f32
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #3, next val will be in f40
fmovd %f20, %f34
fmovs %f16, %f20
fadds %f16, %f17, %f16
fmovd %f20, %f40
membar #Sync
stda %f32, [%i3 + 0 ] %asi
membar #Sync
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET995
nop
RET995:
! lfsr step begin
srlx %l0, 1, %l7
xnor %l7, %l0, %l7
sllx %l7, 63, %l7
or %l7, %l0, %l0
srlx %l0, 1, %l0
P996: !_DWLD [30] (Int)
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
ldx [%i2 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P997: !_LD [24] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_1_173:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_173
nop
P998: !_DWLD [24] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_174:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
P999: !_DWLD [16] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 0], %o1
! move %o1(upper) -> %o1(upper)
! move %o1(lower) -> %o1(lower)
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_1_174:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_174
nop
P1000: !_REPLACEMENT [22] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_175:
sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
sethi %hi(0x10000), %o5
ld [%i2+12], %l6
st %l6, [%i2+12]
add %i2, %o5, %l3
ld [%l3+12], %l6
st %l6, [%l3+12]
add %l3, %o5, %l3
ld [%l3+12], %l6
st %l6, [%l3+12]
add %l3, %o5, %l3
ld [%l3+12], %l6
st %l6, [%l3+12]
P1001: !_LD [26] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1002: !_LD [27] (Int) (Loop exit)
lduw [%i3 + 32], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_1_175:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_175
nop
P1003: !_REPLACEMENT [19] (Int) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_176:
sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS2_O), %i2
sub %i0, %i2, %i2
sethi %hi(0x10000), %l6
ld [%i2+32], %o5
st %o5, [%i2+32]
add %i2, %l6, %l7
ld [%l7+32], %o5
st %o5, [%l7+32]
add %l7, %l6, %l7
ld [%l7+32], %o5
st %o5, [%l7+32]
add %l7, %l6, %l7
ld [%l7+32], %o5
st %o5, [%l7+32]
loop_exit_1_176:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_176
nop
P1004: !_LD [9] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_177:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1005: !_LD [9] (Int) (Loop exit) (CBR)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET1005
nop
RET1005:
! lfsr step begin
srlx %l0, 1, %l7
xnor %l7, %l0, %l7
sllx %l7, 63, %l7
or %l7, %l0, %l0
srlx %l0, 1, %l0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_1_177:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_177
nop
P1006: !_ST [30] (maybe <- 0x80001d) (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_178:
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
stw %l4, [%i3 + 12 ]
add %l4, 1, %l4
P1007: !_NOP (Int) (Loop exit)
nop
loop_exit_1_178:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_178
nop
P1008: !_BLD [14] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_179:
wr %g0, 0xf0, %asi
sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_1_179:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_179
nop
P1009: !_LD [12] (Int) (Loop entry) (LE)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_180:
wr %g0, 0x88, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduwa [%i3 + 0] %asi, %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1010: !_LD [1] (Int) (Loop exit)
lduw [%i0 + 4], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_1_180:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_180
nop
P1011: !_DWLD [11] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_181:
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
ldx [%i2 + 32], %o0
! move %o0(upper) -> %o0(upper)
P1012: !_LD [22] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %l3
! move %l3(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_1_181:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_181
nop
P1013: !_CASX [21] (maybe <- 0x80001e) (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_182:
sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
ldx [%i2], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
mov %o0, %o5
sllx %l4, 32, %o1
add %l4, 1, %l4
or %l4, %o1, %o1
casx [%i2], %o5, %o1
! move %o1(upper) -> %o1(upper)
! move %o1(lower) -> %o1(lower)
add %l4, 1, %l4
P1014: !_BLD [3] (FP) (Loop exit)
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i0 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_1_182:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_182
nop
P1015: !_LD [16] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_183:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1016: !_LD [17] (Int) (Loop exit)
lduw [%i3 + 4], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_1_183:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_183
nop
P1017: !_LD [14] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_184:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1018: !_DWLD [5] (Int)
ldx [%i1 + 0], %l7
! move %l7(upper) -> %o0(lower)
srlx %l7, 32, %l6
or %l6, %o0, %o0
! move %l7(lower) -> %o1(upper)
sllx %l7, 32, %o1
P1019: !_LD [19] (Int) (Loop exit)
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 32], %l6
! move %l6(lower) -> %o1(lower)
or %l6, %o1, %o1
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_1_184:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_184
nop
P1020: !_BLD [1] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_185:
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i0 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_1_185:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_185
nop
P1021: !_BLD [7] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_186:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 7
sethi %hi(0xc0000), %l3
sub %i1, %l3, %i1
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P1022: !_LD [16] (Int)
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1023: !_LD [18] (Int) (Loop exit) (LE) (Branch target of P995)
wr %g0, 0x88, %asi
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduwa [%i3 + 12] %asi, %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
sethi %hi(0xc0000), %l7
add %i1, %l7, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_1_186:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_186
nop
ba P1024
nop
TARGET995:
ba RET995
nop
P1024: !_MEMBAR (Int) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_187:
membar #StoreLoad
loop_exit_1_187:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_187
nop
P1025: !_BSTC [13] (maybe <- 0x40000021) (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_188:
wr %g0, 0xe0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i2
sub %i0, %i2, %i2
! preparing store val #0, next val will be in f32
fmovs %f16, %f20
fadds %f16, %f17, %f16
! preparing store val #1, next val will be in f33
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #2, next val will be in f35
fmovd %f20, %f32
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #3, next val will be in f40
fmovd %f20, %f34
fmovs %f16, %f20
fadds %f16, %f17, %f16
fmovd %f20, %f40
membar #Sync
stda %f32, [%i2 + 0 ] %asi
membar #Sync
loop_exit_1_188:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_188
nop
P1026: !_LD [2] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_189:
lduw [%i0 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1027: !_LD [19] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_1_189:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_189
nop
P1028: !_LD [15] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_190:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1029: !_LD [25] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 4], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_1_190:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_190
nop
P1030: !_BLD [0] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_191:
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i0 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P1031: !_BLD [9] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f32
membar #Sync
! 4 addresses covered
fmovd %f32, %f4
fmovd %f34, %f18
fmovs %f19, %f6
fmovd %f40, %f18
fmovs %f18, %f7
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovd %f4, %f30
fmovd %f6, %f30
!--
loop_exit_1_191:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_191
nop
P1032: !_DWLD [27] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_192:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 32], %o0
! move %o0(upper) -> %o0(upper)
P1033: !_LD [15] (Int) (Loop exit) (LE)
wr %g0, 0x88, %asi
sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduwa [%i2 + 32] %asi, %o5
! move %o5(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_1_192:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_192
nop
P1034: !_BLD [19] (FP) (Loop entry) (Loop exit) (CBR)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_193:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET1034
nop
RET1034:
! lfsr step begin
srlx %l0, 1, %l6
xnor %l6, %l0, %l6
sllx %l6, 63, %l6
or %l6, %l0, %l0
srlx %l0, 1, %l0
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_1_193:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_193
nop
P1035: !_LD [3] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_194:
lduw [%i0 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1036: !_BST [19] (maybe <- 0x40000025) (FP)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i2
sub %i0, %i2, %i2
! preparing store val #0, next val will be in f32
fmovs %f16, %f20
fadds %f16, %f17, %f16
! preparing store val #1, next val will be in f33
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #2, next val will be in f35
fmovd %f20, %f32
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #3, next val will be in f40
fmovd %f20, %f34
fmovs %f16, %f20
fadds %f16, %f17, %f16
fmovd %f20, %f40
membar #Sync
stda %f32, [%i2 + 0 ] %asi
membar #Sync
P1037: !_LD [19] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_1_194:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_194
nop
P1038: !_LD [24] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_195:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1039: !_BLD [10] (FP) (CBR)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET1039
nop
RET1039:
! lfsr step begin
srlx %l0, 1, %l3
xnor %l3, %l0, %l3
sllx %l3, 63, %l3
or %l3, %l0, %l0
srlx %l0, 1, %l0
P1040: !_LD [10] (Int) (Loop exit) (Branch target of P1099)
lduw [%i3 + 12], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_1_195:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_195
nop
ba P1041
nop
TARGET1099:
ba RET1099
nop
P1041: !_DWLD [9] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_196:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
P1042: !_DWLD [9] (Int) (Loop exit) (CBR)
ldx [%i2 + 0], %o1
! move %o1(upper) -> %o1(upper)
! move %o1(lower) -> %o1(lower)
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET1042
nop
RET1042:
! lfsr step begin
srlx %l0, 1, %l6
xnor %l6, %l0, %l6
sllx %l6, 63, %l6
or %l6, %l0, %l0
srlx %l0, 1, %l0
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_1_196:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_196
nop
P1043: !_LD [20] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_197:
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1044: !_LD [4] (Int) (Loop exit)
lduw [%i1 + 0], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_1_197:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_197
nop
P1045: !_REPLACEMENT [22] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_198:
sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS3_O), %i2
sub %i0, %i2, %i2
sethi %hi(0x10000), %l7
ld [%i2+12], %l3
st %l3, [%i2+12]
add %i2, %l7, %o5
ld [%o5+12], %l3
st %l3, [%o5+12]
add %o5, %l7, %o5
ld [%o5+12], %l3
st %l3, [%o5+12]
add %o5, %l7, %o5
ld [%o5+12], %l3
st %l3, [%o5+12]
P1046: !_DWLD [24] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_1_198:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_198
nop
P1047: !_ST [12] (maybe <- 0x40000029) (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_199:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i2
sub %i0, %i2, %i2
! preparing store val #0, next val will be in f20
fmovs %f16, %f20
fadds %f16, %f17, %f16
st %f20, [%i2 + 0 ]
P1048: !_DWLD [18] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1049: !_LD [16] (Int) (Loop exit)
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 0], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_1_199:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_199
nop
P1050: !_LD [25] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_200:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1051: !_BLD [15] (FP)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P1052: !_LD [13] (Int) (Loop exit)
lduw [%i2 + 4], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_1_200:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_200
nop
P1053: !_ST [31] (maybe <- 0x800020) (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_201:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
sub %i0, %i3, %i3
stw %l4, [%i3 + 32 ]
add %l4, 1, %l4
P1054: !_BLD [23] (FP) (Loop exit) (CBR)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET1054
nop
RET1054:
! lfsr step begin
srlx %l0, 1, %l3
xnor %l3, %l0, %l3
sllx %l3, 63, %l3
or %l3, %l0, %l0
srlx %l0, 1, %l0
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_1_201:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_201
nop
P1055: !_BLD [3] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_202:
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i0 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_1_202:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_202
nop
P1056: !_LD [14] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_203:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1057: !_LD [14] (Int) (Loop exit) (CBR) (Branch target of P1243)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET1057
nop
RET1057:
! lfsr step begin
srlx %l0, 1, %l6
xnor %l6, %l0, %l6
sllx %l6, 63, %l6
or %l6, %l0, %l0
srlx %l0, 1, %l0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_1_203:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_203
nop
ba P1058
nop
TARGET1243:
ba RET1243
nop
P1058: !_DWLD [23] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_204:
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 32], %o0
! move %o0(upper) -> %o0(upper)
P1059: !_LD [3] (Int) (Loop exit) (Branch target of P851)
lduw [%i0 + 32], %o5
! move %o5(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_1_204:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_204
nop
ba P1060
nop
TARGET851:
ba RET851
nop
P1060: !_LD [13] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_205:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1061: !_LD [7] (Int) (Loop exit)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 7
sethi %hi(0xc0000), %o5
sub %i1, %o5, %i1
lduw [%i1 + 32], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
sethi %hi(0xc0000), %l7
add %i1, %l7, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_1_205:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_205
nop
P1062: !_DWLD [7] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_206:
ldd [%i1 + 32], %f0
! 1 addresses covered
P1063: !_LD [6] (Int)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 6
sethi %hi(0xc0000), %o5
sub %i1, %o5, %i1
lduw [%i1 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1064: !_LD [26] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
sethi %hi(0xc0000), %l3
add %i1, %l3, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_1_206:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_206
nop
P1065: !_LD [4] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_207:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 4
sethi %hi(0xc0000), %l6
sub %i1, %l6, %i1
lduw [%i1 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1066: !_LD [19] (Int) (Loop exit)
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 32], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
sethi %hi(0xc0000), %l7
add %i1, %l7, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_1_207:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_207
nop
P1067: !_LD [16] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_208:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1068: !_LD [18] (Int) (Loop exit)
lduw [%i3 + 12], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_1_208:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_208
nop
P1069: !_DWLD [3] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_209:
ldx [%i0 + 32], %o0
! move %o0(upper) -> %o0(upper)
P1070: !_BLD [3] (FP)
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i0 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P1071: !_LD [7] (Int) (Loop exit)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 7
sethi %hi(0xc0000), %l3
sub %i1, %l3, %i1
lduw [%i1 + 32], %l7
! move %l7(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
sethi %hi(0xc0000), %o5
add %i1, %o5, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_1_209:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_209
nop
P1072: !_BLD [9] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_210:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_1_210:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_210
nop
P1073: !_DWLD [15] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_211:
sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
ldx [%i3 + 32], %o0
! move %o0(upper) -> %o0(upper)
P1074: !_BLD [21] (FP)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P1075: !_LD [17] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 4], %l7
! move %l7(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_1_211:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_211
nop
P1076: !_BLD [23] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_212:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P1077: !_BLD [16] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f32
membar #Sync
! 4 addresses covered
fmovd %f32, %f4
fmovd %f34, %f18
fmovs %f19, %f6
fmovd %f40, %f18
fmovs %f18, %f7
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovd %f4, %f30
fmovd %f6, %f30
!--
loop_exit_1_212:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_212
nop
P1078: !_LD [8] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_213:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1079: !_LD [18] (FP)
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
ld [%i3 + 12], %f0
! 1 addresses covered
P1080: !_LD [16] (Int) (Loop exit)
lduw [%i3 + 0], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
loop_exit_1_213:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_213
nop
P1081: !_DWLD [26] (Int) (Loop entry) (Branch target of P1189)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_214:
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
ldx [%i2 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
ba P1082
nop
TARGET1189:
ba RET1189
nop
P1082: !_LD [16] (FP)
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
ld [%i3 + 0], %f0
! 1 addresses covered
P1083: !_LD [4] (Int) (Loop exit)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 4
sethi %hi(0xc0000), %o5
sub %i1, %o5, %i1
lduw [%i1 + 0], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
sethi %hi(0xc0000), %l7
add %i1, %l7, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_1_214:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_214
nop
P1084: !_LD [19] (Int) (Loop entry) (LE)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_215:
wr %g0, 0x88, %asi
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduwa [%i2 + 32] %asi, %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1085: !_DWLD [14] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 8], %o5
! move %o5(lower) -> %o0(lower)
srl %o5, 0, %l7
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_1_215:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_215
nop
P1086: !_ST [28] (maybe <- 0x800021) (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_216:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
sub %i0, %i2, %i2
stw %l4, [%i2 + 0 ]
add %l4, 1, %l4
P1087: !_DWLD [26] (Int) (LE)
wr %g0, 0x88, %asi
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
sub %i0, %i3, %i3
ldxa [%i3 + 8] %asi, %l7
! move %l7(upper) -> %o0(upper)
or %l7, %g0, %o0
P1088: !_LD [22] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %l3
! move %l3(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_1_216:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_216
nop
P1089: !_DWLD [4] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_217:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 4
sethi %hi(0xc0000), %l7
sub %i1, %l7, %i1
ldx [%i1 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
P1090: !_BLD [28] (FP) (Loop exit) (CBR)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET1090
nop
RET1090:
! lfsr step begin
srlx %l0, 1, %l6
xnor %l6, %l0, %l6
sllx %l6, 63, %l6
or %l6, %l0, %l0
srlx %l0, 1, %l0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
sethi %hi(0xc0000), %l7
add %i1, %l7, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_1_217:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_217
nop
P1091: !_BSTC [25] (maybe <- 0x4000002a) (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_218:
wr %g0, 0xe0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i2
sub %i0, %i2, %i2
! preparing store val #0, next val will be in f32
fmovs %f16, %f20
fadds %f16, %f17, %f16
! preparing store val #1, next val will be in f33
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #2, next val will be in f35
fmovd %f20, %f32
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #3, next val will be in f40
fmovd %f20, %f34
fmovs %f16, %f20
fadds %f16, %f17, %f16
fmovd %f20, %f40
membar #Sync
stda %f32, [%i2 + 0 ] %asi
membar #Sync
loop_exit_1_218:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_218
nop
P1092: !_CASX [28] (maybe <- 0x800022) (Int) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_219:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
sub %i0, %i3, %i3
ldx [%i3], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
mov %o0, %l3
sllx %l4, 32, %o1
add %l4, 1, %l4
or %l4, %o1, %o1
casx [%i3], %l3, %o1
! move %o1(upper) -> %o1(upper)
! move %o1(lower) -> %o1(lower)
add %l4, 1, %l4
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_1_219:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_219
nop
P1093: !_DWLD [14] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_220:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1094: !_LD [30] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_1_220:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_220
nop
P1095: !_DWLD [28] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_221:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
P1096: !_DWLD [27] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 32], %o1
! move %o1(upper) -> %o1(upper)
P1097: !_LD [19] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 32], %l7
! move %l7(lower) -> %o1(lower)
srlx %o1, 32, %o1
sllx %o1, 32, %o1
or %l7, %o1, %o1
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_1_221:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_221
nop
P1098: !_BLD [18] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_222:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_1_222:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_222
nop
P1099: !_LD [24] (Int) (Loop entry) (CBR)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_223:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET1099
nop
RET1099:
! lfsr step begin
srlx %l0, 1, %l3
xnor %l3, %l0, %l3
sllx %l3, 63, %l3
or %l3, %l0, %l0
srlx %l0, 1, %l0
P1100: !_LD [7] (Int) (Loop exit)
lduw [%i1 + 32], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_1_223:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_223
nop
P1101: !_LD [30] (Int) (Loop entry) (CBR)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_224:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET1101
nop
RET1101:
! lfsr step begin
srlx %l0, 1, %o5
xnor %o5, %l0, %o5
sllx %o5, 63, %o5
or %o5, %l0, %l0
srlx %l0, 1, %l0
P1102: !_NOP (Int)
nop
P1103: !_LD [14] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_1_224:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_224
nop
P1104: !_DWLD [8] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_225:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
P1105: !_LD [9] (Int)
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 4], %o1
! move %o1(lower) -> %o1(upper)
sllx %o1, 32, %o1
P1106: !_LD [27] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %l7
! move %l7(lower) -> %o1(lower)
or %l7, %o1, %o1
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_1_225:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_225
nop
P1107: !_LD [10] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_226:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1108: !_BST [28] (maybe <- 0x4000002e) (FP)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i3
sub %i0, %i3, %i3
! preparing store val #0, next val will be in f32
fmovs %f16, %f20
fadds %f16, %f17, %f16
! preparing store val #1, next val will be in f33
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #2, next val will be in f35
fmovd %f20, %f32
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #3, next val will be in f40
fmovd %f20, %f34
fmovs %f16, %f20
fadds %f16, %f17, %f16
fmovd %f20, %f40
membar #Sync
stda %f32, [%i3 + 0 ] %asi
membar #Sync
P1109: !_LD [25] (Int) (Loop exit)
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 4], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_1_226:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_226
nop
P1110: !_BLD [9] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_227:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P1111: !_BLD [18] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f32
membar #Sync
! 4 addresses covered
fmovd %f32, %f4
fmovd %f34, %f18
fmovs %f19, %f6
fmovd %f40, %f18
fmovs %f18, %f7
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovd %f4, %f30
fmovd %f6, %f30
!--
loop_exit_1_227:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_227
nop
P1112: !_LD [9] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_228:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1113: !_LD [4] (Int) (Loop exit)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 4
sethi %hi(0xc0000), %l7
sub %i1, %l7, %i1
lduw [%i1 + 0], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
sethi %hi(0xc0000), %l6
add %i1, %l6, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_1_228:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_228
nop
P1114: !_LD [15] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_229:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1115: !_LD [18] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_1_229:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_229
nop
P1116: !_BLD [13] (FP) (Loop entry) (Loop exit) (CBR)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_230:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET1116
nop
RET1116:
! lfsr step begin
srlx %l0, 1, %l3
xnor %l3, %l0, %l3
sllx %l3, 63, %l3
or %l3, %l0, %l0
srlx %l0, 1, %l0
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_1_230:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_230
nop
P1117: !_LD [28] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_231:
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1118: !_MEMBAR (Int)
membar #StoreLoad
P1119: !_LD [4] (Int) (Loop exit)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 4
sethi %hi(0xc0000), %l6
sub %i1, %l6, %i1
lduw [%i1 + 0], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
sethi %hi(0xc0000), %l3
add %i1, %l3, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_1_231:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_231
nop
P1120: !_LD [7] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_232:
ld [%i1 + 32], %f0
! 1 addresses covered
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
loop_exit_1_232:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_232
nop
P1121: !_CASX [9] (maybe <- 0x800024) (Int) (Loop entry) (Branch target of P1039)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_233:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
sub %i0, %i2, %i2
ldx [%i2], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
mov %o0, %o5
sllx %l4, 32, %o1
add %l4, 1, %l4
or %l4, %o1, %o1
casx [%i2], %o5, %o1
! move %o1(upper) -> %o1(upper)
! move %o1(lower) -> %o1(lower)
add %l4, 1, %l4
ba P1122
nop
TARGET1039:
ba RET1039
nop
P1122: !_DWLD [30] (Int)
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
ldx [%i3 + 8], %o2
! move %o2(lower) -> %o2(upper)
sllx %o2, 32, %o2
P1123: !_LD [28] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 0], %o5
! move %o5(lower) -> %o2(lower)
or %o5, %o2, %o2
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
mov %o2, %l5
loop_exit_1_233:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_233
nop
P1124: !_DWLD [10] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_234:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1125: !_LD [15] (Int) (Loop exit)
sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 32], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_1_234:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_234
nop
P1126: !_DWLD [12] (Int) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_235:
sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
ldx [%i3 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_1_235:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_235
nop
P1127: !_DWLD [25] (Int) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_236:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_1_236:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_236
nop
P1128: !_LD [16] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_237:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
sub %i0, %i3, %i3
ld [%i3 + 0], %f0
! 1 addresses covered
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
loop_exit_1_237:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_237
nop
P1129: !_BLD [10] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_238:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P1130: !_BLD [16] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f32
membar #Sync
! 4 addresses covered
fmovd %f32, %f4
fmovd %f34, %f18
fmovs %f19, %f6
fmovd %f40, %f18
fmovs %f18, %f7
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovd %f4, %f30
fmovd %f6, %f30
!--
loop_exit_1_238:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_238
nop
P1131: !_BLD [16] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_239:
wr %g0, 0xf0, %asi
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P1132: !_LD [25] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1133: !_LD [22] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_1_239:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_239
nop
P1134: !_LD [28] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_240:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1135: !_LD [3] (Int) (Loop exit)
lduw [%i0 + 32], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_1_240:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_240
nop
P1136: !_LD [9] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_241:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1137: !_LD [0] (Int) (Loop exit)
lduw [%i0 + 0], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_1_241:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_241
nop
P1138: !_LD [0] (Int) (Loop entry) (LE)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_242:
wr %g0, 0x88, %asi
lduwa [%i0 + 0] %asi, %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1139: !_LD [2] (Int) (Loop exit)
lduw [%i0 + 12], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_1_242:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_242
nop
P1140: !_LD [21] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_243:
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1141: !_LD [2] (Int) (Loop exit) (Branch target of P778)
lduw [%i0 + 12], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_1_243:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_243
nop
ba P1142
nop
TARGET778:
ba RET778
nop
P1142: !_ST [25] (maybe <- 0x800026) (Int) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_244:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
sub %i0, %i2, %i2
stw %l4, [%i2 + 4 ]
add %l4, 1, %l4
loop_exit_1_244:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_244
nop
P1143: !_LD [11] (Int) (Loop entry) (LE)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_245:
wr %g0, 0x88, %asi
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduwa [%i3 + 32] %asi, %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1144: !_LD [0] (Int) (Loop exit)
lduw [%i0 + 0], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_1_245:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_245
nop
P1145: !_DWLD [3] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_246:
ldx [%i0 + 32], %o0
! move %o0(upper) -> %o0(upper)
P1146: !_DWLD [23] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 32], %l7
! move %l7(upper) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
srlx %l7, 32, %l6
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_1_246:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_246
nop
P1147: !_REPLACEMENT [12] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_247:
sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS2_O), %i3
sub %i0, %i3, %i3
sethi %hi(0x10000), %l6
ld [%i3+0], %o5
st %o5, [%i3+0]
add %i3, %l6, %l7
ld [%l7+0], %o5
st %o5, [%l7+0]
add %l7, %l6, %l7
ld [%l7+0], %o5
st %o5, [%l7+0]
add %l7, %l6, %l7
ld [%l7+0], %o5
st %o5, [%l7+0]
P1148: !_DWLD [0] (Int) (Loop exit)
ldx [%i0 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_1_247:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_247
nop
P1149: !_PREFETCH [12] (Int) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_248:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i2
sub %i0, %i2, %i2
prefetch [%i2 + 0], 1
loop_exit_1_248:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_248
nop
P1150: !_BLD [4] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_249:
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_1_249:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_249
nop
P1151: !_DWLD [16] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_250:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
P1152: !_DWLD [9] (Int) (Loop exit)
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
ldx [%i2 + 0], %o1
! move %o1(upper) -> %o1(upper)
! move %o1(lower) -> %o1(lower)
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_1_250:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_250
nop
P1153: !_DWLD [24] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_251:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
P1154: !_DWLD [11] (Int)
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
ldx [%i2 + 32], %o1
! move %o1(upper) -> %o1(upper)
P1155: !_LD [22] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %o5
! move %o5(lower) -> %o1(lower)
srlx %o1, 32, %o1
sllx %o1, 32, %o1
or %o5, %o1, %o1
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_1_251:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_251
nop
P1156: !_DWLD [27] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_252:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 32], %o0
! move %o0(upper) -> %o0(upper)
P1157: !_LD [7] (Int) (Loop exit)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 7
sethi %hi(0xc0000), %o5
sub %i1, %o5, %i1
lduw [%i1 + 32], %l6
! move %l6(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
sethi %hi(0xc0000), %l7
add %i1, %l7, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_1_252:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_252
nop
P1158: !_MEMBAR (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_253:
membar #StoreLoad
P1159: !_DWLD [8] (Int) (Loop exit) (LE)
wr %g0, 0x88, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i3
sub %i0, %i3, %i3
ldxa [%i3 + 0] %asi, %l6
! move %l6(lower) -> %o0(upper)
sllx %l6, 32, %o0
! move %l6(upper) -> %o0(lower)
srlx %l6, 32, %l3
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_1_253:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_253
nop
P1160: !_PREFETCH [9] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_254:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i2
sub %i0, %i2, %i2
prefetch [%i2 + 4], 1
P1161: !_BLD [4] (FP) (Loop exit)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 4
sethi %hi(0xc0000), %o5
sub %i1, %o5, %i1
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
sethi %hi(0xc0000), %l3
add %i1, %l3, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_1_254:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_254
nop
P1162: !_DWLD [29] (Int) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_255:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_1_255:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_255
nop
P1163: !_BLD [23] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_256:
wr %g0, 0xf0, %asi
sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P1164: !_CASX [12] (maybe <- 0x800027) (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i3
sub %i0, %i3, %i3
ldx [%i3], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
mov %o0, %l6
sllx %l4, 32, %o1
add %l4, 1, %l4
or %l4, %o1, %o1
casx [%i3], %l6, %o1
! move %o1(upper) -> %o1(upper)
! move %o1(lower) -> %o1(lower)
add %l4, 1, %l4
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_1_256:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_256
nop
P1165: !_LD [1] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_257:
lduw [%i0 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1166: !_LD [22] (Int) (Loop exit)
sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 12], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_1_257:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_257
nop
P1167: !_BLD [11] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_258:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_1_258:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_258
nop
P1168: !_LD [13] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_259:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1169: !_LD [29] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 4], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_1_259:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_259
nop
P1170: !_BST [25] (maybe <- 0x40000032) (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_260:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i2
sub %i0, %i2, %i2
! preparing store val #0, next val will be in f32
fmovs %f16, %f20
fadds %f16, %f17, %f16
! preparing store val #1, next val will be in f33
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #2, next val will be in f35
fmovd %f20, %f32
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #3, next val will be in f40
fmovd %f20, %f34
fmovs %f16, %f20
fadds %f16, %f17, %f16
fmovd %f20, %f40
membar #Sync
stda %f32, [%i2 + 0 ] %asi
membar #Sync
P1171: !_BLD [17] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_1_260:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_260
nop
P1172: !_BLD [12] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_261:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P1173: !_BLD [2] (FP) (Loop exit)
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i0 + 0] %asi, %f32
membar #Sync
! 4 addresses covered
fmovd %f32, %f4
fmovd %f34, %f18
fmovs %f19, %f6
fmovd %f40, %f18
fmovs %f18, %f7
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovd %f4, %f30
fmovd %f6, %f30
!--
loop_exit_1_261:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_261
nop
P1174: !_BLD [13] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_262:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_1_262:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_262
nop
P1175: !_CAS [23] (maybe <- 0x800029) (Int) (Loop entry) (Loop exit) (Branch target of P1034)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_263:
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i2
sub %i0, %i2, %i2
add %i2, 32, %l7
lduw [%l7], %o0
mov %o0, %l6
! move %l6(lower) -> %o0(upper)
sllx %l6, 32, %o0
mov %l4, %l3
cas [%l7], %l6, %l3
! move %l3(lower) -> %o0(lower)
srl %l3, 0, %l6
or %l6, %o0, %o0
add %l4, 1, %l4
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_1_263:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_263
nop
ba P1176
nop
TARGET1034:
ba RET1034
nop
P1176: !_DWLD [7] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_264:
ldx [%i1 + 32], %o0
! move %o0(upper) -> %o0(upper)
P1177: !_DWLD [21] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 0], %l7
! move %l7(upper) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
srlx %l7, 32, %l6
or %l6, %o0, %o0
! move %l7(lower) -> %o1(upper)
sllx %l7, 32, %o1
P1178: !_LD [9] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %l3
! move %l3(lower) -> %o1(lower)
or %l3, %o1, %o1
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_1_264:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_264
nop
P1179: !_PREFETCH [30] (Int) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_265:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i3
sub %i0, %i3, %i3
prefetch [%i3 + 12], 1
loop_exit_1_265:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_265
nop
P1180: !_NOP (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_266:
nop
P1181: !_BLD [25] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_1_266:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_266
nop
P1182: !_BLD [3] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_267:
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i0 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P1183: !_ST [4] (maybe <- 0x40000036) (FP) (Loop exit) (Branch target of P960)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 4
sethi %hi(0xc0000), %l7
sub %i1, %l7, %i1
! preparing store val #0, next val will be in f20
fmovs %f16, %f20
fadds %f16, %f17, %f16
st %f20, [%i1 + 0 ]
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
sethi %hi(0xc0000), %l7
add %i1, %l7, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_1_267:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_267
nop
ba P1184
nop
TARGET960:
ba RET960
nop
P1184: !_DWLD [4] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_268:
ldx [%i1 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
P1185: !_BLD [8] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_1_268:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_268
nop
P1186: !_SWAP [29] (maybe <- 0x80002a) (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_269:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i2
sub %i0, %i2, %i2
mov %l4, %o0
swap [%i2 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
add %l4, 1, %l4
P1187: !_BLD [20] (FP)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P1188: !_LD [30] (Int) (Loop exit)
lduw [%i2 + 12], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_1_269:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_269
nop
P1189: !_SWAP [28] (maybe <- 0x80002b) (Int) (Loop entry) (CBR)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_270:
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
mov %l4, %o0
swap [%i2 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
add %l4, 1, %l4
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET1189
nop
RET1189:
! lfsr step begin
srlx %l0, 1, %l7
xnor %l7, %l0, %l7
sllx %l7, 63, %l7
or %l7, %l0, %l0
srlx %l0, 1, %l0
P1190: !_BLD [31] (FP)
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P1191: !_LD [19] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_1_270:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_270
nop
P1192: !_DWLD [14] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_271:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1193: !_LD [0] (Int) (Loop exit)
lduw [%i0 + 0], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_1_271:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_271
nop
P1194: !_DWLD [26] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_272:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i3
sub %i0, %i3, %i3
ldd [%i3 + 8], %f0
! 1 addresses covered
fmovs %f1, %f0
P1195: !_LD [31] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1196: !_LD [8] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
loop_exit_1_272:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_272
nop
P1197: !_BLD [9] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_273:
wr %g0, 0xf0, %asi
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P1198: !_DWLD [5] (Int) (Loop exit)
ldx [%i1 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_1_273:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_273
nop
P1199: !_LD [29] (Int) (Loop entry) (Branch target of P867)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_274:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
ba P1200
nop
TARGET867:
ba RET867
nop
P1200: !_FLUSHI [20] (Int)
flush %g0
P1201: !_LD [31] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 32], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_1_274:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_274
nop
P1202: !_DWLD [6] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_275:
ldx [%i1 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1203: !_LD [10] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_1_275:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_275
nop
P1204: !_LD [11] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_276:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1205: !_BLD [29] (FP)
wr %g0, 0xf0, %asi
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P1206: !_LD [21] (Int) (Loop exit) (LE)
wr %g0, 0x88, %asi
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduwa [%i2 + 4] %asi, %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_1_276:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_276
nop
P1207: !_LD [31] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_277:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1208: !_LD [30] (Int) (Loop exit)
lduw [%i3 + 12], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_1_277:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_277
nop
P1209: !_LD [1] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_278:
lduw [%i0 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1210: !_LD [11] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 32], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_1_278:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_278
nop
P1211: !_LD [27] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_279:
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1212: !_LD [19] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 32], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_1_279:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_279
nop
P1213: !_LD [27] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_280:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1214: !_BLD [6] (FP)
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P1215: !_LD [3] (Int) (Loop exit)
lduw [%i0 + 32], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_1_280:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_280
nop
P1216: !_NOP (Int) (Loop entry) (Loop exit) (Branch target of P1267)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_281:
nop
loop_exit_1_281:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_281
nop
ba P1217
nop
TARGET1267:
ba RET1267
nop
P1217: !_DWLD [22] (Int) (Loop entry) (Branch target of P1309)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_282:
sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
ldx [%i2 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
ba P1218
nop
TARGET1309:
ba RET1309
nop
P1218: !_LD [11] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_1_282:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_282
nop
P1219: !_LD [26] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_283:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1220: !_LD [1] (Int) (Loop exit)
lduw [%i0 + 4], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_1_283:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_283
nop
P1221: !_CAS [17] (maybe <- 0x80002c) (Int) (Loop entry) (Loop exit) (Branch target of P824)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_284:
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
add %i3, 4, %l7
lduw [%l7], %o0
mov %o0, %l6
! move %l6(lower) -> %o0(upper)
sllx %l6, 32, %o0
mov %l4, %l3
cas [%l7], %l6, %l3
! move %l3(lower) -> %o0(lower)
srl %l3, 0, %l6
or %l6, %o0, %o0
add %l4, 1, %l4
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_1_284:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_284
nop
ba P1222
nop
TARGET824:
ba RET824
nop
P1222: !_LD [23] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_285:
sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1223: !_BLD [9] (FP)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P1224: !_LD [25] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_1_285:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_285
nop
P1225: !_DWLD [25] (Int) (Loop entry) (Loop exit) (Branch target of P1005)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_286:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_1_286:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_286
nop
ba P1226
nop
TARGET1005:
ba RET1005
nop
P1226: !_BLD [30] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_287:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P1227: !_LD [14] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1228: !_LD [28] (Int) (Loop exit)
lduw [%i2 + 0], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_1_287:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_287
nop
P1229: !_LD [28] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_288:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1230: !_DWLD [25] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 0], %l7
! move %l7(upper) -> %o0(lower)
srlx %l7, 32, %l6
or %l6, %o0, %o0
! move %l7(lower) -> %o1(upper)
sllx %l7, 32, %o1
P1231: !_LD [26] (Int) (Loop exit)
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 12], %l6
! move %l6(lower) -> %o1(lower)
or %l6, %o1, %o1
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_1_288:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_288
nop
P1232: !_DWLD [24] (Int) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_289:
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
ldx [%i3 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_1_289:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_289
nop
P1233: !_LD [8] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_290:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i2
sub %i0, %i2, %i2
ld [%i2 + 0], %f0
! 1 addresses covered
P1234: !_BLD [9] (FP) (Loop exit)
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i2 + 0] %asi, %f32
membar #Sync
! 4 addresses covered
fmovd %f32, %f18
fmovs %f18, %f1
fmovs %f19, %f2
fmovd %f34, %f18
fmovs %f19, %f3
fmovd %f40, %f4
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovs %f4, %f30
!--
loop_exit_1_290:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_290
nop
P1235: !_LD [31] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_291:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1236: !_DWLD [7] (FP)
ldd [%i1 + 32], %f0
! 1 addresses covered
P1237: !_LD [3] (Int) (Loop exit)
lduw [%i0 + 32], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
loop_exit_1_291:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_291
nop
P1238: !_BLD [19] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_292:
wr %g0, 0xf0, %asi
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P1239: !_LD [1] (Int)
lduw [%i0 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1240: !_LD [3] (Int) (Loop exit)
lduw [%i0 + 32], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_1_292:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_292
nop
P1241: !_LD [17] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_293:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1242: !_LD [28] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 0], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_1_293:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_293
nop
P1243: !_DWLD [25] (Int) (Loop entry) (CBR)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_294:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET1243
nop
RET1243:
! lfsr step begin
srlx %l0, 1, %l7
xnor %l7, %l0, %l7
sllx %l7, 63, %l7
or %l7, %l0, %l0
srlx %l0, 1, %l0
P1244: !_DWLD [10] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 8], %o1
! move %o1(lower) -> %o1(upper)
sllx %o1, 32, %o1
P1245: !_LD [4] (Int) (Loop exit)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 4
sethi %hi(0xc0000), %l6
sub %i1, %l6, %i1
lduw [%i1 + 0], %o5
! move %o5(lower) -> %o1(lower)
or %o5, %o1, %o1
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
sethi %hi(0xc0000), %l3
add %i1, %l3, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_1_294:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_294
nop
P1246: !_LD [25] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_295:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1247: !_LD [21] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_1_295:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_295
nop
P1248: !_DWLD [14] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_296:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1249: !_BLD [2] (FP)
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i0 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P1250: !_LD [25] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_1_296:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_296
nop
P1251: !_BLD [14] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_297:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_1_297:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_297
nop
P1252: !_DWLD [8] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_298:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
P1253: !_BLD [5] (FP) (Loop exit)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 5
sethi %hi(0xc0000), %l6
sub %i1, %l6, %i1
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
sethi %hi(0xc0000), %l7
add %i1, %l7, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_1_298:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_298
nop
P1254: !_CAS [20] (maybe <- 0x80002d) (Int) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_299:
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3], %o0
mov %o0, %o5
! move %o5(lower) -> %o0(upper)
sllx %o5, 32, %o0
mov %l4, %l7
cas [%i3], %o5, %l7
! move %l7(lower) -> %o0(lower)
srl %l7, 0, %o5
or %o5, %o0, %o0
add %l4, 1, %l4
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_1_299:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_299
nop
P1255: !_DWLD [6] (Int) (Loop entry) (LE) (Branch target of P879)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_300:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 6
sethi %hi(0xc0000), %l3
sub %i1, %l3, %i1
wr %g0, 0x88, %asi
ldxa [%i1 + 8] %asi, %l7
! move %l7(upper) -> %o0(upper)
or %l7, %g0, %o0
ba P1256
nop
TARGET879:
ba RET879
nop
P1256: !_LD [8] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 0], %l3
! move %l3(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
sethi %hi(0xc0000), %l6
add %i1, %l6, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_1_300:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_300
nop
P1257: !_DWLD [6] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_301:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 6
sethi %hi(0xc0000), %l7
sub %i1, %l7, %i1
ldx [%i1 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1258: !_BLD [0] (FP)
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i0 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P1259: !_LD [19] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
sethi %hi(0xc0000), %l3
add %i1, %l3, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_1_301:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_301
nop
P1260: !_NOP (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_302:
nop
P1261: !_LD [29] (Int)
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1262: !_LD [20] (Int) (Loop exit) (Branch target of P798)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_1_302:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_302
nop
ba P1263
nop
TARGET798:
ba RET798
nop
P1263: !_PREFETCH [31] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_303:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
sub %i0, %i2, %i2
prefetch [%i2 + 32], 1
P1264: !_LD [2] (Int)
lduw [%i0 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1265: !_LD [0] (Int) (Loop exit)
lduw [%i0 + 0], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_1_303:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_303
nop
P1266: !_LD [11] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_304:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1267: !_LD [3] (Int) (Loop exit) (CBR)
lduw [%i0 + 32], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET1267
nop
RET1267:
! lfsr step begin
srlx %l0, 1, %o5
xnor %o5, %l0, %o5
sllx %o5, 63, %o5
or %o5, %l0, %l0
srlx %l0, 1, %l0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_1_304:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_304
nop
P1268: !_LD [14] (Int) (Loop entry) (Branch target of P810)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_305:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
ba P1269
nop
TARGET810:
ba RET810
nop
P1269: !_LD [22] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_1_305:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_305
nop
P1270: !_LD [7] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_306:
lduw [%i1 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1271: !_LD [30] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_1_306:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_306
nop
P1272: !_LD [27] (Int) (Loop entry) (LE)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_307:
wr %g0, 0x88, %asi
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduwa [%i3 + 32] %asi, %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1273: !_LD [4] (Int) (Loop exit)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 4
sethi %hi(0xc0000), %o5
sub %i1, %o5, %i1
lduw [%i1 + 0], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
sethi %hi(0xc0000), %l7
add %i1, %l7, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_1_307:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_307
nop
P1274: !_LD [6] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_308:
ld [%i1 + 12], %f0
! 1 addresses covered
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
loop_exit_1_308:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_308
nop
P1275: !_DWLD [27] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_309:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 32], %o0
! move %o0(upper) -> %o0(upper)
P1276: !_DWLD [14] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 8], %l3
! move %l3(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
srl %l3, 0, %o5
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_1_309:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_309
nop
P1277: !_LD [18] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_310:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1278: !_LD [13] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 4], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_1_310:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_310
nop
P1279: !_LD [11] (Int) (Loop entry) (Branch target of P675)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_311:
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
ba P1280
nop
TARGET675:
ba RET675
nop
P1280: !_LD [19] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_1_311:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_311
nop
P1281: !_LD [1] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_312:
lduw [%i0 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1282: !_BLD [15] (FP)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P1283: !_LD [16] (Int) (Loop exit) (CBR)
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 0], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET1283
nop
RET1283:
! lfsr step begin
srlx %l0, 1, %l3
xnor %l3, %l0, %l3
sllx %l3, 63, %l3
or %l3, %l0, %l0
srlx %l0, 1, %l0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_1_312:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_312
nop
P1284: !_MEMBAR (Int) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_313:
membar #StoreLoad
loop_exit_1_313:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_313
nop
P1285: !_CAS [18] (maybe <- 0x80002e) (Int) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_314:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
sub %i0, %i2, %i2
add %i2, 12, %l6
lduw [%l6], %o0
mov %o0, %l3
! move %l3(lower) -> %o0(upper)
sllx %l3, 32, %o0
mov %l4, %o5
cas [%l6], %l3, %o5
! move %o5(lower) -> %o0(lower)
srl %o5, 0, %l3
or %l3, %o0, %o0
add %l4, 1, %l4
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_1_314:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_314
nop
P1286: !_LD [16] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_315:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1287: !_LD [16] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 0], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_1_315:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_315
nop
P1288: !_ST [14] (maybe <- 0x80002f) (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_316:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i3
sub %i0, %i3, %i3
stw %l4, [%i3 + 12 ]
add %l4, 1, %l4
P1289: !_LD [7] (Int)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 7
sethi %hi(0xc0000), %l7
sub %i1, %l7, %i1
lduw [%i1 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1290: !_LD [22] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
sethi %hi(0xc0000), %o5
add %i1, %o5, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_1_316:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_316
nop
P1291: !_LD [11] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_317:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1292: !_LD [15] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 32], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_1_317:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_317
nop
P1293: !_DWLD [17] (Int) (Loop entry) (LE)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_318:
wr %g0, 0x88, %asi
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
sub %i0, %i3, %i3
ldxa [%i3 + 0] %asi, %l3
! move %l3(lower) -> %o0(upper)
sllx %l3, 32, %o0
! move %l3(upper) -> %o0(lower)
srlx %l3, 32, %o5
or %o5, %o0, %o0
P1294: !_BLD [11] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_1_318:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_318
nop
P1295: !_BLD [13] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_319:
wr %g0, 0xf0, %asi
sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P1296: !_DWLD [2] (Int)
ldx [%i0 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1297: !_LD [13] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_1_319:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_319
nop
P1298: !_BLD [12] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_320:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_1_320:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_320
nop
P1299: !_LD [3] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_321:
ld [%i0 + 32], %f0
! 1 addresses covered
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
loop_exit_1_321:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_321
nop
P1300: !_LD [30] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_322:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1301: !_LD [30] (Int) (Loop exit) (CBR)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET1301
nop
RET1301:
! lfsr step begin
srlx %l0, 1, %l6
xnor %l6, %l0, %l6
sllx %l6, 63, %l6
or %l6, %l0, %l0
srlx %l0, 1, %l0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_1_322:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_322
nop
P1302: !_DWLD [22] (Int) (Loop entry) (LE)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_1_323:
wr %g0, 0x88, %asi
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
sub %i0, %i2, %i2
ldxa [%i2 + 8] %asi, %l3
! move %l3(upper) -> %o0(upper)
or %l3, %g0, %o0
P1303: !_DWLD [14] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 8], %o5
! move %o5(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
srl %o5, 0, %l7
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_1_323:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_323
nop
P1304: !_DWLD [0] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_324:
ldx [%i0 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
P1305: !_BLD [1] (FP) (Loop exit)
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i0 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_1_324:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_324
nop
P1306: !_LD [12] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_325:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1307: !_LD [21] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 4], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_1_325:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_325
nop
P1308: !_DWLD [28] (Int) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_1_326:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_1_326:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_1_326
nop
P1309: !_MEMBAR (Int) (CBR)
membar #StoreLoad
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET1309
nop
RET1309:
! lfsr step begin
srlx %l0, 1, %o5
xnor %o5, %l0, %o5
sllx %o5, 63, %o5
or %o5, %l0, %l0
srlx %l0, 1, %l0
END_NODES1: ! Test instruction sequence for CPU 1 ends
sethi %hi(0xdead0e0f), %l3
or %l3, %lo(0xdead0e0f), %l3
! move %l3(lower) -> %o0(upper)
sllx %l3, 32, %o0
stw %l3, [%i5]
ld [%i5], %f0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
restore
retl
nop
!-----------------
! register usage:
! %i0 %i1 : base registers for first 2 regions
! %i2 %i3 : cache registers for 8 regions
! %i4 fixed pointer to per-cpu results area
! %l1 moving pointer to per-cpu FP results area
! %o7 moving pointer to per-cpu integer results area
! %i5 pointer to per-cpu private area
! %l0 holds lfsr, used as source of random bits
! %l2 loop count register
! %f16 running counter for unique fp store values
! %f17 holds increment value for fp counter
! %l4 running counter for unique integer store values (increment value is always 1)
! %l5 move-to register for load values (simulation only)
! %f30 move-to register for FP values (simulation only)
! %l3 %l6 %l7 %o5 : 4 temporary registers
! %o0 %o1 %o2 %o3 %o4 : 5 integer results buffer registers
! %f0-f15 FP results buffer registers
! %f32-f47 FP block load/store registers
func2:
! 1000 (dynamic) instruction sequence begins
save %sp, -192, %sp
! Force %i0-%i3 to be 64-byte aligned
add %i0, 63, %i0
andn %i0, 63, %i0
add %i1, 63, %i1
andn %i1, 63, %i1
add %i2, 63, %i2
andn %i2, 63, %i2
add %i3, 63, %i3
andn %i3, 63, %i3
add %i4, 63, %i4
andn %i4, 63, %i4
add %i5, 63, %i5
andn %i5, 63, %i5
! Initialize pointer to FP load results area
mov %i4, %l1
! Initialize pointer to integer load results area
sethi %hi(0x80000), %o7
or %o7, %lo(0x80000), %o7
add %o7, %l1, %o7
! Initialize %f0-%f62 to 0xdeadbee0deadbee1
sethi %hi(0xdeadbee0), %o5
or %o5, %lo(0xdeadbee0), %o5
stw %o5, [%i5]
sethi %hi(0xdeadbee1), %o5
or %o5, %lo(0xdeadbee1), %o5
stw %o5, [%i5+4]
ldd [%i5], %f0
fmovd %f0, %f2
fmovd %f0, %f4
fmovd %f0, %f6
fmovd %f0, %f8
fmovd %f0, %f10
fmovd %f0, %f12
fmovd %f0, %f14
fmovd %f0, %f16
fmovd %f0, %f18
fmovd %f0, %f20
fmovd %f0, %f22
fmovd %f0, %f24
fmovd %f0, %f26
fmovd %f0, %f28
fmovd %f0, %f30
fmovd %f0, %f32
fmovd %f0, %f34
fmovd %f0, %f36
fmovd %f0, %f38
fmovd %f0, %f40
fmovd %f0, %f42
fmovd %f0, %f44
fmovd %f0, %f46
fmovd %f0, %f48
fmovd %f0, %f50
fmovd %f0, %f52
fmovd %f0, %f54
fmovd %f0, %f56
fmovd %f0, %f58
fmovd %f0, %f60
fmovd %f0, %f62
! Signature for extract_loads script to start extracting load values for this stream
sethi %hi(0x02deade1), %o5
or %o5, %lo(0x02deade1), %o5
stw %o5, [%i5]
ld [%i5], %f16
! Initialize running integer counter in register %l4
sethi %hi(0x1000001), %l4
or %l4, %lo(0x1000001), %l4
! Initialize running FP counter in register %f16
sethi %hi(0x40800001), %o5
or %o5, %lo(0x40800001), %o5
stw %o5, [%i5]
ld [%i5], %f16
! Initialize FP counter increment value in register %f17 (constant)
sethi %hi(0x35000000), %o5
or %o5, %lo(0x35000000), %o5
stw %o5, [%i5]
ld [%i5], %f17
! Initialize LFSR to 0x7bfa^4
sethi %hi(0x7bfa), %l0
or %l0, %lo(0x7bfa), %l0
mulx %l0, %l0, %l0
mulx %l0, %l0, %l0
BEGIN_NODES2: ! Test instruction sequence for CPU 2 begins
P1310: !_DWLD [16] (Int) (Loop entry) (LE)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_0:
wr %g0, 0x88, %asi
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
sub %i0, %i3, %i3
ldxa [%i3 + 0] %asi, %l7
! move %l7(lower) -> %o0(upper)
sllx %l7, 32, %o0
! move %l7(upper) -> %o0(lower)
srlx %l7, 32, %l6
or %l6, %o0, %o0
P1311: !_DWLD [29] (Int) (Loop exit)
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
ldx [%i2 + 0], %o1
! move %o1(upper) -> %o1(upper)
! move %o1(lower) -> %o1(lower)
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_2_0:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_0
nop
P1312: !_BLD [19] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_1:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_2_1:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_1
nop
P1313: !_LD [7] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_2:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 7
sethi %hi(0xc0000), %l3
sub %i1, %l3, %i1
lduw [%i1 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1314: !_LD [14] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
sethi %hi(0xc0000), %l6
add %i1, %l6, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_2_2:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_2
nop
P1315: !_DWLD [1] (Int) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_3:
ldx [%i0 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_2_3:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_3
nop
P1316: !_BLD [9] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_4:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_2_4:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_4
nop
P1317: !_DWLD [30] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_5:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1318: !_LD [14] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_2_5:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_5
nop
P1319: !_DWLD [4] (Int) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_6:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 4
sethi %hi(0xc0000), %l6
sub %i1, %l6, %i1
ldx [%i1 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
sethi %hi(0xc0000), %l3
add %i1, %l3, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_2_6:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_6
nop
P1320: !_DWLD [13] (Int) (Loop entry) (Loop exit) (LE)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_7:
wr %g0, 0x88, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i2
sub %i0, %i2, %i2
ldxa [%i2 + 0] %asi, %l7
! move %l7(lower) -> %o0(upper)
sllx %l7, 32, %o0
! move %l7(upper) -> %o0(lower)
srlx %l7, 32, %l6
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_2_7:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_7
nop
P1321: !_LD [20] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_8:
sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1322: !_DWLD [9] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 0], %l3
! move %l3(upper) -> %o0(lower)
srlx %l3, 32, %o5
or %o5, %o0, %o0
! move %l3(lower) -> %o1(upper)
sllx %l3, 32, %o1
P1323: !_LD [7] (Int) (Loop exit)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 7
sethi %hi(0xc0000), %l6
sub %i1, %l6, %i1
lduw [%i1 + 32], %o5
! move %o5(lower) -> %o1(lower)
or %o5, %o1, %o1
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
sethi %hi(0xc0000), %l3
add %i1, %l3, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_2_8:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_8
nop
P1324: !_DWLD [15] (Int) (Loop entry) (LE) (CBR)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_9:
wr %g0, 0x88, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i3
sub %i0, %i3, %i3
ldxa [%i3 + 32] %asi, %l7
! move %l7(lower) -> %o0(upper)
sllx %l7, 32, %o0
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET1324
nop
RET1324:
! lfsr step begin
srlx %l0, 1, %o5
xnor %o5, %l0, %o5
sllx %o5, 63, %o5
or %o5, %l0, %l0
srlx %l0, 1, %l0
P1325: !_LD [16] (Int) (Loop exit)
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 0], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_2_9:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_9
nop
P1326: !_BLD [14] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_10:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_2_10:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_10
nop
P1327: !_LD [31] (Int) (Loop entry) (Branch target of P1579)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_11:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
ba P1328
nop
TARGET1579:
ba RET1579
nop
P1328: !_LD [14] (Int) (Loop exit) (LE)
wr %g0, 0x88, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduwa [%i3 + 12] %asi, %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_2_11:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_11
nop
P1329: !_BLD [1] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_12:
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i0 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P1330: !_LD [21] (Int) (Branch target of P1740)
sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
ba P1331
nop
TARGET1740:
ba RET1740
nop
P1331: !_LD [25] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 4], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_2_12:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_12
nop
P1332: !_CAS [24] (maybe <- 0x1000001) (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_13:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2], %o0
mov %o0, %l7
! move %l7(lower) -> %o0(upper)
sllx %l7, 32, %o0
mov %l4, %l6
cas [%i2], %l7, %l6
! move %l6(lower) -> %o0(lower)
srl %l6, 0, %l7
or %l7, %o0, %o0
add %l4, 1, %l4
P1333: !_BLD [11] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_2_13:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_13
nop
P1334: !_LD [20] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_14:
sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1335: !_LD [28] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_2_14:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_14
nop
P1336: !_LD [4] (Int) (Loop entry) (Branch target of P1957)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_15:
lduw [%i1 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
ba P1337
nop
TARGET1957:
ba RET1957
nop
P1337: !_LD [30] (Int) (Loop exit)
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 12], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_2_15:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_15
nop
P1338: !_REPLACEMENT [8] (Int) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_16:
sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
sethi %hi(0x10000), %l3
ld [%i3+0], %l7
st %l7, [%i3+0]
add %i3, %l3, %l6
ld [%l6+0], %l7
st %l7, [%l6+0]
add %l6, %l3, %l6
ld [%l6+0], %l7
st %l7, [%l6+0]
add %l6, %l3, %l6
ld [%l6+0], %l7
st %l7, [%l6+0]
loop_exit_2_16:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_16
nop
P1339: !_BSTC [31] (maybe <- 0x40800001) (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_17:
wr %g0, 0xe0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
sub %i0, %i2, %i2
! preparing store val #0, next val will be in f32
fmovs %f16, %f20
fadds %f16, %f17, %f16
! preparing store val #1, next val will be in f33
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #2, next val will be in f35
fmovd %f20, %f32
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #3, next val will be in f40
fmovd %f20, %f34
fmovs %f16, %f20
fadds %f16, %f17, %f16
fmovd %f20, %f40
membar #Sync
stda %f32, [%i2 + 0 ] %asi
membar #Sync
loop_exit_2_17:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_17
nop
P1340: !_ST [8] (maybe <- 0x1000002) (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_18:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
sub %i0, %i3, %i3
stw %l4, [%i3 + 0 ]
add %l4, 1, %l4
P1341: !_DWLD [19] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 32], %o0
! move %o0(upper) -> %o0(upper)
P1342: !_LD [16] (Int) (Loop exit)
lduw [%i2 + 0], %l3
! move %l3(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_2_18:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_18
nop
P1343: !_DWLD [15] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_19:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 32], %o0
! move %o0(upper) -> %o0(upper)
P1344: !_LD [28] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 0], %l7
! move %l7(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_2_19:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_19
nop
P1345: !_DWLD [18] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_20:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i3
sub %i0, %i3, %i3
ldd [%i3 + 8], %f0
! 1 addresses covered
fmovs %f1, %f0
P1346: !_LD [14] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1347: !_LD [20] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
loop_exit_2_20:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_20
nop
P1348: !_BLD [26] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_21:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_2_21:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_21
nop
P1349: !_DWLD [10] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_22:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1350: !_LD [21] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_2_22:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_22
nop
P1351: !_SWAP [24] (maybe <- 0x1000003) (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_23:
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
mov %l4, %o0
swap [%i3 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
add %l4, 1, %l4
P1352: !_LD [24] (Int) (Loop exit)
lduw [%i3 + 0], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_2_23:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_23
nop
P1353: !_SWAP [16] (maybe <- 0x1000004) (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_24:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i2
sub %i0, %i2, %i2
mov %l4, %o0
swap [%i2 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
add %l4, 1, %l4
P1354: !_LD [28] (Int) (Loop exit) (Branch target of P1722)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_2_24:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_24
nop
ba P1355
nop
TARGET1722:
ba RET1722
nop
P1355: !_BLD [10] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_25:
wr %g0, 0xf0, %asi
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P1356: !_BLD [12] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f32
membar #Sync
! 4 addresses covered
fmovd %f32, %f4
fmovd %f34, %f18
fmovs %f19, %f6
fmovd %f40, %f18
fmovs %f18, %f7
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovd %f4, %f30
fmovd %f6, %f30
!--
loop_exit_2_25:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_25
nop
P1357: !_BLD [19] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_26:
wr %g0, 0xf0, %asi
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P1358: !_BLD [18] (FP) (Loop exit)
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i2 + 0] %asi, %f32
membar #Sync
! 4 addresses covered
fmovd %f32, %f4
fmovd %f34, %f18
fmovs %f19, %f6
fmovd %f40, %f18
fmovs %f18, %f7
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovd %f4, %f30
fmovd %f6, %f30
!--
loop_exit_2_26:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_26
nop
P1359: !_BLD [28] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_27:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P1360: !_BLD [0] (FP) (Loop exit)
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i0 + 0] %asi, %f32
membar #Sync
! 4 addresses covered
fmovd %f32, %f4
fmovd %f34, %f18
fmovs %f19, %f6
fmovd %f40, %f18
fmovs %f18, %f7
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovd %f4, %f30
fmovd %f6, %f30
!--
loop_exit_2_27:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_27
nop
P1361: !_LD [28] (Int) (Loop entry) (LE)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_28:
wr %g0, 0x88, %asi
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduwa [%i2 + 0] %asi, %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1362: !_LD [20] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_2_28:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_28
nop
P1363: !_DWLD [28] (Int) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_29:
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
ldx [%i2 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_2_29:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_29
nop
P1364: !_LD [4] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_30:
lduw [%i1 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1365: !_LD [5] (Int) (Loop exit)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 5
sethi %hi(0xc0000), %l7
sub %i1, %l7, %i1
lduw [%i1 + 4], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
sethi %hi(0xc0000), %l6
add %i1, %l6, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_2_30:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_30
nop
P1366: !_DWST [19] (maybe <- 0x1000005) (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_31:
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
mov %l4, %l7
sllx %l7, 32, %l7
stx %l7, [%i3 + 32 ]
add %l4, 1, %l4
P1367: !_LD [3] (Int)
lduw [%i0 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1368: !_LD [30] (Int) (Loop exit) (Branch target of P1904)
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 12], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_2_31:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_31
nop
ba P1369
nop
TARGET1904:
ba RET1904
nop
P1369: !_DWLD [14] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_32:
sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
ldx [%i3 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1370: !_LD [27] (Int) (Loop exit) (CBR)
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 32], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET1370
nop
RET1370:
! lfsr step begin
srlx %l0, 1, %l3
xnor %l3, %l0, %l3
sllx %l3, 63, %l3
or %l3, %l0, %l0
srlx %l0, 1, %l0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_2_32:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_32
nop
P1371: !_SWAP [1] (maybe <- 0x1000006) (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_33:
mov %l4, %o0
swap [%i0 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
add %l4, 1, %l4
P1372: !_LD [16] (Int) (Loop exit)
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 0], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_2_33:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_33
nop
P1373: !_LD [11] (Int) (Loop entry) (LE)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_34:
wr %g0, 0x88, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduwa [%i2 + 32] %asi, %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1374: !_DWLD [29] (Int)
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
ldx [%i3 + 0], %l6
! move %l6(upper) -> %o0(lower)
srlx %l6, 32, %l3
or %l3, %o0, %o0
! move %l6(lower) -> %o1(upper)
sllx %l6, 32, %o1
P1375: !_LD [27] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 32], %l3
! move %l3(lower) -> %o1(lower)
or %l3, %o1, %o1
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_2_34:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_34
nop
P1376: !_DWLD [14] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_35:
sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
ldx [%i3 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1377: !_LD [20] (Int) (Loop exit) (LE)
wr %g0, 0x88, %asi
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduwa [%i2 + 0] %asi, %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_2_35:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_35
nop
P1378: !_DWLD [31] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_36:
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
ldx [%i3 + 32], %o0
! move %o0(upper) -> %o0(upper)
P1379: !_LD [1] (Int) (Loop exit) (LE)
wr %g0, 0x88, %asi
lduwa [%i0 + 4] %asi, %l3
! move %l3(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_2_36:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_36
nop
P1380: !_DWLD [19] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_37:
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
ldx [%i2 + 32], %o0
! move %o0(upper) -> %o0(upper)
P1381: !_DWLD [2] (Int) (Loop exit)
ldx [%i0 + 8], %l7
! move %l7(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
srl %l7, 0, %l6
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_2_37:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_37
nop
P1382: !_LD [4] (Int) (Loop entry) (Branch target of P1455)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_38:
lduw [%i1 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
ba P1383
nop
TARGET1455:
ba RET1455
nop
P1383: !_DWLD [24] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 0], %l3
! move %l3(upper) -> %o0(lower)
srlx %l3, 32, %o5
or %o5, %o0, %o0
! move %l3(lower) -> %o1(upper)
sllx %l3, 32, %o1
P1384: !_LD [21] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %l7
! move %l7(lower) -> %o1(lower)
or %l7, %o1, %o1
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_2_38:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_38
nop
P1385: !_BLD [26] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_39:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_2_39:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_39
nop
P1386: !_BLD [30] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_40:
wr %g0, 0xf0, %asi
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_2_40:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_40
nop
P1387: !_BLD [28] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_41:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_2_41:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_41
nop
P1388: !_LD [8] (Int) (Loop entry) (LE)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_42:
wr %g0, 0x88, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduwa [%i2 + 0] %asi, %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1389: !_DWLD [29] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 0], %l6
! move %l6(upper) -> %o0(lower)
srlx %l6, 32, %l3
or %l3, %o0, %o0
! move %l6(lower) -> %o1(upper)
sllx %l6, 32, %o1
P1390: !_LD [7] (Int) (Loop exit)
lduw [%i1 + 32], %o5
! move %o5(lower) -> %o1(lower)
or %o5, %o1, %o1
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_2_42:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_42
nop
P1391: !_LD [10] (Int) (Loop entry) (CBR)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_43:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET1391
nop
RET1391:
! lfsr step begin
srlx %l0, 1, %l3
xnor %l3, %l0, %l3
sllx %l3, 63, %l3
or %l3, %l0, %l0
srlx %l0, 1, %l0
P1392: !_BLD [9] (FP)
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P1393: !_LD [5] (Int) (Loop exit)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 5
sethi %hi(0xc0000), %l6
sub %i1, %l6, %i1
lduw [%i1 + 4], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
sethi %hi(0xc0000), %l3
add %i1, %l3, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_2_43:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_43
nop
P1394: !_BLD [8] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_44:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_2_44:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_44
nop
P1395: !_DWLD [6] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_45:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 6
sethi %hi(0xc0000), %l7
sub %i1, %l7, %i1
ldx [%i1 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1396: !_LD [27] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 32], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
sethi %hi(0xc0000), %o5
add %i1, %o5, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_2_45:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_45
nop
P1397: !_LD [7] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_46:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 7
sethi %hi(0xc0000), %l3
sub %i1, %l3, %i1
lduw [%i1 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1398: !_LD [31] (Int) (Loop exit) (Branch target of P1608)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
sethi %hi(0xc0000), %l6
add %i1, %l6, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_2_46:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_46
nop
ba P1399
nop
TARGET1608:
ba RET1608
nop
P1399: !_CASX [15] (maybe <- 0x1000007) (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_47:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i2
sub %i0, %i2, %i2
add %i2, 32, %l3
ldx [%l3], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
mov %o0, %o5
sllx %l4, 32, %o1
casx [%l3], %o5, %o1
! move %o1(upper) -> %o1(upper)
! move %o1(lower) -> %o1(lower)
add %l4, 1, %l4
P1400: !_DWLD [3] (Int)
ldx [%i0 + 32], %o2
! move %o2(upper) -> %o2(upper)
P1401: !_LD [6] (Int) (Loop exit)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 6
sethi %hi(0xc0000), %l6
sub %i1, %l6, %i1
lduw [%i1 + 12], %o5
! move %o5(lower) -> %o2(lower)
srlx %o2, 32, %o2
sllx %o2, 32, %o2
or %o5, %o2, %o2
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
mov %o2, %l5
sethi %hi(0xc0000), %l3
add %i1, %l3, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_2_47:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_47
nop
P1402: !_LD [31] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_48:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1403: !_DWLD [1] (FP)
ldd [%i0 + 0], %f0
! 2 addresses covered
P1404: !_LD [7] (Int) (Loop exit)
lduw [%i1 + 32], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
!--
loop_exit_2_48:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_48
nop
P1405: !_CAS [8] (maybe <- 0x1000008) (Int) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_49:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2], %o0
mov %o0, %l3
! move %l3(lower) -> %o0(upper)
sllx %l3, 32, %o0
mov %l4, %o5
cas [%i2], %l3, %o5
! move %o5(lower) -> %o0(lower)
srl %o5, 0, %l3
or %l3, %o0, %o0
add %l4, 1, %l4
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_2_49:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_49
nop
P1406: !_DWLD [31] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_50:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 32], %o0
! move %o0(upper) -> %o0(upper)
P1407: !_DWLD [21] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 0], %l6
! move %l6(upper) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
srlx %l6, 32, %l3
or %l3, %o0, %o0
! move %l6(lower) -> %o1(upper)
sllx %l6, 32, %o1
P1408: !_LD [17] (Int) (Loop exit)
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 4], %o5
! move %o5(lower) -> %o1(lower)
or %o5, %o1, %o1
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_2_50:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_50
nop
P1409: !_DWLD [4] (Int) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_51:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 4
sethi %hi(0xc0000), %l6
sub %i1, %l6, %i1
ldx [%i1 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
sethi %hi(0xc0000), %l3
add %i1, %l3, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_2_51:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_51
nop
P1410: !_BSTC [13] (maybe <- 0x40800005) (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_52:
wr %g0, 0xe0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i2
sub %i0, %i2, %i2
! preparing store val #0, next val will be in f32
fmovs %f16, %f20
fadds %f16, %f17, %f16
! preparing store val #1, next val will be in f33
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #2, next val will be in f35
fmovd %f20, %f32
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #3, next val will be in f40
fmovd %f20, %f34
fmovs %f16, %f20
fadds %f16, %f17, %f16
fmovd %f20, %f40
membar #Sync
stda %f32, [%i2 + 0 ] %asi
membar #Sync
loop_exit_2_52:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_52
nop
P1411: !_CASX [29] (maybe <- 0x1000009) (Int) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_53:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i3
sub %i0, %i3, %i3
ldx [%i3], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
mov %o0, %l7
sllx %l4, 32, %o1
add %l4, 1, %l4
or %l4, %o1, %o1
casx [%i3], %l7, %o1
! move %o1(upper) -> %o1(upper)
! move %o1(lower) -> %o1(lower)
add %l4, 1, %l4
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_2_53:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_53
nop
P1412: !_SWAP [26] (maybe <- 0x100000b) (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_54:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i2
sub %i0, %i2, %i2
mov %l4, %o0
swap [%i2 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
add %l4, 1, %l4
P1413: !_LD [10] (Int) (Loop exit)
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 12], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_2_54:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_54
nop
P1414: !_DWLD [20] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_55:
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
P1415: !_BLD [3] (FP) (Loop exit)
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i0 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_2_55:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_55
nop
P1416: !_LD [29] (FP) (Loop entry) (Loop exit) (CBR)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_56:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i3
sub %i0, %i3, %i3
ld [%i3 + 4], %f0
! 1 addresses covered
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET1416
nop
RET1416:
! lfsr step begin
srlx %l0, 1, %l7
xnor %l7, %l0, %l7
sllx %l7, 63, %l7
or %l7, %l0, %l0
srlx %l0, 1, %l0
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
loop_exit_2_56:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_56
nop
P1417: !_BLD [12] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_57:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P1418: !_LD [19] (Int) (CBR)
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET1418
nop
RET1418:
! lfsr step begin
srlx %l0, 1, %o5
xnor %o5, %l0, %o5
sllx %o5, 63, %o5
or %o5, %l0, %l0
srlx %l0, 1, %l0
P1419: !_LD [17] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_2_57:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_57
nop
P1420: !_DWLD [14] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_58:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1421: !_LD [22] (Int) (Loop exit)
sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 12], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_2_58:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_58
nop
P1422: !_LD [8] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_59:
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1423: !_LD [27] (Int) (Loop exit)
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 32], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_2_59:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_59
nop
P1424: !_LD [8] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_60:
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1425: !_LD [10] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_2_60:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_60
nop
P1426: !_DWLD [19] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_61:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 32], %o0
! move %o0(upper) -> %o0(upper)
P1427: !_LD [6] (Int) (Loop exit) (Branch target of P1812)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 6
sethi %hi(0xc0000), %l3
sub %i1, %l3, %i1
lduw [%i1 + 12], %l7
! move %l7(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
sethi %hi(0xc0000), %o5
add %i1, %o5, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_2_61:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_61
nop
ba P1428
nop
TARGET1812:
ba RET1812
nop
P1428: !_BLD [6] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_62:
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P1429: !_BSTC [20] (maybe <- 0x40800009) (FP) (Loop exit) (Branch target of P1391)
wr %g0, 0xe0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i2
sub %i0, %i2, %i2
! preparing store val #0, next val will be in f32
fmovs %f16, %f20
fadds %f16, %f17, %f16
! preparing store val #1, next val will be in f33
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #2, next val will be in f35
fmovd %f20, %f32
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #3, next val will be in f40
fmovd %f20, %f34
fmovs %f16, %f20
fadds %f16, %f17, %f16
fmovd %f20, %f40
membar #Sync
stda %f32, [%i2 + 0 ] %asi
membar #Sync
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_2_62:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_62
nop
ba P1430
nop
TARGET1391:
ba RET1391
nop
P1430: !_LD [23] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_63:
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1431: !_LD [26] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_2_63:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_63
nop
P1432: !_BSTC [26] (maybe <- 0x4080000d) (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_64:
wr %g0, 0xe0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
sub %i0, %i3, %i3
! preparing store val #0, next val will be in f32
fmovs %f16, %f20
fadds %f16, %f17, %f16
! preparing store val #1, next val will be in f33
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #2, next val will be in f35
fmovd %f20, %f32
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #3, next val will be in f40
fmovd %f20, %f34
fmovs %f16, %f20
fadds %f16, %f17, %f16
fmovd %f20, %f40
membar #Sync
stda %f32, [%i3 + 0 ] %asi
membar #Sync
loop_exit_2_64:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_64
nop
P1433: !_BLD [9] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_65:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_2_65:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_65
nop
P1434: !_DWLD [22] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_66:
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1435: !_BLD [0] (FP)
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i0 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P1436: !_LD [6] (Int) (Loop exit)
lduw [%i1 + 12], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_2_66:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_66
nop
P1437: !_BLD [27] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_67:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_2_67:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_67
nop
P1438: !_LD [2] (Int) (Loop entry) (LE)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_68:
wr %g0, 0x88, %asi
lduwa [%i0 + 12] %asi, %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1439: !_LD [27] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_2_68:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_68
nop
P1440: !_DWST [17] (maybe <- 0x40800011) (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_69:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
sub %i0, %i2, %i2
! preparing store val #0, next val will be in f20
fmovs %f16, %f20
fadds %f16, %f17, %f16
! preparing store val #1, next val will be in f21
fmovs %f16, %f21
fadds %f16, %f17, %f16
std %f20, [%i2 + 0]
P1441: !_DWLD [11] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 32], %o0
! move %o0(upper) -> %o0(upper)
P1442: !_LD [26] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %l7
! move %l7(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_2_69:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_69
nop
P1443: !_LD [9] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_70:
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1444: !_LD [16] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 0], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_2_70:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_70
nop
P1445: !_DWLD [20] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_71:
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
sub %i0, %i3, %i3
ldd [%i3 + 0], %f0
! 2 addresses covered
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
!--
loop_exit_2_71:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_71
nop
P1446: !_BLD [2] (FP) (Loop entry) (Branch target of P1786)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_72:
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i0 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
ba P1447
nop
TARGET1786:
ba RET1786
nop
P1447: !_CAS [27] (maybe <- 0x100000c) (Int) (Loop exit)
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
add %i2, 32, %l7
lduw [%l7], %o0
mov %o0, %l6
! move %l6(lower) -> %o0(upper)
sllx %l6, 32, %o0
mov %l4, %l3
cas [%l7], %l6, %l3
! move %l3(lower) -> %o0(lower)
srl %l3, 0, %l6
or %l6, %o0, %o0
add %l4, 1, %l4
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_2_72:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_72
nop
P1448: !_REPLACEMENT [1] (Int) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_73:
sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS3_O), %i3
sub %i0, %i3, %i3
sethi %hi(0x10000), %l7
ld [%i3+4], %l3
st %l3, [%i3+4]
add %i3, %l7, %o5
ld [%o5+4], %l3
st %l3, [%o5+4]
add %o5, %l7, %o5
ld [%o5+4], %l3
st %l3, [%o5+4]
add %o5, %l7, %o5
ld [%o5+4], %l3
st %l3, [%o5+4]
loop_exit_2_73:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_73
nop
P1449: !_BLD [25] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_74:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P1450: !_LD [20] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1451: !_LD [17] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_2_74:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_74
nop
P1452: !_BLD [0] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_75:
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i0 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P1453: !_BLD [14] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f32
membar #Sync
! 4 addresses covered
fmovd %f32, %f4
fmovd %f34, %f18
fmovs %f19, %f6
fmovd %f40, %f18
fmovs %f18, %f7
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovd %f4, %f30
fmovd %f6, %f30
!--
loop_exit_2_75:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_75
nop
P1454: !_LD [28] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_76:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1455: !_LD [29] (Int) (Loop exit) (CBR)
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 4], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET1455
nop
RET1455:
! lfsr step begin
srlx %l0, 1, %l3
xnor %l3, %l0, %l3
sllx %l3, 63, %l3
or %l3, %l0, %l0
srlx %l0, 1, %l0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_2_76:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_76
nop
P1456: !_LD [11] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_77:
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1457: !_LD [12] (Int) (Loop exit)
sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 0], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_2_77:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_77
nop
P1458: !_BLD [27] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_78:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_2_78:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_78
nop
P1459: !_DWLD [19] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_79:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 32], %o0
! move %o0(upper) -> %o0(upper)
P1460: !_LD [0] (Int) (Loop exit)
lduw [%i0 + 0], %l6
! move %l6(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_2_79:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_79
nop
P1461: !_LD [20] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_80:
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i2
sub %i0, %i2, %i2
ld [%i2 + 0], %f0
! 1 addresses covered
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
loop_exit_2_80:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_80
nop
P1462: !_BSTC [23] (maybe <- 0x40800013) (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_81:
wr %g0, 0xe0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i3
sub %i0, %i3, %i3
! preparing store val #0, next val will be in f32
fmovs %f16, %f20
fadds %f16, %f17, %f16
! preparing store val #1, next val will be in f33
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #2, next val will be in f35
fmovd %f20, %f32
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #3, next val will be in f40
fmovd %f20, %f34
fmovs %f16, %f20
fadds %f16, %f17, %f16
fmovd %f20, %f40
membar #Sync
stda %f32, [%i3 + 0 ] %asi
membar #Sync
loop_exit_2_81:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_81
nop
P1463: !_BLD [24] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_82:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P1464: !_BLD [28] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f32
membar #Sync
! 4 addresses covered
fmovd %f32, %f4
fmovd %f34, %f18
fmovs %f19, %f6
fmovd %f40, %f18
fmovs %f18, %f7
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovd %f4, %f30
fmovd %f6, %f30
!--
loop_exit_2_82:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_82
nop
P1465: !_BLD [30] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_83:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P1466: !_BLD [0] (FP) (Loop exit)
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i0 + 0] %asi, %f32
membar #Sync
! 4 addresses covered
fmovd %f32, %f4
fmovd %f34, %f18
fmovs %f19, %f6
fmovd %f40, %f18
fmovs %f18, %f7
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovd %f4, %f30
fmovd %f6, %f30
!--
loop_exit_2_83:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_83
nop
P1467: !_LD [6] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_84:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 6
sethi %hi(0xc0000), %l6
sub %i1, %l6, %i1
ld [%i1 + 12], %f0
! 1 addresses covered
P1468: !_CASX [27] (maybe <- 0x100000d) (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i3
sub %i0, %i3, %i3
add %i3, 32, %o5
ldx [%o5], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
mov %o0, %l7
sllx %l4, 32, %o1
casx [%o5], %l7, %o1
! move %o1(upper) -> %o1(upper)
! move %o1(lower) -> %o1(lower)
add %l4, 1, %l4
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
sethi %hi(0xc0000), %l7
add %i1, %l7, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_2_84:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_84
nop
P1469: !_LD [15] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_85:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1470: !_LD [4] (Int) (Loop exit)
lduw [%i1 + 0], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_2_85:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_85
nop
P1471: !_DWLD [3] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_86:
ldx [%i0 + 32], %o0
! move %o0(upper) -> %o0(upper)
P1472: !_LD [20] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %l6
! move %l6(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_2_86:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_86
nop
P1473: !_DWLD [17] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_87:
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
ldx [%i2 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
P1474: !_DWLD [11] (Int)
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
ldx [%i3 + 32], %o1
! move %o1(upper) -> %o1(upper)
P1475: !_LD [22] (Int) (Loop exit)
sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 12], %l7
! move %l7(lower) -> %o1(lower)
srlx %o1, 32, %o1
sllx %o1, 32, %o1
or %l7, %o1, %o1
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_2_87:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_87
nop
P1476: !_DWLD [18] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_88:
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
ldx [%i3 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1477: !_LD [11] (FP)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i2
sub %i0, %i2, %i2
ld [%i2 + 32], %f0
! 1 addresses covered
P1478: !_LD [4] (Int) (Loop exit)
lduw [%i1 + 0], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
loop_exit_2_88:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_88
nop
P1479: !_DWLD [0] (Int) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_89:
ldx [%i0 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_2_89:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_89
nop
P1480: !_DWLD [23] (Int) (Loop entry) (CBR)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_90:
sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
ldx [%i3 + 32], %o0
! move %o0(upper) -> %o0(upper)
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET1480
nop
RET1480:
! lfsr step begin
srlx %l0, 1, %l3
xnor %l3, %l0, %l3
sllx %l3, 63, %l3
or %l3, %l0, %l0
srlx %l0, 1, %l0
P1481: !_LD [3] (Int) (Loop exit)
lduw [%i0 + 32], %o5
! move %o5(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_2_90:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_90
nop
P1482: !_BLD [29] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_91:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_2_91:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_91
nop
P1483: !_LD [16] (Int) (Loop entry) (LE)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_92:
wr %g0, 0x88, %asi
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduwa [%i3 + 0] %asi, %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1484: !_LD [13] (Int) (Loop exit) (Branch target of P1538)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_2_92:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_92
nop
ba P1485
nop
TARGET1538:
ba RET1538
nop
P1485: !_DWLD [4] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_93:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 4
sethi %hi(0xc0000), %l3
sub %i1, %l3, %i1
ldx [%i1 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
P1486: !_PREFETCH [11] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i3
sub %i0, %i3, %i3
prefetch [%i3 + 32], 1
!---- flushing int results buffer----
mov %o0, %l5
sethi %hi(0xc0000), %o5
add %i1, %o5, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_2_93:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_93
nop
P1487: !_DWLD [4] (Int) (Loop entry) (CBR)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_94:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 4
sethi %hi(0xc0000), %l3
sub %i1, %l3, %i1
ldx [%i1 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET1487
nop
RET1487:
! lfsr step begin
srlx %l0, 1, %o5
xnor %o5, %l0, %o5
sllx %o5, 63, %o5
or %o5, %l0, %l0
srlx %l0, 1, %l0
P1488: !_DWLD [27] (FP) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i2
sub %i0, %i2, %i2
ldd [%i2 + 32], %f0
! 1 addresses covered
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
sethi %hi(0xc0000), %l3
add %i1, %l3, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_2_94:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_94
nop
P1489: !_LD [17] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_95:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1490: !_LD [23] (Int) (Loop exit) (LE)
wr %g0, 0x88, %asi
sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduwa [%i2 + 32] %asi, %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_2_95:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_95
nop
P1491: !_LD [31] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_96:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i3
sub %i0, %i3, %i3
ld [%i3 + 32], %f0
! 1 addresses covered
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
loop_exit_2_96:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_96
nop
P1492: !_BLD [22] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_97:
wr %g0, 0xf0, %asi
sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_2_97:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_97
nop
P1493: !_NOP (Int) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_98:
nop
loop_exit_2_98:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_98
nop
P1494: !_DWLD [22] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_99:
sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
ldx [%i3 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1495: !_LD [18] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_2_99:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_99
nop
P1496: !_BLD [21] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_100:
wr %g0, 0xf0, %asi
sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_2_100:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_100
nop
P1497: !_BLD [26] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_101:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_2_101:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_101
nop
P1498: !_CAS [23] (maybe <- 0x100000e) (Int) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_102:
sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
add %i3, 32, %l7
lduw [%l7], %o0
mov %o0, %l6
! move %l6(lower) -> %o0(upper)
sllx %l6, 32, %o0
mov %l4, %l3
cas [%l7], %l6, %l3
! move %l3(lower) -> %o0(lower)
srl %l3, 0, %l6
or %l6, %o0, %o0
add %l4, 1, %l4
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_2_102:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_102
nop
P1499: !_LD [28] (Int) (Loop entry) (CBR)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_103:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET1499
nop
RET1499:
! lfsr step begin
srlx %l0, 1, %l6
xnor %l6, %l0, %l6
sllx %l6, 63, %l6
or %l6, %l0, %l0
srlx %l0, 1, %l0
P1500: !_LD [5] (Int) (Loop exit)
lduw [%i1 + 4], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_2_103:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_103
nop
P1501: !_DWLD [7] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_104:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 7
sethi %hi(0xc0000), %l6
sub %i1, %l6, %i1
ldx [%i1 + 32], %o0
! move %o0(upper) -> %o0(upper)
P1502: !_LD [3] (Int) (Loop exit)
lduw [%i0 + 32], %l6
! move %l6(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
sethi %hi(0xc0000), %l7
add %i1, %l7, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_2_104:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_104
nop
P1503: !_LD [14] (Int) (Loop entry) (LE)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_105:
wr %g0, 0x88, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduwa [%i3 + 12] %asi, %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1504: !_LD [9] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_2_105:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_105
nop
P1505: !_BLD [25] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_106:
wr %g0, 0xf0, %asi
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_2_106:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_106
nop
P1506: !_DWLD [28] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_107:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
P1507: !_DWLD [12] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 0], %o1
! move %o1(upper) -> %o1(upper)
! move %o1(lower) -> %o1(lower)
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_2_107:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_107
nop
P1508: !_LD [17] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_108:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i2
sub %i0, %i2, %i2
ld [%i2 + 4], %f0
! 1 addresses covered
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
loop_exit_2_108:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_108
nop
P1509: !_DWLD [2] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_109:
ldx [%i0 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1510: !_DWLD [7] (Int) (Loop exit)
ldx [%i1 + 32], %l7
! move %l7(upper) -> %o0(lower)
srlx %l7, 32, %l6
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_2_109:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_109
nop
P1511: !_BLD [3] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_110:
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i0 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_2_110:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_110
nop
P1512: !_DWLD [31] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_111:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i3
sub %i0, %i3, %i3
ldd [%i3 + 32], %f0
! 1 addresses covered
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
loop_exit_2_111:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_111
nop
P1513: !_LD [16] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_112:
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1514: !_MEMBAR (Int)
membar #StoreLoad
P1515: !_LD [7] (Int) (Loop exit)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 7
sethi %hi(0xc0000), %l7
sub %i1, %l7, %i1
lduw [%i1 + 32], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
sethi %hi(0xc0000), %l6
add %i1, %l6, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_2_112:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_112
nop
P1516: !_LD [27] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_113:
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
ld [%i3 + 32], %f0
! 1 addresses covered
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
loop_exit_2_113:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_113
nop
P1517: !_LD [8] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_114:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1518: !_LD [25] (Int) (Loop exit)
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 4], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_2_114:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_114
nop
P1519: !_BLD [5] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_115:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 5
sethi %hi(0xc0000), %l6
sub %i1, %l6, %i1
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
sethi %hi(0xc0000), %l7
add %i1, %l7, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_2_115:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_115
nop
P1520: !_LD [20] (Int) (Loop entry) (CBR)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_116:
sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET1520
nop
RET1520:
! lfsr step begin
srlx %l0, 1, %l6
xnor %l6, %l0, %l6
sllx %l6, 63, %l6
or %l6, %l0, %l0
srlx %l0, 1, %l0
P1521: !_LD [0] (Int) (Loop exit)
lduw [%i0 + 0], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_2_116:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_116
nop
P1522: !_LD [6] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_117:
lduw [%i1 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1523: !_LD [23] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_2_117:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_117
nop
P1524: !_LD [30] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_118:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1525: !_LD [10] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_2_118:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_118
nop
P1526: !_BLD [12] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_119:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_2_119:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_119
nop
P1527: !_DWLD [3] (Int) (Loop entry) (LE)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_120:
wr %g0, 0x88, %asi
ldxa [%i0 + 32] %asi, %l6
! move %l6(lower) -> %o0(upper)
sllx %l6, 32, %o0
P1528: !_REPLACEMENT [28] (Int)
sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS1_O), %i3
sub %i0, %i3, %i3
sethi %hi(0x10000), %l7
ld [%i3+0], %l3
st %l3, [%i3+0]
add %i3, %l7, %o5
ld [%o5+0], %l3
st %l3, [%o5+0]
add %o5, %l7, %o5
ld [%o5+0], %l3
st %l3, [%o5+0]
add %o5, %l7, %o5
ld [%o5+0], %l3
st %l3, [%o5+0]
P1529: !_LD [28] (Int) (Loop exit) (Branch target of P1520)
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 0], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_2_120:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_120
nop
ba P1530
nop
TARGET1520:
ba RET1520
nop
P1530: !_LD [24] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_121:
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
ld [%i3 + 0], %f0
! 1 addresses covered
P1531: !_LD [30] (Int) (Branch target of P1324)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
ba P1532
nop
TARGET1324:
ba RET1324
nop
P1532: !_LD [17] (Int) (Loop exit)
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 4], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
loop_exit_2_121:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_121
nop
P1533: !_BLD [3] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_122:
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i0 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_2_122:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_122
nop
P1534: !_DWLD [26] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_123:
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
ldx [%i2 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1535: !_BLD [15] (FP)
wr %g0, 0xf0, %asi
sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P1536: !_LD [16] (Int) (Loop exit)
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 0], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_2_123:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_123
nop
P1537: !_LD [12] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_124:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1538: !_LD [29] (Int) (Loop exit) (CBR)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET1538
nop
RET1538:
! lfsr step begin
srlx %l0, 1, %l3
xnor %l3, %l0, %l3
sllx %l3, 63, %l3
or %l3, %l0, %l0
srlx %l0, 1, %l0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_2_124:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_124
nop
P1539: !_DWLD [18] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_125:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1540: !_LD [29] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_2_125:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_125
nop
P1541: !_BLD [0] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_126:
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i0 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P1542: !_BLD [24] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f32
membar #Sync
! 4 addresses covered
fmovd %f32, %f4
fmovd %f34, %f18
fmovs %f19, %f6
fmovd %f40, %f18
fmovs %f18, %f7
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovd %f4, %f30
fmovd %f6, %f30
!--
loop_exit_2_126:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_126
nop
P1543: !_LD [0] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_127:
lduw [%i0 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1544: !_DWLD [8] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 0], %l7
! move %l7(upper) -> %o0(lower)
srlx %l7, 32, %l6
or %l6, %o0, %o0
! move %l7(lower) -> %o1(upper)
sllx %l7, 32, %o1
P1545: !_LD [10] (Int) (Loop exit)
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 12], %l6
! move %l6(lower) -> %o1(lower)
or %l6, %o1, %o1
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_2_127:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_127
nop
P1546: !_LD [16] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_128:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1547: !_LD [11] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_2_128:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_128
nop
P1548: !_BLD [13] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_129:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P1549: !_BLD [6] (FP) (Loop exit)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 6
sethi %hi(0xc0000), %l6
sub %i1, %l6, %i1
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f32
membar #Sync
! 4 addresses covered
fmovd %f32, %f4
fmovd %f34, %f18
fmovs %f19, %f6
fmovd %f40, %f18
fmovs %f18, %f7
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovd %f4, %f30
fmovd %f6, %f30
!--
sethi %hi(0xc0000), %l7
add %i1, %l7, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_2_129:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_129
nop
P1550: !_BLD [5] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_130:
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P1551: !_LD [20] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1552: !_LD [5] (Int) (Loop exit)
lduw [%i1 + 4], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_2_130:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_130
nop
P1553: !_BLD [22] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_131:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_2_131:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_131
nop
P1554: !_LD [30] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_132:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
sub %i0, %i3, %i3
ld [%i3 + 12], %f0
! 1 addresses covered
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
loop_exit_2_132:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_132
nop
P1555: !_DWLD [14] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_133:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1556: !_BLD [4] (FP)
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P1557: !_LD [5] (Int) (Loop exit)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 5
sethi %hi(0xc0000), %o5
sub %i1, %o5, %i1
lduw [%i1 + 4], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
sethi %hi(0xc0000), %l7
add %i1, %l7, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_2_133:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_133
nop
P1558: !_ST [8] (maybe <- 0x100000f) (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_134:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i3
sub %i0, %i3, %i3
stw %l4, [%i3 + 0 ]
add %l4, 1, %l4
P1559: !_LD [25] (FP) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
sub %i0, %i2, %i2
ld [%i2 + 4], %f0
! 1 addresses covered
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
loop_exit_2_134:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_134
nop
P1560: !_ST [1] (maybe <- 0x1000010) (Int) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_135:
stw %l4, [%i0 + 4 ]
add %l4, 1, %l4
loop_exit_2_135:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_135
nop
P1561: !_DWLD [23] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_136:
sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
ldd [%i3 + 32], %f0
! 1 addresses covered
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
loop_exit_2_136:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_136
nop
P1562: !_CASX [4] (maybe <- 0x1000011) (Int) (Loop entry) (LE)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_137:
sllx %l4, 32, %o5
add %l4, 1, %l4
or %l4, %o5, %o5
! Change double-word-level endianess (big endian <-> little endian)
sethi %hi(0xff00ff00), %l7
or %l7, %lo(0xff00ff00), %l7
sllx %l7, 32, %l3
or %l7, %l3, %l7
and %o5, %l7, %l3
srlx %l3, 8, %l3
sllx %o5, 8, %o5
and %o5, %l7, %o5
or %o5, %l3, %o5
sethi %hi(0xffff0000), %l7
srlx %o5, 16, %l3
andn %l3, %l7, %l3
andn %o5, %l7, %o5
sllx %o5, 16, %o5
or %o5, %l3, %o5
srlx %o5, 32, %l3
sllx %o5, 32, %o5
or %o5, %l3, %l3
wr %g0, 0x88, %asi
ldxa [%i1] %asi, %l6
! move %l6(lower) -> %o0(upper)
sllx %l6, 32, %o0
! move %l6(upper) -> %o0(lower)
srlx %l6, 32, %l7
or %l7, %o0, %o0
mov %l6, %l7
mov %l3, %l6
casxa [%i1] %asi, %l7, %l6
! move %l6(lower) -> %o1(upper)
sllx %l6, 32, %o1
! move %l6(upper) -> %o1(lower)
srlx %l6, 32, %l7
or %l7, %o1, %o1
add %l4, 1, %l4
P1563: !_LD [30] (Int) (CBR)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %o2
! move %o2(lower) -> %o2(upper)
sllx %o2, 32, %o2
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET1563
nop
RET1563:
! lfsr step begin
srlx %l0, 1, %l6
xnor %l6, %l0, %l6
sllx %l6, 63, %l6
or %l6, %l0, %l0
srlx %l0, 1, %l0
P1564: !_LD [10] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %o5
! move %o5(lower) -> %o2(lower)
or %o5, %o2, %o2
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
mov %o2, %l5
loop_exit_2_137:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_137
nop
P1565: !_LD [21] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_138:
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1566: !_LD [29] (Int) (Loop exit) (CBR)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 4], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET1566
nop
RET1566:
! lfsr step begin
srlx %l0, 1, %l7
xnor %l7, %l0, %l7
sllx %l7, 63, %l7
or %l7, %l0, %l0
srlx %l0, 1, %l0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_2_138:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_138
nop
P1567: !_BLD [1] (FP) (Loop entry) (Loop exit) (CBR)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_139:
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i0 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET1567
nop
RET1567:
! lfsr step begin
srlx %l0, 1, %l6
xnor %l6, %l0, %l6
sllx %l6, 63, %l6
or %l6, %l0, %l0
srlx %l0, 1, %l0
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_2_139:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_139
nop
P1568: !_LD [19] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_140:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1569: !_BLD [1] (FP)
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i0 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P1570: !_LD [31] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_2_140:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_140
nop
P1571: !_LD [14] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_141:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1572: !_LD [1] (Int) (Loop exit) (LE)
wr %g0, 0x88, %asi
lduwa [%i0 + 4] %asi, %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_2_141:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_141
nop
P1573: !_DWLD [19] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_142:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 32], %o0
! move %o0(upper) -> %o0(upper)
P1574: !_BLD [9] (FP) (CBR)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET1574
nop
RET1574:
! lfsr step begin
srlx %l0, 1, %l7
xnor %l7, %l0, %l7
sllx %l7, 63, %l7
or %l7, %l0, %l0
srlx %l0, 1, %l0
P1575: !_LD [11] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %l6
! move %l6(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_2_142:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_142
nop
P1576: !_LD [27] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_143:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1577: !_DWLD [29] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 0], %o5
! move %o5(upper) -> %o0(lower)
srlx %o5, 32, %l7
or %l7, %o0, %o0
! move %o5(lower) -> %o1(upper)
sllx %o5, 32, %o1
P1578: !_LD [15] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 32], %l6
! move %l6(lower) -> %o1(lower)
or %l6, %o1, %o1
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_2_143:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_143
nop
P1579: !_DWLD [26] (Int) (Loop entry) (CBR)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_144:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET1579
nop
RET1579:
! lfsr step begin
srlx %l0, 1, %l7
xnor %l7, %l0, %l7
sllx %l7, 63, %l7
or %l7, %l0, %l0
srlx %l0, 1, %l0
P1580: !_DWLD [11] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 32], %l3
! move %l3(upper) -> %o0(lower)
srlx %l3, 32, %o5
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_2_144:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_144
nop
P1581: !_LD [28] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_145:
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1582: !_DWST [12] (maybe <- 0x1000013) (Int)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i2
sub %i0, %i2, %i2
sllx %l4, 32, %l6
add %l4, 1, %l4
or %l6, %l4, %l6
stx %l6, [%i2 + 0]
add %l4, 1, %l4
P1583: !_LD [17] (Int) (Loop exit) (CBR)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 4], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET1583
nop
RET1583:
! lfsr step begin
srlx %l0, 1, %o5
xnor %o5, %l0, %o5
sllx %o5, 63, %o5
or %o5, %l0, %l0
srlx %l0, 1, %l0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_2_145:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_145
nop
P1584: !_LD [13] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_146:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i2
sub %i0, %i2, %i2
ld [%i2 + 4], %f0
! 1 addresses covered
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
loop_exit_2_146:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_146
nop
P1585: !_BLD [24] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_147:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_2_147:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_147
nop
P1586: !_BLD [10] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_148:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P1587: !_DWLD [25] (Int) (Loop exit)
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
ldx [%i3 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_2_148:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_148
nop
P1588: !_DWLD [4] (Int) (Loop entry) (Loop exit) (LE)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_149:
wr %g0, 0x88, %asi
ldxa [%i1 + 0] %asi, %l6
! move %l6(lower) -> %o0(upper)
sllx %l6, 32, %o0
! move %l6(upper) -> %o0(lower)
srlx %l6, 32, %l3
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_2_149:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_149
nop
P1589: !_DWLD [16] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_150:
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
ldx [%i2 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
P1590: !_LD [6] (Int)
lduw [%i1 + 12], %o1
! move %o1(lower) -> %o1(upper)
sllx %o1, 32, %o1
P1591: !_LD [6] (Int) (Loop exit) (CBR)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 6
sethi %hi(0xc0000), %l3
sub %i1, %l3, %i1
lduw [%i1 + 12], %l7
! move %l7(lower) -> %o1(lower)
or %l7, %o1, %o1
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET1591
nop
RET1591:
! lfsr step begin
srlx %l0, 1, %o5
xnor %o5, %l0, %o5
sllx %o5, 63, %o5
or %o5, %l0, %l0
srlx %l0, 1, %l0
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
sethi %hi(0xc0000), %l3
add %i1, %l3, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_2_150:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_150
nop
P1592: !_ST [28] (maybe <- 0x1000015) (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_151:
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
stw %l4, [%i3 + 0 ]
add %l4, 1, %l4
P1593: !_ST [14] (maybe <- 0x40800017) (FP) (Loop exit) (Branch target of P1598)
sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
! preparing store val #0, next val will be in f20
fmovs %f16, %f20
fadds %f16, %f17, %f16
st %f20, [%i2 + 12 ]
loop_exit_2_151:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_151
nop
ba P1594
nop
TARGET1598:
ba RET1598
nop
P1594: !_LD [5] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_152:
lduw [%i1 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1595: !_LD [15] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_2_152:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_152
nop
P1596: !_LD [27] (Int) (Loop entry) (Branch target of P1825)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_153:
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
ba P1597
nop
TARGET1825:
ba RET1825
nop
P1597: !_LD [25] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 4], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_2_153:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_153
nop
P1598: !_LD [9] (Int) (Loop entry) (CBR)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_154:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET1598
nop
RET1598:
! lfsr step begin
srlx %l0, 1, %o5
xnor %o5, %l0, %o5
sllx %o5, 63, %o5
or %o5, %l0, %l0
srlx %l0, 1, %l0
P1599: !_LD [6] (Int) (Loop exit)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 6
sethi %hi(0xc0000), %l3
sub %i1, %l3, %i1
lduw [%i1 + 12], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
sethi %hi(0xc0000), %o5
add %i1, %o5, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_2_154:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_154
nop
P1600: !_DWLD [21] (Int) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_155:
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_2_155:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_155
nop
P1601: !_BLD [23] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_156:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_2_156:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_156
nop
P1602: !_REPLACEMENT [1] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_157:
sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
sethi %hi(0x10000), %l6
ld [%i3+4], %o5
st %o5, [%i3+4]
add %i3, %l6, %l7
ld [%l7+4], %o5
st %o5, [%l7+4]
add %l7, %l6, %l7
ld [%l7+4], %o5
st %o5, [%l7+4]
add %l7, %l6, %l7
ld [%l7+4], %o5
st %o5, [%l7+4]
P1603: !_DWLD [29] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_2_157:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_157
nop
P1604: !_ST [14] (maybe <- 0x1000016) (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_158:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i3
sub %i0, %i3, %i3
stw %l4, [%i3 + 12 ]
add %l4, 1, %l4
P1605: !_LD [18] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1606: !_LD [9] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 4], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_2_158:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_158
nop
P1607: !_ST [7] (maybe <- 0x1000017) (Int) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_159:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 7
sethi %hi(0xc0000), %l6
sub %i1, %l6, %i1
stw %l4, [%i1 + 32 ]
add %l4, 1, %l4
sethi %hi(0xc0000), %l6
add %i1, %l6, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_2_159:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_159
nop
P1608: !_LD [14] (Int) (Loop entry) (CBR)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_160:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET1608
nop
RET1608:
! lfsr step begin
srlx %l0, 1, %l3
xnor %l3, %l0, %l3
sllx %l3, 63, %l3
or %l3, %l0, %l0
srlx %l0, 1, %l0
P1609: !_BLD [21] (FP)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P1610: !_LD [15] (Int) (Loop exit)
lduw [%i2 + 32], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_2_160:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_160
nop
P1611: !_DWLD [10] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_161:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1612: !_ST [4] (maybe <- 0x1000018) (Int)
stw %l4, [%i1 + 0 ]
add %l4, 1, %l4
P1613: !_LD [20] (Int) (Loop exit)
sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 0], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_2_161:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_161
nop
P1614: !_LD [25] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_162:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1615: !_BST [26] (maybe <- 0x40800018) (FP) (Branch target of P1927)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i3
sub %i0, %i3, %i3
! preparing store val #0, next val will be in f32
fmovs %f16, %f20
fadds %f16, %f17, %f16
! preparing store val #1, next val will be in f33
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #2, next val will be in f35
fmovd %f20, %f32
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #3, next val will be in f40
fmovd %f20, %f34
fmovs %f16, %f20
fadds %f16, %f17, %f16
fmovd %f20, %f40
membar #Sync
stda %f32, [%i3 + 0 ] %asi
membar #Sync
ba P1616
nop
TARGET1927:
ba RET1927
nop
P1616: !_LD [7] (Int) (Loop exit) (CBR)
lduw [%i1 + 32], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET1616
nop
RET1616:
! lfsr step begin
srlx %l0, 1, %o5
xnor %o5, %l0, %o5
sllx %o5, 63, %o5
or %o5, %l0, %l0
srlx %l0, 1, %l0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_2_162:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_162
nop
P1617: !_DWLD [7] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_163:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 7
sethi %hi(0xc0000), %l6
sub %i1, %l6, %i1
ldx [%i1 + 32], %o0
! move %o0(upper) -> %o0(upper)
P1618: !_DWLD [27] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 32], %l6
! move %l6(upper) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
srlx %l6, 32, %l3
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
sethi %hi(0xc0000), %l7
add %i1, %l7, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_2_163:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_163
nop
P1619: !_DWLD [15] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_164:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 32], %o0
! move %o0(upper) -> %o0(upper)
P1620: !_LD [31] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 32], %o5
! move %o5(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_2_164:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_164
nop
P1621: !_LD [19] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_165:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1622: !_LD [7] (Int) (Loop exit)
lduw [%i1 + 32], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_2_165:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_165
nop
P1623: !_DWLD [7] (Int) (Loop entry) (CBR) (Branch target of P1706)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_166:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 7
sethi %hi(0xc0000), %o5
sub %i1, %o5, %i1
ldx [%i1 + 32], %o0
! move %o0(upper) -> %o0(upper)
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET1623
nop
RET1623:
! lfsr step begin
srlx %l0, 1, %l7
xnor %l7, %l0, %l7
sllx %l7, 63, %l7
or %l7, %l0, %l0
srlx %l0, 1, %l0
ba P1624
nop
TARGET1706:
ba RET1706
nop
P1624: !_LD [8] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 0], %l3
! move %l3(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
sethi %hi(0xc0000), %l6
add %i1, %l6, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_2_166:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_166
nop
P1625: !_DWLD [29] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_167:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i3
sub %i0, %i3, %i3
ldd [%i3 + 0], %f0
! 2 addresses covered
P1626: !_DWLD [14] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1627: !_LD [16] (Int) (Loop exit) (LE)
wr %g0, 0x88, %asi
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduwa [%i3 + 0] %asi, %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
!--
loop_exit_2_167:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_167
nop
P1628: !_BLD [7] (FP) (Loop entry) (Loop exit) (CBR) (Branch target of P1616)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_168:
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET1628
nop
RET1628:
! lfsr step begin
srlx %l0, 1, %l6
xnor %l6, %l0, %l6
sllx %l6, 63, %l6
or %l6, %l0, %l0
srlx %l0, 1, %l0
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_2_168:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_168
nop
ba P1629
nop
TARGET1616:
ba RET1616
nop
P1629: !_LD [11] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_169:
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1630: !_LD [12] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_2_169:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_169
nop
P1631: !_BLD [29] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_170:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_2_170:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_170
nop
P1632: !_BLD [19] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_171:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P1633: !_LD [23] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1634: !_LD [21] (Int) (Loop exit)
lduw [%i2 + 4], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_2_171:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_171
nop
P1635: !_BLD [2] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_172:
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i0 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P1636: !_BLD [21] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f32
membar #Sync
! 4 addresses covered
fmovd %f32, %f4
fmovd %f34, %f18
fmovs %f19, %f6
fmovd %f40, %f18
fmovs %f18, %f7
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovd %f4, %f30
fmovd %f6, %f30
!--
loop_exit_2_172:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_172
nop
P1637: !_BLD [12] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_173:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P1638: !_PREFETCH [27] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i3
sub %i0, %i3, %i3
prefetch [%i3 + 32], 1
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_2_173:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_173
nop
P1639: !_LD [18] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_174:
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1640: !_BLD [6] (FP)
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P1641: !_LD [29] (Int) (Loop exit) (CBR)
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 4], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET1641
nop
RET1641:
! lfsr step begin
srlx %l0, 1, %o5
xnor %o5, %l0, %o5
sllx %o5, 63, %o5
or %o5, %l0, %l0
srlx %l0, 1, %l0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_2_174:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_174
nop
P1642: !_BLD [4] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_175:
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_2_175:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_175
nop
P1643: !_LD [31] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_176:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1644: !_BLD [20] (FP)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P1645: !_LD [5] (Int) (Loop exit) (Branch target of P1952)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 5
sethi %hi(0xc0000), %l6
sub %i1, %l6, %i1
lduw [%i1 + 4], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
sethi %hi(0xc0000), %l3
add %i1, %l3, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_2_176:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_176
nop
ba P1646
nop
TARGET1952:
ba RET1952
nop
P1646: !_BLD [14] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_177:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_2_177:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_177
nop
P1647: !_BLD [8] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_178:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_2_178:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_178
nop
P1648: !_BLD [4] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_179:
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P1649: !_DWLD [18] (Int) (Branch target of P1806)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
ba P1650
nop
TARGET1806:
ba RET1806
nop
P1650: !_LD [23] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_2_179:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_179
nop
P1651: !_DWLD [20] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_180:
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
P1652: !_LD [21] (Int) (LE)
wr %g0, 0x88, %asi
lduwa [%i2 + 4] %asi, %o1
! move %o1(lower) -> %o1(upper)
sllx %o1, 32, %o1
P1653: !_LD [16] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %l6
! move %l6(lower) -> %o1(lower)
or %l6, %o1, %o1
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_2_180:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_180
nop
P1654: !_DWLD [22] (Int) (Loop entry) (Branch target of P1487)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_181:
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
ba P1655
nop
TARGET1487:
ba RET1487
nop
P1655: !_LD [20] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_2_181:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_181
nop
P1656: !_LD [24] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_182:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1657: !_LD [16] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_2_182:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_182
nop
P1658: !_DWLD [21] (Int) (Loop entry) (Loop exit) (Branch target of P1623)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_183:
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_2_183:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_183
nop
ba P1659
nop
TARGET1623:
ba RET1623
nop
P1659: !_LD [2] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_184:
lduw [%i0 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1660: !_LD [31] (Int) (Loop exit) (LE)
wr %g0, 0x88, %asi
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduwa [%i3 + 32] %asi, %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_2_184:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_184
nop
P1661: !_BLD [25] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_185:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P1662: !_LD [9] (FP) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i3
sub %i0, %i3, %i3
ld [%i3 + 4], %f4
! 1 addresses covered
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovs %f4, %f30
!--
loop_exit_2_185:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_185
nop
P1663: !_LD [28] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_186:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1664: !_LD [9] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 4], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_2_186:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_186
nop
P1665: !_LD [17] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_187:
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1666: !_LD [15] (Int) (Loop exit) (Branch target of P1784)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_2_187:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_187
nop
ba P1667
nop
TARGET1784:
ba RET1784
nop
P1667: !_BLD [28] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_188:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_2_188:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_188
nop
P1668: !_BLD [12] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_189:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_2_189:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_189
nop
P1669: !_LD [27] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_190:
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1670: !_DWLD [9] (FP)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i3
sub %i0, %i3, %i3
ldd [%i3 + 0], %f0
! 2 addresses covered
P1671: !_LD [18] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
!--
loop_exit_2_190:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_190
nop
P1672: !_LD [3] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_191:
lduw [%i0 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1673: !_DWLD [3] (Int) (Loop exit)
ldx [%i0 + 32], %l3
! move %l3(upper) -> %o0(lower)
srlx %l3, 32, %o5
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_2_191:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_191
nop
P1674: !_BLD [20] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_192:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P1675: !_BLD [19] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f32
membar #Sync
! 4 addresses covered
fmovd %f32, %f4
fmovd %f34, %f18
fmovs %f19, %f6
fmovd %f40, %f18
fmovs %f18, %f7
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovd %f4, %f30
fmovd %f6, %f30
!--
loop_exit_2_192:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_192
nop
P1676: !_DWLD [1] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_193:
ldx [%i0 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
P1677: !_BLD [18] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_2_193:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_193
nop
P1678: !_BLD [30] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_194:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_2_194:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_194
nop
P1679: !_LD [16] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_195:
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
ld [%i3 + 0], %f0
! 1 addresses covered
P1680: !_BLD [25] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f32
membar #Sync
! 4 addresses covered
fmovd %f32, %f18
fmovs %f18, %f1
fmovs %f19, %f2
fmovd %f34, %f18
fmovs %f19, %f3
fmovd %f40, %f4
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovs %f4, %f30
!--
loop_exit_2_195:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_195
nop
P1681: !_CAS [24] (maybe <- 0x1000019) (Int) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_196:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3], %o0
mov %o0, %l3
! move %l3(lower) -> %o0(upper)
sllx %l3, 32, %o0
mov %l4, %o5
cas [%i3], %l3, %o5
! move %o5(lower) -> %o0(lower)
srl %o5, 0, %l3
or %l3, %o0, %o0
add %l4, 1, %l4
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_2_196:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_196
nop
P1682: !_BLD [28] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_197:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P1683: !_BLD [4] (FP) (Loop exit)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 4
sethi %hi(0xc0000), %l6
sub %i1, %l6, %i1
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f32
membar #Sync
! 4 addresses covered
fmovd %f32, %f4
fmovd %f34, %f18
fmovs %f19, %f6
fmovd %f40, %f18
fmovs %f18, %f7
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovd %f4, %f30
fmovd %f6, %f30
!--
sethi %hi(0xc0000), %l7
add %i1, %l7, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_2_197:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_197
nop
P1684: !_BST [14] (maybe <- 0x4080001c) (FP) (Loop entry) (CBR)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_198:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i3
sub %i0, %i3, %i3
! preparing store val #0, next val will be in f32
fmovs %f16, %f20
fadds %f16, %f17, %f16
! preparing store val #1, next val will be in f33
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #2, next val will be in f35
fmovd %f20, %f32
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #3, next val will be in f40
fmovd %f20, %f34
fmovs %f16, %f20
fadds %f16, %f17, %f16
fmovd %f20, %f40
membar #Sync
stda %f32, [%i3 + 0 ] %asi
membar #Sync
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET1684
nop
RET1684:
! lfsr step begin
srlx %l0, 1, %l7
xnor %l7, %l0, %l7
sllx %l7, 63, %l7
or %l7, %l0, %l0
srlx %l0, 1, %l0
P1685: !_BLD [21] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_2_198:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_198
nop
P1686: !_BLD [29] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_199:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P1687: !_DWST [17] (maybe <- 0x100001a) (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
sub %i0, %i2, %i2
sllx %l4, 32, %l7
add %l4, 1, %l4
or %l7, %l4, %l7
stx %l7, [%i2 + 0]
add %l4, 1, %l4
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_2_199:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_199
nop
P1688: !_DWLD [26] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_200:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1689: !_LD [31] (Int) (Loop exit)
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 32], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_2_200:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_200
nop
P1690: !_DWLD [12] (Int) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_201:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_2_201:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_201
nop
P1691: !_LD [27] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_202:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1692: !_LD [11] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_2_202:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_202
nop
P1693: !_ST [12] (maybe <- 0x100001c) (Int) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_203:
sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
stw %l4, [%i2 + 0 ]
add %l4, 1, %l4
loop_exit_2_203:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_203
nop
P1694: !_BST [3] (maybe <- 0x40800020) (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_204:
wr %g0, 0xf0, %asi
! preparing store val #0, next val will be in f32
fmovs %f16, %f20
fadds %f16, %f17, %f16
! preparing store val #1, next val will be in f33
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #2, next val will be in f35
fmovd %f20, %f32
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #3, next val will be in f40
fmovd %f20, %f34
fmovs %f16, %f20
fadds %f16, %f17, %f16
fmovd %f20, %f40
membar #Sync
stda %f32, [%i0 + 0 ] %asi
membar #Sync
P1695: !_LD [6] (Int)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 6
sethi %hi(0xc0000), %l6
sub %i1, %l6, %i1
lduw [%i1 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1696: !_LD [11] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
sethi %hi(0xc0000), %l7
add %i1, %l7, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_2_204:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_204
nop
P1697: !_DWLD [10] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_205:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1698: !_LD [6] (Int) (Loop exit)
lduw [%i1 + 12], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_2_205:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_205
nop
P1699: !_LD [7] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_206:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 7
sethi %hi(0xc0000), %l6
sub %i1, %l6, %i1
lduw [%i1 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1700: !_LD [10] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
sethi %hi(0xc0000), %l7
add %i1, %l7, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_2_206:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_206
nop
P1701: !_BLD [3] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_207:
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i0 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P1702: !_DWLD [13] (Int) (Loop exit)
sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
ldx [%i2 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_2_207:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_207
nop
P1703: !_LD [6] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_208:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 6
sethi %hi(0xc0000), %o5
sub %i1, %o5, %i1
lduw [%i1 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1704: !_LD [22] (Int) (Loop exit)
sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 12], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
sethi %hi(0xc0000), %l3
add %i1, %l3, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_2_208:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_208
nop
P1705: !_LD [30] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_209:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1706: !_LD [8] (Int) (Loop exit) (CBR)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET1706
nop
RET1706:
! lfsr step begin
srlx %l0, 1, %l7
xnor %l7, %l0, %l7
sllx %l7, 63, %l7
or %l7, %l0, %l0
srlx %l0, 1, %l0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_2_209:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_209
nop
P1707: !_BLD [1] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_210:
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i0 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_2_210:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_210
nop
P1708: !_BLD [29] (FP) (Loop entry) (Loop exit) (Branch target of P1684)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_211:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_2_211:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_211
nop
ba P1709
nop
TARGET1684:
ba RET1684
nop
P1709: !_BLD [19] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_212:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P1710: !_BLD [10] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f32
membar #Sync
! 4 addresses covered
fmovd %f32, %f4
fmovd %f34, %f18
fmovs %f19, %f6
fmovd %f40, %f18
fmovs %f18, %f7
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovd %f4, %f30
fmovd %f6, %f30
!--
loop_exit_2_212:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_212
nop
P1711: !_SWAP [3] (maybe <- 0x100001d) (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_213:
mov %l4, %o0
swap [%i0 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
add %l4, 1, %l4
P1712: !_LD [13] (Int) (Loop exit)
sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 4], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_2_213:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_213
nop
P1713: !_BLD [6] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_214:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 6
sethi %hi(0xc0000), %l3
sub %i1, %l3, %i1
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
sethi %hi(0xc0000), %l6
add %i1, %l6, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_2_214:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_214
nop
P1714: !_LD [26] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_215:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1715: !_BLD [17] (FP)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P1716: !_LD [17] (Int) (Loop exit)
lduw [%i3 + 4], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_2_215:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_215
nop
P1717: !_DWLD [25] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_216:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i2
sub %i0, %i2, %i2
ldd [%i2 + 0], %f0
! 2 addresses covered
P1718: !_BLD [27] (FP) (Loop exit)
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i2 + 0] %asi, %f32
membar #Sync
! 4 addresses covered
fmovd %f32, %f2
fmovd %f34, %f18
fmovs %f19, %f4
fmovd %f40, %f18
fmovs %f18, %f5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovd %f4, %f30
!--
loop_exit_2_216:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_216
nop
P1719: !_BLD [6] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_217:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 6
sethi %hi(0xc0000), %l7
sub %i1, %l7, %i1
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
sethi %hi(0xc0000), %o5
add %i1, %o5, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_2_217:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_217
nop
P1720: !_LD [0] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_218:
lduw [%i0 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1721: !_DWLD [8] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 0], %l3
! move %l3(upper) -> %o0(lower)
srlx %l3, 32, %o5
or %o5, %o0, %o0
! move %l3(lower) -> %o1(upper)
sllx %l3, 32, %o1
P1722: !_LD [3] (Int) (Loop exit) (CBR)
lduw [%i0 + 32], %l7
! move %l7(lower) -> %o1(lower)
or %l7, %o1, %o1
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET1722
nop
RET1722:
! lfsr step begin
srlx %l0, 1, %o5
xnor %o5, %l0, %o5
sllx %o5, 63, %o5
or %o5, %l0, %l0
srlx %l0, 1, %l0
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_2_218:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_218
nop
P1723: !_DWLD [14] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_219:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1724: !_FLUSHI [10] (Int)
flush %g0
P1725: !_LD [16] (Int) (Loop exit)
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 0], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_2_219:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_219
nop
P1726: !_LD [21] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_220:
sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1727: !_LD [28] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_2_220:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_220
nop
P1728: !_BLD [5] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_221:
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_2_221:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_221
nop
P1729: !_BST [20] (maybe <- 0x40800024) (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_222:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i2
sub %i0, %i2, %i2
! preparing store val #0, next val will be in f32
fmovs %f16, %f20
fadds %f16, %f17, %f16
! preparing store val #1, next val will be in f33
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #2, next val will be in f35
fmovd %f20, %f32
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #3, next val will be in f40
fmovd %f20, %f34
fmovs %f16, %f20
fadds %f16, %f17, %f16
fmovd %f20, %f40
membar #Sync
stda %f32, [%i2 + 0 ] %asi
membar #Sync
P1730: !_LD [1] (Int)
lduw [%i0 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1731: !_LD [26] (Int) (Loop exit)
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 12], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_2_222:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_222
nop
P1732: !_LD [4] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_223:
ld [%i1 + 0], %f0
! 1 addresses covered
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
loop_exit_2_223:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_223
nop
P1733: !_BLD [20] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_224:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_2_224:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_224
nop
P1734: !_BSTC [27] (maybe <- 0x40800028) (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_225:
wr %g0, 0xe0, %asi
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
! preparing store val #0, next val will be in f32
fmovs %f16, %f20
fadds %f16, %f17, %f16
! preparing store val #1, next val will be in f33
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #2, next val will be in f35
fmovd %f20, %f32
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #3, next val will be in f40
fmovd %f20, %f34
fmovs %f16, %f20
fadds %f16, %f17, %f16
fmovd %f20, %f40
membar #Sync
stda %f32, [%i3 + 0 ] %asi
membar #Sync
loop_exit_2_225:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_225
nop
P1735: !_BSTC [5] (maybe <- 0x4080002c) (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_226:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 5
sethi %hi(0xc0000), %l3
sub %i1, %l3, %i1
wr %g0, 0xe0, %asi
! preparing store val #0, next val will be in f32
fmovs %f16, %f20
fadds %f16, %f17, %f16
! preparing store val #1, next val will be in f33
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #2, next val will be in f35
fmovd %f20, %f32
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #3, next val will be in f40
fmovd %f20, %f34
fmovs %f16, %f20
fadds %f16, %f17, %f16
fmovd %f20, %f40
membar #Sync
stda %f32, [%i1 + 0 ] %asi
membar #Sync
P1736: !_BLD [30] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
sethi %hi(0xc0000), %l3
add %i1, %l3, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_2_226:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_226
nop
P1737: !_DWLD [31] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_227:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 32], %o0
! move %o0(upper) -> %o0(upper)
P1738: !_BLD [2] (FP)
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i0 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P1739: !_LD [29] (Int) (Loop exit)
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 4], %l7
! move %l7(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_2_227:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_227
nop
P1740: !_REPLACEMENT [31] (Int) (Loop entry) (Loop exit) (CBR)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_228:
sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS3_O), %i3
sub %i0, %i3, %i3
sethi %hi(0x10000), %l3
ld [%i3+32], %l7
st %l7, [%i3+32]
add %i3, %l3, %l6
ld [%l6+32], %l7
st %l7, [%l6+32]
add %l6, %l3, %l6
ld [%l6+32], %l7
st %l7, [%l6+32]
add %l6, %l3, %l6
ld [%l6+32], %l7
st %l7, [%l6+32]
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET1740
nop
RET1740:
! lfsr step begin
srlx %l0, 1, %o5
xnor %o5, %l0, %o5
sllx %o5, 63, %o5
or %o5, %l0, %l0
srlx %l0, 1, %l0
loop_exit_2_228:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_228
nop
P1741: !_BLD [12] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_229:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P1742: !_BLD [21] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f32
membar #Sync
! 4 addresses covered
fmovd %f32, %f4
fmovd %f34, %f18
fmovs %f19, %f6
fmovd %f40, %f18
fmovs %f18, %f7
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovd %f4, %f30
fmovd %f6, %f30
!--
loop_exit_2_229:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_229
nop
P1743: !_FLUSHI [23] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_230:
flush %g0
P1744: !_LD [22] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1745: !_LD [28] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_2_230:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_230
nop
P1746: !_DWLD [8] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_231:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
P1747: !_DWLD [4] (Int) (Loop exit)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 4
sethi %hi(0xc0000), %l3
sub %i1, %l3, %i1
ldx [%i1 + 0], %o1
! move %o1(upper) -> %o1(upper)
! move %o1(lower) -> %o1(lower)
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
sethi %hi(0xc0000), %o5
add %i1, %o5, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_2_231:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_231
nop
P1748: !_LD [30] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_232:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1749: !_LD [12] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 0], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_2_232:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_232
nop
P1750: !_LD [14] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_233:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1751: !_LD [6] (Int) (Loop exit)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 6
sethi %hi(0xc0000), %l3
sub %i1, %l3, %i1
lduw [%i1 + 12], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
sethi %hi(0xc0000), %o5
add %i1, %o5, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_2_233:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_233
nop
P1752: !_ST [5] (maybe <- 0x100001e) (Int) (Loop entry) (Loop exit) (LE)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_234:
wr %g0, 0x88, %asi
! Change single-word-level endianess (big endian <-> little endian)
sethi %hi(0xff00ff00), %l6
or %l6, %lo(0xff00ff00), %l6
and %l4, %l6, %l7
srl %l7, 8, %l7
sll %l4, 8, %l3
and %l3, %l6, %l3
or %l3, %l7, %l3
srl %l3, 16, %l7
sll %l3, 16, %l3
srl %l3, 0, %l3
or %l3, %l7, %l3
stwa %l3, [%i1 + 4] %asi
add %l4, 1, %l4
loop_exit_2_234:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_234
nop
P1753: !_CASX [8] (maybe <- 0x100001f) (Int) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_235:
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
ldx [%i2], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
mov %o0, %l6
sllx %l4, 32, %o1
add %l4, 1, %l4
or %l4, %o1, %o1
casx [%i2], %l6, %o1
! move %o1(upper) -> %o1(upper)
! move %o1(lower) -> %o1(lower)
add %l4, 1, %l4
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_2_235:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_235
nop
P1754: !_LD [19] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_236:
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1755: !_LD [6] (Int) (Loop exit)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 6
sethi %hi(0xc0000), %l3
sub %i1, %l3, %i1
lduw [%i1 + 12], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
sethi %hi(0xc0000), %o5
add %i1, %o5, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_2_236:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_236
nop
P1756: !_BSTC [6] (maybe <- 0x40800030) (FP) (Loop entry) (Branch target of P1953)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_237:
wr %g0, 0xe0, %asi
! preparing store val #0, next val will be in f32
fmovs %f16, %f20
fadds %f16, %f17, %f16
! preparing store val #1, next val will be in f33
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #2, next val will be in f35
fmovd %f20, %f32
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #3, next val will be in f40
fmovd %f20, %f34
fmovs %f16, %f20
fadds %f16, %f17, %f16
fmovd %f20, %f40
membar #Sync
stda %f32, [%i1 + 0 ] %asi
membar #Sync
ba P1757
nop
TARGET1953:
ba RET1953
nop
P1757: !_LD [2] (Int)
lduw [%i0 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1758: !_LD [7] (Int) (Loop exit)
lduw [%i1 + 32], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_2_237:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_237
nop
P1759: !_DWLD [31] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_238:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 32], %o0
! move %o0(upper) -> %o0(upper)
P1760: !_LD [26] (Int) (Loop exit)
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 12], %l6
! move %l6(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_2_238:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_238
nop
P1761: !_PREFETCH [17] (Int) (Loop entry) (Branch target of P1416)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_239:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
sub %i0, %i2, %i2
prefetch [%i2 + 4], 1
ba P1762
nop
TARGET1416:
ba RET1416
nop
P1762: !_DWLD [27] (Int)
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
ldx [%i3 + 32], %o0
! move %o0(upper) -> %o0(upper)
P1763: !_LD [16] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 0], %l3
! move %l3(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_2_239:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_239
nop
P1764: !_BLD [8] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_240:
wr %g0, 0xf0, %asi
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P1765: !_BLD [7] (FP) (Loop exit) (Branch target of P1641)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 7
sethi %hi(0xc0000), %l7
sub %i1, %l7, %i1
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f32
membar #Sync
! 4 addresses covered
fmovd %f32, %f4
fmovd %f34, %f18
fmovs %f19, %f6
fmovd %f40, %f18
fmovs %f18, %f7
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovd %f4, %f30
fmovd %f6, %f30
!--
sethi %hi(0xc0000), %o5
add %i1, %o5, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_2_240:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_240
nop
ba P1766
nop
TARGET1641:
ba RET1641
nop
P1766: !_BLD [9] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_241:
wr %g0, 0xf0, %asi
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P1767: !_DWLD [18] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1768: !_LD [17] (Int) (Loop exit)
lduw [%i3 + 4], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_2_241:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_241
nop
P1769: !_BLD [14] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_242:
wr %g0, 0xf0, %asi
sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P1770: !_DWLD [24] (Int) (Loop exit)
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
ldx [%i3 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_2_242:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_242
nop
P1771: !_DWLD [16] (Int) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_243:
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
ldx [%i2 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_2_243:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_243
nop
P1772: !_BLD [27] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_244:
wr %g0, 0xf0, %asi
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P1773: !_DWLD [17] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_2_244:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_244
nop
P1774: !_CASX [19] (maybe <- 0x1000021) (Int) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_245:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
sub %i0, %i3, %i3
add %i3, 32, %o5
ldx [%o5], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
mov %o0, %l7
sllx %l4, 32, %o1
casx [%o5], %l7, %o1
! move %o1(upper) -> %o1(upper)
! move %o1(lower) -> %o1(lower)
add %l4, 1, %l4
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_2_245:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_245
nop
P1775: !_NOP (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_246:
nop
P1776: !_DWLD [19] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 32], %o0
! move %o0(upper) -> %o0(upper)
P1777: !_LD [25] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 4], %l3
! move %l3(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_2_246:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_246
nop
P1778: !_MEMBAR (Int) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_247:
membar #StoreLoad
loop_exit_2_247:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_247
nop
P1779: !_NOP (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_248:
nop
P1780: !_BLD [11] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_2_248:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_248
nop
P1781: !_DWLD [8] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_249:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
P1782: !_DWLD [21] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 0], %o1
! move %o1(upper) -> %o1(upper)
! move %o1(lower) -> %o1(lower)
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_2_249:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_249
nop
P1783: !_BLD [7] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_250:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 7
sethi %hi(0xc0000), %o5
sub %i1, %o5, %i1
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P1784: !_MEMBAR (Int) (Loop exit) (CBR)
membar #StoreLoad
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET1784
nop
RET1784:
! lfsr step begin
srlx %l0, 1, %l3
xnor %l3, %l0, %l3
sllx %l3, 63, %l3
or %l3, %l0, %l0
srlx %l0, 1, %l0
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
sethi %hi(0xc0000), %l6
add %i1, %l6, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_2_250:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_250
nop
P1785: !_BLD [9] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_251:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P1786: !_BLD [3] (FP) (Loop exit) (CBR) (Branch target of P1480)
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i0 + 0] %asi, %f32
membar #Sync
! 4 addresses covered
fmovd %f32, %f4
fmovd %f34, %f18
fmovs %f19, %f6
fmovd %f40, %f18
fmovs %f18, %f7
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET1786
nop
RET1786:
! lfsr step begin
srlx %l0, 1, %o5
xnor %o5, %l0, %o5
sllx %o5, 63, %o5
or %o5, %l0, %l0
srlx %l0, 1, %l0
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovd %f4, %f30
fmovd %f6, %f30
!--
loop_exit_2_251:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_251
nop
ba P1787
nop
TARGET1480:
ba RET1480
nop
P1787: !_DWLD [23] (Int) (Loop entry) (Branch target of P1574)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_252:
sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
ldx [%i2 + 32], %o0
! move %o0(upper) -> %o0(upper)
ba P1788
nop
TARGET1574:
ba RET1574
nop
P1788: !_LD [26] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %l6
! move %l6(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_2_252:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_252
nop
P1789: !_LD [14] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_253:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1790: !_LD [26] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_2_253:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_253
nop
P1791: !_LD [0] (Int) (Loop entry) (LE)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_254:
wr %g0, 0x88, %asi
lduwa [%i0 + 0] %asi, %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1792: !_LD [17] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_2_254:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_254
nop
P1793: !_DWLD [18] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_255:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1794: !_LD [29] (Int) (Loop exit) (LE)
wr %g0, 0x88, %asi
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduwa [%i2 + 4] %asi, %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_2_255:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_255
nop
P1795: !_SWAP [8] (maybe <- 0x1000022) (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_256:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i3
sub %i0, %i3, %i3
mov %l4, %o0
swap [%i3 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
add %l4, 1, %l4
P1796: !_LD [28] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 0], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_2_256:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_256
nop
P1797: !_BLD [7] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_257:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 7
sethi %hi(0xc0000), %l3
sub %i1, %l3, %i1
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
sethi %hi(0xc0000), %l6
add %i1, %l6, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_2_257:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_257
nop
P1798: !_DWLD [19] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_258:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 32], %o0
! move %o0(upper) -> %o0(upper)
P1799: !_LD [12] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 0], %l7
! move %l7(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_2_258:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_258
nop
P1800: !_LD [18] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_259:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1801: !_LD [19] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 32], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_2_259:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_259
nop
P1802: !_DWLD [18] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_260:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1803: !_LD [5] (Int) (Loop exit)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 5
sethi %hi(0xc0000), %l3
sub %i1, %l3, %i1
lduw [%i1 + 4], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
sethi %hi(0xc0000), %o5
add %i1, %o5, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_2_260:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_260
nop
P1804: !_BSTC [5] (maybe <- 0x40800034) (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_261:
wr %g0, 0xe0, %asi
! preparing store val #0, next val will be in f32
fmovs %f16, %f20
fadds %f16, %f17, %f16
! preparing store val #1, next val will be in f33
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #2, next val will be in f35
fmovd %f20, %f32
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #3, next val will be in f40
fmovd %f20, %f34
fmovs %f16, %f20
fadds %f16, %f17, %f16
fmovd %f20, %f40
membar #Sync
stda %f32, [%i1 + 0 ] %asi
membar #Sync
P1805: !_LD [6] (Int)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 6
sethi %hi(0xc0000), %o5
sub %i1, %o5, %i1
lduw [%i1 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1806: !_LD [30] (Int) (Loop exit) (CBR)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET1806
nop
RET1806:
! lfsr step begin
srlx %l0, 1, %l3
xnor %l3, %l0, %l3
sllx %l3, 63, %l3
or %l3, %l0, %l0
srlx %l0, 1, %l0
!---- flushing int results buffer----
mov %o0, %l5
sethi %hi(0xc0000), %l6
add %i1, %l6, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_2_261:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_261
nop
P1807: !_DWLD [9] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_262:
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
ldx [%i3 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
P1808: !_DWLD [29] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 0], %o1
! move %o1(upper) -> %o1(upper)
! move %o1(lower) -> %o1(lower)
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_2_262:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_262
nop
P1809: !_DWLD [4] (Int) (Loop entry) (Loop exit) (Branch target of P1566)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_263:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 4
sethi %hi(0xc0000), %l3
sub %i1, %l3, %i1
ldx [%i1 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
sethi %hi(0xc0000), %o5
add %i1, %o5, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_2_263:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_263
nop
ba P1810
nop
TARGET1566:
ba RET1566
nop
P1810: !_BLD [17] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_264:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P1811: !_LD [7] (Int)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 7
sethi %hi(0xc0000), %l3
sub %i1, %l3, %i1
lduw [%i1 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1812: !_LD [27] (Int) (Loop exit) (CBR)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 32], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET1812
nop
RET1812:
! lfsr step begin
srlx %l0, 1, %l6
xnor %l6, %l0, %l6
sllx %l6, 63, %l6
or %l6, %l0, %l0
srlx %l0, 1, %l0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
sethi %hi(0xc0000), %l7
add %i1, %l7, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_2_264:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_264
nop
P1813: !_BLD [11] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_265:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P1814: !_BLD [27] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f32
membar #Sync
! 4 addresses covered
fmovd %f32, %f4
fmovd %f34, %f18
fmovs %f19, %f6
fmovd %f40, %f18
fmovs %f18, %f7
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovd %f4, %f30
fmovd %f6, %f30
!--
loop_exit_2_265:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_265
nop
P1815: !_BST [6] (maybe <- 0x40800038) (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_266:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 6
sethi %hi(0xc0000), %l6
sub %i1, %l6, %i1
wr %g0, 0xf0, %asi
! preparing store val #0, next val will be in f32
fmovs %f16, %f20
fadds %f16, %f17, %f16
! preparing store val #1, next val will be in f33
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #2, next val will be in f35
fmovd %f20, %f32
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #3, next val will be in f40
fmovd %f20, %f34
fmovs %f16, %f20
fadds %f16, %f17, %f16
fmovd %f20, %f40
membar #Sync
stda %f32, [%i1 + 0 ] %asi
membar #Sync
P1816: !_LD [1] (Int) (CBR)
lduw [%i0 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET1816
nop
RET1816:
! lfsr step begin
srlx %l0, 1, %o5
xnor %o5, %l0, %o5
sllx %o5, 63, %o5
or %o5, %l0, %l0
srlx %l0, 1, %l0
P1817: !_LD [14] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
sethi %hi(0xc0000), %o5
add %i1, %o5, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_2_266:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_266
nop
P1818: !_DWLD [1] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_267:
ldx [%i0 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
P1819: !_DWLD [12] (FP) (Loop exit) (Branch target of P1563)
sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
ldd [%i2 + 0], %f0
! 2 addresses covered
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
!--
loop_exit_2_267:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_267
nop
ba P1820
nop
TARGET1563:
ba RET1563
nop
P1820: !_BLD [14] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_268:
wr %g0, 0xf0, %asi
sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P1821: !_SWAP [29] (maybe <- 0x1000023) (Int)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i2
sub %i0, %i2, %i2
mov %l4, %o0
swap [%i2 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
add %l4, 1, %l4
P1822: !_LD [26] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_2_268:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_268
nop
P1823: !_BLD [26] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_269:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_2_269:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_269
nop
P1824: !_DWLD [1] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_270:
ldx [%i0 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
P1825: !_LD [30] (Int) (CBR)
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 12], %o1
! move %o1(lower) -> %o1(upper)
sllx %o1, 32, %o1
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET1825
nop
RET1825:
! lfsr step begin
srlx %l0, 1, %l7
xnor %l7, %l0, %l7
sllx %l7, 63, %l7
or %l7, %l0, %l0
srlx %l0, 1, %l0
P1826: !_LD [9] (Int) (Loop exit) (Branch target of P1591)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %l3
! move %l3(lower) -> %o1(lower)
or %l3, %o1, %o1
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_2_270:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_270
nop
ba P1827
nop
TARGET1591:
ba RET1591
nop
P1827: !_DWLD [2] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_271:
ldx [%i0 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1828: !_BLD [18] (FP)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P1829: !_LD [19] (Int) (Loop exit) (LE)
wr %g0, 0x88, %asi
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduwa [%i2 + 32] %asi, %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_2_271:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_271
nop
P1830: !_BLD [22] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_272:
wr %g0, 0xf0, %asi
sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P1831: !_MEMBAR (Int) (Loop exit)
membar #StoreLoad
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_2_272:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_272
nop
P1832: !_LD [1] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_273:
lduw [%i0 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1833: !_LD [21] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_2_273:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_273
nop
P1834: !_LD [23] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_274:
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1835: !_LD [25] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_2_274:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_274
nop
P1836: !_DWLD [28] (Int) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_275:
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
ldx [%i3 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_2_275:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_275
nop
P1837: !_BLD [30] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_276:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P1838: !_BLD [10] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f32
membar #Sync
! 4 addresses covered
fmovd %f32, %f4
fmovd %f34, %f18
fmovs %f19, %f6
fmovd %f40, %f18
fmovs %f18, %f7
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovd %f4, %f30
fmovd %f6, %f30
!--
loop_exit_2_276:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_276
nop
P1839: !_BLD [10] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_277:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_2_277:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_277
nop
P1840: !_REPLACEMENT [20] (Int) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_278:
sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS3_O), %i3
sub %i0, %i3, %i3
sethi %hi(0x10000), %l7
ld [%i3+0], %l3
st %l3, [%i3+0]
add %i3, %l7, %o5
ld [%o5+0], %l3
st %l3, [%o5+0]
add %o5, %l7, %o5
ld [%o5+0], %l3
st %l3, [%o5+0]
add %o5, %l7, %o5
ld [%o5+0], %l3
st %l3, [%o5+0]
loop_exit_2_278:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_278
nop
P1841: !_BLD [18] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_279:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_2_279:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_279
nop
P1842: !_LD [25] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_280:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1843: !_LD [25] (Int) (Loop exit) (LE)
wr %g0, 0x88, %asi
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduwa [%i2 + 4] %asi, %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_2_280:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_280
nop
P1844: !_DWLD [12] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_281:
sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
ldx [%i3 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
P1845: !_DWLD [28] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 0], %o1
! move %o1(upper) -> %o1(upper)
! move %o1(lower) -> %o1(lower)
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_2_281:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_281
nop
P1846: !_DWLD [4] (Int) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_282:
ldx [%i1 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_2_282:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_282
nop
P1847: !_LD [11] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_283:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1848: !_DWLD [16] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 0], %o5
! move %o5(upper) -> %o0(lower)
srlx %o5, 32, %l7
or %l7, %o0, %o0
! move %o5(lower) -> %o1(upper)
sllx %o5, 32, %o1
P1849: !_LD [13] (Int) (Loop exit) (LE)
wr %g0, 0x88, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduwa [%i3 + 4] %asi, %l7
! move %l7(lower) -> %o1(lower)
or %l7, %o1, %o1
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_2_283:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_283
nop
P1850: !_LD [18] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_284:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1851: !_BLD [14] (FP)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P1852: !_LD [0] (Int) (Loop exit)
lduw [%i0 + 0], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_2_284:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_284
nop
P1853: !_LD [14] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_285:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1854: !_DWLD [26] (Int) (Loop exit)
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
ldx [%i3 + 8], %l7
! move %l7(lower) -> %o0(lower)
srl %l7, 0, %l6
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_2_285:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_285
nop
P1855: !_BLD [29] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_286:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P1856: !_BLD [31] (FP) (Loop exit)
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i2 + 0] %asi, %f32
membar #Sync
! 4 addresses covered
fmovd %f32, %f4
fmovd %f34, %f18
fmovs %f19, %f6
fmovd %f40, %f18
fmovs %f18, %f7
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovd %f4, %f30
fmovd %f6, %f30
!--
loop_exit_2_286:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_286
nop
P1857: !_ST [17] (maybe <- 0x4080003c) (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_287:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i3
sub %i0, %i3, %i3
! preparing store val #0, next val will be in f20
fmovs %f16, %f20
fadds %f16, %f17, %f16
st %f20, [%i3 + 4 ]
loop_exit_2_287:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_287
nop
P1858: !_LD [24] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_288:
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1859: !_LD [17] (Int) (Loop exit) (Branch target of P1583)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 4], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_2_288:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_288
nop
ba P1860
nop
TARGET1583:
ba RET1583
nop
P1860: !_DWLD [2] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_289:
ldx [%i0 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1861: !_LD [17] (Int) (Loop exit) (LE) (CBR)
wr %g0, 0x88, %asi
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduwa [%i2 + 4] %asi, %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET1861
nop
RET1861:
! lfsr step begin
srlx %l0, 1, %l7
xnor %l7, %l0, %l7
sllx %l7, 63, %l7
or %l7, %l0, %l0
srlx %l0, 1, %l0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_2_289:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_289
nop
P1862: !_BLD [23] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_290:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P1863: !_DWLD [7] (Int)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 7
sethi %hi(0xc0000), %l3
sub %i1, %l3, %i1
ldx [%i1 + 32], %o0
! move %o0(upper) -> %o0(upper)
P1864: !_LD [11] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 32], %l3
! move %l3(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
sethi %hi(0xc0000), %l6
add %i1, %l6, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_2_290:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_290
nop
P1865: !_LD [19] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_291:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1866: !_LD [14] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_2_291:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_291
nop
P1867: !_LD [23] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_292:
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
sub %i0, %i3, %i3
ld [%i3 + 32], %f0
! 1 addresses covered
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
loop_exit_2_292:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_292
nop
P1868: !_LD [2] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_293:
lduw [%i0 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1869: !_LD [5] (Int) (Loop exit) (Branch target of P1961)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 5
sethi %hi(0xc0000), %l3
sub %i1, %l3, %i1
lduw [%i1 + 4], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
sethi %hi(0xc0000), %o5
add %i1, %o5, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_2_293:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_293
nop
ba P1870
nop
TARGET1961:
ba RET1961
nop
P1870: !_BLD [15] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_294:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_2_294:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_294
nop
P1871: !_BLD [7] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_295:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 7
sethi %hi(0xc0000), %l6
sub %i1, %l6, %i1
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P1872: !_ST [7] (maybe <- 0x1000024) (Int) (Loop exit)
stw %l4, [%i1 + 32 ]
add %l4, 1, %l4
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
sethi %hi(0xc0000), %l6
add %i1, %l6, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_2_295:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_295
nop
P1873: !_LD [30] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_296:
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1874: !_DWLD [10] (Int) (Loop exit) (Branch target of P1816)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 8], %l7
! move %l7(lower) -> %o0(lower)
srl %l7, 0, %l6
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_2_296:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_296
nop
ba P1875
nop
TARGET1816:
ba RET1816
nop
P1875: !_DWLD [18] (Int) (Loop entry) (Branch target of P1567)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_297:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
ba P1876
nop
TARGET1567:
ba RET1567
nop
P1876: !_BLD [12] (FP)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P1877: !_LD [29] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 4], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_2_297:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_297
nop
P1878: !_BLD [5] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_298:
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P1879: !_DWLD [28] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_2_298:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_298
nop
P1880: !_LD [20] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_299:
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1881: !_BLD [8] (FP)
wr %g0, 0xf0, %asi
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P1882: !_LD [24] (Int) (Loop exit)
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 0], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_2_299:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_299
nop
P1883: !_DWLD [11] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_300:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i2
sub %i0, %i2, %i2
ldd [%i2 + 32], %f0
! 1 addresses covered
P1884: !_DWLD [28] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
loop_exit_2_300:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_300
nop
P1885: !_DWLD [28] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_301:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
P1886: !_LD [20] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %o1
! move %o1(lower) -> %o1(upper)
sllx %o1, 32, %o1
P1887: !_LD [11] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 32], %l3
! move %l3(lower) -> %o1(lower)
or %l3, %o1, %o1
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_2_301:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_301
nop
P1888: !_CASX [19] (maybe <- 0x1000025) (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_302:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i3
sub %i0, %i3, %i3
add %i3, 32, %o5
ldx [%o5], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
mov %o0, %l7
sllx %l4, 32, %o1
casx [%o5], %l7, %o1
! move %o1(upper) -> %o1(upper)
! move %o1(lower) -> %o1(lower)
add %l4, 1, %l4
P1889: !_REPLACEMENT [18] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS2_O), %i2
sub %i0, %i2, %i2
sethi %hi(0x10000), %o5
ld [%i2+12], %l6
st %l6, [%i2+12]
add %i2, %o5, %l3
ld [%l3+12], %l6
st %l6, [%l3+12]
add %l3, %o5, %l3
ld [%l3+12], %l6
st %l6, [%l3+12]
add %l3, %o5, %l3
ld [%l3+12], %l6
st %l6, [%l3+12]
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_2_302:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_302
nop
P1890: !_PREFETCH [13] (Int) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_303:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i3
sub %i0, %i3, %i3
prefetch [%i3 + 4], 1
loop_exit_2_303:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_303
nop
P1891: !_BLD [29] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_304:
wr %g0, 0xf0, %asi
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_2_304:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_304
nop
P1892: !_LD [20] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_305:
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1893: !_FLUSHI [18] (Int)
flush %g0
P1894: !_LD [0] (Int) (Loop exit)
lduw [%i0 + 0], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_2_305:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_305
nop
P1895: !_DWLD [1] (Int) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_306:
ldx [%i0 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_2_306:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_306
nop
P1896: !_DWLD [18] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_307:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1897: !_LD [19] (Int) (Loop exit)
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 32], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_2_307:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_307
nop
P1898: !_BLD [30] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_308:
wr %g0, 0xf0, %asi
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_2_308:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_308
nop
P1899: !_LD [22] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_309:
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1900: !_BLD [29] (FP)
wr %g0, 0xf0, %asi
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P1901: !_LD [8] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_2_309:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_309
nop
P1902: !_BSTC [15] (maybe <- 0x4080003d) (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_310:
wr %g0, 0xe0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i2
sub %i0, %i2, %i2
! preparing store val #0, next val will be in f32
fmovs %f16, %f20
fadds %f16, %f17, %f16
! preparing store val #1, next val will be in f33
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #2, next val will be in f35
fmovd %f20, %f32
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #3, next val will be in f40
fmovd %f20, %f34
fmovs %f16, %f20
fadds %f16, %f17, %f16
fmovd %f20, %f40
membar #Sync
stda %f32, [%i2 + 0 ] %asi
membar #Sync
P1903: !_BST [14] (maybe <- 0x40800041) (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
! preparing store val #0, next val will be in f32
fmovs %f16, %f20
fadds %f16, %f17, %f16
! preparing store val #1, next val will be in f33
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #2, next val will be in f35
fmovd %f20, %f32
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #3, next val will be in f40
fmovd %f20, %f34
fmovs %f16, %f20
fadds %f16, %f17, %f16
fmovd %f20, %f40
membar #Sync
stda %f32, [%i3 + 0 ] %asi
membar #Sync
loop_exit_2_310:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_310
nop
P1904: !_LD [22] (Int) (Loop entry) (CBR)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_311:
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET1904
nop
RET1904:
! lfsr step begin
srlx %l0, 1, %l3
xnor %l3, %l0, %l3
sllx %l3, 63, %l3
or %l3, %l0, %l0
srlx %l0, 1, %l0
P1905: !_LD [15] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_2_311:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_311
nop
P1906: !_BLD [29] (FP) (Loop entry) (Loop exit) (Branch target of P1959)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_312:
wr %g0, 0xf0, %asi
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_2_312:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_312
nop
ba P1907
nop
TARGET1959:
ba RET1959
nop
P1907: !_DWLD [18] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_313:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1908: !_LD [14] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_2_313:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_313
nop
P1909: !_DWLD [4] (Int) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_314:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 4
sethi %hi(0xc0000), %l3
sub %i1, %l3, %i1
ldx [%i1 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
sethi %hi(0xc0000), %o5
add %i1, %o5, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_2_314:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_314
nop
P1910: !_NOP (Int) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_315:
nop
loop_exit_2_315:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_315
nop
P1911: !_SWAP [22] (maybe <- 0x1000026) (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_316:
sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
mov %l4, %o0
swap [%i3 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
add %l4, 1, %l4
P1912: !_LD [10] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_2_316:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_316
nop
P1913: !_LD [0] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_317:
lduw [%i0 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1914: !_BLD [13] (FP)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P1915: !_LD [9] (Int) (Loop exit)
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 4], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_2_317:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_317
nop
P1916: !_DWLD [6] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_318:
ldx [%i1 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1917: !_LD [22] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_2_318:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_318
nop
P1918: !_LD [2] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_319:
lduw [%i0 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1919: !_LD [20] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 0], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_2_319:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_319
nop
P1920: !_LD [22] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_320:
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1921: !_DWLD [5] (FP)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 5
sethi %hi(0xc0000), %l6
sub %i1, %l6, %i1
ldd [%i1 + 0], %f0
! 2 addresses covered
P1922: !_LD [2] (Int) (Loop exit)
lduw [%i0 + 12], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
!--
sethi %hi(0xc0000), %l3
add %i1, %l3, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_2_320:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_320
nop
P1923: !_DWLD [25] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_321:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
sub %i0, %i2, %i2
ldd [%i2 + 0], %f0
! 2 addresses covered
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
!--
loop_exit_2_321:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_321
nop
P1924: !_BLD [28] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_322:
wr %g0, 0xf0, %asi
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_2_322:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_322
nop
P1925: !_BLD [29] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_323:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P1926: !_BLD [28] (FP) (Loop exit)
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i2 + 0] %asi, %f32
membar #Sync
! 4 addresses covered
fmovd %f32, %f4
fmovd %f34, %f18
fmovs %f19, %f6
fmovd %f40, %f18
fmovs %f18, %f7
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovd %f4, %f30
fmovd %f6, %f30
!--
loop_exit_2_323:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_323
nop
P1927: !_BLD [0] (FP) (Loop entry) (Loop exit) (CBR)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_324:
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i0 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET1927
nop
RET1927:
! lfsr step begin
srlx %l0, 1, %o5
xnor %o5, %l0, %o5
sllx %o5, 63, %o5
or %o5, %l0, %l0
srlx %l0, 1, %l0
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_2_324:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_324
nop
P1928: !_LD [10] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_325:
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1929: !_LD [28] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 0], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_2_325:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_325
nop
P1930: !_LD [1] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_326:
lduw [%i0 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1931: !_BLD [0] (FP) (Branch target of P1628)
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i0 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
ba P1932
nop
TARGET1628:
ba RET1628
nop
P1932: !_LD [18] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_2_326:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_326
nop
P1933: !_DWLD [12] (Int) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_327:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_2_327:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_327
nop
P1934: !_LD [31] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_328:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1935: !_DWLD [14] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 8], %l6
! move %l6(lower) -> %o0(lower)
srl %l6, 0, %l3
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_2_328:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_328
nop
P1936: !_BLD [29] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_329:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_2_329:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_329
nop
P1937: !_DWST [17] (maybe <- 0x1000027) (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_330:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i2
sub %i0, %i2, %i2
sllx %l4, 32, %l6
add %l4, 1, %l4
or %l6, %l4, %l6
stx %l6, [%i2 + 0]
add %l4, 1, %l4
P1938: !_LD [9] (Int)
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1939: !_LD [28] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 0], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_2_330:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_330
nop
P1940: !_DWLD [6] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_331:
ldx [%i1 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1941: !_LD [19] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_2_331:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_331
nop
P1942: !_REPLACEMENT [13] (Int) (Loop entry) (Loop exit) (Branch target of P1370)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_332:
sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
sethi %hi(0x10000), %l3
ld [%i2+4], %l7
st %l7, [%i2+4]
add %i2, %l3, %l6
ld [%l6+4], %l7
st %l7, [%l6+4]
add %l6, %l3, %l6
ld [%l6+4], %l7
st %l7, [%l6+4]
add %l6, %l3, %l6
ld [%l6+4], %l7
st %l7, [%l6+4]
loop_exit_2_332:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_332
nop
ba P1943
nop
TARGET1370:
ba RET1370
nop
P1943: !_LD [8] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_333:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1944: !_BST [10] (maybe <- 0x40800045) (FP)
wr %g0, 0xf0, %asi
! preparing store val #0, next val will be in f32
fmovs %f16, %f20
fadds %f16, %f17, %f16
! preparing store val #1, next val will be in f33
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #2, next val will be in f35
fmovd %f20, %f32
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #3, next val will be in f40
fmovd %f20, %f34
fmovs %f16, %f20
fadds %f16, %f17, %f16
fmovd %f20, %f40
membar #Sync
stda %f32, [%i3 + 0 ] %asi
membar #Sync
P1945: !_LD [19] (Int) (Loop exit)
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 32], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_2_333:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_333
nop
P1946: !_DWLD [19] (Int) (Loop entry) (LE)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_334:
wr %g0, 0x88, %asi
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
ldxa [%i3 + 32] %asi, %o5
! move %o5(lower) -> %o0(upper)
sllx %o5, 32, %o0
P1947: !_LD [4] (Int) (Loop exit)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 4
sethi %hi(0xc0000), %l3
sub %i1, %l3, %i1
lduw [%i1 + 0], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
sethi %hi(0xc0000), %o5
add %i1, %o5, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_2_334:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_334
nop
P1948: !_PREFETCH [29] (Int) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_335:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i2
sub %i0, %i2, %i2
prefetch [%i2 + 4], 1
loop_exit_2_335:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_335
nop
P1949: !_ST [15] (maybe <- 0x1000029) (Int) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_336:
sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
stw %l4, [%i3 + 32 ]
add %l4, 1, %l4
loop_exit_2_336:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_336
nop
P1950: !_LD [17] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_337:
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1951: !_LD [22] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_2_337:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_337
nop
P1952: !_DWLD [25] (Int) (Loop entry) (CBR)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_338:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET1952
nop
RET1952:
! lfsr step begin
srlx %l0, 1, %l7
xnor %l7, %l0, %l7
sllx %l7, 63, %l7
or %l7, %l0, %l0
srlx %l0, 1, %l0
P1953: !_ST [21] (maybe <- 0x100002a) (Int) (Loop exit) (CBR)
sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
stw %l4, [%i3 + 4 ]
add %l4, 1, %l4
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET1953
nop
RET1953:
! lfsr step begin
srlx %l0, 1, %o5
xnor %o5, %l0, %o5
sllx %o5, 63, %o5
or %o5, %l0, %l0
srlx %l0, 1, %l0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_2_338:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_338
nop
P1954: !_DWLD [6] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_339:
ldx [%i1 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1955: !_BLD [27] (FP)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P1956: !_LD [20] (Int) (Loop exit)
sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 0], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_2_339:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_339
nop
P1957: !_LD [14] (FP) (Loop entry) (CBR)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_340:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i2
sub %i0, %i2, %i2
ld [%i2 + 12], %f0
! 1 addresses covered
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET1957
nop
RET1957:
! lfsr step begin
srlx %l0, 1, %l3
xnor %l3, %l0, %l3
sllx %l3, 63, %l3
or %l3, %l0, %l0
srlx %l0, 1, %l0
P1958: !_REPLACEMENT [3] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS3_O), %i3
sub %i0, %i3, %i3
sethi %hi(0x10000), %l6
ld [%i3+32], %o5
st %o5, [%i3+32]
add %i3, %l6, %l7
ld [%l7+32], %o5
st %o5, [%l7+32]
add %l7, %l6, %l7
ld [%l7+32], %o5
st %o5, [%l7+32]
add %l7, %l6, %l7
ld [%l7+32], %o5
st %o5, [%l7+32]
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
loop_exit_2_340:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_340
nop
P1959: !_LD [6] (FP) (Loop entry) (Loop exit) (CBR) (Branch target of P1499)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_341:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 6
sethi %hi(0xc0000), %l6
sub %i1, %l6, %i1
ld [%i1 + 12], %f0
! 1 addresses covered
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET1959
nop
RET1959:
! lfsr step begin
srlx %l0, 1, %l7
xnor %l7, %l0, %l7
sllx %l7, 63, %l7
or %l7, %l0, %l0
srlx %l0, 1, %l0
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
sethi %hi(0xc0000), %o5
add %i1, %o5, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_2_341:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_341
nop
ba P1960
nop
TARGET1499:
ba RET1499
nop
P1960: !_LD [25] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_342:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1961: !_LD [4] (Int) (Loop exit) (CBR)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 4
sethi %hi(0xc0000), %l7
sub %i1, %l7, %i1
lduw [%i1 + 0], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET1961
nop
RET1961:
! lfsr step begin
srlx %l0, 1, %l6
xnor %l6, %l0, %l6
sllx %l6, 63, %l6
or %l6, %l0, %l0
srlx %l0, 1, %l0
!---- flushing int results buffer----
mov %o0, %l5
sethi %hi(0xc0000), %l7
add %i1, %l7, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_2_342:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_342
nop
P1962: !_DWLD [31] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_343:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 32], %o0
! move %o0(upper) -> %o0(upper)
P1963: !_LD [18] (Int) (Loop exit) (Branch target of P1861)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %o5
! move %o5(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_2_343:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_343
nop
ba P1964
nop
TARGET1861:
ba RET1861
nop
P1964: !_LD [20] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_344:
sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1965: !_LD [4] (Int) (Loop exit) (Branch target of P1418)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 4
sethi %hi(0xc0000), %o5
sub %i1, %o5, %i1
lduw [%i1 + 0], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
sethi %hi(0xc0000), %l7
add %i1, %l7, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_2_344:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_344
nop
ba P1966
nop
TARGET1418:
ba RET1418
nop
P1966: !_LD [13] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_2_345:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1967: !_LD [16] (FP)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i3
sub %i0, %i3, %i3
ld [%i3 + 0], %f0
! 1 addresses covered
P1968: !_LD [13] (Int) (Loop exit)
lduw [%i2 + 4], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
loop_exit_2_345:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_345
nop
P1969: !_LD [26] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_2_346:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1970: !_SWAP [4] (maybe <- 0x100002b) (Int) (Loop exit)
mov %l4, %l7
swap [%i1 + 0], %l7
! move %l7(lower) -> %o0(lower)
srl %l7, 0, %l3
or %l3, %o0, %o0
add %l4, 1, %l4
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_2_346:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_2_346
nop
P1971: !_MEMBAR (Int)
membar #StoreLoad
END_NODES2: ! Test instruction sequence for CPU 2 ends
sethi %hi(0xdead0e0f), %l6
or %l6, %lo(0xdead0e0f), %l6
! move %l6(lower) -> %o0(upper)
sllx %l6, 32, %o0
stw %l6, [%i5]
ld [%i5], %f0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
restore
retl
nop
!-----------------
! register usage:
! %i0 %i1 : base registers for first 2 regions
! %i2 %i3 : cache registers for 8 regions
! %i4 fixed pointer to per-cpu results area
! %l1 moving pointer to per-cpu FP results area
! %o7 moving pointer to per-cpu integer results area
! %i5 pointer to per-cpu private area
! %l0 holds lfsr, used as source of random bits
! %l2 loop count register
! %f16 running counter for unique fp store values
! %f17 holds increment value for fp counter
! %l4 running counter for unique integer store values (increment value is always 1)
! %l5 move-to register for load values (simulation only)
! %f30 move-to register for FP values (simulation only)
! %l3 %l6 %l7 %o5 : 4 temporary registers
! %o0 %o1 %o2 %o3 %o4 : 5 integer results buffer registers
! %f0-f15 FP results buffer registers
! %f32-f47 FP block load/store registers
func3:
! 1000 (dynamic) instruction sequence begins
save %sp, -192, %sp
! Force %i0-%i3 to be 64-byte aligned
add %i0, 63, %i0
andn %i0, 63, %i0
add %i1, 63, %i1
andn %i1, 63, %i1
add %i2, 63, %i2
andn %i2, 63, %i2
add %i3, 63, %i3
andn %i3, 63, %i3
add %i4, 63, %i4
andn %i4, 63, %i4
add %i5, 63, %i5
andn %i5, 63, %i5
! Initialize pointer to FP load results area
mov %i4, %l1
! Initialize pointer to integer load results area
sethi %hi(0x80000), %o7
or %o7, %lo(0x80000), %o7
add %o7, %l1, %o7
! Initialize %f0-%f62 to 0xdeadbee0deadbee1
sethi %hi(0xdeadbee0), %l3
or %l3, %lo(0xdeadbee0), %l3
stw %l3, [%i5]
sethi %hi(0xdeadbee1), %l3
or %l3, %lo(0xdeadbee1), %l3
stw %l3, [%i5+4]
ldd [%i5], %f0
fmovd %f0, %f2
fmovd %f0, %f4
fmovd %f0, %f6
fmovd %f0, %f8
fmovd %f0, %f10
fmovd %f0, %f12
fmovd %f0, %f14
fmovd %f0, %f16
fmovd %f0, %f18
fmovd %f0, %f20
fmovd %f0, %f22
fmovd %f0, %f24
fmovd %f0, %f26
fmovd %f0, %f28
fmovd %f0, %f30
fmovd %f0, %f32
fmovd %f0, %f34
fmovd %f0, %f36
fmovd %f0, %f38
fmovd %f0, %f40
fmovd %f0, %f42
fmovd %f0, %f44
fmovd %f0, %f46
fmovd %f0, %f48
fmovd %f0, %f50
fmovd %f0, %f52
fmovd %f0, %f54
fmovd %f0, %f56
fmovd %f0, %f58
fmovd %f0, %f60
fmovd %f0, %f62
! Signature for extract_loads script to start extracting load values for this stream
sethi %hi(0x03deade1), %l3
or %l3, %lo(0x03deade1), %l3
stw %l3, [%i5]
ld [%i5], %f16
! Initialize running integer counter in register %l4
sethi %hi(0x1800001), %l4
or %l4, %lo(0x1800001), %l4
! Initialize running FP counter in register %f16
sethi %hi(0x41000001), %l3
or %l3, %lo(0x41000001), %l3
stw %l3, [%i5]
ld [%i5], %f16
! Initialize FP counter increment value in register %f17 (constant)
sethi %hi(0x35800000), %l3
or %l3, %lo(0x35800000), %l3
stw %l3, [%i5]
ld [%i5], %f17
! Initialize LFSR to 0x2285^4
sethi %hi(0x2285), %l0
or %l0, %lo(0x2285), %l0
mulx %l0, %l0, %l0
mulx %l0, %l0, %l0
BEGIN_NODES3: ! Test instruction sequence for CPU 3 begins
P1972: !_LD [28] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_0:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1973: !_BLD [24] (FP)
wr %g0, 0xf0, %asi
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P1974: !_LD [9] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 4], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_3_0:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_0
nop
P1975: !_DWLD [19] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_1:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 32], %o0
! move %o0(upper) -> %o0(upper)
P1976: !_DWLD [27] (Int) (Loop exit)
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
ldx [%i3 + 32], %l3
! move %l3(upper) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
srlx %l3, 32, %o5
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_3_1:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_1
nop
P1977: !_LD [7] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_2:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 7
sethi %hi(0xc0000), %l7
sub %i1, %l7, %i1
lduw [%i1 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1978: !_BLD [0] (FP)
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i0 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P1979: !_LD [6] (Int) (Loop exit)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #2
!Logical addr: 6
sethi %hi(0xc0000), %l6
sub %i1, %l6, %i1
lduw [%i1 + 12], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
sethi %hi(0x180000), %l3
add %i1, %l3, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_3_2:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_2
nop
P1980: !_DWLD [11] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_3:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 32], %o0
! move %o0(upper) -> %o0(upper)
P1981: !_BLD [19] (FP)
wr %g0, 0xf0, %asi
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P1982: !_LD [0] (Int) (Loop exit)
lduw [%i0 + 0], %l6
! move %l6(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_3_3:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_3
nop
P1983: !_BLD [15] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_4:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P1984: !_LD [16] (Int)
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1985: !_LD [6] (Int) (Loop exit)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 6
sethi %hi(0xc0000), %l7
sub %i1, %l7, %i1
lduw [%i1 + 12], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
sethi %hi(0xc0000), %l6
add %i1, %l6, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_3_4:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_4
nop
P1986: !_DWLD [4] (Int) (Loop entry) (Loop exit) (CBR)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_5:
ldx [%i1 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET1986
nop
RET1986:
! lfsr step begin
srlx %l0, 1, %l3
xnor %l3, %l0, %l3
sllx %l3, 63, %l3
or %l3, %l0, %l0
srlx %l0, 1, %l0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_3_5:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_5
nop
P1987: !_BLD [24] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_6:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P1988: !_DWLD [3] (Int) (LE)
wr %g0, 0x88, %asi
ldxa [%i0 + 32] %asi, %l3
! move %l3(lower) -> %o0(upper)
sllx %l3, 32, %o0
P1989: !_LD [20] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_3_6:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_6
nop
P1990: !_LD [29] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_7:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1991: !_LD [12] (FP)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i3
sub %i0, %i3, %i3
ld [%i3 + 0], %f0
! 1 addresses covered
P1992: !_LD [31] (Int) (Loop exit)
lduw [%i2 + 32], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
loop_exit_3_7:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_7
nop
P1993: !_BLD [24] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_8:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_3_8:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_8
nop
P1994: !_LD [5] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_9:
lduw [%i1 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1995: !_ST [23] (maybe <- 0x1800001) (Int)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
sub %i0, %i3, %i3
stw %l4, [%i3 + 32 ]
add %l4, 1, %l4
P1996: !_LD [0] (Int) (Loop exit)
lduw [%i0 + 0], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_3_9:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_9
nop
P1997: !_LD [20] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_10:
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P1998: !_BLD [26] (FP)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P1999: !_LD [2] (Int) (Loop exit)
lduw [%i0 + 12], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_3_10:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_10
nop
P2000: !_DWLD [23] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_11:
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 32], %o0
! move %o0(upper) -> %o0(upper)
P2001: !_LD [7] (Int) (Loop exit)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 7
sethi %hi(0xc0000), %o5
sub %i1, %o5, %i1
lduw [%i1 + 32], %l6
! move %l6(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
sethi %hi(0xc0000), %l7
add %i1, %l7, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_3_11:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_11
nop
P2002: !_DWLD [28] (Int) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_12:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_3_12:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_12
nop
P2003: !_SWAP [30] (maybe <- 0x1800002) (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_13:
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
mov %l4, %o0
swap [%i2 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
add %l4, 1, %l4
P2004: !_LD [8] (Int) (Loop exit) (Branch target of P2432)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_3_13:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_13
nop
ba P2005
nop
TARGET2432:
ba RET2432
nop
P2005: !_SWAP [11] (maybe <- 0x1800003) (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_14:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
sub %i0, %i2, %i2
mov %l4, %o0
swap [%i2 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
add %l4, 1, %l4
P2006: !_LD [26] (Int) (Loop exit) (CBR)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET2006
nop
RET2006:
! lfsr step begin
srlx %l0, 1, %o5
xnor %o5, %l0, %o5
sllx %o5, 63, %o5
or %o5, %l0, %l0
srlx %l0, 1, %l0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_3_14:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_14
nop
P2007: !_LD [0] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_15:
lduw [%i0 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2008: !_LD [18] (Int) (Loop exit) (Branch target of P2385)
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 12], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_3_15:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_15
nop
ba P2009
nop
TARGET2385:
ba RET2385
nop
P2009: !_LD [4] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_16:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 4
sethi %hi(0xc0000), %o5
sub %i1, %o5, %i1
ld [%i1 + 0], %f0
! 1 addresses covered
P2010: !_BLD [9] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f32
membar #Sync
! 4 addresses covered
fmovd %f32, %f18
fmovs %f18, %f1
fmovs %f19, %f2
fmovd %f34, %f18
fmovs %f19, %f3
fmovd %f40, %f4
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovs %f4, %f30
!--
sethi %hi(0xc0000), %l3
add %i1, %l3, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_3_16:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_16
nop
P2011: !_NOP (Int) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_17:
nop
loop_exit_3_17:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_17
nop
P2012: !_BLD [23] (FP) (Loop entry) (Branch target of P2441)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_18:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
ba P2013
nop
TARGET2441:
ba RET2441
nop
P2013: !_DWLD [28] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_3_18:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_18
nop
P2014: !_DWLD [25] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_19:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
P2015: !_LD [7] (Int)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 7
sethi %hi(0xc0000), %l6
sub %i1, %l6, %i1
lduw [%i1 + 32], %o1
! move %o1(lower) -> %o1(upper)
sllx %o1, 32, %o1
P2016: !_LD [18] (Int) (Loop exit)
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 12], %l6
! move %l6(lower) -> %o1(lower)
or %l6, %o1, %o1
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
sethi %hi(0xc0000), %l7
add %i1, %l7, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_3_19:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_19
nop
P2017: !_DWST [22] (maybe <- 0x1800004) (Int) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_20:
sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
mov %l4, %l3
stx %l3, [%i2 + 8]
add %l4, 1, %l4
loop_exit_3_20:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_20
nop
P2018: !_LD [16] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_21:
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2019: !_LD [23] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 32], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_3_21:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_21
nop
P2020: !_DWLD [15] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_22:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 32], %o0
! move %o0(upper) -> %o0(upper)
P2021: !_DWLD [19] (FP)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
sub %i0, %i2, %i2
ldd [%i2 + 32], %f0
! 1 addresses covered
P2022: !_LD [28] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %l7
! move %l7(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
loop_exit_3_22:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_22
nop
P2023: !_DWST [2] (maybe <- 0x1800005) (Int) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_23:
mov %l4, %l6
stx %l6, [%i0 + 8]
add %l4, 1, %l4
loop_exit_3_23:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_23
nop
P2024: !_LD [18] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_24:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2025: !_LD [0] (Int) (Loop exit)
lduw [%i0 + 0], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_3_24:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_24
nop
P2026: !_LD [1] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_25:
lduw [%i0 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2027: !_MEMBAR (Int)
membar #StoreLoad
P2028: !_LD [0] (Int) (Loop exit)
lduw [%i0 + 0], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_3_25:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_25
nop
P2029: !_LD [17] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_26:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2030: !_LD [10] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_3_26:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_26
nop
P2031: !_REPLACEMENT [8] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_27:
sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS1_O), %i3
sub %i0, %i3, %i3
sethi %hi(0x10000), %l3
ld [%i3+0], %l7
st %l7, [%i3+0]
add %i3, %l3, %l6
ld [%l6+0], %l7
st %l7, [%l6+0]
add %l6, %l3, %l6
ld [%l6+0], %l7
st %l7, [%l6+0]
add %l6, %l3, %l6
ld [%l6+0], %l7
st %l7, [%l6+0]
P2032: !_DWLD [8] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_3_27:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_27
nop
P2033: !_DWLD [5] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_28:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 5
sethi %hi(0xc0000), %l7
sub %i1, %l7, %i1
ldx [%i1 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
P2034: !_BLD [28] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
sethi %hi(0xc0000), %l6
add %i1, %l6, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_3_28:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_28
nop
P2035: !_BLD [18] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_29:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P2036: !_NOP (Int) (Loop exit)
nop
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_3_29:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_29
nop
P2037: !_LD [29] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_30:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2038: !_LD [23] (Int) (Loop exit) (Branch target of P2455)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 32], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_3_30:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_30
nop
ba P2039
nop
TARGET2455:
ba RET2455
nop
P2039: !_BLD [7] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_31:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 7
sethi %hi(0xc0000), %l7
sub %i1, %l7, %i1
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
sethi %hi(0xc0000), %o5
add %i1, %o5, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_3_31:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_31
nop
P2040: !_DWLD [12] (Int) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_32:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_3_32:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_32
nop
P2041: !_DWLD [1] (Int) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_33:
ldx [%i0 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_3_33:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_33
nop
P2042: !_BSTC [20] (maybe <- 0x41000001) (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_34:
wr %g0, 0xe0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i2
sub %i0, %i2, %i2
! preparing store val #0, next val will be in f32
fmovs %f16, %f20
fadds %f16, %f17, %f16
! preparing store val #1, next val will be in f33
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #2, next val will be in f35
fmovd %f20, %f32
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #3, next val will be in f40
fmovd %f20, %f34
fmovs %f16, %f20
fadds %f16, %f17, %f16
fmovd %f20, %f40
membar #Sync
stda %f32, [%i2 + 0 ] %asi
membar #Sync
loop_exit_3_34:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_34
nop
P2043: !_DWLD [18] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_35:
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
ldd [%i3 + 8], %f0
! 1 addresses covered
fmovs %f1, %f0
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
loop_exit_3_35:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_35
nop
P2044: !_LD [16] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_36:
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2045: !_LD [21] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 4], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_3_36:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_36
nop
P2046: !_DWLD [23] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_37:
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 32], %o0
! move %o0(upper) -> %o0(upper)
P2047: !_LD [19] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %o5
! move %o5(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_3_37:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_37
nop
P2048: !_CASX [15] (maybe <- 0x1800006) (Int) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_38:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i2
sub %i0, %i2, %i2
add %i2, 32, %l7
ldx [%l7], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
mov %o0, %l6
sllx %l4, 32, %o1
casx [%l7], %l6, %o1
! move %o1(upper) -> %o1(upper)
! move %o1(lower) -> %o1(lower)
add %l4, 1, %l4
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_3_38:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_38
nop
P2049: !_LD [12] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_39:
sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2050: !_BLD [12] (FP)
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P2051: !_LD [9] (Int) (Loop exit) (LE)
wr %g0, 0x88, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduwa [%i2 + 4] %asi, %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_3_39:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_39
nop
P2052: !_LD [18] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_40:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2053: !_LD [7] (Int) (Loop exit)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 7
sethi %hi(0xc0000), %o5
sub %i1, %o5, %i1
lduw [%i1 + 32], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
sethi %hi(0xc0000), %l7
add %i1, %l7, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_3_40:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_40
nop
P2054: !_LD [22] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_41:
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2055: !_LD [26] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_3_41:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_41
nop
P2056: !_BLD [6] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_42:
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P2057: !_ST [13] (maybe <- 0x1800007) (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i2
sub %i0, %i2, %i2
stw %l4, [%i2 + 4 ]
add %l4, 1, %l4
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_3_42:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_42
nop
P2058: !_MEMBAR (Int) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_43:
membar #StoreLoad
loop_exit_3_43:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_43
nop
P2059: !_LD [20] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_44:
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i3
sub %i0, %i3, %i3
ld [%i3 + 0], %f0
! 1 addresses covered
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
loop_exit_3_44:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_44
nop
P2060: !_DWLD [11] (Int) (Loop entry) (CBR)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_45:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 32], %o0
! move %o0(upper) -> %o0(upper)
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET2060
nop
RET2060:
! lfsr step begin
srlx %l0, 1, %o5
xnor %o5, %l0, %o5
sllx %o5, 63, %o5
or %o5, %l0, %l0
srlx %l0, 1, %l0
P2061: !_LD [9] (Int) (Loop exit)
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 4], %l7
! move %l7(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_3_45:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_45
nop
P2062: !_LD [5] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_46:
lduw [%i1 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2063: !_BLD [25] (FP)
wr %g0, 0xf0, %asi
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P2064: !_LD [0] (Int) (Loop exit)
lduw [%i0 + 0], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_3_46:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_46
nop
P2065: !_DWLD [4] (Int) (Loop entry) (Branch target of P2296)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_47:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 4
sethi %hi(0xc0000), %l7
sub %i1, %l7, %i1
ldx [%i1 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
ba P2066
nop
TARGET2296:
ba RET2296
nop
P2066: !_BLD [6] (FP) (Loop exit)
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
sethi %hi(0xc0000), %l6
add %i1, %l6, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_3_47:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_47
nop
P2067: !_DWLD [24] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_48:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
P2068: !_DWLD [19] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 32], %o1
! move %o1(upper) -> %o1(upper)
P2069: !_LD [27] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %l6
! move %l6(lower) -> %o1(lower)
srlx %o1, 32, %o1
sllx %o1, 32, %o1
or %l6, %o1, %o1
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_3_48:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_48
nop
P2070: !_MEMBAR (Int) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_49:
membar #StoreLoad
loop_exit_3_49:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_49
nop
P2071: !_SWAP [29] (maybe <- 0x1800008) (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_50:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i2
sub %i0, %i2, %i2
mov %l4, %o0
swap [%i2 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
add %l4, 1, %l4
P2072: !_BLD [1] (FP)
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i0 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P2073: !_LD [18] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_3_50:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_50
nop
P2074: !_LD [26] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_51:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2075: !_ST [4] (maybe <- 0x1800009) (Int)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 4
sethi %hi(0xc0000), %l7
sub %i1, %l7, %i1
stw %l4, [%i1 + 0 ]
add %l4, 1, %l4
P2076: !_LD [17] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 4], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
sethi %hi(0xc0000), %l3
add %i1, %l3, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_3_51:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_51
nop
P2077: !_ST [8] (maybe <- 0x180000a) (Int) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_52:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i2
sub %i0, %i2, %i2
stw %l4, [%i2 + 0 ]
add %l4, 1, %l4
loop_exit_3_52:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_52
nop
P2078: !_LD [29] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_53:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2079: !_FLUSHI [5] (Int)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 5
sethi %hi(0xc0000), %l3
sub %i1, %l3, %i1
flush %g0
P2080: !_LD [24] (Int) (Loop exit) (LE)
wr %g0, 0x88, %asi
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduwa [%i2 + 0] %asi, %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
sethi %hi(0xc0000), %o5
add %i1, %o5, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_3_53:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_53
nop
P2081: !_BLD [8] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_54:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_3_54:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_54
nop
P2082: !_BLD [12] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_55:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P2083: !_CASX [15] (maybe <- 0x180000b) (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i3
sub %i0, %i3, %i3
add %i3, 32, %l3
ldx [%l3], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
mov %o0, %o5
sllx %l4, 32, %o1
casx [%l3], %o5, %o1
! move %o1(upper) -> %o1(upper)
! move %o1(lower) -> %o1(lower)
add %l4, 1, %l4
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_3_55:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_55
nop
P2084: !_BLD [20] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_56:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P2085: !_DWLD [28] (Int) (Loop exit)
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
ldx [%i3 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_3_56:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_56
nop
P2086: !_DWLD [30] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_57:
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
ldx [%i2 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2087: !_BLD [10] (FP)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P2088: !_LD [3] (Int) (Loop exit)
lduw [%i0 + 32], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_3_57:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_57
nop
P2089: !_BLD [13] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_58:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P2090: !_BLD [2] (FP) (Loop exit)
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i0 + 0] %asi, %f32
membar #Sync
! 4 addresses covered
fmovd %f32, %f4
fmovd %f34, %f18
fmovs %f19, %f6
fmovd %f40, %f18
fmovs %f18, %f7
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovd %f4, %f30
fmovd %f6, %f30
!--
loop_exit_3_58:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_58
nop
P2091: !_BLD [11] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_59:
wr %g0, 0xf0, %asi
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P2092: !_LD [2] (Int)
lduw [%i0 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2093: !_LD [28] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 0], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_3_59:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_59
nop
P2094: !_PREFETCH [0] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_60:
prefetch [%i0 + 0], 1
P2095: !_BLD [12] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_3_60:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_60
nop
P2096: !_LD [23] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_61:
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2097: !_DWLD [19] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 32], %l6
! move %l6(upper) -> %o0(lower)
srlx %l6, 32, %l3
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_3_61:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_61
nop
P2098: !_DWLD [27] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_62:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 32], %o0
! move %o0(upper) -> %o0(upper)
P2099: !_LD [15] (Int) (Loop exit) (CBR)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %o5
! move %o5(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %o5, %o0, %o0
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET2099
nop
RET2099:
! lfsr step begin
srlx %l0, 1, %l3
xnor %l3, %l0, %l3
sllx %l3, 63, %l3
or %l3, %l0, %l0
srlx %l0, 1, %l0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_3_62:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_62
nop
P2100: !_LD [13] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_63:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2101: !_NOP (Int)
nop
P2102: !_LD [28] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_3_63:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_63
nop
P2103: !_DWLD [2] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_64:
ldx [%i0 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2104: !_LD [1] (Int) (Loop exit)
lduw [%i0 + 4], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_3_64:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_64
nop
P2105: !_BLD [14] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_65:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P2106: !_BLD [28] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f32
membar #Sync
! 4 addresses covered
fmovd %f32, %f4
fmovd %f34, %f18
fmovs %f19, %f6
fmovd %f40, %f18
fmovs %f18, %f7
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovd %f4, %f30
fmovd %f6, %f30
!--
loop_exit_3_65:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_65
nop
P2107: !_CASX [21] (maybe <- 0x180000c) (Int) (Loop entry) (LE)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_66:
sllx %l4, 32, %l7
add %l4, 1, %l4
or %l4, %l7, %l7
! Change double-word-level endianess (big endian <-> little endian)
sethi %hi(0xff00ff00), %l6
or %l6, %lo(0xff00ff00), %l6
sllx %l6, 32, %o5
or %l6, %o5, %l6
and %l7, %l6, %o5
srlx %o5, 8, %o5
sllx %l7, 8, %l7
and %l7, %l6, %l7
or %l7, %o5, %l7
sethi %hi(0xffff0000), %l6
srlx %l7, 16, %o5
andn %o5, %l6, %o5
andn %l7, %l6, %l7
sllx %l7, 16, %l7
or %l7, %o5, %l7
srlx %l7, 32, %o5
sllx %l7, 32, %l7
or %l7, %o5, %o5
wr %g0, 0x88, %asi
sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
ldxa [%i2] %asi, %l3
! move %l3(lower) -> %o0(upper)
sllx %l3, 32, %o0
! move %l3(upper) -> %o0(lower)
srlx %l3, 32, %l6
or %l6, %o0, %o0
mov %l3, %l6
mov %o5, %l3
casxa [%i2] %asi, %l6, %l3
! move %l3(lower) -> %o1(upper)
sllx %l3, 32, %o1
! move %l3(upper) -> %o1(lower)
srlx %l3, 32, %l6
or %l6, %o1, %o1
add %l4, 1, %l4
P2108: !_DWLD [3] (Int)
ldx [%i0 + 32], %o2
! move %o2(upper) -> %o2(upper)
P2109: !_LD [8] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %l6
! move %l6(lower) -> %o2(lower)
srlx %o2, 32, %o2
sllx %o2, 32, %o2
or %l6, %o2, %o2
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
mov %o2, %l5
loop_exit_3_66:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_66
nop
P2110: !_DWLD [27] (Int) (Loop entry) (LE)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_67:
wr %g0, 0x88, %asi
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i2
sub %i0, %i2, %i2
ldxa [%i2 + 32] %asi, %l3
! move %l3(lower) -> %o0(upper)
sllx %l3, 32, %o0
P2111: !_LD [2] (Int) (Loop exit)
lduw [%i0 + 12], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_3_67:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_67
nop
P2112: !_DWLD [30] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_68:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2113: !_LD [8] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 0], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_3_68:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_68
nop
P2114: !_CAS [15] (maybe <- 0x180000e) (Int) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_69:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i3
sub %i0, %i3, %i3
add %i3, 32, %l3
lduw [%l3], %o0
mov %o0, %o5
! move %o5(lower) -> %o0(upper)
sllx %o5, 32, %o0
mov %l4, %l7
cas [%l3], %o5, %l7
! move %l7(lower) -> %o0(lower)
srl %l7, 0, %o5
or %o5, %o0, %o0
add %l4, 1, %l4
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_3_69:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_69
nop
P2115: !_BLD [9] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_70:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_3_70:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_70
nop
P2116: !_DWLD [3] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_71:
ldx [%i0 + 32], %o0
! move %o0(upper) -> %o0(upper)
P2117: !_BLD [9] (FP) (CBR)
wr %g0, 0xf0, %asi
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET2117
nop
RET2117:
! lfsr step begin
srlx %l0, 1, %l6
xnor %l6, %l0, %l6
sllx %l6, 63, %l6
or %l6, %l0, %l0
srlx %l0, 1, %l0
P2118: !_LD [25] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %o5
! move %o5(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_3_71:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_71
nop
P2119: !_LD [8] (Int) (Loop entry) (CBR)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_72:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET2119
nop
RET2119:
! lfsr step begin
srlx %l0, 1, %l3
xnor %l3, %l0, %l3
sllx %l3, 63, %l3
or %l3, %l0, %l0
srlx %l0, 1, %l0
P2120: !_LD [3] (Int) (Loop exit)
lduw [%i0 + 32], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_3_72:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_72
nop
P2121: !_LD [8] (Int) (Loop entry) (LE)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_73:
wr %g0, 0x88, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduwa [%i2 + 0] %asi, %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2122: !_BLD [27] (FP)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P2123: !_LD [18] (Int) (Loop exit)
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 12], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_3_73:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_73
nop
P2124: !_LD [9] (Int) (Loop entry) (CBR)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_74:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET2124
nop
RET2124:
! lfsr step begin
srlx %l0, 1, %l6
xnor %l6, %l0, %l6
sllx %l6, 63, %l6
or %l6, %l0, %l0
srlx %l0, 1, %l0
P2125: !_DWLD [10] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 8], %l3
! move %l3(lower) -> %o0(lower)
srl %l3, 0, %o5
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_3_74:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_74
nop
P2126: !_DWLD [4] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_75:
ldx [%i1 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
P2127: !_BLD [5] (FP) (Loop exit)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 5
sethi %hi(0xc0000), %l3
sub %i1, %l3, %i1
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
sethi %hi(0xc0000), %l6
add %i1, %l6, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_3_75:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_75
nop
P2128: !_BLD [29] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_76:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P2129: !_BLD [11] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f32
membar #Sync
! 4 addresses covered
fmovd %f32, %f4
fmovd %f34, %f18
fmovs %f19, %f6
fmovd %f40, %f18
fmovs %f18, %f7
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovd %f4, %f30
fmovd %f6, %f30
!--
loop_exit_3_76:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_76
nop
P2130: !_CAS [27] (maybe <- 0x180000f) (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_77:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i3
sub %i0, %i3, %i3
add %i3, 32, %l6
lduw [%l6], %o0
mov %o0, %l3
! move %l3(lower) -> %o0(upper)
sllx %l3, 32, %o0
mov %l4, %o5
cas [%l6], %l3, %o5
! move %o5(lower) -> %o0(lower)
srl %o5, 0, %l3
or %l3, %o0, %o0
add %l4, 1, %l4
P2131: !_DWLD [1] (Int) (Loop exit)
ldx [%i0 + 0], %o1
! move %o1(upper) -> %o1(upper)
! move %o1(lower) -> %o1(lower)
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_3_77:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_77
nop
P2132: !_DWLD [7] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_78:
ldx [%i1 + 32], %o0
! move %o0(upper) -> %o0(upper)
P2133: !_DWLD [24] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 0], %l3
! move %l3(upper) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
srlx %l3, 32, %o5
or %o5, %o0, %o0
! move %l3(lower) -> %o1(upper)
sllx %l3, 32, %o1
P2134: !_LD [1] (Int) (Loop exit)
lduw [%i0 + 4], %l7
! move %l7(lower) -> %o1(lower)
or %l7, %o1, %o1
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_3_78:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_78
nop
P2135: !_BLD [8] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_79:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_3_79:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_79
nop
P2136: !_CAS [6] (maybe <- 0x1800010) (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_80:
add %i1, 12, %o5
lduw [%o5], %o0
mov %o0, %l7
! move %l7(lower) -> %o0(upper)
sllx %l7, 32, %o0
mov %l4, %l6
cas [%o5], %l7, %l6
! move %l6(lower) -> %o0(lower)
srl %l6, 0, %l7
or %l7, %o0, %o0
add %l4, 1, %l4
P2137: !_ST [7] (maybe <- 0x1800011) (Int) (Loop exit) (LE)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 7
sethi %hi(0xc0000), %l7
sub %i1, %l7, %i1
wr %g0, 0x88, %asi
! Change single-word-level endianess (big endian <-> little endian)
sethi %hi(0xff00ff00), %l3
or %l3, %lo(0xff00ff00), %l3
and %l4, %l3, %l6
srl %l6, 8, %l6
sll %l4, 8, %o5
and %o5, %l3, %o5
or %o5, %l6, %o5
srl %o5, 16, %l6
sll %o5, 16, %o5
srl %o5, 0, %o5
or %o5, %l6, %o5
stwa %o5, [%i1 + 32] %asi
add %l4, 1, %l4
!---- flushing int results buffer----
mov %o0, %l5
sethi %hi(0xc0000), %l7
add %i1, %l7, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_3_80:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_80
nop
P2138: !_LD [19] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_81:
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2139: !_MEMBAR (Int)
membar #StoreLoad
P2140: !_LD [14] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_3_81:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_81
nop
P2141: !_LD [18] (Int) (Loop entry) (LE)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_82:
wr %g0, 0x88, %asi
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduwa [%i2 + 12] %asi, %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2142: !_DWLD [27] (FP)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i3
sub %i0, %i3, %i3
ldd [%i3 + 32], %f0
! 1 addresses covered
P2143: !_LD [13] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
loop_exit_3_82:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_82
nop
P2144: !_CASX [16] (maybe <- 0x1800012) (Int) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_83:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
sub %i0, %i3, %i3
ldx [%i3], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
mov %o0, %l3
sllx %l4, 32, %o1
add %l4, 1, %l4
or %l4, %o1, %o1
casx [%i3], %l3, %o1
! move %o1(upper) -> %o1(upper)
! move %o1(lower) -> %o1(lower)
add %l4, 1, %l4
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_3_83:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_83
nop
P2145: !_BLD [26] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_84:
wr %g0, 0xf0, %asi
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P2146: !_BLD [23] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f32
membar #Sync
! 4 addresses covered
fmovd %f32, %f4
fmovd %f34, %f18
fmovs %f19, %f6
fmovd %f40, %f18
fmovs %f18, %f7
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovd %f4, %f30
fmovd %f6, %f30
!--
loop_exit_3_84:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_84
nop
P2147: !_BLD [2] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_85:
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i0 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_3_85:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_85
nop
P2148: !_DWLD [2] (Int) (Loop entry) (Branch target of P2375)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_86:
ldx [%i0 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
ba P2149
nop
TARGET2375:
ba RET2375
nop
P2149: !_LD [27] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 32], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_3_86:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_86
nop
P2150: !_LD [2] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_87:
lduw [%i0 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2151: !_DWLD [28] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 0], %o5
! move %o5(upper) -> %o0(lower)
srlx %o5, 32, %l7
or %l7, %o0, %o0
! move %o5(lower) -> %o1(upper)
sllx %o5, 32, %o1
P2152: !_LD [27] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 32], %l6
! move %l6(lower) -> %o1(lower)
or %l6, %o1, %o1
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_3_87:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_87
nop
P2153: !_BLD [25] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_88:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_3_88:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_88
nop
P2154: !_BLD [8] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_89:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P2155: !_LD [6] (Int)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 6
sethi %hi(0xc0000), %l6
sub %i1, %l6, %i1
lduw [%i1 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2156: !_LD [20] (Int) (Loop exit)
sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 0], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
sethi %hi(0xc0000), %l7
add %i1, %l7, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_3_89:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_89
nop
P2157: !_DWLD [18] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_90:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2158: !_BLD [8] (FP)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P2159: !_LD [7] (Int) (Loop exit) (Branch target of P2418)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 7
sethi %hi(0xc0000), %l7
sub %i1, %l7, %i1
lduw [%i1 + 32], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
sethi %hi(0xc0000), %l6
add %i1, %l6, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_3_90:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_90
nop
ba P2160
nop
TARGET2418:
ba RET2418
nop
P2160: !_BLD [30] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_91:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P2161: !_LD [26] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2162: !_LD [11] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 32], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_3_91:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_91
nop
P2163: !_DWLD [17] (Int) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_92:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_3_92:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_92
nop
P2164: !_LD [28] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_93:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2165: !_LD [1] (Int) (Loop exit)
lduw [%i0 + 4], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_3_93:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_93
nop
P2166: !_BLD [2] (FP) (Loop entry) (Branch target of P2060)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_94:
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i0 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
ba P2167
nop
TARGET2060:
ba RET2060
nop
P2167: !_DWLD [7] (Int)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 7
sethi %hi(0xc0000), %l7
sub %i1, %l7, %i1
ldx [%i1 + 32], %o0
! move %o0(upper) -> %o0(upper)
P2168: !_LD [13] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 4], %l7
! move %l7(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
sethi %hi(0xc0000), %o5
add %i1, %o5, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_3_94:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_94
nop
P2169: !_BLD [23] (FP) (Loop entry) (Branch target of P2436)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_95:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
ba P2170
nop
TARGET2436:
ba RET2436
nop
P2170: !_BLD [16] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f32
membar #Sync
! 4 addresses covered
fmovd %f32, %f4
fmovd %f34, %f18
fmovs %f19, %f6
fmovd %f40, %f18
fmovs %f18, %f7
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovd %f4, %f30
fmovd %f6, %f30
!--
loop_exit_3_95:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_95
nop
P2171: !_BLD [30] (FP) (Loop entry) (CBR)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_96:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET2171
nop
RET2171:
! lfsr step begin
srlx %l0, 1, %o5
xnor %o5, %l0, %o5
sllx %o5, 63, %o5
or %o5, %l0, %l0
srlx %l0, 1, %l0
P2172: !_BLD [13] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f32
membar #Sync
! 4 addresses covered
fmovd %f32, %f4
fmovd %f34, %f18
fmovs %f19, %f6
fmovd %f40, %f18
fmovs %f18, %f7
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovd %f4, %f30
fmovd %f6, %f30
!--
loop_exit_3_96:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_96
nop
P2173: !_LD [30] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_97:
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2174: !_LD [20] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_3_97:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_97
nop
P2175: !_LD [29] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_98:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2176: !_LD [19] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_3_98:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_98
nop
P2177: !_LD [27] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_99:
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2178: !_DWLD [9] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 0], %l6
! move %l6(upper) -> %o0(lower)
srlx %l6, 32, %l3
or %l3, %o0, %o0
! move %l6(lower) -> %o1(upper)
sllx %l6, 32, %o1
P2179: !_LD [27] (Int) (Loop exit) (Branch target of P2274)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 32], %l3
! move %l3(lower) -> %o1(lower)
or %l3, %o1, %o1
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_3_99:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_99
nop
ba P2180
nop
TARGET2274:
ba RET2274
nop
P2180: !_BLD [17] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_100:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_3_100:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_100
nop
P2181: !_DWLD [2] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_101:
ldx [%i0 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2182: !_LD [0] (Int) (Loop exit)
lduw [%i0 + 0], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_3_101:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_101
nop
P2183: !_LD [6] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_102:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 6
sethi %hi(0xc0000), %l6
sub %i1, %l6, %i1
ld [%i1 + 12], %f0
! 1 addresses covered
P2184: !_LD [20] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2185: !_LD [22] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
sethi %hi(0xc0000), %o5
add %i1, %o5, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_3_102:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_102
nop
P2186: !_DWLD [21] (Int) (Loop entry) (Branch target of P2354)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_103:
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
ba P2187
nop
TARGET2354:
ba RET2354
nop
P2187: !_BLD [24] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_3_103:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_103
nop
P2188: !_MEMBAR (Int) (Loop entry) (CBR)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_104:
membar #StoreLoad
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET2188
nop
RET2188:
! lfsr step begin
srlx %l0, 1, %l3
xnor %l3, %l0, %l3
sllx %l3, 63, %l3
or %l3, %l0, %l0
srlx %l0, 1, %l0
P2189: !_BLD [29] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_3_104:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_104
nop
P2190: !_BLD [4] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_105:
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P2191: !_BLD [5] (FP) (Loop exit)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 5
sethi %hi(0xc0000), %o5
sub %i1, %o5, %i1
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f32
membar #Sync
! 4 addresses covered
fmovd %f32, %f4
fmovd %f34, %f18
fmovs %f19, %f6
fmovd %f40, %f18
fmovs %f18, %f7
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovd %f4, %f30
fmovd %f6, %f30
!--
sethi %hi(0xc0000), %l3
add %i1, %l3, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_3_105:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_105
nop
P2192: !_BLD [12] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_106:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P2193: !_BLD [24] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f32
membar #Sync
! 4 addresses covered
fmovd %f32, %f4
fmovd %f34, %f18
fmovs %f19, %f6
fmovd %f40, %f18
fmovs %f18, %f7
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovd %f4, %f30
fmovd %f6, %f30
!--
loop_exit_3_106:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_106
nop
P2194: !_BSTC [30] (maybe <- 0x41000005) (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_107:
wr %g0, 0xe0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i3
sub %i0, %i3, %i3
! preparing store val #0, next val will be in f32
fmovs %f16, %f20
fadds %f16, %f17, %f16
! preparing store val #1, next val will be in f33
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #2, next val will be in f35
fmovd %f20, %f32
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #3, next val will be in f40
fmovd %f20, %f34
fmovs %f16, %f20
fadds %f16, %f17, %f16
fmovd %f20, %f40
membar #Sync
stda %f32, [%i3 + 0 ] %asi
membar #Sync
P2195: !_LD [8] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2196: !_LD [17] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 4], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_3_107:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_107
nop
P2197: !_BLD [18] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_108:
wr %g0, 0xf0, %asi
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_3_108:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_108
nop
P2198: !_LD [6] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_109:
ld [%i1 + 12], %f0
! 1 addresses covered
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
loop_exit_3_109:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_109
nop
P2199: !_BLD [17] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_110:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_3_110:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_110
nop
P2200: !_LD [30] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_111:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2201: !_BLD [0] (FP)
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i0 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P2202: !_LD [18] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_3_111:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_111
nop
P2203: !_BLD [27] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_112:
wr %g0, 0xf0, %asi
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P2204: !_REPLACEMENT [23] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS3_O), %i3
sub %i0, %i3, %i3
sethi %hi(0x10000), %l3
ld [%i3+32], %l7
st %l7, [%i3+32]
add %i3, %l3, %l6
ld [%l6+32], %l7
st %l7, [%l6+32]
add %l6, %l3, %l6
ld [%l6+32], %l7
st %l7, [%l6+32]
add %l6, %l3, %l6
ld [%l6+32], %l7
st %l7, [%l6+32]
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_3_112:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_112
nop
P2205: !_LD [29] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_113:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2206: !_LD [29] (Int) (Loop exit)
lduw [%i2 + 4], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_3_113:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_113
nop
P2207: !_PREFETCH [21] (Int) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_114:
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i3
sub %i0, %i3, %i3
prefetch [%i3 + 4], 1
loop_exit_3_114:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_114
nop
P2208: !_BLD [23] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_115:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P2209: !_NOP (Int) (Loop exit)
nop
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_3_115:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_115
nop
P2210: !_LD [6] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_116:
lduw [%i1 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2211: !_LD [17] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 4], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_3_116:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_116
nop
P2212: !_LD [31] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_117:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2213: !_LD [19] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_3_117:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_117
nop
P2214: !_DWLD [17] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_118:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
P2215: !_LD [12] (Int)
sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 0], %o1
! move %o1(lower) -> %o1(upper)
sllx %o1, 32, %o1
P2216: !_LD [13] (Int) (Loop exit)
lduw [%i3 + 4], %l3
! move %l3(lower) -> %o1(lower)
or %l3, %o1, %o1
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_3_118:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_118
nop
P2217: !_DWLD [23] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_119:
sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
ldx [%i2 + 32], %o0
! move %o0(upper) -> %o0(upper)
P2218: !_FLUSHI [4] (Int)
flush %g0
P2219: !_LD [24] (Int) (Loop exit) (LE)
wr %g0, 0x88, %asi
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduwa [%i3 + 0] %asi, %o5
! move %o5(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_3_119:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_119
nop
P2220: !_BSTC [8] (maybe <- 0x41000009) (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_120:
wr %g0, 0xe0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
sub %i0, %i2, %i2
! preparing store val #0, next val will be in f32
fmovs %f16, %f20
fadds %f16, %f17, %f16
! preparing store val #1, next val will be in f33
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #2, next val will be in f35
fmovd %f20, %f32
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #3, next val will be in f40
fmovd %f20, %f34
fmovs %f16, %f20
fadds %f16, %f17, %f16
fmovd %f20, %f40
membar #Sync
stda %f32, [%i2 + 0 ] %asi
membar #Sync
P2221: !_DWLD [19] (Int)
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
ldx [%i3 + 32], %o0
! move %o0(upper) -> %o0(upper)
P2222: !_LD [29] (Int) (Loop exit) (Branch target of P2099)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %l3
! move %l3(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_3_120:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_120
nop
ba P2223
nop
TARGET2099:
ba RET2099
nop
P2223: !_BLD [21] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_121:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_3_121:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_121
nop
P2224: !_FLUSHI [21] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_122:
flush %g0
P2225: !_BLD [5] (FP) (Loop exit)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 5
sethi %hi(0xc0000), %l3
sub %i1, %l3, %i1
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
sethi %hi(0xc0000), %l6
add %i1, %l6, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_3_122:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_122
nop
P2226: !_LD [18] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_123:
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2227: !_LD [10] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_3_123:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_123
nop
P2228: !_DWLD [22] (Int) (Loop entry) (CBR)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_124:
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET2228
nop
RET2228:
! lfsr step begin
srlx %l0, 1, %l7
xnor %l7, %l0, %l7
sllx %l7, 63, %l7
or %l7, %l0, %l0
srlx %l0, 1, %l0
P2229: !_LD [25] (Int) (Loop exit) (CBR)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 4], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET2229
nop
RET2229:
! lfsr step begin
srlx %l0, 1, %l7
xnor %l7, %l0, %l7
sllx %l7, 63, %l7
or %l7, %l0, %l0
srlx %l0, 1, %l0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_3_124:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_124
nop
P2230: !_LD [24] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_125:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2231: !_LD [1] (Int) (Loop exit)
lduw [%i0 + 4], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_3_125:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_125
nop
P2232: !_BLD [24] (FP) (Loop entry) (Branch target of P2523)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_126:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
ba P2233
nop
TARGET2523:
ba RET2523
nop
P2233: !_ST [21] (maybe <- 0x1800014) (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
sub %i0, %i2, %i2
stw %l4, [%i2 + 4 ]
add %l4, 1, %l4
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_3_126:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_126
nop
P2234: !_BLD [11] (FP) (Loop entry) (CBR)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_127:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET2234
nop
RET2234:
! lfsr step begin
srlx %l0, 1, %o5
xnor %o5, %l0, %o5
sllx %o5, 63, %o5
or %o5, %l0, %l0
srlx %l0, 1, %l0
P2235: !_BLD [20] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f32
membar #Sync
! 4 addresses covered
fmovd %f32, %f4
fmovd %f34, %f18
fmovs %f19, %f6
fmovd %f40, %f18
fmovs %f18, %f7
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovd %f4, %f30
fmovd %f6, %f30
!--
loop_exit_3_127:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_127
nop
P2236: !_DWLD [15] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_128:
sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
ldx [%i3 + 32], %o0
! move %o0(upper) -> %o0(upper)
P2237: !_LD [26] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %l7
! move %l7(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_3_128:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_128
nop
P2238: !_NOP (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_129:
nop
P2239: !_LD [9] (Int) (Branch target of P2419)
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
ba P2240
nop
TARGET2419:
ba RET2419
nop
P2240: !_LD [9] (Int) (Loop exit)
lduw [%i3 + 4], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_3_129:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_129
nop
P2241: !_DWLD [17] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_130:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
sub %i0, %i2, %i2
ldd [%i2 + 0], %f0
! 2 addresses covered
P2242: !_DWLD [4] (Int) (Loop exit)
ldx [%i1 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
!--
loop_exit_3_130:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_130
nop
P2243: !_LD [30] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_131:
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2244: !_LD [2] (Int) (Loop exit)
lduw [%i0 + 12], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_3_131:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_131
nop
P2245: !_DWLD [29] (Int) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_132:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_3_132:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_132
nop
P2246: !_DWLD [10] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_133:
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
ldx [%i3 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2247: !_LD [21] (Int) (Loop exit)
sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 4], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_3_133:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_133
nop
P2248: !_PREFETCH [19] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_134:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
sub %i0, %i3, %i3
prefetch [%i3 + 32], 1
P2249: !_BLD [0] (FP) (Loop exit)
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i0 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_3_134:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_134
nop
P2250: !_DWLD [7] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_135:
ldx [%i1 + 32], %o0
! move %o0(upper) -> %o0(upper)
P2251: !_LD [25] (Int) (Loop exit)
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 4], %l3
! move %l3(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_3_135:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_135
nop
P2252: !_LD [18] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_136:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2253: !_BLD [9] (FP)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P2254: !_LD [0] (Int) (Loop exit)
lduw [%i0 + 0], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_3_136:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_136
nop
P2255: !_SWAP [31] (maybe <- 0x1800015) (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_137:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i3
sub %i0, %i3, %i3
mov %l4, %o0
swap [%i3 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
add %l4, 1, %l4
P2256: !_DWLD [24] (Int)
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
ldx [%i2 + 0], %l6
! move %l6(upper) -> %o0(lower)
srlx %l6, 32, %l3
or %l3, %o0, %o0
! move %l6(lower) -> %o1(upper)
sllx %l6, 32, %o1
P2257: !_LD [16] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %l3
! move %l3(lower) -> %o1(lower)
or %l3, %o1, %o1
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_3_137:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_137
nop
P2258: !_BLD [24] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_138:
wr %g0, 0xf0, %asi
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_3_138:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_138
nop
P2259: !_LD [27] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_139:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2260: !_DWLD [27] (Int) (Loop exit)
ldx [%i3 + 32], %o5
! move %o5(upper) -> %o0(lower)
srlx %o5, 32, %l7
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_3_139:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_139
nop
P2261: !_CASX [4] (maybe <- 0x1800016) (Int) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_140:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 4
sethi %hi(0xc0000), %l6
sub %i1, %l6, %i1
ldx [%i1], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
mov %o0, %l7
sllx %l4, 32, %o1
add %l4, 1, %l4
or %l4, %o1, %o1
casx [%i1], %l7, %o1
! move %o1(upper) -> %o1(upper)
! move %o1(lower) -> %o1(lower)
add %l4, 1, %l4
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
sethi %hi(0xc0000), %l7
add %i1, %l7, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_3_140:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_140
nop
P2262: !_DWLD [29] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_141:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
P2263: !_DWLD [8] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 0], %o1
! move %o1(upper) -> %o1(upper)
! move %o1(lower) -> %o1(lower)
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_3_141:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_141
nop
P2264: !_BLD [2] (FP) (Loop entry) (Branch target of P2273)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_142:
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i0 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
ba P2265
nop
TARGET2273:
ba RET2273
nop
P2265: !_LD [20] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2266: !_LD [16] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_3_142:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_142
nop
P2267: !_DWLD [15] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_143:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 32], %o0
! move %o0(upper) -> %o0(upper)
P2268: !_BLD [3] (FP)
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i0 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P2269: !_LD [31] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %l3
! move %l3(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_3_143:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_143
nop
P2270: !_DWLD [24] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_144:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
P2271: !_CAS [11] (maybe <- 0x1800018) (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i3
sub %i0, %i3, %i3
add %i3, 32, %l7
lduw [%l7], %o1
mov %o1, %l6
! move %l6(lower) -> %o1(upper)
sllx %l6, 32, %o1
mov %l4, %l3
cas [%l7], %l6, %l3
! move %l3(lower) -> %o1(lower)
srl %l3, 0, %l6
or %l6, %o1, %o1
add %l4, 1, %l4
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_3_144:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_144
nop
P2272: !_LD [31] (Int) (Loop entry) (LE)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_145:
wr %g0, 0x88, %asi
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduwa [%i2 + 32] %asi, %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2273: !_LD [31] (Int) (Loop exit) (CBR)
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 32], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET2273
nop
RET2273:
! lfsr step begin
srlx %l0, 1, %o5
xnor %o5, %l0, %o5
sllx %o5, 63, %o5
or %o5, %l0, %l0
srlx %l0, 1, %l0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_3_145:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_145
nop
P2274: !_LD [9] (Int) (Loop entry) (CBR)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_146:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET2274
nop
RET2274:
! lfsr step begin
srlx %l0, 1, %o5
xnor %o5, %l0, %o5
sllx %o5, 63, %o5
or %o5, %l0, %l0
srlx %l0, 1, %l0
P2275: !_DWLD [18] (FP)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
sub %i0, %i3, %i3
ldd [%i3 + 8], %f0
! 1 addresses covered
fmovs %f1, %f0
P2276: !_LD [17] (Int) (Loop exit)
lduw [%i3 + 4], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
loop_exit_3_146:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_146
nop
P2277: !_DWLD [27] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_147:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 32], %o0
! move %o0(upper) -> %o0(upper)
P2278: !_DWLD [15] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 32], %l3
! move %l3(upper) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
srlx %l3, 32, %o5
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_3_147:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_147
nop
P2279: !_BSTC [12] (maybe <- 0x4100000d) (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_148:
wr %g0, 0xe0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i2
sub %i0, %i2, %i2
! preparing store val #0, next val will be in f32
fmovs %f16, %f20
fadds %f16, %f17, %f16
! preparing store val #1, next val will be in f33
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #2, next val will be in f35
fmovd %f20, %f32
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #3, next val will be in f40
fmovd %f20, %f34
fmovs %f16, %f20
fadds %f16, %f17, %f16
fmovd %f20, %f40
membar #Sync
stda %f32, [%i2 + 0 ] %asi
membar #Sync
P2280: !_BLD [2] (FP) (Loop exit)
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i0 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_3_148:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_148
nop
P2281: !_BLD [5] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_149:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 5
sethi %hi(0xc0000), %o5
sub %i1, %o5, %i1
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P2282: !_LD [10] (Int) (CBR)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET2282
nop
RET2282:
! lfsr step begin
srlx %l0, 1, %l7
xnor %l7, %l0, %l7
sllx %l7, 63, %l7
or %l7, %l0, %l0
srlx %l0, 1, %l0
P2283: !_LD [23] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 32], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
sethi %hi(0xc0000), %l7
add %i1, %l7, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_3_149:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_149
nop
P2284: !_BLD [0] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_150:
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i0 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_3_150:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_150
nop
P2285: !_DWLD [30] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_151:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2286: !_LD [24] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 0], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_3_151:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_151
nop
P2287: !_DWLD [5] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_152:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 5
sethi %hi(0xc0000), %l7
sub %i1, %l7, %i1
ldx [%i1 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
P2288: !_BLD [17] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
sethi %hi(0xc0000), %l6
add %i1, %l6, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_3_152:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_152
nop
P2289: !_DWLD [31] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_153:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 32], %o0
! move %o0(upper) -> %o0(upper)
P2290: !_LD [29] (Int) (Loop exit)
lduw [%i2 + 4], %l7
! move %l7(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_3_153:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_153
nop
P2291: !_DWLD [7] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_154:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 7
sethi %hi(0xc0000), %l3
sub %i1, %l3, %i1
ldx [%i1 + 32], %o0
! move %o0(upper) -> %o0(upper)
P2292: !_LD [15] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %l3
! move %l3(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
sethi %hi(0xc0000), %l6
add %i1, %l6, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_3_154:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_154
nop
P2293: !_LD [12] (Int) (Loop entry) (CBR)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_155:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET2293
nop
RET2293:
! lfsr step begin
srlx %l0, 1, %l6
xnor %l6, %l0, %l6
sllx %l6, 63, %l6
or %l6, %l0, %l0
srlx %l0, 1, %l0
P2294: !_LD [9] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 4], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_3_155:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_155
nop
P2295: !_BLD [14] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_156:
wr %g0, 0xf0, %asi
sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_3_156:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_156
nop
P2296: !_DWLD [9] (Int) (Loop entry) (CBR) (Branch target of P2561)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_157:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET2296
nop
RET2296:
! lfsr step begin
srlx %l0, 1, %l6
xnor %l6, %l0, %l6
sllx %l6, 63, %l6
or %l6, %l0, %l0
srlx %l0, 1, %l0
ba P2297
nop
TARGET2561:
ba RET2561
nop
P2297: !_DWLD [12] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 0], %o1
! move %o1(upper) -> %o1(upper)
! move %o1(lower) -> %o1(lower)
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_3_157:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_157
nop
P2298: !_BLD [29] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_158:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_3_158:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_158
nop
P2299: !_DWST [5] (maybe <- 0x1800019) (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_159:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 5
sethi %hi(0xc0000), %o5
sub %i1, %o5, %i1
sllx %l4, 32, %l3
add %l4, 1, %l4
or %l3, %l4, %l3
stx %l3, [%i1 + 0]
add %l4, 1, %l4
P2300: !_LD [22] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2301: !_LD [2] (Int) (Loop exit)
lduw [%i0 + 12], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
sethi %hi(0xc0000), %l3
add %i1, %l3, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_3_159:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_159
nop
P2302: !_BLD [22] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_160:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P2303: !_DWLD [28] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_3_160:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_160
nop
P2304: !_BLD [19] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_161:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_3_161:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_161
nop
P2305: !_REPLACEMENT [5] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_162:
sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS2_O), %i2
sub %i0, %i2, %i2
sethi %hi(0x10000), %o5
ld [%i2+4], %l6
st %l6, [%i2+4]
add %i2, %o5, %l3
ld [%l3+4], %l6
st %l6, [%l3+4]
add %l3, %o5, %l3
ld [%l3+4], %l6
st %l6, [%l3+4]
add %l3, %o5, %l3
ld [%l3+4], %l6
st %l6, [%l3+4]
P2306: !_BLD [2] (FP) (Loop exit)
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i0 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_3_162:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_162
nop
P2307: !_PREFETCH [14] (Int) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_163:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i3
sub %i0, %i3, %i3
prefetch [%i3 + 12], 1
loop_exit_3_163:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_163
nop
P2308: !_BLD [7] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_164:
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_3_164:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_164
nop
P2309: !_DWLD [12] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_165:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
P2310: !_LD [23] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %o1
! move %o1(lower) -> %o1(upper)
sllx %o1, 32, %o1
P2311: !_LD [23] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 32], %l6
! move %l6(lower) -> %o1(lower)
or %l6, %o1, %o1
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_3_165:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_165
nop
P2312: !_LD [2] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_166:
lduw [%i0 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2313: !_DWLD [6] (Int) (Loop exit)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 6
sethi %hi(0xc0000), %l6
sub %i1, %l6, %i1
ldx [%i1 + 8], %o5
! move %o5(lower) -> %o0(lower)
srl %o5, 0, %l7
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
sethi %hi(0xc0000), %l3
add %i1, %l3, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_3_166:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_166
nop
P2314: !_DWLD [0] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_167:
ldd [%i0 + 0], %f0
! 2 addresses covered
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
!--
loop_exit_3_167:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_167
nop
P2315: !_LD [9] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_168:
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2316: !_LD [11] (Int) (Loop exit)
lduw [%i3 + 32], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_3_168:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_168
nop
P2317: !_BLD [5] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_169:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 5
sethi %hi(0xc0000), %l3
sub %i1, %l3, %i1
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P2318: !_LD [21] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2319: !_LD [17] (Int) (Loop exit)
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 4], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
sethi %hi(0xc0000), %l7
add %i1, %l7, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_3_169:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_169
nop
P2320: !_BLD [12] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_170:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P2321: !_LD [9] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2322: !_LD [3] (Int) (Loop exit)
lduw [%i0 + 32], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_3_170:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_170
nop
P2323: !_LD [0] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_171:
lduw [%i0 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2324: !_LD [19] (Int) (Loop exit)
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 32], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_3_171:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_171
nop
P2325: !_PREFETCH [23] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_172:
sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
prefetch [%i3 + 32], 1
P2326: !_CASX [6] (maybe <- 0x180001b) (Int) (Loop exit)
add %i1, 8, %l6
ldx [%l6], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
mov %o0, %l3
mov %l4, %o1
casx [%l6], %l3, %o1
! move %o1(upper) -> %o1(upper)
! move %o1(lower) -> %o1(lower)
add %l4, 1, %l4
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_3_172:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_172
nop
P2327: !_DWLD [6] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_173:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 6
sethi %hi(0xc0000), %l6
sub %i1, %l6, %i1
ldx [%i1 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2328: !_LD [5] (Int) (Loop exit)
lduw [%i1 + 4], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
sethi %hi(0xc0000), %l7
add %i1, %l7, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_3_173:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_173
nop
P2329: !_BLD [4] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_174:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 4
sethi %hi(0xc0000), %o5
sub %i1, %o5, %i1
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P2330: !_LD [22] (FP) (Loop exit)
sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
ld [%i2 + 12], %f4
! 1 addresses covered
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovs %f4, %f30
!--
sethi %hi(0xc0000), %l3
add %i1, %l3, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_3_174:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_174
nop
P2331: !_NOP (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_175:
nop
P2332: !_BLD [10] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_3_175:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_175
nop
P2333: !_DWLD [18] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_176:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2334: !_LD [15] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_3_176:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_176
nop
P2335: !_LD [1] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_177:
lduw [%i0 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2336: !_LD [12] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 0], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_3_177:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_177
nop
P2337: !_DWLD [23] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_178:
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 32], %o0
! move %o0(upper) -> %o0(upper)
P2338: !_DWLD [16] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 0], %o5
! move %o5(upper) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
srlx %o5, 32, %l7
or %l7, %o0, %o0
! move %o5(lower) -> %o1(upper)
sllx %o5, 32, %o1
P2339: !_LD [31] (Int) (Loop exit)
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 32], %l7
! move %l7(lower) -> %o1(lower)
or %l7, %o1, %o1
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_3_178:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_178
nop
P2340: !_FLUSHI [18] (Int) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_179:
flush %g0
loop_exit_3_179:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_179
nop
P2341: !_BLD [10] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_180:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P2342: !_LD [17] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2343: !_LD [9] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_3_180:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_180
nop
P2344: !_FLUSHI [4] (Int) (Loop entry) (Loop exit) (Branch target of P2171)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_181:
flush %g0
loop_exit_3_181:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_181
nop
ba P2345
nop
TARGET2171:
ba RET2171
nop
P2345: !_DWLD [19] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_182:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 32], %o0
! move %o0(upper) -> %o0(upper)
P2346: !_LD [24] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 0], %l6
! move %l6(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_3_182:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_182
nop
P2347: !_CAS [28] (maybe <- 0x180001c) (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_183:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3], %o0
mov %o0, %l3
! move %l3(lower) -> %o0(upper)
sllx %l3, 32, %o0
mov %l4, %o5
cas [%i3], %l3, %o5
! move %o5(lower) -> %o0(lower)
srl %o5, 0, %l3
or %l3, %o0, %o0
add %l4, 1, %l4
P2348: !_DWLD [7] (Int) (CBR)
ldx [%i1 + 32], %o1
! move %o1(upper) -> %o1(upper)
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET2348
nop
RET2348:
! lfsr step begin
srlx %l0, 1, %l7
xnor %l7, %l0, %l7
sllx %l7, 63, %l7
or %l7, %l0, %l0
srlx %l0, 1, %l0
P2349: !_LD [2] (Int) (Loop exit)
lduw [%i0 + 12], %l6
! move %l6(lower) -> %o1(lower)
srlx %o1, 32, %o1
sllx %o1, 32, %o1
or %l6, %o1, %o1
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_3_183:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_183
nop
P2350: !_REPLACEMENT [27] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_184:
sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS1_O), %i2
sub %i0, %i2, %i2
sethi %hi(0x10000), %o5
ld [%i2+32], %l6
st %l6, [%i2+32]
add %i2, %o5, %l3
ld [%l3+32], %l6
st %l6, [%l3+32]
add %l3, %o5, %l3
ld [%l3+32], %l6
st %l6, [%l3+32]
add %l3, %o5, %l3
ld [%l3+32], %l6
st %l6, [%l3+32]
P2351: !_DWLD [3] (FP) (Loop exit)
ldd [%i0 + 32], %f0
! 1 addresses covered
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
loop_exit_3_184:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_184
nop
P2352: !_DWLD [20] (Int) (Loop entry) (LE)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_185:
wr %g0, 0x88, %asi
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i3
sub %i0, %i3, %i3
ldxa [%i3 + 0] %asi, %l6
! move %l6(lower) -> %o0(upper)
sllx %l6, 32, %o0
! move %l6(upper) -> %o0(lower)
srlx %l6, 32, %l3
or %l3, %o0, %o0
P2353: !_LD [1] (FP) (Loop exit)
ld [%i0 + 4], %f0
! 1 addresses covered
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
loop_exit_3_185:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_185
nop
P2354: !_LD [30] (FP) (Loop entry) (Loop exit) (CBR)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_186:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
sub %i0, %i2, %i2
ld [%i2 + 12], %f0
! 1 addresses covered
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET2354
nop
RET2354:
! lfsr step begin
srlx %l0, 1, %l3
xnor %l3, %l0, %l3
sllx %l3, 63, %l3
or %l3, %l0, %l0
srlx %l0, 1, %l0
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
loop_exit_3_186:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_186
nop
P2355: !_BLD [4] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_187:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 4
sethi %hi(0xc0000), %l7
sub %i1, %l7, %i1
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P2356: !_BLD [29] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f32
membar #Sync
! 4 addresses covered
fmovd %f32, %f4
fmovd %f34, %f18
fmovs %f19, %f6
fmovd %f40, %f18
fmovs %f18, %f7
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovd %f4, %f30
fmovd %f6, %f30
!--
sethi %hi(0xc0000), %o5
add %i1, %o5, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_3_187:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_187
nop
P2357: !_DWLD [30] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_188:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2358: !_LD [24] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_3_188:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_188
nop
P2359: !_REPLACEMENT [9] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_189:
sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS2_O), %i2
sub %i0, %i2, %i2
sethi %hi(0x10000), %o5
ld [%i2+4], %l6
st %l6, [%i2+4]
add %i2, %o5, %l3
ld [%l3+4], %l6
st %l6, [%l3+4]
add %l3, %o5, %l3
ld [%l3+4], %l6
st %l6, [%l3+4]
add %l3, %o5, %l3
ld [%l3+4], %l6
st %l6, [%l3+4]
P2360: !_SWAP [23] (maybe <- 0x180001d) (Int) (LE)
wr %g0, 0x88, %asi
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i3
sub %i0, %i3, %i3
mov %l4, %o0
! Change single-word-level endianess (big endian <-> little endian)
sethi %hi(0xff00ff00), %l7
or %l7, %lo(0xff00ff00), %l7
and %o0, %l7, %o5
srl %o5, 8, %o5
sll %o0, 8, %o0
and %o0, %l7, %o0
or %o0, %o5, %o0
srl %o0, 16, %o5
sll %o0, 16, %o0
srl %o0, 0, %o0
or %o0, %o5, %o0
swapa [%i3 + 32] %asi, %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
add %l4, 1, %l4
P2361: !_LD [28] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 0], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_3_189:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_189
nop
P2362: !_LD [15] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_190:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2363: !_BLD [21] (FP) (CBR)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET2363
nop
RET2363:
! lfsr step begin
srlx %l0, 1, %l3
xnor %l3, %l0, %l3
sllx %l3, 63, %l3
or %l3, %l0, %l0
srlx %l0, 1, %l0
P2364: !_LD [13] (Int) (Loop exit)
lduw [%i3 + 4], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_3_190:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_190
nop
P2365: !_BSTC [20] (maybe <- 0x41000011) (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_191:
wr %g0, 0xe0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i3
sub %i0, %i3, %i3
! preparing store val #0, next val will be in f32
fmovs %f16, %f20
fadds %f16, %f17, %f16
! preparing store val #1, next val will be in f33
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #2, next val will be in f35
fmovd %f20, %f32
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #3, next val will be in f40
fmovd %f20, %f34
fmovs %f16, %f20
fadds %f16, %f17, %f16
fmovd %f20, %f40
membar #Sync
stda %f32, [%i3 + 0 ] %asi
membar #Sync
loop_exit_3_191:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_191
nop
P2366: !_DWLD [15] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_192:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 32], %o0
! move %o0(upper) -> %o0(upper)
P2367: !_LD [27] (Int) (Loop exit) (Branch target of P2006)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %l6
! move %l6(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_3_192:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_192
nop
ba P2368
nop
TARGET2006:
ba RET2006
nop
P2368: !_BLD [11] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_193:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P2369: !_DWLD [3] (Int)
ldx [%i0 + 32], %o0
! move %o0(upper) -> %o0(upper)
P2370: !_LD [22] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %o5
! move %o5(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_3_193:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_193
nop
P2371: !_DWLD [31] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_194:
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
ldx [%i2 + 32], %o0
! move %o0(upper) -> %o0(upper)
P2372: !_LD [26] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %l6
! move %l6(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_3_194:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_194
nop
P2373: !_BLD [26] (FP) (Loop entry) (Loop exit) (Branch target of P2293)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_195:
wr %g0, 0xf0, %asi
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_3_195:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_195
nop
ba P2374
nop
TARGET2293:
ba RET2293
nop
P2374: !_BLD [7] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_196:
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_3_196:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_196
nop
P2375: !_LD [4] (Int) (Loop entry) (CBR)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_197:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 4
sethi %hi(0xc0000), %l7
sub %i1, %l7, %i1
lduw [%i1 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET2375
nop
RET2375:
! lfsr step begin
srlx %l0, 1, %l6
xnor %l6, %l0, %l6
sllx %l6, 63, %l6
or %l6, %l0, %l0
srlx %l0, 1, %l0
P2376: !_LD [6] (Int) (Loop exit)
lduw [%i1 + 12], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
sethi %hi(0xc0000), %l3
add %i1, %l3, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_3_197:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_197
nop
P2377: !_LD [31] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_198:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
sub %i0, %i3, %i3
ld [%i3 + 32], %f0
! 1 addresses covered
P2378: !_LD [3] (Int)
lduw [%i0 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2379: !_LD [3] (Int) (Loop exit)
lduw [%i0 + 32], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
loop_exit_3_198:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_198
nop
P2380: !_DWLD [6] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_199:
ldx [%i1 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2381: !_LD [12] (Int) (Loop exit)
sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 0], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_3_199:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_199
nop
P2382: !_DWLD [1] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_200:
ldd [%i0 + 0], %f0
! 2 addresses covered
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
!--
loop_exit_3_200:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_200
nop
P2383: !_BLD [16] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_201:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P2384: !_LD [5] (FP) (Loop exit)
ld [%i1 + 4], %f4
! 1 addresses covered
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovs %f4, %f30
!--
loop_exit_3_201:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_201
nop
P2385: !_BLD [2] (FP) (Loop entry) (Loop exit) (CBR)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_202:
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i0 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET2385
nop
RET2385:
! lfsr step begin
srlx %l0, 1, %l7
xnor %l7, %l0, %l7
sllx %l7, 63, %l7
or %l7, %l0, %l0
srlx %l0, 1, %l0
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_3_202:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_202
nop
P2386: !_DWLD [11] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_203:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 32], %o0
! move %o0(upper) -> %o0(upper)
P2387: !_DWLD [24] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 0], %l3
! move %l3(upper) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
srlx %l3, 32, %o5
or %o5, %o0, %o0
! move %l3(lower) -> %o1(upper)
sllx %l3, 32, %o1
P2388: !_LD [5] (Int) (Loop exit)
lduw [%i1 + 4], %l7
! move %l7(lower) -> %o1(lower)
or %l7, %o1, %o1
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_3_203:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_203
nop
P2389: !_LD [25] (Int) (Loop entry) (CBR)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_204:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET2389
nop
RET2389:
! lfsr step begin
srlx %l0, 1, %o5
xnor %o5, %l0, %o5
sllx %o5, 63, %o5
or %o5, %l0, %l0
srlx %l0, 1, %l0
P2390: !_DWLD [25] (Int)
ldx [%i2 + 0], %l6
! move %l6(upper) -> %o0(lower)
srlx %l6, 32, %l3
or %l3, %o0, %o0
! move %l6(lower) -> %o1(upper)
sllx %l6, 32, %o1
P2391: !_LD [14] (Int) (Loop exit) (CBR) (Branch target of P2348)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %l3
! move %l3(lower) -> %o1(lower)
or %l3, %o1, %o1
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET2391
nop
RET2391:
! lfsr step begin
srlx %l0, 1, %l6
xnor %l6, %l0, %l6
sllx %l6, 63, %l6
or %l6, %l0, %l0
srlx %l0, 1, %l0
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_3_204:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_204
nop
ba P2392
nop
TARGET2348:
ba RET2348
nop
P2392: !_DWLD [15] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_205:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 32], %o0
! move %o0(upper) -> %o0(upper)
P2393: !_LD [4] (Int) (Loop exit)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 4
sethi %hi(0xc0000), %l6
sub %i1, %l6, %i1
lduw [%i1 + 0], %o5
! move %o5(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
sethi %hi(0xc0000), %l3
add %i1, %l3, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_3_205:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_205
nop
P2394: !_BLD [23] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_206:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_3_206:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_206
nop
P2395: !_BLD [26] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_207:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P2396: !_BLD [13] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f32
membar #Sync
! 4 addresses covered
fmovd %f32, %f4
fmovd %f34, %f18
fmovs %f19, %f6
fmovd %f40, %f18
fmovs %f18, %f7
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovd %f4, %f30
fmovd %f6, %f30
!--
loop_exit_3_207:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_207
nop
P2397: !_DWLD [28] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_208:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
P2398: !_BLD [15] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_3_208:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_208
nop
P2399: !_NOP (Int) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_209:
nop
loop_exit_3_209:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_209
nop
P2400: !_DWLD [31] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_210:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 32], %o0
! move %o0(upper) -> %o0(upper)
P2401: !_BLD [30] (FP)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P2402: !_LD [2] (Int) (Loop exit)
lduw [%i0 + 12], %l7
! move %l7(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_3_210:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_210
nop
P2403: !_LD [10] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_211:
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2404: !_DWLD [3] (Int) (Loop exit)
ldx [%i0 + 32], %l3
! move %l3(upper) -> %o0(lower)
srlx %l3, 32, %o5
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_3_211:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_211
nop
P2405: !_LD [10] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_212:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2406: !_LD [9] (Int) (Loop exit) (Branch target of P2391)
lduw [%i3 + 4], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_3_212:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_212
nop
ba P2407
nop
TARGET2391:
ba RET2391
nop
P2407: !_DWLD [20] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_213:
sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
ldx [%i2 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
P2408: !_DWLD [30] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 8], %o1
! move %o1(lower) -> %o1(upper)
sllx %o1, 32, %o1
P2409: !_LD [0] (Int) (Loop exit)
lduw [%i0 + 0], %o5
! move %o5(lower) -> %o1(lower)
or %o5, %o1, %o1
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_3_213:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_213
nop
P2410: !_DWLD [23] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_214:
sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
ldx [%i2 + 32], %o0
! move %o0(upper) -> %o0(upper)
P2411: !_LD [24] (Int) (Loop exit)
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 0], %l6
! move %l6(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_3_214:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_214
nop
P2412: !_BLD [12] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_215:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P2413: !_DWLD [9] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_3_215:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_215
nop
P2414: !_LD [4] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_216:
lduw [%i1 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2415: !_DWLD [30] (Int) (Loop exit) (Branch target of P2228)
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
ldx [%i2 + 8], %o5
! move %o5(lower) -> %o0(lower)
srl %o5, 0, %l7
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_3_216:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_216
nop
ba P2416
nop
TARGET2228:
ba RET2228
nop
P2416: !_DWLD [18] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_217:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2417: !_BLD [17] (FP)
wr %g0, 0xf0, %asi
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P2418: !_LD [26] (Int) (Loop exit) (LE) (CBR)
wr %g0, 0x88, %asi
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduwa [%i3 + 12] %asi, %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET2418
nop
RET2418:
! lfsr step begin
srlx %l0, 1, %l7
xnor %l7, %l0, %l7
sllx %l7, 63, %l7
or %l7, %l0, %l0
srlx %l0, 1, %l0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_3_217:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_217
nop
P2419: !_LD [17] (Int) (Loop entry) (CBR)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_218:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET2419
nop
RET2419:
! lfsr step begin
srlx %l0, 1, %o5
xnor %o5, %l0, %o5
sllx %o5, 63, %o5
or %o5, %l0, %l0
srlx %l0, 1, %l0
P2420: !_LD [9] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 4], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_3_218:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_218
nop
P2421: !_DWLD [1] (Int) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_219:
ldx [%i0 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_3_219:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_219
nop
P2422: !_DWLD [13] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_220:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i2
sub %i0, %i2, %i2
ldd [%i2 + 0], %f0
! 2 addresses covered
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
!--
loop_exit_3_220:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_220
nop
P2423: !_BLD [20] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_221:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P2424: !_LD [8] (FP) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
sub %i0, %i2, %i2
ld [%i2 + 0], %f4
! 1 addresses covered
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovs %f4, %f30
!--
loop_exit_3_221:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_221
nop
P2425: !_SWAP [1] (maybe <- 0x180001e) (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_222:
mov %l4, %o0
swap [%i0 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
add %l4, 1, %l4
P2426: !_LD [15] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_3_222:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_222
nop
P2427: !_LD [8] (FP) (Loop entry) (Loop exit) (CBR)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_223:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i2
sub %i0, %i2, %i2
ld [%i2 + 0], %f0
! 1 addresses covered
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET2427
nop
RET2427:
! lfsr step begin
srlx %l0, 1, %l7
xnor %l7, %l0, %l7
sllx %l7, 63, %l7
or %l7, %l0, %l0
srlx %l0, 1, %l0
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
loop_exit_3_223:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_223
nop
P2428: !_LD [13] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_224:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2429: !_LD [17] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_3_224:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_224
nop
P2430: !_BLD [18] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_225:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P2431: !_DWLD [5] (Int) (Loop exit)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 5
sethi %hi(0xc0000), %l7
sub %i1, %l7, %i1
ldx [%i1 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
sethi %hi(0xc0000), %l6
add %i1, %l6, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_3_225:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_225
nop
P2432: !_BLD [17] (FP) (Loop entry) (CBR)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_226:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET2432
nop
RET2432:
! lfsr step begin
srlx %l0, 1, %l7
xnor %l7, %l0, %l7
sllx %l7, 63, %l7
or %l7, %l0, %l0
srlx %l0, 1, %l0
P2433: !_DWLD [26] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2434: !_LD [27] (Int) (Loop exit)
lduw [%i3 + 32], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_3_226:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_226
nop
P2435: !_LD [4] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_227:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 4
sethi %hi(0xc0000), %l6
sub %i1, %l6, %i1
lduw [%i1 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2436: !_DWLD [0] (Int) (CBR)
ldx [%i0 + 0], %l6
! move %l6(upper) -> %o0(lower)
srlx %l6, 32, %l3
or %l3, %o0, %o0
! move %l6(lower) -> %o1(upper)
sllx %l6, 32, %o1
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET2436
nop
RET2436:
! lfsr step begin
srlx %l0, 1, %l7
xnor %l7, %l0, %l7
sllx %l7, 63, %l7
or %l7, %l0, %l0
srlx %l0, 1, %l0
P2437: !_LD [14] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %l6
! move %l6(lower) -> %o1(lower)
or %l6, %o1, %o1
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
sethi %hi(0xc0000), %l7
add %i1, %l7, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_3_227:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_227
nop
P2438: !_BLD [16] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_228:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_3_228:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_228
nop
P2439: !_DWLD [30] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_229:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2440: !_MEMBAR (Int)
membar #StoreLoad
P2441: !_LD [24] (Int) (Loop exit) (CBR)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET2441
nop
RET2441:
! lfsr step begin
srlx %l0, 1, %l7
xnor %l7, %l0, %l7
sllx %l7, 63, %l7
or %l7, %l0, %l0
srlx %l0, 1, %l0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_3_229:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_229
nop
P2442: !_BLD [1] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_230:
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i0 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P2443: !_DWLD [10] (Int)
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
ldx [%i2 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2444: !_LD [1] (Int) (Loop exit)
lduw [%i0 + 4], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_3_230:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_230
nop
P2445: !_LD [26] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_231:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2446: !_LD [25] (Int) (Loop exit)
lduw [%i3 + 4], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_3_231:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_231
nop
P2447: !_LD [14] (Int) (Loop entry) (LE)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_232:
wr %g0, 0x88, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduwa [%i2 + 12] %asi, %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2448: !_LD [27] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_3_232:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_232
nop
P2449: !_BLD [17] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_233:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P2450: !_DWLD [7] (Int)
ldx [%i1 + 32], %o0
! move %o0(upper) -> %o0(upper)
P2451: !_LD [31] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %o5
! move %o5(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_3_233:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_233
nop
P2452: !_BSTC [5] (maybe <- 0x41000015) (FP) (Loop entry) (Loop exit) (CBR)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_234:
wr %g0, 0xe0, %asi
! preparing store val #0, next val will be in f32
fmovs %f16, %f20
fadds %f16, %f17, %f16
! preparing store val #1, next val will be in f33
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #2, next val will be in f35
fmovd %f20, %f32
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #3, next val will be in f40
fmovd %f20, %f34
fmovs %f16, %f20
fadds %f16, %f17, %f16
fmovd %f20, %f40
membar #Sync
stda %f32, [%i1 + 0 ] %asi
membar #Sync
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET2452
nop
RET2452:
! lfsr step begin
srlx %l0, 1, %l3
xnor %l3, %l0, %l3
sllx %l3, 63, %l3
or %l3, %l0, %l0
srlx %l0, 1, %l0
loop_exit_3_234:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_234
nop
P2453: !_LD [30] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_235:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2454: !_NOP (Int)
nop
P2455: !_LD [5] (Int) (Loop exit) (CBR) (Branch target of P2427)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 5
sethi %hi(0xc0000), %l6
sub %i1, %l6, %i1
lduw [%i1 + 4], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET2455
nop
RET2455:
! lfsr step begin
srlx %l0, 1, %l3
xnor %l3, %l0, %l3
sllx %l3, 63, %l3
or %l3, %l0, %l0
srlx %l0, 1, %l0
!---- flushing int results buffer----
mov %o0, %l5
sethi %hi(0xc0000), %l6
add %i1, %l6, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_3_235:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_235
nop
ba P2456
nop
TARGET2427:
ba RET2427
nop
P2456: !_LD [8] (FP) (Loop entry) (Branch target of P2452)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_236:
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
ld [%i3 + 0], %f0
! 1 addresses covered
ba P2457
nop
TARGET2452:
ba RET2452
nop
P2457: !_MEMBAR (Int) (Loop exit)
membar #StoreLoad
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
loop_exit_3_236:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_236
nop
P2458: !_BST [1] (maybe <- 0x41000019) (FP) (Loop entry) (Loop exit) (Branch target of P2537)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_237:
wr %g0, 0xf0, %asi
! preparing store val #0, next val will be in f32
fmovs %f16, %f20
fadds %f16, %f17, %f16
! preparing store val #1, next val will be in f33
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #2, next val will be in f35
fmovd %f20, %f32
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #3, next val will be in f40
fmovd %f20, %f34
fmovs %f16, %f20
fadds %f16, %f17, %f16
fmovd %f20, %f40
membar #Sync
stda %f32, [%i0 + 0 ] %asi
membar #Sync
loop_exit_3_237:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_237
nop
ba P2459
nop
TARGET2537:
ba RET2537
nop
P2459: !_DWLD [2] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_238:
ldx [%i0 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2460: !_CAS [15] (maybe <- 0x180001f) (Int)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i2
sub %i0, %i2, %i2
add %i2, 32, %l3
lduw [%l3], %l7
mov %l7, %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
mov %l4, %o1
cas [%l3], %o5, %o1
! move %o1(lower) -> %o1(upper)
sllx %o1, 32, %o1
add %l4, 1, %l4
P2461: !_LD [31] (Int) (Loop exit)
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 32], %l6
! move %l6(lower) -> %o1(lower)
or %l6, %o1, %o1
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_3_238:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_238
nop
P2462: !_DWLD [1] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_239:
ldx [%i0 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
P2463: !_BLD [7] (FP) (Loop exit)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 7
sethi %hi(0xc0000), %l6
sub %i1, %l6, %i1
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
sethi %hi(0xc0000), %l7
add %i1, %l7, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_3_239:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_239
nop
P2464: !_DWLD [31] (Int) (Loop entry) (CBR)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_240:
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
ldx [%i2 + 32], %o0
! move %o0(upper) -> %o0(upper)
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET2464
nop
RET2464:
! lfsr step begin
srlx %l0, 1, %l6
xnor %l6, %l0, %l6
sllx %l6, 63, %l6
or %l6, %l0, %l0
srlx %l0, 1, %l0
P2465: !_CAS [29] (maybe <- 0x1800020) (Int) (LE)
! Change single-word-level endianess (big endian <-> little endian)
sethi %hi(0xff00ff00), %l3
or %l3, %lo(0xff00ff00), %l3
and %l4, %l3, %o5
srl %o5, 8, %o5
sll %l4, 8, %l6
and %l6, %l3, %l6
or %l6, %o5, %l6
srl %l6, 16, %o5
sll %l6, 16, %l6
srl %l6, 0, %l6
or %l6, %o5, %l6
wr %g0, 0x88, %asi
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
sub %i0, %i3, %i3
add %i3, 4, %l3
lduwa [%l3] %asi, %l7
mov %l7, %o5
! move %o5(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %o5, %o0, %o0
mov %l6, %o1
casa [%l3] %asi, %o5, %o1
! move %o1(lower) -> %o1(upper)
sllx %o1, 32, %o1
add %l4, 1, %l4
P2466: !_LD [1] (Int) (Loop exit)
lduw [%i0 + 4], %l3
! move %l3(lower) -> %o1(lower)
or %l3, %o1, %o1
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_3_240:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_240
nop
P2467: !_BLD [22] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_241:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_3_241:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_241
nop
P2468: !_LD [13] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_242:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2469: !_LD [17] (Int) (Loop exit)
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 4], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_3_242:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_242
nop
P2470: !_DWLD [11] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_243:
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
ldx [%i3 + 32], %o0
! move %o0(upper) -> %o0(upper)
P2471: !_LD [0] (Int) (Loop exit)
lduw [%i0 + 0], %l7
! move %l7(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_3_243:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_243
nop
P2472: !_DWLD [0] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_244:
ldx [%i0 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
P2473: !_LD [28] (Int) (Branch target of P2363)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 0], %o1
! move %o1(lower) -> %o1(upper)
sllx %o1, 32, %o1
ba P2474
nop
TARGET2363:
ba RET2363
nop
P2474: !_LD [5] (Int) (Loop exit)
lduw [%i1 + 4], %l7
! move %l7(lower) -> %o1(lower)
or %l7, %o1, %o1
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_3_244:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_244
nop
P2475: !_LD [15] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_245:
sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2476: !_LD [14] (Int) (Loop exit)
lduw [%i3 + 12], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_3_245:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_245
nop
P2477: !_SWAP [0] (maybe <- 0x1800021) (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_246:
mov %l4, %o0
swap [%i0 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
add %l4, 1, %l4
P2478: !_BLD [5] (FP)
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P2479: !_LD [15] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 32], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_3_246:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_246
nop
P2480: !_BSTC [23] (maybe <- 0x4100001d) (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_247:
wr %g0, 0xe0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
sub %i0, %i3, %i3
! preparing store val #0, next val will be in f32
fmovs %f16, %f20
fadds %f16, %f17, %f16
! preparing store val #1, next val will be in f33
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #2, next val will be in f35
fmovd %f20, %f32
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #3, next val will be in f40
fmovd %f20, %f34
fmovs %f16, %f20
fadds %f16, %f17, %f16
fmovd %f20, %f40
membar #Sync
stda %f32, [%i3 + 0 ] %asi
membar #Sync
loop_exit_3_247:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_247
nop
P2481: !_BLD [25] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_248:
wr %g0, 0xf0, %asi
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_3_248:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_248
nop
P2482: !_LD [25] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_249:
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2483: !_LD [31] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 32], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_3_249:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_249
nop
P2484: !_BLD [25] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_250:
wr %g0, 0xf0, %asi
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P2485: !_DWLD [10] (Int) (Branch target of P2282)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
ba P2486
nop
TARGET2282:
ba RET2282
nop
P2486: !_LD [23] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_3_250:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_250
nop
P2487: !_LD [26] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_251:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2488: !_LD [30] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_3_251:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_251
nop
P2489: !_SWAP [17] (maybe <- 0x1800022) (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_252:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
sub %i0, %i2, %i2
mov %l4, %o0
swap [%i2 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
add %l4, 1, %l4
P2490: !_DWLD [11] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 32], %o5
! move %o5(upper) -> %o0(lower)
srlx %o5, 32, %l7
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_3_252:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_252
nop
P2491: !_DWLD [20] (Int) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_253:
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_3_253:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_253
nop
P2492: !_LD [7] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_254:
lduw [%i1 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2493: !_LD [24] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_3_254:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_254
nop
P2494: !_NOP (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_255:
nop
P2495: !_LD [30] (Int)
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2496: !_LD [18] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_3_255:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_255
nop
P2497: !_LD [28] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_256:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2498: !_DWLD [1] (FP) (Branch target of P2557)
ldd [%i0 + 0], %f0
! 2 addresses covered
ba P2499
nop
TARGET2557:
ba RET2557
nop
P2499: !_LD [4] (Int) (Loop exit)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 4
sethi %hi(0xc0000), %l3
sub %i1, %l3, %i1
lduw [%i1 + 0], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
!--
sethi %hi(0xc0000), %o5
add %i1, %o5, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_3_256:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_256
nop
P2500: !_BLD [8] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_257:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P2501: !_BLD [29] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f32
membar #Sync
! 4 addresses covered
fmovd %f32, %f4
fmovd %f34, %f18
fmovs %f19, %f6
fmovd %f40, %f18
fmovs %f18, %f7
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovd %f4, %f30
fmovd %f6, %f30
!--
loop_exit_3_257:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_257
nop
P2502: !_LD [4] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_258:
lduw [%i1 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2503: !_LD [24] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_3_258:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_258
nop
P2504: !_LD [15] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_259:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2505: !_BLD [21] (FP)
wr %g0, 0xf0, %asi
sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P2506: !_LD [1] (Int) (Loop exit)
lduw [%i0 + 4], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_3_259:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_259
nop
P2507: !_LD [30] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_260:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2508: !_LD [8] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_3_260:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_260
nop
P2509: !_MEMBAR (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_261:
membar #StoreLoad
P2510: !_BLD [21] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_3_261:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_261
nop
P2511: !_BST [30] (maybe <- 0x41000021) (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_262:
wr %g0, 0xf0, %asi
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
! preparing store val #0, next val will be in f32
fmovs %f16, %f20
fadds %f16, %f17, %f16
! preparing store val #1, next val will be in f33
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #2, next val will be in f35
fmovd %f20, %f32
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #3, next val will be in f40
fmovd %f20, %f34
fmovs %f16, %f20
fadds %f16, %f17, %f16
fmovd %f20, %f40
membar #Sync
stda %f32, [%i3 + 0 ] %asi
membar #Sync
loop_exit_3_262:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_262
nop
P2512: !_DWLD [22] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_263:
sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
ldx [%i2 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2513: !_LD [4] (Int) (Loop exit)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 4
sethi %hi(0xc0000), %l6
sub %i1, %l6, %i1
lduw [%i1 + 0], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
sethi %hi(0xc0000), %l3
add %i1, %l3, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_3_263:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_263
nop
P2514: !_SWAP [12] (maybe <- 0x1800023) (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_264:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i3
sub %i0, %i3, %i3
mov %l4, %o0
swap [%i3 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
add %l4, 1, %l4
P2515: !_BLD [18] (FP)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P2516: !_LD [20] (Int) (Loop exit)
sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 0], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_3_264:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_264
nop
P2517: !_BLD [24] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_265:
wr %g0, 0xf0, %asi
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_3_265:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_265
nop
P2518: !_LD [1] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_266:
lduw [%i0 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2519: !_BLD [11] (FP)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P2520: !_LD [21] (Int) (Loop exit)
sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 4], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_3_266:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_266
nop
P2521: !_DWLD [28] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_267:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
P2522: !_LD [5] (Int) (Branch target of P2229)
lduw [%i1 + 4], %o1
! move %o1(lower) -> %o1(upper)
sllx %o1, 32, %o1
ba P2523
nop
TARGET2229:
ba RET2229
nop
P2523: !_LD [8] (Int) (Loop exit) (CBR)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 0], %o5
! move %o5(lower) -> %o1(lower)
or %o5, %o1, %o1
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET2523
nop
RET2523:
! lfsr step begin
srlx %l0, 1, %l3
xnor %l3, %l0, %l3
sllx %l3, 63, %l3
or %l3, %l0, %l0
srlx %l0, 1, %l0
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_3_267:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_267
nop
P2524: !_BLD [5] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_268:
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P2525: !_LD [31] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2526: !_LD [10] (Int) (Loop exit) (Branch target of P2464)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_3_268:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_268
nop
ba P2527
nop
TARGET2464:
ba RET2464
nop
P2527: !_BST [14] (maybe <- 0x41000025) (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_269:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i3
sub %i0, %i3, %i3
! preparing store val #0, next val will be in f32
fmovs %f16, %f20
fadds %f16, %f17, %f16
! preparing store val #1, next val will be in f33
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #2, next val will be in f35
fmovd %f20, %f32
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #3, next val will be in f40
fmovd %f20, %f34
fmovs %f16, %f20
fadds %f16, %f17, %f16
fmovd %f20, %f40
membar #Sync
stda %f32, [%i3 + 0 ] %asi
membar #Sync
P2528: !_MEMBAR (Int) (Loop exit)
membar #StoreLoad
loop_exit_3_269:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_269
nop
P2529: !_ST [4] (maybe <- 0x41000029) (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_270:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 4
sethi %hi(0xc0000), %l6
sub %i1, %l6, %i1
! preparing store val #0, next val will be in f20
fmovs %f16, %f20
fadds %f16, %f17, %f16
st %f20, [%i1 + 0 ]
sethi %hi(0xc0000), %l6
add %i1, %l6, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_3_270:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_270
nop
P2530: !_REPLACEMENT [0] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_271:
sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS3_O), %i2
sub %i0, %i2, %i2
sethi %hi(0x10000), %l7
ld [%i2+0], %l3
st %l3, [%i2+0]
add %i2, %l7, %o5
ld [%o5+0], %l3
st %l3, [%o5+0]
add %o5, %l7, %o5
ld [%o5+0], %l3
st %l3, [%o5+0]
add %o5, %l7, %o5
ld [%o5+0], %l3
st %l3, [%o5+0]
P2531: !_DWLD [0] (Int) (Loop exit)
ldx [%i0 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_3_271:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_271
nop
P2532: !_FLUSHI [29] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_272:
flush %g0
P2533: !_ST [3] (maybe <- 0x1800024) (Int) (Loop exit)
stw %l4, [%i0 + 32 ]
add %l4, 1, %l4
loop_exit_3_272:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_272
nop
P2534: !_DWLD [24] (Int) (Loop entry) (Branch target of P2234)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_273:
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
ldx [%i3 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
ba P2535
nop
TARGET2234:
ba RET2234
nop
P2535: !_BLD [26] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_3_273:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_273
nop
P2536: !_LD [0] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_274:
lduw [%i0 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2537: !_LD [31] (Int) (Loop exit) (CBR)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET2537
nop
RET2537:
! lfsr step begin
srlx %l0, 1, %o5
xnor %o5, %l0, %o5
sllx %o5, 63, %o5
or %o5, %l0, %l0
srlx %l0, 1, %l0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_3_274:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_274
nop
P2538: !_LD [22] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_275:
sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2539: !_DWLD [26] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 8], %l6
! move %l6(lower) -> %o0(lower)
srl %l6, 0, %l3
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_3_275:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_275
nop
P2540: !_REPLACEMENT [6] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_276:
sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS1_O), %i2
sub %i0, %i2, %i2
sethi %hi(0x10000), %o5
ld [%i2+12], %l6
st %l6, [%i2+12]
add %i2, %o5, %l3
ld [%l3+12], %l6
st %l6, [%l3+12]
add %l3, %o5, %l3
ld [%l3+12], %l6
st %l6, [%l3+12]
add %l3, %o5, %l3
ld [%l3+12], %l6
st %l6, [%l3+12]
P2541: !_LD [31] (Int)
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2542: !_LD [12] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 0], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_3_276:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_276
nop
P2543: !_ST [9] (maybe <- 0x1800025) (Int) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_277:
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
stw %l4, [%i3 + 4 ]
add %l4, 1, %l4
loop_exit_3_277:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_277
nop
P2544: !_BLD [6] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_278:
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_3_278:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_278
nop
P2545: !_CAS [21] (maybe <- 0x1800026) (Int) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_279:
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i2
sub %i0, %i2, %i2
add %i2, 4, %l3
lduw [%l3], %o0
mov %o0, %o5
! move %o5(lower) -> %o0(upper)
sllx %o5, 32, %o0
mov %l4, %l7
cas [%l3], %o5, %l7
! move %l7(lower) -> %o0(lower)
srl %l7, 0, %o5
or %o5, %o0, %o0
add %l4, 1, %l4
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_3_279:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_279
nop
P2546: !_CASX [26] (maybe <- 0x1800027) (Int) (Loop entry) (Loop exit) (LE)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_280:
! Change single-word-level endianess (big endian <-> little endian)
sethi %hi(0xff00ff00), %l6
or %l6, %lo(0xff00ff00), %l6
and %l4, %l6, %l3
srl %l3, 8, %l3
sll %l4, 8, %l7
and %l7, %l6, %l7
or %l7, %l3, %l7
srl %l7, 16, %l3
sll %l7, 16, %l7
srl %l7, 0, %l7
or %l7, %l3, %l7
sllx %l7, 32, %l7
wr %g0, 0x88, %asi
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i3
sub %i0, %i3, %i3
add %i3, 8, %l6
ldxa [%l6] %asi, %o5
! move %o5(lower) -> %o0(upper)
sllx %o5, 32, %o0
! move %o5(upper) -> %o0(lower)
srlx %o5, 32, %l3
or %l3, %o0, %o0
mov %o5, %l3
mov %l7, %o5
casxa [%l6] %asi, %l3, %o5
! move %o5(lower) -> %o1(upper)
sllx %o5, 32, %o1
! move %o5(upper) -> %o1(lower)
srlx %o5, 32, %l3
or %l3, %o1, %o1
add %l4, 1, %l4
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_3_280:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_280
nop
P2547: !_LD [14] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_281:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2548: !_LD [26] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_3_281:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_281
nop
P2549: !_LD [31] (Int) (Loop entry) (LE)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_282:
wr %g0, 0x88, %asi
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduwa [%i2 + 32] %asi, %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2550: !_LD [8] (Int) (Loop exit)
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 0], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_3_282:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_282
nop
P2551: !_BLD [26] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_283:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P2552: !_BSTC [31] (maybe <- 0x4100002a) (FP) (Loop exit)
wr %g0, 0xe0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
sub %i0, %i3, %i3
! preparing store val #0, next val will be in f32
fmovs %f16, %f20
fadds %f16, %f17, %f16
! preparing store val #1, next val will be in f33
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #2, next val will be in f35
fmovd %f20, %f32
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #3, next val will be in f40
fmovd %f20, %f34
fmovs %f16, %f20
fadds %f16, %f17, %f16
fmovd %f20, %f40
membar #Sync
stda %f32, [%i3 + 0 ] %asi
membar #Sync
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_3_283:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_283
nop
P2553: !_DWLD [25] (Int) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_284:
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
ldx [%i2 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_3_284:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_284
nop
P2554: !_MEMBAR (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_285:
membar #StoreLoad
P2555: !_BLD [16] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_3_285:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_285
nop
P2556: !_DWLD [31] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_286:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 32], %o0
! move %o0(upper) -> %o0(upper)
P2557: !_LD [19] (Int) (Loop exit) (CBR)
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 32], %l3
! move %l3(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %l3, %o0, %o0
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET2557
nop
RET2557:
! lfsr step begin
srlx %l0, 1, %l6
xnor %l6, %l0, %l6
sllx %l6, 63, %l6
or %l6, %l0, %l0
srlx %l0, 1, %l0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_3_286:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_286
nop
P2558: !_DWLD [9] (Int) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_287:
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
ldx [%i2 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_3_287:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_287
nop
P2559: !_BLD [12] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_288:
wr %g0, 0xf0, %asi
sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P2560: !_ST [24] (maybe <- 0x1800028) (Int) (Loop exit)
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
stw %l4, [%i2 + 0 ]
add %l4, 1, %l4
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_3_288:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_288
nop
P2561: !_DWLD [0] (Int) (Loop entry) (Loop exit) (CBR)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_289:
ldx [%i0 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET2561
nop
RET2561:
! lfsr step begin
srlx %l0, 1, %l7
xnor %l7, %l0, %l7
sllx %l7, 63, %l7
or %l7, %l0, %l0
srlx %l0, 1, %l0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_3_289:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_289
nop
P2562: !_SWAP [18] (maybe <- 0x1800029) (Int) (Loop entry) (Branch target of P2565)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_290:
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
mov %l4, %o0
swap [%i3 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
add %l4, 1, %l4
ba P2563
nop
TARGET2565:
ba RET2565
nop
P2563: !_DWLD [9] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 0], %l6
! move %l6(upper) -> %o0(lower)
srlx %l6, 32, %l3
or %l3, %o0, %o0
! move %l6(lower) -> %o1(upper)
sllx %l6, 32, %o1
P2564: !_LD [3] (Int) (Loop exit)
lduw [%i0 + 32], %o5
! move %o5(lower) -> %o1(lower)
or %o5, %o1, %o1
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_3_290:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_290
nop
P2565: !_DWLD [4] (Int) (Loop entry) (CBR)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_291:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 4
sethi %hi(0xc0000), %l6
sub %i1, %l6, %i1
ldx [%i1 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET2565
nop
RET2565:
! lfsr step begin
srlx %l0, 1, %l3
xnor %l3, %l0, %l3
sllx %l3, 63, %l3
or %l3, %l0, %l0
srlx %l0, 1, %l0
P2566: !_NOP (Int) (Loop exit)
nop
!---- flushing int results buffer----
mov %o0, %l5
sethi %hi(0xc0000), %l6
add %i1, %l6, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_3_291:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_291
nop
P2567: !_DWLD [15] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_292:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 32], %o0
! move %o0(upper) -> %o0(upper)
P2568: !_LD [6] (Int) (Loop exit)
lduw [%i1 + 12], %l7
! move %l7(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_3_292:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_292
nop
P2569: !_LD [27] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_293:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2570: !_LD [31] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_3_293:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_293
nop
P2571: !_LD [19] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_294:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2572: !_LD [21] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 4], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_3_294:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_294
nop
P2573: !_LD [7] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_295:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 7
sethi %hi(0xc0000), %l3
sub %i1, %l3, %i1
lduw [%i1 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2574: !_BLD [14] (FP)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P2575: !_LD [11] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
sethi %hi(0xc0000), %l7
add %i1, %l7, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_3_295:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_295
nop
P2576: !_SWAP [18] (maybe <- 0x180002a) (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_296:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
sub %i0, %i2, %i2
mov %l4, %o0
swap [%i2 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
add %l4, 1, %l4
P2577: !_LD [21] (FP)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
sub %i0, %i3, %i3
ld [%i3 + 4], %f0
! 1 addresses covered
P2578: !_LD [14] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
loop_exit_3_296:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_296
nop
P2579: !_BLD [9] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_297:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_3_297:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_297
nop
P2580: !_BLD [20] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_298:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P2581: !_BLD [29] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f32
membar #Sync
! 4 addresses covered
fmovd %f32, %f4
fmovd %f34, %f18
fmovs %f19, %f6
fmovd %f40, %f18
fmovs %f18, %f7
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovd %f4, %f30
fmovd %f6, %f30
!--
loop_exit_3_298:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_298
nop
P2582: !_DWLD [29] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_299:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
P2583: !_BLD [13] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_3_299:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_299
nop
P2584: !_LD [11] (Int) (Loop entry) (LE)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_300:
wr %g0, 0x88, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduwa [%i2 + 32] %asi, %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2585: !_LD [13] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 4], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_3_300:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_300
nop
P2586: !_LD [30] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_301:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2587: !_LD [2] (Int) (Loop exit)
lduw [%i0 + 12], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_3_301:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_301
nop
P2588: !_DWLD [22] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_302:
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2589: !_LD [1] (Int) (Loop exit)
lduw [%i0 + 4], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_3_302:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_302
nop
P2590: !_BSTC [3] (maybe <- 0x4100002e) (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_303:
wr %g0, 0xe0, %asi
! preparing store val #0, next val will be in f32
fmovs %f16, %f20
fadds %f16, %f17, %f16
! preparing store val #1, next val will be in f33
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #2, next val will be in f35
fmovd %f20, %f32
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #3, next val will be in f40
fmovd %f20, %f34
fmovs %f16, %f20
fadds %f16, %f17, %f16
fmovd %f20, %f40
membar #Sync
stda %f32, [%i0 + 0 ] %asi
membar #Sync
P2591: !_DWLD [2] (Int) (LE)
wr %g0, 0x88, %asi
ldxa [%i0 + 8] %asi, %l6
! move %l6(upper) -> %o0(upper)
or %l6, %g0, %o0
P2592: !_LD [27] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 32], %o5
! move %o5(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_3_303:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_303
nop
P2593: !_LD [6] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_304:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 6
sethi %hi(0xc0000), %l6
sub %i1, %l6, %i1
lduw [%i1 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2594: !_BLD [2] (FP)
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i0 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P2595: !_LD [4] (Int) (Loop exit)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #2
!Logical addr: 4
sethi %hi(0xc0000), %l3
sub %i1, %l3, %i1
lduw [%i1 + 0], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
sethi %hi(0x180000), %o5
add %i1, %o5, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_3_304:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_304
nop
P2596: !_DWLD [15] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_305:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i3
sub %i0, %i3, %i3
ldd [%i3 + 32], %f0
! 1 addresses covered
P2597: !_DWLD [6] (Int)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 6
sethi %hi(0xc0000), %l3
sub %i1, %l3, %i1
ldx [%i1 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2598: !_LD [21] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
sethi %hi(0xc0000), %l6
add %i1, %l6, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_3_305:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_305
nop
P2599: !_DWLD [15] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_306:
sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
ldx [%i3 + 32], %o0
! move %o0(upper) -> %o0(upper)
P2600: !_LD [3] (Int) (Loop exit)
lduw [%i0 + 32], %l7
! move %l7(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_3_306:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_306
nop
P2601: !_PREFETCH [10] (Int) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_307:
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
prefetch [%i2 + 12], 1
loop_exit_3_307:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_307
nop
P2602: !_BLD [28] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_308:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P2603: !_BLD [7] (FP) (Loop exit) (Branch target of P2188)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 7
sethi %hi(0xc0000), %l7
sub %i1, %l7, %i1
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f32
membar #Sync
! 4 addresses covered
fmovd %f32, %f4
fmovd %f34, %f18
fmovs %f19, %f6
fmovd %f40, %f18
fmovs %f18, %f7
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovd %f4, %f30
fmovd %f6, %f30
!--
sethi %hi(0xc0000), %o5
add %i1, %o5, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_3_308:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_308
nop
ba P2604
nop
TARGET2188:
ba RET2188
nop
P2604: !_LD [1] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_309:
lduw [%i0 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2605: !_LD [19] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 32], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_3_309:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_309
nop
P2606: !_BST [23] (maybe <- 0x41000032) (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_310:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
sub %i0, %i3, %i3
! preparing store val #0, next val will be in f32
fmovs %f16, %f20
fadds %f16, %f17, %f16
! preparing store val #1, next val will be in f33
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #2, next val will be in f35
fmovd %f20, %f32
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #3, next val will be in f40
fmovd %f20, %f34
fmovs %f16, %f20
fadds %f16, %f17, %f16
fmovd %f20, %f40
membar #Sync
stda %f32, [%i3 + 0 ] %asi
membar #Sync
P2607: !_LD [30] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2608: !_LD [18] (Int) (Loop exit) (Branch target of P2119)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_3_310:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_310
nop
ba P2609
nop
TARGET2119:
ba RET2119
nop
P2609: !_BLD [8] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_311:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_3_311:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_311
nop
P2610: !_LD [26] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_312:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2611: !_BLD [4] (FP)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 4
sethi %hi(0xc0000), %o5
sub %i1, %o5, %i1
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P2612: !_LD [4] (Int) (Loop exit)
lduw [%i1 + 0], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
sethi %hi(0xc0000), %l7
add %i1, %l7, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_3_312:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_312
nop
P2613: !_BLD [22] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_313:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P2614: !_LD [22] (Int)
lduw [%i2 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2615: !_LD [2] (Int) (Loop exit) (Branch target of P2117)
lduw [%i0 + 12], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_3_313:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_313
nop
ba P2616
nop
TARGET2117:
ba RET2117
nop
P2616: !_DWLD [1] (Int) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_314:
ldx [%i0 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_3_314:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_314
nop
P2617: !_DWLD [24] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_315:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i3
sub %i0, %i3, %i3
ldd [%i3 + 0], %f0
! 2 addresses covered
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
!--
loop_exit_3_315:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_315
nop
P2618: !_BLD [16] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_316:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_3_316:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_316
nop
P2619: !_DWLD [25] (Int) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_317:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_3_317:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_317
nop
P2620: !_DWLD [6] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_318:
ldx [%i1 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2621: !_BLD [15] (FP)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P2622: !_LD [7] (Int) (Loop exit)
lduw [%i1 + 32], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_3_318:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_318
nop
P2623: !_CASX [5] (maybe <- 0x180002b) (Int) (Loop entry) (Branch target of P1986)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_319:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 5
sethi %hi(0xc0000), %l7
sub %i1, %l7, %i1
ldx [%i1], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
mov %o0, %o5
sllx %l4, 32, %o1
add %l4, 1, %l4
or %l4, %o1, %o1
casx [%i1], %o5, %o1
! move %o1(upper) -> %o1(upper)
! move %o1(lower) -> %o1(lower)
add %l4, 1, %l4
ba P2624
nop
TARGET1986:
ba RET1986
nop
P2624: !_BLD [30] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
sethi %hi(0xc0000), %o5
add %i1, %o5, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_3_319:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_319
nop
P2625: !_BLD [4] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_320:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 4
sethi %hi(0xc0000), %l3
sub %i1, %l3, %i1
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P2626: !_LD [8] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2627: !_LD [12] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
sethi %hi(0xc0000), %l7
add %i1, %l7, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_3_320:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_320
nop
P2628: !_LD [30] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_321:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2629: !_LD [12] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_3_321:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_321
nop
P2630: !_BLD [8] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_322:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P2631: !_LD [20] (Int)
sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2632: !_LD [24] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 0], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_3_322:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_322
nop
P2633: !_DWLD [12] (Int) (Loop entry) (Branch target of P2389)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_323:
sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
ldx [%i3 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
ba P2634
nop
TARGET2389:
ba RET2389
nop
P2634: !_LD [30] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %o1
! move %o1(lower) -> %o1(upper)
sllx %o1, 32, %o1
P2635: !_LD [19] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %l7
! move %l7(lower) -> %o1(lower)
or %l7, %o1, %o1
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_3_323:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_323
nop
P2636: !_BLD [10] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_324:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P2637: !_DWLD [1] (Int) (Loop exit)
ldx [%i0 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_3_324:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_324
nop
P2638: !_LD [18] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_325:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2639: !_BLD [11] (FP)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P2640: !_LD [30] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_3_325:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_325
nop
P2641: !_BLD [6] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_326:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 6
sethi %hi(0xc0000), %l7
sub %i1, %l7, %i1
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
sethi %hi(0xc0000), %o5
add %i1, %o5, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_3_326:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_326
nop
P2642: !_LD [8] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_327:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2643: !_LD [15] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_3_327:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_327
nop
P2644: !_DWLD [4] (Int) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_328:
ldx [%i1 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_3_328:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_328
nop
P2645: !_BSTC [29] (maybe <- 0x41000036) (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_329:
wr %g0, 0xe0, %asi
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
! preparing store val #0, next val will be in f32
fmovs %f16, %f20
fadds %f16, %f17, %f16
! preparing store val #1, next val will be in f33
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #2, next val will be in f35
fmovd %f20, %f32
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #3, next val will be in f40
fmovd %f20, %f34
fmovs %f16, %f20
fadds %f16, %f17, %f16
fmovd %f20, %f40
membar #Sync
stda %f32, [%i2 + 0 ] %asi
membar #Sync
loop_exit_3_329:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_329
nop
P2646: !_LD [10] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_330:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2647: !_LD [15] (Int) (Loop exit) (Branch target of P2124)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 32], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_3_330:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_330
nop
ba P2648
nop
TARGET2124:
ba RET2124
nop
P2648: !_DWLD [15] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_3_331:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i3
sub %i0, %i3, %i3
ldd [%i3 + 32], %f0
! 1 addresses covered
P2649: !_LD [21] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2650: !_LD [21] (Int) (Loop exit)
lduw [%i2 + 4], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
loop_exit_3_331:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_331
nop
P2651: !_LD [26] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_3_332:
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2652: !_LD [17] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_3_332:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_3_332
nop
P2653: !_MEMBAR (Int)
membar #StoreLoad
END_NODES3: ! Test instruction sequence for CPU 3 ends
sethi %hi(0xdead0e0f), %l6
or %l6, %lo(0xdead0e0f), %l6
! move %l6(lower) -> %o0(upper)
sllx %l6, 32, %o0
stw %l6, [%i5]
ld [%i5], %f0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
restore
retl
nop
!-----------------
! register usage:
! %i0 %i1 : base registers for first 2 regions
! %i2 %i3 : cache registers for 8 regions
! %i4 fixed pointer to per-cpu results area
! %l1 moving pointer to per-cpu FP results area
! %o7 moving pointer to per-cpu integer results area
! %i5 pointer to per-cpu private area
! %l0 holds lfsr, used as source of random bits
! %l2 loop count register
! %f16 running counter for unique fp store values
! %f17 holds increment value for fp counter
! %l4 running counter for unique integer store values (increment value is always 1)
! %l5 move-to register for load values (simulation only)
! %f30 move-to register for FP values (simulation only)
! %l3 %l6 %l7 %o5 : 4 temporary registers
! %o0 %o1 %o2 %o3 %o4 : 5 integer results buffer registers
! %f0-f15 FP results buffer registers
! %f32-f47 FP block load/store registers
func4:
! 1000 (dynamic) instruction sequence begins
save %sp, -192, %sp
! Force %i0-%i3 to be 64-byte aligned
add %i0, 63, %i0
andn %i0, 63, %i0
add %i1, 63, %i1
andn %i1, 63, %i1
add %i2, 63, %i2
andn %i2, 63, %i2
add %i3, 63, %i3
andn %i3, 63, %i3
add %i4, 63, %i4
andn %i4, 63, %i4
add %i5, 63, %i5
andn %i5, 63, %i5
! Initialize pointer to FP load results area
mov %i4, %l1
! Initialize pointer to integer load results area
sethi %hi(0x80000), %o7
or %o7, %lo(0x80000), %o7
add %o7, %l1, %o7
! Initialize %f0-%f62 to 0xdeadbee0deadbee1
sethi %hi(0xdeadbee0), %l3
or %l3, %lo(0xdeadbee0), %l3
stw %l3, [%i5]
sethi %hi(0xdeadbee1), %l3
or %l3, %lo(0xdeadbee1), %l3
stw %l3, [%i5+4]
ldd [%i5], %f0
fmovd %f0, %f2
fmovd %f0, %f4
fmovd %f0, %f6
fmovd %f0, %f8
fmovd %f0, %f10
fmovd %f0, %f12
fmovd %f0, %f14
fmovd %f0, %f16
fmovd %f0, %f18
fmovd %f0, %f20
fmovd %f0, %f22
fmovd %f0, %f24
fmovd %f0, %f26
fmovd %f0, %f28
fmovd %f0, %f30
fmovd %f0, %f32
fmovd %f0, %f34
fmovd %f0, %f36
fmovd %f0, %f38
fmovd %f0, %f40
fmovd %f0, %f42
fmovd %f0, %f44
fmovd %f0, %f46
fmovd %f0, %f48
fmovd %f0, %f50
fmovd %f0, %f52
fmovd %f0, %f54
fmovd %f0, %f56
fmovd %f0, %f58
fmovd %f0, %f60
fmovd %f0, %f62
! Signature for extract_loads script to start extracting load values for this stream
sethi %hi(0x04deade1), %l3
or %l3, %lo(0x04deade1), %l3
stw %l3, [%i5]
ld [%i5], %f16
! Initialize running integer counter in register %l4
sethi %hi(0x2000001), %l4
or %l4, %lo(0x2000001), %l4
! Initialize running FP counter in register %f16
sethi %hi(0x41800001), %l3
or %l3, %lo(0x41800001), %l3
stw %l3, [%i5]
ld [%i5], %f16
! Initialize FP counter increment value in register %f17 (constant)
sethi %hi(0x36000000), %l3
or %l3, %lo(0x36000000), %l3
stw %l3, [%i5]
ld [%i5], %f17
! Initialize LFSR to 0x2200^4
sethi %hi(0x2200), %l0
or %l0, %lo(0x2200), %l0
mulx %l0, %l0, %l0
mulx %l0, %l0, %l0
BEGIN_NODES4: ! Test instruction sequence for CPU 4 begins
P2654: !_LD [19] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_0:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2655: !_LD [23] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 32], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_4_0:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_0
nop
P2656: !_LD [3] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_1:
lduw [%i0 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2657: !_DWLD [12] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 0], %l3
! move %l3(upper) -> %o0(lower)
srlx %l3, 32, %o5
or %o5, %o0, %o0
! move %l3(lower) -> %o1(upper)
sllx %l3, 32, %o1
P2658: !_LD [6] (Int) (Loop exit)
lduw [%i1 + 12], %l7
! move %l7(lower) -> %o1(lower)
or %l7, %o1, %o1
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_4_1:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_1
nop
P2659: !_DWLD [23] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_2:
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 32], %o0
! move %o0(upper) -> %o0(upper)
P2660: !_LD [5] (Int) (Loop exit)
lduw [%i1 + 4], %l3
! move %l3(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_4_2:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_2
nop
P2661: !_ST [8] (maybe <- 0x41800001) (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_3:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i3
sub %i0, %i3, %i3
! preparing store val #0, next val will be in f20
fmovs %f16, %f20
fadds %f16, %f17, %f16
st %f20, [%i3 + 0 ]
P2662: !_DWLD [30] (FP) (Loop exit)
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
ldd [%i2 + 8], %f0
! 1 addresses covered
fmovs %f1, %f0
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
loop_exit_4_3:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_3
nop
P2663: !_NOP (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_4:
nop
P2664: !_BLD [0] (FP) (Loop exit)
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i0 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_4_4:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_4
nop
P2665: !_LD [14] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_5:
sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2666: !_BLD [8] (FP)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P2667: !_LD [5] (Int) (Loop exit)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 5
sethi %hi(0xc0000), %l3
sub %i1, %l3, %i1
lduw [%i1 + 4], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
sethi %hi(0xc0000), %o5
add %i1, %o5, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_4_5:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_5
nop
P2668: !_BLD [22] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_6:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_4_6:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_6
nop
P2669: !_BLD [10] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_7:
wr %g0, 0xf0, %asi
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P2670: !_MEMBAR (Int) (Loop exit)
membar #StoreLoad
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_4_7:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_7
nop
P2671: !_DWLD [8] (Int) (Loop entry) (Loop exit) (CBR)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_8:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET2671
nop
RET2671:
! lfsr step begin
srlx %l0, 1, %l7
xnor %l7, %l0, %l7
sllx %l7, 63, %l7
or %l7, %l0, %l0
srlx %l0, 1, %l0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_4_8:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_8
nop
P2672: !_BLD [28] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_9:
wr %g0, 0xf0, %asi
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P2673: !_BLD [17] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f32
membar #Sync
! 4 addresses covered
fmovd %f32, %f4
fmovd %f34, %f18
fmovs %f19, %f6
fmovd %f40, %f18
fmovs %f18, %f7
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovd %f4, %f30
fmovd %f6, %f30
!--
loop_exit_4_9:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_9
nop
P2674: !_BLD [27] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_10:
wr %g0, 0xf0, %asi
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_4_10:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_10
nop
P2675: !_LD [16] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_11:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2676: !_LD [19] (Int) (Loop exit)
lduw [%i3 + 32], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_4_11:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_11
nop
P2677: !_BLD [22] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_12:
wr %g0, 0xf0, %asi
sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P2678: !_BLD [21] (FP) (Loop exit)
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i2 + 0] %asi, %f32
membar #Sync
! 4 addresses covered
fmovd %f32, %f4
fmovd %f34, %f18
fmovs %f19, %f6
fmovd %f40, %f18
fmovs %f18, %f7
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovd %f4, %f30
fmovd %f6, %f30
!--
loop_exit_4_12:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_12
nop
P2679: !_LD [25] (Int) (Loop entry) (LE)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_13:
wr %g0, 0x88, %asi
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduwa [%i3 + 4] %asi, %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2680: !_LD [31] (Int) (Loop exit)
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 32], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_4_13:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_13
nop
P2681: !_LD [11] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_14:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2682: !_LD [27] (Int) (Loop exit) (Branch target of P2671)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 32], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_4_14:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_14
nop
ba P2683
nop
TARGET2671:
ba RET2671
nop
P2683: !_LD [5] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_15:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 5
sethi %hi(0xc0000), %o5
sub %i1, %o5, %i1
lduw [%i1 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2684: !_LD [19] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
sethi %hi(0xc0000), %l3
add %i1, %l3, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_4_15:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_15
nop
P2685: !_BLD [24] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_16:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_4_16:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_16
nop
P2686: !_DWLD [28] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_17:
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
ldx [%i3 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
P2687: !_LD [23] (Int) (LE)
wr %g0, 0x88, %asi
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduwa [%i2 + 32] %asi, %o1
! move %o1(lower) -> %o1(upper)
sllx %o1, 32, %o1
P2688: !_LD [15] (Int) (Loop exit) (LE)
wr %g0, 0x88, %asi
sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduwa [%i3 + 32] %asi, %l6
! move %l6(lower) -> %o1(lower)
or %l6, %o1, %o1
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_4_17:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_17
nop
P2689: !_BLD [19] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_18:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P2690: !_DWLD [2] (Int)
ldx [%i0 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2691: !_LD [24] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_4_18:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_18
nop
P2692: !_BLD [26] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_19:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P2693: !_LD [28] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2694: !_LD [2] (Int) (Loop exit)
lduw [%i0 + 12], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_4_19:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_19
nop
P2695: !_BLD [28] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_20:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_4_20:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_20
nop
P2696: !_BLD [20] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_21:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_4_21:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_21
nop
P2697: !_DWLD [12] (Int) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_22:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_4_22:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_22
nop
P2698: !_DWLD [0] (Int) (Loop entry) (Loop exit) (CBR)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_23:
ldx [%i0 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET2698
nop
RET2698:
! lfsr step begin
srlx %l0, 1, %l6
xnor %l6, %l0, %l6
sllx %l6, 63, %l6
or %l6, %l0, %l0
srlx %l0, 1, %l0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_4_23:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_23
nop
P2699: !_LD [27] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_24:
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2700: !_LD [25] (Int) (Loop exit)
lduw [%i3 + 4], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_4_24:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_24
nop
P2701: !_BLD [5] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_25:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 5
sethi %hi(0xc0000), %l6
sub %i1, %l6, %i1
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P2702: !_BLD [14] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f32
membar #Sync
! 4 addresses covered
fmovd %f32, %f4
fmovd %f34, %f18
fmovs %f19, %f6
fmovd %f40, %f18
fmovs %f18, %f7
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovd %f4, %f30
fmovd %f6, %f30
!--
sethi %hi(0xc0000), %l7
add %i1, %l7, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_4_25:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_25
nop
P2703: !_BLD [29] (FP) (Loop entry) (Branch target of P3102)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_26:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
ba P2704
nop
TARGET3102:
ba RET3102
nop
P2704: !_DWLD [15] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 32], %o0
! move %o0(upper) -> %o0(upper)
P2705: !_LD [0] (Int) (Loop exit)
lduw [%i0 + 0], %l3
! move %l3(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_4_26:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_26
nop
P2706: !_LD [23] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_27:
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2707: !_LD [23] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 32], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_4_27:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_27
nop
P2708: !_LD [1] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_28:
lduw [%i0 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2709: !_DWLD [4] (Int)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 4
sethi %hi(0xc0000), %l7
sub %i1, %l7, %i1
ldx [%i1 + 0], %l3
! move %l3(upper) -> %o0(lower)
srlx %l3, 32, %o5
or %o5, %o0, %o0
! move %l3(lower) -> %o1(upper)
sllx %l3, 32, %o1
P2710: !_LD [22] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %l7
! move %l7(lower) -> %o1(lower)
or %l7, %o1, %o1
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
sethi %hi(0xc0000), %o5
add %i1, %o5, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_4_28:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_28
nop
P2711: !_BLD [30] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_29:
wr %g0, 0xf0, %asi
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_4_29:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_29
nop
P2712: !_CASX [12] (maybe <- 0x2000001) (Int) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_30:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i3
sub %i0, %i3, %i3
ldx [%i3], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
mov %o0, %l7
sllx %l4, 32, %o1
add %l4, 1, %l4
or %l4, %o1, %o1
casx [%i3], %l7, %o1
! move %o1(upper) -> %o1(upper)
! move %o1(lower) -> %o1(lower)
add %l4, 1, %l4
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_4_30:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_30
nop
P2713: !_LD [16] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_31:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2714: !_LD [1] (Int) (Loop exit)
lduw [%i0 + 4], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_4_31:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_31
nop
P2715: !_BSTC [24] (maybe <- 0x41800002) (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_32:
wr %g0, 0xe0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
sub %i0, %i3, %i3
! preparing store val #0, next val will be in f32
fmovs %f16, %f20
fadds %f16, %f17, %f16
! preparing store val #1, next val will be in f33
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #2, next val will be in f35
fmovd %f20, %f32
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #3, next val will be in f40
fmovd %f20, %f34
fmovs %f16, %f20
fadds %f16, %f17, %f16
fmovd %f20, %f40
membar #Sync
stda %f32, [%i3 + 0 ] %asi
membar #Sync
P2716: !_BLD [13] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_4_32:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_32
nop
P2717: !_LD [26] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_33:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2718: !_BST [28] (maybe <- 0x41800006) (FP)
wr %g0, 0xf0, %asi
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
! preparing store val #0, next val will be in f32
fmovs %f16, %f20
fadds %f16, %f17, %f16
! preparing store val #1, next val will be in f33
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #2, next val will be in f35
fmovd %f20, %f32
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #3, next val will be in f40
fmovd %f20, %f34
fmovs %f16, %f20
fadds %f16, %f17, %f16
fmovd %f20, %f40
membar #Sync
stda %f32, [%i2 + 0 ] %asi
membar #Sync
P2719: !_LD [15] (Int) (Loop exit) (CBR)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET2719
nop
RET2719:
! lfsr step begin
srlx %l0, 1, %o5
xnor %o5, %l0, %o5
sllx %o5, 63, %o5
or %o5, %l0, %l0
srlx %l0, 1, %l0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_4_33:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_33
nop
P2720: !_LD [3] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_34:
lduw [%i0 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2721: !_LD [13] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_4_34:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_34
nop
P2722: !_DWLD [3] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_35:
ldx [%i0 + 32], %o0
! move %o0(upper) -> %o0(upper)
P2723: !_LD [16] (Int) (Loop exit)
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 0], %o5
! move %o5(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_4_35:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_35
nop
P2724: !_DWLD [1] (Int) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_36:
ldx [%i0 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_4_36:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_36
nop
P2725: !_BLD [23] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_37:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P2726: !_DWLD [28] (Int) (Loop exit)
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
ldx [%i3 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_4_37:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_37
nop
P2727: !_DWLD [26] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_38:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2728: !_DWLD [25] (Int)
ldx [%i2 + 0], %l3
! move %l3(upper) -> %o0(lower)
srlx %l3, 32, %o5
or %o5, %o0, %o0
! move %l3(lower) -> %o1(upper)
sllx %l3, 32, %o1
P2729: !_LD [24] (Int) (Loop exit)
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 0], %o5
! move %o5(lower) -> %o1(lower)
or %o5, %o1, %o1
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_4_38:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_38
nop
P2730: !_LD [21] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_39:
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2731: !_BLD [23] (FP)
wr %g0, 0xf0, %asi
sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P2732: !_LD [29] (Int) (Loop exit)
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 4], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_4_39:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_39
nop
P2733: !_DWLD [5] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_40:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 5
sethi %hi(0xc0000), %o5
sub %i1, %o5, %i1
ldx [%i1 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
P2734: !_LD [20] (Int)
sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 0], %o1
! move %o1(lower) -> %o1(upper)
sllx %o1, 32, %o1
P2735: !_LD [8] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 0], %l7
! move %l7(lower) -> %o1(lower)
or %l7, %o1, %o1
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
sethi %hi(0xc0000), %o5
add %i1, %o5, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_4_40:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_40
nop
P2736: !_BLD [1] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_41:
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i0 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_4_41:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_41
nop
P2737: !_DWLD [22] (FP) (Loop entry) (Loop exit) (CBR)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_42:
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i3
sub %i0, %i3, %i3
ldd [%i3 + 8], %f0
! 1 addresses covered
fmovs %f1, %f0
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET2737
nop
RET2737:
! lfsr step begin
srlx %l0, 1, %l7
xnor %l7, %l0, %l7
sllx %l7, 63, %l7
or %l7, %l0, %l0
srlx %l0, 1, %l0
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
loop_exit_4_42:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_42
nop
P2738: !_FLUSHI [2] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_43:
flush %g0
P2739: !_BLD [29] (FP) (Loop exit) (Branch target of P2719)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_4_43:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_43
nop
ba P2740
nop
TARGET2719:
ba RET2719
nop
P2740: !_LD [31] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_44:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2741: !_LD [24] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 0], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_4_44:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_44
nop
P2742: !_LD [10] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_45:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i3
sub %i0, %i3, %i3
ld [%i3 + 12], %f0
! 1 addresses covered
P2743: !_BLD [29] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f32
membar #Sync
! 4 addresses covered
fmovd %f32, %f18
fmovs %f18, %f1
fmovs %f19, %f2
fmovd %f34, %f18
fmovs %f19, %f3
fmovd %f40, %f4
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovs %f4, %f30
!--
loop_exit_4_45:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_45
nop
P2744: !_NOP (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_46:
nop
P2745: !_DWLD [25] (Int) (Loop exit) (LE)
wr %g0, 0x88, %asi
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i3
sub %i0, %i3, %i3
ldxa [%i3 + 0] %asi, %l3
! move %l3(lower) -> %o0(upper)
sllx %l3, 32, %o0
! move %l3(upper) -> %o0(lower)
srlx %l3, 32, %o5
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_4_46:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_46
nop
P2746: !_BLD [21] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_47:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_4_47:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_47
nop
P2747: !_LD [3] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_48:
lduw [%i0 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2748: !_BLD [6] (FP)
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P2749: !_LD [2] (Int) (Loop exit)
lduw [%i0 + 12], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_4_48:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_48
nop
P2750: !_ST [18] (maybe <- 0x2000003) (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_49:
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
stw %l4, [%i3 + 12 ]
add %l4, 1, %l4
P2751: !_BLD [6] (FP) (Loop exit)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 6
sethi %hi(0xc0000), %l6
sub %i1, %l6, %i1
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
sethi %hi(0xc0000), %l7
add %i1, %l7, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_4_49:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_49
nop
P2752: !_DWLD [16] (Int) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_50:
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
ldx [%i2 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_4_50:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_50
nop
P2753: !_DWLD [21] (Int) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_51:
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_4_51:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_51
nop
P2754: !_LD [2] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_52:
lduw [%i0 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2755: !_LD [17] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_4_52:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_52
nop
P2756: !_LD [26] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_53:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2757: !_LD [18] (Int) (Loop exit) (Branch target of P3037)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_4_53:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_53
nop
ba P2758
nop
TARGET3037:
ba RET3037
nop
P2758: !_DWLD [0] (Int) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_54:
ldx [%i0 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_4_54:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_54
nop
P2759: !_DWLD [25] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_55:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
P2760: !_LD [29] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %o1
! move %o1(lower) -> %o1(upper)
sllx %o1, 32, %o1
P2761: !_LD [20] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %l3
! move %l3(lower) -> %o1(lower)
or %l3, %o1, %o1
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_4_55:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_55
nop
P2762: !_DWLD [28] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_56:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
P2763: !_BLD [30] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_4_56:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_56
nop
P2764: !_DWLD [29] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_57:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
P2765: !_CASX [0] (maybe <- 0x2000004) (Int) (Loop exit)
ldx [%i0], %o1
! move %o1(upper) -> %o1(upper)
! move %o1(lower) -> %o1(lower)
mov %o1, %l6
sllx %l4, 32, %o2
add %l4, 1, %l4
or %l4, %o2, %o2
casx [%i0], %l6, %o2
! move %o2(upper) -> %o2(upper)
! move %o2(lower) -> %o2(lower)
add %l4, 1, %l4
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
mov %o2, %l5
loop_exit_4_57:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_57
nop
P2766: !_DWLD [18] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_58:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2767: !_LD [18] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_4_58:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_58
nop
P2768: !_BLD [14] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_59:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P2769: !_BLD [9] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f32
membar #Sync
! 4 addresses covered
fmovd %f32, %f4
fmovd %f34, %f18
fmovs %f19, %f6
fmovd %f40, %f18
fmovs %f18, %f7
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovd %f4, %f30
fmovd %f6, %f30
!--
loop_exit_4_59:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_59
nop
P2770: !_DWLD [30] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_60:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2771: !_LD [7] (Int) (Loop exit)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 7
sethi %hi(0xc0000), %l3
sub %i1, %l3, %i1
lduw [%i1 + 32], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
sethi %hi(0xc0000), %o5
add %i1, %o5, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_4_60:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_60
nop
P2772: !_ST [24] (maybe <- 0x2000006) (Int) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_61:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i2
sub %i0, %i2, %i2
stw %l4, [%i2 + 0 ]
add %l4, 1, %l4
loop_exit_4_61:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_61
nop
P2773: !_BLD [8] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_62:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P2774: !_BLD [22] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f32
membar #Sync
! 4 addresses covered
fmovd %f32, %f4
fmovd %f34, %f18
fmovs %f19, %f6
fmovd %f40, %f18
fmovs %f18, %f7
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovd %f4, %f30
fmovd %f6, %f30
!--
loop_exit_4_62:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_62
nop
P2775: !_BLD [31] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_63:
wr %g0, 0xf0, %asi
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_4_63:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_63
nop
P2776: !_LD [19] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_64:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2777: !_ST [0] (maybe <- 0x4180000a) (FP)
! preparing store val #0, next val will be in f20
fmovs %f16, %f20
fadds %f16, %f17, %f16
st %f20, [%i0 + 0 ]
P2778: !_LD [6] (Int) (Loop exit)
lduw [%i1 + 12], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_4_64:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_64
nop
P2779: !_LD [10] (Int) (Loop entry) (Branch target of P3094)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_65:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
ba P2780
nop
TARGET3094:
ba RET3094
nop
P2780: !_BLD [17] (FP)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P2781: !_LD [3] (Int) (Loop exit) (LE)
wr %g0, 0x88, %asi
lduwa [%i0 + 32] %asi, %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_4_65:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_65
nop
P2782: !_DWLD [6] (Int) (Loop entry) (CBR)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_66:
ldx [%i1 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET2782
nop
RET2782:
! lfsr step begin
srlx %l0, 1, %l7
xnor %l7, %l0, %l7
sllx %l7, 63, %l7
or %l7, %l0, %l0
srlx %l0, 1, %l0
P2783: !_DWLD [29] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 0], %l6
! move %l6(upper) -> %o0(lower)
srlx %l6, 32, %l3
or %l3, %o0, %o0
! move %l6(lower) -> %o1(upper)
sllx %l6, 32, %o1
P2784: !_LD [5] (Int) (Loop exit)
lduw [%i1 + 4], %o5
! move %o5(lower) -> %o1(lower)
or %o5, %o1, %o1
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_4_66:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_66
nop
P2785: !_ST [31] (maybe <- 0x2000007) (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_67:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i2
sub %i0, %i2, %i2
stw %l4, [%i2 + 32 ]
add %l4, 1, %l4
P2786: !_DWLD [16] (FP) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
sub %i0, %i3, %i3
ldd [%i3 + 0], %f0
! 2 addresses covered
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
!--
loop_exit_4_67:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_67
nop
P2787: !_LD [20] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_68:
sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2788: !_LD [21] (Int) (Loop exit)
lduw [%i2 + 4], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_4_68:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_68
nop
P2789: !_LD [5] (Int) (Loop entry) (LE)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_69:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 5
sethi %hi(0xc0000), %l3
sub %i1, %l3, %i1
wr %g0, 0x88, %asi
lduwa [%i1 + 4] %asi, %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2790: !_LD [22] (Int) (Loop exit)
sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 12], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
sethi %hi(0xc0000), %l6
add %i1, %l6, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_4_69:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_69
nop
P2791: !_BLD [21] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_70:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_4_70:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_70
nop
P2792: !_LD [27] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_71:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2793: !_BST [9] (maybe <- 0x4180000b) (FP)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i2
sub %i0, %i2, %i2
! preparing store val #0, next val will be in f32
fmovs %f16, %f20
fadds %f16, %f17, %f16
! preparing store val #1, next val will be in f33
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #2, next val will be in f35
fmovd %f20, %f32
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #3, next val will be in f40
fmovd %f20, %f34
fmovs %f16, %f20
fadds %f16, %f17, %f16
fmovd %f20, %f40
membar #Sync
stda %f32, [%i2 + 0 ] %asi
membar #Sync
P2794: !_LD [10] (Int) (Loop exit)
lduw [%i2 + 12], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_4_71:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_71
nop
P2795: !_BLD [7] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_72:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 7
sethi %hi(0xc0000), %l6
sub %i1, %l6, %i1
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
sethi %hi(0xc0000), %l7
add %i1, %l7, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_4_72:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_72
nop
P2796: !_BLD [2] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_73:
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i0 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_4_73:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_73
nop
P2797: !_DWLD [26] (Int) (Loop entry) (CBR)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_74:
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
ldx [%i3 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET2797
nop
RET2797:
! lfsr step begin
srlx %l0, 1, %o5
xnor %o5, %l0, %o5
sllx %o5, 63, %o5
or %o5, %l0, %l0
srlx %l0, 1, %l0
P2798: !_LD [15] (FP)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i2
sub %i0, %i2, %i2
ld [%i2 + 32], %f0
! 1 addresses covered
P2799: !_LD [14] (Int) (Loop exit)
sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 12], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
loop_exit_4_74:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_74
nop
P2800: !_LD [11] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_75:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2801: !_LD [1] (Int) (Loop exit)
lduw [%i0 + 4], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_4_75:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_75
nop
P2802: !_DWLD [24] (Int) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_76:
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
ldx [%i3 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_4_76:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_76
nop
P2803: !_LD [13] (Int) (Loop entry) (Branch target of P3161)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_77:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
ba P2804
nop
TARGET3161:
ba RET3161
nop
P2804: !_LD [31] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_4_77:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_77
nop
P2805: !_LD [19] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_78:
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2806: !_LD [8] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_4_78:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_78
nop
P2807: !_BLD [18] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_79:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_4_79:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_79
nop
P2808: !_DWLD [22] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_80:
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2809: !_LD [22] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_4_80:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_80
nop
P2810: !_BLD [2] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_81:
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i0 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_4_81:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_81
nop
P2811: !_DWST [13] (maybe <- 0x2000008) (Int) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_82:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i3
sub %i0, %i3, %i3
sllx %l4, 32, %o5
add %l4, 1, %l4
or %o5, %l4, %o5
stx %o5, [%i3 + 0]
add %l4, 1, %l4
loop_exit_4_82:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_82
nop
P2812: !_BLD [7] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_83:
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P2813: !_MEMBAR (Int) (Loop exit)
membar #StoreLoad
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_4_83:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_83
nop
P2814: !_LD [20] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_84:
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2815: !_SWAP [27] (maybe <- 0x200000a) (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
sub %i0, %i3, %i3
mov %l4, %l7
swap [%i3 + 32], %l7
! move %l7(lower) -> %o0(lower)
srl %l7, 0, %l3
or %l3, %o0, %o0
add %l4, 1, %l4
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_4_84:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_84
nop
P2816: !_BLD [17] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_85:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P2817: !_LD [22] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2818: !_LD [17] (Int) (Loop exit)
lduw [%i2 + 4], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_4_85:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_85
nop
P2819: !_LD [6] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_86:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 6
sethi %hi(0xc0000), %l7
sub %i1, %l7, %i1
lduw [%i1 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2820: !_LD [12] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 0], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
sethi %hi(0xc0000), %o5
add %i1, %o5, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_4_86:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_86
nop
P2821: !_BLD [29] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_87:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_4_87:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_87
nop
P2822: !_LD [5] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_88:
lduw [%i1 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2823: !_LD [13] (Int) (Loop exit) (CBR)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET2823
nop
RET2823:
! lfsr step begin
srlx %l0, 1, %o5
xnor %o5, %l0, %o5
sllx %o5, 63, %o5
or %o5, %l0, %l0
srlx %l0, 1, %l0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_4_88:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_88
nop
P2824: !_DWLD [24] (Int) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_89:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_4_89:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_89
nop
P2825: !_DWLD [21] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_90:
sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
ldx [%i2 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
P2826: !_BLD [31] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_4_90:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_90
nop
P2827: !_BLD [24] (FP) (Loop entry) (Loop exit) (Branch target of P3071)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_91:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_4_91:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_91
nop
ba P2828
nop
TARGET3071:
ba RET3071
nop
P2828: !_DWLD [6] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_92:
ldx [%i1 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2829: !_LD [15] (Int) (Loop exit)
sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 32], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_4_92:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_92
nop
P2830: !_DWLD [13] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_93:
sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
ldx [%i2 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
P2831: !_LD [9] (Int)
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 4], %o1
! move %o1(lower) -> %o1(upper)
sllx %o1, 32, %o1
P2832: !_LD [6] (Int) (Loop exit)
lduw [%i1 + 12], %l7
! move %l7(lower) -> %o1(lower)
or %l7, %o1, %o1
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_4_93:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_93
nop
P2833: !_DWLD [24] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_94:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
P2834: !_DWLD [0] (Int) (Loop exit) (Branch target of P3210)
ldx [%i0 + 0], %o1
! move %o1(upper) -> %o1(upper)
! move %o1(lower) -> %o1(lower)
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_4_94:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_94
nop
ba P2835
nop
TARGET3210:
ba RET3210
nop
P2835: !_BLD [18] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_95:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P2836: !_DWST [15] (maybe <- 0x4180000f) (FP) (Loop exit)
sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
! preparing store val #0, next val will be in f20
fmovs %f16, %f20
fadds %f16, %f17, %f16
std %f20, [%i2 + 32]
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_4_95:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_95
nop
P2837: !_DWLD [5] (Int) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_96:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 5
sethi %hi(0xc0000), %o5
sub %i1, %o5, %i1
ldx [%i1 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
sethi %hi(0xc0000), %l7
add %i1, %l7, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_4_96:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_96
nop
P2838: !_BST [0] (maybe <- 0x41800010) (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_97:
wr %g0, 0xf0, %asi
! preparing store val #0, next val will be in f32
fmovs %f16, %f20
fadds %f16, %f17, %f16
! preparing store val #1, next val will be in f33
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #2, next val will be in f35
fmovd %f20, %f32
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #3, next val will be in f40
fmovd %f20, %f34
fmovs %f16, %f20
fadds %f16, %f17, %f16
fmovd %f20, %f40
membar #Sync
stda %f32, [%i0 + 0 ] %asi
membar #Sync
loop_exit_4_97:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_97
nop
P2839: !_BLD [11] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_98:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P2840: !_DWLD [5] (Int) (Loop exit)
ldx [%i1 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_4_98:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_98
nop
P2841: !_DWLD [9] (Int) (Loop entry) (Loop exit) (Branch target of P2823)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_99:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_4_99:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_99
nop
ba P2842
nop
TARGET2823:
ba RET2823
nop
P2842: !_LD [31] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_100:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2843: !_LD [26] (Int) (Loop exit)
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 12], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_4_100:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_100
nop
P2844: !_DWLD [1] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_101:
ldx [%i0 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
P2845: !_DWLD [21] (Int) (Loop exit) (CBR)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 0], %o1
! move %o1(upper) -> %o1(upper)
! move %o1(lower) -> %o1(lower)
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET2845
nop
RET2845:
! lfsr step begin
srlx %l0, 1, %l7
xnor %l7, %l0, %l7
sllx %l7, 63, %l7
or %l7, %l0, %l0
srlx %l0, 1, %l0
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_4_101:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_101
nop
P2846: !_DWST [15] (maybe <- 0x200000b) (Int) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_102:
sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
mov %l4, %l3
sllx %l3, 32, %l3
stx %l3, [%i2 + 32 ]
add %l4, 1, %l4
loop_exit_4_102:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_102
nop
P2847: !_BLD [31] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_103:
wr %g0, 0xf0, %asi
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_4_103:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_103
nop
P2848: !_DWST [18] (maybe <- 0x200000c) (Int) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_104:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i2
sub %i0, %i2, %i2
mov %l4, %l7
stx %l7, [%i2 + 8]
add %l4, 1, %l4
loop_exit_4_104:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_104
nop
P2849: !_BLD [6] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_105:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 6
sethi %hi(0xc0000), %l7
sub %i1, %l7, %i1
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P2850: !_LD [30] (Int)
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2851: !_LD [18] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
sethi %hi(0xc0000), %l3
add %i1, %l3, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_4_105:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_105
nop
P2852: !_DWLD [29] (Int) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_106:
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
ldx [%i3 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_4_106:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_106
nop
P2853: !_DWLD [0] (Int) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_107:
ldx [%i0 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_4_107:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_107
nop
P2854: !_BLD [8] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_108:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P2855: !_BLD [18] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f32
membar #Sync
! 4 addresses covered
fmovd %f32, %f4
fmovd %f34, %f18
fmovs %f19, %f6
fmovd %f40, %f18
fmovs %f18, %f7
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovd %f4, %f30
fmovd %f6, %f30
!--
loop_exit_4_108:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_108
nop
P2856: !_BLD [19] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_109:
wr %g0, 0xf0, %asi
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_4_109:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_109
nop
P2857: !_BSTC [15] (maybe <- 0x41800014) (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_110:
wr %g0, 0xe0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i3
sub %i0, %i3, %i3
! preparing store val #0, next val will be in f32
fmovs %f16, %f20
fadds %f16, %f17, %f16
! preparing store val #1, next val will be in f33
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #2, next val will be in f35
fmovd %f20, %f32
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #3, next val will be in f40
fmovd %f20, %f34
fmovs %f16, %f20
fadds %f16, %f17, %f16
fmovd %f20, %f40
membar #Sync
stda %f32, [%i3 + 0 ] %asi
membar #Sync
P2858: !_DWLD [17] (Int) (Loop exit)
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
ldx [%i2 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_4_110:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_110
nop
P2859: !_DWLD [21] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_111:
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
P2860: !_DWLD [29] (Int) (Loop exit)
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
ldx [%i2 + 0], %o1
! move %o1(upper) -> %o1(upper)
! move %o1(lower) -> %o1(lower)
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_4_111:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_111
nop
P2861: !_BLD [8] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_112:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_4_112:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_112
nop
P2862: !_LD [6] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_113:
lduw [%i1 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2863: !_BLD [28] (FP)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P2864: !_LD [3] (Int) (Loop exit) (Branch target of P3164)
lduw [%i0 + 32], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_4_113:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_113
nop
ba P2865
nop
TARGET3164:
ba RET3164
nop
P2865: !_BST [8] (maybe <- 0x41800018) (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_114:
wr %g0, 0xf0, %asi
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
! preparing store val #0, next val will be in f32
fmovs %f16, %f20
fadds %f16, %f17, %f16
! preparing store val #1, next val will be in f33
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #2, next val will be in f35
fmovd %f20, %f32
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #3, next val will be in f40
fmovd %f20, %f34
fmovs %f16, %f20
fadds %f16, %f17, %f16
fmovd %f20, %f40
membar #Sync
stda %f32, [%i3 + 0 ] %asi
membar #Sync
P2866: !_BLD [7] (FP) (Loop exit)
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_4_114:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_114
nop
P2867: !_DWLD [6] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_115:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 6
sethi %hi(0xc0000), %l6
sub %i1, %l6, %i1
ldx [%i1 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2868: !_DWLD [13] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 0], %l6
! move %l6(upper) -> %o0(lower)
srlx %l6, 32, %l3
or %l3, %o0, %o0
! move %l6(lower) -> %o1(upper)
sllx %l6, 32, %o1
P2869: !_LD [11] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %l3
! move %l3(lower) -> %o1(lower)
or %l3, %o1, %o1
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
sethi %hi(0xc0000), %l6
add %i1, %l6, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_4_115:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_115
nop
P2870: !_DWLD [7] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_116:
ldx [%i1 + 32], %o0
! move %o0(upper) -> %o0(upper)
P2871: !_DWLD [28] (Int) (CBR)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 0], %l7
! move %l7(upper) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
srlx %l7, 32, %l6
or %l6, %o0, %o0
! move %l7(lower) -> %o1(upper)
sllx %l7, 32, %o1
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET2871
nop
RET2871:
! lfsr step begin
srlx %l0, 1, %o5
xnor %o5, %l0, %o5
sllx %o5, 63, %o5
or %o5, %l0, %l0
srlx %l0, 1, %l0
P2872: !_LD [2] (Int) (Loop exit)
lduw [%i0 + 12], %l6
! move %l6(lower) -> %o1(lower)
or %l6, %o1, %o1
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_4_116:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_116
nop
P2873: !_CASX [8] (maybe <- 0x200000d) (Int) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_117:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
sub %i0, %i3, %i3
ldx [%i3], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
mov %o0, %l3
sllx %l4, 32, %o1
add %l4, 1, %l4
or %l4, %o1, %o1
casx [%i3], %l3, %o1
! move %o1(upper) -> %o1(upper)
! move %o1(lower) -> %o1(lower)
add %l4, 1, %l4
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_4_117:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_117
nop
P2874: !_DWLD [19] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_118:
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
ldx [%i2 + 32], %o0
! move %o0(upper) -> %o0(upper)
P2875: !_LD [28] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %l6
! move %l6(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_4_118:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_118
nop
P2876: !_LD [11] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_119:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2877: !_BLD [2] (FP)
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i0 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P2878: !_LD [8] (Int) (Loop exit)
lduw [%i2 + 0], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_4_119:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_119
nop
P2879: !_DWLD [31] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_120:
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
ldx [%i3 + 32], %o0
! move %o0(upper) -> %o0(upper)
P2880: !_CAS [4] (maybe <- 0x200000f) (Int)
lduw [%i1], %o5
mov %o5, %l3
! move %l3(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %l3, %o0, %o0
mov %l4, %o1
cas [%i1], %l3, %o1
! move %o1(lower) -> %o1(upper)
sllx %o1, 32, %o1
add %l4, 1, %l4
P2881: !_LD [21] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %l7
! move %l7(lower) -> %o1(lower)
or %l7, %o1, %o1
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_4_120:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_120
nop
P2882: !_LD [7] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_121:
lduw [%i1 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2883: !_LD [0] (Int) (Loop exit)
lduw [%i0 + 0], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_4_121:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_121
nop
P2884: !_BLD [1] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_122:
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i0 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_4_122:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_122
nop
P2885: !_LD [28] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_123:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2886: !_DWLD [31] (Int) (Loop exit)
ldx [%i3 + 32], %o5
! move %o5(upper) -> %o0(lower)
srlx %o5, 32, %l7
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_4_123:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_123
nop
P2887: !_BLD [19] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_124:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_4_124:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_124
nop
P2888: !_BLD [21] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_125:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_4_125:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_125
nop
P2889: !_LD [20] (Int) (Loop entry) (Branch target of P3190)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_126:
sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
ba P2890
nop
TARGET3190:
ba RET3190
nop
P2890: !_LD [17] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 4], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_4_126:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_126
nop
P2891: !_DWLD [23] (Int) (Loop entry) (Branch target of P3230)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_127:
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 32], %o0
! move %o0(upper) -> %o0(upper)
ba P2892
nop
TARGET3230:
ba RET3230
nop
P2892: !_LD [28] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %l7
! move %l7(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_4_127:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_127
nop
P2893: !_DWLD [14] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_128:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2894: !_LD [24] (Int) (Loop exit)
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 0], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_4_128:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_128
nop
P2895: !_DWLD [30] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_129:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2896: !_BLD [9] (FP)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P2897: !_LD [21] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_4_129:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_129
nop
P2898: !_BLD [12] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_130:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P2899: !_BLD [28] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f32
membar #Sync
! 4 addresses covered
fmovd %f32, %f4
fmovd %f34, %f18
fmovs %f19, %f6
fmovd %f40, %f18
fmovs %f18, %f7
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovd %f4, %f30
fmovd %f6, %f30
!--
loop_exit_4_130:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_130
nop
P2900: !_BLD [6] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_131:
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_4_131:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_131
nop
P2901: !_DWLD [12] (FP) (Loop entry) (Loop exit) (Branch target of P3011)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_132:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i3
sub %i0, %i3, %i3
ldd [%i3 + 0], %f0
! 2 addresses covered
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
!--
loop_exit_4_132:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_132
nop
ba P2902
nop
TARGET3011:
ba RET3011
nop
P2902: !_BLD [29] (FP) (Loop entry) (Loop exit) (CBR)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_133:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET2902
nop
RET2902:
! lfsr step begin
srlx %l0, 1, %l7
xnor %l7, %l0, %l7
sllx %l7, 63, %l7
or %l7, %l0, %l0
srlx %l0, 1, %l0
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_4_133:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_133
nop
P2903: !_BLD [8] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_134:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_4_134:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_134
nop
P2904: !_BLD [11] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_135:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P2905: !_SWAP [19] (maybe <- 0x2000010) (Int)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i3
sub %i0, %i3, %i3
mov %l4, %o0
swap [%i3 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
add %l4, 1, %l4
P2906: !_LD [20] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 0], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_4_135:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_135
nop
P2907: !_LD [15] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_136:
sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2908: !_NOP (Int)
nop
P2909: !_LD [28] (Int) (Loop exit)
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 0], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_4_136:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_136
nop
P2910: !_LD [3] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_137:
lduw [%i0 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2911: !_ST [19] (maybe <- 0x2000011) (Int)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
sub %i0, %i3, %i3
stw %l4, [%i3 + 32 ]
add %l4, 1, %l4
P2912: !_LD [7] (Int) (Loop exit)
lduw [%i1 + 32], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_4_137:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_137
nop
P2913: !_ST [5] (maybe <- 0x2000012) (Int) (Loop entry) (LE)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_138:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 5
sethi %hi(0xc0000), %l6
sub %i1, %l6, %i1
wr %g0, 0x88, %asi
! Change single-word-level endianess (big endian <-> little endian)
sethi %hi(0xff00ff00), %o5
or %o5, %lo(0xff00ff00), %o5
and %l4, %o5, %l3
srl %l3, 8, %l3
sll %l4, 8, %l7
and %l7, %o5, %l7
or %l7, %l3, %l7
srl %l7, 16, %l3
sll %l7, 16, %l7
srl %l7, 0, %l7
or %l7, %l3, %l7
stwa %l7, [%i1 + 4] %asi
add %l4, 1, %l4
P2914: !_LD [25] (FP) (Loop exit)
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
ld [%i2 + 4], %f0
! 1 addresses covered
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
sethi %hi(0xc0000), %l6
add %i1, %l6, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_4_138:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_138
nop
P2915: !_DWLD [7] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_139:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 7
sethi %hi(0xc0000), %l7
sub %i1, %l7, %i1
ldx [%i1 + 32], %o0
! move %o0(upper) -> %o0(upper)
P2916: !_LD [18] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %l7
! move %l7(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
sethi %hi(0xc0000), %o5
add %i1, %o5, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_4_139:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_139
nop
P2917: !_FLUSHI [18] (Int) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_140:
flush %g0
loop_exit_4_140:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_140
nop
P2918: !_FLUSHI [12] (Int) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_141:
flush %g0
loop_exit_4_141:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_141
nop
P2919: !_LD [8] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_142:
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2920: !_DWLD [3] (Int) (Loop exit) (LE)
wr %g0, 0x88, %asi
ldxa [%i0 + 32] %asi, %o5
! move %o5(lower) -> %o0(lower)
srl %o5, 0, %l7
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_4_142:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_142
nop
P2921: !_DWLD [22] (Int) (Loop entry) (CBR)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_143:
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET2921
nop
RET2921:
! lfsr step begin
srlx %l0, 1, %l3
xnor %l3, %l0, %l3
sllx %l3, 63, %l3
or %l3, %l0, %l0
srlx %l0, 1, %l0
P2922: !_LD [9] (Int) (Loop exit)
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 4], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_4_143:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_143
nop
P2923: !_BLD [28] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_144:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_4_144:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_144
nop
P2924: !_FLUSHI [1] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_145:
flush %g0
P2925: !_DWLD [27] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 32], %o0
! move %o0(upper) -> %o0(upper)
P2926: !_LD [20] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %l7
! move %l7(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_4_145:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_145
nop
P2927: !_BLD [6] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_146:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 6
sethi %hi(0xc0000), %l3
sub %i1, %l3, %i1
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
sethi %hi(0xc0000), %l6
add %i1, %l6, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_4_146:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_146
nop
P2928: !_DWLD [31] (Int) (Loop entry) (Branch target of P2902)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_147:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 32], %o0
! move %o0(upper) -> %o0(upper)
ba P2929
nop
TARGET2902:
ba RET2902
nop
P2929: !_LD [19] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %l7
! move %l7(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_4_147:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_147
nop
P2930: !_LD [1] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_148:
lduw [%i0 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2931: !_DWLD [2] (Int) (Loop exit) (CBR)
ldx [%i0 + 8], %l3
! move %l3(lower) -> %o0(lower)
srl %l3, 0, %o5
or %o5, %o0, %o0
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET2931
nop
RET2931:
! lfsr step begin
srlx %l0, 1, %l6
xnor %l6, %l0, %l6
sllx %l6, 63, %l6
or %l6, %l0, %l0
srlx %l0, 1, %l0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_4_148:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_148
nop
P2932: !_PREFETCH [16] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_149:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
sub %i0, %i2, %i2
prefetch [%i2 + 0], 1
P2933: !_LD [6] (Int)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 6
sethi %hi(0xc0000), %o5
sub %i1, %o5, %i1
lduw [%i1 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2934: !_LD [25] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 4], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
sethi %hi(0xc0000), %l3
add %i1, %l3, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_4_149:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_149
nop
P2935: !_BLD [6] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_150:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 6
sethi %hi(0xc0000), %l6
sub %i1, %l6, %i1
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
sethi %hi(0xc0000), %l7
add %i1, %l7, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_4_150:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_150
nop
P2936: !_LD [21] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_151:
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2937: !_LD [13] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 4], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_4_151:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_151
nop
P2938: !_DWLD [24] (Int) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_152:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_4_152:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_152
nop
P2939: !_LD [16] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_153:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2940: !_BLD [27] (FP)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P2941: !_LD [26] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_4_153:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_153
nop
P2942: !_DWLD [27] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_154:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 32], %o0
! move %o0(upper) -> %o0(upper)
P2943: !_DWLD [29] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 0], %o5
! move %o5(upper) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
srlx %o5, 32, %l7
or %l7, %o0, %o0
! move %o5(lower) -> %o1(upper)
sllx %o5, 32, %o1
P2944: !_LD [4] (Int) (Loop exit)
lduw [%i1 + 0], %l6
! move %l6(lower) -> %o1(lower)
or %l6, %o1, %o1
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_4_154:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_154
nop
P2945: !_LD [10] (Int) (Loop entry) (LE)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_155:
wr %g0, 0x88, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduwa [%i2 + 12] %asi, %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2946: !_LD [14] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_4_155:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_155
nop
P2947: !_LD [29] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_156:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2948: !_LD [24] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_4_156:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_156
nop
P2949: !_DWLD [13] (Int) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_157:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_4_157:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_157
nop
P2950: !_DWLD [29] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_158:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
P2951: !_LD [7] (Int)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 7
sethi %hi(0xc0000), %l6
sub %i1, %l6, %i1
lduw [%i1 + 32], %o1
! move %o1(lower) -> %o1(upper)
sllx %o1, 32, %o1
P2952: !_LD [7] (Int) (Loop exit)
lduw [%i1 + 32], %l6
! move %l6(lower) -> %o1(lower)
or %l6, %o1, %o1
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
sethi %hi(0xc0000), %l7
add %i1, %l7, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_4_158:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_158
nop
P2953: !_DWLD [22] (Int) (Loop entry) (Branch target of P3291)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_159:
sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
ldx [%i2 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
ba P2954
nop
TARGET3291:
ba RET3291
nop
P2954: !_LD [0] (Int) (Loop exit)
lduw [%i0 + 0], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_4_159:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_159
nop
P2955: !_LD [16] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_160:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2956: !_LD [12] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 0], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_4_160:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_160
nop
P2957: !_FLUSHI [31] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_161:
flush %g0
P2958: !_LD [22] (Int)
sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2959: !_LD [10] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_4_161:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_161
nop
P2960: !_BLD [29] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_162:
wr %g0, 0xf0, %asi
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_4_162:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_162
nop
P2961: !_BLD [5] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_163:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 5
sethi %hi(0xc0000), %o5
sub %i1, %o5, %i1
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
sethi %hi(0xc0000), %l3
add %i1, %l3, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_4_163:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_163
nop
P2962: !_DWLD [10] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_164:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2963: !_LD [30] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_4_164:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_164
nop
P2964: !_LD [21] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_165:
sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
ld [%i2 + 4], %f0
! 1 addresses covered
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
loop_exit_4_165:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_165
nop
P2965: !_BLD [9] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_166:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P2966: !_LD [14] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2967: !_LD [27] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_4_166:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_166
nop
P2968: !_DWLD [10] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_167:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2969: !_LD [13] (Int) (Loop exit) (LE)
wr %g0, 0x88, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduwa [%i3 + 4] %asi, %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_4_167:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_167
nop
P2970: !_DWLD [9] (Int) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_168:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_4_168:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_168
nop
P2971: !_BLD [26] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_169:
wr %g0, 0xf0, %asi
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P2972: !_DWLD [25] (Int) (Loop exit) (Branch target of P2871)
ldx [%i3 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_4_169:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_169
nop
ba P2973
nop
TARGET2871:
ba RET2871
nop
P2973: !_DWLD [19] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_170:
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
ldd [%i2 + 32], %f0
! 1 addresses covered
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
loop_exit_4_170:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_170
nop
P2974: !_LD [8] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_171:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2975: !_LD [6] (Int) (Loop exit)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 6
sethi %hi(0xc0000), %l3
sub %i1, %l3, %i1
lduw [%i1 + 12], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
sethi %hi(0xc0000), %o5
add %i1, %o5, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_4_171:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_171
nop
P2976: !_BLD [16] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_172:
wr %g0, 0xf0, %asi
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_4_172:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_172
nop
P2977: !_BLD [9] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_173:
wr %g0, 0xf0, %asi
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P2978: !_BLD [22] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f32
membar #Sync
! 4 addresses covered
fmovd %f32, %f4
fmovd %f34, %f18
fmovs %f19, %f6
fmovd %f40, %f18
fmovs %f18, %f7
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovd %f4, %f30
fmovd %f6, %f30
!--
loop_exit_4_173:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_173
nop
P2979: !_DWLD [10] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_174:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2980: !_LD [26] (Int) (Loop exit)
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 12], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_4_174:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_174
nop
P2981: !_BLD [27] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_175:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_4_175:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_175
nop
P2982: !_BLD [2] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_176:
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i0 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P2983: !_LD [2] (Int)
lduw [%i0 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2984: !_LD [30] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_4_176:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_176
nop
P2985: !_MEMBAR (Int) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_177:
membar #StoreLoad
loop_exit_4_177:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_177
nop
P2986: !_DWLD [13] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_178:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
P2987: !_BLD [1] (FP) (Loop exit)
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i0 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_4_178:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_178
nop
P2988: !_LD [1] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_179:
lduw [%i0 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2989: !_LD [7] (Int) (Loop exit)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 7
sethi %hi(0xc0000), %l6
sub %i1, %l6, %i1
lduw [%i1 + 32], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
sethi %hi(0xc0000), %l3
add %i1, %l3, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_4_179:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_179
nop
P2990: !_DWLD [9] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_180:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
P2991: !_DWLD [28] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 0], %o1
! move %o1(upper) -> %o1(upper)
! move %o1(lower) -> %o1(lower)
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_4_180:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_180
nop
P2992: !_LD [19] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_181:
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2993: !_BLD [3] (FP) (Branch target of P3183)
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i0 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
ba P2994
nop
TARGET3183:
ba RET3183
nop
P2994: !_LD [3] (Int) (Loop exit)
lduw [%i0 + 32], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_4_181:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_181
nop
P2995: !_DWLD [7] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_182:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 7
sethi %hi(0xc0000), %l6
sub %i1, %l6, %i1
ldx [%i1 + 32], %o0
! move %o0(upper) -> %o0(upper)
P2996: !_LD [18] (Int) (Loop exit)
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 12], %l6
! move %l6(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
sethi %hi(0xc0000), %l7
add %i1, %l7, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_4_182:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_182
nop
P2997: !_DWLD [16] (FP) (Loop entry) (Branch target of P2797)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_183:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
sub %i0, %i2, %i2
ldd [%i2 + 0], %f0
! 2 addresses covered
ba P2998
nop
TARGET2797:
ba RET2797
nop
P2998: !_LD [2] (Int)
lduw [%i0 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P2999: !_LD [18] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
!--
loop_exit_4_183:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_183
nop
P3000: !_DWLD [6] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_184:
ldx [%i1 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3001: !_BLD [14] (FP)
wr %g0, 0xf0, %asi
sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P3002: !_LD [5] (Int) (Loop exit)
lduw [%i1 + 4], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_4_184:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_184
nop
P3003: !_DWLD [2] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_185:
ldx [%i0 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3004: !_LD [9] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 4], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_4_185:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_185
nop
P3005: !_DWLD [1] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_186:
ldx [%i0 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
P3006: !_DWLD [20] (Int) (Loop exit) (CBR)
sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
ldx [%i2 + 0], %o1
! move %o1(upper) -> %o1(upper)
! move %o1(lower) -> %o1(lower)
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET3006
nop
RET3006:
! lfsr step begin
srlx %l0, 1, %o5
xnor %o5, %l0, %o5
sllx %o5, 63, %o5
or %o5, %l0, %l0
srlx %l0, 1, %l0
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_4_186:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_186
nop
P3007: !_BLD [7] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_187:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 7
sethi %hi(0xc0000), %l6
sub %i1, %l6, %i1
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
sethi %hi(0xc0000), %l7
add %i1, %l7, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_4_187:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_187
nop
P3008: !_NOP (Int) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_188:
nop
loop_exit_4_188:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_188
nop
P3009: !_LD [1] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_189:
lduw [%i0 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3010: !_FLUSHI [8] (Int) (Branch target of P2737)
flush %g0
ba P3011
nop
TARGET2737:
ba RET2737
nop
P3011: !_LD [18] (Int) (Loop exit) (CBR)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET3011
nop
RET3011:
! lfsr step begin
srlx %l0, 1, %l7
xnor %l7, %l0, %l7
sllx %l7, 63, %l7
or %l7, %l0, %l0
srlx %l0, 1, %l0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_4_189:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_189
nop
P3012: !_BLD [25] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_190:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P3013: !_DWLD [28] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_4_190:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_190
nop
P3014: !_LD [19] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_191:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3015: !_LD [0] (Int) (Loop exit)
lduw [%i0 + 0], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_4_191:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_191
nop
P3016: !_LD [1] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_192:
lduw [%i0 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3017: !_LD [22] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_4_192:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_192
nop
P3018: !_DWLD [18] (Int) (Loop entry) (LE)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_193:
wr %g0, 0x88, %asi
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i2
sub %i0, %i2, %i2
ldxa [%i2 + 8] %asi, %l6
! move %l6(upper) -> %o0(upper)
or %l6, %g0, %o0
P3019: !_LD [6] (Int) (Loop exit) (Branch target of P2782)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 6
sethi %hi(0xc0000), %l7
sub %i1, %l7, %i1
lduw [%i1 + 12], %l3
! move %l3(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
sethi %hi(0xc0000), %l6
add %i1, %l6, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_4_193:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_193
nop
ba P3020
nop
TARGET2782:
ba RET2782
nop
P3020: !_DWLD [1] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_194:
ldd [%i0 + 0], %f0
! 2 addresses covered
P3021: !_DWLD [12] (Int) (Loop exit) (Branch target of P3168)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
!--
loop_exit_4_194:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_194
nop
ba P3022
nop
TARGET3168:
ba RET3168
nop
P3022: !_DWLD [29] (Int) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_195:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_4_195:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_195
nop
P3023: !_NOP (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_196:
nop
P3024: !_LD [28] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3025: !_LD [24] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 0], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_4_196:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_196
nop
P3026: !_DWLD [18] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_197:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3027: !_LD [13] (FP) (Branch target of P3103)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i2
sub %i0, %i2, %i2
ld [%i2 + 4], %f0
! 1 addresses covered
ba P3028
nop
TARGET3103:
ba RET3103
nop
P3028: !_LD [27] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
loop_exit_4_197:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_197
nop
P3029: !_BST [29] (maybe <- 0x4180001c) (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_198:
wr %g0, 0xf0, %asi
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
! preparing store val #0, next val will be in f32
fmovs %f16, %f20
fadds %f16, %f17, %f16
! preparing store val #1, next val will be in f33
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #2, next val will be in f35
fmovd %f20, %f32
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #3, next val will be in f40
fmovd %f20, %f34
fmovs %f16, %f20
fadds %f16, %f17, %f16
fmovd %f20, %f40
membar #Sync
stda %f32, [%i2 + 0 ] %asi
membar #Sync
P3030: !_BLD [29] (FP) (Loop exit)
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_4_198:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_198
nop
P3031: !_DWLD [10] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_199:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3032: !_LD [29] (Int) (Loop exit)
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 4], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_4_199:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_199
nop
P3033: !_LD [4] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_200:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 4
sethi %hi(0xc0000), %l6
sub %i1, %l6, %i1
lduw [%i1 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3034: !_DWLD [10] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 8], %l6
! move %l6(lower) -> %o0(lower)
srl %l6, 0, %l3
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
sethi %hi(0xc0000), %l7
add %i1, %l7, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_4_200:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_200
nop
P3035: !_LD [24] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_201:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3036: !_LD [14] (Int) (Loop exit) (CBR)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET3036
nop
RET3036:
! lfsr step begin
srlx %l0, 1, %l3
xnor %l3, %l0, %l3
sllx %l3, 63, %l3
or %l3, %l0, %l0
srlx %l0, 1, %l0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_4_201:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_201
nop
P3037: !_BLD [13] (FP) (Loop entry) (Loop exit) (CBR)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_202:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET3037
nop
RET3037:
! lfsr step begin
srlx %l0, 1, %o5
xnor %o5, %l0, %o5
sllx %o5, 63, %o5
or %o5, %l0, %l0
srlx %l0, 1, %l0
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_4_202:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_202
nop
P3038: !_LD [14] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_203:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3039: !_LD [29] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_4_203:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_203
nop
P3040: !_DWLD [31] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_204:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 32], %o0
! move %o0(upper) -> %o0(upper)
P3041: !_DWLD [8] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 0], %o5
! move %o5(upper) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
srlx %o5, 32, %l7
or %l7, %o0, %o0
! move %o5(lower) -> %o1(upper)
sllx %o5, 32, %o1
P3042: !_LD [2] (Int) (Loop exit)
lduw [%i0 + 12], %l6
! move %l6(lower) -> %o1(lower)
or %l6, %o1, %o1
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_4_204:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_204
nop
P3043: !_LD [25] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_205:
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
ld [%i3 + 4], %f0
! 1 addresses covered
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
loop_exit_4_205:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_205
nop
P3044: !_DWLD [4] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_206:
ldx [%i1 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
P3045: !_LD [7] (Int)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 7
sethi %hi(0xc0000), %o5
sub %i1, %o5, %i1
lduw [%i1 + 32], %o1
! move %o1(lower) -> %o1(upper)
sllx %o1, 32, %o1
P3046: !_LD [22] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %o5
! move %o5(lower) -> %o1(lower)
or %o5, %o1, %o1
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
sethi %hi(0xc0000), %l3
add %i1, %l3, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_4_206:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_206
nop
P3047: !_LD [31] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_207:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3048: !_PREFETCH [15] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i2
sub %i0, %i2, %i2
prefetch [%i2 + 32], 1
P3049: !_LD [8] (Int) (Loop exit)
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 0], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_4_207:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_207
nop
P3050: !_DWLD [6] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_208:
ldx [%i1 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3051: !_LD [31] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 32], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_4_208:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_208
nop
P3052: !_LD [29] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_209:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3053: !_LD [3] (Int) (Loop exit) (LE)
wr %g0, 0x88, %asi
lduwa [%i0 + 32] %asi, %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_4_209:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_209
nop
P3054: !_DWST [17] (maybe <- 0x2000013) (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_210:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i2
sub %i0, %i2, %i2
sllx %l4, 32, %l3
add %l4, 1, %l4
or %l3, %l4, %l3
stx %l3, [%i2 + 0]
add %l4, 1, %l4
P3055: !_LD [18] (FP) (Loop exit)
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
ld [%i3 + 12], %f0
! 1 addresses covered
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
loop_exit_4_210:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_210
nop
P3056: !_BLD [4] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_211:
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P3057: !_BST [20] (maybe <- 0x41800020) (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
sub %i0, %i2, %i2
! preparing store val #0, next val will be in f32
fmovs %f16, %f20
fadds %f16, %f17, %f16
! preparing store val #1, next val will be in f33
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #2, next val will be in f35
fmovd %f20, %f32
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #3, next val will be in f40
fmovd %f20, %f34
fmovs %f16, %f20
fadds %f16, %f17, %f16
fmovd %f20, %f40
membar #Sync
stda %f32, [%i2 + 0 ] %asi
membar #Sync
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_4_211:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_211
nop
P3058: !_BLD [5] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_212:
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P3059: !_DWLD [16] (Int) (Loop exit) (Branch target of P3061)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_4_212:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_212
nop
ba P3060
nop
TARGET3061:
ba RET3061
nop
P3060: !_BLD [26] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_213:
wr %g0, 0xf0, %asi
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P3061: !_LD [25] (Int) (CBR)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET3061
nop
RET3061:
! lfsr step begin
srlx %l0, 1, %l6
xnor %l6, %l0, %l6
sllx %l6, 63, %l6
or %l6, %l0, %l0
srlx %l0, 1, %l0
P3062: !_LD [5] (Int) (Loop exit)
lduw [%i1 + 4], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_4_213:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_213
nop
P3063: !_MEMBAR (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_214:
membar #StoreLoad
P3064: !_DWLD [3] (FP) (Loop exit) (Branch target of P2845)
ldd [%i0 + 32], %f0
! 1 addresses covered
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
loop_exit_4_214:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_214
nop
ba P3065
nop
TARGET2845:
ba RET2845
nop
P3065: !_LD [26] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_215:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3066: !_LD [31] (Int) (Loop exit) (Branch target of P2921)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_4_215:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_215
nop
ba P3067
nop
TARGET2921:
ba RET2921
nop
P3067: !_NOP (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_216:
nop
P3068: !_LD [27] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3069: !_LD [24] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_4_216:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_216
nop
P3070: !_DWLD [9] (Int) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_217:
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
ldx [%i2 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_4_217:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_217
nop
P3071: !_REPLACEMENT [31] (Int) (Loop entry) (Loop exit) (CBR)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_218:
sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
sethi %hi(0x10000), %l3
ld [%i3+32], %l7
st %l7, [%i3+32]
add %i3, %l3, %l6
ld [%l6+32], %l7
st %l7, [%l6+32]
add %l6, %l3, %l6
ld [%l6+32], %l7
st %l7, [%l6+32]
add %l6, %l3, %l6
ld [%l6+32], %l7
st %l7, [%l6+32]
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET3071
nop
RET3071:
! lfsr step begin
srlx %l0, 1, %o5
xnor %o5, %l0, %o5
sllx %o5, 63, %o5
or %o5, %l0, %l0
srlx %l0, 1, %l0
loop_exit_4_218:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_218
nop
P3072: !_DWLD [6] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_219:
ldx [%i1 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3073: !_LD [25] (Int) (Loop exit)
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 4], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_4_219:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_219
nop
P3074: !_DWLD [28] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_220:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
P3075: !_DWLD [8] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 0], %o1
! move %o1(upper) -> %o1(upper)
! move %o1(lower) -> %o1(lower)
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_4_220:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_220
nop
P3076: !_FLUSHI [0] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_221:
flush %g0
P3077: !_LD [28] (Int)
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3078: !_LD [13] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_4_221:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_221
nop
P3079: !_DWLD [22] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_222:
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3080: !_LD [20] (Int) (Loop exit)
lduw [%i3 + 0], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_4_222:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_222
nop
P3081: !_LD [2] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_223:
lduw [%i0 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3082: !_LD [29] (Int) (Loop exit)
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 4], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_4_223:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_223
nop
P3083: !_CASX [31] (maybe <- 0x2000015) (Int) (Loop entry) (Loop exit) (LE)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_224:
! Change single-word-level endianess (big endian <-> little endian)
sethi %hi(0xff00ff00), %l6
or %l6, %lo(0xff00ff00), %l6
and %l4, %l6, %l3
srl %l3, 8, %l3
sll %l4, 8, %l7
and %l7, %l6, %l7
or %l7, %l3, %l7
srl %l7, 16, %l3
sll %l7, 16, %l7
srl %l7, 0, %l7
or %l7, %l3, %l7
wr %g0, 0x88, %asi
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
sub %i0, %i3, %i3
add %i3, 32, %l6
ldxa [%l6] %asi, %o5
! move %o5(lower) -> %o0(upper)
sllx %o5, 32, %o0
! move %o5(upper) -> %o0(lower)
srlx %o5, 32, %l3
or %l3, %o0, %o0
mov %o5, %l3
mov %l7, %o5
casxa [%l6] %asi, %l3, %o5
! move %o5(lower) -> %o1(upper)
sllx %o5, 32, %o1
! move %o5(upper) -> %o1(lower)
srlx %o5, 32, %l3
or %l3, %o1, %o1
add %l4, 1, %l4
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_4_224:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_224
nop
P3084: !_DWLD [11] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_225:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 32], %o0
! move %o0(upper) -> %o0(upper)
P3085: !_BLD [20] (FP)
wr %g0, 0xf0, %asi
sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P3086: !_LD [24] (Int) (Loop exit)
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 0], %l6
! move %l6(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_4_225:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_225
nop
P3087: !_FLUSHI [23] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_226:
flush %g0
P3088: !_LD [22] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3089: !_LD [26] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_4_226:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_226
nop
P3090: !_DWLD [19] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_227:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 32], %o0
! move %o0(upper) -> %o0(upper)
P3091: !_DWLD [13] (Int)
sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
ldx [%i2 + 0], %l7
! move %l7(upper) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
srlx %l7, 32, %l6
or %l6, %o0, %o0
! move %l7(lower) -> %o1(upper)
sllx %l7, 32, %o1
P3092: !_LD [27] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %l3
! move %l3(lower) -> %o1(lower)
or %l3, %o1, %o1
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_4_227:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_227
nop
P3093: !_BLD [0] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_228:
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i0 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_4_228:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_228
nop
P3094: !_LD [28] (Int) (Loop entry) (CBR) (Branch target of P3107)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_229:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET3094
nop
RET3094:
! lfsr step begin
srlx %l0, 1, %l7
xnor %l7, %l0, %l7
sllx %l7, 63, %l7
or %l7, %l0, %l0
srlx %l0, 1, %l0
ba P3095
nop
TARGET3107:
ba RET3107
nop
P3095: !_LD [28] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_4_229:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_229
nop
P3096: !_BLD [24] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_230:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P3097: !_BLD [28] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f32
membar #Sync
! 4 addresses covered
fmovd %f32, %f4
fmovd %f34, %f18
fmovs %f19, %f6
fmovd %f40, %f18
fmovs %f18, %f7
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovd %f4, %f30
fmovd %f6, %f30
!--
loop_exit_4_230:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_230
nop
P3098: !_LD [30] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_231:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3099: !_LD [28] (Int) (Loop exit)
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 0], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_4_231:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_231
nop
P3100: !_BLD [15] (FP) (Loop entry) (Loop exit) (Branch target of P3036)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_232:
wr %g0, 0xf0, %asi
sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_4_232:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_232
nop
ba P3101
nop
TARGET3036:
ba RET3036
nop
P3101: !_BLD [9] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_233:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_4_233:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_233
nop
P3102: !_LD [28] (Int) (Loop entry) (CBR)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_234:
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET3102
nop
RET3102:
! lfsr step begin
srlx %l0, 1, %l3
xnor %l3, %l0, %l3
sllx %l3, 63, %l3
or %l3, %l0, %l0
srlx %l0, 1, %l0
P3103: !_LD [31] (Int) (Loop exit) (CBR)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET3103
nop
RET3103:
! lfsr step begin
srlx %l0, 1, %l3
xnor %l3, %l0, %l3
sllx %l3, 63, %l3
or %l3, %l0, %l0
srlx %l0, 1, %l0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_4_234:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_234
nop
P3104: !_DWLD [31] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_235:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 32], %o0
! move %o0(upper) -> %o0(upper)
P3105: !_DWLD [14] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 8], %l7
! move %l7(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
srl %l7, 0, %l6
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_4_235:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_235
nop
P3106: !_BLD [18] (FP) (Loop entry) (Loop exit) (Branch target of P2931)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_236:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_4_236:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_236
nop
ba P3107
nop
TARGET2931:
ba RET2931
nop
P3107: !_FLUSHI [2] (Int) (Loop entry) (Loop exit) (CBR)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_237:
flush %g0
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET3107
nop
RET3107:
! lfsr step begin
srlx %l0, 1, %l7
xnor %l7, %l0, %l7
sllx %l7, 63, %l7
or %l7, %l0, %l0
srlx %l0, 1, %l0
loop_exit_4_237:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_237
nop
P3108: !_DWLD [15] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_238:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 32], %o0
! move %o0(upper) -> %o0(upper)
P3109: !_DWLD [16] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 0], %l3
! move %l3(upper) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
srlx %l3, 32, %o5
or %o5, %o0, %o0
! move %l3(lower) -> %o1(upper)
sllx %l3, 32, %o1
P3110: !_LD [4] (Int) (Loop exit)
lduw [%i1 + 0], %l7
! move %l7(lower) -> %o1(lower)
or %l7, %o1, %o1
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_4_238:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_238
nop
P3111: !_CAS [17] (maybe <- 0x2000016) (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_239:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
sub %i0, %i3, %i3
add %i3, 4, %l7
lduw [%l7], %o0
mov %o0, %l6
! move %l6(lower) -> %o0(upper)
sllx %l6, 32, %o0
mov %l4, %l3
cas [%l7], %l6, %l3
! move %l3(lower) -> %o0(lower)
srl %l3, 0, %l6
or %l6, %o0, %o0
add %l4, 1, %l4
P3112: !_LD [25] (FP) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
sub %i0, %i2, %i2
ld [%i2 + 4], %f0
! 1 addresses covered
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
loop_exit_4_239:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_239
nop
P3113: !_BLD [2] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_240:
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i0 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_4_240:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_240
nop
P3114: !_BLD [12] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_241:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P3115: !_DWLD [11] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 32], %o0
! move %o0(upper) -> %o0(upper)
P3116: !_LD [24] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %l3
! move %l3(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_4_241:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_241
nop
P3117: !_DWLD [4] (Int) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_242:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 4
sethi %hi(0xc0000), %l7
sub %i1, %l7, %i1
ldx [%i1 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
sethi %hi(0xc0000), %l6
add %i1, %l6, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_4_242:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_242
nop
P3118: !_BLD [0] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_243:
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i0 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_4_243:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_243
nop
P3119: !_BLD [18] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_244:
wr %g0, 0xf0, %asi
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_4_244:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_244
nop
P3120: !_FLUSHI [8] (Int) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_245:
flush %g0
loop_exit_4_245:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_245
nop
P3121: !_LD [27] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_246:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3122: !_REPLACEMENT [28] (Int)
sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS3_O), %i2
sub %i0, %i2, %i2
sethi %hi(0x10000), %l6
ld [%i2+0], %o5
st %o5, [%i2+0]
add %i2, %l6, %l7
ld [%l7+0], %o5
st %o5, [%l7+0]
add %l7, %l6, %l7
ld [%l7+0], %o5
st %o5, [%l7+0]
add %l7, %l6, %l7
ld [%l7+0], %o5
st %o5, [%l7+0]
P3123: !_LD [17] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 4], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_4_246:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_246
nop
P3124: !_LD [10] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_247:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3125: !_LD [14] (Int) (Loop exit) (Branch target of P2698)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_4_247:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_247
nop
ba P3126
nop
TARGET2698:
ba RET2698
nop
P3126: !_DWLD [2] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_248:
ldx [%i0 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3127: !_LD [16] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 0], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_4_248:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_248
nop
P3128: !_BLD [11] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_249:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_4_249:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_249
nop
P3129: !_LD [4] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_250:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 4
sethi %hi(0xc0000), %l6
sub %i1, %l6, %i1
lduw [%i1 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3130: !_BST [16] (maybe <- 0x41800024) (FP)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i2
sub %i0, %i2, %i2
! preparing store val #0, next val will be in f32
fmovs %f16, %f20
fadds %f16, %f17, %f16
! preparing store val #1, next val will be in f33
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #2, next val will be in f35
fmovd %f20, %f32
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #3, next val will be in f40
fmovd %f20, %f34
fmovs %f16, %f20
fadds %f16, %f17, %f16
fmovd %f20, %f40
membar #Sync
stda %f32, [%i2 + 0 ] %asi
membar #Sync
P3131: !_LD [29] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 4], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
sethi %hi(0xc0000), %l7
add %i1, %l7, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_4_250:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_250
nop
P3132: !_NOP (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_251:
nop
P3133: !_BLD [9] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_4_251:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_251
nop
P3134: !_DWLD [0] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_252:
ldx [%i0 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
P3135: !_LD [18] (Int) (LE)
wr %g0, 0x88, %asi
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduwa [%i3 + 12] %asi, %o1
! move %o1(lower) -> %o1(upper)
sllx %o1, 32, %o1
P3136: !_LD [21] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %o5
! move %o5(lower) -> %o1(lower)
or %o5, %o1, %o1
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_4_252:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_252
nop
P3137: !_BLD [7] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_253:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 7
sethi %hi(0xc0000), %l6
sub %i1, %l6, %i1
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P3138: !_DWLD [19] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 32], %o0
! move %o0(upper) -> %o0(upper)
P3139: !_LD [23] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 32], %l7
! move %l7(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
sethi %hi(0xc0000), %o5
add %i1, %o5, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_4_253:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_253
nop
P3140: !_BLD [8] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_254:
wr %g0, 0xf0, %asi
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_4_254:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_254
nop
P3141: !_BLD [20] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_255:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_4_255:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_255
nop
P3142: !_DWLD [13] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_256:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
P3143: !_DWLD [27] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 32], %o1
! move %o1(upper) -> %o1(upper)
P3144: !_LD [11] (Int) (Loop exit)
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 32], %l6
! move %l6(lower) -> %o1(lower)
srlx %o1, 32, %o1
sllx %o1, 32, %o1
or %l6, %o1, %o1
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_4_256:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_256
nop
P3145: !_BLD [18] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_257:
wr %g0, 0xf0, %asi
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_4_257:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_257
nop
P3146: !_BLD [31] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_258:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_4_258:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_258
nop
P3147: !_LD [10] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_259:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3148: !_LD [25] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 4], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_4_259:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_259
nop
P3149: !_DWLD [23] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_260:
sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
ldx [%i2 + 32], %o0
! move %o0(upper) -> %o0(upper)
P3150: !_LD [18] (Int) (Loop exit)
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 12], %l3
! move %l3(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_4_260:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_260
nop
P3151: !_DWLD [18] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_261:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3152: !_LD [19] (Int) (Loop exit)
lduw [%i2 + 32], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_4_261:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_261
nop
P3153: !_BLD [26] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_262:
wr %g0, 0xf0, %asi
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_4_262:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_262
nop
P3154: !_LD [18] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_263:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3155: !_LD [0] (Int) (Loop exit)
lduw [%i0 + 0], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_4_263:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_263
nop
P3156: !_BLD [21] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_264:
wr %g0, 0xf0, %asi
sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P3157: !_DWLD [7] (Int)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 7
sethi %hi(0xc0000), %l3
sub %i1, %l3, %i1
ldx [%i1 + 32], %o0
! move %o0(upper) -> %o0(upper)
P3158: !_LD [23] (Int) (Loop exit)
lduw [%i3 + 32], %l3
! move %l3(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
sethi %hi(0xc0000), %l6
add %i1, %l6, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_4_264:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_264
nop
P3159: !_MEMBAR (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_265:
membar #StoreLoad
P3160: !_LD [25] (Int)
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3161: !_LD [2] (Int) (Loop exit) (CBR)
lduw [%i0 + 12], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET3161
nop
RET3161:
! lfsr step begin
srlx %l0, 1, %l3
xnor %l3, %l0, %l3
sllx %l3, 63, %l3
or %l3, %l0, %l0
srlx %l0, 1, %l0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_4_265:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_265
nop
P3162: !_BLD [30] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_266:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_4_266:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_266
nop
P3163: !_BLD [31] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_267:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P3164: !_DWST [29] (maybe <- 0x2000017) (Int) (Loop exit) (CBR)
sllx %l4, 32, %l3
add %l4, 1, %l4
or %l3, %l4, %l3
stx %l3, [%i2 + 0]
add %l4, 1, %l4
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET3164
nop
RET3164:
! lfsr step begin
srlx %l0, 1, %o5
xnor %o5, %l0, %o5
sllx %o5, 63, %o5
or %o5, %l0, %l0
srlx %l0, 1, %l0
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_4_267:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_267
nop
P3165: !_LD [25] (Int) (Loop entry) (LE)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_268:
wr %g0, 0x88, %asi
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduwa [%i3 + 4] %asi, %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3166: !_LD [13] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_4_268:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_268
nop
P3167: !_BLD [24] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_269:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_4_269:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_269
nop
P3168: !_LD [30] (Int) (Loop entry) (CBR)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_270:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET3168
nop
RET3168:
! lfsr step begin
srlx %l0, 1, %o5
xnor %o5, %l0, %o5
sllx %o5, 63, %o5
or %o5, %l0, %l0
srlx %l0, 1, %l0
P3169: !_LD [30] (Int) (Loop exit)
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 12], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_4_270:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_270
nop
P3170: !_LD [28] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_271:
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3171: !_LD [4] (Int) (Loop exit)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 4
sethi %hi(0xc0000), %l7
sub %i1, %l7, %i1
lduw [%i1 + 0], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
sethi %hi(0xc0000), %l6
add %i1, %l6, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_4_271:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_271
nop
P3172: !_LD [17] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_272:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3173: !_LD [31] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 32], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_4_272:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_272
nop
P3174: !_MEMBAR (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_273:
membar #StoreLoad
P3175: !_BLD [12] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_4_273:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_273
nop
P3176: !_DWLD [10] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_274:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3177: !_LD [2] (Int) (Loop exit)
lduw [%i0 + 12], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_4_274:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_274
nop
P3178: !_DWLD [17] (Int) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_275:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_4_275:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_275
nop
P3179: !_DWLD [6] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_276:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 6
sethi %hi(0xc0000), %o5
sub %i1, %o5, %i1
ldx [%i1 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3180: !_LD [21] (Int) (Loop exit)
sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 4], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
sethi %hi(0xc0000), %l3
add %i1, %l3, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_4_276:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_276
nop
P3181: !_PREFETCH [18] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_277:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i3
sub %i0, %i3, %i3
prefetch [%i3 + 12], 1
P3182: !_LD [30] (FP) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
sub %i0, %i2, %i2
ld [%i2 + 12], %f0
! 1 addresses covered
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
loop_exit_4_277:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_277
nop
P3183: !_DWLD [31] (Int) (Loop entry) (CBR)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_278:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 32], %o0
! move %o0(upper) -> %o0(upper)
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET3183
nop
RET3183:
! lfsr step begin
srlx %l0, 1, %l7
xnor %l7, %l0, %l7
sllx %l7, 63, %l7
or %l7, %l0, %l0
srlx %l0, 1, %l0
P3184: !_DWLD [23] (Int) (Loop exit)
sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
ldx [%i2 + 32], %l3
! move %l3(upper) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
srlx %l3, 32, %o5
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_4_278:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_278
nop
P3185: !_LD [5] (Int) (Loop entry) (LE)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_279:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 5
sethi %hi(0xc0000), %l7
sub %i1, %l7, %i1
wr %g0, 0x88, %asi
lduwa [%i1 + 4] %asi, %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3186: !_LD [9] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 4], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
sethi %hi(0xc0000), %o5
add %i1, %o5, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_4_279:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_279
nop
P3187: !_LD [22] (Int) (Loop entry) (LE)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_280:
wr %g0, 0x88, %asi
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduwa [%i2 + 12] %asi, %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3188: !_DWLD [31] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 32], %l3
! move %l3(upper) -> %o0(lower)
srlx %l3, 32, %o5
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_4_280:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_280
nop
P3189: !_DWLD [22] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_281:
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3190: !_LD [24] (Int) (Loop exit) (CBR)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET3190
nop
RET3190:
! lfsr step begin
srlx %l0, 1, %o5
xnor %o5, %l0, %o5
sllx %o5, 63, %o5
or %o5, %l0, %l0
srlx %l0, 1, %l0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_4_281:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_281
nop
P3191: !_LD [17] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_282:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3192: !_DWLD [30] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 8], %l6
! move %l6(lower) -> %o0(lower)
srl %l6, 0, %l3
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_4_282:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_282
nop
P3193: !_DWLD [31] (Int) (Loop entry) (LE)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_283:
wr %g0, 0x88, %asi
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i2
sub %i0, %i2, %i2
ldxa [%i2 + 32] %asi, %l6
! move %l6(lower) -> %o0(upper)
sllx %l6, 32, %o0
P3194: !_LD [31] (Int) (Loop exit)
lduw [%i2 + 32], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_4_283:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_283
nop
P3195: !_DWLD [19] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_284:
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
ldx [%i3 + 32], %o0
! move %o0(upper) -> %o0(upper)
P3196: !_LD [30] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %l6
! move %l6(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_4_284:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_284
nop
P3197: !_DWLD [26] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_285:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3198: !_BLD [15] (FP)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P3199: !_LD [10] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_4_285:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_285
nop
P3200: !_ST [14] (maybe <- 0x2000019) (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_286:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i2
sub %i0, %i2, %i2
stw %l4, [%i2 + 12 ]
add %l4, 1, %l4
P3201: !_LD [28] (Int)
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3202: !_LD [6] (Int) (Loop exit)
lduw [%i1 + 12], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_4_286:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_286
nop
P3203: !_BLD [4] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_287:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 4
sethi %hi(0xc0000), %o5
sub %i1, %o5, %i1
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P3204: !_DWLD [26] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3205: !_LD [11] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
sethi %hi(0xc0000), %l6
add %i1, %l6, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_4_287:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_287
nop
P3206: !_BLD [10] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_288:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_4_288:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_288
nop
P3207: !_LD [14] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_289:
sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3208: !_LD [24] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 0], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_4_289:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_289
nop
P3209: !_LD [8] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_290:
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3210: !_LD [8] (Int) (Loop exit) (CBR)
lduw [%i3 + 0], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET3210
nop
RET3210:
! lfsr step begin
srlx %l0, 1, %l7
xnor %l7, %l0, %l7
sllx %l7, 63, %l7
or %l7, %l0, %l0
srlx %l0, 1, %l0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_4_290:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_290
nop
P3211: !_DWLD [7] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_291:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 7
sethi %hi(0xc0000), %l3
sub %i1, %l3, %i1
ldd [%i1 + 32], %f0
! 1 addresses covered
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
sethi %hi(0xc0000), %l6
add %i1, %l6, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_4_291:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_291
nop
P3212: !_DWLD [27] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_292:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i2
sub %i0, %i2, %i2
ldd [%i2 + 32], %f0
! 1 addresses covered
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
loop_exit_4_292:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_292
nop
P3213: !_BLD [21] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_293:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_4_293:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_293
nop
P3214: !_BLD [30] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_294:
wr %g0, 0xf0, %asi
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P3215: !_DWLD [7] (Int)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 7
sethi %hi(0xc0000), %l6
sub %i1, %l6, %i1
ldx [%i1 + 32], %o0
! move %o0(upper) -> %o0(upper)
P3216: !_LD [1] (Int) (Loop exit)
lduw [%i0 + 4], %l6
! move %l6(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
sethi %hi(0xc0000), %l7
add %i1, %l7, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_4_294:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_294
nop
P3217: !_BLD [23] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_295:
wr %g0, 0xf0, %asi
sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P3218: !_DWLD [10] (Int)
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
ldx [%i2 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3219: !_LD [30] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_4_295:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_295
nop
P3220: !_NOP (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_296:
nop
P3221: !_MEMBAR (Int) (Loop exit)
membar #StoreLoad
loop_exit_4_296:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_296
nop
P3222: !_DWLD [30] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_297:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
sub %i0, %i2, %i2
ldd [%i2 + 8], %f0
! 1 addresses covered
fmovs %f1, %f0
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
loop_exit_4_297:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_297
nop
P3223: !_NOP (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_298:
nop
P3224: !_LD [3] (Int)
lduw [%i0 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3225: !_LD [23] (Int) (Loop exit) (LE)
wr %g0, 0x88, %asi
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduwa [%i3 + 32] %asi, %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_4_298:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_298
nop
P3226: !_LD [30] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_299:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
sub %i0, %i2, %i2
ld [%i2 + 12], %f0
! 1 addresses covered
P3227: !_ST [22] (maybe <- 0x200001a) (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
sub %i0, %i3, %i3
stw %l4, [%i3 + 12 ]
add %l4, 1, %l4
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
loop_exit_4_299:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_299
nop
P3228: !_DWLD [26] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_300:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i2
sub %i0, %i2, %i2
ldd [%i2 + 8], %f0
! 1 addresses covered
fmovs %f1, %f0
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
loop_exit_4_300:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_300
nop
P3229: !_BLD [7] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_301:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 7
sethi %hi(0xc0000), %l7
sub %i1, %l7, %i1
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
sethi %hi(0xc0000), %o5
add %i1, %o5, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_4_301:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_301
nop
P3230: !_BLD [15] (FP) (Loop entry) (Loop exit) (CBR)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_302:
wr %g0, 0xf0, %asi
sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET3230
nop
RET3230:
! lfsr step begin
srlx %l0, 1, %l3
xnor %l3, %l0, %l3
sllx %l3, 63, %l3
or %l3, %l0, %l0
srlx %l0, 1, %l0
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_4_302:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_302
nop
P3231: !_BLD [19] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_303:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P3232: !_DWLD [28] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_4_303:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_303
nop
P3233: !_DWLD [22] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_304:
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3234: !_DWLD [26] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 8], %l7
! move %l7(lower) -> %o0(lower)
srl %l7, 0, %l6
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_4_304:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_304
nop
P3235: !_LD [22] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_305:
sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3236: !_BLD [29] (FP)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P3237: !_LD [11] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 32], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_4_305:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_305
nop
P3238: !_SWAP [4] (maybe <- 0x200001b) (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_306:
mov %l4, %o0
swap [%i1 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
add %l4, 1, %l4
P3239: !_LD [5] (Int) (Loop exit)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 5
sethi %hi(0xc0000), %l7
sub %i1, %l7, %i1
lduw [%i1 + 4], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
sethi %hi(0xc0000), %l6
add %i1, %l6, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_4_306:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_306
nop
P3240: !_DWLD [18] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_307:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3241: !_LD [0] (Int) (Loop exit) (LE)
wr %g0, 0x88, %asi
lduwa [%i0 + 0] %asi, %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_4_307:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_307
nop
P3242: !_DWLD [20] (Int) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_308:
sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
ldx [%i2 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_4_308:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_308
nop
P3243: !_REPLACEMENT [5] (Int) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_309:
sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS3_O), %i3
sub %i0, %i3, %i3
sethi %hi(0x10000), %l3
ld [%i3+4], %l7
st %l7, [%i3+4]
add %i3, %l3, %l6
ld [%l6+4], %l7
st %l7, [%l6+4]
add %l6, %l3, %l6
ld [%l6+4], %l7
st %l7, [%l6+4]
add %l6, %l3, %l6
ld [%l6+4], %l7
st %l7, [%l6+4]
loop_exit_4_309:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_309
nop
P3244: !_LD [24] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_310:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i2
sub %i0, %i2, %i2
ld [%i2 + 0], %f0
! 1 addresses covered
P3245: !_BLD [23] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f32
membar #Sync
! 4 addresses covered
fmovd %f32, %f18
fmovs %f18, %f1
fmovs %f19, %f2
fmovd %f34, %f18
fmovs %f19, %f3
fmovd %f40, %f4
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovs %f4, %f30
!--
loop_exit_4_310:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_310
nop
P3246: !_BLD [28] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_311:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P3247: !_LD [30] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3248: !_LD [0] (Int) (Loop exit)
lduw [%i0 + 0], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_4_311:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_311
nop
P3249: !_LD [15] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_312:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i2
sub %i0, %i2, %i2
ld [%i2 + 32], %f0
! 1 addresses covered
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
loop_exit_4_312:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_312
nop
P3250: !_BST [25] (maybe <- 0x41800028) (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_313:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i3
sub %i0, %i3, %i3
! preparing store val #0, next val will be in f32
fmovs %f16, %f20
fadds %f16, %f17, %f16
! preparing store val #1, next val will be in f33
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #2, next val will be in f35
fmovd %f20, %f32
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #3, next val will be in f40
fmovd %f20, %f34
fmovs %f16, %f20
fadds %f16, %f17, %f16
fmovd %f20, %f40
membar #Sync
stda %f32, [%i3 + 0 ] %asi
membar #Sync
P3251: !_DWLD [12] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_4_313:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_313
nop
P3252: !_LD [21] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_314:
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3253: !_BLD [12] (FP) (Branch target of P3006)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
ba P3254
nop
TARGET3006:
ba RET3006
nop
P3254: !_LD [3] (Int) (Loop exit)
lduw [%i0 + 32], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_4_314:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_314
nop
P3255: !_DWLD [15] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_315:
sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
ldx [%i3 + 32], %o0
! move %o0(upper) -> %o0(upper)
P3256: !_LD [10] (FP)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i2
sub %i0, %i2, %i2
ld [%i2 + 12], %f0
! 1 addresses covered
P3257: !_LD [7] (Int) (Loop exit)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 7
sethi %hi(0xc0000), %l7
sub %i1, %l7, %i1
lduw [%i1 + 32], %l3
! move %l3(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
sethi %hi(0xc0000), %l6
add %i1, %l6, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_4_315:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_315
nop
P3258: !_BLD [12] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_316:
wr %g0, 0xf0, %asi
sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P3259: !_BLD [16] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f32
membar #Sync
! 4 addresses covered
fmovd %f32, %f4
fmovd %f34, %f18
fmovs %f19, %f6
fmovd %f40, %f18
fmovs %f18, %f7
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovd %f4, %f30
fmovd %f6, %f30
!--
loop_exit_4_316:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_316
nop
P3260: !_DWLD [12] (Int) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_317:
sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
ldx [%i3 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_4_317:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_317
nop
P3261: !_BLD [30] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_318:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P3262: !_NOP (Int) (Loop exit)
nop
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_4_318:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_318
nop
P3263: !_DWLD [18] (Int) (Loop entry) (LE)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_319:
wr %g0, 0x88, %asi
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
sub %i0, %i3, %i3
ldxa [%i3 + 8] %asi, %o5
! move %o5(upper) -> %o0(upper)
or %o5, %g0, %o0
P3264: !_BLD [0] (FP)
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i0 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P3265: !_LD [6] (Int) (Loop exit)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 6
sethi %hi(0xc0000), %l3
sub %i1, %l3, %i1
lduw [%i1 + 12], %l7
! move %l7(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
sethi %hi(0xc0000), %o5
add %i1, %o5, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_4_319:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_319
nop
P3266: !_BLD [10] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_320:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_4_320:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_320
nop
P3267: !_LD [14] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_321:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i3
sub %i0, %i3, %i3
ld [%i3 + 12], %f0
! 1 addresses covered
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
loop_exit_4_321:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_321
nop
P3268: !_LD [17] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_322:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3269: !_DWLD [20] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 0], %o5
! move %o5(upper) -> %o0(lower)
srlx %o5, 32, %l7
or %l7, %o0, %o0
! move %o5(lower) -> %o1(upper)
sllx %o5, 32, %o1
P3270: !_LD [19] (Int) (Loop exit)
lduw [%i2 + 32], %l6
! move %l6(lower) -> %o1(lower)
or %l6, %o1, %o1
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_4_322:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_322
nop
P3271: !_LD [31] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_323:
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3272: !_BLD [24] (FP)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P3273: !_LD [4] (Int) (Loop exit)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 4
sethi %hi(0xc0000), %l7
sub %i1, %l7, %i1
lduw [%i1 + 0], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
sethi %hi(0xc0000), %l6
add %i1, %l6, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_4_323:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_323
nop
P3274: !_BLD [10] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_324:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P3275: !_BLD [17] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f32
membar #Sync
! 4 addresses covered
fmovd %f32, %f4
fmovd %f34, %f18
fmovs %f19, %f6
fmovd %f40, %f18
fmovs %f18, %f7
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovd %f4, %f30
fmovd %f6, %f30
!--
loop_exit_4_324:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_324
nop
P3276: !_BLD [28] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_325:
wr %g0, 0xf0, %asi
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P3277: !_BLD [17] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f32
membar #Sync
! 4 addresses covered
fmovd %f32, %f4
fmovd %f34, %f18
fmovs %f19, %f6
fmovd %f40, %f18
fmovs %f18, %f7
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovd %f4, %f30
fmovd %f6, %f30
!--
loop_exit_4_325:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_325
nop
P3278: !_BLD [15] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_326:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_4_326:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_326
nop
P3279: !_DWLD [31] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_327:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 32], %o0
! move %o0(upper) -> %o0(upper)
P3280: !_LD [12] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 0], %o5
! move %o5(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_4_327:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_327
nop
P3281: !_LD [1] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_328:
lduw [%i0 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3282: !_LD [6] (Int) (Loop exit)
lduw [%i1 + 12], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_4_328:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_328
nop
P3283: !_LD [17] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_329:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3284: !_LD [4] (Int) (Loop exit)
lduw [%i1 + 0], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_4_329:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_329
nop
P3285: !_BLD [29] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_330:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P3286: !_BLD [21] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f32
membar #Sync
! 4 addresses covered
fmovd %f32, %f4
fmovd %f34, %f18
fmovs %f19, %f6
fmovd %f40, %f18
fmovs %f18, %f7
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovd %f4, %f30
fmovd %f6, %f30
!--
loop_exit_4_330:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_330
nop
P3287: !_BLD [28] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_331:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P3288: !_LD [9] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3289: !_LD [25] (Int) (Loop exit)
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 4], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_4_331:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_331
nop
P3290: !_BLD [0] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_332:
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i0 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_4_332:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_332
nop
P3291: !_LD [31] (Int) (Loop entry) (CBR)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_333:
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET3291
nop
RET3291:
! lfsr step begin
srlx %l0, 1, %l7
xnor %l7, %l0, %l7
sllx %l7, 63, %l7
or %l7, %l0, %l0
srlx %l0, 1, %l0
P3292: !_LD [4] (Int) (Loop exit)
lduw [%i1 + 0], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_4_333:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_333
nop
P3293: !_CAS [10] (maybe <- 0x200001c) (Int) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_4_334:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
sub %i0, %i2, %i2
add %i2, 12, %l3
lduw [%l3], %o0
mov %o0, %o5
! move %o5(lower) -> %o0(upper)
sllx %o5, 32, %o0
mov %l4, %l7
cas [%l3], %o5, %l7
! move %l7(lower) -> %o0(lower)
srl %l7, 0, %o5
or %o5, %o0, %o0
add %l4, 1, %l4
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_4_334:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_334
nop
P3294: !_BLD [17] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_335:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_4_335:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_335
nop
P3295: !_DWLD [17] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_336:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
P3296: !_BLD [7] (FP) (Loop exit)
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_4_336:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_336
nop
P3297: !_DWLD [2] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_337:
ldx [%i0 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3298: !_DWLD [0] (Int)
ldx [%i0 + 0], %l6
! move %l6(upper) -> %o0(lower)
srlx %l6, 32, %l3
or %l3, %o0, %o0
! move %l6(lower) -> %o1(upper)
sllx %l6, 32, %o1
P3299: !_LD [27] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %l3
! move %l3(lower) -> %o1(lower)
or %l3, %o1, %o1
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_4_337:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_337
nop
P3300: !_DWLD [2] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_4_338:
ldd [%i0 + 8], %f0
! 1 addresses covered
fmovs %f1, %f0
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
loop_exit_4_338:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_4_338
nop
P3301: !_MEMBAR (Int)
membar #StoreLoad
END_NODES4: ! Test instruction sequence for CPU 4 ends
sethi %hi(0xdead0e0f), %l3
or %l3, %lo(0xdead0e0f), %l3
! move %l3(lower) -> %o0(upper)
sllx %l3, 32, %o0
stw %l3, [%i5]
ld [%i5], %f0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
restore
retl
nop
!-----------------
! register usage:
! %i0 %i1 : base registers for first 2 regions
! %i2 %i3 : cache registers for 8 regions
! %i4 fixed pointer to per-cpu results area
! %l1 moving pointer to per-cpu FP results area
! %o7 moving pointer to per-cpu integer results area
! %i5 pointer to per-cpu private area
! %l0 holds lfsr, used as source of random bits
! %l2 loop count register
! %f16 running counter for unique fp store values
! %f17 holds increment value for fp counter
! %l4 running counter for unique integer store values (increment value is always 1)
! %l5 move-to register for load values (simulation only)
! %f30 move-to register for FP values (simulation only)
! %l3 %l6 %l7 %o5 : 4 temporary registers
! %o0 %o1 %o2 %o3 %o4 : 5 integer results buffer registers
! %f0-f15 FP results buffer registers
! %f32-f47 FP block load/store registers
func5:
! 1000 (dynamic) instruction sequence begins
save %sp, -192, %sp
! Force %i0-%i3 to be 64-byte aligned
add %i0, 63, %i0
andn %i0, 63, %i0
add %i1, 63, %i1
andn %i1, 63, %i1
add %i2, 63, %i2
andn %i2, 63, %i2
add %i3, 63, %i3
andn %i3, 63, %i3
add %i4, 63, %i4
andn %i4, 63, %i4
add %i5, 63, %i5
andn %i5, 63, %i5
! Initialize pointer to FP load results area
mov %i4, %l1
! Initialize pointer to integer load results area
sethi %hi(0x80000), %o7
or %o7, %lo(0x80000), %o7
add %o7, %l1, %o7
! Initialize %f0-%f62 to 0xdeadbee0deadbee1
sethi %hi(0xdeadbee0), %o5
or %o5, %lo(0xdeadbee0), %o5
stw %o5, [%i5]
sethi %hi(0xdeadbee1), %o5
or %o5, %lo(0xdeadbee1), %o5
stw %o5, [%i5+4]
ldd [%i5], %f0
fmovd %f0, %f2
fmovd %f0, %f4
fmovd %f0, %f6
fmovd %f0, %f8
fmovd %f0, %f10
fmovd %f0, %f12
fmovd %f0, %f14
fmovd %f0, %f16
fmovd %f0, %f18
fmovd %f0, %f20
fmovd %f0, %f22
fmovd %f0, %f24
fmovd %f0, %f26
fmovd %f0, %f28
fmovd %f0, %f30
fmovd %f0, %f32
fmovd %f0, %f34
fmovd %f0, %f36
fmovd %f0, %f38
fmovd %f0, %f40
fmovd %f0, %f42
fmovd %f0, %f44
fmovd %f0, %f46
fmovd %f0, %f48
fmovd %f0, %f50
fmovd %f0, %f52
fmovd %f0, %f54
fmovd %f0, %f56
fmovd %f0, %f58
fmovd %f0, %f60
fmovd %f0, %f62
! Signature for extract_loads script to start extracting load values for this stream
sethi %hi(0x05deade1), %o5
or %o5, %lo(0x05deade1), %o5
stw %o5, [%i5]
ld [%i5], %f16
! Initialize running integer counter in register %l4
sethi %hi(0x2800001), %l4
or %l4, %lo(0x2800001), %l4
! Initialize running FP counter in register %f16
sethi %hi(0x42000001), %o5
or %o5, %lo(0x42000001), %o5
stw %o5, [%i5]
ld [%i5], %f16
! Initialize FP counter increment value in register %f17 (constant)
sethi %hi(0x36800000), %o5
or %o5, %lo(0x36800000), %o5
stw %o5, [%i5]
ld [%i5], %f17
! Initialize LFSR to 0x2690^4
sethi %hi(0x2690), %l0
or %l0, %lo(0x2690), %l0
mulx %l0, %l0, %l0
mulx %l0, %l0, %l0
BEGIN_NODES5: ! Test instruction sequence for CPU 5 begins
P3302: !_LD [15] (Int) (Loop entry) (LE)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_0:
wr %g0, 0x88, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduwa [%i2 + 32] %asi, %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3303: !_MEMBAR (Int)
membar #StoreLoad
P3304: !_LD [24] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_5_0:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_0
nop
P3305: !_ST [1] (maybe <- 0x2800001) (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_1:
stw %l4, [%i0 + 4 ]
add %l4, 1, %l4
P3306: !_BSTC [13] (maybe <- 0x42000001) (FP) (Loop exit)
wr %g0, 0xe0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i2
sub %i0, %i2, %i2
! preparing store val #0, next val will be in f32
fmovs %f16, %f20
fadds %f16, %f17, %f16
! preparing store val #1, next val will be in f33
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #2, next val will be in f35
fmovd %f20, %f32
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #3, next val will be in f40
fmovd %f20, %f34
fmovs %f16, %f20
fadds %f16, %f17, %f16
fmovd %f20, %f40
membar #Sync
stda %f32, [%i2 + 0 ] %asi
membar #Sync
loop_exit_5_1:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_1
nop
P3307: !_BLD [6] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_2:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 6
sethi %hi(0xc0000), %o5
sub %i1, %o5, %i1
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P3308: !_DWLD [8] (FP) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
sub %i0, %i3, %i3
ldd [%i3 + 0], %f4
! 2 addresses covered
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovd %f4, %f30
!--
sethi %hi(0xc0000), %l3
add %i1, %l3, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_5_2:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_2
nop
P3309: !_LD [19] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_3:
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3310: !_CAS [17] (maybe <- 0x2800002) (Int) (LE)
! Change single-word-level endianess (big endian <-> little endian)
sethi %hi(0xff00ff00), %l6
or %l6, %lo(0xff00ff00), %l6
and %l4, %l6, %l3
srl %l3, 8, %l3
sll %l4, 8, %l7
and %l7, %l6, %l7
or %l7, %l3, %l7
srl %l7, 16, %l3
sll %l7, 16, %l7
srl %l7, 0, %l7
or %l7, %l3, %l7
wr %g0, 0x88, %asi
add %i2, 4, %l6
lduwa [%l6] %asi, %o5
mov %o5, %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
mov %l7, %o1
casa [%l6] %asi, %l3, %o1
! move %o1(lower) -> %o1(upper)
sllx %o1, 32, %o1
add %l4, 1, %l4
P3311: !_LD [30] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %l7
! move %l7(lower) -> %o1(lower)
or %l7, %o1, %o1
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_5_3:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_3
nop
P3312: !_DWLD [5] (Int) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_4:
ldx [%i1 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_5_4:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_4
nop
P3313: !_REPLACEMENT [27] (Int) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_5:
sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS1_O), %i2
sub %i0, %i2, %i2
sethi %hi(0x10000), %l3
ld [%i2+32], %l7
st %l7, [%i2+32]
add %i2, %l3, %l6
ld [%l6+32], %l7
st %l7, [%l6+32]
add %l6, %l3, %l6
ld [%l6+32], %l7
st %l7, [%l6+32]
add %l6, %l3, %l6
ld [%l6+32], %l7
st %l7, [%l6+32]
loop_exit_5_5:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_5
nop
P3314: !_FLUSHI [26] (Int) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_6:
flush %g0
loop_exit_5_6:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_6
nop
P3315: !_DWLD [15] (Int) (Loop entry) (Branch target of P3912)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_7:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 32], %o0
! move %o0(upper) -> %o0(upper)
ba P3316
nop
TARGET3912:
ba RET3912
nop
P3316: !_BLD [31] (FP)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P3317: !_LD [30] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %l7
! move %l7(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_5_7:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_7
nop
P3318: !_LD [15] (Int) (Loop entry) (Branch target of P3733)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_8:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
ba P3319
nop
TARGET3733:
ba RET3733
nop
P3319: !_LD [13] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 4], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_5_8:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_8
nop
P3320: !_BLD [8] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_9:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P3321: !_LD [28] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3322: !_LD [12] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 0], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_5_9:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_9
nop
P3323: !_DWLD [18] (Int) (Loop entry) (LE)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_10:
wr %g0, 0x88, %asi
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
sub %i0, %i3, %i3
ldxa [%i3 + 8] %asi, %l7
! move %l7(upper) -> %o0(upper)
or %l7, %g0, %o0
P3324: !_LD [29] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %l3
! move %l3(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_5_10:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_10
nop
P3325: !_LD [25] (Int) (Loop entry) (CBR)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_11:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET3325
nop
RET3325:
! lfsr step begin
srlx %l0, 1, %l6
xnor %l6, %l0, %l6
sllx %l6, 63, %l6
or %l6, %l0, %l0
srlx %l0, 1, %l0
P3326: !_DWLD [30] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 8], %o5
! move %o5(lower) -> %o0(lower)
srl %o5, 0, %l7
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_5_11:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_11
nop
P3327: !_LD [20] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_12:
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3328: !_LD [5] (Int) (Loop exit) (Branch target of P3916)
lduw [%i1 + 4], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_5_12:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_12
nop
ba P3329
nop
TARGET3916:
ba RET3916
nop
P3329: !_BLD [3] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_13:
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i0 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P3330: !_DWLD [28] (Int) (Loop exit) (CBR)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET3330
nop
RET3330:
! lfsr step begin
srlx %l0, 1, %l7
xnor %l7, %l0, %l7
sllx %l7, 63, %l7
or %l7, %l0, %l0
srlx %l0, 1, %l0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_5_13:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_13
nop
P3331: !_DWLD [18] (FP) (Loop entry) (Loop exit) (CBR)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_14:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i3
sub %i0, %i3, %i3
ldd [%i3 + 8], %f0
! 1 addresses covered
fmovs %f1, %f0
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET3331
nop
RET3331:
! lfsr step begin
srlx %l0, 1, %l6
xnor %l6, %l0, %l6
sllx %l6, 63, %l6
or %l6, %l0, %l0
srlx %l0, 1, %l0
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
loop_exit_5_14:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_14
nop
P3332: !_BLD [26] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_15:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P3333: !_BLD [10] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f32
membar #Sync
! 4 addresses covered
fmovd %f32, %f4
fmovd %f34, %f18
fmovs %f19, %f6
fmovd %f40, %f18
fmovs %f18, %f7
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovd %f4, %f30
fmovd %f6, %f30
!--
loop_exit_5_15:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_15
nop
P3334: !_DWLD [30] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_16:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3335: !_LD [28] (Int) (Loop exit)
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 0], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_5_16:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_16
nop
P3336: !_BST [25] (maybe <- 0x42000005) (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_17:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i2
sub %i0, %i2, %i2
! preparing store val #0, next val will be in f32
fmovs %f16, %f20
fadds %f16, %f17, %f16
! preparing store val #1, next val will be in f33
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #2, next val will be in f35
fmovd %f20, %f32
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #3, next val will be in f40
fmovd %f20, %f34
fmovs %f16, %f20
fadds %f16, %f17, %f16
fmovd %f20, %f40
membar #Sync
stda %f32, [%i2 + 0 ] %asi
membar #Sync
P3337: !_DWLD [10] (Int) (LE)
wr %g0, 0x88, %asi
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
ldxa [%i3 + 8] %asi, %l3
! move %l3(upper) -> %o0(upper)
or %l3, %g0, %o0
P3338: !_LD [25] (Int) (Loop exit)
lduw [%i2 + 4], %l7
! move %l7(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_5_17:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_17
nop
P3339: !_DWLD [21] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_18:
sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
ldx [%i2 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
P3340: !_LD [28] (Int)
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 0], %o1
! move %o1(lower) -> %o1(upper)
sllx %o1, 32, %o1
P3341: !_LD [20] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 0], %o5
! move %o5(lower) -> %o1(lower)
or %o5, %o1, %o1
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_5_18:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_18
nop
P3342: !_BLD [1] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_19:
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i0 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_5_19:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_19
nop
P3343: !_LD [6] (Int) (Loop entry) (Branch target of P3483)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_20:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 6
sethi %hi(0xc0000), %l7
sub %i1, %l7, %i1
lduw [%i1 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
ba P3344
nop
TARGET3483:
ba RET3483
nop
P3344: !_BLD [11] (FP)
wr %g0, 0xf0, %asi
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P3345: !_LD [17] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
sethi %hi(0xc0000), %l3
add %i1, %l3, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_5_20:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_20
nop
P3346: !_LD [20] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_21:
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3347: !_BLD [5] (FP)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 5
sethi %hi(0xc0000), %o5
sub %i1, %o5, %i1
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P3348: !_LD [0] (Int) (Loop exit)
lduw [%i0 + 0], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
sethi %hi(0xc0000), %l7
add %i1, %l7, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_5_21:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_21
nop
P3349: !_BLD [18] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_22:
wr %g0, 0xf0, %asi
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_5_22:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_22
nop
P3350: !_LD [26] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_23:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3351: !_LD [11] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 32], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_5_23:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_23
nop
P3352: !_DWLD [31] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_24:
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
ldx [%i3 + 32], %o0
! move %o0(upper) -> %o0(upper)
P3353: !_LD [19] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 32], %o5
! move %o5(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_5_24:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_24
nop
P3354: !_DWST [11] (maybe <- 0x2800003) (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_25:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i3
sub %i0, %i3, %i3
mov %l4, %l6
sllx %l6, 32, %l6
stx %l6, [%i3 + 32 ]
add %l4, 1, %l4
P3355: !_LD [9] (Int) (Branch target of P3431)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
ba P3356
nop
TARGET3431:
ba RET3431
nop
P3356: !_LD [10] (Int) (Loop exit)
lduw [%i2 + 12], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_5_25:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_25
nop
P3357: !_LD [20] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_26:
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3358: !_LD [29] (Int) (Loop exit)
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 4], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_5_26:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_26
nop
P3359: !_BLD [5] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_27:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 5
sethi %hi(0xc0000), %l3
sub %i1, %l3, %i1
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P3360: !_LD [28] (Int)
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3361: !_LD [16] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 0], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
sethi %hi(0xc0000), %l7
add %i1, %l7, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_5_27:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_27
nop
P3362: !_DWLD [8] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_28:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
P3363: !_ST [14] (maybe <- 0x2800004) (Int) (Loop exit)
sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
stw %l4, [%i2 + 12 ]
add %l4, 1, %l4
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_5_28:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_28
nop
P3364: !_LD [4] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_29:
lduw [%i1 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3365: !_LD [17] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 4], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_5_29:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_29
nop
P3366: !_DWLD [12] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_30:
sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
ldx [%i2 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
P3367: !_BLD [7] (FP) (Loop exit)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 7
sethi %hi(0xc0000), %l7
sub %i1, %l7, %i1
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
sethi %hi(0xc0000), %o5
add %i1, %o5, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_5_30:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_30
nop
P3368: !_BLD [5] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_31:
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_5_31:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_31
nop
P3369: !_BLD [27] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_32:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_5_32:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_32
nop
P3370: !_LD [26] (Int) (Loop entry) (Branch target of P3801)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_33:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
ba P3371
nop
TARGET3801:
ba RET3801
nop
P3371: !_SWAP [31] (maybe <- 0x2800005) (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
sub %i0, %i3, %i3
mov %l4, %l3
swap [%i3 + 32], %l3
! move %l3(lower) -> %o0(lower)
srl %l3, 0, %l7
or %l7, %o0, %o0
add %l4, 1, %l4
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_5_33:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_33
nop
P3372: !_DWST [1] (maybe <- 0x2800006) (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_34:
sllx %l4, 32, %l7
add %l4, 1, %l4
or %l7, %l4, %l7
stx %l7, [%i0 + 0]
add %l4, 1, %l4
P3373: !_SWAP [3] (maybe <- 0x2800008) (Int)
mov %l4, %o0
swap [%i0 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
add %l4, 1, %l4
P3374: !_LD [1] (Int) (Loop exit)
lduw [%i0 + 4], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_5_34:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_34
nop
P3375: !_DWLD [15] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_35:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 32], %o0
! move %o0(upper) -> %o0(upper)
P3376: !_DWLD [22] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 8], %l3
! move %l3(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
srl %l3, 0, %o5
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_5_35:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_35
nop
P3377: !_LD [12] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_36:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3378: !_LD [18] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_5_36:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_36
nop
P3379: !_BLD [24] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_37:
wr %g0, 0xf0, %asi
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P3380: !_SWAP [13] (maybe <- 0x2800009) (Int)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i3
sub %i0, %i3, %i3
mov %l4, %o0
swap [%i3 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
add %l4, 1, %l4
P3381: !_LD [11] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 32], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_5_37:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_37
nop
P3382: !_LD [16] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_38:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3383: !_LD [9] (Int) (Loop exit)
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 4], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_5_38:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_38
nop
P3384: !_BLD [3] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_39:
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i0 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P3385: !_BLD [31] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f32
membar #Sync
! 4 addresses covered
fmovd %f32, %f4
fmovd %f34, %f18
fmovs %f19, %f6
fmovd %f40, %f18
fmovs %f18, %f7
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovd %f4, %f30
fmovd %f6, %f30
!--
loop_exit_5_39:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_39
nop
P3386: !_DWLD [1] (Int) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_40:
ldx [%i0 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_5_40:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_40
nop
P3387: !_DWLD [16] (Int) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_41:
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
ldx [%i2 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_5_41:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_41
nop
P3388: !_BLD [10] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_42:
wr %g0, 0xf0, %asi
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_5_42:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_42
nop
P3389: !_BLD [5] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_43:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 5
sethi %hi(0xc0000), %l3
sub %i1, %l3, %i1
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
sethi %hi(0xc0000), %l6
add %i1, %l6, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_5_43:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_43
nop
P3390: !_DWLD [25] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_44:
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
ldx [%i2 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
P3391: !_CASX [24] (maybe <- 0x280000a) (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
sub %i0, %i3, %i3
ldx [%i3], %o1
! move %o1(upper) -> %o1(upper)
! move %o1(lower) -> %o1(lower)
mov %o1, %l6
sllx %l4, 32, %o2
add %l4, 1, %l4
or %l4, %o2, %o2
casx [%i3], %l6, %o2
! move %o2(upper) -> %o2(upper)
! move %o2(lower) -> %o2(lower)
add %l4, 1, %l4
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
mov %o2, %l5
loop_exit_5_44:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_44
nop
P3392: !_BLD [21] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_45:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_5_45:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_45
nop
P3393: !_DWLD [20] (Int) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_46:
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_5_46:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_46
nop
P3394: !_DWLD [29] (Int) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_47:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_5_47:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_47
nop
P3395: !_BLD [26] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_48:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P3396: !_BLD [29] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f32
membar #Sync
! 4 addresses covered
fmovd %f32, %f4
fmovd %f34, %f18
fmovs %f19, %f6
fmovd %f40, %f18
fmovs %f18, %f7
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovd %f4, %f30
fmovd %f6, %f30
!--
loop_exit_5_48:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_48
nop
P3397: !_LD [29] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_49:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3398: !_LD [10] (Int) (Loop exit)
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 12], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_5_49:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_49
nop
P3399: !_BLD [9] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_50:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P3400: !_LD [22] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3401: !_LD [14] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_5_50:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_50
nop
P3402: !_BLD [2] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_51:
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i0 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P3403: !_LD [23] (Int)
sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3404: !_LD [20] (Int) (Loop exit)
lduw [%i2 + 0], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_5_51:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_51
nop
P3405: !_BLD [19] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_52:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P3406: !_LD [12] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3407: !_LD [4] (Int) (Loop exit)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 4
sethi %hi(0xc0000), %l7
sub %i1, %l7, %i1
lduw [%i1 + 0], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
sethi %hi(0xc0000), %l6
add %i1, %l6, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_5_52:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_52
nop
P3408: !_FLUSHI [17] (Int) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_53:
flush %g0
loop_exit_5_53:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_53
nop
P3409: !_DWLD [20] (Int) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_54:
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_5_54:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_54
nop
P3410: !_ST [1] (maybe <- 0x280000c) (Int) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_55:
stw %l4, [%i0 + 4 ]
add %l4, 1, %l4
loop_exit_5_55:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_55
nop
P3411: !_LD [30] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_56:
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3412: !_LD [9] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 4], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_5_56:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_56
nop
P3413: !_LD [15] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_57:
sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3414: !_FLUSHI [9] (Int)
flush %g0
P3415: !_LD [25] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 4], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_5_57:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_57
nop
P3416: !_BLD [5] (FP) (Loop entry) (CBR)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_58:
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET3416
nop
RET3416:
! lfsr step begin
srlx %l0, 1, %l3
xnor %l3, %l0, %l3
sllx %l3, 63, %l3
or %l3, %l0, %l0
srlx %l0, 1, %l0
P3417: !_BLD [13] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f32
membar #Sync
! 4 addresses covered
fmovd %f32, %f4
fmovd %f34, %f18
fmovs %f19, %f6
fmovd %f40, %f18
fmovs %f18, %f7
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovd %f4, %f30
fmovd %f6, %f30
!--
loop_exit_5_58:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_58
nop
P3418: !_DWLD [29] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_59:
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
ldx [%i3 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
P3419: !_BSTC [14] (maybe <- 0x42000009) (FP) (Loop exit)
wr %g0, 0xe0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i2
sub %i0, %i2, %i2
! preparing store val #0, next val will be in f32
fmovs %f16, %f20
fadds %f16, %f17, %f16
! preparing store val #1, next val will be in f33
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #2, next val will be in f35
fmovd %f20, %f32
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #3, next val will be in f40
fmovd %f20, %f34
fmovs %f16, %f20
fadds %f16, %f17, %f16
fmovd %f20, %f40
membar #Sync
stda %f32, [%i2 + 0 ] %asi
membar #Sync
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_5_59:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_59
nop
P3420: !_LD [31] (Int) (Loop entry) (LE)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_60:
wr %g0, 0x88, %asi
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduwa [%i3 + 32] %asi, %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3421: !_LD [21] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_5_60:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_60
nop
P3422: !_DWLD [21] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_61:
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
sub %i0, %i3, %i3
ldd [%i3 + 0], %f0
! 2 addresses covered
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
!--
loop_exit_5_61:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_61
nop
P3423: !_DWLD [12] (Int) (Loop entry) (Loop exit) (CBR)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_62:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET3423
nop
RET3423:
! lfsr step begin
srlx %l0, 1, %l3
xnor %l3, %l0, %l3
sllx %l3, 63, %l3
or %l3, %l0, %l0
srlx %l0, 1, %l0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_5_62:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_62
nop
P3424: !_DWLD [16] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_63:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
sub %i0, %i3, %i3
ldd [%i3 + 0], %f0
! 2 addresses covered
P3425: !_BLD [17] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f32
membar #Sync
! 4 addresses covered
fmovd %f32, %f2
fmovd %f34, %f18
fmovs %f19, %f4
fmovd %f40, %f18
fmovs %f18, %f5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovd %f4, %f30
!--
loop_exit_5_63:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_63
nop
P3426: !_DWLD [21] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_64:
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
P3427: !_DWLD [12] (Int) (Loop exit)
sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
ldx [%i2 + 0], %o1
! move %o1(upper) -> %o1(upper)
! move %o1(lower) -> %o1(lower)
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_5_64:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_64
nop
P3428: !_BLD [26] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_65:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_5_65:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_65
nop
P3429: !_LD [26] (Int) (Loop entry) (LE)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_66:
wr %g0, 0x88, %asi
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduwa [%i2 + 12] %asi, %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3430: !_LD [22] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_5_66:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_66
nop
P3431: !_BLD [24] (FP) (Loop entry) (CBR)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_67:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET3431
nop
RET3431:
! lfsr step begin
srlx %l0, 1, %l7
xnor %l7, %l0, %l7
sllx %l7, 63, %l7
or %l7, %l0, %l0
srlx %l0, 1, %l0
P3432: !_BLD [14] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f32
membar #Sync
! 4 addresses covered
fmovd %f32, %f4
fmovd %f34, %f18
fmovs %f19, %f6
fmovd %f40, %f18
fmovs %f18, %f7
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovd %f4, %f30
fmovd %f6, %f30
!--
loop_exit_5_67:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_67
nop
P3433: !_DWLD [5] (Int) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_68:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 5
sethi %hi(0xc0000), %l3
sub %i1, %l3, %i1
ldx [%i1 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
sethi %hi(0xc0000), %o5
add %i1, %o5, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_5_68:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_68
nop
P3434: !_DWLD [22] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_69:
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3435: !_BLD [16] (FP)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P3436: !_LD [4] (Int) (Loop exit)
lduw [%i1 + 0], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_5_69:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_69
nop
P3437: !_BLD [0] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_70:
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i0 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_5_70:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_70
nop
P3438: !_BLD [18] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_71:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P3439: !_DWLD [15] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 32], %o0
! move %o0(upper) -> %o0(upper)
P3440: !_LD [28] (Int) (Loop exit)
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 0], %l3
! move %l3(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_5_71:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_71
nop
P3441: !_CAS [22] (maybe <- 0x280000d) (Int) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_72:
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i3
sub %i0, %i3, %i3
add %i3, 12, %l3
lduw [%l3], %o0
mov %o0, %o5
! move %o5(lower) -> %o0(upper)
sllx %o5, 32, %o0
mov %l4, %l7
cas [%l3], %o5, %l7
! move %l7(lower) -> %o0(lower)
srl %l7, 0, %o5
or %o5, %o0, %o0
add %l4, 1, %l4
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_5_72:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_72
nop
P3442: !_BLD [10] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_73:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P3443: !_LD [8] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3444: !_LD [11] (Int) (Loop exit)
lduw [%i3 + 32], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_5_73:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_73
nop
P3445: !_DWLD [12] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_74:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i2
sub %i0, %i2, %i2
ldd [%i2 + 0], %f0
! 2 addresses covered
P3446: !_BLD [13] (FP) (Loop exit) (Branch target of P3925)
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i2 + 0] %asi, %f32
membar #Sync
! 4 addresses covered
fmovd %f32, %f2
fmovd %f34, %f18
fmovs %f19, %f4
fmovd %f40, %f18
fmovs %f18, %f5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovd %f4, %f30
!--
loop_exit_5_74:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_74
nop
ba P3447
nop
TARGET3925:
ba RET3925
nop
P3447: !_LD [11] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_75:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3448: !_LD [0] (Int) (Loop exit)
lduw [%i0 + 0], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_5_75:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_75
nop
P3449: !_BLD [4] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_76:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 4
sethi %hi(0xc0000), %l7
sub %i1, %l7, %i1
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P3450: !_DWLD [6] (Int)
ldx [%i1 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3451: !_LD [17] (Int) (Loop exit)
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 4], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
sethi %hi(0xc0000), %l3
add %i1, %l3, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_5_76:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_76
nop
P3452: !_DWLD [24] (Int) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_77:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_5_77:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_77
nop
P3453: !_DWLD [22] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_78:
sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
ldx [%i2 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3454: !_LD [14] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_5_78:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_78
nop
P3455: !_NOP (Int) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_79:
nop
loop_exit_5_79:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_79
nop
P3456: !_LD [2] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_80:
lduw [%i0 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3457: !_LD [26] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_5_80:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_80
nop
P3458: !_BLD [28] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_81:
wr %g0, 0xf0, %asi
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_5_81:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_81
nop
P3459: !_SWAP [2] (maybe <- 0x280000e) (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_82:
mov %l4, %o0
swap [%i0 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
add %l4, 1, %l4
P3460: !_LD [7] (Int) (Loop exit)
lduw [%i1 + 32], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_5_82:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_82
nop
P3461: !_BLD [23] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_83:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P3462: !_BLD [0] (FP) (Loop exit)
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i0 + 0] %asi, %f32
membar #Sync
! 4 addresses covered
fmovd %f32, %f4
fmovd %f34, %f18
fmovs %f19, %f6
fmovd %f40, %f18
fmovs %f18, %f7
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovd %f4, %f30
fmovd %f6, %f30
!--
loop_exit_5_83:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_83
nop
P3463: !_LD [12] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_84:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3464: !_LD [16] (Int) (Loop exit)
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 0], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_5_84:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_84
nop
P3465: !_DWLD [12] (Int) (Loop entry) (Branch target of P3877)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_85:
sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
ldx [%i3 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
ba P3466
nop
TARGET3877:
ba RET3877
nop
P3466: !_LD [2] (Int)
lduw [%i0 + 12], %o1
! move %o1(lower) -> %o1(upper)
sllx %o1, 32, %o1
P3467: !_LD [13] (Int) (Loop exit) (LE)
wr %g0, 0x88, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduwa [%i2 + 4] %asi, %l6
! move %l6(lower) -> %o1(lower)
or %l6, %o1, %o1
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_5_85:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_85
nop
P3468: !_BLD [10] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_86:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P3469: !_BLD [2] (FP) (Loop exit)
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i0 + 0] %asi, %f32
membar #Sync
! 4 addresses covered
fmovd %f32, %f4
fmovd %f34, %f18
fmovs %f19, %f6
fmovd %f40, %f18
fmovs %f18, %f7
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovd %f4, %f30
fmovd %f6, %f30
!--
loop_exit_5_86:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_86
nop
P3470: !_PREFETCH [6] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_87:
prefetch [%i1 + 12], 1
P3471: !_DWLD [21] (FP) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
sub %i0, %i2, %i2
ldd [%i2 + 0], %f0
! 2 addresses covered
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
!--
loop_exit_5_87:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_87
nop
P3472: !_BLD [30] (FP) (Loop entry) (Loop exit) (CBR)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_88:
wr %g0, 0xf0, %asi
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET3472
nop
RET3472:
! lfsr step begin
srlx %l0, 1, %o5
xnor %o5, %l0, %o5
sllx %o5, 63, %o5
or %o5, %l0, %l0
srlx %l0, 1, %l0
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_5_88:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_88
nop
P3473: !_DWLD [2] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_89:
ldx [%i0 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3474: !_LD [11] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 32], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_5_89:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_89
nop
P3475: !_BLD [27] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_90:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P3476: !_LD [24] (Int)
lduw [%i3 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3477: !_LD [8] (Int) (Loop exit)
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 0], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_5_90:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_90
nop
P3478: !_LD [17] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_91:
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3479: !_LD [20] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 0], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_5_91:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_91
nop
P3480: !_DWLD [15] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_92:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 32], %o0
! move %o0(upper) -> %o0(upper)
P3481: !_LD [8] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 0], %l3
! move %l3(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_5_92:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_92
nop
P3482: !_BLD [4] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_93:
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P3483: !_MEMBAR (Int) (Loop exit) (CBR)
membar #StoreLoad
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET3483
nop
RET3483:
! lfsr step begin
srlx %l0, 1, %o5
xnor %o5, %l0, %o5
sllx %o5, 63, %o5
or %o5, %l0, %l0
srlx %l0, 1, %l0
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_5_93:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_93
nop
P3484: !_DWLD [20] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_94:
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
P3485: !_DWLD [2] (FP) (Loop exit)
ldd [%i0 + 8], %f0
! 1 addresses covered
fmovs %f1, %f0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
loop_exit_5_94:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_94
nop
P3486: !_BSTC [2] (maybe <- 0x4200000d) (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_95:
wr %g0, 0xe0, %asi
! preparing store val #0, next val will be in f32
fmovs %f16, %f20
fadds %f16, %f17, %f16
! preparing store val #1, next val will be in f33
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #2, next val will be in f35
fmovd %f20, %f32
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #3, next val will be in f40
fmovd %f20, %f34
fmovs %f16, %f20
fadds %f16, %f17, %f16
fmovd %f20, %f40
membar #Sync
stda %f32, [%i0 + 0 ] %asi
membar #Sync
P3487: !_DWLD [5] (FP) (Loop exit)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 5
sethi %hi(0xc0000), %l3
sub %i1, %l3, %i1
ldd [%i1 + 0], %f0
! 2 addresses covered
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
!--
sethi %hi(0xc0000), %l6
add %i1, %l6, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_5_95:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_95
nop
P3488: !_DWLD [19] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_96:
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
ldx [%i2 + 32], %o0
! move %o0(upper) -> %o0(upper)
P3489: !_BLD [27] (FP) (CBR)
wr %g0, 0xf0, %asi
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET3489
nop
RET3489:
! lfsr step begin
srlx %l0, 1, %l6
xnor %l6, %l0, %l6
sllx %l6, 63, %l6
or %l6, %l0, %l0
srlx %l0, 1, %l0
P3490: !_LD [19] (Int) (Loop exit) (CBR)
lduw [%i2 + 32], %o5
! move %o5(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %o5, %o0, %o0
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET3490
nop
RET3490:
! lfsr step begin
srlx %l0, 1, %l3
xnor %l3, %l0, %l3
sllx %l3, 63, %l3
or %l3, %l0, %l0
srlx %l0, 1, %l0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_5_96:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_96
nop
P3491: !_LD [17] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_97:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3492: !_LD [17] (Int) (Loop exit)
lduw [%i2 + 4], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_5_97:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_97
nop
P3493: !_BLD [26] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_98:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P3494: !_DWLD [0] (Int) (Loop exit)
ldx [%i0 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_5_98:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_98
nop
P3495: !_DWLD [2] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_99:
ldx [%i0 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3496: !_LD [11] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 32], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_5_99:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_99
nop
P3497: !_LD [29] (Int) (Loop entry) (Branch target of P3325)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_100:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
ba P3498
nop
TARGET3325:
ba RET3325
nop
P3498: !_LD [11] (FP)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i2
sub %i0, %i2, %i2
ld [%i2 + 32], %f0
! 1 addresses covered
P3499: !_LD [9] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 4], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
loop_exit_5_100:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_100
nop
P3500: !_BLD [23] (FP) (Loop entry) (Loop exit) (Branch target of P3330)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_101:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_5_101:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_101
nop
ba P3501
nop
TARGET3330:
ba RET3330
nop
P3501: !_LD [14] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_102:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i3
sub %i0, %i3, %i3
ld [%i3 + 12], %f0
! 1 addresses covered
P3502: !_LD [8] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3503: !_LD [18] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
loop_exit_5_102:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_102
nop
P3504: !_DWLD [19] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_103:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 32], %o0
! move %o0(upper) -> %o0(upper)
P3505: !_LD [8] (Int) (Loop exit) (LE)
wr %g0, 0x88, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduwa [%i3 + 0] %asi, %l6
! move %l6(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_5_103:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_103
nop
P3506: !_MEMBAR (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_104:
membar #StoreLoad
P3507: !_LD [28] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3508: !_LD [29] (Int) (Loop exit)
lduw [%i2 + 4], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_5_104:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_104
nop
P3509: !_LD [15] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_105:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3510: !_LD [31] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 32], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_5_105:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_105
nop
P3511: !_DWLD [15] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_106:
sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
ldx [%i3 + 32], %o0
! move %o0(upper) -> %o0(upper)
P3512: !_LD [12] (Int) (Loop exit)
lduw [%i3 + 0], %o5
! move %o5(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_5_106:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_106
nop
P3513: !_DWLD [22] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_107:
sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
ldx [%i2 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3514: !_LD [22] (Int) (Loop exit)
lduw [%i2 + 12], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_5_107:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_107
nop
P3515: !_LD [5] (Int) (Loop entry) (CBR)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_108:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 5
sethi %hi(0xc0000), %o5
sub %i1, %o5, %i1
lduw [%i1 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET3515
nop
RET3515:
! lfsr step begin
srlx %l0, 1, %l7
xnor %l7, %l0, %l7
sllx %l7, 63, %l7
or %l7, %l0, %l0
srlx %l0, 1, %l0
P3516: !_DWLD [4] (Int)
ldx [%i1 + 0], %l3
! move %l3(upper) -> %o0(lower)
srlx %l3, 32, %o5
or %o5, %o0, %o0
! move %l3(lower) -> %o1(upper)
sllx %l3, 32, %o1
P3517: !_LD [2] (Int) (Loop exit)
lduw [%i0 + 12], %o5
! move %o5(lower) -> %o1(lower)
or %o5, %o1, %o1
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
sethi %hi(0xc0000), %l3
add %i1, %l3, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_5_108:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_108
nop
P3518: !_LD [23] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_109:
sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3519: !_LD [2] (Int) (Loop exit)
lduw [%i0 + 12], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_5_109:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_109
nop
P3520: !_LD [31] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_110:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3521: !_LD [20] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_5_110:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_110
nop
P3522: !_BLD [16] (FP) (Loop entry) (CBR)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_111:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET3522
nop
RET3522:
! lfsr step begin
srlx %l0, 1, %l6
xnor %l6, %l0, %l6
sllx %l6, 63, %l6
or %l6, %l0, %l0
srlx %l0, 1, %l0
P3523: !_BLD [22] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f32
membar #Sync
! 4 addresses covered
fmovd %f32, %f4
fmovd %f34, %f18
fmovs %f19, %f6
fmovd %f40, %f18
fmovs %f18, %f7
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovd %f4, %f30
fmovd %f6, %f30
!--
loop_exit_5_111:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_111
nop
P3524: !_FLUSHI [30] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_112:
flush %g0
P3525: !_FLUSHI [24] (Int) (Loop exit)
flush %g0
loop_exit_5_112:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_112
nop
P3526: !_MEMBAR (Int) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_113:
membar #StoreLoad
loop_exit_5_113:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_113
nop
P3527: !_DWLD [24] (Int) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_114:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_5_114:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_114
nop
P3528: !_LD [9] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_115:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3529: !_LD [29] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_5_115:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_115
nop
P3530: !_PREFETCH [12] (Int) (Loop entry) (Loop exit) (CBR)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_116:
sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
prefetch [%i3 + 0], 1
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET3530
nop
RET3530:
! lfsr step begin
srlx %l0, 1, %l6
xnor %l6, %l0, %l6
sllx %l6, 63, %l6
or %l6, %l0, %l0
srlx %l0, 1, %l0
loop_exit_5_116:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_116
nop
P3531: !_DWLD [28] (Int) (Loop entry) (Branch target of P3879)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_117:
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
ldx [%i2 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
ba P3532
nop
TARGET3879:
ba RET3879
nop
P3532: !_BLD [7] (FP) (Loop exit) (CBR)
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET3532
nop
RET3532:
! lfsr step begin
srlx %l0, 1, %l7
xnor %l7, %l0, %l7
sllx %l7, 63, %l7
or %l7, %l0, %l0
srlx %l0, 1, %l0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_5_117:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_117
nop
P3533: !_BLD [26] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_118:
wr %g0, 0xf0, %asi
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P3534: !_BSTC [7] (maybe <- 0x42000011) (FP) (Loop exit)
wr %g0, 0xe0, %asi
! preparing store val #0, next val will be in f32
fmovs %f16, %f20
fadds %f16, %f17, %f16
! preparing store val #1, next val will be in f33
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #2, next val will be in f35
fmovd %f20, %f32
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #3, next val will be in f40
fmovd %f20, %f34
fmovs %f16, %f20
fadds %f16, %f17, %f16
fmovd %f20, %f40
membar #Sync
stda %f32, [%i1 + 0 ] %asi
membar #Sync
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_5_118:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_118
nop
P3535: !_BLD [15] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_119:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P3536: !_BLD [19] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f32
membar #Sync
! 4 addresses covered
fmovd %f32, %f4
fmovd %f34, %f18
fmovs %f19, %f6
fmovd %f40, %f18
fmovs %f18, %f7
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovd %f4, %f30
fmovd %f6, %f30
!--
loop_exit_5_119:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_119
nop
P3537: !_BLD [29] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_120:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_5_120:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_120
nop
P3538: !_ST [13] (maybe <- 0x280000f) (Int) (Loop entry) (LE)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_121:
wr %g0, 0x88, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i3
sub %i0, %i3, %i3
! Change single-word-level endianess (big endian <-> little endian)
sethi %hi(0xff00ff00), %l7
or %l7, %lo(0xff00ff00), %l7
and %l4, %l7, %o5
srl %o5, 8, %o5
sll %l4, 8, %l6
and %l6, %l7, %l6
or %l6, %o5, %l6
srl %l6, 16, %o5
sll %l6, 16, %l6
srl %l6, 0, %l6
or %l6, %o5, %l6
stwa %l6, [%i3 + 4] %asi
add %l4, 1, %l4
P3539: !_BLD [5] (FP) (Loop exit)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 5
sethi %hi(0xc0000), %l3
sub %i1, %l3, %i1
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
sethi %hi(0xc0000), %l6
add %i1, %l6, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_5_121:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_121
nop
P3540: !_DWLD [29] (Int) (Loop entry) (CBR)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_122:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET3540
nop
RET3540:
! lfsr step begin
srlx %l0, 1, %l3
xnor %l3, %l0, %l3
sllx %l3, 63, %l3
or %l3, %l0, %l0
srlx %l0, 1, %l0
P3541: !_BLD [16] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_5_122:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_122
nop
P3542: !_DWLD [2] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_123:
ldx [%i0 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3543: !_DWLD [4] (Int)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 4
sethi %hi(0xc0000), %l6
sub %i1, %l6, %i1
ldx [%i1 + 0], %o5
! move %o5(upper) -> %o0(lower)
srlx %o5, 32, %l7
or %l7, %o0, %o0
! move %o5(lower) -> %o1(upper)
sllx %o5, 32, %o1
P3544: !_LD [10] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %l6
! move %l6(lower) -> %o1(lower)
or %l6, %o1, %o1
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
sethi %hi(0xc0000), %l7
add %i1, %l7, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_5_123:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_123
nop
P3545: !_BLD [13] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_124:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_5_124:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_124
nop
P3546: !_DWLD [27] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_125:
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
ldx [%i2 + 32], %o0
! move %o0(upper) -> %o0(upper)
P3547: !_DWLD [2] (FP)
ldd [%i0 + 8], %f0
! 1 addresses covered
fmovs %f1, %f0
P3548: !_LD [24] (Int) (Loop exit)
lduw [%i2 + 0], %l6
! move %l6(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
loop_exit_5_125:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_125
nop
P3549: !_SWAP [10] (maybe <- 0x2800010) (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_126:
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
mov %l4, %o0
swap [%i3 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
add %l4, 1, %l4
P3550: !_BLD [3] (FP)
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i0 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P3551: !_LD [9] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_5_126:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_126
nop
P3552: !_LD [20] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_127:
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3553: !_LD [19] (Int) (Loop exit)
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 32], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_5_127:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_127
nop
P3554: !_BLD [15] (FP) (Loop entry) (Loop exit) (Branch target of P3969)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_128:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_5_128:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_128
nop
ba P3555
nop
TARGET3969:
ba RET3969
nop
P3555: !_DWLD [7] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_129:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 7
sethi %hi(0xc0000), %l7
sub %i1, %l7, %i1
ldx [%i1 + 32], %o0
! move %o0(upper) -> %o0(upper)
P3556: !_LD [9] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %l7
! move %l7(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
sethi %hi(0xc0000), %o5
add %i1, %o5, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_5_129:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_129
nop
P3557: !_DWLD [9] (Int) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_130:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_5_130:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_130
nop
P3558: !_LD [1] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_131:
lduw [%i0 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3559: !_LD [17] (Int) (Loop exit) (LE)
wr %g0, 0x88, %asi
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduwa [%i2 + 4] %asi, %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_5_131:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_131
nop
P3560: !_NOP (Int) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_132:
nop
loop_exit_5_132:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_132
nop
P3561: !_DWLD [29] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_133:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
P3562: !_BLD [8] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_5_133:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_133
nop
P3563: !_LD [26] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_134:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3564: !_LD [23] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 32], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_5_134:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_134
nop
P3565: !_DWLD [26] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_135:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3566: !_LD [16] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 0], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_5_135:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_135
nop
P3567: !_BLD [9] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_136:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P3568: !_BLD [19] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f32
membar #Sync
! 4 addresses covered
fmovd %f32, %f4
fmovd %f34, %f18
fmovs %f19, %f6
fmovd %f40, %f18
fmovs %f18, %f7
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovd %f4, %f30
fmovd %f6, %f30
!--
loop_exit_5_136:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_136
nop
P3569: !_BLD [19] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_137:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_5_137:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_137
nop
P3570: !_BLD [22] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_138:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P3571: !_BLD [2] (FP) (Loop exit) (Branch target of P3840)
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i0 + 0] %asi, %f32
membar #Sync
! 4 addresses covered
fmovd %f32, %f4
fmovd %f34, %f18
fmovs %f19, %f6
fmovd %f40, %f18
fmovs %f18, %f7
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovd %f4, %f30
fmovd %f6, %f30
!--
loop_exit_5_138:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_138
nop
ba P3572
nop
TARGET3840:
ba RET3840
nop
P3572: !_BLD [11] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_139:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_5_139:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_139
nop
P3573: !_NOP (Int) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_140:
nop
loop_exit_5_140:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_140
nop
P3574: !_DWLD [14] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_141:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3575: !_BLD [14] (FP)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P3576: !_LD [1] (Int) (Loop exit)
lduw [%i0 + 4], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_5_141:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_141
nop
P3577: !_DWLD [18] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_142:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3578: !_LD [26] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_5_142:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_142
nop
P3579: !_LD [5] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_143:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 5
sethi %hi(0xc0000), %l3
sub %i1, %l3, %i1
lduw [%i1 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3580: !_SWAP [31] (maybe <- 0x2800011) (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i2
sub %i0, %i2, %i2
mov %l4, %l6
swap [%i2 + 32], %l6
! move %l6(lower) -> %o0(lower)
srl %l6, 0, %o5
or %o5, %o0, %o0
add %l4, 1, %l4
!---- flushing int results buffer----
mov %o0, %l5
sethi %hi(0xc0000), %l7
add %i1, %l7, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_5_143:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_143
nop
P3581: !_FLUSHI [16] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_144:
flush %g0
P3582: !_BLD [29] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_5_144:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_144
nop
P3583: !_LD [8] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_145:
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3584: !_LD [18] (Int) (Loop exit)
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 12], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_5_145:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_145
nop
P3585: !_LD [14] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_146:
sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3586: !_LD [21] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 4], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_5_146:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_146
nop
P3587: !_LD [12] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_147:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3588: !_LD [9] (Int) (Loop exit)
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 4], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_5_147:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_147
nop
P3589: !_DWLD [30] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_148:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3590: !_LD [22] (Int) (Loop exit) (CBR) (Branch target of P3682)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET3590
nop
RET3590:
! lfsr step begin
srlx %l0, 1, %l3
xnor %l3, %l0, %l3
sllx %l3, 63, %l3
or %l3, %l0, %l0
srlx %l0, 1, %l0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_5_148:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_148
nop
ba P3591
nop
TARGET3682:
ba RET3682
nop
P3591: !_DWLD [15] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_149:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 32], %o0
! move %o0(upper) -> %o0(upper)
P3592: !_BLD [13] (FP)
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P3593: !_LD [20] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %o5
! move %o5(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_5_149:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_149
nop
P3594: !_BLD [11] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_150:
wr %g0, 0xf0, %asi
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_5_150:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_150
nop
P3595: !_CASX [2] (maybe <- 0x2800012) (Int) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_151:
add %i0, 8, %l3
ldx [%l3], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
mov %o0, %o5
mov %l4, %o1
casx [%l3], %o5, %o1
! move %o1(upper) -> %o1(upper)
! move %o1(lower) -> %o1(lower)
add %l4, 1, %l4
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_5_151:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_151
nop
P3596: !_DWLD [15] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_152:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 32], %o0
! move %o0(upper) -> %o0(upper)
P3597: !_DWLD [11] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 32], %l3
! move %l3(upper) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
srlx %l3, 32, %o5
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_5_152:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_152
nop
P3598: !_LD [27] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_153:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i3
sub %i0, %i3, %i3
ld [%i3 + 32], %f0
! 1 addresses covered
P3599: !_DWLD [13] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
loop_exit_5_153:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_153
nop
P3600: !_BLD [23] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_154:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_5_154:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_154
nop
P3601: !_DWLD [4] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_155:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 4
sethi %hi(0xc0000), %o5
sub %i1, %o5, %i1
ldx [%i1 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
P3602: !_BST [25] (maybe <- 0x42000015) (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i2
sub %i0, %i2, %i2
! preparing store val #0, next val will be in f32
fmovs %f16, %f20
fadds %f16, %f17, %f16
! preparing store val #1, next val will be in f33
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #2, next val will be in f35
fmovd %f20, %f32
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #3, next val will be in f40
fmovd %f20, %f34
fmovs %f16, %f20
fadds %f16, %f17, %f16
fmovd %f20, %f40
membar #Sync
stda %f32, [%i2 + 0 ] %asi
membar #Sync
!---- flushing int results buffer----
mov %o0, %l5
sethi %hi(0xc0000), %l6
add %i1, %l6, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_5_155:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_155
nop
P3603: !_LD [25] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_156:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3604: !_BLD [14] (FP)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P3605: !_LD [2] (Int) (Loop exit)
lduw [%i0 + 12], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_5_156:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_156
nop
P3606: !_BLD [16] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_157:
wr %g0, 0xf0, %asi
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_5_157:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_157
nop
P3607: !_DWLD [16] (Int) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_158:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_5_158:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_158
nop
P3608: !_DWLD [8] (Int) (Loop entry) (Loop exit) (CBR) (Branch target of P3489)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_159:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET3608
nop
RET3608:
! lfsr step begin
srlx %l0, 1, %l3
xnor %l3, %l0, %l3
sllx %l3, 63, %l3
or %l3, %l0, %l0
srlx %l0, 1, %l0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_5_159:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_159
nop
ba P3609
nop
TARGET3489:
ba RET3489
nop
P3609: !_CASX [1] (maybe <- 0x2800013) (Int) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_160:
ldx [%i0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
mov %o0, %o5
sllx %l4, 32, %o1
add %l4, 1, %l4
or %l4, %o1, %o1
casx [%i0], %o5, %o1
! move %o1(upper) -> %o1(upper)
! move %o1(lower) -> %o1(lower)
add %l4, 1, %l4
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_5_160:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_160
nop
P3610: !_LD [14] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_161:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i2
sub %i0, %i2, %i2
ld [%i2 + 12], %f0
! 1 addresses covered
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
loop_exit_5_161:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_161
nop
P3611: !_LD [0] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_162:
lduw [%i0 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3612: !_NOP (Int)
nop
P3613: !_LD [2] (Int) (Loop exit)
lduw [%i0 + 12], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_5_162:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_162
nop
P3614: !_LD [16] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_163:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3615: !_LD [19] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 32], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_5_163:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_163
nop
P3616: !_CAS [11] (maybe <- 0x2800015) (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_164:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i3
sub %i0, %i3, %i3
add %i3, 32, %o5
lduw [%o5], %o0
mov %o0, %l7
! move %l7(lower) -> %o0(upper)
sllx %l7, 32, %o0
mov %l4, %l6
cas [%o5], %l7, %l6
! move %l6(lower) -> %o0(lower)
srl %l6, 0, %l7
or %l7, %o0, %o0
add %l4, 1, %l4
P3617: !_BLD [15] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_5_164:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_164
nop
P3618: !_BLD [18] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_165:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P3619: !_DWLD [16] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_5_165:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_165
nop
P3620: !_DWLD [16] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_166:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
P3621: !_DWLD [0] (Int) (Loop exit)
ldx [%i0 + 0], %o1
! move %o1(upper) -> %o1(upper)
! move %o1(lower) -> %o1(lower)
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_5_166:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_166
nop
P3622: !_LD [21] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_167:
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3623: !_LD [18] (Int) (Loop exit) (Branch target of P3727)
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 12], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_5_167:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_167
nop
ba P3624
nop
TARGET3727:
ba RET3727
nop
P3624: !_REPLACEMENT [31] (Int) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_168:
sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS2_O), %i2
sub %i0, %i2, %i2
sethi %hi(0x10000), %l3
ld [%i2+32], %l7
st %l7, [%i2+32]
add %i2, %l3, %l6
ld [%l6+32], %l7
st %l7, [%l6+32]
add %l6, %l3, %l6
ld [%l6+32], %l7
st %l7, [%l6+32]
add %l6, %l3, %l6
ld [%l6+32], %l7
st %l7, [%l6+32]
loop_exit_5_168:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_168
nop
P3625: !_CAS [10] (maybe <- 0x2800016) (Int) (Loop entry) (Loop exit) (Branch target of P3634)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_169:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
sub %i0, %i3, %i3
add %i3, 12, %l7
lduw [%l7], %o0
mov %o0, %l6
! move %l6(lower) -> %o0(upper)
sllx %l6, 32, %o0
mov %l4, %l3
cas [%l7], %l6, %l3
! move %l3(lower) -> %o0(lower)
srl %l3, 0, %l6
or %l6, %o0, %o0
add %l4, 1, %l4
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_5_169:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_169
nop
ba P3626
nop
TARGET3634:
ba RET3634
nop
P3626: !_DWLD [15] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_170:
sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
ldx [%i2 + 32], %o0
! move %o0(upper) -> %o0(upper)
P3627: !_LD [18] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %l7
! move %l7(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_5_170:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_170
nop
P3628: !_DWLD [11] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_171:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
sub %i0, %i2, %i2
ldd [%i2 + 32], %f0
! 1 addresses covered
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
loop_exit_5_171:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_171
nop
P3629: !_DWLD [27] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_172:
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
ldx [%i3 + 32], %o0
! move %o0(upper) -> %o0(upper)
P3630: !_MEMBAR (Int)
membar #StoreLoad
P3631: !_LD [2] (Int) (Loop exit)
lduw [%i0 + 12], %l7
! move %l7(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_5_172:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_172
nop
P3632: !_LD [31] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_173:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3633: !_LD [16] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_5_173:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_173
nop
P3634: !_NOP (Int) (Loop entry) (CBR)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_174:
nop
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET3634
nop
RET3634:
! lfsr step begin
srlx %l0, 1, %l7
xnor %l7, %l0, %l7
sllx %l7, 63, %l7
or %l7, %l0, %l0
srlx %l0, 1, %l0
P3635: !_REPLACEMENT [28] (Int) (Loop exit) (Branch target of P3648)
sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
sethi %hi(0x10000), %l3
ld [%i2+0], %l7
st %l7, [%i2+0]
add %i2, %l3, %l6
ld [%l6+0], %l7
st %l7, [%l6+0]
add %l6, %l3, %l6
ld [%l6+0], %l7
st %l7, [%l6+0]
add %l6, %l3, %l6
ld [%l6+0], %l7
st %l7, [%l6+0]
loop_exit_5_174:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_174
nop
ba P3636
nop
TARGET3648:
ba RET3648
nop
P3636: !_BLD [8] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_175:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P3637: !_DWLD [25] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_5_175:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_175
nop
P3638: !_LD [31] (Int) (Loop entry) (Branch target of P3416)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_176:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
ba P3639
nop
TARGET3416:
ba RET3416
nop
P3639: !_LD [0] (Int) (Loop exit)
lduw [%i0 + 0], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_5_176:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_176
nop
P3640: !_BLD [2] (FP) (Loop entry) (Loop exit) (CBR)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_177:
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i0 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET3640
nop
RET3640:
! lfsr step begin
srlx %l0, 1, %l7
xnor %l7, %l0, %l7
sllx %l7, 63, %l7
or %l7, %l0, %l0
srlx %l0, 1, %l0
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_5_177:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_177
nop
P3641: !_BLD [17] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_178:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_5_178:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_178
nop
P3642: !_BLD [26] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_179:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_5_179:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_179
nop
P3643: !_BLD [22] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_180:
wr %g0, 0xf0, %asi
sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P3644: !_LD [13] (Int)
sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3645: !_LD [28] (Int) (Loop exit)
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 0], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_5_180:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_180
nop
P3646: !_DWLD [15] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_181:
sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
ldx [%i3 + 32], %o0
! move %o0(upper) -> %o0(upper)
P3647: !_LD [22] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %l7
! move %l7(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_5_181:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_181
nop
P3648: !_BLD [22] (FP) (Loop entry) (CBR)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_182:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET3648
nop
RET3648:
! lfsr step begin
srlx %l0, 1, %l3
xnor %l3, %l0, %l3
sllx %l3, 63, %l3
or %l3, %l0, %l0
srlx %l0, 1, %l0
P3649: !_DWLD [10] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3650: !_LD [26] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_5_182:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_182
nop
P3651: !_BLD [1] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_183:
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i0 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P3652: !_DWLD [1] (Int) (Loop exit)
ldx [%i0 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_5_183:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_183
nop
P3653: !_LD [21] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_184:
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
sub %i0, %i2, %i2
ld [%i2 + 4], %f0
! 1 addresses covered
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
loop_exit_5_184:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_184
nop
P3654: !_DWLD [23] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_185:
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 32], %o0
! move %o0(upper) -> %o0(upper)
P3655: !_LD [30] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %l6
! move %l6(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_5_185:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_185
nop
P3656: !_LD [27] (Int) (Loop entry) (CBR)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_186:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET3656
nop
RET3656:
! lfsr step begin
srlx %l0, 1, %l6
xnor %l6, %l0, %l6
sllx %l6, 63, %l6
or %l6, %l0, %l0
srlx %l0, 1, %l0
P3657: !_LD [13] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_5_186:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_186
nop
P3658: !_LD [25] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_187:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3659: !_LD [23] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 32], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_5_187:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_187
nop
P3660: !_NOP (Int) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_188:
nop
loop_exit_5_188:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_188
nop
P3661: !_DWLD [23] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_189:
sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
ldx [%i3 + 32], %o0
! move %o0(upper) -> %o0(upper)
P3662: !_LD [24] (Int) (Loop exit) (Branch target of P3663)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 0], %l6
! move %l6(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_5_189:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_189
nop
ba P3663
nop
TARGET3663:
ba RET3663
nop
P3663: !_LD [0] (Int) (Loop entry) (CBR)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_190:
lduw [%i0 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET3663
nop
RET3663:
! lfsr step begin
srlx %l0, 1, %l7
xnor %l7, %l0, %l7
sllx %l7, 63, %l7
or %l7, %l0, %l0
srlx %l0, 1, %l0
P3664: !_DWLD [4] (Int)
ldx [%i1 + 0], %l3
! move %l3(upper) -> %o0(lower)
srlx %l3, 32, %o5
or %o5, %o0, %o0
! move %l3(lower) -> %o1(upper)
sllx %l3, 32, %o1
P3665: !_LD [20] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %o5
! move %o5(lower) -> %o1(lower)
or %o5, %o1, %o1
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_5_190:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_190
nop
P3666: !_DWLD [29] (Int) (Loop entry) (Branch target of P3717)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_191:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
ba P3667
nop
TARGET3717:
ba RET3717
nop
P3667: !_DWLD [25] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 0], %o1
! move %o1(upper) -> %o1(upper)
! move %o1(lower) -> %o1(lower)
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_5_191:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_191
nop
P3668: !_LD [19] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_192:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3669: !_DWLD [5] (Int)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 5
sethi %hi(0xc0000), %l6
sub %i1, %l6, %i1
ldx [%i1 + 0], %o5
! move %o5(upper) -> %o0(lower)
srlx %o5, 32, %l7
or %l7, %o0, %o0
! move %o5(lower) -> %o1(upper)
sllx %o5, 32, %o1
P3670: !_LD [0] (Int) (Loop exit)
lduw [%i0 + 0], %l6
! move %l6(lower) -> %o1(lower)
or %l6, %o1, %o1
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
sethi %hi(0xc0000), %l7
add %i1, %l7, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_5_192:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_192
nop
P3671: !_BLD [26] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_193:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_5_193:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_193
nop
P3672: !_BLD [25] (FP) (Loop entry) (CBR)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_194:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET3672
nop
RET3672:
! lfsr step begin
srlx %l0, 1, %l6
xnor %l6, %l0, %l6
sllx %l6, 63, %l6
or %l6, %l0, %l0
srlx %l0, 1, %l0
P3673: !_BLD [31] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f32
membar #Sync
! 4 addresses covered
fmovd %f32, %f4
fmovd %f34, %f18
fmovs %f19, %f6
fmovd %f40, %f18
fmovs %f18, %f7
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovd %f4, %f30
fmovd %f6, %f30
!--
loop_exit_5_194:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_194
nop
P3674: !_BLD [19] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_195:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_5_195:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_195
nop
P3675: !_LD [19] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_196:
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3676: !_LD [7] (Int) (Loop exit) (Branch target of P3905)
lduw [%i1 + 32], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_5_196:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_196
nop
ba P3677
nop
TARGET3905:
ba RET3905
nop
P3677: !_LD [20] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_197:
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
sub %i0, %i2, %i2
ld [%i2 + 0], %f0
! 1 addresses covered
P3678: !_LD [15] (FP) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i3
sub %i0, %i3, %i3
ld [%i3 + 32], %f1
! 1 addresses covered
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
!--
loop_exit_5_197:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_197
nop
P3679: !_DWLD [26] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_198:
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
ldx [%i2 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3680: !_LD [19] (Int) (Loop exit)
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 32], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_5_198:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_198
nop
P3681: !_LD [1] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_199:
lduw [%i0 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3682: !_LD [27] (Int) (Loop exit) (CBR)
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 32], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET3682
nop
RET3682:
! lfsr step begin
srlx %l0, 1, %l3
xnor %l3, %l0, %l3
sllx %l3, 63, %l3
or %l3, %l0, %l0
srlx %l0, 1, %l0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_5_199:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_199
nop
P3683: !_LD [11] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_200:
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3684: !_BLD [3] (FP)
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i0 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P3685: !_LD [22] (Int) (Loop exit) (Branch target of P3540)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_5_200:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_200
nop
ba P3686
nop
TARGET3540:
ba RET3540
nop
P3686: !_BLD [4] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_201:
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P3687: !_LD [13] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3688: !_LD [26] (Int) (Loop exit)
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 12], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_5_201:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_201
nop
P3689: !_BLD [15] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_202:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P3690: !_LD [26] (Int)
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3691: !_LD [4] (Int) (Loop exit) (LE)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 4
sethi %hi(0xc0000), %l7
sub %i1, %l7, %i1
wr %g0, 0x88, %asi
lduwa [%i1 + 0] %asi, %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
sethi %hi(0xc0000), %l6
add %i1, %l6, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_5_202:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_202
nop
P3692: !_LD [27] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_203:
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3693: !_LD [25] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_5_203:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_203
nop
P3694: !_NOP (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_204:
nop
P3695: !_DWLD [2] (Int)
ldx [%i0 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3696: !_LD [2] (Int) (Loop exit)
lduw [%i0 + 12], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_5_204:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_204
nop
P3697: !_ST [9] (maybe <- 0x2800017) (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_205:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i3
sub %i0, %i3, %i3
stw %l4, [%i3 + 4 ]
add %l4, 1, %l4
P3698: !_FLUSHI [7] (Int) (Loop exit)
flush %g0
loop_exit_5_205:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_205
nop
P3699: !_DWLD [1] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_206:
ldx [%i0 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
P3700: !_BLD [8] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_5_206:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_206
nop
P3701: !_BLD [13] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_207:
wr %g0, 0xf0, %asi
sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_5_207:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_207
nop
P3702: !_DWLD [5] (Int) (Loop entry) (LE)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_208:
wr %g0, 0x88, %asi
ldxa [%i1 + 0] %asi, %l7
! move %l7(lower) -> %o0(upper)
sllx %l7, 32, %o0
! move %l7(upper) -> %o0(lower)
srlx %l7, 32, %l6
or %l6, %o0, %o0
P3703: !_DWLD [17] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 0], %o1
! move %o1(upper) -> %o1(upper)
! move %o1(lower) -> %o1(lower)
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_5_208:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_208
nop
P3704: !_DWLD [25] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_209:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
P3705: !_DWLD [13] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 0], %o1
! move %o1(upper) -> %o1(upper)
! move %o1(lower) -> %o1(lower)
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_5_209:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_209
nop
P3706: !_DWLD [26] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_210:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3707: !_LD [26] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_5_210:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_210
nop
P3708: !_DWLD [13] (Int) (Loop entry) (CBR)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_211:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET3708
nop
RET3708:
! lfsr step begin
srlx %l0, 1, %l6
xnor %l6, %l0, %l6
sllx %l6, 63, %l6
or %l6, %l0, %l0
srlx %l0, 1, %l0
P3709: !_BLD [22] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_5_211:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_211
nop
P3710: !_LD [28] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_212:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3711: !_FLUSHI [13] (Int)
flush %g0
P3712: !_LD [26] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_5_212:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_212
nop
P3713: !_BLD [20] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_213:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P3714: !_DWLD [7] (Int)
ldx [%i1 + 32], %o0
! move %o0(upper) -> %o0(upper)
P3715: !_LD [29] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %o5
! move %o5(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_5_213:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_213
nop
P3716: !_BLD [29] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_214:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P3717: !_BLD [23] (FP) (Loop exit) (CBR)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f32
membar #Sync
! 4 addresses covered
fmovd %f32, %f4
fmovd %f34, %f18
fmovs %f19, %f6
fmovd %f40, %f18
fmovs %f18, %f7
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET3717
nop
RET3717:
! lfsr step begin
srlx %l0, 1, %l7
xnor %l7, %l0, %l7
sllx %l7, 63, %l7
or %l7, %l0, %l0
srlx %l0, 1, %l0
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovd %f4, %f30
fmovd %f6, %f30
!--
loop_exit_5_214:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_214
nop
P3718: !_LD [10] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_215:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3719: !_DWLD [14] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 8], %l3
! move %l3(lower) -> %o0(lower)
srl %l3, 0, %o5
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_5_215:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_215
nop
P3720: !_BLD [1] (FP) (Loop entry) (Loop exit) (Branch target of P3490)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_216:
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i0 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_5_216:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_216
nop
ba P3721
nop
TARGET3490:
ba RET3490
nop
P3721: !_BLD [6] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_217:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 6
sethi %hi(0xc0000), %o5
sub %i1, %o5, %i1
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P3722: !_BST [23] (maybe <- 0x42000019) (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
sub %i0, %i3, %i3
! preparing store val #0, next val will be in f32
fmovs %f16, %f20
fadds %f16, %f17, %f16
! preparing store val #1, next val will be in f33
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #2, next val will be in f35
fmovd %f20, %f32
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #3, next val will be in f40
fmovd %f20, %f34
fmovs %f16, %f20
fadds %f16, %f17, %f16
fmovd %f20, %f40
membar #Sync
stda %f32, [%i3 + 0 ] %asi
membar #Sync
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
sethi %hi(0xc0000), %o5
add %i1, %o5, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_5_217:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_217
nop
P3723: !_DWLD [16] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_218:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
P3724: !_LD [24] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %o1
! move %o1(lower) -> %o1(upper)
sllx %o1, 32, %o1
P3725: !_LD [27] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 32], %o5
! move %o5(lower) -> %o1(lower)
or %o5, %o1, %o1
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_5_218:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_218
nop
P3726: !_LD [31] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_219:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3727: !_LD [21] (Int) (Loop exit) (CBR)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET3727
nop
RET3727:
! lfsr step begin
srlx %l0, 1, %l7
xnor %l7, %l0, %l7
sllx %l7, 63, %l7
or %l7, %l0, %l0
srlx %l0, 1, %l0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_5_219:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_219
nop
P3728: !_DWLD [24] (Int) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_220:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_5_220:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_220
nop
P3729: !_BLD [17] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_221:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_5_221:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_221
nop
P3730: !_DWLD [28] (Int) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_222:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_5_222:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_222
nop
P3731: !_BLD [19] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_223:
wr %g0, 0xf0, %asi
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P3732: !_CAS [28] (maybe <- 0x2800018) (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3], %o0
mov %o0, %l6
! move %l6(lower) -> %o0(upper)
sllx %l6, 32, %o0
mov %l4, %l3
cas [%i3], %l6, %l3
! move %l3(lower) -> %o0(lower)
srl %l3, 0, %l6
or %l6, %o0, %o0
add %l4, 1, %l4
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_5_223:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_223
nop
P3733: !_BLD [1] (FP) (Loop entry) (Loop exit) (CBR)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_224:
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i0 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET3733
nop
RET3733:
! lfsr step begin
srlx %l0, 1, %o5
xnor %o5, %l0, %o5
sllx %o5, 63, %o5
or %o5, %l0, %l0
srlx %l0, 1, %l0
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_5_224:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_224
nop
P3734: !_BLD [22] (FP) (Loop entry) (Loop exit) (Branch target of P3472)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_225:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_5_225:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_225
nop
ba P3735
nop
TARGET3472:
ba RET3472
nop
P3735: !_BLD [12] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_226:
wr %g0, 0xf0, %asi
sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P3736: !_BLD [27] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f32
membar #Sync
! 4 addresses covered
fmovd %f32, %f4
fmovd %f34, %f18
fmovs %f19, %f6
fmovd %f40, %f18
fmovs %f18, %f7
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovd %f4, %f30
fmovd %f6, %f30
!--
loop_exit_5_226:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_226
nop
P3737: !_DWST [11] (maybe <- 0x2800019) (Int) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_227:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
sub %i0, %i3, %i3
mov %l4, %l6
sllx %l6, 32, %l6
stx %l6, [%i3 + 32 ]
add %l4, 1, %l4
loop_exit_5_227:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_227
nop
P3738: !_DWLD [13] (Int) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_228:
sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
ldx [%i2 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_5_228:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_228
nop
P3739: !_BLD [18] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_229:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P3740: !_LD [26] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3741: !_LD [13] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 4], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_5_229:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_229
nop
P3742: !_LD [13] (Int) (Loop entry) (LE)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_230:
wr %g0, 0x88, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduwa [%i2 + 4] %asi, %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3743: !_DWLD [19] (Int) (Loop exit) (CBR)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 32], %o5
! move %o5(upper) -> %o0(lower)
srlx %o5, 32, %l7
or %l7, %o0, %o0
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET3743
nop
RET3743:
! lfsr step begin
srlx %l0, 1, %l3
xnor %l3, %l0, %l3
sllx %l3, 63, %l3
or %l3, %l0, %l0
srlx %l0, 1, %l0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_5_230:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_230
nop
P3744: !_FLUSHI [8] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_231:
flush %g0
P3745: !_LD [20] (Int)
sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3746: !_LD [23] (Int) (Loop exit)
lduw [%i2 + 32], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_5_231:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_231
nop
P3747: !_BLD [7] (FP) (Loop entry) (Loop exit) (Branch target of P3515)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_232:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 7
sethi %hi(0xc0000), %l3
sub %i1, %l3, %i1
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
sethi %hi(0xc0000), %l6
add %i1, %l6, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_5_232:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_232
nop
ba P3748
nop
TARGET3515:
ba RET3515
nop
P3748: !_LD [7] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_233:
ld [%i1 + 32], %f0
! 1 addresses covered
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
loop_exit_5_233:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_233
nop
P3749: !_FLUSHI [20] (Int) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_234:
flush %g0
loop_exit_5_234:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_234
nop
P3750: !_BLD [27] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_235:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P3751: !_BLD [22] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f32
membar #Sync
! 4 addresses covered
fmovd %f32, %f4
fmovd %f34, %f18
fmovs %f19, %f6
fmovd %f40, %f18
fmovs %f18, %f7
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovd %f4, %f30
fmovd %f6, %f30
!--
loop_exit_5_235:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_235
nop
P3752: !_LD [1] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_236:
lduw [%i0 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3753: !_BLD [19] (FP)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P3754: !_LD [3] (Int) (Loop exit)
lduw [%i0 + 32], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_5_236:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_236
nop
P3755: !_DWLD [31] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_237:
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
ldx [%i2 + 32], %o0
! move %o0(upper) -> %o0(upper)
P3756: !_LD [8] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %l6
! move %l6(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_5_237:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_237
nop
P3757: !_BLD [0] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_238:
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i0 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_5_238:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_238
nop
P3758: !_BLD [28] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_239:
wr %g0, 0xf0, %asi
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P3759: !_LD [13] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3760: !_LD [6] (Int) (Loop exit)
lduw [%i1 + 12], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_5_239:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_239
nop
P3761: !_LD [14] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_240:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3762: !_LD [2] (Int) (Loop exit)
lduw [%i0 + 12], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_5_240:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_240
nop
P3763: !_LD [9] (FP) (Loop entry) (Loop exit) (CBR)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_241:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i3
sub %i0, %i3, %i3
ld [%i3 + 4], %f0
! 1 addresses covered
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET3763
nop
RET3763:
! lfsr step begin
srlx %l0, 1, %l7
xnor %l7, %l0, %l7
sllx %l7, 63, %l7
or %l7, %l0, %l0
srlx %l0, 1, %l0
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
loop_exit_5_241:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_241
nop
P3764: !_LD [27] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_242:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i2
sub %i0, %i2, %i2
ld [%i2 + 32], %f0
! 1 addresses covered
P3765: !_SWAP [21] (maybe <- 0x280001a) (Int)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i3
sub %i0, %i3, %i3
mov %l4, %o0
swap [%i3 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
add %l4, 1, %l4
P3766: !_LD [9] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
loop_exit_5_242:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_242
nop
P3767: !_LD [31] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_243:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3768: !_LD [17] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_5_243:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_243
nop
P3769: !_BLD [6] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_244:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 6
sethi %hi(0xc0000), %l6
sub %i1, %l6, %i1
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
sethi %hi(0xc0000), %l7
add %i1, %l7, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_5_244:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_244
nop
P3770: !_DWLD [21] (Int) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_245:
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_5_245:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_245
nop
P3771: !_DWLD [19] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_246:
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
ldx [%i2 + 32], %o0
! move %o0(upper) -> %o0(upper)
P3772: !_LD [0] (Int) (Loop exit) (LE)
wr %g0, 0x88, %asi
lduwa [%i0 + 0] %asi, %l7
! move %l7(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_5_246:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_246
nop
P3773: !_BLD [13] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_247:
wr %g0, 0xf0, %asi
sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_5_247:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_247
nop
P3774: !_MEMBAR (Int) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_248:
membar #StoreLoad
loop_exit_5_248:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_248
nop
P3775: !_DWLD [11] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_249:
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
ldx [%i2 + 32], %o0
! move %o0(upper) -> %o0(upper)
P3776: !_LD [0] (Int) (Loop exit)
lduw [%i0 + 0], %o5
! move %o5(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_5_249:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_249
nop
P3777: !_LD [23] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_250:
sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3778: !_LD [17] (Int) (Loop exit)
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 4], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_5_250:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_250
nop
P3779: !_BST [21] (maybe <- 0x4200001d) (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_251:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i3
sub %i0, %i3, %i3
! preparing store val #0, next val will be in f32
fmovs %f16, %f20
fadds %f16, %f17, %f16
! preparing store val #1, next val will be in f33
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #2, next val will be in f35
fmovd %f20, %f32
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #3, next val will be in f40
fmovd %f20, %f34
fmovs %f16, %f20
fadds %f16, %f17, %f16
fmovd %f20, %f40
membar #Sync
stda %f32, [%i3 + 0 ] %asi
membar #Sync
loop_exit_5_251:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_251
nop
P3780: !_LD [26] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_252:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3781: !_LD [17] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 4], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_5_252:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_252
nop
P3782: !_BLD [2] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_253:
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i0 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_5_253:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_253
nop
P3783: !_DWLD [6] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_254:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 6
sethi %hi(0xc0000), %o5
sub %i1, %o5, %i1
ldx [%i1 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3784: !_LD [20] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 0], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
sethi %hi(0xc0000), %l3
add %i1, %l3, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_5_254:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_254
nop
P3785: !_LD [25] (Int) (Loop entry) (Branch target of P3423)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_255:
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
ba P3786
nop
TARGET3423:
ba RET3423
nop
P3786: !_LD [27] (Int) (Loop exit)
lduw [%i3 + 32], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_5_255:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_255
nop
P3787: !_BLD [18] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_256:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_5_256:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_256
nop
P3788: !_BLD [26] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_257:
wr %g0, 0xf0, %asi
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P3789: !_DWLD [4] (Int) (Loop exit)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 4
sethi %hi(0xc0000), %l6
sub %i1, %l6, %i1
ldx [%i1 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
sethi %hi(0xc0000), %l3
add %i1, %l3, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_5_257:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_257
nop
P3790: !_LD [16] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_258:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3791: !_BLD [9] (FP)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P3792: !_LD [1] (Int) (Loop exit)
lduw [%i0 + 4], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_5_258:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_258
nop
P3793: !_BLD [28] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_259:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_5_259:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_259
nop
P3794: !_DWLD [0] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_260:
ldx [%i0 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
P3795: !_LD [31] (Int) (Branch target of P3708)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %o1
! move %o1(lower) -> %o1(upper)
sllx %o1, 32, %o1
ba P3796
nop
TARGET3708:
ba RET3708
nop
P3796: !_LD [8] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 0], %o5
! move %o5(lower) -> %o1(lower)
or %o5, %o1, %o1
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_5_260:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_260
nop
P3797: !_LD [4] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_261:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 4
sethi %hi(0xc0000), %l6
sub %i1, %l6, %i1
lduw [%i1 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3798: !_BLD [18] (FP)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P3799: !_LD [17] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
sethi %hi(0xc0000), %o5
add %i1, %o5, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_5_261:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_261
nop
P3800: !_LD [24] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_262:
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3801: !_LD [25] (Int) (Loop exit) (LE) (CBR)
wr %g0, 0x88, %asi
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduwa [%i2 + 4] %asi, %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET3801
nop
RET3801:
! lfsr step begin
srlx %l0, 1, %l6
xnor %l6, %l0, %l6
sllx %l6, 63, %l6
or %l6, %l0, %l0
srlx %l0, 1, %l0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_5_262:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_262
nop
P3802: !_BST [26] (maybe <- 0x42000021) (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_263:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
sub %i0, %i3, %i3
! preparing store val #0, next val will be in f32
fmovs %f16, %f20
fadds %f16, %f17, %f16
! preparing store val #1, next val will be in f33
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #2, next val will be in f35
fmovd %f20, %f32
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #3, next val will be in f40
fmovd %f20, %f34
fmovs %f16, %f20
fadds %f16, %f17, %f16
fmovd %f20, %f40
membar #Sync
stda %f32, [%i3 + 0 ] %asi
membar #Sync
P3803: !_DWLD [13] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_5_263:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_263
nop
P3804: !_DWLD [5] (Int) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_264:
ldx [%i1 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_5_264:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_264
nop
P3805: !_DWLD [5] (Int) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_265:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 5
sethi %hi(0xc0000), %l6
sub %i1, %l6, %i1
ldx [%i1 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
sethi %hi(0xc0000), %l3
add %i1, %l3, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_5_265:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_265
nop
P3806: !_LD [16] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_266:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3807: !_CAS [1] (maybe <- 0x280001b) (Int)
add %i0, 4, %l6
lduw [%l6], %o5
mov %o5, %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
mov %l4, %o1
cas [%l6], %l3, %o1
! move %o1(lower) -> %o1(upper)
sllx %o1, 32, %o1
add %l4, 1, %l4
P3808: !_LD [16] (Int) (Loop exit)
lduw [%i3 + 0], %l6
! move %l6(lower) -> %o1(lower)
or %l6, %o1, %o1
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_5_266:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_266
nop
P3809: !_BLD [2] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_267:
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i0 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_5_267:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_267
nop
P3810: !_LD [11] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_268:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3811: !_DWLD [31] (FP)
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
ldd [%i3 + 32], %f0
! 1 addresses covered
P3812: !_LD [29] (Int) (Loop exit) (LE) (Branch target of P3331)
wr %g0, 0x88, %asi
lduwa [%i3 + 4] %asi, %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
loop_exit_5_268:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_268
nop
ba P3813
nop
TARGET3331:
ba RET3331
nop
P3813: !_BLD [16] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_269:
wr %g0, 0xf0, %asi
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P3814: !_LD [17] (Int)
lduw [%i2 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3815: !_LD [16] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_5_269:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_269
nop
P3816: !_LD [19] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_270:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3817: !_LD [26] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_5_270:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_270
nop
P3818: !_BLD [17] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_271:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P3819: !_DWLD [11] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 32], %o0
! move %o0(upper) -> %o0(upper)
P3820: !_LD [23] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 32], %l3
! move %l3(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_5_271:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_271
nop
P3821: !_LD [14] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_272:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3822: !_LD [28] (Int) (Loop exit)
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 0], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_5_272:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_272
nop
P3823: !_BLD [15] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_273:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_5_273:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_273
nop
P3824: !_LD [0] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_274:
lduw [%i0 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3825: !_BLD [0] (FP) (CBR)
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i0 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET3825
nop
RET3825:
! lfsr step begin
srlx %l0, 1, %l6
xnor %l6, %l0, %l6
sllx %l6, 63, %l6
or %l6, %l0, %l0
srlx %l0, 1, %l0
P3826: !_LD [25] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_5_274:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_274
nop
P3827: !_LD [3] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_275:
lduw [%i0 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3828: !_LD [30] (Int) (Loop exit)
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 12], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_5_275:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_275
nop
P3829: !_BLD [9] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_276:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P3830: !_DWLD [18] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3831: !_LD [13] (Int) (Loop exit)
sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 4], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_5_276:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_276
nop
P3832: !_BLD [1] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_277:
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i0 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_5_277:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_277
nop
P3833: !_SWAP [22] (maybe <- 0x280001c) (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_278:
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
sub %i0, %i3, %i3
mov %l4, %o0
swap [%i3 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
add %l4, 1, %l4
P3834: !_LD [3] (Int) (Loop exit)
lduw [%i0 + 32], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_5_278:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_278
nop
P3835: !_LD [2] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_279:
lduw [%i0 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3836: !_LD [14] (Int) (Loop exit)
sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 12], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_5_279:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_279
nop
P3837: !_BLD [20] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_280:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P3838: !_BLD [28] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f32
membar #Sync
! 4 addresses covered
fmovd %f32, %f4
fmovd %f34, %f18
fmovs %f19, %f6
fmovd %f40, %f18
fmovs %f18, %f7
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovd %f4, %f30
fmovd %f6, %f30
!--
loop_exit_5_280:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_280
nop
P3839: !_REPLACEMENT [10] (Int) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_281:
sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS2_O), %i3
sub %i0, %i3, %i3
sethi %hi(0x10000), %o5
ld [%i3+12], %l6
st %l6, [%i3+12]
add %i3, %o5, %l3
ld [%l3+12], %l6
st %l6, [%l3+12]
add %l3, %o5, %l3
ld [%l3+12], %l6
st %l6, [%l3+12]
add %l3, %o5, %l3
ld [%l3+12], %l6
st %l6, [%l3+12]
loop_exit_5_281:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_281
nop
P3840: !_BLD [5] (FP) (Loop entry) (Loop exit) (CBR)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_282:
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET3840
nop
RET3840:
! lfsr step begin
srlx %l0, 1, %o5
xnor %o5, %l0, %o5
sllx %o5, 63, %o5
or %o5, %l0, %l0
srlx %l0, 1, %l0
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_5_282:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_282
nop
P3841: !_BLD [24] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_283:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_5_283:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_283
nop
P3842: !_ST [30] (maybe <- 0x280001d) (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_284:
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
stw %l4, [%i3 + 12 ]
add %l4, 1, %l4
P3843: !_DWLD [5] (Int) (Loop exit)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 5
sethi %hi(0xc0000), %l7
sub %i1, %l7, %i1
ldx [%i1 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
sethi %hi(0xc0000), %l6
add %i1, %l6, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_5_284:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_284
nop
P3844: !_LD [8] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_285:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3845: !_LD [28] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_5_285:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_285
nop
P3846: !_LD [27] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_286:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3847: !_LD [22] (Int) (Loop exit)
sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 12], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_5_286:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_286
nop
P3848: !_BLD [10] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_287:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P3849: !_DWLD [3] (Int)
ldx [%i0 + 32], %o0
! move %o0(upper) -> %o0(upper)
P3850: !_LD [15] (Int) (Loop exit) (CBR) (Branch target of P3532)
sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 32], %l7
! move %l7(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %l7, %o0, %o0
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET3850
nop
RET3850:
! lfsr step begin
srlx %l0, 1, %o5
xnor %o5, %l0, %o5
sllx %o5, 63, %o5
or %o5, %l0, %l0
srlx %l0, 1, %l0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_5_287:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_287
nop
ba P3851
nop
TARGET3532:
ba RET3532
nop
P3851: !_LD [22] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_288:
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3852: !_BLD [12] (FP)
wr %g0, 0xf0, %asi
sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P3853: !_LD [20] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 0], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_5_288:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_288
nop
P3854: !_CAS [15] (maybe <- 0x280001e) (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_289:
sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
add %i3, 32, %l6
lduw [%l6], %o0
mov %o0, %l3
! move %l3(lower) -> %o0(upper)
sllx %l3, 32, %o0
mov %l4, %o5
cas [%l6], %l3, %o5
! move %o5(lower) -> %o0(lower)
srl %o5, 0, %l3
or %l3, %o0, %o0
add %l4, 1, %l4
P3855: !_DWLD [12] (FP) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i2
sub %i0, %i2, %i2
ldd [%i2 + 0], %f0
! 2 addresses covered
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
!--
loop_exit_5_289:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_289
nop
P3856: !_SWAP [26] (maybe <- 0x280001f) (Int) (Loop entry) (Branch target of P3522)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_290:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i3
sub %i0, %i3, %i3
mov %l4, %o0
swap [%i3 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
add %l4, 1, %l4
ba P3857
nop
TARGET3522:
ba RET3522
nop
P3857: !_BSTC [20] (maybe <- 0x42000025) (FP)
wr %g0, 0xe0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i2
sub %i0, %i2, %i2
! preparing store val #0, next val will be in f32
fmovs %f16, %f20
fadds %f16, %f17, %f16
! preparing store val #1, next val will be in f33
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #2, next val will be in f35
fmovd %f20, %f32
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #3, next val will be in f40
fmovd %f20, %f34
fmovs %f16, %f20
fadds %f16, %f17, %f16
fmovd %f20, %f40
membar #Sync
stda %f32, [%i2 + 0 ] %asi
membar #Sync
P3858: !_LD [15] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_5_290:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_290
nop
P3859: !_DWLD [24] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_291:
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
ldx [%i2 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
P3860: !_DWLD [19] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 32], %o1
! move %o1(upper) -> %o1(upper)
P3861: !_LD [25] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %o5
! move %o5(lower) -> %o1(lower)
srlx %o1, 32, %o1
sllx %o1, 32, %o1
or %o5, %o1, %o1
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_5_291:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_291
nop
P3862: !_BLD [18] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_292:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_5_292:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_292
nop
P3863: !_NOP (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_293:
nop
P3864: !_LD [18] (Int) (Branch target of P3976)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
ba P3865
nop
TARGET3976:
ba RET3976
nop
P3865: !_LD [5] (Int) (Loop exit)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 5
sethi %hi(0xc0000), %l6
sub %i1, %l6, %i1
lduw [%i1 + 4], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
sethi %hi(0xc0000), %l3
add %i1, %l3, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_5_293:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_293
nop
P3866: !_BLD [5] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_294:
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P3867: !_LD [1] (Int)
lduw [%i0 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3868: !_LD [29] (Int) (Loop exit) (LE)
wr %g0, 0x88, %asi
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduwa [%i3 + 4] %asi, %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_5_294:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_294
nop
P3869: !_SWAP [1] (maybe <- 0x2800020) (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_295:
mov %l4, %o0
swap [%i0 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
add %l4, 1, %l4
P3870: !_BLD [15] (FP)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P3871: !_LD [1] (Int) (Loop exit)
lduw [%i0 + 4], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_5_295:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_295
nop
P3872: !_LD [16] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_296:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3873: !_LD [12] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 0], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_5_296:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_296
nop
P3874: !_BLD [7] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_297:
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_5_297:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_297
nop
P3875: !_LD [27] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_298:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3876: !_LD [10] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_5_298:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_298
nop
P3877: !_DWLD [21] (Int) (Loop entry) (CBR)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_299:
sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
ldx [%i3 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET3877
nop
RET3877:
! lfsr step begin
srlx %l0, 1, %o5
xnor %o5, %l0, %o5
sllx %o5, 63, %o5
or %o5, %l0, %l0
srlx %l0, 1, %l0
P3878: !_DWLD [3] (Int)
ldx [%i0 + 32], %o1
! move %o1(upper) -> %o1(upper)
P3879: !_LD [31] (Int) (Loop exit) (CBR)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 32], %l3
! move %l3(lower) -> %o1(lower)
srlx %o1, 32, %o1
sllx %o1, 32, %o1
or %l3, %o1, %o1
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET3879
nop
RET3879:
! lfsr step begin
srlx %l0, 1, %l6
xnor %l6, %l0, %l6
sllx %l6, 63, %l6
or %l6, %l0, %l0
srlx %l0, 1, %l0
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_5_299:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_299
nop
P3880: !_BST [26] (maybe <- 0x42000029) (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_300:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i3
sub %i0, %i3, %i3
! preparing store val #0, next val will be in f32
fmovs %f16, %f20
fadds %f16, %f17, %f16
! preparing store val #1, next val will be in f33
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #2, next val will be in f35
fmovd %f20, %f32
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #3, next val will be in f40
fmovd %f20, %f34
fmovs %f16, %f20
fadds %f16, %f17, %f16
fmovd %f20, %f40
membar #Sync
stda %f32, [%i3 + 0 ] %asi
membar #Sync
P3881: !_BLD [4] (FP) (Loop exit)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 4
sethi %hi(0xc0000), %l7
sub %i1, %l7, %i1
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
sethi %hi(0xc0000), %o5
add %i1, %o5, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_5_300:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_300
nop
P3882: !_DWLD [12] (Int) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_301:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_5_301:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_301
nop
P3883: !_CAS [24] (maybe <- 0x2800021) (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_302:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3], %o0
mov %o0, %l3
! move %l3(lower) -> %o0(upper)
sllx %l3, 32, %o0
mov %l4, %o5
cas [%i3], %l3, %o5
! move %o5(lower) -> %o0(lower)
srl %o5, 0, %l3
or %l3, %o0, %o0
add %l4, 1, %l4
P3884: !_BLD [28] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_5_302:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_302
nop
P3885: !_BLD [24] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_303:
wr %g0, 0xf0, %asi
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_5_303:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_303
nop
P3886: !_DWLD [23] (Int) (Loop entry) (Branch target of P3763)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_304:
sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
ldx [%i2 + 32], %o0
! move %o0(upper) -> %o0(upper)
ba P3887
nop
TARGET3763:
ba RET3763
nop
P3887: !_DWLD [7] (Int) (Loop exit)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 7
sethi %hi(0xc0000), %l6
sub %i1, %l6, %i1
ldx [%i1 + 32], %o5
! move %o5(upper) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
srlx %o5, 32, %l7
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
sethi %hi(0xc0000), %l3
add %i1, %l3, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_5_304:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_304
nop
P3888: !_LD [2] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_305:
lduw [%i0 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3889: !_LD [9] (FP)
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
ld [%i3 + 4], %f0
! 1 addresses covered
P3890: !_LD [9] (Int) (Loop exit)
lduw [%i3 + 4], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
loop_exit_5_305:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_305
nop
P3891: !_DWLD [12] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_306:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
P3892: !_LD [2] (Int) (Branch target of P3530)
lduw [%i0 + 12], %o1
! move %o1(lower) -> %o1(upper)
sllx %o1, 32, %o1
ba P3893
nop
TARGET3530:
ba RET3530
nop
P3893: !_LD [17] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 4], %l7
! move %l7(lower) -> %o1(lower)
or %l7, %o1, %o1
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_5_306:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_306
nop
P3894: !_LD [18] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_307:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3895: !_REPLACEMENT [14] (Int)
sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS3_O), %i3
sub %i0, %i3, %i3
sethi %hi(0x10000), %o5
ld [%i3+12], %l6
st %l6, [%i3+12]
add %i3, %o5, %l3
ld [%l3+12], %l6
st %l6, [%l3+12]
add %l3, %o5, %l3
ld [%l3+12], %l6
st %l6, [%l3+12]
add %l3, %o5, %l3
ld [%l3+12], %l6
st %l6, [%l3+12]
P3896: !_LD [28] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 0], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_5_307:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_307
nop
P3897: !_BLD [10] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_308:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_5_308:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_308
nop
P3898: !_MEMBAR (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_309:
membar #StoreLoad
P3899: !_DWLD [28] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_5_309:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_309
nop
P3900: !_LD [8] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_310:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3901: !_LD [16] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 0], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_5_310:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_310
nop
P3902: !_DWLD [30] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_311:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3903: !_LD [18] (Int) (Loop exit)
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 12], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_5_311:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_311
nop
P3904: !_BLD [4] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_312:
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P3905: !_BLD [27] (FP) (Loop exit) (CBR)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f32
membar #Sync
! 4 addresses covered
fmovd %f32, %f4
fmovd %f34, %f18
fmovs %f19, %f6
fmovd %f40, %f18
fmovs %f18, %f7
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET3905
nop
RET3905:
! lfsr step begin
srlx %l0, 1, %l3
xnor %l3, %l0, %l3
sllx %l3, 63, %l3
or %l3, %l0, %l0
srlx %l0, 1, %l0
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovd %f4, %f30
fmovd %f6, %f30
!--
loop_exit_5_312:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_312
nop
P3906: !_MEMBAR (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_313:
membar #StoreLoad
P3907: !_BST [16] (maybe <- 0x4200002d) (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
sub %i0, %i2, %i2
! preparing store val #0, next val will be in f32
fmovs %f16, %f20
fadds %f16, %f17, %f16
! preparing store val #1, next val will be in f33
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #2, next val will be in f35
fmovd %f20, %f32
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #3, next val will be in f40
fmovd %f20, %f34
fmovs %f16, %f20
fadds %f16, %f17, %f16
fmovd %f20, %f40
membar #Sync
stda %f32, [%i2 + 0 ] %asi
membar #Sync
loop_exit_5_313:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_313
nop
P3908: !_REPLACEMENT [31] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_314:
sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS2_O), %i3
sub %i0, %i3, %i3
sethi %hi(0x10000), %o5
ld [%i3+32], %l6
st %l6, [%i3+32]
add %i3, %o5, %l3
ld [%l3+32], %l6
st %l6, [%l3+32]
add %l3, %o5, %l3
ld [%l3+32], %l6
st %l6, [%l3+32]
add %l3, %o5, %l3
ld [%l3+32], %l6
st %l6, [%l3+32]
P3909: !_BLD [16] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_5_314:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_314
nop
P3910: !_BLD [27] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_315:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P3911: !_CAS [11] (maybe <- 0x2800022) (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
sub %i0, %i2, %i2
add %i2, 32, %l7
lduw [%l7], %o0
mov %o0, %l6
! move %l6(lower) -> %o0(upper)
sllx %l6, 32, %o0
mov %l4, %l3
cas [%l7], %l6, %l3
! move %l3(lower) -> %o0(lower)
srl %l3, 0, %l6
or %l6, %o0, %o0
add %l4, 1, %l4
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_5_315:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_315
nop
P3912: !_LD [25] (Int) (Loop entry) (CBR)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_316:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET3912
nop
RET3912:
! lfsr step begin
srlx %l0, 1, %l3
xnor %l3, %l0, %l3
sllx %l3, 63, %l3
or %l3, %l0, %l0
srlx %l0, 1, %l0
P3913: !_LD [2] (Int) (Loop exit) (LE)
wr %g0, 0x88, %asi
lduwa [%i0 + 12] %asi, %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_5_316:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_316
nop
P3914: !_LD [26] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_317:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
sub %i0, %i2, %i2
ld [%i2 + 12], %f0
! 1 addresses covered
P3915: !_BLD [18] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f32
membar #Sync
! 4 addresses covered
fmovd %f32, %f18
fmovs %f18, %f1
fmovs %f19, %f2
fmovd %f34, %f18
fmovs %f19, %f3
fmovd %f40, %f4
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovs %f4, %f30
!--
loop_exit_5_317:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_317
nop
P3916: !_LD [11] (Int) (Loop entry) (CBR)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_318:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET3916
nop
RET3916:
! lfsr step begin
srlx %l0, 1, %l6
xnor %l6, %l0, %l6
sllx %l6, 63, %l6
or %l6, %l0, %l0
srlx %l0, 1, %l0
P3917: !_LD [3] (Int) (Loop exit)
lduw [%i0 + 32], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_5_318:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_318
nop
P3918: !_REPLACEMENT [23] (Int) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_319:
sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS2_O), %i3
sub %i0, %i3, %i3
sethi %hi(0x10000), %l7
ld [%i3+32], %l3
st %l3, [%i3+32]
add %i3, %l7, %o5
ld [%o5+32], %l3
st %l3, [%o5+32]
add %o5, %l7, %o5
ld [%o5+32], %l3
st %l3, [%o5+32]
add %o5, %l7, %o5
ld [%o5+32], %l3
st %l3, [%o5+32]
loop_exit_5_319:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_319
nop
P3919: !_LD [20] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_320:
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3920: !_LD [31] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_5_320:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_320
nop
P3921: !_DWLD [31] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_321:
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
ldx [%i2 + 32], %o0
! move %o0(upper) -> %o0(upper)
P3922: !_LD [18] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %l3
! move %l3(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_5_321:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_321
nop
P3923: !_BLD [6] (FP) (Loop entry) (Loop exit) (Branch target of P3825)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_322:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 6
sethi %hi(0xc0000), %l7
sub %i1, %l7, %i1
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
sethi %hi(0xc0000), %o5
add %i1, %o5, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_5_322:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_322
nop
ba P3924
nop
TARGET3825:
ba RET3825
nop
P3924: !_BLD [14] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_323:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P3925: !_DWLD [13] (Int) (Loop exit) (CBR)
sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
ldx [%i3 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET3925
nop
RET3925:
! lfsr step begin
srlx %l0, 1, %o5
xnor %o5, %l0, %o5
sllx %o5, 63, %o5
or %o5, %l0, %l0
srlx %l0, 1, %l0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_5_323:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_323
nop
P3926: !_LD [13] (Int) (Loop entry) (Branch target of P3743)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_324:
sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
ba P3927
nop
TARGET3743:
ba RET3743
nop
P3927: !_LD [15] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_5_324:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_324
nop
P3928: !_DWLD [28] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_325:
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
ldd [%i2 + 0], %f0
! 2 addresses covered
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
!--
loop_exit_5_325:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_325
nop
P3929: !_DWLD [9] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_326:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
P3930: !_DWLD [2] (Int)
ldx [%i0 + 8], %o1
! move %o1(lower) -> %o1(upper)
sllx %o1, 32, %o1
P3931: !_LD [6] (Int) (Loop exit) (Branch target of P3672)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 6
sethi %hi(0xc0000), %l6
sub %i1, %l6, %i1
lduw [%i1 + 12], %o5
! move %o5(lower) -> %o1(lower)
or %o5, %o1, %o1
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
sethi %hi(0xc0000), %l3
add %i1, %l3, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_5_326:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_326
nop
ba P3932
nop
TARGET3672:
ba RET3672
nop
P3932: !_BLD [5] (FP) (Loop entry) (Branch target of P3850)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_327:
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
ba P3933
nop
TARGET3850:
ba RET3850
nop
P3933: !_CASX [19] (maybe <- 0x2800023) (Int) (Loop exit)
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
add %i2, 32, %o5
ldx [%o5], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
mov %o0, %l7
sllx %l4, 32, %o1
casx [%o5], %l7, %o1
! move %o1(upper) -> %o1(upper)
! move %o1(lower) -> %o1(lower)
add %l4, 1, %l4
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_5_327:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_327
nop
P3934: !_BLD [7] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_328:
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_5_328:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_328
nop
P3935: !_LD [15] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_329:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3936: !_DWLD [29] (FP)
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
ldd [%i2 + 0], %f0
! 2 addresses covered
P3937: !_LD [27] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
!--
loop_exit_5_329:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_329
nop
P3938: !_SWAP [27] (maybe <- 0x2800024) (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_330:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i2
sub %i0, %i2, %i2
mov %l4, %o0
swap [%i2 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
add %l4, 1, %l4
P3939: !_BLD [2] (FP)
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i0 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P3940: !_LD [23] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_5_330:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_330
nop
P3941: !_BLD [2] (FP) (Loop entry) (Loop exit) (Branch target of P3656)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_331:
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i0 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_5_331:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_331
nop
ba P3942
nop
TARGET3656:
ba RET3656
nop
P3942: !_DWLD [3] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_332:
ldd [%i0 + 32], %f0
! 1 addresses covered
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
loop_exit_5_332:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_332
nop
P3943: !_LD [2] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_333:
lduw [%i0 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3944: !_DWLD [13] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 0], %l6
! move %l6(upper) -> %o0(lower)
srlx %l6, 32, %l3
or %l3, %o0, %o0
! move %l6(lower) -> %o1(upper)
sllx %l6, 32, %o1
P3945: !_LD [2] (Int) (Loop exit)
lduw [%i0 + 12], %l3
! move %l3(lower) -> %o1(lower)
or %l3, %o1, %o1
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_5_333:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_333
nop
P3946: !_LD [9] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_334:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3947: !_BLD [14] (FP)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P3948: !_LD [17] (Int) (Loop exit)
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 4], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_5_334:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_334
nop
P3949: !_PREFETCH [12] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_335:
sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
prefetch [%i2 + 0], 1
P3950: !_DWLD [15] (Int) (Branch target of P3590)
ldx [%i2 + 32], %o0
! move %o0(upper) -> %o0(upper)
ba P3951
nop
TARGET3590:
ba RET3590
nop
P3951: !_LD [28] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %l6
! move %l6(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_5_335:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_335
nop
P3952: !_DWLD [12] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_336:
sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
ldd [%i2 + 0], %f0
! 2 addresses covered
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
!--
loop_exit_5_336:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_336
nop
P3953: !_DWLD [6] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_337:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 6
sethi %hi(0xc0000), %l3
sub %i1, %l3, %i1
ldx [%i1 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3954: !_LD [30] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
sethi %hi(0xc0000), %l6
add %i1, %l6, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_5_337:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_337
nop
P3955: !_DWLD [15] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_338:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 32], %o0
! move %o0(upper) -> %o0(upper)
P3956: !_LD [16] (Int) (Loop exit)
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 0], %l7
! move %l7(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_5_338:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_338
nop
P3957: !_BLD [21] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_339:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P3958: !_LD [23] (Int) (LE) (Branch target of P3608)
wr %g0, 0x88, %asi
lduwa [%i2 + 32] %asi, %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
ba P3959
nop
TARGET3608:
ba RET3608
nop
P3959: !_LD [23] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_5_339:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_339
nop
P3960: !_BLD [28] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_340:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_5_340:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_340
nop
P3961: !_MEMBAR (Int) (Loop entry) (Branch target of P3640)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_341:
membar #StoreLoad
ba P3962
nop
TARGET3640:
ba RET3640
nop
P3962: !_DWLD [7] (Int)
ldx [%i1 + 32], %o0
! move %o0(upper) -> %o0(upper)
P3963: !_LD [0] (Int) (Loop exit)
lduw [%i0 + 0], %l6
! move %l6(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_5_341:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_341
nop
P3964: !_LD [21] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_342:
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i3
sub %i0, %i3, %i3
ld [%i3 + 4], %f0
! 1 addresses covered
P3965: !_LD [25] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3966: !_LD [0] (Int) (Loop exit)
lduw [%i0 + 0], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
loop_exit_5_342:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_342
nop
P3967: !_BLD [24] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_343:
wr %g0, 0xf0, %asi
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_5_343:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_343
nop
P3968: !_DWST [0] (maybe <- 0x42000031) (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_344:
! preparing store val #0, next val will be in f20
fmovs %f16, %f20
fadds %f16, %f17, %f16
! preparing store val #1, next val will be in f21
fmovs %f16, %f21
fadds %f16, %f17, %f16
std %f20, [%i0 + 0]
loop_exit_5_344:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_344
nop
P3969: !_BLD [2] (FP) (Loop entry) (Loop exit) (CBR)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_345:
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i0 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET3969
nop
RET3969:
! lfsr step begin
srlx %l0, 1, %l3
xnor %l3, %l0, %l3
sllx %l3, 63, %l3
or %l3, %l0, %l0
srlx %l0, 1, %l0
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_5_345:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_345
nop
P3970: !_NOP (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_5_346:
nop
P3971: !_BLD [10] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_5_346:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_346
nop
P3972: !_DWLD [9] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_347:
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
ldx [%i3 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
P3973: !_LD [18] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %o1
! move %o1(lower) -> %o1(upper)
sllx %o1, 32, %o1
P3974: !_LD [23] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %l7
! move %l7(lower) -> %o1(lower)
or %l7, %o1, %o1
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_5_347:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_347
nop
P3975: !_BLD [27] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_348:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P3976: !_LD [22] (Int) (LE) (CBR)
wr %g0, 0x88, %asi
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduwa [%i3 + 12] %asi, %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET3976
nop
RET3976:
! lfsr step begin
srlx %l0, 1, %o5
xnor %o5, %l0, %o5
sllx %o5, 63, %o5
or %o5, %l0, %l0
srlx %l0, 1, %l0
P3977: !_LD [28] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 0], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_5_348:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_348
nop
P3978: !_BLD [15] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_349:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P3979: !_LD [16] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3980: !_LD [31] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_5_349:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_349
nop
P3981: !_LD [27] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_5_350:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3982: !_LD [1] (Int) (Loop exit)
lduw [%i0 + 4], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_5_350:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_5_350
nop
P3983: !_MEMBAR (Int)
membar #StoreLoad
END_NODES5: ! Test instruction sequence for CPU 5 ends
sethi %hi(0xdead0e0f), %l6
or %l6, %lo(0xdead0e0f), %l6
! move %l6(lower) -> %o0(upper)
sllx %l6, 32, %o0
stw %l6, [%i5]
ld [%i5], %f0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
restore
retl
nop
!-----------------
! register usage:
! %i0 %i1 : base registers for first 2 regions
! %i2 %i3 : cache registers for 8 regions
! %i4 fixed pointer to per-cpu results area
! %l1 moving pointer to per-cpu FP results area
! %o7 moving pointer to per-cpu integer results area
! %i5 pointer to per-cpu private area
! %l0 holds lfsr, used as source of random bits
! %l2 loop count register
! %f16 running counter for unique fp store values
! %f17 holds increment value for fp counter
! %l4 running counter for unique integer store values (increment value is always 1)
! %l5 move-to register for load values (simulation only)
! %f30 move-to register for FP values (simulation only)
! %l3 %l6 %l7 %o5 : 4 temporary registers
! %o0 %o1 %o2 %o3 %o4 : 5 integer results buffer registers
! %f0-f15 FP results buffer registers
! %f32-f47 FP block load/store registers
func6:
! 1000 (dynamic) instruction sequence begins
save %sp, -192, %sp
! Force %i0-%i3 to be 64-byte aligned
add %i0, 63, %i0
andn %i0, 63, %i0
add %i1, 63, %i1
andn %i1, 63, %i1
add %i2, 63, %i2
andn %i2, 63, %i2
add %i3, 63, %i3
andn %i3, 63, %i3
add %i4, 63, %i4
andn %i4, 63, %i4
add %i5, 63, %i5
andn %i5, 63, %i5
! Initialize pointer to FP load results area
mov %i4, %l1
! Initialize pointer to integer load results area
sethi %hi(0x80000), %o7
or %o7, %lo(0x80000), %o7
add %o7, %l1, %o7
! Initialize %f0-%f62 to 0xdeadbee0deadbee1
sethi %hi(0xdeadbee0), %l3
or %l3, %lo(0xdeadbee0), %l3
stw %l3, [%i5]
sethi %hi(0xdeadbee1), %l3
or %l3, %lo(0xdeadbee1), %l3
stw %l3, [%i5+4]
ldd [%i5], %f0
fmovd %f0, %f2
fmovd %f0, %f4
fmovd %f0, %f6
fmovd %f0, %f8
fmovd %f0, %f10
fmovd %f0, %f12
fmovd %f0, %f14
fmovd %f0, %f16
fmovd %f0, %f18
fmovd %f0, %f20
fmovd %f0, %f22
fmovd %f0, %f24
fmovd %f0, %f26
fmovd %f0, %f28
fmovd %f0, %f30
fmovd %f0, %f32
fmovd %f0, %f34
fmovd %f0, %f36
fmovd %f0, %f38
fmovd %f0, %f40
fmovd %f0, %f42
fmovd %f0, %f44
fmovd %f0, %f46
fmovd %f0, %f48
fmovd %f0, %f50
fmovd %f0, %f52
fmovd %f0, %f54
fmovd %f0, %f56
fmovd %f0, %f58
fmovd %f0, %f60
fmovd %f0, %f62
! Signature for extract_loads script to start extracting load values for this stream
sethi %hi(0x06deade1), %l3
or %l3, %lo(0x06deade1), %l3
stw %l3, [%i5]
ld [%i5], %f16
! Initialize running integer counter in register %l4
sethi %hi(0x3000001), %l4
or %l4, %lo(0x3000001), %l4
! Initialize running FP counter in register %f16
sethi %hi(0x42800001), %l3
or %l3, %lo(0x42800001), %l3
stw %l3, [%i5]
ld [%i5], %f16
! Initialize FP counter increment value in register %f17 (constant)
sethi %hi(0x37000000), %l3
or %l3, %lo(0x37000000), %l3
stw %l3, [%i5]
ld [%i5], %f17
! Initialize LFSR to 0x164b^4
sethi %hi(0x164b), %l0
or %l0, %lo(0x164b), %l0
mulx %l0, %l0, %l0
mulx %l0, %l0, %l0
BEGIN_NODES6: ! Test instruction sequence for CPU 6 begins
P3984: !_CAS [1] (maybe <- 0x3000001) (Int) (Loop entry) (Loop exit) (CBR)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_0:
add %i0, 4, %o5
lduw [%o5], %o0
mov %o0, %l7
! move %l7(lower) -> %o0(upper)
sllx %l7, 32, %o0
mov %l4, %l6
cas [%o5], %l7, %l6
! move %l6(lower) -> %o0(lower)
srl %l6, 0, %l7
or %l7, %o0, %o0
add %l4, 1, %l4
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET3984
nop
RET3984:
! lfsr step begin
srlx %l0, 1, %l7
xnor %l7, %l0, %l7
sllx %l7, 63, %l7
or %l7, %l0, %l0
srlx %l0, 1, %l0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_6_0:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_0
nop
P3985: !_ST [0] (maybe <- 0x3000002) (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_1:
stw %l4, [%i0 + 0 ]
add %l4, 1, %l4
P3986: !_BLD [19] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_6_1:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_1
nop
P3987: !_BLD [2] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_2:
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i0 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_6_2:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_2
nop
P3988: !_CAS [29] (maybe <- 0x3000003) (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_3:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i2
sub %i0, %i2, %i2
add %i2, 4, %l3
lduw [%l3], %o0
mov %o0, %o5
! move %o5(lower) -> %o0(upper)
sllx %o5, 32, %o0
mov %l4, %l7
cas [%l3], %o5, %l7
! move %l7(lower) -> %o0(lower)
srl %l7, 0, %o5
or %o5, %o0, %o0
add %l4, 1, %l4
P3989: !_LD [27] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %o1
! move %o1(lower) -> %o1(upper)
sllx %o1, 32, %o1
P3990: !_LD [0] (Int) (Loop exit)
lduw [%i0 + 0], %o5
! move %o5(lower) -> %o1(lower)
or %o5, %o1, %o1
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_6_3:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_3
nop
P3991: !_CAS [12] (maybe <- 0x3000004) (Int) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_4:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2], %o0
mov %o0, %l7
! move %l7(lower) -> %o0(upper)
sllx %l7, 32, %o0
mov %l4, %l6
cas [%i2], %l7, %l6
! move %l6(lower) -> %o0(lower)
srl %l6, 0, %l7
or %l7, %o0, %o0
add %l4, 1, %l4
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_6_4:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_4
nop
P3992: !_BLD [21] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_5:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P3993: !_DWLD [21] (Int) (Loop exit)
sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
ldx [%i2 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_6_5:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_5
nop
P3994: !_LD [15] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_6:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P3995: !_LD [12] (Int) (Loop exit) (CBR)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 0], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET3995
nop
RET3995:
! lfsr step begin
srlx %l0, 1, %l3
xnor %l3, %l0, %l3
sllx %l3, 63, %l3
or %l3, %l0, %l0
srlx %l0, 1, %l0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_6_6:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_6
nop
P3996: !_BLD [27] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_7:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_6_7:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_7
nop
P3997: !_BST [8] (maybe <- 0x42800001) (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_8:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i2
sub %i0, %i2, %i2
! preparing store val #0, next val will be in f32
fmovs %f16, %f20
fadds %f16, %f17, %f16
! preparing store val #1, next val will be in f33
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #2, next val will be in f35
fmovd %f20, %f32
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #3, next val will be in f40
fmovd %f20, %f34
fmovs %f16, %f20
fadds %f16, %f17, %f16
fmovd %f20, %f40
membar #Sync
stda %f32, [%i2 + 0 ] %asi
membar #Sync
loop_exit_6_8:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_8
nop
P3998: !_DWLD [28] (Int) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_9:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_6_9:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_9
nop
P3999: !_BLD [31] (FP) (Loop entry) (Loop exit) (CBR)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_10:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET3999
nop
RET3999:
! lfsr step begin
srlx %l0, 1, %l3
xnor %l3, %l0, %l3
sllx %l3, 63, %l3
or %l3, %l0, %l0
srlx %l0, 1, %l0
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_6_10:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_10
nop
P4000: !_SWAP [23] (maybe <- 0x3000005) (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_11:
sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
mov %l4, %o0
swap [%i3 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
add %l4, 1, %l4
P4001: !_LD [14] (Int) (Loop exit)
sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 12], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_6_11:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_11
nop
P4002: !_LD [2] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_12:
lduw [%i0 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4003: !_BLD [31] (FP)
wr %g0, 0xf0, %asi
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P4004: !_LD [21] (Int) (Loop exit)
sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 4], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_6_12:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_12
nop
P4005: !_DWLD [10] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_13:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4006: !_LD [8] (Int) (Loop exit)
lduw [%i3 + 0], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_6_13:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_13
nop
P4007: !_LD [23] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_14:
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4008: !_SWAP [5] (maybe <- 0x3000006) (Int) (Loop exit) (LE)
wr %g0, 0x88, %asi
mov %l4, %l7
! Change single-word-level endianess (big endian <-> little endian)
sethi %hi(0xff00ff00), %l3
or %l3, %lo(0xff00ff00), %l3
and %l7, %l3, %l6
srl %l6, 8, %l6
sll %l7, 8, %l7
and %l7, %l3, %l7
or %l7, %l6, %l7
srl %l7, 16, %l6
sll %l7, 16, %l7
srl %l7, 0, %l7
or %l7, %l6, %l7
swapa [%i1 + 4] %asi, %l7
! move %l7(lower) -> %o0(lower)
srl %l7, 0, %l3
or %l3, %o0, %o0
add %l4, 1, %l4
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_6_14:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_14
nop
P4009: !_DWST [14] (maybe <- 0x3000007) (Int) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_15:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i3
sub %i0, %i3, %i3
mov %l4, %l6
stx %l6, [%i3 + 8]
add %l4, 1, %l4
loop_exit_6_15:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_15
nop
P4010: !_BLD [28] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_16:
wr %g0, 0xf0, %asi
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_6_16:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_16
nop
P4011: !_LD [8] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_17:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4012: !_LD [13] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_6_17:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_17
nop
P4013: !_LD [28] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_18:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4014: !_LD [7] (Int) (Loop exit)
lduw [%i1 + 32], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_6_18:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_18
nop
P4015: !_LD [7] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_19:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 7
sethi %hi(0xc0000), %l7
sub %i1, %l7, %i1
ld [%i1 + 32], %f0
! 1 addresses covered
P4016: !_LD [31] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4017: !_LD [0] (Int) (Loop exit)
lduw [%i0 + 0], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
sethi %hi(0xc0000), %l3
add %i1, %l3, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_6_19:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_19
nop
P4018: !_FLUSHI [14] (Int) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_20:
flush %g0
loop_exit_6_20:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_20
nop
P4019: !_BLD [8] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_21:
wr %g0, 0xf0, %asi
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P4020: !_DWST [8] (maybe <- 0x3000008) (Int) (Loop exit)
sllx %l4, 32, %o5
add %l4, 1, %l4
or %o5, %l4, %o5
stx %o5, [%i3 + 0]
add %l4, 1, %l4
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_6_21:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_21
nop
P4021: !_LD [17] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_22:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4022: !_DWLD [6] (FP)
ldd [%i1 + 8], %f0
! 1 addresses covered
fmovs %f1, %f0
P4023: !_LD [3] (Int) (Loop exit)
lduw [%i0 + 32], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
loop_exit_6_22:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_22
nop
P4024: !_BLD [12] (FP) (Loop entry) (Loop exit) (Branch target of P4038)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_23:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_6_23:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_23
nop
ba P4025
nop
TARGET4038:
ba RET4038
nop
P4025: !_DWLD [2] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_24:
ldx [%i0 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4026: !_LD [11] (Int) (Loop exit)
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 32], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_6_24:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_24
nop
P4027: !_DWLD [17] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_25:
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
ldx [%i3 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
P4028: !_BST [16] (maybe <- 0x42800005) (FP) (Loop exit) (Branch target of P4276)
wr %g0, 0xf0, %asi
! preparing store val #0, next val will be in f32
fmovs %f16, %f20
fadds %f16, %f17, %f16
! preparing store val #1, next val will be in f33
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #2, next val will be in f35
fmovd %f20, %f32
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #3, next val will be in f40
fmovd %f20, %f34
fmovs %f16, %f20
fadds %f16, %f17, %f16
fmovd %f20, %f40
membar #Sync
stda %f32, [%i3 + 0 ] %asi
membar #Sync
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_6_25:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_25
nop
ba P4029
nop
TARGET4276:
ba RET4276
nop
P4029: !_DWLD [2] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_26:
ldx [%i0 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4030: !_LD [9] (Int) (Loop exit)
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 4], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_6_26:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_26
nop
P4031: !_BLD [10] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_27:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_6_27:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_27
nop
P4032: !_DWLD [15] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_28:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 32], %o0
! move %o0(upper) -> %o0(upper)
P4033: !_LD [23] (Int) (Loop exit) (CBR)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %l3
! move %l3(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %l3, %o0, %o0
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET4033
nop
RET4033:
! lfsr step begin
srlx %l0, 1, %l6
xnor %l6, %l0, %l6
sllx %l6, 63, %l6
or %l6, %l0, %l0
srlx %l0, 1, %l0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_6_28:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_28
nop
P4034: !_BLD [21] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_29:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P4035: !_ST [29] (maybe <- 0x42800009) (FP) (Loop exit) (Branch target of P4385)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i3
sub %i0, %i3, %i3
! preparing store val #0, next val will be in f20
fmovs %f16, %f20
fadds %f16, %f17, %f16
st %f20, [%i3 + 4 ]
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_6_29:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_29
nop
ba P4036
nop
TARGET4385:
ba RET4385
nop
P4036: !_BLD [30] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_30:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_6_30:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_30
nop
P4037: !_DWLD [21] (Int) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_31:
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_6_31:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_31
nop
P4038: !_BLD [5] (FP) (Loop entry) (CBR)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_32:
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET4038
nop
RET4038:
! lfsr step begin
srlx %l0, 1, %l6
xnor %l6, %l0, %l6
sllx %l6, 63, %l6
or %l6, %l0, %l0
srlx %l0, 1, %l0
P4039: !_BLD [20] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f32
membar #Sync
! 4 addresses covered
fmovd %f32, %f4
fmovd %f34, %f18
fmovs %f19, %f6
fmovd %f40, %f18
fmovs %f18, %f7
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovd %f4, %f30
fmovd %f6, %f30
!--
loop_exit_6_32:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_32
nop
P4040: !_DWST [1] (maybe <- 0x300000a) (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_33:
sllx %l4, 32, %l3
add %l4, 1, %l4
or %l3, %l4, %l3
stx %l3, [%i0 + 0]
add %l4, 1, %l4
P4041: !_CAS [13] (maybe <- 0x300000c) (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i3
sub %i0, %i3, %i3
add %i3, 4, %l6
lduw [%l6], %o0
mov %o0, %l3
! move %l3(lower) -> %o0(upper)
sllx %l3, 32, %o0
mov %l4, %o5
cas [%l6], %l3, %o5
! move %o5(lower) -> %o0(lower)
srl %o5, 0, %l3
or %l3, %o0, %o0
add %l4, 1, %l4
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_6_33:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_33
nop
P4042: !_DWLD [13] (Int) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_34:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_6_34:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_34
nop
P4043: !_BLD [27] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_35:
wr %g0, 0xf0, %asi
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P4044: !_DWLD [18] (Int)
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
ldx [%i2 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4045: !_LD [28] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_6_35:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_35
nop
P4046: !_BLD [19] (FP) (Loop entry) (CBR)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_36:
wr %g0, 0xf0, %asi
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET4046
nop
RET4046:
! lfsr step begin
srlx %l0, 1, %o5
xnor %o5, %l0, %o5
sllx %o5, 63, %o5
or %o5, %l0, %l0
srlx %l0, 1, %l0
P4047: !_LD [8] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4048: !_LD [7] (Int) (Loop exit)
lduw [%i1 + 32], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_6_36:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_36
nop
P4049: !_LD [26] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_37:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4050: !_LD [15] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_6_37:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_37
nop
P4051: !_DWLD [19] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_38:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 32], %o0
! move %o0(upper) -> %o0(upper)
P4052: !_LD [31] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %l3
! move %l3(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_6_38:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_38
nop
P4053: !_LD [9] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_39:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4054: !_LD [18] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_6_39:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_39
nop
P4055: !_BLD [15] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_40:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_6_40:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_40
nop
P4056: !_FLUSHI [0] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_41:
flush %g0
P4057: !_LD [5] (Int)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 5
sethi %hi(0xc0000), %l7
sub %i1, %l7, %i1
lduw [%i1 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4058: !_LD [26] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
sethi %hi(0xc0000), %o5
add %i1, %o5, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_6_41:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_41
nop
P4059: !_BLD [8] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_42:
wr %g0, 0xf0, %asi
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_6_42:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_42
nop
P4060: !_LD [24] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_43:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4061: !_BLD [24] (FP)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P4062: !_LD [9] (Int) (Loop exit)
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 4], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_6_43:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_43
nop
P4063: !_LD [4] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_44:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 4
sethi %hi(0xc0000), %l3
sub %i1, %l3, %i1
lduw [%i1 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4064: !_LD [21] (Int) (Loop exit) (Branch target of P4231)
sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 4], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
sethi %hi(0xc0000), %l6
add %i1, %l6, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_6_44:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_44
nop
ba P4065
nop
TARGET4231:
ba RET4231
nop
P4065: !_SWAP [4] (maybe <- 0x300000d) (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_45:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 4
sethi %hi(0xc0000), %l7
sub %i1, %l7, %i1
mov %l4, %o0
swap [%i1 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
add %l4, 1, %l4
P4066: !_LD [30] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
sethi %hi(0xc0000), %l3
add %i1, %l3, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_6_45:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_45
nop
P4067: !_BLD [27] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_46:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P4068: !_BLD [23] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f32
membar #Sync
! 4 addresses covered
fmovd %f32, %f4
fmovd %f34, %f18
fmovs %f19, %f6
fmovd %f40, %f18
fmovs %f18, %f7
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovd %f4, %f30
fmovd %f6, %f30
!--
loop_exit_6_46:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_46
nop
P4069: !_BLD [5] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_47:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 5
sethi %hi(0xc0000), %o5
sub %i1, %o5, %i1
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P4070: !_BLD [15] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f32
membar #Sync
! 4 addresses covered
fmovd %f32, %f4
fmovd %f34, %f18
fmovs %f19, %f6
fmovd %f40, %f18
fmovs %f18, %f7
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovd %f4, %f30
fmovd %f6, %f30
!--
sethi %hi(0xc0000), %l3
add %i1, %l3, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_6_47:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_47
nop
P4071: !_BSTC [17] (maybe <- 0x4280000a) (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_48:
wr %g0, 0xe0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i3
sub %i0, %i3, %i3
! preparing store val #0, next val will be in f32
fmovs %f16, %f20
fadds %f16, %f17, %f16
! preparing store val #1, next val will be in f33
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #2, next val will be in f35
fmovd %f20, %f32
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #3, next val will be in f40
fmovd %f20, %f34
fmovs %f16, %f20
fadds %f16, %f17, %f16
fmovd %f20, %f40
membar #Sync
stda %f32, [%i3 + 0 ] %asi
membar #Sync
loop_exit_6_48:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_48
nop
P4072: !_LD [31] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_49:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4073: !_LD [19] (Int) (Loop exit) (LE)
wr %g0, 0x88, %asi
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduwa [%i3 + 32] %asi, %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_6_49:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_49
nop
P4074: !_BLD [8] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_50:
wr %g0, 0xf0, %asi
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_6_50:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_50
nop
P4075: !_BLD [25] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_51:
wr %g0, 0xf0, %asi
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P4076: !_BLD [14] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f32
membar #Sync
! 4 addresses covered
fmovd %f32, %f4
fmovd %f34, %f18
fmovs %f19, %f6
fmovd %f40, %f18
fmovs %f18, %f7
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovd %f4, %f30
fmovd %f6, %f30
!--
loop_exit_6_51:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_51
nop
P4077: !_DWLD [25] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_52:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
P4078: !_BLD [1] (FP) (Loop exit)
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i0 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_6_52:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_52
nop
P4079: !_BLD [10] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_53:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_6_53:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_53
nop
P4080: !_LD [23] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_54:
sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4081: !_LD [17] (Int) (Loop exit) (CBR)
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 4], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET4081
nop
RET4081:
! lfsr step begin
srlx %l0, 1, %l7
xnor %l7, %l0, %l7
sllx %l7, 63, %l7
or %l7, %l0, %l0
srlx %l0, 1, %l0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_6_54:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_54
nop
P4082: !_LD [3] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_55:
lduw [%i0 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4083: !_DWLD [6] (Int) (Loop exit)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 6
sethi %hi(0xc0000), %l7
sub %i1, %l7, %i1
ldx [%i1 + 8], %l3
! move %l3(lower) -> %o0(lower)
srl %l3, 0, %o5
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
sethi %hi(0xc0000), %l6
add %i1, %l6, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_6_55:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_55
nop
P4084: !_DWLD [24] (Int) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_56:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_6_56:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_56
nop
P4085: !_SWAP [14] (maybe <- 0x300000e) (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_57:
sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
mov %l4, %o0
swap [%i2 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
add %l4, 1, %l4
P4086: !_LD [6] (Int) (Loop exit)
lduw [%i1 + 12], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_6_57:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_57
nop
P4087: !_BLD [17] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_58:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P4088: !_DWLD [16] (Int) (Loop exit)
ldx [%i3 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_6_58:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_58
nop
P4089: !_LD [22] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_59:
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4090: !_LD [12] (Int) (Loop exit)
sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 0], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_6_59:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_59
nop
P4091: !_DWLD [3] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_60:
ldx [%i0 + 32], %o0
! move %o0(upper) -> %o0(upper)
P4092: !_LD [12] (Int) (Loop exit)
sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 0], %l7
! move %l7(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_6_60:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_60
nop
P4093: !_BLD [7] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_61:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 7
sethi %hi(0xc0000), %l3
sub %i1, %l3, %i1
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P4094: !_MEMBAR (Int) (Loop exit) (Branch target of P4567)
membar #StoreLoad
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
sethi %hi(0xc0000), %l6
add %i1, %l6, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_6_61:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_61
nop
ba P4095
nop
TARGET4567:
ba RET4567
nop
P4095: !_LD [11] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_62:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4096: !_BLD [18] (FP)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P4097: !_LD [18] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_6_62:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_62
nop
P4098: !_DWLD [6] (Int) (Loop entry) (CBR)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_63:
ldx [%i1 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET4098
nop
RET4098:
! lfsr step begin
srlx %l0, 1, %o5
xnor %o5, %l0, %o5
sllx %o5, 63, %o5
or %o5, %l0, %l0
srlx %l0, 1, %l0
P4099: !_BLD [2] (FP) (Branch target of P4458)
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i0 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
ba P4100
nop
TARGET4458:
ba RET4458
nop
P4100: !_LD [21] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_6_63:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_63
nop
P4101: !_DWLD [19] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_64:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
sub %i0, %i3, %i3
ldd [%i3 + 32], %f0
! 1 addresses covered
P4102: !_LD [21] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4103: !_LD [25] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 4], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
loop_exit_6_64:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_64
nop
P4104: !_LD [3] (Int) (Loop entry) (Branch target of P3984)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_65:
lduw [%i0 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
ba P4105
nop
TARGET3984:
ba RET3984
nop
P4105: !_LD [25] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_6_65:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_65
nop
P4106: !_LD [2] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_66:
lduw [%i0 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4107: !_LD [4] (Int) (Loop exit)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 4
sethi %hi(0xc0000), %o5
sub %i1, %o5, %i1
lduw [%i1 + 0], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
sethi %hi(0xc0000), %l7
add %i1, %l7, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_6_66:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_66
nop
P4108: !_LD [28] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_67:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4109: !_DWLD [15] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 32], %o5
! move %o5(upper) -> %o0(lower)
srlx %o5, 32, %l7
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_6_67:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_67
nop
P4110: !_DWLD [19] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_68:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 32], %o0
! move %o0(upper) -> %o0(upper)
P4111: !_LD [13] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %l6
! move %l6(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_6_68:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_68
nop
P4112: !_BLD [26] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_69:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P4113: !_ST [26] (maybe <- 0x300000f) (Int) (Loop exit)
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
stw %l4, [%i2 + 12 ]
add %l4, 1, %l4
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_6_69:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_69
nop
P4114: !_BLD [0] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_70:
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i0 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_6_70:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_70
nop
P4115: !_DWLD [14] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_71:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4116: !_LD [26] (Int) (Loop exit) (LE)
wr %g0, 0x88, %asi
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduwa [%i2 + 12] %asi, %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_6_71:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_71
nop
P4117: !_DWLD [14] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_72:
sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
ldx [%i3 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4118: !_LD [27] (Int) (Loop exit)
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 32], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_6_72:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_72
nop
P4119: !_ST [12] (maybe <- 0x3000010) (Int) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_73:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i3
sub %i0, %i3, %i3
stw %l4, [%i3 + 0 ]
add %l4, 1, %l4
loop_exit_6_73:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_73
nop
P4120: !_DWLD [2] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_74:
ldx [%i0 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4121: !_BSTC [17] (maybe <- 0x4280000e) (FP)
wr %g0, 0xe0, %asi
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
! preparing store val #0, next val will be in f32
fmovs %f16, %f20
fadds %f16, %f17, %f16
! preparing store val #1, next val will be in f33
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #2, next val will be in f35
fmovd %f20, %f32
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #3, next val will be in f40
fmovd %f20, %f34
fmovs %f16, %f20
fadds %f16, %f17, %f16
fmovd %f20, %f40
membar #Sync
stda %f32, [%i2 + 0 ] %asi
membar #Sync
P4122: !_LD [21] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 4], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_6_74:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_74
nop
P4123: !_DWLD [16] (Int) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_75:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_6_75:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_75
nop
P4124: !_BLD [17] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_76:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_6_76:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_76
nop
P4125: !_DWLD [31] (FP) (Loop entry) (Loop exit) (Branch target of P4204)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_77:
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
ldd [%i2 + 32], %f0
! 1 addresses covered
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
loop_exit_6_77:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_77
nop
ba P4126
nop
TARGET4204:
ba RET4204
nop
P4126: !_BLD [13] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_78:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P4127: !_LD [4] (Int)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 4
sethi %hi(0xc0000), %l7
sub %i1, %l7, %i1
lduw [%i1 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4128: !_LD [19] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 32], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
sethi %hi(0xc0000), %o5
add %i1, %o5, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_6_78:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_78
nop
P4129: !_BLD [23] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_79:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P4130: !_DWLD [22] (Int)
ldx [%i3 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4131: !_LD [28] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 0], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_6_79:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_79
nop
P4132: !_DWLD [24] (Int) (Loop entry) (Loop exit) (Branch target of P4513)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_80:
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
ldx [%i3 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_6_80:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_80
nop
ba P4133
nop
TARGET4513:
ba RET4513
nop
P4133: !_BLD [20] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_81:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_6_81:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_81
nop
P4134: !_NOP (Int) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_82:
nop
loop_exit_6_82:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_82
nop
P4135: !_BLD [13] (FP) (Loop entry) (CBR)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_83:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET4135
nop
RET4135:
! lfsr step begin
srlx %l0, 1, %l7
xnor %l7, %l0, %l7
sllx %l7, 63, %l7
or %l7, %l0, %l0
srlx %l0, 1, %l0
P4136: !_BLD [10] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f32
membar #Sync
! 4 addresses covered
fmovd %f32, %f4
fmovd %f34, %f18
fmovs %f19, %f6
fmovd %f40, %f18
fmovs %f18, %f7
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovd %f4, %f30
fmovd %f6, %f30
!--
loop_exit_6_83:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_83
nop
P4137: !_BLD [29] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_84:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P4138: !_DWLD [16] (Int) (Loop exit) (CBR)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET4138
nop
RET4138:
! lfsr step begin
srlx %l0, 1, %o5
xnor %o5, %l0, %o5
sllx %o5, 63, %o5
or %o5, %l0, %l0
srlx %l0, 1, %l0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_6_84:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_84
nop
P4139: !_DWLD [22] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_85:
sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
ldx [%i3 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4140: !_DWLD [7] (Int) (Loop exit)
ldx [%i1 + 32], %l6
! move %l6(upper) -> %o0(lower)
srlx %l6, 32, %l3
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_6_85:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_85
nop
P4141: !_DWLD [17] (Int) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_86:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_6_86:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_86
nop
P4142: !_BLD [18] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_87:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P4143: !_LD [17] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4144: !_LD [16] (Int) (Loop exit)
lduw [%i2 + 0], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_6_87:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_87
nop
P4145: !_BLD [16] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_88:
wr %g0, 0xf0, %asi
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_6_88:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_88
nop
P4146: !_DWLD [20] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_89:
sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
ldx [%i2 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
P4147: !_BLD [18] (FP) (Loop exit) (Branch target of P4258)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_6_89:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_89
nop
ba P4148
nop
TARGET4258:
ba RET4258
nop
P4148: !_DWLD [29] (Int) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_90:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_6_90:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_90
nop
P4149: !_BLD [27] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_91:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P4150: !_BLD [16] (FP) (Loop exit) (Branch target of P4156)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f32
membar #Sync
! 4 addresses covered
fmovd %f32, %f4
fmovd %f34, %f18
fmovs %f19, %f6
fmovd %f40, %f18
fmovs %f18, %f7
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovd %f4, %f30
fmovd %f6, %f30
!--
loop_exit_6_91:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_91
nop
ba P4151
nop
TARGET4156:
ba RET4156
nop
P4151: !_BLD [19] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_92:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P4152: !_LD [10] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4153: !_LD [2] (Int) (Loop exit)
lduw [%i0 + 12], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_6_92:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_92
nop
P4154: !_DWLD [0] (Int) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_93:
ldx [%i0 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_6_93:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_93
nop
P4155: !_BLD [3] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_94:
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i0 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_6_94:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_94
nop
P4156: !_BSTC [9] (maybe <- 0x42800012) (FP) (Loop entry) (Loop exit) (CBR)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_95:
wr %g0, 0xe0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
sub %i0, %i3, %i3
! preparing store val #0, next val will be in f32
fmovs %f16, %f20
fadds %f16, %f17, %f16
! preparing store val #1, next val will be in f33
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #2, next val will be in f35
fmovd %f20, %f32
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #3, next val will be in f40
fmovd %f20, %f34
fmovs %f16, %f20
fadds %f16, %f17, %f16
fmovd %f20, %f40
membar #Sync
stda %f32, [%i3 + 0 ] %asi
membar #Sync
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET4156
nop
RET4156:
! lfsr step begin
srlx %l0, 1, %o5
xnor %o5, %l0, %o5
sllx %o5, 63, %o5
or %o5, %l0, %l0
srlx %l0, 1, %l0
loop_exit_6_95:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_95
nop
P4157: !_LD [8] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_96:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4158: !_LD [31] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_6_96:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_96
nop
P4159: !_BLD [30] (FP) (Loop entry) (Branch target of P4161)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_97:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
ba P4160
nop
TARGET4161:
ba RET4161
nop
P4160: !_DWLD [4] (Int) (Loop exit)
ldx [%i1 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_6_97:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_97
nop
P4161: !_LD [18] (Int) (Loop entry) (CBR)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_98:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET4161
nop
RET4161:
! lfsr step begin
srlx %l0, 1, %l7
xnor %l7, %l0, %l7
sllx %l7, 63, %l7
or %l7, %l0, %l0
srlx %l0, 1, %l0
P4162: !_LD [7] (Int) (Loop exit)
lduw [%i1 + 32], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_6_98:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_98
nop
P4163: !_LD [9] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_99:
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4164: !_LD [6] (Int) (Loop exit)
lduw [%i1 + 12], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_6_99:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_99
nop
P4165: !_LD [2] (Int) (Loop entry) (CBR)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_100:
lduw [%i0 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET4165
nop
RET4165:
! lfsr step begin
srlx %l0, 1, %o5
xnor %o5, %l0, %o5
sllx %o5, 63, %o5
or %o5, %l0, %l0
srlx %l0, 1, %l0
P4166: !_LD [27] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_6_100:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_100
nop
P4167: !_LD [17] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_101:
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4168: !_LD [12] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_6_101:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_101
nop
P4169: !_LD [19] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_102:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4170: !_BLD [18] (FP)
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P4171: !_LD [0] (Int) (Loop exit)
lduw [%i0 + 0], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_6_102:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_102
nop
P4172: !_LD [16] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_103:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4173: !_DWLD [5] (FP)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 5
sethi %hi(0xc0000), %l7
sub %i1, %l7, %i1
ldd [%i1 + 0], %f0
! 2 addresses covered
P4174: !_LD [6] (Int) (Loop exit)
lduw [%i1 + 12], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
!--
sethi %hi(0xc0000), %l6
add %i1, %l6, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_6_103:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_103
nop
P4175: !_DWLD [19] (Int) (Loop entry) (Branch target of P4234)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_104:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 32], %o0
! move %o0(upper) -> %o0(upper)
ba P4176
nop
TARGET4234:
ba RET4234
nop
P4176: !_LD [5] (Int) (Loop exit)
lduw [%i1 + 4], %l7
! move %l7(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_6_104:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_104
nop
P4177: !_LD [27] (Int) (Loop entry) (CBR)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_105:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET4177
nop
RET4177:
! lfsr step begin
srlx %l0, 1, %o5
xnor %o5, %l0, %o5
sllx %o5, 63, %o5
or %o5, %l0, %l0
srlx %l0, 1, %l0
P4178: !_LD [18] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_6_105:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_105
nop
P4179: !_LD [26] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_106:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4180: !_BLD [1] (FP)
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i0 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P4181: !_LD [21] (Int) (Loop exit) (CBR)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET4181
nop
RET4181:
! lfsr step begin
srlx %l0, 1, %l6
xnor %l6, %l0, %l6
sllx %l6, 63, %l6
or %l6, %l0, %l0
srlx %l0, 1, %l0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_6_106:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_106
nop
P4182: !_DWLD [30] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_107:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4183: !_BLD [31] (FP) (CBR)
wr %g0, 0xf0, %asi
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET4183
nop
RET4183:
! lfsr step begin
srlx %l0, 1, %l7
xnor %l7, %l0, %l7
sllx %l7, 63, %l7
or %l7, %l0, %l0
srlx %l0, 1, %l0
P4184: !_LD [2] (Int) (Loop exit) (Branch target of P4250)
lduw [%i0 + 12], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_6_107:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_107
nop
ba P4185
nop
TARGET4250:
ba RET4250
nop
P4185: !_DWLD [22] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_108:
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4186: !_LD [1] (Int) (Loop exit)
lduw [%i0 + 4], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_6_108:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_108
nop
P4187: !_BLD [30] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_109:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P4188: !_MEMBAR (Int) (Loop exit)
membar #StoreLoad
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_6_109:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_109
nop
P4189: !_BLD [17] (FP) (Loop entry) (Branch target of P4383)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_110:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
ba P4190
nop
TARGET4383:
ba RET4383
nop
P4190: !_LD [28] (Int) (Branch target of P4455)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
ba P4191
nop
TARGET4455:
ba RET4455
nop
P4191: !_LD [29] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 4], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_6_110:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_110
nop
P4192: !_BLD [17] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_111:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_6_111:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_111
nop
P4193: !_BLD [12] (FP) (Loop entry) (Loop exit) (CBR)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_112:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET4193
nop
RET4193:
! lfsr step begin
srlx %l0, 1, %o5
xnor %o5, %l0, %o5
sllx %o5, 63, %o5
or %o5, %l0, %l0
srlx %l0, 1, %l0
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_6_112:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_112
nop
P4194: !_DWLD [24] (Int) (Loop entry) (Branch target of P4469)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_113:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
ba P4195
nop
TARGET4469:
ba RET4469
nop
P4195: !_DWLD [23] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 32], %o1
! move %o1(upper) -> %o1(upper)
P4196: !_LD [21] (Int) (Loop exit)
lduw [%i3 + 4], %o5
! move %o5(lower) -> %o1(lower)
srlx %o1, 32, %o1
sllx %o1, 32, %o1
or %o5, %o1, %o1
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_6_113:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_113
nop
P4197: !_BST [8] (maybe <- 0x42800016) (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_114:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i2
sub %i0, %i2, %i2
! preparing store val #0, next val will be in f32
fmovs %f16, %f20
fadds %f16, %f17, %f16
! preparing store val #1, next val will be in f33
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #2, next val will be in f35
fmovd %f20, %f32
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #3, next val will be in f40
fmovd %f20, %f34
fmovs %f16, %f20
fadds %f16, %f17, %f16
fmovd %f20, %f40
membar #Sync
stda %f32, [%i2 + 0 ] %asi
membar #Sync
loop_exit_6_114:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_114
nop
P4198: !_BLD [3] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_115:
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i0 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_6_115:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_115
nop
P4199: !_DWLD [23] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_116:
sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
ldx [%i3 + 32], %o0
! move %o0(upper) -> %o0(upper)
P4200: !_BLD [10] (FP) (CBR)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET4200
nop
RET4200:
! lfsr step begin
srlx %l0, 1, %l7
xnor %l7, %l0, %l7
sllx %l7, 63, %l7
or %l7, %l0, %l0
srlx %l0, 1, %l0
P4201: !_LD [21] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 4], %l6
! move %l6(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_6_116:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_116
nop
P4202: !_DWLD [24] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_117:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
P4203: !_LD [26] (Int)
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 12], %o1
! move %o1(lower) -> %o1(upper)
sllx %o1, 32, %o1
P4204: !_LD [29] (Int) (Loop exit) (CBR)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %l6
! move %l6(lower) -> %o1(lower)
or %l6, %o1, %o1
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET4204
nop
RET4204:
! lfsr step begin
srlx %l0, 1, %l7
xnor %l7, %l0, %l7
sllx %l7, 63, %l7
or %l7, %l0, %l0
srlx %l0, 1, %l0
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_6_117:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_117
nop
P4205: !_DWLD [10] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_118:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4206: !_LD [9] (Int) (Loop exit)
lduw [%i3 + 4], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_6_118:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_118
nop
P4207: !_LD [6] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_119:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 6
sethi %hi(0xc0000), %l7
sub %i1, %l7, %i1
lduw [%i1 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4208: !_ST [5] (maybe <- 0x3000011) (Int)
stw %l4, [%i1 + 4 ]
add %l4, 1, %l4
P4209: !_LD [3] (Int) (Loop exit)
lduw [%i0 + 32], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
sethi %hi(0xc0000), %o5
add %i1, %o5, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_6_119:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_119
nop
P4210: !_DWLD [13] (Int) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_120:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_6_120:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_120
nop
P4211: !_DWLD [14] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_121:
sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
ldx [%i3 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4212: !_LD [9] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_6_121:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_121
nop
P4213: !_BLD [30] (FP) (Loop entry) (Loop exit) (Branch target of P4449)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_122:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_6_122:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_122
nop
ba P4214
nop
TARGET4449:
ba RET4449
nop
P4214: !_DWLD [15] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_123:
sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
ldx [%i2 + 32], %o0
! move %o0(upper) -> %o0(upper)
P4215: !_DWST [14] (maybe <- 0x3000012) (Int)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i3
sub %i0, %i3, %i3
mov %l4, %l7
stx %l7, [%i3 + 8]
add %l4, 1, %l4
P4216: !_LD [5] (Int) (Loop exit)
lduw [%i1 + 4], %l7
! move %l7(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_6_123:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_123
nop
P4217: !_BLD [5] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_124:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 5
sethi %hi(0xc0000), %l3
sub %i1, %l3, %i1
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
sethi %hi(0xc0000), %l6
add %i1, %l6, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_6_124:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_124
nop
P4218: !_LD [19] (Int) (Loop entry) (LE)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_125:
wr %g0, 0x88, %asi
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduwa [%i2 + 32] %asi, %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4219: !_DWLD [15] (Int) (Loop exit) (Branch target of P4657)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 32], %l7
! move %l7(upper) -> %o0(lower)
srlx %l7, 32, %l6
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_6_125:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_125
nop
ba P4220
nop
TARGET4657:
ba RET4657
nop
P4220: !_BLD [21] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_126:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_6_126:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_126
nop
P4221: !_LD [1] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_127:
lduw [%i0 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4222: !_DWLD [12] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 0], %l6
! move %l6(upper) -> %o0(lower)
srlx %l6, 32, %l3
or %l3, %o0, %o0
! move %l6(lower) -> %o1(upper)
sllx %l6, 32, %o1
P4223: !_LD [30] (Int) (Loop exit) (Branch target of P4365)
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 12], %l3
! move %l3(lower) -> %o1(lower)
or %l3, %o1, %o1
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_6_127:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_127
nop
ba P4224
nop
TARGET4365:
ba RET4365
nop
P4224: !_LD [6] (Int) (Loop entry) (Branch target of P4177)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_128:
lduw [%i1 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
ba P4225
nop
TARGET4177:
ba RET4177
nop
P4225: !_LD [4] (Int) (Loop exit)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 4
sethi %hi(0xc0000), %l3
sub %i1, %l3, %i1
lduw [%i1 + 0], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
sethi %hi(0xc0000), %o5
add %i1, %o5, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_6_128:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_128
nop
P4226: !_LD [3] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_129:
ld [%i0 + 32], %f0
! 1 addresses covered
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
loop_exit_6_129:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_129
nop
P4227: !_LD [11] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_130:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4228: !_DWLD [7] (Int) (Loop exit)
ldx [%i1 + 32], %l6
! move %l6(upper) -> %o0(lower)
srlx %l6, 32, %l3
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_6_130:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_130
nop
P4229: !_BLD [22] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_131:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P4230: !_LD [27] (Int)
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4231: !_LD [22] (Int) (Loop exit) (CBR)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET4231
nop
RET4231:
! lfsr step begin
srlx %l0, 1, %l6
xnor %l6, %l0, %l6
sllx %l6, 63, %l6
or %l6, %l0, %l0
srlx %l0, 1, %l0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_6_131:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_131
nop
P4232: !_NOP (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_132:
nop
P4233: !_DWLD [19] (Int) (Branch target of P4200)
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
ldx [%i3 + 32], %o0
! move %o0(upper) -> %o0(upper)
ba P4234
nop
TARGET4200:
ba RET4200
nop
P4234: !_LD [24] (Int) (Loop exit) (CBR)
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 0], %o5
! move %o5(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %o5, %o0, %o0
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET4234
nop
RET4234:
! lfsr step begin
srlx %l0, 1, %l3
xnor %l3, %l0, %l3
sllx %l3, 63, %l3
or %l3, %l0, %l0
srlx %l0, 1, %l0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_6_132:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_132
nop
P4235: !_LD [31] (Int) (Loop entry) (LE)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_133:
wr %g0, 0x88, %asi
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduwa [%i3 + 32] %asi, %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4236: !_LD [13] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_6_133:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_133
nop
P4237: !_DWLD [10] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_134:
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
ldd [%i3 + 8], %f0
! 1 addresses covered
fmovs %f1, %f0
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
loop_exit_6_134:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_134
nop
P4238: !_DWLD [26] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_135:
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
ldx [%i2 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4239: !_LD [2] (Int) (Loop exit)
lduw [%i0 + 12], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_6_135:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_135
nop
P4240: !_LD [12] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_136:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4241: !_LD [7] (Int) (Loop exit)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 7
sethi %hi(0xc0000), %l7
sub %i1, %l7, %i1
lduw [%i1 + 32], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
sethi %hi(0xc0000), %l6
add %i1, %l6, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_6_136:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_136
nop
P4242: !_DWLD [9] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_137:
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
ldx [%i2 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
P4243: !_LD [6] (Int) (Branch target of P4046)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 6
sethi %hi(0xc0000), %l3
sub %i1, %l3, %i1
lduw [%i1 + 12], %o1
! move %o1(lower) -> %o1(upper)
sllx %o1, 32, %o1
ba P4244
nop
TARGET4046:
ba RET4046
nop
P4244: !_LD [30] (Int) (Loop exit) (Branch target of P4320)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %l3
! move %l3(lower) -> %o1(lower)
or %l3, %o1, %o1
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
sethi %hi(0xc0000), %l6
add %i1, %l6, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_6_137:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_137
nop
ba P4245
nop
TARGET4320:
ba RET4320
nop
P4245: !_LD [27] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_138:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
sub %i0, %i2, %i2
ld [%i2 + 32], %f0
! 1 addresses covered
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
loop_exit_6_138:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_138
nop
P4246: !_BLD [16] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_139:
wr %g0, 0xf0, %asi
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_6_139:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_139
nop
P4247: !_BLD [29] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_140:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_6_140:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_140
nop
P4248: !_BLD [18] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_141:
wr %g0, 0xf0, %asi
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P4249: !_LD [22] (Int)
sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4250: !_LD [13] (Int) (Loop exit) (CBR)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 4], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET4250
nop
RET4250:
! lfsr step begin
srlx %l0, 1, %l3
xnor %l3, %l0, %l3
sllx %l3, 63, %l3
or %l3, %l0, %l0
srlx %l0, 1, %l0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_6_141:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_141
nop
P4251: !_DWLD [20] (Int) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_142:
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_6_142:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_142
nop
P4252: !_DWLD [6] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_143:
ldx [%i1 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4253: !_LD [19] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_6_143:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_143
nop
P4254: !_BLD [13] (FP) (Loop entry) (Branch target of P4081)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_144:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
ba P4255
nop
TARGET4081:
ba RET4081
nop
P4255: !_LD [31] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4256: !_LD [20] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 0], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_6_144:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_144
nop
P4257: !_LD [25] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_145:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4258: !_LD [20] (Int) (Loop exit) (CBR)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 0], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET4258
nop
RET4258:
! lfsr step begin
srlx %l0, 1, %o5
xnor %o5, %l0, %o5
sllx %o5, 63, %o5
or %o5, %l0, %l0
srlx %l0, 1, %l0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_6_145:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_145
nop
P4259: !_LD [3] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_146:
lduw [%i0 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4260: !_LD [1] (Int) (Loop exit)
lduw [%i0 + 4], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_6_146:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_146
nop
P4261: !_BLD [13] (FP) (Loop entry) (Loop exit) (Branch target of P4602)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_147:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_6_147:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_147
nop
ba P4262
nop
TARGET4602:
ba RET4602
nop
P4262: !_BLD [21] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_148:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_6_148:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_148
nop
P4263: !_LD [16] (Int) (Loop entry) (CBR)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_149:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET4263
nop
RET4263:
! lfsr step begin
srlx %l0, 1, %l6
xnor %l6, %l0, %l6
sllx %l6, 63, %l6
or %l6, %l0, %l0
srlx %l0, 1, %l0
P4264: !_DWLD [14] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 8], %o5
! move %o5(lower) -> %o0(lower)
srl %o5, 0, %l7
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_6_149:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_149
nop
P4265: !_BLD [4] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_150:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 4
sethi %hi(0xc0000), %l6
sub %i1, %l6, %i1
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P4266: !_BLD [26] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f32
membar #Sync
! 4 addresses covered
fmovd %f32, %f4
fmovd %f34, %f18
fmovs %f19, %f6
fmovd %f40, %f18
fmovs %f18, %f7
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovd %f4, %f30
fmovd %f6, %f30
!--
sethi %hi(0xc0000), %l7
add %i1, %l7, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_6_150:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_150
nop
P4267: !_BLD [25] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_151:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_6_151:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_151
nop
P4268: !_PREFETCH [22] (Int) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_152:
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i3
sub %i0, %i3, %i3
prefetch [%i3 + 12], 1
loop_exit_6_152:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_152
nop
P4269: !_LD [14] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_153:
sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4270: !_SWAP [13] (maybe <- 0x3000013) (Int) (Loop exit)
mov %l4, %o5
swap [%i2 + 4], %o5
! move %o5(lower) -> %o0(lower)
srl %o5, 0, %l6
or %l6, %o0, %o0
add %l4, 1, %l4
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_6_153:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_153
nop
P4271: !_BLD [31] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_154:
wr %g0, 0xf0, %asi
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_6_154:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_154
nop
P4272: !_FLUSHI [20] (Int) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_155:
flush %g0
loop_exit_6_155:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_155
nop
P4273: !_BLD [26] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_156:
wr %g0, 0xf0, %asi
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_6_156:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_156
nop
P4274: !_ST [18] (maybe <- 0x3000014) (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_157:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i3
sub %i0, %i3, %i3
stw %l4, [%i3 + 12 ]
add %l4, 1, %l4
P4275: !_LD [14] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4276: !_LD [29] (Int) (Loop exit) (CBR)
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 4], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET4276
nop
RET4276:
! lfsr step begin
srlx %l0, 1, %l7
xnor %l7, %l0, %l7
sllx %l7, 63, %l7
or %l7, %l0, %l0
srlx %l0, 1, %l0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_6_157:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_157
nop
P4277: !_BLD [22] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_158:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_6_158:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_158
nop
P4278: !_DWLD [27] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_159:
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
ldx [%i3 + 32], %o0
! move %o0(upper) -> %o0(upper)
P4279: !_LD [15] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 32], %l7
! move %l7(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_6_159:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_159
nop
P4280: !_BLD [27] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_160:
wr %g0, 0xf0, %asi
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P4281: !_BLD [7] (FP) (Loop exit)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 7
sethi %hi(0xc0000), %l3
sub %i1, %l3, %i1
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f32
membar #Sync
! 4 addresses covered
fmovd %f32, %f4
fmovd %f34, %f18
fmovs %f19, %f6
fmovd %f40, %f18
fmovs %f18, %f7
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovd %f4, %f30
fmovd %f6, %f30
!--
sethi %hi(0xc0000), %l6
add %i1, %l6, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_6_160:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_160
nop
P4282: !_LD [28] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_161:
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4283: !_LD [5] (Int) (Loop exit)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 5
sethi %hi(0xc0000), %l3
sub %i1, %l3, %i1
lduw [%i1 + 4], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
sethi %hi(0xc0000), %o5
add %i1, %o5, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_6_161:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_161
nop
P4284: !_LD [18] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_162:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4285: !_LD [24] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 0], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_6_162:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_162
nop
P4286: !_BLD [17] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_163:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_6_163:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_163
nop
P4287: !_LD [23] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_164:
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4288: !_DWLD [10] (Int) (Loop exit)
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
ldx [%i3 + 8], %o5
! move %o5(lower) -> %o0(lower)
srl %o5, 0, %l7
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_6_164:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_164
nop
P4289: !_LD [25] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_165:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4290: !_LD [24] (Int) (Loop exit)
lduw [%i2 + 0], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_6_165:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_165
nop
P4291: !_DWLD [19] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_166:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 32], %o0
! move %o0(upper) -> %o0(upper)
P4292: !_LD [19] (Int) (Loop exit)
lduw [%i3 + 32], %o5
! move %o5(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_6_166:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_166
nop
P4293: !_DWLD [25] (Int) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_167:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_6_167:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_167
nop
P4294: !_DWLD [2] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_168:
ldx [%i0 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4295: !_LD [12] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_6_168:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_168
nop
P4296: !_LD [21] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_169:
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4297: !_LD [28] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_6_169:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_169
nop
P4298: !_BLD [7] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_170:
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_6_170:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_170
nop
P4299: !_BLD [28] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_171:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P4300: !_LD [1] (Int)
lduw [%i0 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4301: !_LD [12] (Int) (Loop exit)
sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 0], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_6_171:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_171
nop
P4302: !_DWST [27] (maybe <- 0x3000015) (Int) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_172:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i2
sub %i0, %i2, %i2
mov %l4, %l6
sllx %l6, 32, %l6
stx %l6, [%i2 + 32 ]
add %l4, 1, %l4
loop_exit_6_172:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_172
nop
P4303: !_DWLD [9] (Int) (Loop entry) (Loop exit) (LE)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_173:
wr %g0, 0x88, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i3
sub %i0, %i3, %i3
ldxa [%i3 + 0] %asi, %o5
! move %o5(lower) -> %o0(upper)
sllx %o5, 32, %o0
! move %o5(upper) -> %o0(lower)
srlx %o5, 32, %l7
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_6_173:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_173
nop
P4304: !_LD [15] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_174:
sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4305: !_LD [20] (Int) (Loop exit) (Branch target of P4138)
sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 0], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_6_174:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_174
nop
ba P4306
nop
TARGET4138:
ba RET4138
nop
P4306: !_BLD [3] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_175:
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i0 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_6_175:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_175
nop
P4307: !_LD [24] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_176:
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4308: !_DWLD [16] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 0], %l3
! move %l3(upper) -> %o0(lower)
srlx %l3, 32, %o5
or %o5, %o0, %o0
! move %l3(lower) -> %o1(upper)
sllx %l3, 32, %o1
P4309: !_LD [18] (Int) (Loop exit)
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 12], %o5
! move %o5(lower) -> %o1(lower)
or %o5, %o1, %o1
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_6_176:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_176
nop
P4310: !_LD [0] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_177:
lduw [%i0 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4311: !_BLD [9] (FP) (Branch target of P4618)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
ba P4312
nop
TARGET4618:
ba RET4618
nop
P4312: !_LD [13] (Int) (Loop exit)
sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 4], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_6_177:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_177
nop
P4313: !_BLD [10] (FP) (Loop entry) (Branch target of P3995)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_178:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
ba P4314
nop
TARGET3995:
ba RET3995
nop
P4314: !_LD [29] (Int) (LE)
wr %g0, 0x88, %asi
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduwa [%i2 + 4] %asi, %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4315: !_LD [31] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_6_178:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_178
nop
P4316: !_LD [29] (Int) (Loop entry) (CBR)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_179:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET4316
nop
RET4316:
! lfsr step begin
srlx %l0, 1, %l3
xnor %l3, %l0, %l3
sllx %l3, 63, %l3
or %l3, %l0, %l0
srlx %l0, 1, %l0
P4317: !_LD [29] (Int) (Loop exit)
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 4], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_6_179:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_179
nop
P4318: !_CASX [16] (maybe <- 0x3000016) (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_180:
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
ldx [%i2], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
mov %o0, %l6
sllx %l4, 32, %o1
add %l4, 1, %l4
or %l4, %o1, %o1
casx [%i2], %l6, %o1
! move %o1(upper) -> %o1(upper)
! move %o1(lower) -> %o1(lower)
add %l4, 1, %l4
P4319: !_BLD [24] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_6_180:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_180
nop
P4320: !_LD [22] (Int) (Loop entry) (LE) (CBR)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_181:
wr %g0, 0x88, %asi
sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduwa [%i2 + 12] %asi, %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET4320
nop
RET4320:
! lfsr step begin
srlx %l0, 1, %l6
xnor %l6, %l0, %l6
sllx %l6, 63, %l6
or %l6, %l0, %l0
srlx %l0, 1, %l0
P4321: !_LD [7] (Int) (Loop exit)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 7
sethi %hi(0xc0000), %l7
sub %i1, %l7, %i1
lduw [%i1 + 32], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
sethi %hi(0xc0000), %l6
add %i1, %l6, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_6_181:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_181
nop
P4322: !_DWLD [3] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_182:
ldd [%i0 + 32], %f0
! 1 addresses covered
P4323: !_ST [17] (maybe <- 0x3000018) (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
sub %i0, %i3, %i3
stw %l4, [%i3 + 4 ]
add %l4, 1, %l4
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
loop_exit_6_182:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_182
nop
P4324: !_BLD [14] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_183:
wr %g0, 0xf0, %asi
sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_6_183:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_183
nop
P4325: !_BLD [14] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_184:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P4326: !_LD [24] (Int) (Branch target of P4550)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
ba P4327
nop
TARGET4550:
ba RET4550
nop
P4327: !_LD [11] (Int) (Loop exit) (Branch target of P4316)
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 32], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_6_184:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_184
nop
ba P4328
nop
TARGET4316:
ba RET4316
nop
P4328: !_BLD [1] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_185:
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i0 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_6_185:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_185
nop
P4329: !_DWLD [24] (Int) (Loop entry) (Loop exit) (LE)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_186:
wr %g0, 0x88, %asi
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i2
sub %i0, %i2, %i2
ldxa [%i2 + 0] %asi, %l7
! move %l7(lower) -> %o0(upper)
sllx %l7, 32, %o0
! move %l7(upper) -> %o0(lower)
srlx %l7, 32, %l6
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_6_186:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_186
nop
P4330: !_BLD [13] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_187:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_6_187:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_187
nop
P4331: !_LD [9] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_188:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4332: !_LD [12] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_6_188:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_188
nop
P4333: !_LD [20] (FP) (Loop entry) (Loop exit) (Branch target of P4416)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_189:
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i2
sub %i0, %i2, %i2
ld [%i2 + 0], %f0
! 1 addresses covered
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
loop_exit_6_189:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_189
nop
ba P4334
nop
TARGET4416:
ba RET4416
nop
P4334: !_BLD [30] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_190:
wr %g0, 0xf0, %asi
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P4335: !_DWLD [10] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4336: !_LD [12] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_6_190:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_190
nop
P4337: !_LD [25] (Int) (Loop entry) (CBR)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_191:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET4337
nop
RET4337:
! lfsr step begin
srlx %l0, 1, %l7
xnor %l7, %l0, %l7
sllx %l7, 63, %l7
or %l7, %l0, %l0
srlx %l0, 1, %l0
P4338: !_BLD [10] (FP)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P4339: !_LD [22] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_6_191:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_191
nop
P4340: !_BLD [21] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_192:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_6_192:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_192
nop
P4341: !_LD [24] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_193:
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4342: !_LD [28] (Int) (Loop exit)
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 0], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_6_193:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_193
nop
P4343: !_BLD [13] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_194:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P4344: !_BLD [12] (FP) (Loop exit)
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i2 + 0] %asi, %f32
membar #Sync
! 4 addresses covered
fmovd %f32, %f4
fmovd %f34, %f18
fmovs %f19, %f6
fmovd %f40, %f18
fmovs %f18, %f7
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovd %f4, %f30
fmovd %f6, %f30
!--
loop_exit_6_194:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_194
nop
P4345: !_MEMBAR (Int) (Loop entry) (Loop exit) (CBR)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_195:
membar #StoreLoad
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET4345
nop
RET4345:
! lfsr step begin
srlx %l0, 1, %l6
xnor %l6, %l0, %l6
sllx %l6, 63, %l6
or %l6, %l0, %l0
srlx %l0, 1, %l0
loop_exit_6_195:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_195
nop
P4346: !_LD [28] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_196:
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4347: !_LD [2] (Int) (Loop exit)
lduw [%i0 + 12], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_6_196:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_196
nop
P4348: !_DWLD [21] (Int) (Loop entry) (Loop exit) (CBR)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_197:
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET4348
nop
RET4348:
! lfsr step begin
srlx %l0, 1, %o5
xnor %o5, %l0, %o5
sllx %o5, 63, %o5
or %o5, %l0, %l0
srlx %l0, 1, %l0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_6_197:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_197
nop
P4349: !_DWLD [31] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_198:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 32], %o0
! move %o0(upper) -> %o0(upper)
P4350: !_BLD [25] (FP)
wr %g0, 0xf0, %asi
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P4351: !_LD [12] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %l7
! move %l7(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_6_198:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_198
nop
P4352: !_BLD [27] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_199:
wr %g0, 0xf0, %asi
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_6_199:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_199
nop
P4353: !_DWLD [10] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_200:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4354: !_BLD [11] (FP) (CBR)
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET4354
nop
RET4354:
! lfsr step begin
srlx %l0, 1, %l3
xnor %l3, %l0, %l3
sllx %l3, 63, %l3
or %l3, %l0, %l0
srlx %l0, 1, %l0
P4355: !_LD [3] (Int) (Loop exit)
lduw [%i0 + 32], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_6_200:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_200
nop
P4356: !_BSTC [31] (maybe <- 0x4280001a) (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_201:
wr %g0, 0xe0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
sub %i0, %i2, %i2
! preparing store val #0, next val will be in f32
fmovs %f16, %f20
fadds %f16, %f17, %f16
! preparing store val #1, next val will be in f33
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #2, next val will be in f35
fmovd %f20, %f32
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #3, next val will be in f40
fmovd %f20, %f34
fmovs %f16, %f20
fadds %f16, %f17, %f16
fmovd %f20, %f40
membar #Sync
stda %f32, [%i2 + 0 ] %asi
membar #Sync
P4357: !_LD [9] (Int)
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4358: !_LD [6] (Int) (Loop exit)
lduw [%i1 + 12], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_6_201:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_201
nop
P4359: !_LD [2] (Int) (Loop entry) (Branch target of P4431)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_202:
lduw [%i0 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
ba P4360
nop
TARGET4431:
ba RET4431
nop
P4360: !_DWLD [10] (Int) (Loop exit)
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
ldx [%i2 + 8], %l7
! move %l7(lower) -> %o0(lower)
srl %l7, 0, %l6
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_6_202:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_202
nop
P4361: !_DWLD [14] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_203:
sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
ldx [%i3 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4362: !_LD [18] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_6_203:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_203
nop
P4363: !_MEMBAR (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_204:
membar #StoreLoad
P4364: !_LD [17] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4365: !_LD [30] (Int) (Loop exit) (CBR)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET4365
nop
RET4365:
! lfsr step begin
srlx %l0, 1, %l3
xnor %l3, %l0, %l3
sllx %l3, 63, %l3
or %l3, %l0, %l0
srlx %l0, 1, %l0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_6_204:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_204
nop
P4366: !_BLD [5] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_205:
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_6_205:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_205
nop
P4367: !_DWLD [25] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_206:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
P4368: !_DWLD [27] (Int)
ldx [%i3 + 32], %o1
! move %o1(upper) -> %o1(upper)
P4369: !_LD [21] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %l7
! move %l7(lower) -> %o1(lower)
srlx %o1, 32, %o1
sllx %o1, 32, %o1
or %l7, %o1, %o1
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_6_206:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_206
nop
P4370: !_DWLD [29] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_207:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
P4371: !_LD [17] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %o1
! move %o1(lower) -> %o1(upper)
sllx %o1, 32, %o1
P4372: !_LD [10] (Int) (Loop exit)
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 12], %l7
! move %l7(lower) -> %o1(lower)
or %l7, %o1, %o1
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_6_207:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_207
nop
P4373: !_BLD [24] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_208:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_6_208:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_208
nop
P4374: !_LD [28] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_209:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4375: !_BLD [9] (FP)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P4376: !_LD [22] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_6_209:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_209
nop
P4377: !_REPLACEMENT [9] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_210:
sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS1_O), %i2
sub %i0, %i2, %i2
sethi %hi(0x10000), %l6
ld [%i2+4], %o5
st %o5, [%i2+4]
add %i2, %l6, %l7
ld [%l7+4], %o5
st %o5, [%l7+4]
add %l7, %l6, %l7
ld [%l7+4], %o5
st %o5, [%l7+4]
add %l7, %l6, %l7
ld [%l7+4], %o5
st %o5, [%l7+4]
P4378: !_BLD [16] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_6_210:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_210
nop
P4379: !_DWLD [0] (Int) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_211:
ldx [%i0 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_6_211:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_211
nop
P4380: !_BSTC [8] (maybe <- 0x4280001e) (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_212:
wr %g0, 0xe0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i2
sub %i0, %i2, %i2
! preparing store val #0, next val will be in f32
fmovs %f16, %f20
fadds %f16, %f17, %f16
! preparing store val #1, next val will be in f33
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #2, next val will be in f35
fmovd %f20, %f32
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #3, next val will be in f40
fmovd %f20, %f34
fmovs %f16, %f20
fadds %f16, %f17, %f16
fmovd %f20, %f40
membar #Sync
stda %f32, [%i2 + 0 ] %asi
membar #Sync
loop_exit_6_212:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_212
nop
P4381: !_LD [2] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_213:
lduw [%i0 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4382: !_NOP (Int)
nop
P4383: !_LD [21] (Int) (Loop exit) (CBR)
sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 4], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET4383
nop
RET4383:
! lfsr step begin
srlx %l0, 1, %o5
xnor %o5, %l0, %o5
sllx %o5, 63, %o5
or %o5, %l0, %l0
srlx %l0, 1, %l0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_6_213:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_213
nop
P4384: !_DWLD [8] (Int) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_214:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_6_214:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_214
nop
P4385: !_BLD [30] (FP) (Loop entry) (CBR)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_215:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET4385
nop
RET4385:
! lfsr step begin
srlx %l0, 1, %l6
xnor %l6, %l0, %l6
sllx %l6, 63, %l6
or %l6, %l0, %l0
srlx %l0, 1, %l0
P4386: !_LD [26] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4387: !_LD [23] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_6_215:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_215
nop
P4388: !_DWLD [12] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_216:
sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
ldd [%i2 + 0], %f0
! 2 addresses covered
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
!--
loop_exit_6_216:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_216
nop
P4389: !_BLD [1] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_217:
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i0 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P4390: !_LD [9] (Int) (Branch target of P4098)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
ba P4391
nop
TARGET4098:
ba RET4098
nop
P4391: !_LD [27] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 32], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_6_217:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_217
nop
P4392: !_LD [16] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_218:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4393: !_DWST [4] (maybe <- 0x3000019) (Int)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 4
sethi %hi(0xc0000), %l7
sub %i1, %l7, %i1
sllx %l4, 32, %o5
add %l4, 1, %l4
or %o5, %l4, %o5
stx %o5, [%i1 + 0]
add %l4, 1, %l4
P4394: !_LD [6] (Int) (Loop exit)
lduw [%i1 + 12], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
sethi %hi(0xc0000), %l3
add %i1, %l3, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_6_218:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_218
nop
P4395: !_LD [18] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_219:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i2
sub %i0, %i2, %i2
ld [%i2 + 12], %f0
! 1 addresses covered
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
loop_exit_6_219:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_219
nop
P4396: !_BLD [8] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_220:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P4397: !_DWLD [6] (Int)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 6
sethi %hi(0xc0000), %o5
sub %i1, %o5, %i1
ldx [%i1 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4398: !_LD [24] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 0], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
sethi %hi(0xc0000), %l3
add %i1, %l3, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_6_220:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_220
nop
P4399: !_DWLD [26] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_221:
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
ldx [%i3 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4400: !_LD [2] (Int) (Loop exit)
lduw [%i0 + 12], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_6_221:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_221
nop
P4401: !_DWLD [9] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_222:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
sub %i0, %i2, %i2
ldd [%i2 + 0], %f0
! 2 addresses covered
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
!--
loop_exit_6_222:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_222
nop
P4402: !_MEMBAR (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_223:
membar #StoreLoad
P4403: !_LD [27] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4404: !_LD [3] (Int) (Loop exit)
lduw [%i0 + 32], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_6_223:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_223
nop
P4405: !_DWLD [8] (Int) (Loop entry) (Loop exit) (Branch target of P4193)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_224:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_6_224:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_224
nop
ba P4406
nop
TARGET4193:
ba RET4193
nop
P4406: !_BLD [9] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_225:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P4407: !_LD [9] (Int)
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4408: !_LD [20] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_6_225:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_225
nop
P4409: !_REPLACEMENT [28] (Int) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_226:
sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
sethi %hi(0x10000), %l7
ld [%i2+0], %l3
st %l3, [%i2+0]
add %i2, %l7, %o5
ld [%o5+0], %l3
st %l3, [%o5+0]
add %o5, %l7, %o5
ld [%o5+0], %l3
st %l3, [%o5+0]
add %o5, %l7, %o5
ld [%o5+0], %l3
st %l3, [%o5+0]
loop_exit_6_226:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_226
nop
P4410: !_BLD [22] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_227:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P4411: !_LD [8] (Int) (LE)
wr %g0, 0x88, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduwa [%i2 + 0] %asi, %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4412: !_LD [29] (Int) (Loop exit) (Branch target of P4183)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 4], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_6_227:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_227
nop
ba P4413
nop
TARGET4183:
ba RET4183
nop
P4413: !_DWLD [4] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_228:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 4
sethi %hi(0xc0000), %l3
sub %i1, %l3, %i1
ldd [%i1 + 0], %f0
! 2 addresses covered
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
!--
sethi %hi(0xc0000), %l6
add %i1, %l6, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_6_228:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_228
nop
P4414: !_LD [23] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_229:
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4415: !_LD [29] (Int) (Loop exit)
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 4], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_6_229:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_229
nop
P4416: !_DWLD [28] (Int) (Loop entry) (Loop exit) (CBR)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_230:
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
ldx [%i2 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET4416
nop
RET4416:
! lfsr step begin
srlx %l0, 1, %l7
xnor %l7, %l0, %l7
sllx %l7, 63, %l7
or %l7, %l0, %l0
srlx %l0, 1, %l0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_6_230:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_230
nop
P4417: !_LD [28] (Int) (Loop entry) (LE)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_231:
wr %g0, 0x88, %asi
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduwa [%i3 + 0] %asi, %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4418: !_DWLD [7] (Int) (Loop exit)
ldx [%i1 + 32], %l3
! move %l3(upper) -> %o0(lower)
srlx %l3, 32, %o5
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_6_231:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_231
nop
P4419: !_LD [14] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_232:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4420: !_LD [28] (Int) (Loop exit) (LE)
wr %g0, 0x88, %asi
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduwa [%i3 + 0] %asi, %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_6_232:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_232
nop
P4421: !_BLD [29] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_233:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_6_233:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_233
nop
P4422: !_DWLD [5] (Int) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_234:
ldx [%i1 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_6_234:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_234
nop
P4423: !_DWLD [20] (Int) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_235:
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_6_235:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_235
nop
P4424: !_BLD [31] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_236:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_6_236:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_236
nop
P4425: !_LD [11] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_237:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4426: !_LD [4] (Int) (Loop exit)
lduw [%i1 + 0], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_6_237:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_237
nop
P4427: !_BLD [18] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_238:
wr %g0, 0xf0, %asi
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_6_238:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_238
nop
P4428: !_CAS [30] (maybe <- 0x300001b) (Int) (Loop entry) (Branch target of P4561)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_239:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i3
sub %i0, %i3, %i3
add %i3, 12, %o5
lduw [%o5], %o0
mov %o0, %l7
! move %l7(lower) -> %o0(upper)
sllx %l7, 32, %o0
mov %l4, %l6
cas [%o5], %l7, %l6
! move %l6(lower) -> %o0(lower)
srl %l6, 0, %l7
or %l7, %o0, %o0
add %l4, 1, %l4
ba P4429
nop
TARGET4561:
ba RET4561
nop
P4429: !_BLD [18] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_6_239:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_239
nop
P4430: !_DWLD [4] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_240:
ldx [%i1 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
P4431: !_DWLD [14] (Int) (CBR)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 8], %o1
! move %o1(lower) -> %o1(upper)
sllx %o1, 32, %o1
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET4431
nop
RET4431:
! lfsr step begin
srlx %l0, 1, %l6
xnor %l6, %l0, %l6
sllx %l6, 63, %l6
or %l6, %l0, %l0
srlx %l0, 1, %l0
P4432: !_LD [17] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %o5
! move %o5(lower) -> %o1(lower)
or %o5, %o1, %o1
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_6_240:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_240
nop
P4433: !_DWLD [24] (Int) (Loop entry) (Loop exit) (Branch target of P4135)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_241:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_6_241:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_241
nop
ba P4434
nop
TARGET4135:
ba RET4135
nop
P4434: !_DWLD [14] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_242:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4435: !_LD [27] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_6_242:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_242
nop
P4436: !_BLD [18] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_243:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_6_243:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_243
nop
P4437: !_LD [23] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_244:
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4438: !_DWLD [4] (FP)
ldd [%i1 + 0], %f0
! 2 addresses covered
P4439: !_LD [11] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 32], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
!--
loop_exit_6_244:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_244
nop
P4440: !_DWLD [1] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_245:
ldx [%i0 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
P4441: !_BLD [11] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_6_245:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_245
nop
P4442: !_DWLD [15] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_246:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 32], %o0
! move %o0(upper) -> %o0(upper)
P4443: !_DWST [8] (maybe <- 0x300001c) (Int)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i3
sub %i0, %i3, %i3
sllx %l4, 32, %l7
add %l4, 1, %l4
or %l7, %l4, %l7
stx %l7, [%i3 + 0]
add %l4, 1, %l4
P4444: !_LD [16] (Int) (Loop exit) (Branch target of P4348)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 0], %l7
! move %l7(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_6_246:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_246
nop
ba P4445
nop
TARGET4348:
ba RET4348
nop
P4445: !_DWLD [22] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_247:
sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
ldd [%i3 + 8], %f0
! 1 addresses covered
fmovs %f1, %f0
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
loop_exit_6_247:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_247
nop
P4446: !_BLD [30] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_248:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_6_248:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_248
nop
P4447: !_DWLD [15] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_249:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 32], %o0
! move %o0(upper) -> %o0(upper)
P4448: !_BLD [24] (FP)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P4449: !_LD [5] (Int) (Loop exit) (CBR)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 5
sethi %hi(0xc0000), %l7
sub %i1, %l7, %i1
lduw [%i1 + 4], %l3
! move %l3(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %l3, %o0, %o0
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET4449
nop
RET4449:
! lfsr step begin
srlx %l0, 1, %l6
xnor %l6, %l0, %l6
sllx %l6, 63, %l6
or %l6, %l0, %l0
srlx %l0, 1, %l0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
sethi %hi(0xc0000), %l7
add %i1, %l7, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_6_249:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_249
nop
P4450: !_LD [31] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_250:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4451: !_LD [14] (Int) (Loop exit)
sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 12], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_6_250:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_250
nop
P4452: !_BLD [4] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_251:
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_6_251:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_251
nop
P4453: !_DWLD [26] (Int) (Loop entry) (CBR)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_252:
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
ldx [%i3 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET4453
nop
RET4453:
! lfsr step begin
srlx %l0, 1, %l6
xnor %l6, %l0, %l6
sllx %l6, 63, %l6
or %l6, %l0, %l0
srlx %l0, 1, %l0
P4454: !_LD [12] (Int) (Loop exit)
sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 0], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_6_252:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_252
nop
P4455: !_LD [24] (Int) (Loop entry) (CBR)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_253:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET4455
nop
RET4455:
! lfsr step begin
srlx %l0, 1, %l3
xnor %l3, %l0, %l3
sllx %l3, 63, %l3
or %l3, %l0, %l0
srlx %l0, 1, %l0
P4456: !_LD [24] (Int) (Loop exit)
lduw [%i3 + 0], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_6_253:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_253
nop
P4457: !_CASX [13] (maybe <- 0x300001e) (Int) (Loop entry) (Loop exit) (CBR)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_254:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i2
sub %i0, %i2, %i2
ldx [%i2], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
mov %o0, %l6
sllx %l4, 32, %o1
add %l4, 1, %l4
or %l4, %o1, %o1
casx [%i2], %l6, %o1
! move %o1(upper) -> %o1(upper)
! move %o1(lower) -> %o1(lower)
add %l4, 1, %l4
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET4457
nop
RET4457:
! lfsr step begin
srlx %l0, 1, %l6
xnor %l6, %l0, %l6
sllx %l6, 63, %l6
or %l6, %l0, %l0
srlx %l0, 1, %l0
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_6_254:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_254
nop
P4458: !_DWLD [1] (Int) (Loop entry) (Loop exit) (CBR)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_255:
ldx [%i0 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET4458
nop
RET4458:
! lfsr step begin
srlx %l0, 1, %l6
xnor %l6, %l0, %l6
sllx %l6, 63, %l6
or %l6, %l0, %l0
srlx %l0, 1, %l0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_6_255:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_255
nop
P4459: !_LD [5] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_256:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 5
sethi %hi(0xc0000), %o5
sub %i1, %o5, %i1
lduw [%i1 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4460: !_LD [5] (Int) (Loop exit)
lduw [%i1 + 4], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
sethi %hi(0xc0000), %l3
add %i1, %l3, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_6_256:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_256
nop
P4461: !_BLD [18] (FP) (Loop entry) (Loop exit) (Branch target of P4453)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_257:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_6_257:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_257
nop
ba P4462
nop
TARGET4453:
ba RET4453
nop
P4462: !_BLD [26] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_258:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_6_258:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_258
nop
P4463: !_BLD [30] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_259:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P4464: !_LD [29] (Int)
lduw [%i3 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4465: !_LD [28] (Int) (Loop exit)
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 0], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_6_259:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_259
nop
P4466: !_BLD [8] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_260:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P4467: !_DWLD [23] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 32], %o0
! move %o0(upper) -> %o0(upper)
P4468: !_LD [16] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %o5
! move %o5(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_6_260:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_260
nop
P4469: !_DWLD [1] (Int) (Loop entry) (CBR)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_261:
ldx [%i0 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET4469
nop
RET4469:
! lfsr step begin
srlx %l0, 1, %l3
xnor %l3, %l0, %l3
sllx %l3, 63, %l3
or %l3, %l0, %l0
srlx %l0, 1, %l0
P4470: !_BLD [18] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_6_261:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_261
nop
P4471: !_BLD [6] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_262:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 6
sethi %hi(0xc0000), %l7
sub %i1, %l7, %i1
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
sethi %hi(0xc0000), %o5
add %i1, %o5, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_6_262:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_262
nop
P4472: !_BLD [13] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_263:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P4473: !_BLD [20] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f32
membar #Sync
! 4 addresses covered
fmovd %f32, %f4
fmovd %f34, %f18
fmovs %f19, %f6
fmovd %f40, %f18
fmovs %f18, %f7
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovd %f4, %f30
fmovd %f6, %f30
!--
loop_exit_6_263:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_263
nop
P4474: !_LD [16] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_264:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4475: !_LD [4] (Int) (Loop exit) (LE)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 4
sethi %hi(0xc0000), %l3
sub %i1, %l3, %i1
wr %g0, 0x88, %asi
lduwa [%i1 + 0] %asi, %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
sethi %hi(0xc0000), %o5
add %i1, %o5, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_6_264:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_264
nop
P4476: !_LD [8] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_265:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4477: !_BLD [26] (FP)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P4478: !_LD [5] (Int) (Loop exit)
lduw [%i1 + 4], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_6_265:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_265
nop
P4479: !_BLD [9] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_266:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_6_266:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_266
nop
P4480: !_BLD [15] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_267:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_6_267:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_267
nop
P4481: !_LD [31] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_268:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4482: !_LD [19] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_6_268:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_268
nop
P4483: !_DWLD [0] (Int) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_269:
ldx [%i0 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_6_269:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_269
nop
P4484: !_BLD [21] (FP) (Loop entry) (Loop exit) (Branch target of P4165)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_270:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_6_270:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_270
nop
ba P4485
nop
TARGET4165:
ba RET4165
nop
P4485: !_DWLD [10] (Int) (Loop entry) (Branch target of P3999)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_271:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
ba P4486
nop
TARGET3999:
ba RET3999
nop
P4486: !_DWLD [0] (Int)
ldx [%i0 + 0], %l3
! move %l3(upper) -> %o0(lower)
srlx %l3, 32, %o5
or %o5, %o0, %o0
! move %l3(lower) -> %o1(upper)
sllx %l3, 32, %o1
P4487: !_LD [13] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %o5
! move %o5(lower) -> %o1(lower)
or %o5, %o1, %o1
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_6_271:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_271
nop
P4488: !_BLD [28] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_272:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P4489: !_DWLD [1] (Int) (Loop exit)
ldx [%i0 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_6_272:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_272
nop
P4490: !_BLD [26] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_273:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_6_273:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_273
nop
P4491: !_DWLD [7] (Int) (Loop entry) (LE)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_274:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 7
sethi %hi(0xc0000), %l7
sub %i1, %l7, %i1
wr %g0, 0x88, %asi
ldxa [%i1 + 32] %asi, %l3
! move %l3(lower) -> %o0(upper)
sllx %l3, 32, %o0
P4492: !_LD [25] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 4], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
sethi %hi(0xc0000), %o5
add %i1, %o5, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_6_274:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_274
nop
P4493: !_DWLD [6] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_275:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 6
sethi %hi(0xc0000), %l3
sub %i1, %l3, %i1
ldx [%i1 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4494: !_LD [4] (Int) (Loop exit)
lduw [%i1 + 0], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
sethi %hi(0xc0000), %l6
add %i1, %l6, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_6_275:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_275
nop
P4495: !_CASX [24] (maybe <- 0x3000020) (Int) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_276:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i2
sub %i0, %i2, %i2
ldx [%i2], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
mov %o0, %o5
sllx %l4, 32, %o1
add %l4, 1, %l4
or %l4, %o1, %o1
casx [%i2], %o5, %o1
! move %o1(upper) -> %o1(upper)
! move %o1(lower) -> %o1(lower)
add %l4, 1, %l4
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_6_276:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_276
nop
P4496: !_BSTC [18] (maybe <- 0x42800022) (FP) (Loop entry) (Loop exit) (Branch target of P4345)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_277:
wr %g0, 0xe0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i3
sub %i0, %i3, %i3
! preparing store val #0, next val will be in f32
fmovs %f16, %f20
fadds %f16, %f17, %f16
! preparing store val #1, next val will be in f33
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #2, next val will be in f35
fmovd %f20, %f32
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #3, next val will be in f40
fmovd %f20, %f34
fmovs %f16, %f20
fadds %f16, %f17, %f16
fmovd %f20, %f40
membar #Sync
stda %f32, [%i3 + 0 ] %asi
membar #Sync
loop_exit_6_277:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_277
nop
ba P4497
nop
TARGET4345:
ba RET4345
nop
P4497: !_BLD [3] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_278:
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i0 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_6_278:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_278
nop
P4498: !_DWLD [3] (Int) (Loop entry) (LE)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_279:
wr %g0, 0x88, %asi
ldxa [%i0 + 32] %asi, %o5
! move %o5(lower) -> %o0(upper)
sllx %o5, 32, %o0
P4499: !_BLD [13] (FP)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P4500: !_LD [23] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_6_279:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_279
nop
P4501: !_SWAP [10] (maybe <- 0x3000022) (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_280:
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
mov %l4, %o0
swap [%i2 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
add %l4, 1, %l4
P4502: !_LD [12] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_6_280:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_280
nop
P4503: !_DWLD [5] (Int) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_281:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 5
sethi %hi(0xc0000), %o5
sub %i1, %o5, %i1
ldx [%i1 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
sethi %hi(0xc0000), %l7
add %i1, %l7, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_6_281:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_281
nop
P4504: !_DWLD [1] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_282:
ldx [%i0 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
P4505: !_DWLD [5] (Int) (Loop exit)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 5
sethi %hi(0xc0000), %l6
sub %i1, %l6, %i1
ldx [%i1 + 0], %o1
! move %o1(upper) -> %o1(upper)
! move %o1(lower) -> %o1(lower)
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
sethi %hi(0xc0000), %l3
add %i1, %l3, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_6_282:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_282
nop
P4506: !_BLD [7] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_283:
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P4507: !_REPLACEMENT [16] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS2_O), %i2
sub %i0, %i2, %i2
sethi %hi(0x10000), %l7
ld [%i2+0], %l3
st %l3, [%i2+0]
add %i2, %l7, %o5
ld [%o5+0], %l3
st %l3, [%o5+0]
add %o5, %l7, %o5
ld [%o5+0], %l3
st %l3, [%o5+0]
add %o5, %l7, %o5
ld [%o5+0], %l3
st %l3, [%o5+0]
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_6_283:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_283
nop
P4508: !_BLD [4] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_284:
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_6_284:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_284
nop
P4509: !_DWLD [4] (Int) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_285:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 4
sethi %hi(0xc0000), %o5
sub %i1, %o5, %i1
ldx [%i1 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
sethi %hi(0xc0000), %l7
add %i1, %l7, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_6_285:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_285
nop
P4510: !_DWLD [21] (Int) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_286:
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_6_286:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_286
nop
P4511: !_LD [2] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_287:
lduw [%i0 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4512: !_LD [17] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_6_287:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_287
nop
P4513: !_LD [25] (Int) (Loop entry) (CBR)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_288:
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET4513
nop
RET4513:
! lfsr step begin
srlx %l0, 1, %o5
xnor %o5, %l0, %o5
sllx %o5, 63, %o5
or %o5, %l0, %l0
srlx %l0, 1, %l0
P4514: !_LD [9] (Int) (Loop exit)
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 4], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_6_288:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_288
nop
P4515: !_BLD [31] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_289:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_6_289:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_289
nop
P4516: !_DWLD [7] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_290:
ldd [%i1 + 32], %f0
! 1 addresses covered
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
loop_exit_6_290:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_290
nop
P4517: !_LD [6] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_291:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 6
sethi %hi(0xc0000), %l7
sub %i1, %l7, %i1
lduw [%i1 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4518: !_BLD [25] (FP)
wr %g0, 0xf0, %asi
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P4519: !_LD [26] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
sethi %hi(0xc0000), %l3
add %i1, %l3, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_6_291:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_291
nop
P4520: !_BLD [16] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_292:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P4521: !_DWLD [22] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4522: !_LD [21] (Int) (Loop exit)
lduw [%i3 + 4], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_6_292:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_292
nop
P4523: !_DWLD [9] (Int) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_293:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_6_293:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_293
nop
P4524: !_DWLD [16] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_294:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
P4525: !_CASX [21] (maybe <- 0x3000023) (Int) (Loop exit)
sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
ldx [%i2], %o1
! move %o1(upper) -> %o1(upper)
! move %o1(lower) -> %o1(lower)
mov %o1, %l7
sllx %l4, 32, %o2
add %l4, 1, %l4
or %l4, %o2, %o2
casx [%i2], %l7, %o2
! move %o2(upper) -> %o2(upper)
! move %o2(lower) -> %o2(lower)
add %l4, 1, %l4
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
mov %o2, %l5
loop_exit_6_294:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_294
nop
P4526: !_BLD [29] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_295:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_6_295:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_295
nop
P4527: !_LD [7] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_296:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 7
sethi %hi(0xc0000), %l3
sub %i1, %l3, %i1
ld [%i1 + 32], %f0
! 1 addresses covered
P4528: !_SWAP [18] (maybe <- 0x3000025) (Int)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i2
sub %i0, %i2, %i2
mov %l4, %o0
swap [%i2 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
add %l4, 1, %l4
P4529: !_LD [17] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 4], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
sethi %hi(0xc0000), %o5
add %i1, %o5, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_6_296:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_296
nop
P4530: !_DWLD [5] (Int) (Loop entry) (Loop exit) (CBR)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_297:
ldx [%i1 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET4530
nop
RET4530:
! lfsr step begin
srlx %l0, 1, %l7
xnor %l7, %l0, %l7
sllx %l7, 63, %l7
or %l7, %l0, %l0
srlx %l0, 1, %l0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_6_297:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_297
nop
P4531: !_LD [27] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_298:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4532: !_LD [16] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_6_298:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_298
nop
P4533: !_LD [4] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_299:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 4
sethi %hi(0xc0000), %l7
sub %i1, %l7, %i1
ld [%i1 + 0], %f0
! 1 addresses covered
P4534: !_LD [27] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4535: !_LD [9] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 4], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
sethi %hi(0xc0000), %l3
add %i1, %l3, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_6_299:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_299
nop
P4536: !_FLUSHI [13] (Int) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_300:
flush %g0
loop_exit_6_300:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_300
nop
P4537: !_LD [29] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_301:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4538: !_LD [13] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 4], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_6_301:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_301
nop
P4539: !_BLD [17] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_302:
wr %g0, 0xf0, %asi
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P4540: !_LD [0] (Int)
lduw [%i0 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4541: !_LD [5] (Int) (Loop exit)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 5
sethi %hi(0xc0000), %o5
sub %i1, %o5, %i1
lduw [%i1 + 4], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
sethi %hi(0xc0000), %l7
add %i1, %l7, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_6_302:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_302
nop
P4542: !_DWLD [20] (Int) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_303:
sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
ldx [%i3 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_6_303:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_303
nop
P4543: !_LD [27] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_304:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i2
sub %i0, %i2, %i2
ld [%i2 + 32], %f0
! 1 addresses covered
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
loop_exit_6_304:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_304
nop
P4544: !_DWLD [10] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_305:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4545: !_DWLD [14] (Int) (Loop exit)
sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
ldx [%i2 + 8], %l3
! move %l3(lower) -> %o0(lower)
srl %l3, 0, %o5
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_6_305:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_305
nop
P4546: !_DWLD [15] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_306:
sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
ldx [%i3 + 32], %o0
! move %o0(upper) -> %o0(upper)
P4547: !_BLD [13] (FP)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P4548: !_LD [11] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %l7
! move %l7(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_6_306:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_306
nop
P4549: !_DWLD [31] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_307:
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
ldd [%i2 + 32], %f0
! 1 addresses covered
P4550: !_DWLD [13] (Int) (Loop exit) (CBR)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET4550
nop
RET4550:
! lfsr step begin
srlx %l0, 1, %o5
xnor %o5, %l0, %o5
sllx %o5, 63, %o5
or %o5, %l0, %l0
srlx %l0, 1, %l0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
loop_exit_6_307:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_307
nop
P4551: !_DWLD [6] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_308:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 6
sethi %hi(0xc0000), %l6
sub %i1, %l6, %i1
ldx [%i1 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4552: !_BLD [30] (FP) (Branch target of P4530)
wr %g0, 0xf0, %asi
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
ba P4553
nop
TARGET4530:
ba RET4530
nop
P4553: !_LD [8] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
sethi %hi(0xc0000), %o5
add %i1, %o5, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_6_308:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_308
nop
P4554: !_BLD [30] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_309:
wr %g0, 0xf0, %asi
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_6_309:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_309
nop
P4555: !_DWLD [5] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_310:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 5
sethi %hi(0xc0000), %l6
sub %i1, %l6, %i1
ldx [%i1 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
P4556: !_DWLD [6] (FP) (Loop exit)
ldd [%i1 + 8], %f0
! 1 addresses covered
fmovs %f1, %f0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
sethi %hi(0xc0000), %l3
add %i1, %l3, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_6_310:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_310
nop
P4557: !_LD [29] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_311:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4558: !_LD [26] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_6_311:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_311
nop
P4559: !_LD [7] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_312:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 7
sethi %hi(0xc0000), %o5
sub %i1, %o5, %i1
lduw [%i1 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4560: !_BLD [8] (FP)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P4561: !_LD [16] (Int) (Loop exit) (CBR)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 0], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET4561
nop
RET4561:
! lfsr step begin
srlx %l0, 1, %l6
xnor %l6, %l0, %l6
sllx %l6, 63, %l6
or %l6, %l0, %l0
srlx %l0, 1, %l0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
sethi %hi(0xc0000), %l7
add %i1, %l7, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_6_312:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_312
nop
P4562: !_LD [30] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_313:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4563: !_LD [31] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 32], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_6_313:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_313
nop
P4564: !_LD [21] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_314:
sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4565: !_SWAP [20] (maybe <- 0x3000026) (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i2
sub %i0, %i2, %i2
mov %l4, %l7
swap [%i2 + 0], %l7
! move %l7(lower) -> %o0(lower)
srl %l7, 0, %l3
or %l3, %o0, %o0
add %l4, 1, %l4
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_6_314:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_314
nop
P4566: !_LD [2] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_315:
lduw [%i0 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4567: !_LD [19] (Int) (Loop exit) (CBR)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET4567
nop
RET4567:
! lfsr step begin
srlx %l0, 1, %l6
xnor %l6, %l0, %l6
sllx %l6, 63, %l6
or %l6, %l0, %l0
srlx %l0, 1, %l0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_6_315:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_315
nop
P4568: !_LD [28] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_316:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4569: !_CAS [15] (maybe <- 0x3000027) (Int) (Branch target of P4263)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i3
sub %i0, %i3, %i3
add %i3, 32, %o5
lduw [%o5], %l6
mov %l6, %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
mov %l4, %o1
cas [%o5], %l7, %o1
! move %o1(lower) -> %o1(upper)
sllx %o1, 32, %o1
add %l4, 1, %l4
ba P4570
nop
TARGET4263:
ba RET4263
nop
P4570: !_LD [15] (Int) (Loop exit)
lduw [%i3 + 32], %o5
! move %o5(lower) -> %o1(lower)
or %o5, %o1, %o1
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_6_316:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_316
nop
P4571: !_DWLD [16] (Int) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_317:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_6_317:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_317
nop
P4572: !_BLD [13] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_318:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P4573: !_BLD [1] (FP) (Loop exit)
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i0 + 0] %asi, %f32
membar #Sync
! 4 addresses covered
fmovd %f32, %f4
fmovd %f34, %f18
fmovs %f19, %f6
fmovd %f40, %f18
fmovs %f18, %f7
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovd %f4, %f30
fmovd %f6, %f30
!--
loop_exit_6_318:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_318
nop
P4574: !_LD [27] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_319:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4575: !_DWLD [2] (Int) (Loop exit)
ldx [%i0 + 8], %o5
! move %o5(lower) -> %o0(lower)
srl %o5, 0, %l7
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_6_319:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_319
nop
P4576: !_LD [30] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_320:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4577: !_BLD [18] (FP)
wr %g0, 0xf0, %asi
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P4578: !_LD [23] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_6_320:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_320
nop
P4579: !_BLD [29] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_321:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P4580: !_BLD [21] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f32
membar #Sync
! 4 addresses covered
fmovd %f32, %f4
fmovd %f34, %f18
fmovs %f19, %f6
fmovd %f40, %f18
fmovs %f18, %f7
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovd %f4, %f30
fmovd %f6, %f30
!--
loop_exit_6_321:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_321
nop
P4581: !_DWLD [26] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_322:
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
ldx [%i2 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4582: !_DWLD [17] (Int)
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
ldx [%i3 + 0], %l6
! move %l6(upper) -> %o0(lower)
srlx %l6, 32, %l3
or %l3, %o0, %o0
! move %l6(lower) -> %o1(upper)
sllx %l6, 32, %o1
P4583: !_LD [23] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 32], %l3
! move %l3(lower) -> %o1(lower)
or %l3, %o1, %o1
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_6_322:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_322
nop
P4584: !_LD [1] (Int) (Loop entry) (LE)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_323:
wr %g0, 0x88, %asi
lduwa [%i0 + 4] %asi, %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4585: !_DWLD [22] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 8], %l7
! move %l7(lower) -> %o0(lower)
srl %l7, 0, %l6
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_6_323:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_323
nop
P4586: !_LD [8] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_324:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4587: !_SWAP [20] (maybe <- 0x3000028) (Int) (Loop exit)
sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
mov %l4, %l6
swap [%i3 + 0], %l6
! move %l6(lower) -> %o0(lower)
srl %l6, 0, %o5
or %o5, %o0, %o0
add %l4, 1, %l4
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_6_324:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_324
nop
P4588: !_DWLD [29] (Int) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_325:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_6_325:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_325
nop
P4589: !_BLD [17] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_326:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P4590: !_LD [25] (Int)
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4591: !_LD [28] (Int) (Loop exit)
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 0], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_6_326:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_326
nop
P4592: !_DWLD [15] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_327:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 32], %o0
! move %o0(upper) -> %o0(upper)
P4593: !_LD [30] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %l6
! move %l6(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_6_327:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_327
nop
P4594: !_LD [18] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_328:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4595: !_LD [30] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_6_328:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_328
nop
P4596: !_LD [13] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_329:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4597: !_DWLD [12] (FP)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i3
sub %i0, %i3, %i3
ldd [%i3 + 0], %f0
! 2 addresses covered
P4598: !_LD [11] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 32], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
!--
loop_exit_6_329:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_329
nop
P4599: !_NOP (Int) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_330:
nop
loop_exit_6_330:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_330
nop
P4600: !_DWLD [4] (Int) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_331:
ldx [%i1 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_6_331:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_331
nop
P4601: !_LD [26] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_332:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4602: !_DWLD [18] (Int) (Loop exit) (CBR) (Branch target of P4457)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 8], %l3
! move %l3(lower) -> %o0(lower)
srl %l3, 0, %o5
or %o5, %o0, %o0
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET4602
nop
RET4602:
! lfsr step begin
srlx %l0, 1, %l6
xnor %l6, %l0, %l6
sllx %l6, 63, %l6
or %l6, %l0, %l0
srlx %l0, 1, %l0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_6_332:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_332
nop
ba P4603
nop
TARGET4457:
ba RET4457
nop
P4603: !_BLD [28] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_333:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_6_333:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_333
nop
P4604: !_DWLD [16] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_334:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
P4605: !_LD [31] (Int)
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 32], %o1
! move %o1(lower) -> %o1(upper)
sllx %o1, 32, %o1
P4606: !_LD [14] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %o5
! move %o5(lower) -> %o1(lower)
or %o5, %o1, %o1
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_6_334:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_334
nop
P4607: !_LD [11] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_335:
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4608: !_LD [17] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_6_335:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_335
nop
P4609: !_LD [18] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_336:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4610: !_LD [17] (Int) (Loop exit)
lduw [%i3 + 4], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_6_336:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_336
nop
P4611: !_BSTC [18] (maybe <- 0x42800026) (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_337:
wr %g0, 0xe0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i2
sub %i0, %i2, %i2
! preparing store val #0, next val will be in f32
fmovs %f16, %f20
fadds %f16, %f17, %f16
! preparing store val #1, next val will be in f33
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #2, next val will be in f35
fmovd %f20, %f32
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #3, next val will be in f40
fmovd %f20, %f34
fmovs %f16, %f20
fadds %f16, %f17, %f16
fmovd %f20, %f40
membar #Sync
stda %f32, [%i2 + 0 ] %asi
membar #Sync
P4612: !_DWLD [1] (Int) (Loop exit)
ldx [%i0 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_6_337:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_337
nop
P4613: !_LD [3] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_338:
lduw [%i0 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4614: !_LD [26] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_6_338:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_338
nop
P4615: !_LD [25] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_339:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4616: !_LD [20] (Int) (Loop exit)
sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 0], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_6_339:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_339
nop
P4617: !_BLD [21] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_340:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P4618: !_DWLD [15] (Int) (CBR)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 32], %o0
! move %o0(upper) -> %o0(upper)
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET4618
nop
RET4618:
! lfsr step begin
srlx %l0, 1, %o5
xnor %o5, %l0, %o5
sllx %o5, 63, %o5
or %o5, %l0, %l0
srlx %l0, 1, %l0
P4619: !_LD [11] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 32], %l7
! move %l7(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_6_340:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_340
nop
P4620: !_BLD [11] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_341:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_6_341:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_341
nop
P4621: !_DWLD [2] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_342:
ldx [%i0 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4622: !_BLD [4] (FP)
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P4623: !_LD [24] (Int) (Loop exit) (Branch target of P4354)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 0], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_6_342:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_342
nop
ba P4624
nop
TARGET4354:
ba RET4354
nop
P4624: !_LD [18] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_343:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4625: !_DWLD [25] (Int)
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
ldx [%i2 + 0], %l3
! move %l3(upper) -> %o0(lower)
srlx %l3, 32, %o5
or %o5, %o0, %o0
! move %l3(lower) -> %o1(upper)
sllx %l3, 32, %o1
P4626: !_LD [26] (Int) (Loop exit)
lduw [%i2 + 12], %l7
! move %l7(lower) -> %o1(lower)
or %l7, %o1, %o1
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_6_343:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_343
nop
P4627: !_NOP (Int) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_344:
nop
loop_exit_6_344:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_344
nop
P4628: !_CAS [27] (maybe <- 0x3000029) (Int) (Loop entry) (Loop exit) (Branch target of P4181)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_345:
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
add %i3, 32, %o5
lduw [%o5], %o0
mov %o0, %l7
! move %l7(lower) -> %o0(upper)
sllx %l7, 32, %o0
mov %l4, %l6
cas [%o5], %l7, %l6
! move %l6(lower) -> %o0(lower)
srl %l6, 0, %l7
or %l7, %o0, %o0
add %l4, 1, %l4
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_6_345:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_345
nop
ba P4629
nop
TARGET4181:
ba RET4181
nop
P4629: !_DWLD [4] (Int) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_346:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 4
sethi %hi(0xc0000), %o5
sub %i1, %o5, %i1
ldx [%i1 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
sethi %hi(0xc0000), %l7
add %i1, %l7, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_6_346:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_346
nop
P4630: !_CAS [17] (maybe <- 0x300002a) (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_347:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i2
sub %i0, %i2, %i2
add %i2, 4, %l3
lduw [%l3], %o0
mov %o0, %o5
! move %o5(lower) -> %o0(upper)
sllx %o5, 32, %o0
mov %l4, %l7
cas [%l3], %o5, %l7
! move %l7(lower) -> %o0(lower)
srl %l7, 0, %o5
or %o5, %o0, %o0
add %l4, 1, %l4
P4631: !_BLD [17] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_6_347:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_347
nop
P4632: !_BLD [11] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_348:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P4633: !_BLD [26] (FP) (Loop exit) (Branch target of P4033)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f32
membar #Sync
! 4 addresses covered
fmovd %f32, %f4
fmovd %f34, %f18
fmovs %f19, %f6
fmovd %f40, %f18
fmovs %f18, %f7
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovd %f4, %f30
fmovd %f6, %f30
!--
loop_exit_6_348:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_348
nop
ba P4634
nop
TARGET4033:
ba RET4033
nop
P4634: !_REPLACEMENT [23] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_349:
sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS3_O), %i2
sub %i0, %i2, %i2
sethi %hi(0x10000), %o5
ld [%i2+32], %l6
st %l6, [%i2+32]
add %i2, %o5, %l3
ld [%l3+32], %l6
st %l6, [%l3+32]
add %l3, %o5, %l3
ld [%l3+32], %l6
st %l6, [%l3+32]
add %l3, %o5, %l3
ld [%l3+32], %l6
st %l6, [%l3+32]
P4635: !_BLD [21] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_6_349:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_349
nop
P4636: !_LD [5] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_350:
lduw [%i1 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4637: !_LD [15] (Int) (Loop exit)
sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 32], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_6_350:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_350
nop
P4638: !_BLD [18] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_351:
wr %g0, 0xf0, %asi
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_6_351:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_351
nop
P4639: !_PREFETCH [9] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_352:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
sub %i0, %i2, %i2
prefetch [%i2 + 4], 1
P4640: !_DWLD [8] (Int) (Loop exit)
ldx [%i2 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_6_352:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_352
nop
P4641: !_BLD [15] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_353:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_6_353:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_353
nop
P4642: !_LD [1] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_354:
lduw [%i0 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4643: !_DWLD [25] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 0], %l6
! move %l6(upper) -> %o0(lower)
srlx %l6, 32, %l3
or %l3, %o0, %o0
! move %l6(lower) -> %o1(upper)
sllx %l6, 32, %o1
P4644: !_LD [26] (Int) (Loop exit)
lduw [%i2 + 12], %o5
! move %o5(lower) -> %o1(lower)
or %o5, %o1, %o1
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_6_354:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_354
nop
P4645: !_DWLD [2] (Int) (Loop entry) (Branch target of P4337)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_355:
ldx [%i0 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
ba P4646
nop
TARGET4337:
ba RET4337
nop
P4646: !_LD [2] (Int) (Loop exit)
lduw [%i0 + 12], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_6_355:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_355
nop
P4647: !_BLD [13] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_356:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P4648: !_LD [1] (Int)
lduw [%i0 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4649: !_LD [27] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 32], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_6_356:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_356
nop
P4650: !_CASX [2] (maybe <- 0x300002b) (Int) (Loop entry) (Loop exit) (LE)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_357:
! Change single-word-level endianess (big endian <-> little endian)
sethi %hi(0xff00ff00), %o5
or %o5, %lo(0xff00ff00), %o5
and %l4, %o5, %l7
srl %l7, 8, %l7
sll %l4, 8, %l3
and %l3, %o5, %l3
or %l3, %l7, %l3
srl %l3, 16, %l7
sll %l3, 16, %l3
srl %l3, 0, %l3
or %l3, %l7, %l3
sllx %l3, 32, %l3
wr %g0, 0x88, %asi
add %i0, 8, %o5
ldxa [%o5] %asi, %l6
! move %l6(lower) -> %o0(upper)
sllx %l6, 32, %o0
! move %l6(upper) -> %o0(lower)
srlx %l6, 32, %l7
or %l7, %o0, %o0
mov %l6, %l7
mov %l3, %l6
casxa [%o5] %asi, %l7, %l6
! move %l6(lower) -> %o1(upper)
sllx %l6, 32, %o1
! move %l6(upper) -> %o1(lower)
srlx %l6, 32, %l7
or %l7, %o1, %o1
add %l4, 1, %l4
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_6_357:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_357
nop
P4651: !_CASX [10] (maybe <- 0x300002c) (Int) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_358:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i3
sub %i0, %i3, %i3
add %i3, 8, %l6
ldx [%l6], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
mov %o0, %l3
mov %l4, %o1
casx [%l6], %l3, %o1
! move %o1(upper) -> %o1(upper)
! move %o1(lower) -> %o1(lower)
add %l4, 1, %l4
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_6_358:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_358
nop
P4652: !_LD [7] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_359:
lduw [%i1 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4653: !_LD [22] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_6_359:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_359
nop
P4654: !_DWLD [10] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_360:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4655: !_LD [5] (Int) (Loop exit)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 5
sethi %hi(0xc0000), %l6
sub %i1, %l6, %i1
lduw [%i1 + 4], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
sethi %hi(0xc0000), %l3
add %i1, %l3, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_6_360:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_360
nop
P4656: !_DWLD [16] (Int) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_361:
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
ldx [%i2 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_6_361:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_361
nop
P4657: !_DWLD [5] (Int) (Loop entry) (Loop exit) (CBR)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_362:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 5
sethi %hi(0xc0000), %l3
sub %i1, %l3, %i1
ldx [%i1 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET4657
nop
RET4657:
! lfsr step begin
srlx %l0, 1, %o5
xnor %o5, %l0, %o5
sllx %o5, 63, %o5
or %o5, %l0, %l0
srlx %l0, 1, %l0
!---- flushing int results buffer----
mov %o0, %l5
sethi %hi(0xc0000), %l3
add %i1, %l3, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_6_362:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_362
nop
P4658: !_DWLD [17] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_6_363:
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
ldx [%i3 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
P4659: !_BLD [8] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_6_363:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_363
nop
P4660: !_BLD [5] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_6_364:
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_6_364:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_6_364
nop
P4661: !_MEMBAR (Int)
membar #StoreLoad
END_NODES6: ! Test instruction sequence for CPU 6 ends
sethi %hi(0xdead0e0f), %o5
or %o5, %lo(0xdead0e0f), %o5
! move %o5(lower) -> %o0(upper)
sllx %o5, 32, %o0
stw %o5, [%i5]
ld [%i5], %f0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
restore
retl
nop
!-----------------
! register usage:
! %i0 %i1 : base registers for first 2 regions
! %i2 %i3 : cache registers for 8 regions
! %i4 fixed pointer to per-cpu results area
! %l1 moving pointer to per-cpu FP results area
! %o7 moving pointer to per-cpu integer results area
! %i5 pointer to per-cpu private area
! %l0 holds lfsr, used as source of random bits
! %l2 loop count register
! %f16 running counter for unique fp store values
! %f17 holds increment value for fp counter
! %l4 running counter for unique integer store values (increment value is always 1)
! %l5 move-to register for load values (simulation only)
! %f30 move-to register for FP values (simulation only)
! %l3 %l6 %l7 %o5 : 4 temporary registers
! %o0 %o1 %o2 %o3 %o4 : 5 integer results buffer registers
! %f0-f15 FP results buffer registers
! %f32-f47 FP block load/store registers
func7:
! 1000 (dynamic) instruction sequence begins
save %sp, -192, %sp
! Force %i0-%i3 to be 64-byte aligned
add %i0, 63, %i0
andn %i0, 63, %i0
add %i1, 63, %i1
andn %i1, 63, %i1
add %i2, 63, %i2
andn %i2, 63, %i2
add %i3, 63, %i3
andn %i3, 63, %i3
add %i4, 63, %i4
andn %i4, 63, %i4
add %i5, 63, %i5
andn %i5, 63, %i5
! Initialize pointer to FP load results area
mov %i4, %l1
! Initialize pointer to integer load results area
sethi %hi(0x80000), %o7
or %o7, %lo(0x80000), %o7
add %o7, %l1, %o7
! Initialize %f0-%f62 to 0xdeadbee0deadbee1
sethi %hi(0xdeadbee0), %l7
or %l7, %lo(0xdeadbee0), %l7
stw %l7, [%i5]
sethi %hi(0xdeadbee1), %l7
or %l7, %lo(0xdeadbee1), %l7
stw %l7, [%i5+4]
ldd [%i5], %f0
fmovd %f0, %f2
fmovd %f0, %f4
fmovd %f0, %f6
fmovd %f0, %f8
fmovd %f0, %f10
fmovd %f0, %f12
fmovd %f0, %f14
fmovd %f0, %f16
fmovd %f0, %f18
fmovd %f0, %f20
fmovd %f0, %f22
fmovd %f0, %f24
fmovd %f0, %f26
fmovd %f0, %f28
fmovd %f0, %f30
fmovd %f0, %f32
fmovd %f0, %f34
fmovd %f0, %f36
fmovd %f0, %f38
fmovd %f0, %f40
fmovd %f0, %f42
fmovd %f0, %f44
fmovd %f0, %f46
fmovd %f0, %f48
fmovd %f0, %f50
fmovd %f0, %f52
fmovd %f0, %f54
fmovd %f0, %f56
fmovd %f0, %f58
fmovd %f0, %f60
fmovd %f0, %f62
! Signature for extract_loads script to start extracting load values for this stream
sethi %hi(0x07deade1), %l7
or %l7, %lo(0x07deade1), %l7
stw %l7, [%i5]
ld [%i5], %f16
! Initialize running integer counter in register %l4
sethi %hi(0x3800001), %l4
or %l4, %lo(0x3800001), %l4
! Initialize running FP counter in register %f16
sethi %hi(0x43000001), %l7
or %l7, %lo(0x43000001), %l7
stw %l7, [%i5]
ld [%i5], %f16
! Initialize FP counter increment value in register %f17 (constant)
sethi %hi(0x37800000), %l7
or %l7, %lo(0x37800000), %l7
stw %l7, [%i5]
ld [%i5], %f17
! Initialize LFSR to 0x4463^4
sethi %hi(0x4463), %l0
or %l0, %lo(0x4463), %l0
mulx %l0, %l0, %l0
mulx %l0, %l0, %l0
BEGIN_NODES7: ! Test instruction sequence for CPU 7 begins
P4662: !_BLD [10] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_0:
wr %g0, 0xf0, %asi
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P4663: !_MEMBAR (Int) (Loop exit)
membar #StoreLoad
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_7_0:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_0
nop
P4664: !_LD [11] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_1:
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
ld [%i2 + 32], %f0
! 1 addresses covered
P4665: !_NOP (Int) (Loop exit)
nop
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
loop_exit_7_1:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_1
nop
P4666: !_DWLD [9] (Int) (Loop entry) (Loop exit) (LE) (CBR)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_2:
wr %g0, 0x88, %asi
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
ldxa [%i3 + 0] %asi, %l6
! move %l6(lower) -> %o0(upper)
sllx %l6, 32, %o0
! move %l6(upper) -> %o0(lower)
srlx %l6, 32, %l3
or %l3, %o0, %o0
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET4666
nop
RET4666:
! lfsr step begin
srlx %l0, 1, %l7
xnor %l7, %l0, %l7
sllx %l7, 63, %l7
or %l7, %l0, %l0
srlx %l0, 1, %l0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_7_2:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_2
nop
P4667: !_LD [11] (Int) (Loop entry) (LE)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_3:
wr %g0, 0x88, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduwa [%i2 + 32] %asi, %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4668: !_BLD [27] (FP) (Branch target of P5239)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
ba P4669
nop
TARGET5239:
ba RET5239
nop
P4669: !_LD [4] (Int) (Loop exit) (LE)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 4
sethi %hi(0xc0000), %o5
sub %i1, %o5, %i1
wr %g0, 0x88, %asi
lduwa [%i1 + 0] %asi, %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
sethi %hi(0xc0000), %l7
add %i1, %l7, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_7_3:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_3
nop
P4670: !_BLD [28] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_4:
wr %g0, 0xf0, %asi
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P4671: !_DWLD [26] (Int)
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
ldx [%i3 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4672: !_LD [29] (Int) (Loop exit)
lduw [%i2 + 4], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_7_4:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_4
nop
P4673: !_PREFETCH [1] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_5:
prefetch [%i0 + 4], 1
P4674: !_LD [14] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4675: !_LD [0] (Int) (Loop exit)
lduw [%i0 + 0], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_7_5:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_5
nop
P4676: !_BLD [17] (FP) (Loop entry) (Loop exit) (CBR)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_6:
wr %g0, 0xf0, %asi
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET4676
nop
RET4676:
! lfsr step begin
srlx %l0, 1, %l3
xnor %l3, %l0, %l3
sllx %l3, 63, %l3
or %l3, %l0, %l0
srlx %l0, 1, %l0
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_7_6:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_6
nop
P4677: !_LD [30] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_7:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4678: !_MEMBAR (Int)
membar #StoreLoad
P4679: !_LD [2] (Int) (Loop exit)
lduw [%i0 + 12], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_7_7:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_7
nop
P4680: !_BLD [7] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_8:
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_7_8:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_8
nop
P4681: !_BSTC [13] (maybe <- 0x43000001) (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_9:
wr %g0, 0xe0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i3
sub %i0, %i3, %i3
! preparing store val #0, next val will be in f32
fmovs %f16, %f20
fadds %f16, %f17, %f16
! preparing store val #1, next val will be in f33
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #2, next val will be in f35
fmovd %f20, %f32
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #3, next val will be in f40
fmovd %f20, %f34
fmovs %f16, %f20
fadds %f16, %f17, %f16
fmovd %f20, %f40
membar #Sync
stda %f32, [%i3 + 0 ] %asi
membar #Sync
P4682: !_DWLD [11] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 32], %o0
! move %o0(upper) -> %o0(upper)
P4683: !_LD [14] (Int) (Loop exit)
sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 12], %l7
! move %l7(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_7_9:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_9
nop
P4684: !_LD [27] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_10:
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
ld [%i2 + 32], %f0
! 1 addresses covered
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
loop_exit_7_10:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_10
nop
P4685: !_BLD [21] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_11:
wr %g0, 0xf0, %asi
sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P4686: !_DWLD [20] (Int) (Loop exit)
ldx [%i3 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_7_11:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_11
nop
P4687: !_BLD [13] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_12:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P4688: !_DWLD [24] (Int) (Loop exit)
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
ldx [%i3 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_7_12:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_12
nop
P4689: !_BLD [14] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_13:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P4690: !_BLD [31] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f32
membar #Sync
! 4 addresses covered
fmovd %f32, %f4
fmovd %f34, %f18
fmovs %f19, %f6
fmovd %f40, %f18
fmovs %f18, %f7
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovd %f4, %f30
fmovd %f6, %f30
!--
loop_exit_7_13:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_13
nop
P4691: !_LD [27] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_14:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4692: !_LD [28] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_7_14:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_14
nop
P4693: !_BLD [9] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_15:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P4694: !_MEMBAR (Int) (Loop exit)
membar #StoreLoad
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_7_15:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_15
nop
P4695: !_DWLD [23] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_16:
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 32], %o0
! move %o0(upper) -> %o0(upper)
P4696: !_LD [15] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 32], %o5
! move %o5(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_7_16:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_16
nop
P4697: !_BLD [5] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_17:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 5
sethi %hi(0xc0000), %l6
sub %i1, %l6, %i1
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
sethi %hi(0xc0000), %l7
add %i1, %l7, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_7_17:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_17
nop
P4698: !_LD [30] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_18:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4699: !_LD [14] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_7_18:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_18
nop
P4700: !_FLUSHI [13] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_19:
flush %g0
P4701: !_CAS [30] (maybe <- 0x3800001) (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i3
sub %i0, %i3, %i3
add %i3, 12, %o5
lduw [%o5], %o0
mov %o0, %l7
! move %l7(lower) -> %o0(upper)
sllx %l7, 32, %o0
mov %l4, %l6
cas [%o5], %l7, %l6
! move %l6(lower) -> %o0(lower)
srl %l6, 0, %l7
or %l7, %o0, %o0
add %l4, 1, %l4
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_7_19:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_19
nop
P4702: !_MEMBAR (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_20:
membar #StoreLoad
P4703: !_LD [12] (Int) (LE)
wr %g0, 0x88, %asi
sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduwa [%i2 + 0] %asi, %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4704: !_LD [25] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 4], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_7_20:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_20
nop
P4705: !_LD [31] (Int) (Loop entry) (Branch target of P5189)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_21:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
ba P4706
nop
TARGET5189:
ba RET5189
nop
P4706: !_LD [11] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_7_21:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_21
nop
P4707: !_DWLD [4] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_22:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 4
sethi %hi(0xc0000), %o5
sub %i1, %o5, %i1
ldd [%i1 + 0], %f0
! 2 addresses covered
P4708: !_LD [6] (Int)
lduw [%i1 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4709: !_LD [13] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
!--
sethi %hi(0xc0000), %l6
add %i1, %l6, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_7_22:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_22
nop
P4710: !_CAS [8] (maybe <- 0x3800002) (Int) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_23:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3], %o0
mov %o0, %l7
! move %l7(lower) -> %o0(upper)
sllx %l7, 32, %o0
mov %l4, %l6
cas [%i3], %l7, %l6
! move %l6(lower) -> %o0(lower)
srl %l6, 0, %l7
or %l7, %o0, %o0
add %l4, 1, %l4
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_7_23:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_23
nop
P4711: !_REPLACEMENT [3] (Int) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_24:
sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS2_O), %i2
sub %i0, %i2, %i2
sethi %hi(0x10000), %l3
ld [%i2+32], %l7
st %l7, [%i2+32]
add %i2, %l3, %l6
ld [%l6+32], %l7
st %l7, [%l6+32]
add %l6, %l3, %l6
ld [%l6+32], %l7
st %l7, [%l6+32]
add %l6, %l3, %l6
ld [%l6+32], %l7
st %l7, [%l6+32]
loop_exit_7_24:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_24
nop
P4712: !_DWLD [17] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_25:
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
ldx [%i3 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
P4713: !_LD [13] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %o1
! move %o1(lower) -> %o1(upper)
sllx %o1, 32, %o1
P4714: !_LD [28] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %l7
! move %l7(lower) -> %o1(lower)
or %l7, %o1, %o1
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_7_25:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_25
nop
P4715: !_DWLD [21] (Int) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_26:
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_7_26:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_26
nop
P4716: !_BLD [3] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_27:
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i0 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P4717: !_DWLD [12] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_7_27:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_27
nop
P4718: !_DWST [23] (maybe <- 0x3800003) (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_28:
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
sub %i0, %i2, %i2
mov %l4, %l3
sllx %l3, 32, %l3
stx %l3, [%i2 + 32 ]
add %l4, 1, %l4
P4719: !_BLD [10] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_7_28:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_28
nop
P4720: !_CAS [25] (maybe <- 0x3800004) (Int) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_29:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
sub %i0, %i2, %i2
add %i2, 4, %l7
lduw [%l7], %o0
mov %o0, %l6
! move %l6(lower) -> %o0(upper)
sllx %l6, 32, %o0
mov %l4, %l3
cas [%l7], %l6, %l3
! move %l3(lower) -> %o0(lower)
srl %l3, 0, %l6
or %l6, %o0, %o0
add %l4, 1, %l4
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_7_29:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_29
nop
P4721: !_BLD [27] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_30:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P4722: !_DWLD [30] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4723: !_LD [17] (Int) (Loop exit) (LE)
wr %g0, 0x88, %asi
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduwa [%i3 + 4] %asi, %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_7_30:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_30
nop
P4724: !_BLD [4] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_31:
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P4725: !_LD [7] (Int)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 7
sethi %hi(0xc0000), %l6
sub %i1, %l6, %i1
lduw [%i1 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4726: !_LD [9] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
sethi %hi(0xc0000), %l7
add %i1, %l7, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_7_31:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_31
nop
P4727: !_LD [10] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_32:
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4728: !_BLD [26] (FP)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P4729: !_LD [19] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_7_32:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_32
nop
P4730: !_BLD [8] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_33:
wr %g0, 0xf0, %asi
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_7_33:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_33
nop
P4731: !_BLD [20] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_34:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P4732: !_BLD [16] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f32
membar #Sync
! 4 addresses covered
fmovd %f32, %f4
fmovd %f34, %f18
fmovs %f19, %f6
fmovd %f40, %f18
fmovs %f18, %f7
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovd %f4, %f30
fmovd %f6, %f30
!--
loop_exit_7_34:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_34
nop
P4733: !_SWAP [13] (maybe <- 0x3800005) (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_35:
sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
mov %l4, %o0
swap [%i3 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
add %l4, 1, %l4
P4734: !_DWLD [13] (Int)
ldx [%i3 + 0], %l7
! move %l7(upper) -> %o0(lower)
srlx %l7, 32, %l6
or %l6, %o0, %o0
! move %l7(lower) -> %o1(upper)
sllx %l7, 32, %o1
P4735: !_LD [15] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 32], %l6
! move %l6(lower) -> %o1(lower)
or %l6, %o1, %o1
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_7_35:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_35
nop
P4736: !_BLD [3] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_36:
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i0 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P4737: !_DWLD [15] (FP) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i3
sub %i0, %i3, %i3
ldd [%i3 + 32], %f4
! 1 addresses covered
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovs %f4, %f30
!--
loop_exit_7_36:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_36
nop
P4738: !_BLD [22] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_37:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_7_37:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_37
nop
P4739: !_DWLD [26] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_38:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4740: !_BLD [14] (FP)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P4741: !_LD [4] (Int) (Loop exit)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 4
sethi %hi(0xc0000), %l6
sub %i1, %l6, %i1
lduw [%i1 + 0], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
sethi %hi(0xc0000), %l3
add %i1, %l3, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_7_38:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_38
nop
P4742: !_BLD [26] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_39:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_7_39:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_39
nop
P4743: !_BLD [30] (FP) (Loop entry) (Loop exit) (Branch target of P5039)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_40:
wr %g0, 0xf0, %asi
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_7_40:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_40
nop
ba P4744
nop
TARGET5039:
ba RET5039
nop
P4744: !_DWLD [14] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_41:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4745: !_DWLD [24] (Int)
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
ldx [%i2 + 0], %l3
! move %l3(upper) -> %o0(lower)
srlx %l3, 32, %o5
or %o5, %o0, %o0
! move %l3(lower) -> %o1(upper)
sllx %l3, 32, %o1
P4746: !_LD [24] (Int) (Loop exit)
lduw [%i2 + 0], %l7
! move %l7(lower) -> %o1(lower)
or %l7, %o1, %o1
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_7_41:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_41
nop
P4747: !_LD [26] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_42:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4748: !_LD [7] (Int) (Loop exit)
lduw [%i1 + 32], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_7_42:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_42
nop
P4749: !_BLD [9] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_43:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P4750: !_DWLD [0] (Int) (Loop exit) (Branch target of P4959)
ldx [%i0 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_7_43:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_43
nop
ba P4751
nop
TARGET4959:
ba RET4959
nop
P4751: !_DWLD [6] (Int) (Loop entry) (CBR)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_44:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 6
sethi %hi(0xc0000), %l7
sub %i1, %l7, %i1
ldx [%i1 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET4751
nop
RET4751:
! lfsr step begin
srlx %l0, 1, %l6
xnor %l6, %l0, %l6
sllx %l6, 63, %l6
or %l6, %l0, %l0
srlx %l0, 1, %l0
P4752: !_LD [23] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
sethi %hi(0xc0000), %l3
add %i1, %l3, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_7_44:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_44
nop
P4753: !_REPLACEMENT [25] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_45:
sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS1_O), %i2
sub %i0, %i2, %i2
sethi %hi(0x10000), %l7
ld [%i2+4], %l3
st %l3, [%i2+4]
add %i2, %l7, %o5
ld [%o5+4], %l3
st %l3, [%o5+4]
add %o5, %l7, %o5
ld [%o5+4], %l3
st %l3, [%o5+4]
add %o5, %l7, %o5
ld [%o5+4], %l3
st %l3, [%o5+4]
P4754: !_BLD [1] (FP) (Loop exit)
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i0 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_7_45:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_45
nop
P4755: !_BLD [28] (FP) (Loop entry) (CBR)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_46:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET4755
nop
RET4755:
! lfsr step begin
srlx %l0, 1, %o5
xnor %o5, %l0, %o5
sllx %o5, 63, %o5
or %o5, %l0, %l0
srlx %l0, 1, %l0
P4756: !_BLD [3] (FP) (Loop exit)
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i0 + 0] %asi, %f32
membar #Sync
! 4 addresses covered
fmovd %f32, %f4
fmovd %f34, %f18
fmovs %f19, %f6
fmovd %f40, %f18
fmovs %f18, %f7
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovd %f4, %f30
fmovd %f6, %f30
!--
loop_exit_7_46:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_46
nop
P4757: !_CAS [13] (maybe <- 0x3800006) (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_47:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i2
sub %i0, %i2, %i2
add %i2, 4, %o5
lduw [%o5], %o0
mov %o0, %l7
! move %l7(lower) -> %o0(upper)
sllx %l7, 32, %o0
mov %l4, %l6
cas [%o5], %l7, %l6
! move %l6(lower) -> %o0(lower)
srl %l6, 0, %l7
or %l7, %o0, %o0
add %l4, 1, %l4
P4758: !_BLD [29] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_7_47:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_47
nop
P4759: !_DWLD [18] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_48:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4760: !_LD [30] (FP)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
sub %i0, %i3, %i3
ld [%i3 + 12], %f0
! 1 addresses covered
P4761: !_LD [28] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 0], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
loop_exit_7_48:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_48
nop
P4762: !_LD [19] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_49:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4763: !_LD [20] (Int) (Loop exit) (LE)
wr %g0, 0x88, %asi
sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduwa [%i2 + 0] %asi, %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_7_49:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_49
nop
P4764: !_LD [18] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_50:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4765: !_LD [30] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_7_50:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_50
nop
P4766: !_DWLD [31] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_51:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 32], %o0
! move %o0(upper) -> %o0(upper)
P4767: !_LD [13] (Int) (Loop exit)
sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 4], %l7
! move %l7(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_7_51:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_51
nop
P4768: !_BLD [2] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_52:
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i0 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P4769: !_NOP (Int) (Loop exit)
nop
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_7_52:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_52
nop
P4770: !_LD [30] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_53:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4771: !_BLD [27] (FP)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P4772: !_LD [6] (Int) (Loop exit) (Branch target of P5058)
lduw [%i1 + 12], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_7_53:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_53
nop
ba P4773
nop
TARGET5058:
ba RET5058
nop
P4773: !_DWLD [26] (Int) (Loop entry) (CBR)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_54:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET4773
nop
RET4773:
! lfsr step begin
srlx %l0, 1, %o5
xnor %o5, %l0, %o5
sllx %o5, 63, %o5
or %o5, %l0, %l0
srlx %l0, 1, %l0
P4774: !_REPLACEMENT [8] (Int) (Branch target of P4751)
sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS3_O), %i2
sub %i0, %i2, %i2
sethi %hi(0x10000), %l3
ld [%i2+0], %l7
st %l7, [%i2+0]
add %i2, %l3, %l6
ld [%l6+0], %l7
st %l7, [%l6+0]
add %l6, %l3, %l6
ld [%l6+0], %l7
st %l7, [%l6+0]
add %l6, %l3, %l6
ld [%l6+0], %l7
st %l7, [%l6+0]
ba P4775
nop
TARGET4751:
ba RET4751
nop
P4775: !_LD [28] (Int) (Loop exit)
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 0], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_7_54:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_54
nop
P4776: !_DWLD [0] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_55:
ldx [%i0 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
P4777: !_DWLD [4] (Int) (Loop exit)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 4
sethi %hi(0xc0000), %l6
sub %i1, %l6, %i1
ldx [%i1 + 0], %o1
! move %o1(upper) -> %o1(upper)
! move %o1(lower) -> %o1(lower)
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
sethi %hi(0xc0000), %l3
add %i1, %l3, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_7_55:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_55
nop
P4778: !_DWLD [3] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_56:
ldx [%i0 + 32], %o0
! move %o0(upper) -> %o0(upper)
P4779: !_LD [6] (Int) (Loop exit)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 6
sethi %hi(0xc0000), %o5
sub %i1, %o5, %i1
lduw [%i1 + 12], %l6
! move %l6(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
sethi %hi(0xc0000), %l7
add %i1, %l7, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_7_56:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_56
nop
P4780: !_BLD [17] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_57:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P4781: !_DWLD [22] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4782: !_LD [26] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_7_57:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_57
nop
P4783: !_DWLD [31] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_58:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 32], %o0
! move %o0(upper) -> %o0(upper)
P4784: !_LD [14] (Int) (Loop exit)
sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 12], %l6
! move %l6(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_7_58:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_58
nop
P4785: !_BLD [12] (FP) (Loop entry) (CBR)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_59:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET4785
nop
RET4785:
! lfsr step begin
srlx %l0, 1, %l3
xnor %l3, %l0, %l3
sllx %l3, 63, %l3
or %l3, %l0, %l0
srlx %l0, 1, %l0
P4786: !_DWLD [11] (FP) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i2
sub %i0, %i2, %i2
ldd [%i2 + 32], %f4
! 1 addresses covered
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovs %f4, %f30
!--
loop_exit_7_59:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_59
nop
P4787: !_DWLD [28] (Int) (Loop entry) (LE)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_60:
wr %g0, 0x88, %asi
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i3
sub %i0, %i3, %i3
ldxa [%i3 + 0] %asi, %l3
! move %l3(lower) -> %o0(upper)
sllx %l3, 32, %o0
! move %l3(upper) -> %o0(lower)
srlx %l3, 32, %o5
or %o5, %o0, %o0
P4788: !_BLD [9] (FP) (Loop exit) (Branch target of P4755)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_7_60:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_60
nop
ba P4789
nop
TARGET4755:
ba RET4755
nop
P4789: !_DWLD [25] (Int) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_61:
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
ldx [%i3 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_7_61:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_61
nop
P4790: !_FLUSHI [23] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_62:
flush %g0
P4791: !_BLD [23] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_7_62:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_62
nop
P4792: !_LD [27] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_63:
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4793: !_DWLD [10] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 8], %l3
! move %l3(lower) -> %o0(lower)
srl %l3, 0, %o5
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_7_63:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_63
nop
P4794: !_CASX [12] (maybe <- 0x3800007) (Int) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_64:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i3
sub %i0, %i3, %i3
ldx [%i3], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
mov %o0, %l7
sllx %l4, 32, %o1
add %l4, 1, %l4
or %l4, %o1, %o1
casx [%i3], %l7, %o1
! move %o1(upper) -> %o1(upper)
! move %o1(lower) -> %o1(lower)
add %l4, 1, %l4
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_7_64:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_64
nop
P4795: !_LD [17] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_65:
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4796: !_DWLD [3] (Int) (Loop exit)
ldx [%i0 + 32], %o5
! move %o5(upper) -> %o0(lower)
srlx %o5, 32, %l7
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_7_65:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_65
nop
P4797: !_LD [19] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_66:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4798: !_LD [20] (Int) (Loop exit) (LE)
wr %g0, 0x88, %asi
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduwa [%i2 + 0] %asi, %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_7_66:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_66
nop
P4799: !_BLD [11] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_67:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_7_67:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_67
nop
P4800: !_REPLACEMENT [17] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_68:
sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS1_O), %i2
sub %i0, %i2, %i2
sethi %hi(0x10000), %l6
ld [%i2+4], %o5
st %o5, [%i2+4]
add %i2, %l6, %l7
ld [%l7+4], %o5
st %o5, [%l7+4]
add %l7, %l6, %l7
ld [%l7+4], %o5
st %o5, [%l7+4]
add %l7, %l6, %l7
ld [%l7+4], %o5
st %o5, [%l7+4]
P4801: !_BLD [17] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_7_68:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_68
nop
P4802: !_BLD [7] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_69:
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_7_69:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_69
nop
P4803: !_DWLD [11] (Int) (Loop entry) (CBR)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_70:
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
ldx [%i2 + 32], %o0
! move %o0(upper) -> %o0(upper)
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET4803
nop
RET4803:
! lfsr step begin
srlx %l0, 1, %l7
xnor %l7, %l0, %l7
sllx %l7, 63, %l7
or %l7, %l0, %l0
srlx %l0, 1, %l0
P4804: !_LD [19] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %l3
! move %l3(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_7_70:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_70
nop
P4805: !_BLD [17] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_71:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_7_71:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_71
nop
P4806: !_DWLD [25] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_72:
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
ldd [%i3 + 0], %f0
! 2 addresses covered
P4807: !_PREFETCH [20] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i2
sub %i0, %i2, %i2
prefetch [%i2 + 0], 1
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
!--
loop_exit_7_72:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_72
nop
P4808: !_LD [29] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_73:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4809: !_LD [0] (Int) (Loop exit)
lduw [%i0 + 0], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_7_73:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_73
nop
P4810: !_DWLD [20] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_74:
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i2
sub %i0, %i2, %i2
ldd [%i2 + 0], %f0
! 2 addresses covered
P4811: !_REPLACEMENT [8] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS1_O), %i3
sub %i0, %i3, %i3
sethi %hi(0x10000), %l6
ld [%i3+0], %o5
st %o5, [%i3+0]
add %i3, %l6, %l7
ld [%l7+0], %o5
st %o5, [%l7+0]
add %l7, %l6, %l7
ld [%l7+0], %o5
st %o5, [%l7+0]
add %l7, %l6, %l7
ld [%l7+0], %o5
st %o5, [%l7+0]
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
!--
loop_exit_7_74:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_74
nop
P4812: !_BLD [31] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_75:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_7_75:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_75
nop
P4813: !_DWLD [22] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_76:
sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
ldx [%i3 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4814: !_LD [19] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 32], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_7_76:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_76
nop
P4815: !_DWLD [11] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_77:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i3
sub %i0, %i3, %i3
ldd [%i3 + 32], %f0
! 1 addresses covered
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
loop_exit_7_77:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_77
nop
P4816: !_LD [28] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_78:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4817: !_DWLD [9] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 0], %l7
! move %l7(upper) -> %o0(lower)
srlx %l7, 32, %l6
or %l6, %o0, %o0
! move %l7(lower) -> %o1(upper)
sllx %l7, 32, %o1
P4818: !_LD [7] (Int) (Loop exit)
lduw [%i1 + 32], %l3
! move %l3(lower) -> %o1(lower)
or %l3, %o1, %o1
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_7_78:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_78
nop
P4819: !_BLD [20] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_79:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_7_79:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_79
nop
P4820: !_BLD [10] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_80:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_7_80:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_80
nop
P4821: !_LD [30] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_81:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4822: !_LD [21] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 4], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_7_81:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_81
nop
P4823: !_BLD [24] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_82:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P4824: !_BLD [4] (FP) (Loop exit)
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f32
membar #Sync
! 4 addresses covered
fmovd %f32, %f4
fmovd %f34, %f18
fmovs %f19, %f6
fmovd %f40, %f18
fmovs %f18, %f7
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovd %f4, %f30
fmovd %f6, %f30
!--
loop_exit_7_82:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_82
nop
P4825: !_NOP (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_83:
nop
P4826: !_REPLACEMENT [22] (Int) (Loop exit)
sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
sethi %hi(0x10000), %l7
ld [%i3+12], %l3
st %l3, [%i3+12]
add %i3, %l7, %o5
ld [%o5+12], %l3
st %l3, [%o5+12]
add %o5, %l7, %o5
ld [%o5+12], %l3
st %l3, [%o5+12]
add %o5, %l7, %o5
ld [%o5+12], %l3
st %l3, [%o5+12]
loop_exit_7_83:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_83
nop
P4827: !_LD [31] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_84:
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4828: !_CAS [8] (maybe <- 0x3800009) (Int)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3], %l3
mov %l3, %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
mov %l4, %o1
cas [%i3], %l6, %o1
! move %o1(lower) -> %o1(upper)
sllx %o1, 32, %o1
add %l4, 1, %l4
P4829: !_LD [1] (Int) (Loop exit)
lduw [%i0 + 4], %o5
! move %o5(lower) -> %o1(lower)
or %o5, %o1, %o1
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_7_84:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_84
nop
P4830: !_DWLD [22] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_85:
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4831: !_LD [14] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_7_85:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_85
nop
P4832: !_DWLD [21] (Int) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_86:
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_7_86:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_86
nop
P4833: !_BSTC [9] (maybe <- 0x43000005) (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_87:
wr %g0, 0xe0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i3
sub %i0, %i3, %i3
! preparing store val #0, next val will be in f32
fmovs %f16, %f20
fadds %f16, %f17, %f16
! preparing store val #1, next val will be in f33
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #2, next val will be in f35
fmovd %f20, %f32
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #3, next val will be in f40
fmovd %f20, %f34
fmovs %f16, %f20
fadds %f16, %f17, %f16
fmovd %f20, %f40
membar #Sync
stda %f32, [%i3 + 0 ] %asi
membar #Sync
P4834: !_DWLD [17] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_7_87:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_87
nop
P4835: !_DWLD [18] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_88:
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
ldx [%i3 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4836: !_LD [22] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_7_88:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_88
nop
P4837: !_PREFETCH [0] (Int) (Loop entry) (Loop exit) (CBR)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_89:
prefetch [%i0 + 0], 1
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET4837
nop
RET4837:
! lfsr step begin
srlx %l0, 1, %l3
xnor %l3, %l0, %l3
sllx %l3, 63, %l3
or %l3, %l0, %l0
srlx %l0, 1, %l0
loop_exit_7_89:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_89
nop
P4838: !_BSTC [19] (maybe <- 0x43000009) (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_90:
wr %g0, 0xe0, %asi
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
! preparing store val #0, next val will be in f32
fmovs %f16, %f20
fadds %f16, %f17, %f16
! preparing store val #1, next val will be in f33
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #2, next val will be in f35
fmovd %f20, %f32
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #3, next val will be in f40
fmovd %f20, %f34
fmovs %f16, %f20
fadds %f16, %f17, %f16
fmovd %f20, %f40
membar #Sync
stda %f32, [%i3 + 0 ] %asi
membar #Sync
loop_exit_7_90:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_90
nop
P4839: !_LD [22] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_91:
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4840: !_LD [22] (Int) (Loop exit)
lduw [%i2 + 12], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_7_91:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_91
nop
P4841: !_MEMBAR (Int) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_92:
membar #StoreLoad
loop_exit_7_92:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_92
nop
P4842: !_PREFETCH [5] (Int) (Loop entry) (Loop exit) (LE)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_93:
wr %g0, 0x88, %asi
prefetcha [%i1 + 4] %asi, 1
loop_exit_7_93:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_93
nop
P4843: !_LD [7] (Int) (Loop entry) (LE)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_94:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 7
sethi %hi(0xc0000), %o5
sub %i1, %o5, %i1
wr %g0, 0x88, %asi
lduwa [%i1 + 32] %asi, %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4844: !_LD [16] (Int) (Loop exit)
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 0], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
sethi %hi(0xc0000), %l3
add %i1, %l3, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_7_94:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_94
nop
P4845: !_DWLD [5] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_95:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 5
sethi %hi(0xc0000), %l6
sub %i1, %l6, %i1
ldx [%i1 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
P4846: !_LD [28] (Int)
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 0], %o1
! move %o1(lower) -> %o1(upper)
sllx %o1, 32, %o1
P4847: !_LD [7] (Int) (Loop exit)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #2
!Logical addr: 7
sethi %hi(0xc0000), %l7
sub %i1, %l7, %i1
lduw [%i1 + 32], %l3
! move %l3(lower) -> %o1(lower)
or %l3, %o1, %o1
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
sethi %hi(0x180000), %l6
add %i1, %l6, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_7_95:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_95
nop
P4848: !_BLD [1] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_96:
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i0 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_7_96:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_96
nop
P4849: !_LD [27] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_97:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4850: !_LD [13] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_7_97:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_97
nop
P4851: !_DWLD [24] (Int) (Loop entry) (Loop exit) (Branch target of P5302)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_98:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_7_98:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_98
nop
ba P4852
nop
TARGET5302:
ba RET5302
nop
P4852: !_LD [14] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_99:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4853: !_LD [25] (Int) (Loop exit)
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 4], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_7_99:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_99
nop
P4854: !_BLD [16] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_100:
wr %g0, 0xf0, %asi
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_7_100:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_100
nop
P4855: !_FLUSHI [23] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_101:
flush %g0
P4856: !_BLD [13] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_7_101:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_101
nop
P4857: !_CAS [1] (maybe <- 0x380000a) (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_102:
add %i0, 4, %l3
lduw [%l3], %o0
mov %o0, %o5
! move %o5(lower) -> %o0(upper)
sllx %o5, 32, %o0
mov %l4, %l7
cas [%l3], %o5, %l7
! move %l7(lower) -> %o0(lower)
srl %l7, 0, %o5
or %o5, %o0, %o0
add %l4, 1, %l4
P4858: !_DWLD [19] (Int)
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
ldx [%i2 + 32], %o1
! move %o1(upper) -> %o1(upper)
P4859: !_LD [19] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %o5
! move %o5(lower) -> %o1(lower)
srlx %o1, 32, %o1
sllx %o1, 32, %o1
or %o5, %o1, %o1
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_7_102:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_102
nop
P4860: !_BLD [20] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_103:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P4861: !_SWAP [3] (maybe <- 0x380000b) (Int)
mov %l4, %o0
swap [%i0 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
add %l4, 1, %l4
P4862: !_LD [5] (Int) (Loop exit)
lduw [%i1 + 4], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_7_103:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_103
nop
P4863: !_BLD [2] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_104:
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i0 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_7_104:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_104
nop
P4864: !_DWLD [4] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_105:
ldx [%i1 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
P4865: !_BLD [4] (FP) (Loop exit)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 4
sethi %hi(0xc0000), %l3
sub %i1, %l3, %i1
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
sethi %hi(0xc0000), %l6
add %i1, %l6, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_7_105:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_105
nop
P4866: !_DWLD [23] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_106:
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 32], %o0
! move %o0(upper) -> %o0(upper)
P4867: !_LD [22] (Int) (Loop exit)
sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 12], %l7
! move %l7(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_7_106:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_106
nop
P4868: !_DWLD [4] (Int) (Loop entry) (Branch target of P5200)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_107:
ldx [%i1 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
ba P4869
nop
TARGET5200:
ba RET5200
nop
P4869: !_DWLD [30] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 8], %o1
! move %o1(lower) -> %o1(upper)
sllx %o1, 32, %o1
P4870: !_LD [1] (Int) (Loop exit) (Branch target of P4907)
lduw [%i0 + 4], %l7
! move %l7(lower) -> %o1(lower)
or %l7, %o1, %o1
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_7_107:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_107
nop
ba P4871
nop
TARGET4907:
ba RET4907
nop
P4871: !_LD [28] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_108:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4872: !_DWLD [23] (Int) (Loop exit)
sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
ldx [%i3 + 32], %l3
! move %l3(upper) -> %o0(lower)
srlx %l3, 32, %o5
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_7_108:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_108
nop
P4873: !_LD [28] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_109:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4874: !_LD [13] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 4], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_7_109:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_109
nop
P4875: !_BLD [15] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_110:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_7_110:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_110
nop
P4876: !_FLUSHI [28] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_111:
flush %g0
P4877: !_DWLD [11] (Int)
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
ldx [%i3 + 32], %o0
! move %o0(upper) -> %o0(upper)
P4878: !_LD [15] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 32], %l7
! move %l7(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_7_111:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_111
nop
P4879: !_DWLD [12] (Int) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_112:
sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
ldx [%i3 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_7_112:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_112
nop
P4880: !_LD [18] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_113:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4881: !_LD [25] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 4], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_7_113:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_113
nop
P4882: !_BLD [21] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_114:
wr %g0, 0xf0, %asi
sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P4883: !_REPLACEMENT [3] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS1_O), %i3
sub %i0, %i3, %i3
sethi %hi(0x10000), %o5
ld [%i3+32], %l6
st %l6, [%i3+32]
add %i3, %o5, %l3
ld [%l3+32], %l6
st %l6, [%l3+32]
add %l3, %o5, %l3
ld [%l3+32], %l6
st %l6, [%l3+32]
add %l3, %o5, %l3
ld [%l3+32], %l6
st %l6, [%l3+32]
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_7_114:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_114
nop
P4884: !_LD [4] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_115:
lduw [%i1 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4885: !_LD [6] (Int) (Loop exit)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 6
sethi %hi(0xc0000), %l6
sub %i1, %l6, %i1
lduw [%i1 + 12], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
sethi %hi(0xc0000), %l3
add %i1, %l3, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_7_115:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_115
nop
P4886: !_DWLD [7] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_116:
ldx [%i1 + 32], %o0
! move %o0(upper) -> %o0(upper)
P4887: !_LD [13] (FP)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i2
sub %i0, %i2, %i2
ld [%i2 + 4], %f0
! 1 addresses covered
P4888: !_LD [19] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %l6
! move %l6(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
loop_exit_7_116:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_116
nop
P4889: !_LD [19] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_117:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4890: !_LD [6] (Int) (Loop exit)
lduw [%i1 + 12], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_7_117:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_117
nop
P4891: !_DWLD [16] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_118:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
P4892: !_BLD [14] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_7_118:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_118
nop
P4893: !_DWLD [31] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_119:
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
ldd [%i3 + 32], %f0
! 1 addresses covered
P4894: !_BLD [28] (FP) (Loop exit)
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i3 + 0] %asi, %f32
membar #Sync
! 4 addresses covered
fmovd %f32, %f18
fmovs %f18, %f1
fmovs %f19, %f2
fmovd %f34, %f18
fmovs %f19, %f3
fmovd %f40, %f4
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovs %f4, %f30
!--
loop_exit_7_119:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_119
nop
P4895: !_DWLD [1] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_120:
ldx [%i0 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
P4896: !_LD [12] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 0], %o1
! move %o1(lower) -> %o1(upper)
sllx %o1, 32, %o1
P4897: !_LD [11] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %l7
! move %l7(lower) -> %o1(lower)
or %l7, %o1, %o1
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_7_120:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_120
nop
P4898: !_DWLD [18] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_121:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4899: !_LD [27] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_7_121:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_121
nop
P4900: !_LD [0] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_122:
lduw [%i0 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4901: !_BLD [12] (FP)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P4902: !_LD [21] (Int) (Loop exit)
sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 4], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_7_122:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_122
nop
P4903: !_LD [6] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_123:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 6
sethi %hi(0xc0000), %l3
sub %i1, %l3, %i1
lduw [%i1 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4904: !_DWLD [31] (Int) (Loop exit)
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
ldx [%i2 + 32], %l3
! move %l3(upper) -> %o0(lower)
srlx %l3, 32, %o5
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
sethi %hi(0xc0000), %l6
add %i1, %l6, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_7_123:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_123
nop
P4905: !_PREFETCH [8] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_124:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
sub %i0, %i3, %i3
prefetch [%i3 + 0], 1
P4906: !_DWLD [15] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 32], %o0
! move %o0(upper) -> %o0(upper)
P4907: !_LD [18] (Int) (Loop exit) (CBR)
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 12], %o5
! move %o5(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %o5, %o0, %o0
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET4907
nop
RET4907:
! lfsr step begin
srlx %l0, 1, %l3
xnor %l3, %l0, %l3
sllx %l3, 63, %l3
or %l3, %l0, %l0
srlx %l0, 1, %l0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_7_124:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_124
nop
P4908: !_BSTC [4] (maybe <- 0x4300000d) (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_125:
wr %g0, 0xe0, %asi
! preparing store val #0, next val will be in f32
fmovs %f16, %f20
fadds %f16, %f17, %f16
! preparing store val #1, next val will be in f33
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #2, next val will be in f35
fmovd %f20, %f32
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #3, next val will be in f40
fmovd %f20, %f34
fmovs %f16, %f20
fadds %f16, %f17, %f16
fmovd %f20, %f40
membar #Sync
stda %f32, [%i1 + 0 ] %asi
membar #Sync
P4909: !_BLD [15] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_7_125:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_125
nop
P4910: !_BLD [14] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_126:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P4911: !_LD [20] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4912: !_LD [11] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_7_126:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_126
nop
P4913: !_BLD [14] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_127:
wr %g0, 0xf0, %asi
sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P4914: !_LD [2] (Int)
lduw [%i0 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4915: !_LD [4] (Int) (Loop exit)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 4
sethi %hi(0xc0000), %l3
sub %i1, %l3, %i1
lduw [%i1 + 0], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
sethi %hi(0xc0000), %o5
add %i1, %o5, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_7_127:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_127
nop
P4916: !_DWLD [23] (Int) (Loop entry) (LE)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_128:
wr %g0, 0x88, %asi
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i3
sub %i0, %i3, %i3
ldxa [%i3 + 32] %asi, %l6
! move %l6(lower) -> %o0(upper)
sllx %l6, 32, %o0
P4917: !_BST [5] (maybe <- 0x43000011) (FP)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 5
sethi %hi(0xc0000), %l7
sub %i1, %l7, %i1
wr %g0, 0xf0, %asi
! preparing store val #0, next val will be in f32
fmovs %f16, %f20
fadds %f16, %f17, %f16
! preparing store val #1, next val will be in f33
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #2, next val will be in f35
fmovd %f20, %f32
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #3, next val will be in f40
fmovd %f20, %f34
fmovs %f16, %f20
fadds %f16, %f17, %f16
fmovd %f20, %f40
membar #Sync
stda %f32, [%i1 + 0 ] %asi
membar #Sync
P4918: !_LD [9] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
sethi %hi(0xc0000), %l3
add %i1, %l3, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_7_128:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_128
nop
P4919: !_LD [25] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_129:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4920: !_LD [11] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 32], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_7_129:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_129
nop
P4921: !_BLD [4] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_130:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 4
sethi %hi(0xc0000), %o5
sub %i1, %o5, %i1
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
sethi %hi(0xc0000), %l3
add %i1, %l3, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_7_130:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_130
nop
P4922: !_BLD [15] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_131:
wr %g0, 0xf0, %asi
sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_7_131:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_131
nop
P4923: !_BLD [31] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_132:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_7_132:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_132
nop
P4924: !_LD [19] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_133:
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4925: !_LD [26] (Int) (Loop exit)
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 12], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_7_133:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_133
nop
P4926: !_LD [7] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_134:
ld [%i1 + 32], %f0
! 1 addresses covered
P4927: !_BLD [8] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f32
membar #Sync
! 4 addresses covered
fmovd %f32, %f18
fmovs %f18, %f1
fmovs %f19, %f2
fmovd %f34, %f18
fmovs %f19, %f3
fmovd %f40, %f4
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovs %f4, %f30
!--
loop_exit_7_134:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_134
nop
P4928: !_SWAP [22] (maybe <- 0x380000c) (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_135:
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i2
sub %i0, %i2, %i2
mov %l4, %o0
swap [%i2 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
add %l4, 1, %l4
P4929: !_LD [23] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_7_135:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_135
nop
P4930: !_DWLD [12] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_136:
sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
ldx [%i2 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
P4931: !_MEMBAR (Int) (Loop exit)
membar #StoreLoad
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_7_136:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_136
nop
P4932: !_BLD [28] (FP) (Loop entry) (CBR)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_137:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET4932
nop
RET4932:
! lfsr step begin
srlx %l0, 1, %o5
xnor %o5, %l0, %o5
sllx %o5, 63, %o5
or %o5, %l0, %l0
srlx %l0, 1, %l0
P4933: !_LD [0] (Int) (Branch target of P5024)
lduw [%i0 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
ba P4934
nop
TARGET5024:
ba RET5024
nop
P4934: !_LD [19] (Int) (Loop exit)
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 32], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_7_137:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_137
nop
P4935: !_LD [19] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_138:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4936: !_LD [3] (Int) (Loop exit)
lduw [%i0 + 32], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_7_138:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_138
nop
P4937: !_CAS [21] (maybe <- 0x380000d) (Int) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_139:
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i2
sub %i0, %i2, %i2
add %i2, 4, %l7
lduw [%l7], %o0
mov %o0, %l6
! move %l6(lower) -> %o0(upper)
sllx %l6, 32, %o0
mov %l4, %l3
cas [%l7], %l6, %l3
! move %l3(lower) -> %o0(lower)
srl %l3, 0, %l6
or %l6, %o0, %o0
add %l4, 1, %l4
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_7_139:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_139
nop
P4938: !_BLD [9] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_140:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_7_140:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_140
nop
P4939: !_DWLD [16] (Int) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_141:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_7_141:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_141
nop
P4940: !_LD [14] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_142:
sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4941: !_LD [31] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 32], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_7_142:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_142
nop
P4942: !_DWLD [12] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_143:
sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
ldx [%i3 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
P4943: !_DWLD [2] (Int)
ldx [%i0 + 8], %o1
! move %o1(lower) -> %o1(upper)
sllx %o1, 32, %o1
P4944: !_LD [23] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 32], %o5
! move %o5(lower) -> %o1(lower)
or %o5, %o1, %o1
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_7_143:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_143
nop
P4945: !_BLD [6] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_144:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 6
sethi %hi(0xc0000), %l6
sub %i1, %l6, %i1
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P4946: !_LD [31] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4947: !_LD [12] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 0], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
sethi %hi(0xc0000), %o5
add %i1, %o5, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_7_144:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_144
nop
P4948: !_LD [27] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_145:
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4949: !_DWLD [11] (Int) (Loop exit)
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
ldx [%i2 + 32], %l3
! move %l3(upper) -> %o0(lower)
srlx %l3, 32, %o5
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_7_145:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_145
nop
P4950: !_BLD [29] (FP) (Loop entry) (Branch target of P4676)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_146:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
ba P4951
nop
TARGET4676:
ba RET4676
nop
P4951: !_BLD [8] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f32
membar #Sync
! 4 addresses covered
fmovd %f32, %f4
fmovd %f34, %f18
fmovs %f19, %f6
fmovd %f40, %f18
fmovs %f18, %f7
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovd %f4, %f30
fmovd %f6, %f30
!--
loop_exit_7_146:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_146
nop
P4952: !_DWLD [10] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_147:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4953: !_LD [23] (Int) (Loop exit)
sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 32], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_7_147:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_147
nop
P4954: !_DWLD [21] (Int) (Loop entry) (Loop exit) (LE)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_148:
wr %g0, 0x88, %asi
sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
ldxa [%i3 + 0] %asi, %o5
! move %o5(lower) -> %o0(upper)
sllx %o5, 32, %o0
! move %o5(upper) -> %o0(lower)
srlx %o5, 32, %l7
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_7_148:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_148
nop
P4955: !_BLD [20] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_149:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_7_149:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_149
nop
P4956: !_LD [23] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_150:
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4957: !_LD [14] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_7_150:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_150
nop
P4958: !_DWLD [15] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_151:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i3
sub %i0, %i3, %i3
ldd [%i3 + 32], %f0
! 1 addresses covered
P4959: !_BLD [19] (FP) (Loop exit) (CBR)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f32
membar #Sync
! 4 addresses covered
fmovd %f32, %f18
fmovs %f18, %f1
fmovs %f19, %f2
fmovd %f34, %f18
fmovs %f19, %f3
fmovd %f40, %f4
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET4959
nop
RET4959:
! lfsr step begin
srlx %l0, 1, %l7
xnor %l7, %l0, %l7
sllx %l7, 63, %l7
or %l7, %l0, %l0
srlx %l0, 1, %l0
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovs %f4, %f30
!--
loop_exit_7_151:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_151
nop
P4960: !_BLD [15] (FP) (Loop entry) (Loop exit) (CBR) (Branch target of P4837)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_152:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET4960
nop
RET4960:
! lfsr step begin
srlx %l0, 1, %l3
xnor %l3, %l0, %l3
sllx %l3, 63, %l3
or %l3, %l0, %l0
srlx %l0, 1, %l0
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_7_152:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_152
nop
ba P4961
nop
TARGET4837:
ba RET4837
nop
P4961: !_BLD [27] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_153:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P4962: !_DWLD [15] (Int) (LE)
wr %g0, 0x88, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i3
sub %i0, %i3, %i3
ldxa [%i3 + 32] %asi, %l3
! move %l3(lower) -> %o0(upper)
sllx %l3, 32, %o0
P4963: !_LD [3] (Int) (Loop exit)
lduw [%i0 + 32], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_7_153:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_153
nop
P4964: !_DWLD [24] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_154:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
P4965: !_LD [0] (Int)
lduw [%i0 + 0], %o1
! move %o1(lower) -> %o1(upper)
sllx %o1, 32, %o1
P4966: !_LD [27] (Int) (Loop exit)
lduw [%i2 + 32], %o5
! move %o5(lower) -> %o1(lower)
or %o5, %o1, %o1
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_7_154:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_154
nop
P4967: !_BST [13] (maybe <- 0x43000015) (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_155:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i3
sub %i0, %i3, %i3
! preparing store val #0, next val will be in f32
fmovs %f16, %f20
fadds %f16, %f17, %f16
! preparing store val #1, next val will be in f33
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #2, next val will be in f35
fmovd %f20, %f32
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #3, next val will be in f40
fmovd %f20, %f34
fmovs %f16, %f20
fadds %f16, %f17, %f16
fmovd %f20, %f40
membar #Sync
stda %f32, [%i3 + 0 ] %asi
membar #Sync
loop_exit_7_155:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_155
nop
P4968: !_BLD [28] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_156:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P4969: !_DWLD [16] (Int) (Loop exit)
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
ldx [%i3 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_7_156:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_156
nop
P4970: !_BLD [11] (FP) (Loop entry) (Branch target of P4773)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_157:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
ba P4971
nop
TARGET4773:
ba RET4773
nop
P4971: !_BLD [10] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f32
membar #Sync
! 4 addresses covered
fmovd %f32, %f4
fmovd %f34, %f18
fmovs %f19, %f6
fmovd %f40, %f18
fmovs %f18, %f7
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovd %f4, %f30
fmovd %f6, %f30
!--
loop_exit_7_157:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_157
nop
P4972: !_LD [22] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_158:
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4973: !_LD [25] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 4], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_7_158:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_158
nop
P4974: !_LD [9] (Int) (Loop entry) (LE)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_159:
wr %g0, 0x88, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduwa [%i2 + 4] %asi, %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4975: !_LD [17] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 4], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_7_159:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_159
nop
P4976: !_LD [28] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_160:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4977: !_LD [10] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_7_160:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_160
nop
P4978: !_DWLD [31] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_161:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 32], %o0
! move %o0(upper) -> %o0(upper)
P4979: !_BLD [12] (FP)
wr %g0, 0xf0, %asi
sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P4980: !_LD [18] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %l7
! move %l7(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_7_161:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_161
nop
P4981: !_BLD [3] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_162:
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i0 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P4982: !_BSTC [19] (maybe <- 0x43000019) (FP) (Loop exit)
wr %g0, 0xe0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
sub %i0, %i3, %i3
! preparing store val #0, next val will be in f32
fmovs %f16, %f20
fadds %f16, %f17, %f16
! preparing store val #1, next val will be in f33
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #2, next val will be in f35
fmovd %f20, %f32
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #3, next val will be in f40
fmovd %f20, %f34
fmovs %f16, %f20
fadds %f16, %f17, %f16
fmovd %f20, %f40
membar #Sync
stda %f32, [%i3 + 0 ] %asi
membar #Sync
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_7_162:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_162
nop
P4983: !_MEMBAR (Int) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_163:
membar #StoreLoad
loop_exit_7_163:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_163
nop
P4984: !_DWLD [15] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_164:
sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
ldx [%i2 + 32], %o0
! move %o0(upper) -> %o0(upper)
P4985: !_LD [13] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 4], %o5
! move %o5(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_7_164:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_164
nop
P4986: !_LD [23] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_165:
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4987: !_BLD [22] (FP)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P4988: !_LD [1] (Int) (Loop exit)
lduw [%i0 + 4], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_7_165:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_165
nop
P4989: !_LD [11] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_166:
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4990: !_LD [5] (Int) (Loop exit)
lduw [%i1 + 4], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_7_166:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_166
nop
P4991: !_DWLD [11] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_167:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 32], %o0
! move %o0(upper) -> %o0(upper)
P4992: !_LD [4] (Int) (Loop exit)
lduw [%i1 + 0], %l6
! move %l6(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_7_167:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_167
nop
P4993: !_LD [18] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_168:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P4994: !_LD [31] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_7_168:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_168
nop
P4995: !_BLD [11] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_169:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_7_169:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_169
nop
P4996: !_DWLD [1] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_170:
ldx [%i0 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
P4997: !_BLD [27] (FP) (Loop exit) (Branch target of P5220)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_7_170:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_170
nop
ba P4998
nop
TARGET5220:
ba RET5220
nop
P4998: !_DWLD [21] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_171:
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
P4999: !_DWLD [30] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 8], %o1
! move %o1(lower) -> %o1(upper)
sllx %o1, 32, %o1
P5000: !_LD [16] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 0], %l6
! move %l6(lower) -> %o1(lower)
or %l6, %o1, %o1
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_7_171:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_171
nop
P5001: !_BLD [13] (FP) (Loop entry) (Branch target of P5151)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_172:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
ba P5002
nop
TARGET5151:
ba RET5151
nop
P5002: !_BLD [11] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f32
membar #Sync
! 4 addresses covered
fmovd %f32, %f4
fmovd %f34, %f18
fmovs %f19, %f6
fmovd %f40, %f18
fmovs %f18, %f7
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovd %f4, %f30
fmovd %f6, %f30
!--
loop_exit_7_172:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_172
nop
P5003: !_LD [4] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_173:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 4
sethi %hi(0xc0000), %l6
sub %i1, %l6, %i1
lduw [%i1 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P5004: !_LD [30] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
sethi %hi(0xc0000), %l7
add %i1, %l7, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_7_173:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_173
nop
P5005: !_DWLD [25] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_174:
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
ldd [%i2 + 0], %f0
! 2 addresses covered
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
!--
loop_exit_7_174:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_174
nop
P5006: !_LD [12] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_175:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P5007: !_LD [10] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_7_175:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_175
nop
P5008: !_LD [14] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_176:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P5009: !_LD [11] (Int) (Loop exit)
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 32], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_7_176:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_176
nop
P5010: !_DWLD [28] (Int) (Loop entry) (LE)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_177:
wr %g0, 0x88, %asi
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i3
sub %i0, %i3, %i3
ldxa [%i3 + 0] %asi, %l7
! move %l7(lower) -> %o0(upper)
sllx %l7, 32, %o0
! move %l7(upper) -> %o0(lower)
srlx %l7, 32, %l6
or %l6, %o0, %o0
P5011: !_BLD [1] (FP) (Loop exit)
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i0 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_7_177:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_177
nop
P5012: !_DWLD [7] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_178:
ldx [%i1 + 32], %o0
! move %o0(upper) -> %o0(upper)
P5013: !_LD [23] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 32], %l6
! move %l6(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_7_178:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_178
nop
P5014: !_LD [3] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_179:
lduw [%i0 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P5015: !_LD [20] (Int) (Loop exit)
sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 0], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_7_179:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_179
nop
P5016: !_DWLD [28] (Int) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_180:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_7_180:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_180
nop
P5017: !_BLD [27] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_181:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P5018: !_BLD [9] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f32
membar #Sync
! 4 addresses covered
fmovd %f32, %f4
fmovd %f34, %f18
fmovs %f19, %f6
fmovd %f40, %f18
fmovs %f18, %f7
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovd %f4, %f30
fmovd %f6, %f30
!--
loop_exit_7_181:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_181
nop
P5019: !_DWLD [8] (Int) (Loop entry) (LE)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_182:
wr %g0, 0x88, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i3
sub %i0, %i3, %i3
ldxa [%i3 + 0] %asi, %l3
! move %l3(lower) -> %o0(upper)
sllx %l3, 32, %o0
! move %l3(upper) -> %o0(lower)
srlx %l3, 32, %o5
or %o5, %o0, %o0
P5020: !_DWLD [8] (Int) (Loop exit)
ldx [%i3 + 0], %o1
! move %o1(upper) -> %o1(upper)
! move %o1(lower) -> %o1(lower)
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_7_182:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_182
nop
P5021: !_BLD [8] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_183:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_7_183:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_183
nop
P5022: !_MEMBAR (Int) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_184:
membar #StoreLoad
loop_exit_7_184:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_184
nop
P5023: !_LD [7] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_185:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 7
sethi %hi(0xc0000), %o5
sub %i1, %o5, %i1
ld [%i1 + 32], %f0
! 1 addresses covered
P5024: !_LD [10] (Int) (CBR)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET5024
nop
RET5024:
! lfsr step begin
srlx %l0, 1, %l7
xnor %l7, %l0, %l7
sllx %l7, 63, %l7
or %l7, %l0, %l0
srlx %l0, 1, %l0
P5025: !_LD [6] (Int) (Loop exit)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #2
!Logical addr: 6
sethi %hi(0xc0000), %o5
sub %i1, %o5, %i1
lduw [%i1 + 12], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
sethi %hi(0x180000), %l7
add %i1, %l7, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_7_185:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_185
nop
P5026: !_LD [10] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_186:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P5027: !_LD [14] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_7_186:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_186
nop
P5028: !_DWLD [6] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_187:
ldx [%i1 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P5029: !_DWLD [10] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 8], %l6
! move %l6(lower) -> %o0(lower)
srl %l6, 0, %l3
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_7_187:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_187
nop
P5030: !_DWLD [15] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_188:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 32], %o0
! move %o0(upper) -> %o0(upper)
P5031: !_BLD [30] (FP)
wr %g0, 0xf0, %asi
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P5032: !_LD [31] (Int) (Loop exit)
lduw [%i2 + 32], %o5
! move %o5(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_7_188:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_188
nop
P5033: !_DWST [31] (maybe <- 0x380000e) (Int) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_189:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
sub %i0, %i3, %i3
mov %l4, %l7
sllx %l7, 32, %l7
stx %l7, [%i3 + 32 ]
add %l4, 1, %l4
loop_exit_7_189:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_189
nop
P5034: !_LD [11] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_190:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P5035: !_LD [19] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_7_190:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_190
nop
P5036: !_DWLD [9] (Int) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_191:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_7_191:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_191
nop
P5037: !_DWLD [23] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_192:
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 32], %o0
! move %o0(upper) -> %o0(upper)
P5038: !_LD [14] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %o5
! move %o5(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_7_192:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_192
nop
P5039: !_DWLD [4] (Int) (Loop entry) (CBR) (Branch target of P4785)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_193:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 4
sethi %hi(0xc0000), %l6
sub %i1, %l6, %i1
ldx [%i1 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET5039
nop
RET5039:
! lfsr step begin
srlx %l0, 1, %l3
xnor %l3, %l0, %l3
sllx %l3, 63, %l3
or %l3, %l0, %l0
srlx %l0, 1, %l0
ba P5040
nop
TARGET4785:
ba RET4785
nop
P5040: !_LD [12] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %o1
! move %o1(lower) -> %o1(upper)
sllx %o1, 32, %o1
P5041: !_LD [15] (Int) (Loop exit)
sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 32], %l6
! move %l6(lower) -> %o1(lower)
or %l6, %o1, %o1
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
sethi %hi(0xc0000), %l7
add %i1, %l7, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_7_193:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_193
nop
P5042: !_LD [18] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_194:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P5043: !_LD [9] (Int) (Loop exit)
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 4], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_7_194:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_194
nop
P5044: !_DWLD [30] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_195:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P5045: !_LD [7] (Int) (Loop exit) (Branch target of P4932)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 7
sethi %hi(0xc0000), %o5
sub %i1, %o5, %i1
lduw [%i1 + 32], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
sethi %hi(0xc0000), %l7
add %i1, %l7, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_7_195:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_195
nop
ba P5046
nop
TARGET4932:
ba RET4932
nop
P5046: !_BLD [20] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_196:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_7_196:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_196
nop
P5047: !_BLD [9] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_197:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_7_197:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_197
nop
P5048: !_BLD [18] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_198:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P5049: !_MEMBAR (Int) (Loop exit)
membar #StoreLoad
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_7_198:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_198
nop
P5050: !_LD [3] (Int) (Loop entry) (Branch target of P4960)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_199:
lduw [%i0 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
ba P5051
nop
TARGET4960:
ba RET4960
nop
P5051: !_LD [18] (Int) (Loop exit)
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 12], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_7_199:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_199
nop
P5052: !_FLUSHI [6] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_200:
flush %g0
P5053: !_BLD [8] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_7_200:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_200
nop
P5054: !_BLD [26] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_201:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_7_201:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_201
nop
P5055: !_DWLD [5] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_202:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 5
sethi %hi(0xc0000), %l6
sub %i1, %l6, %i1
ldx [%i1 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
P5056: !_DWLD [12] (FP) (Loop exit)
sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
ldd [%i2 + 0], %f0
! 2 addresses covered
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
!--
sethi %hi(0xc0000), %l3
add %i1, %l3, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_7_202:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_202
nop
P5057: !_LD [8] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_203:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P5058: !_LD [24] (Int) (Loop exit) (CBR)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 0], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET5058
nop
RET5058:
! lfsr step begin
srlx %l0, 1, %l7
xnor %l7, %l0, %l7
sllx %l7, 63, %l7
or %l7, %l0, %l0
srlx %l0, 1, %l0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_7_203:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_203
nop
P5059: !_BLD [22] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_204:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_7_204:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_204
nop
P5060: !_LD [8] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_205:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P5061: !_BLD [17] (FP) (CBR)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET5061
nop
RET5061:
! lfsr step begin
srlx %l0, 1, %l6
xnor %l6, %l0, %l6
sllx %l6, 63, %l6
or %l6, %l0, %l0
srlx %l0, 1, %l0
P5062: !_LD [25] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_7_205:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_205
nop
P5063: !_BLD [4] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_206:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 4
sethi %hi(0xc0000), %l6
sub %i1, %l6, %i1
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
sethi %hi(0xc0000), %l7
add %i1, %l7, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_7_206:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_206
nop
P5064: !_LD [6] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_207:
lduw [%i1 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P5065: !_DWLD [6] (FP) (CBR) (Branch target of P5177)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 6
sethi %hi(0xc0000), %l6
sub %i1, %l6, %i1
ldd [%i1 + 8], %f0
! 1 addresses covered
fmovs %f1, %f0
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET5065
nop
RET5065:
! lfsr step begin
srlx %l0, 1, %l7
xnor %l7, %l0, %l7
sllx %l7, 63, %l7
or %l7, %l0, %l0
srlx %l0, 1, %l0
ba P5066
nop
TARGET5177:
ba RET5177
nop
P5066: !_LD [23] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
sethi %hi(0xc0000), %l6
add %i1, %l6, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_7_207:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_207
nop
P5067: !_LD [29] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_208:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P5068: !_LD [29] (Int) (Loop exit)
lduw [%i2 + 4], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_7_208:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_208
nop
P5069: !_LD [4] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_209:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 4
sethi %hi(0xc0000), %l3
sub %i1, %l3, %i1
lduw [%i1 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P5070: !_BLD [16] (FP)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P5071: !_LD [12] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 0], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
sethi %hi(0xc0000), %l7
add %i1, %l7, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_7_209:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_209
nop
P5072: !_LD [10] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_210:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P5073: !_DWLD [4] (Int)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 4
sethi %hi(0xc0000), %l6
sub %i1, %l6, %i1
ldx [%i1 + 0], %o5
! move %o5(upper) -> %o0(lower)
srlx %o5, 32, %l7
or %l7, %o0, %o0
! move %o5(lower) -> %o1(upper)
sllx %o5, 32, %o1
P5074: !_LD [21] (Int) (Loop exit) (Branch target of P5140)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %l6
! move %l6(lower) -> %o1(lower)
or %l6, %o1, %o1
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
sethi %hi(0xc0000), %l7
add %i1, %l7, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_7_210:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_210
nop
ba P5075
nop
TARGET5140:
ba RET5140
nop
P5075: !_DWLD [28] (Int) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_211:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_7_211:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_211
nop
P5076: !_DWLD [15] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_212:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 32], %o0
! move %o0(upper) -> %o0(upper)
P5077: !_LD [28] (Int) (Loop exit)
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 0], %o5
! move %o5(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_7_212:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_212
nop
P5078: !_SWAP [17] (maybe <- 0x380000f) (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_213:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
sub %i0, %i2, %i2
mov %l4, %o0
swap [%i2 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
add %l4, 1, %l4
P5079: !_LD [31] (FP)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
sub %i0, %i3, %i3
ld [%i3 + 32], %f0
! 1 addresses covered
P5080: !_LD [10] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
loop_exit_7_213:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_213
nop
P5081: !_DWLD [15] (Int) (Loop entry) (Branch target of P5061)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_214:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 32], %o0
! move %o0(upper) -> %o0(upper)
ba P5082
nop
TARGET5061:
ba RET5061
nop
P5082: !_BLD [24] (FP)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P5083: !_LD [31] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %l6
! move %l6(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_7_214:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_214
nop
P5084: !_DWLD [31] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_215:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 32], %o0
! move %o0(upper) -> %o0(upper)
P5085: !_LD [31] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %o5
! move %o5(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_7_215:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_215
nop
P5086: !_BLD [6] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_216:
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P5087: !_BLD [8] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f32
membar #Sync
! 4 addresses covered
fmovd %f32, %f4
fmovd %f34, %f18
fmovs %f19, %f6
fmovd %f40, %f18
fmovs %f18, %f7
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovd %f4, %f30
fmovd %f6, %f30
!--
loop_exit_7_216:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_216
nop
P5088: !_BLD [26] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_217:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P5089: !_LD [27] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P5090: !_LD [20] (Int) (Loop exit) (LE)
wr %g0, 0x88, %asi
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduwa [%i3 + 0] %asi, %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_7_217:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_217
nop
P5091: !_BST [5] (maybe <- 0x4300001d) (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_218:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 5
sethi %hi(0xc0000), %l6
sub %i1, %l6, %i1
wr %g0, 0xf0, %asi
! preparing store val #0, next val will be in f32
fmovs %f16, %f20
fadds %f16, %f17, %f16
! preparing store val #1, next val will be in f33
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #2, next val will be in f35
fmovd %f20, %f32
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #3, next val will be in f40
fmovd %f20, %f34
fmovs %f16, %f20
fadds %f16, %f17, %f16
fmovd %f20, %f40
membar #Sync
stda %f32, [%i1 + 0 ] %asi
membar #Sync
P5092: !_LD [28] (Int) (CBR)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET5092
nop
RET5092:
! lfsr step begin
srlx %l0, 1, %o5
xnor %o5, %l0, %o5
sllx %o5, 63, %o5
or %o5, %l0, %l0
srlx %l0, 1, %l0
P5093: !_LD [13] (Int) (Loop exit) (LE)
wr %g0, 0x88, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduwa [%i3 + 4] %asi, %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
sethi %hi(0xc0000), %o5
add %i1, %o5, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_7_218:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_218
nop
P5094: !_BLD [29] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_219:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P5095: !_BLD [8] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f32
membar #Sync
! 4 addresses covered
fmovd %f32, %f4
fmovd %f34, %f18
fmovs %f19, %f6
fmovd %f40, %f18
fmovs %f18, %f7
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovd %f4, %f30
fmovd %f6, %f30
!--
loop_exit_7_219:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_219
nop
P5096: !_DWLD [17] (Int) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_220:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_7_220:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_220
nop
P5097: !_DWLD [26] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_221:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P5098: !_LD [25] (Int) (Loop exit)
lduw [%i3 + 4], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_7_221:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_221
nop
P5099: !_DWLD [28] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_222:
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
ldx [%i2 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
P5100: !_BLD [17] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_7_222:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_222
nop
P5101: !_DWLD [9] (Int) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_223:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_7_223:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_223
nop
P5102: !_BLD [15] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_224:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P5103: !_LD [6] (Int)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 6
sethi %hi(0xc0000), %o5
sub %i1, %o5, %i1
lduw [%i1 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P5104: !_LD [3] (Int) (Loop exit)
lduw [%i0 + 32], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
sethi %hi(0xc0000), %l3
add %i1, %l3, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_7_224:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_224
nop
P5105: !_LD [14] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_225:
sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P5106: !_LD [11] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_7_225:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_225
nop
P5107: !_BLD [4] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_226:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 4
sethi %hi(0xc0000), %o5
sub %i1, %o5, %i1
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
sethi %hi(0xc0000), %l3
add %i1, %l3, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_7_226:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_226
nop
P5108: !_SWAP [29] (maybe <- 0x3800010) (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_227:
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
mov %l4, %o0
swap [%i2 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
add %l4, 1, %l4
P5109: !_DWLD [23] (FP)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i3
sub %i0, %i3, %i3
ldd [%i3 + 32], %f0
! 1 addresses covered
P5110: !_LD [12] (Int) (Loop exit)
sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 0], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
loop_exit_7_227:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_227
nop
P5111: !_BLD [17] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_228:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_7_228:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_228
nop
P5112: !_LD [27] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_229:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P5113: !_LD [25] (Int) (Loop exit)
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 4], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_7_229:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_229
nop
P5114: !_LD [28] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_230:
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P5115: !_BLD [19] (FP)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P5116: !_LD [15] (Int) (Loop exit)
sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 32], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_7_230:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_230
nop
P5117: !_REPLACEMENT [14] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_231:
sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
sethi %hi(0x10000), %o5
ld [%i3+12], %l6
st %l6, [%i3+12]
add %i3, %o5, %l3
ld [%l3+12], %l6
st %l6, [%l3+12]
add %l3, %o5, %l3
ld [%l3+12], %l6
st %l6, [%l3+12]
add %l3, %o5, %l3
ld [%l3+12], %l6
st %l6, [%l3+12]
P5118: !_LD [12] (Int)
sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P5119: !_LD [25] (Int) (Loop exit) (LE)
wr %g0, 0x88, %asi
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduwa [%i3 + 4] %asi, %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_7_231:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_231
nop
P5120: !_DWLD [16] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_232:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
P5121: !_DWLD [20] (Int) (Loop exit)
sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
ldx [%i3 + 0], %o1
! move %o1(upper) -> %o1(upper)
! move %o1(lower) -> %o1(lower)
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_7_232:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_232
nop
P5122: !_NOP (Int) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_233:
nop
loop_exit_7_233:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_233
nop
P5123: !_LD [24] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_234:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i2
sub %i0, %i2, %i2
ld [%i2 + 0], %f0
! 1 addresses covered
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
loop_exit_7_234:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_234
nop
P5124: !_BLD [27] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_235:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_7_235:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_235
nop
P5125: !_DWLD [8] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_236:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
P5126: !_ST [25] (maybe <- 0x3800011) (Int) (Loop exit) (LE)
wr %g0, 0x88, %asi
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i3
sub %i0, %i3, %i3
! Change single-word-level endianess (big endian <-> little endian)
sethi %hi(0xff00ff00), %l7
or %l7, %lo(0xff00ff00), %l7
and %l4, %l7, %o5
srl %o5, 8, %o5
sll %l4, 8, %l6
and %l6, %l7, %l6
or %l6, %o5, %l6
srl %l6, 16, %o5
sll %l6, 16, %l6
srl %l6, 0, %l6
or %l6, %o5, %l6
stwa %l6, [%i3 + 4] %asi
add %l4, 1, %l4
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_7_236:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_236
nop
P5127: !_LD [29] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_237:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P5128: !_LD [18] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_7_237:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_237
nop
P5129: !_LD [18] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_238:
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P5130: !_LD [23] (Int) (Loop exit)
sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 32], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_7_238:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_238
nop
P5131: !_BLD [15] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_239:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P5132: !_BSTC [9] (maybe <- 0x43000021) (FP) (Loop exit)
wr %g0, 0xe0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i3
sub %i0, %i3, %i3
! preparing store val #0, next val will be in f32
fmovs %f16, %f20
fadds %f16, %f17, %f16
! preparing store val #1, next val will be in f33
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #2, next val will be in f35
fmovd %f20, %f32
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #3, next val will be in f40
fmovd %f20, %f34
fmovs %f16, %f20
fadds %f16, %f17, %f16
fmovd %f20, %f40
membar #Sync
stda %f32, [%i3 + 0 ] %asi
membar #Sync
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_7_239:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_239
nop
P5133: !_DWLD [31] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_240:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 32], %o0
! move %o0(upper) -> %o0(upper)
P5134: !_LD [17] (Int) (Loop exit) (LE)
wr %g0, 0x88, %asi
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduwa [%i3 + 4] %asi, %l7
! move %l7(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_7_240:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_240
nop
P5135: !_LD [0] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_241:
lduw [%i0 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P5136: !_NOP (Int)
nop
P5137: !_LD [0] (Int) (Loop exit)
lduw [%i0 + 0], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_7_241:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_241
nop
P5138: !_LD [26] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_242:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P5139: !_SWAP [16] (maybe <- 0x3800012) (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
sub %i0, %i3, %i3
mov %l4, %l3
swap [%i3 + 0], %l3
! move %l3(lower) -> %o0(lower)
srl %l3, 0, %l7
or %l7, %o0, %o0
add %l4, 1, %l4
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_7_242:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_242
nop
P5140: !_DWLD [3] (Int) (Loop entry) (CBR)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_243:
ldx [%i0 + 32], %o0
! move %o0(upper) -> %o0(upper)
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET5140
nop
RET5140:
! lfsr step begin
srlx %l0, 1, %l3
xnor %l3, %l0, %l3
sllx %l3, 63, %l3
or %l3, %l0, %l0
srlx %l0, 1, %l0
P5141: !_DWLD [20] (Int) (Branch target of P5092)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 0], %o5
! move %o5(upper) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
srlx %o5, 32, %l7
or %l7, %o0, %o0
! move %o5(lower) -> %o1(upper)
sllx %o5, 32, %o1
ba P5142
nop
TARGET5092:
ba RET5092
nop
P5142: !_LD [3] (Int) (Loop exit)
lduw [%i0 + 32], %l6
! move %l6(lower) -> %o1(lower)
or %l6, %o1, %o1
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_7_243:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_243
nop
P5143: !_BLD [10] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_244:
wr %g0, 0xf0, %asi
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P5144: !_BLD [18] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f32
membar #Sync
! 4 addresses covered
fmovd %f32, %f4
fmovd %f34, %f18
fmovs %f19, %f6
fmovd %f40, %f18
fmovs %f18, %f7
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovd %f4, %f30
fmovd %f6, %f30
!--
loop_exit_7_244:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_244
nop
P5145: !_LD [23] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_245:
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P5146: !_LD [7] (Int) (Loop exit)
lduw [%i1 + 32], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_7_245:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_245
nop
P5147: !_LD [7] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_246:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 7
sethi %hi(0xc0000), %o5
sub %i1, %o5, %i1
lduw [%i1 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P5148: !_LD [29] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
sethi %hi(0xc0000), %l3
add %i1, %l3, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_7_246:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_246
nop
P5149: !_BLD [11] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_247:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P5150: !_BLD [25] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f32
membar #Sync
! 4 addresses covered
fmovd %f32, %f4
fmovd %f34, %f18
fmovs %f19, %f6
fmovd %f40, %f18
fmovs %f18, %f7
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovd %f4, %f30
fmovd %f6, %f30
!--
loop_exit_7_247:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_247
nop
P5151: !_DWLD [18] (Int) (Loop entry) (CBR) (Branch target of P4666)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_248:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET5151
nop
RET5151:
! lfsr step begin
srlx %l0, 1, %l7
xnor %l7, %l0, %l7
sllx %l7, 63, %l7
or %l7, %l0, %l0
srlx %l0, 1, %l0
ba P5152
nop
TARGET4666:
ba RET4666
nop
P5152: !_LD [24] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 0], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_7_248:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_248
nop
P5153: !_BLD [31] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_249:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P5154: !_BLD [15] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f32
membar #Sync
! 4 addresses covered
fmovd %f32, %f4
fmovd %f34, %f18
fmovs %f19, %f6
fmovd %f40, %f18
fmovs %f18, %f7
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovd %f4, %f30
fmovd %f6, %f30
!--
loop_exit_7_249:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_249
nop
P5155: !_LD [5] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_250:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 5
sethi %hi(0xc0000), %l3
sub %i1, %l3, %i1
lduw [%i1 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P5156: !_LD [10] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
sethi %hi(0xc0000), %l6
add %i1, %l6, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_7_250:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_250
nop
P5157: !_BLD [5] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_251:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 5
sethi %hi(0xc0000), %l7
sub %i1, %l7, %i1
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i1 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
sethi %hi(0xc0000), %o5
add %i1, %o5, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_7_251:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_251
nop
P5158: !_LD [5] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_252:
lduw [%i1 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P5159: !_LD [29] (Int) (Loop exit)
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 4], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_7_252:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_252
nop
P5160: !_DWLD [8] (Int) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_253:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_7_253:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_253
nop
P5161: !_LD [14] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_254:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P5162: !_LD [15] (Int) (Loop exit)
lduw [%i2 + 32], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_7_254:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_254
nop
P5163: !_DWLD [8] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_255:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
P5164: !_BLD [26] (FP) (Loop exit) (Branch target of P5176)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_7_255:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_255
nop
ba P5165
nop
TARGET5176:
ba RET5176
nop
P5165: !_LD [22] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_256:
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P5166: !_LD [31] (Int) (Loop exit)
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 32], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_7_256:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_256
nop
P5167: !_DWLD [2] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_257:
ldx [%i0 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P5168: !_LD [29] (Int) (Loop exit)
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 4], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_7_257:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_257
nop
P5169: !_NOP (Int) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_258:
nop
loop_exit_7_258:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_258
nop
P5170: !_LD [15] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_259:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P5171: !_LD [18] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_7_259:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_259
nop
P5172: !_BLD [22] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_260:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P5173: !_LD [8] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P5174: !_LD [28] (Int) (Loop exit)
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 0], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_7_260:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_260
nop
P5175: !_DWLD [28] (Int) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_261:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_7_261:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_261
nop
P5176: !_DWLD [27] (Int) (Loop entry) (CBR)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_262:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 32], %o0
! move %o0(upper) -> %o0(upper)
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET5176
nop
RET5176:
! lfsr step begin
srlx %l0, 1, %o5
xnor %o5, %l0, %o5
sllx %o5, 63, %o5
or %o5, %l0, %l0
srlx %l0, 1, %l0
P5177: !_LD [16] (Int) (Loop exit) (CBR)
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 0], %l7
! move %l7(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %l7, %o0, %o0
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET5177
nop
RET5177:
! lfsr step begin
srlx %l0, 1, %o5
xnor %o5, %l0, %o5
sllx %o5, 63, %o5
or %o5, %l0, %l0
srlx %l0, 1, %l0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_7_262:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_262
nop
P5178: !_LD [13] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_263:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P5179: !_BLD [24] (FP)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P5180: !_LD [9] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_7_263:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_263
nop
P5181: !_BLD [15] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_264:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_7_264:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_264
nop
P5182: !_LD [24] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_265:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P5183: !_DWLD [11] (FP)
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
ldd [%i3 + 32], %f0
! 1 addresses covered
P5184: !_LD [16] (Int) (Loop exit)
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 0], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
loop_exit_7_265:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_265
nop
P5185: !_LD [8] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_266:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P5186: !_BLD [23] (FP)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P5187: !_LD [17] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 4], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_7_266:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_266
nop
P5188: !_DWLD [7] (Int) (Loop entry) (LE)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_267:
wr %g0, 0x88, %asi
ldxa [%i1 + 32] %asi, %o5
! move %o5(lower) -> %o0(upper)
sllx %o5, 32, %o0
P5189: !_LD [23] (FP) (CBR)
sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
ld [%i2 + 32], %f0
! 1 addresses covered
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET5189
nop
RET5189:
! lfsr step begin
srlx %l0, 1, %l6
xnor %l6, %l0, %l6
sllx %l6, 63, %l6
or %l6, %l0, %l0
srlx %l0, 1, %l0
P5190: !_LD [27] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
loop_exit_7_267:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_267
nop
P5191: !_DWLD [9] (Int) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_268:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_7_268:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_268
nop
P5192: !_DWLD [9] (Int) (Loop entry) (LE)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_269:
wr %g0, 0x88, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
sub %i0, %i3, %i3
ldxa [%i3 + 0] %asi, %l7
! move %l7(lower) -> %o0(upper)
sllx %l7, 32, %o0
! move %l7(upper) -> %o0(lower)
srlx %l7, 32, %l6
or %l6, %o0, %o0
P5193: !_BLD [23] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_7_269:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_269
nop
P5194: !_LD [14] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_270:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P5195: !_LD [20] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 0], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_7_270:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_270
nop
P5196: !_REPLACEMENT [3] (Int) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_271:
sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS2_O), %i3
sub %i0, %i3, %i3
sethi %hi(0x10000), %o5
ld [%i3+32], %l6
st %l6, [%i3+32]
add %i3, %o5, %l3
ld [%l3+32], %l6
st %l6, [%l3+32]
add %l3, %o5, %l3
ld [%l3+32], %l6
st %l6, [%l3+32]
add %l3, %o5, %l3
ld [%l3+32], %l6
st %l6, [%l3+32]
loop_exit_7_271:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_271
nop
P5197: !_LD [28] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_272:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i2
sub %i0, %i2, %i2
ld [%i2 + 0], %f0
! 1 addresses covered
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
loop_exit_7_272:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_272
nop
P5198: !_DWLD [31] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_273:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 32], %o0
! move %o0(upper) -> %o0(upper)
P5199: !_LD [25] (Int) (Loop exit)
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 4], %l6
! move %l6(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_7_273:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_273
nop
P5200: !_DWLD [21] (Int) (Loop entry) (Loop exit) (CBR)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_274:
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET5200
nop
RET5200:
! lfsr step begin
srlx %l0, 1, %l6
xnor %l6, %l0, %l6
sllx %l6, 63, %l6
or %l6, %l0, %l0
srlx %l0, 1, %l0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_7_274:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_274
nop
P5201: !_CAS [18] (maybe <- 0x3800013) (Int) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_275:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i2
sub %i0, %i2, %i2
add %i2, 12, %l6
lduw [%l6], %o0
mov %o0, %l3
! move %l3(lower) -> %o0(upper)
sllx %l3, 32, %o0
mov %l4, %o5
cas [%l6], %l3, %o5
! move %o5(lower) -> %o0(lower)
srl %o5, 0, %l3
or %l3, %o0, %o0
add %l4, 1, %l4
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_7_275:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_275
nop
P5202: !_DWLD [19] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_276:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 32], %o0
! move %o0(upper) -> %o0(upper)
P5203: !_DWLD [24] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 0], %l6
! move %l6(upper) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
srlx %l6, 32, %l3
or %l3, %o0, %o0
! move %l6(lower) -> %o1(upper)
sllx %l6, 32, %o1
P5204: !_LD [11] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %o5
! move %o5(lower) -> %o1(lower)
or %o5, %o1, %o1
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_7_276:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_276
nop
P5205: !_DWLD [9] (Int) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_277:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_7_277:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_277
nop
P5206: !_DWLD [2] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_278:
ldx [%i0 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P5207: !_BLD [10] (FP)
wr %g0, 0xf0, %asi
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P5208: !_LD [30] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_7_278:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_278
nop
P5209: !_CAS [21] (maybe <- 0x3800014) (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_279:
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i3
sub %i0, %i3, %i3
add %i3, 4, %l6
lduw [%l6], %o0
mov %o0, %l3
! move %l3(lower) -> %o0(upper)
sllx %l3, 32, %o0
mov %l4, %o5
cas [%l6], %l3, %o5
! move %o5(lower) -> %o0(lower)
srl %o5, 0, %l3
or %l3, %o0, %o0
add %l4, 1, %l4
P5210: !_CAS [5] (maybe <- 0x3800015) (Int) (Loop exit)
add %i1, 4, %l6
lduw [%l6], %o1
mov %o1, %l3
! move %l3(lower) -> %o1(upper)
sllx %l3, 32, %o1
mov %l4, %o5
cas [%l6], %l3, %o5
! move %o5(lower) -> %o1(lower)
srl %o5, 0, %l3
or %l3, %o1, %o1
add %l4, 1, %l4
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_7_279:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_279
nop
P5211: !_BLD [0] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_280:
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i0 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P5212: !_BLD [30] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f32
membar #Sync
! 4 addresses covered
fmovd %f32, %f4
fmovd %f34, %f18
fmovs %f19, %f6
fmovd %f40, %f18
fmovs %f18, %f7
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
fmovd %f4, %f30
fmovd %f6, %f30
!--
loop_exit_7_280:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_280
nop
P5213: !_DWLD [2] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_281:
ldx [%i0 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P5214: !_LD [11] (Int) (Loop exit)
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 32], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_7_281:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_281
nop
P5215: !_LD [29] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_282:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P5216: !_NOP (Int) (Branch target of P5065)
nop
ba P5217
nop
TARGET5065:
ba RET5065
nop
P5217: !_LD [2] (Int) (Loop exit)
lduw [%i0 + 12], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_7_282:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_282
nop
P5218: !_MEMBAR (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_283:
membar #StoreLoad
P5219: !_BLD [21] (FP) (Loop exit)
wr %g0, 0xf0, %asi
sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_7_283:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_283
nop
P5220: !_DWLD [18] (Int) (Loop entry) (CBR)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_284:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET5220
nop
RET5220:
! lfsr step begin
srlx %l0, 1, %l3
xnor %l3, %l0, %l3
sllx %l3, 63, %l3
or %l3, %l0, %l0
srlx %l0, 1, %l0
P5221: !_LD [6] (Int) (Loop exit)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 6
sethi %hi(0xc0000), %l6
sub %i1, %l6, %i1
lduw [%i1 + 12], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
sethi %hi(0xc0000), %l3
add %i1, %l3, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_7_284:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_284
nop
P5222: !_ST [19] (maybe <- 0x3800016) (Int) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_285:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i3
sub %i0, %i3, %i3
stw %l4, [%i3 + 32 ]
add %l4, 1, %l4
loop_exit_7_285:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_285
nop
P5223: !_CASX [13] (maybe <- 0x3800017) (Int) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_286:
sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
ldx [%i2], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
mov %o0, %l7
sllx %l4, 32, %o1
add %l4, 1, %l4
or %l4, %o1, %o1
casx [%i2], %l7, %o1
! move %o1(upper) -> %o1(upper)
! move %o1(lower) -> %o1(lower)
add %l4, 1, %l4
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_7_286:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_286
nop
P5224: !_DWLD [19] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_287:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 32], %o0
! move %o0(upper) -> %o0(upper)
P5225: !_LD [5] (Int) (Loop exit) (LE)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 5
sethi %hi(0xc0000), %l6
sub %i1, %l6, %i1
wr %g0, 0x88, %asi
lduwa [%i1 + 4] %asi, %o5
! move %o5(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
sethi %hi(0xc0000), %l3
add %i1, %l3, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_7_287:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_287
nop
P5226: !_LD [16] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_288:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P5227: !_LD [20] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_7_288:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_288
nop
P5228: !_DWLD [24] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_289:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
sub %i0, %i2, %i2
ldd [%i2 + 0], %f0
! 2 addresses covered
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
!--
loop_exit_7_289:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_289
nop
P5229: !_NOP (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_290:
nop
P5230: !_LD [23] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P5231: !_LD [22] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_7_290:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_290
nop
P5232: !_DWLD [20] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_291:
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
P5233: !_DWLD [1] (Int) (Loop exit)
ldx [%i0 + 0], %o1
! move %o1(upper) -> %o1(upper)
! move %o1(lower) -> %o1(lower)
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_7_291:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_291
nop
P5234: !_LD [18] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_292:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i2
sub %i0, %i2, %i2
ld [%i2 + 12], %f0
! 1 addresses covered
P5235: !_DWLD [11] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 32], %o0
! move %o0(upper) -> %o0(upper)
P5236: !_LD [2] (Int) (Loop exit)
lduw [%i0 + 12], %l6
! move %l6(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
loop_exit_7_292:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_292
nop
P5237: !_LD [13] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_293:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P5238: !_LD [18] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_7_293:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_293
nop
P5239: !_CASX [1] (maybe <- 0x3800019) (Int) (Loop entry) (Loop exit) (CBR)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_294:
ldx [%i0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
mov %o0, %l7
sllx %l4, 32, %o1
add %l4, 1, %l4
or %l4, %o1, %o1
casx [%i0], %l7, %o1
! move %o1(upper) -> %o1(upper)
! move %o1(lower) -> %o1(lower)
add %l4, 1, %l4
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET5239
nop
RET5239:
! lfsr step begin
srlx %l0, 1, %l7
xnor %l7, %l0, %l7
sllx %l7, 63, %l7
or %l7, %l0, %l0
srlx %l0, 1, %l0
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_7_294:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_294
nop
P5240: !_DWLD [23] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_295:
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 32], %o0
! move %o0(upper) -> %o0(upper)
P5241: !_DWST [12] (maybe <- 0x380001b) (Int)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i3
sub %i0, %i3, %i3
sllx %l4, 32, %o5
add %l4, 1, %l4
or %o5, %l4, %o5
stx %o5, [%i3 + 0]
add %l4, 1, %l4
P5242: !_LD [25] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %o5
! move %o5(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_7_295:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_295
nop
P5243: !_DWLD [2] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_296:
ldx [%i0 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P5244: !_BLD [20] (FP)
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
sub %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P5245: !_LD [29] (Int) (Loop exit)
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 4], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_7_296:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_296
nop
P5246: !_BST [30] (maybe <- 0x43000025) (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_297:
wr %g0, 0xf0, %asi
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
! preparing store val #0, next val will be in f32
fmovs %f16, %f20
fadds %f16, %f17, %f16
! preparing store val #1, next val will be in f33
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #2, next val will be in f35
fmovd %f20, %f32
fmovs %f16, %f21
fadds %f16, %f17, %f16
! preparing store val #3, next val will be in f40
fmovd %f20, %f34
fmovs %f16, %f20
fadds %f16, %f17, %f16
fmovd %f20, %f40
membar #Sync
stda %f32, [%i3 + 0 ] %asi
membar #Sync
loop_exit_7_297:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_297
nop
P5247: !_BLD [30] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_298:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_7_298:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_298
nop
P5248: !_CAS [17] (maybe <- 0x380001d) (Int) (Loop entry) (Loop exit) (Branch target of P4803)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_299:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i3
sub %i0, %i3, %i3
add %i3, 4, %o5
lduw [%o5], %o0
mov %o0, %l7
! move %l7(lower) -> %o0(upper)
sllx %l7, 32, %o0
mov %l4, %l6
cas [%o5], %l7, %l6
! move %l6(lower) -> %o0(lower)
srl %l6, 0, %l7
or %l7, %o0, %o0
add %l4, 1, %l4
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_7_299:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_299
nop
ba P5249
nop
TARGET4803:
ba RET4803
nop
P5249: !_REPLACEMENT [26] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_300:
sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS1_O), %i2
sub %i0, %i2, %i2
sethi %hi(0x10000), %l3
ld [%i2+12], %l7
st %l7, [%i2+12]
add %i2, %l3, %l6
ld [%l6+12], %l7
st %l7, [%l6+12]
add %l6, %l3, %l6
ld [%l6+12], %l7
st %l7, [%l6+12]
add %l6, %l3, %l6
ld [%l6+12], %l7
st %l7, [%l6+12]
P5250: !_DWLD [9] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_7_300:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_300
nop
P5251: !_LD [29] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_301:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P5252: !_LD [10] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 12], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_7_301:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_301
nop
P5253: !_DWST [10] (maybe <- 0x380001e) (Int) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_302:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
sub %i0, %i2, %i2
mov %l4, %l6
stx %l6, [%i2 + 8]
add %l4, 1, %l4
loop_exit_7_302:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_302
nop
P5254: !_DWST [28] (maybe <- 0x380001f) (Int) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_303:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i3
sub %i0, %i3, %i3
sllx %l4, 32, %l6
add %l4, 1, %l4
or %l6, %l4, %l6
stx %l6, [%i3 + 0]
add %l4, 1, %l4
loop_exit_7_303:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_303
nop
P5255: !_BLD [24] (FP) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_304:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_7_304:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_304
nop
P5256: !_DWLD [9] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_305:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
P5257: !_LD [3] (Int)
lduw [%i0 + 32], %o1
! move %o1(lower) -> %o1(upper)
sllx %o1, 32, %o1
P5258: !_LD [9] (Int) (Loop exit)
lduw [%i3 + 4], %l6
! move %l6(lower) -> %o1(lower)
or %l6, %o1, %o1
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_7_305:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_305
nop
P5259: !_LD [21] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_306:
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P5260: !_LD [11] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_7_306:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_306
nop
P5261: !_LD [7] (FP) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_307:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 7
sethi %hi(0xc0000), %l6
sub %i1, %l6, %i1
ld [%i1 + 32], %f0
! 1 addresses covered
P5262: !_LD [23] (Int)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P5263: !_LD [15] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
sethi %hi(0xc0000), %o5
add %i1, %o5, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_7_307:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_307
nop
P5264: !_BLD [12] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_308:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_7_308:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_308
nop
P5265: !_DWLD [16] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_309:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
P5266: !_PREFETCH [24] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i2
sub %i0, %i2, %i2
prefetch [%i2 + 0], 1
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_7_309:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_309
nop
P5267: !_DWLD [27] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_310:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 32], %o0
! move %o0(upper) -> %o0(upper)
P5268: !_LD [21] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 4], %l6
! move %l6(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_7_310:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_310
nop
P5269: !_DWLD [14] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_311:
sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
ldx [%i3 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P5270: !_DWST [6] (maybe <- 0x43000029) (FP)
! preparing store val #0, next val will be in f21
fmovs %f16, %f21
fadds %f16, %f17, %f16
std %f20, [%i1 + 8]
P5271: !_LD [10] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_7_311:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_311
nop
P5272: !_BLD [0] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_312:
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i0 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_7_312:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_312
nop
P5273: !_LD [28] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_313:
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P5274: !_BLD [1] (FP)
wr %g0, 0xf0, %asi
membar #Sync
ldda [%i0 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P5275: !_LD [24] (Int) (Loop exit)
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 0], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_7_313:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_313
nop
P5276: !_LD [6] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_314:
lduw [%i1 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P5277: !_LD [28] (Int) (Loop exit)
sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 0], %l6
! move %l6(lower) -> %o0(lower)
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_7_314:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_314
nop
P5278: !_LD [19] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_315:
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 32], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P5279: !_LD [6] (Int) (Loop exit)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 6
sethi %hi(0xc0000), %l6
sub %i1, %l6, %i1
lduw [%i1 + 12], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
sethi %hi(0xc0000), %l3
add %i1, %l3, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_7_315:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_315
nop
P5280: !_DWLD [26] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_316:
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
ldx [%i3 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P5281: !_DWLD [16] (Int)
sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
ldx [%i2 + 0], %l6
! move %l6(upper) -> %o0(lower)
srlx %l6, 32, %l3
or %l3, %o0, %o0
! move %l6(lower) -> %o1(upper)
sllx %l6, 32, %o1
P5282: !_LD [21] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 4], %o5
! move %o5(lower) -> %o1(lower)
or %o5, %o1, %o1
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_7_316:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_316
nop
P5283: !_BLD [8] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_317:
wr %g0, 0xf0, %asi
sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_7_317:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_317
nop
P5284: !_BLD [13] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_318:
wr %g0, 0xf0, %asi
sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_7_318:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_318
nop
P5285: !_DWLD [10] (Int) (Loop entry) (LE)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_319:
wr %g0, 0x88, %asi
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i2
sub %i0, %i2, %i2
ldxa [%i2 + 8] %asi, %l7
! move %l7(upper) -> %o0(upper)
or %l7, %g0, %o0
P5286: !_LD [21] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 4], %l3
! move %l3(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_7_319:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_319
nop
P5287: !_LD [2] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_320:
lduw [%i0 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P5288: !_LD [24] (Int) (Loop exit)
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 0], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_7_320:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_320
nop
P5289: !_BLD [21] (FP) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_321:
wr %g0, 0xf0, %asi
sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
membar #Sync
ldda [%i3 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
P5290: !_DWLD [5] (Int) (Loop exit)
ldx [%i1 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_7_321:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_321
nop
P5291: !_LD [5] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_322:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 5
sethi %hi(0xc0000), %l3
sub %i1, %l3, %i1
lduw [%i1 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P5292: !_LD [5] (Int) (Loop exit)
lduw [%i1 + 4], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
sethi %hi(0xc0000), %l6
add %i1, %l6, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_7_322:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_322
nop
P5293: !_CASX [5] (maybe <- 0x3800021) (Int) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_323:
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 5
sethi %hi(0xc0000), %l7
sub %i1, %l7, %i1
ldx [%i1], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
mov %o0, %o5
sllx %l4, 32, %o1
add %l4, 1, %l4
or %l4, %o1, %o1
casx [%i1], %o5, %o1
! move %o1(upper) -> %o1(upper)
! move %o1(lower) -> %o1(lower)
add %l4, 1, %l4
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
sethi %hi(0xc0000), %o5
add %i1, %o5, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_7_323:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_323
nop
P5294: !_LD [21] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_324:
sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
lduw [%i2 + 4], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P5295: !_LD [4] (Int) (Loop exit)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 4
sethi %hi(0xc0000), %l7
sub %i1, %l7, %i1
lduw [%i1 + 0], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
sethi %hi(0xc0000), %l6
add %i1, %l6, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_7_324:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_324
nop
P5296: !_LD [26] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_325:
sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3
add %i0, %i3, %i3
lduw [%i3 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P5297: !_LD [4] (Int) (Loop exit)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 4
sethi %hi(0xc0000), %l3
sub %i1, %l3, %i1
lduw [%i1 + 0], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
sethi %hi(0xc0000), %o5
add %i1, %o5, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_7_325:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_325
nop
P5298: !_DWLD [22] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_326:
sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2
add %i0, %i2, %i2
ldx [%i2 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P5299: !_LD [21] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 4], %l3
! move %l3(lower) -> %o0(lower)
or %l3, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_7_326:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_326
nop
P5300: !_BLD [22] (FP) (Loop entry) (Loop exit)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_327:
wr %g0, 0xf0, %asi
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i2
sub %i0, %i2, %i2
membar #Sync
ldda [%i2 + 0] %asi, %f0
membar #Sync
! 4 addresses covered
fmovs %f3, %f2
fmovs %f8, %f3
!---- flushing fp results buffer to %f30 ----
fmovd %f0, %f30
fmovd %f2, %f30
!--
loop_exit_7_327:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_327
nop
P5301: !_DWLD [26] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_328:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 8], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P5302: !_LD [3] (Int) (Loop exit) (CBR)
lduw [%i0 + 32], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
! cbranch
andcc %l0, 1, %g0
be,pn %xcc, TARGET5302
nop
RET5302:
! lfsr step begin
srlx %l0, 1, %l3
xnor %l3, %l0, %l3
sllx %l3, 63, %l3
or %l3, %l0, %l0
srlx %l0, 1, %l0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_7_328:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_328
nop
P5303: !_DWLD [9] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_329:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
P5304: !_DWLD [11] (Int)
ldx [%i2 + 32], %o1
! move %o1(upper) -> %o1(upper)
P5305: !_LD [15] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %l6
! move %l6(lower) -> %o1(lower)
srlx %o1, 32, %o1
sllx %o1, 32, %o1
or %l6, %o1, %o1
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_7_329:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_329
nop
P5306: !_LD [25] (Int) (Loop entry) (LE)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_330:
wr %g0, 0x88, %asi
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduwa [%i2 + 4] %asi, %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P5307: !_LD [23] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 32], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_7_330:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_330
nop
P5308: !_DWLD [27] (Int) (Loop entry)
sethi %hi(0x1), %l2
or %l2, %lo(0x1), %l2
loop_entry_7_331:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 32], %o0
! move %o0(upper) -> %o0(upper)
P5309: !_LD [7] (Int) (Loop exit)
!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
!Logical addr: 7
sethi %hi(0xc0000), %o5
sub %i1, %o5, %i1
lduw [%i1 + 32], %l6
! move %l6(lower) -> %o0(lower)
srlx %o0, 32, %o0
sllx %o0, 32, %o0
or %l6, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
sethi %hi(0xc0000), %l7
add %i1, %l7, %i1
!-- End Aliased access: base register for region 1 (%i1) restored
loop_exit_7_331:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_331
nop
P5310: !_DWLD [23] (Int) (Loop entry) (LE)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_332:
wr %g0, 0x88, %asi
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
sub %i0, %i3, %i3
ldxa [%i3 + 32] %asi, %l3
! move %l3(lower) -> %o0(upper)
sllx %l3, 32, %o0
P5311: !_LD [19] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 32], %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_7_332:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_332
nop
P5312: !_LD [20] (Int) (Loop entry) (CBR)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_333:
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
sub %i0, %i3, %i3
lduw [%i3 + 0], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
! cbranch
andcc %l0, 1, %g0
be,pt %xcc, TARGET5312
nop
RET5312:
! lfsr step begin
srlx %l0, 1, %o5
xnor %o5, %l0, %o5
sllx %o5, 63, %o5
or %o5, %l0, %l0
srlx %l0, 1, %l0
P5313: !_LD [19] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 32], %l7
! move %l7(lower) -> %o0(lower)
or %l7, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_7_333:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_333
nop
P5314: !_DWLD [12] (Int) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_334:
sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_7_334:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_334
nop
P5315: !_LD [22] (Int) (Loop entry)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_335:
sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i2
sub %i0, %i2, %i2
lduw [%i2 + 12], %o0
! move %o0(lower) -> %o0(upper)
sllx %o0, 32, %o0
P5316: !_LD [27] (Int) (Loop exit) (LE)
wr %g0, 0x88, %asi
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
sub %i0, %i3, %i3
lduwa [%i3 + 32] %asi, %o5
! move %o5(lower) -> %o0(lower)
or %o5, %o0, %o0
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_7_335:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_335
nop
P5317: !_DWLD [25] (Int) (Loop entry) (Loop exit)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_336:
sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
!---- flushing int results buffer----
mov %o0, %l5
loop_exit_7_336:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_336
nop
P5318: !_DWLD [9] (Int) (Loop entry) (Branch target of P5312)
sethi %hi(0x2), %l2
or %l2, %lo(0x2), %l2
loop_entry_7_337:
sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
sub %i0, %i3, %i3
ldx [%i3 + 0], %o0
! move %o0(upper) -> %o0(upper)
! move %o0(lower) -> %o0(lower)
ba P5319
nop
TARGET5312:
ba RET5312
nop
P5319: !_DWLD [28] (Int) (Loop exit)
sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
sub %i0, %i2, %i2
ldx [%i2 + 0], %o1
! move %o1(upper) -> %o1(upper)
! move %o1(lower) -> %o1(lower)
!---- flushing int results buffer----
mov %o0, %l5
mov %o1, %l5
loop_exit_7_337:
sub %l2, 1, %l2
cmp %l2, 0
bg loop_entry_7_337
nop
P5320: !_MEMBAR (Int)
membar #StoreLoad
END_NODES7: ! Test instruction sequence for CPU 7 ends
sethi %hi(0xdead0e0f), %o5
or %o5, %lo(0xdead0e0f), %o5
! move %o5(lower) -> %o0(upper)
sllx %o5, 32, %o0
stw %o5, [%i5]
ld [%i5], %f0
!---- flushing int results buffer----
mov %o0, %l5
!---- flushing fp results buffer to %f30 ----
fmovs %f0, %f30
!--
restore
retl
nop
tsotool_text_end:
!#0 N1 P1 BLD 28 -1 FP BE Pri
!#0 N2 P1 BLD 29 -1 FP BE Pri
!#A N1 N2
!#0 N3 P1 BLD 30 -1 FP BE Pri
!#0 N4 P1 BLD 31 -1 FP BE Pri
!#0 N5 P2 BLD 0 -1 FP BE Pri
!#0 N6 P2 BLD 1 -1 FP BE Pri
!#A N5 N6
!#0 N7 P2 BLD 2 -1 FP BE Pri
!#0 N8 P2 BLD 3 -1 FP BE Pri
!#0 N9 P3 LD 9 -1 Int BE Pri
!#0 N10 P4 LD 0 -1 Int LE Pri
!#0 N11 P2 BLD 0 -1 FP BE Pri
!#0 N12 P2 BLD 1 -1 FP BE Pri
!#A N11 N12
!#0 N13 P2 BLD 2 -1 FP BE Pri
!#0 N14 P2 BLD 3 -1 FP BE Pri
!#0 N15 P3 LD 9 -1 Int BE Pri
!#0 N16 P4 LD 0 -1 Int LE Pri
!#0 N17 P5 LD 22 -1 Int BE Pri
!#0 N18 P6 LD 14 -1 Int BE Pri
!#0 N19 P5 LD 22 -1 Int BE Pri
!#0 N20 P6 LD 14 -1 Int BE Pri
!#0 N21 P7 LD 16 -1 FP BE Pri
!#0 N22 P7 LD 16 -1 FP BE Pri
!#0 N23 P8 BLD 8 -1 FP BE Pri
!#0 N24 P8 BLD 9 -1 FP BE Pri
!#A N23 N24
!#0 N25 P8 BLD 10 -1 FP BE Pri
!#0 N26 P8 BLD 11 -1 FP BE Pri
!#0 N27 P8 BLD 8 -1 FP BE Pri
!#0 N28 P8 BLD 9 -1 FP BE Pri
!#A N27 N28
!#0 N29 P8 BLD 10 -1 FP BE Pri
!#0 N30 P8 BLD 11 -1 FP BE Pri
!#0 N32 P10 BLD 24 -1 FP BE Pri
!#0 N33 P10 BLD 25 -1 FP BE Pri
!#A N32 N33
!#0 N34 P10 BLD 26 -1 FP BE Pri
!#0 N35 P10 BLD 27 -1 FP BE Pri
!#0 N37 P10 BLD 24 -1 FP BE Pri
!#0 N38 P10 BLD 25 -1 FP BE Pri
!#A N37 N38
!#0 N39 P10 BLD 26 -1 FP BE Pri
!#0 N40 P10 BLD 27 -1 FP BE Pri
!#0 N41 P11 DWLD 16 -1 Int BE Pri
!#0 N42 P11 DWLD 17 -1 Int BE Pri
!#A N41 N42
!#0 N43 P12 DWLD 12 -1 Int BE Pri
!#0 N44 P12 DWLD 13 -1 Int BE Pri
!#A N43 N44
!#0 N45 P13 BLD 28 -1 FP BE Pri
!#0 N46 P13 BLD 29 -1 FP BE Pri
!#A N45 N46
!#0 N47 P13 BLD 30 -1 FP BE Pri
!#0 N48 P13 BLD 31 -1 FP BE Pri
!#0 N49 P12 DWLD 12 -1 Int BE Pri
!#0 N50 P12 DWLD 13 -1 Int BE Pri
!#A N49 N50
!#0 N51 P13 BLD 28 -1 FP BE Pri
!#0 N52 P13 BLD 29 -1 FP BE Pri
!#A N51 N52
!#0 N53 P13 BLD 30 -1 FP BE Pri
!#0 N54 P13 BLD 31 -1 FP BE Pri
!#0 N55 P14 LD 23 -1 Int BE Pri
!#0 N56 P14 CAS 23 -1 N55 0x1 Int BE Pri
!#0 N57 P14 LD 23 -1 Int BE Pri
!#0 N58 P14 CAS 23 -1 N57 0x2 Int BE Pri
!#0 N59 P15 BLD 8 -1 FP BE Pri
!#0 N60 P15 BLD 9 -1 FP BE Pri
!#A N59 N60
!#0 N61 P15 BLD 10 -1 FP BE Pri
!#0 N62 P15 BLD 11 -1 FP BE Pri
!#0 N63 P15 BLD 8 -1 FP BE Pri
!#0 N64 P15 BLD 9 -1 FP BE Pri
!#A N63 N64
!#0 N65 P15 BLD 10 -1 FP BE Pri
!#0 N66 P15 BLD 11 -1 FP BE Pri
!#0 N67 P16 BLD 8 -1 FP BE Pri
!#0 N68 P16 BLD 9 -1 FP BE Pri
!#A N67 N68
!#0 N69 P16 BLD 10 -1 FP BE Pri
!#0 N70 P16 BLD 11 -1 FP BE Pri
!#0 N71 P17 LD 5 -1 Int BE Pri
!#0 N72 P18 LD 21 -1 Int BE Pri
!#0 N73 P19 LD 3 -1 Int BE Pri
!#0 N74 P20 LD 3 -1 Int BE Pri
!#0 N75 P21 BLD 8 -1 FP BE Pri
!#0 N76 P21 BLD 9 -1 FP BE Pri
!#A N75 N76
!#0 N77 P21 BLD 10 -1 FP BE Pri
!#0 N78 P21 BLD 11 -1 FP BE Pri
!#0 N79 P22 BLD 20 -1 FP BE Pri
!#0 N80 P22 BLD 21 -1 FP BE Pri
!#A N79 N80
!#0 N81 P22 BLD 22 -1 FP BE Pri
!#0 N82 P22 BLD 23 -1 FP BE Pri
!#0 N83 P23 DWLD 24 -1 Int BE Pri
!#0 N84 P23 DWLD 25 -1 Int BE Pri
!#A N83 N84
!#0 N85 P23 CASX 24 -1 N83 0x3 Int BE Pri
!#0 N86 P23 CASX 25 -1 N84 0x4 Int BE Pri
!#A N85 N86
!#0 N87 P24 BST 24 0x3f800001 FP BE Pri
!#0 N88 P24 BST 25 0x3f800002 FP BE Pri
!#A N87 N88
!#0 N89 P24 BST 26 0x3f800003 FP BE Pri
!#0 N90 P24 BST 27 0x3f800004 FP BE Pri
!#0 N91 P25 LD 29 -1 Int BE Pri
!#0 N92 P26 LD 11 -1 Int BE Pri
!#0 N93 P27 LD 25 -1 Int BE Pri
!#0 N94 P28 LD 1 -1 Int BE Pri
!#0 N95 P27 LD 25 -1 Int BE Pri
!#0 N96 P28 LD 1 -1 Int BE Pri
!#0 N97 P29 ST 11 0x5 Int BE Pri
!#0 N98 P29 ST 11 0x6 Int BE Pri
!#0 N99 P30 DWLD 19 -1 Int BE Pri
!#0 N100 P31 LD 19 -1 Int BE Pri
!#0 N101 P32 LD 3 -1 Int BE Pri
!#0 N102 P33 LD 8 -1 FP BE Pri
!#0 N103 P34 LD 15 -1 Int BE Pri
!#0 N104 P32 LD 3 -1 Int BE Pri
!#0 N105 P33 LD 8 -1 FP BE Pri
!#0 N106 P34 LD 15 -1 Int BE Pri
!#0 N107 P35 SWAP 6 0xffffffff 0x7 Int BE Pri
!#0 N108 P36 BLD 28 -1 FP BE Pri
!#0 N109 P36 BLD 29 -1 FP BE Pri
!#A N108 N109
!#0 N110 P36 BLD 30 -1 FP BE Pri
!#0 N111 P36 BLD 31 -1 FP BE Pri
!#0 N112 P37 LD 0 -1 Int BE Pri
!#0 N113 P35 SWAP 6 0xffffffff 0x8 Int BE Pri
!#0 N114 P36 BLD 28 -1 FP BE Pri
!#0 N115 P36 BLD 29 -1 FP BE Pri
!#A N114 N115
!#0 N116 P36 BLD 30 -1 FP BE Pri
!#0 N117 P36 BLD 31 -1 FP BE Pri
!#0 N118 P37 LD 0 -1 Int BE Pri
!#0 N119 P38 BLD 24 -1 FP BE Pri
!#0 N120 P38 BLD 25 -1 FP BE Pri
!#A N119 N120
!#0 N121 P38 BLD 26 -1 FP BE Pri
!#0 N122 P38 BLD 27 -1 FP BE Pri
!#0 N123 P39 BLD 0 -1 FP BE Pri
!#0 N124 P39 BLD 1 -1 FP BE Pri
!#A N123 N124
!#0 N125 P39 BLD 2 -1 FP BE Pri
!#0 N126 P39 BLD 3 -1 FP BE Pri
!#0 N127 P40 BLD 16 -1 FP BE Pri
!#0 N128 P40 BLD 17 -1 FP BE Pri
!#A N127 N128
!#0 N129 P40 BLD 18 -1 FP BE Pri
!#0 N130 P40 BLD 19 -1 FP BE Pri
!#0 N131 P41 DWLD 16 -1 Int BE Pri
!#0 N132 P41 DWLD 17 -1 Int BE Pri
!#A N131 N132
!#0 N133 P40 BLD 16 -1 FP BE Pri
!#0 N134 P40 BLD 17 -1 FP BE Pri
!#A N133 N134
!#0 N135 P40 BLD 18 -1 FP BE Pri
!#0 N136 P40 BLD 19 -1 FP BE Pri
!#0 N137 P41 DWLD 16 -1 Int BE Pri
!#0 N138 P41 DWLD 17 -1 Int BE Pri
!#A N137 N138
!#0 N139 P42 BLD 8 -1 FP BE Pri
!#0 N140 P42 BLD 9 -1 FP BE Pri
!#A N139 N140
!#0 N141 P42 BLD 10 -1 FP BE Pri
!#0 N142 P42 BLD 11 -1 FP BE Pri
!#0 N143 P43 BLD 12 -1 FP BE Pri
!#0 N144 P43 BLD 13 -1 FP BE Pri
!#A N143 N144
!#0 N145 P43 BLD 14 -1 FP BE Pri
!#0 N146 P43 BLD 15 -1 FP BE Pri
!#0 N147 P42 BLD 8 -1 FP BE Pri
!#0 N148 P42 BLD 9 -1 FP BE Pri
!#A N147 N148
!#0 N149 P42 BLD 10 -1 FP BE Pri
!#0 N150 P42 BLD 11 -1 FP BE Pri
!#0 N151 P43 BLD 12 -1 FP BE Pri
!#0 N152 P43 BLD 13 -1 FP BE Pri
!#A N151 N152
!#0 N153 P43 BLD 14 -1 FP BE Pri
!#0 N154 P43 BLD 15 -1 FP BE Pri
!#0 N155 P44 DWLD 23 -1 Int BE Pri
!#0 N156 P45 DWLD 24 -1 Int BE Pri
!#0 N157 P45 DWLD 25 -1 Int BE Pri
!#A N156 N157
!#0 N158 P46 LD 10 -1 Int BE Pri
!#0 N159 P44 DWLD 23 -1 Int BE Pri
!#0 N160 P45 DWLD 24 -1 Int BE Pri
!#0 N161 P45 DWLD 25 -1 Int BE Pri
!#A N160 N161
!#0 N162 P46 LD 10 -1 Int BE Pri
!#0 N163 P47 LD 21 -1 Int BE Pri
!#0 N164 P48 LD 8 -1 Int BE Pri
!#0 N165 P47 LD 21 -1 Int BE Pri
!#0 N166 P48 LD 8 -1 Int BE Pri
!#0 N167 P49 BLD 0 -1 FP BE Pri
!#0 N168 P49 BLD 1 -1 FP BE Pri
!#A N167 N168
!#0 N169 P49 BLD 2 -1 FP BE Pri
!#0 N170 P49 BLD 3 -1 FP BE Pri
!#0 N171 P49 BLD 0 -1 FP BE Pri
!#0 N172 P49 BLD 1 -1 FP BE Pri
!#A N171 N172
!#0 N173 P49 BLD 2 -1 FP BE Pri
!#0 N174 P49 BLD 3 -1 FP BE Pri
!#0 N175 P50 BLD 24 -1 FP BE Pri
!#0 N176 P50 BLD 25 -1 FP BE Pri
!#A N175 N176
!#0 N177 P50 BLD 26 -1 FP BE Pri
!#0 N178 P50 BLD 27 -1 FP BE Pri
!#0 N179 P51 ST 5 0x9 Int BE Pri
!#0 N180 P52 DWLD 2 -1 Int BE Pri
!#0 N181 P53 LD 4 -1 Int BE Pri
!#0 N182 P54 DWLD 8 -1 Int BE Pri
!#0 N183 P54 DWLD 9 -1 Int BE Pri
!#A N182 N183
!#0 N184 P55 DWLD 31 -1 FP BE Pri
!#0 N185 P54 DWLD 8 -1 Int BE Pri
!#0 N186 P54 DWLD 9 -1 Int BE Pri
!#A N185 N186
!#0 N187 P55 DWLD 31 -1 FP BE Pri
!#0 N188 P56 DWLD 24 -1 Int BE Pri
!#0 N189 P56 DWLD 25 -1 Int BE Pri
!#A N188 N189
!#0 N190 P56 CASX 24 -1 N188 0xa Int BE Pri
!#0 N191 P56 CASX 25 -1 N189 0xb Int BE Pri
!#A N190 N191
!#0 N192 P56 DWLD 24 -1 Int BE Pri
!#0 N193 P56 DWLD 25 -1 Int BE Pri
!#A N192 N193
!#0 N194 P56 CASX 24 -1 N192 0xc Int BE Pri
!#0 N195 P56 CASX 25 -1 N193 0xd Int BE Pri
!#A N194 N195
!#0 N196 P57 LD 4 -1 Int BE Pri
!#0 N197 P58 BSTC 24 0x3f800005 FP BE Pri
!#0 N198 P58 BSTC 25 0x3f800006 FP BE Pri
!#A N197 N198
!#0 N199 P58 BSTC 26 0x3f800007 FP BE Pri
!#0 N200 P58 BSTC 27 0x3f800008 FP BE Pri
!#0 N201 P59 LD 29 -1 Int BE Pri
!#0 N202 P57 LD 4 -1 Int BE Pri
!#0 N203 P58 BSTC 24 0x3f800009 FP BE Pri
!#0 N204 P58 BSTC 25 0x3f80000a FP BE Pri
!#A N203 N204
!#0 N205 P58 BSTC 26 0x3f80000b FP BE Pri
!#0 N206 P58 BSTC 27 0x3f80000c FP BE Pri
!#0 N207 P59 LD 29 -1 Int BE Pri
!#0 N208 P60 LD 27 -1 Int BE Pri
!#0 N209 P61 LD 19 -1 Int BE Pri
!#0 N210 P62 LD 23 -1 Int BE Pri
!#0 N211 P63 LD 21 -1 Int LE Pri
!#0 N212 P63 CAS 21 -1 N211 0xe Int LE Pri
!#0 N213 P64 LD 4 -1 Int BE Pri
!#0 N214 P62 LD 23 -1 Int BE Pri
!#0 N215 P63 LD 21 -1 Int LE Pri
!#0 N216 P63 CAS 21 -1 N215 0xf Int LE Pri
!#0 N217 P64 LD 4 -1 Int BE Pri
!#0 N218 P65 DWLD 6 -1 Int BE Pri
!#0 N219 P66 LD 26 -1 Int BE Pri
!#0 N220 P67 DWLD 24 -1 Int BE Pri
!#0 N221 P67 DWLD 25 -1 Int BE Pri
!#A N220 N221
!#0 N222 P67 DWLD 24 -1 Int BE Pri
!#0 N223 P67 DWLD 25 -1 Int BE Pri
!#A N222 N223
!#0 N224 P68 BLD 20 -1 FP BE Pri
!#0 N225 P68 BLD 21 -1 FP BE Pri
!#A N224 N225
!#0 N226 P68 BLD 22 -1 FP BE Pri
!#0 N227 P68 BLD 23 -1 FP BE Pri
!#0 N228 P69 BLD 20 -1 FP BE Pri
!#0 N229 P69 BLD 21 -1 FP BE Pri
!#A N228 N229
!#0 N230 P69 BLD 22 -1 FP BE Pri
!#0 N231 P69 BLD 23 -1 FP BE Pri
!#0 N232 P70 LD 29 -1 Int BE Pri
!#0 N233 P71 LD 21 -1 Int BE Pri
!#0 N234 P69 BLD 20 -1 FP BE Pri
!#0 N235 P69 BLD 21 -1 FP BE Pri
!#A N234 N235
!#0 N236 P69 BLD 22 -1 FP BE Pri
!#0 N237 P69 BLD 23 -1 FP BE Pri
!#0 N238 P70 LD 29 -1 Int BE Pri
!#0 N239 P71 LD 21 -1 Int BE Pri
!#0 N240 P72 LD 17 -1 Int BE Pri
!#0 N241 P73 LD 28 -1 Int BE Pri
!#0 N242 P72 LD 17 -1 Int BE Pri
!#0 N243 P73 LD 28 -1 Int BE Pri
!#0 N244 P74 LD 3 -1 Int BE Pri
!#0 N245 P75 LD 8 -1 Int BE Pri
!#0 N246 P74 LD 3 -1 Int BE Pri
!#0 N247 P75 LD 8 -1 Int BE Pri
!#0 N248 P76 DWLD 7 -1 Int BE Pri
!#0 N249 P77 LD 1 -1 Int BE Pri
!#0 N250 P76 DWLD 7 -1 Int BE Pri
!#0 N251 P77 LD 1 -1 Int BE Pri
!#0 N252 P78 LD 28 -1 Int BE Pri
!#0 N253 P78 CAS 28 -1 N252 0x10 Int BE Pri
!#0 N254 P79 DWLD 8 -1 Int BE Pri
!#0 N255 P79 DWLD 9 -1 Int BE Pri
!#A N254 N255
!#0 N256 P78 LD 28 -1 Int BE Pri
!#0 N257 P78 CAS 28 -1 N256 0x11 Int BE Pri
!#0 N258 P79 DWLD 8 -1 Int BE Pri
!#0 N259 P79 DWLD 9 -1 Int BE Pri
!#A N258 N259
!#0 N260 P80 MEMBAR
!#0 N261 P81 BLD 16 -1 FP BE Pri
!#0 N262 P81 BLD 17 -1 FP BE Pri
!#A N261 N262
!#0 N263 P81 BLD 18 -1 FP BE Pri
!#0 N264 P81 BLD 19 -1 FP BE Pri
!#0 N265 P81 BLD 16 -1 FP BE Pri
!#0 N266 P81 BLD 17 -1 FP BE Pri
!#A N265 N266
!#0 N267 P81 BLD 18 -1 FP BE Pri
!#0 N268 P81 BLD 19 -1 FP BE Pri
!#0 N269 P82 DWLD 24 -1 Int BE Pri
!#0 N270 P82 DWLD 25 -1 Int BE Pri
!#A N269 N270
!#0 N271 P83 BLD 20 -1 FP BE Pri
!#0 N272 P83 BLD 21 -1 FP BE Pri
!#A N271 N272
!#0 N273 P83 BLD 22 -1 FP BE Pri
!#0 N274 P83 BLD 23 -1 FP BE Pri
!#0 N275 P82 DWLD 24 -1 Int BE Pri
!#0 N276 P82 DWLD 25 -1 Int BE Pri
!#A N275 N276
!#0 N277 P83 BLD 20 -1 FP BE Pri
!#0 N278 P83 BLD 21 -1 FP BE Pri
!#A N277 N278
!#0 N279 P83 BLD 22 -1 FP BE Pri
!#0 N280 P83 BLD 23 -1 FP BE Pri
!#0 N281 P84 LD 5 -1 Int BE Pri
!#0 N282 P85 BLD 28 -1 FP BE Pri
!#0 N283 P85 BLD 29 -1 FP BE Pri
!#A N282 N283
!#0 N284 P85 BLD 30 -1 FP BE Pri
!#0 N285 P85 BLD 31 -1 FP BE Pri
!#0 N286 P86 LD 9 -1 Int BE Pri
!#0 N287 P84 LD 5 -1 Int BE Pri
!#0 N288 P85 BLD 28 -1 FP BE Pri
!#0 N289 P85 BLD 29 -1 FP BE Pri
!#A N288 N289
!#0 N290 P85 BLD 30 -1 FP BE Pri
!#0 N291 P85 BLD 31 -1 FP BE Pri
!#0 N292 P86 LD 9 -1 Int BE Pri
!#0 N293 P87 LD 27 -1 Int LE Pri
!#0 N294 P88 DWLD 3 -1 FP BE Pri
!#0 N295 P89 LD 27 -1 Int BE Pri
!#0 N296 P87 LD 27 -1 Int LE Pri
!#0 N297 P88 DWLD 3 -1 FP BE Pri
!#0 N298 P89 LD 27 -1 Int BE Pri
!#0 N299 P90 LD 4 -1 Int BE Pri
!#0 N300 P91 LD 22 -1 Int BE Pri
!#0 N301 P92 BLD 8 -1 FP BE Pri
!#0 N302 P92 BLD 9 -1 FP BE Pri
!#A N301 N302
!#0 N303 P92 BLD 10 -1 FP BE Pri
!#0 N304 P92 BLD 11 -1 FP BE Pri
!#0 N305 P92 BLD 8 -1 FP BE Pri
!#0 N306 P92 BLD 9 -1 FP BE Pri
!#A N305 N306
!#0 N307 P92 BLD 10 -1 FP BE Pri
!#0 N308 P92 BLD 11 -1 FP BE Pri
!#0 N309 P93 LD 25 -1 Int BE Pri
!#0 N310 P94 LD 14 -1 Int BE Pri
!#0 N311 P93 LD 25 -1 Int BE Pri
!#0 N312 P94 LD 14 -1 Int BE Pri
!#0 N313 P95 LD 23 -1 FP BE Pri
!#0 N314 P96 DWLD 7 -1 FP BE Pri
!#0 N315 P95 LD 23 -1 FP BE Pri
!#0 N316 P96 DWLD 7 -1 FP BE Pri
!#0 N321 P99 BLD 24 -1 FP BE Pri
!#0 N322 P99 BLD 25 -1 FP BE Pri
!#A N321 N322
!#0 N323 P99 BLD 26 -1 FP BE Pri
!#0 N324 P99 BLD 27 -1 FP BE Pri
!#0 N325 P100 DWLD 7 -1,0x0 Int BE Pri
!#0 N326 P100 CASX 7 -1,0x0 N325 0x12 Int BE Pri
!#0 N327 P99 BLD 24 -1 FP BE Pri
!#0 N328 P99 BLD 25 -1 FP BE Pri
!#A N327 N328
!#0 N329 P99 BLD 26 -1 FP BE Pri
!#0 N330 P99 BLD 27 -1 FP BE Pri
!#0 N331 P100 DWLD 7 -1,0x0 Int BE Pri
!#0 N332 P100 CASX 7 -1,0x0 N331 0x13 Int BE Pri
!#0 N333 P101 LD 26 -1 Int BE Pri
!#0 N334 P102 DWLD 3 -1 Int BE Pri
!#0 N335 P101 LD 26 -1 Int BE Pri
!#0 N336 P102 DWLD 3 -1 Int BE Pri
!#0 N337 P103 DWLD 12 -1 Int BE Pri
!#0 N338 P103 DWLD 13 -1 Int BE Pri
!#A N337 N338
!#0 N339 P104 LD 15 -1 Int BE Pri
!#0 N340 P105 LD 4 -1 Int BE Pri
!#0 N341 P104 LD 15 -1 Int BE Pri
!#0 N342 P105 LD 4 -1 Int BE Pri
!#0 N343 P106 DWLD 4 -1 Int BE Pri
!#0 N344 P106 DWLD 5 -1 Int BE Pri
!#A N343 N344
!#0 N345 P106 DWLD 4 -1 Int BE Pri
!#0 N346 P106 DWLD 5 -1 Int BE Pri
!#A N345 N346
!#0 N347 P107 BLD 0 -1 FP BE Pri
!#0 N348 P107 BLD 1 -1 FP BE Pri
!#A N347 N348
!#0 N349 P107 BLD 2 -1 FP BE Pri
!#0 N350 P107 BLD 3 -1 FP BE Pri
!#0 N351 P108 LD 18 -1 Int BE Pri
!#0 N352 P109 DWLD 15 -1 Int BE Pri
!#0 N353 P108 LD 18 -1 Int BE Pri
!#0 N354 P109 DWLD 15 -1 Int BE Pri
!#0 N355 P110 BLD 12 -1 FP BE Pri
!#0 N356 P110 BLD 13 -1 FP BE Pri
!#A N355 N356
!#0 N357 P110 BLD 14 -1 FP BE Pri
!#0 N358 P110 BLD 15 -1 FP BE Pri
!#0 N359 P111 BLD 20 -1 FP BE Pri
!#0 N360 P111 BLD 21 -1 FP BE Pri
!#A N359 N360
!#0 N361 P111 BLD 22 -1 FP BE Pri
!#0 N362 P111 BLD 23 -1 FP BE Pri
!#0 N363 P111 BLD 20 -1 FP BE Pri
!#0 N364 P111 BLD 21 -1 FP BE Pri
!#A N363 N364
!#0 N365 P111 BLD 22 -1 FP BE Pri
!#0 N366 P111 BLD 23 -1 FP BE Pri
!#0 N367 P112 DWLD 15 -1 Int BE Pri
!#0 N368 P113 LD 6 -1 Int BE Pri
!#0 N369 P112 DWLD 15 -1 Int BE Pri
!#0 N370 P113 LD 6 -1 Int BE Pri
!#0 N371 P114 LD 4 -1 Int BE Pri
!#0 N372 P115 LD 13 -1 Int LE Pri
!#0 N375 P117 LD 31 -1 FP BE Pri
!#0 N376 P118 LD 5 -1 Int BE Pri
!#0 N377 P119 LD 23 -1 Int BE Pri
!#0 N378 P120 DWLD 16 -1 Int BE Pri
!#0 N379 P120 DWLD 17 -1 Int BE Pri
!#A N378 N379
!#0 N380 P120 DWLD 16 -1 Int BE Pri
!#0 N381 P120 DWLD 17 -1 Int BE Pri
!#A N380 N381
!#0 N382 P121 LD 10 -1 FP BE Pri
!#0 N383 P122 BLD 8 -1 FP BE Pri
!#0 N384 P122 BLD 9 -1 FP BE Pri
!#A N383 N384
!#0 N385 P122 BLD 10 -1 FP BE Pri
!#0 N386 P122 BLD 11 -1 FP BE Pri
!#0 N387 P123 BLD 24 -1 FP BE Pri
!#0 N388 P123 BLD 25 -1 FP BE Pri
!#A N387 N388
!#0 N389 P123 BLD 26 -1 FP BE Pri
!#0 N390 P123 BLD 27 -1 FP BE Pri
!#0 N391 P124 LD 30 -1 Int BE Pri
!#0 N392 P125 LD 28 -1 Int BE Pri
!#0 N393 P126 BLD 20 -1 FP BE Pri
!#0 N394 P126 BLD 21 -1 FP BE Pri
!#A N393 N394
!#0 N395 P126 BLD 22 -1 FP BE Pri
!#0 N396 P126 BLD 23 -1 FP BE Pri
!#0 N397 P127 DWLD 31 -1 Int BE Pri
!#0 N398 P128 LD 4 -1 Int BE Pri
!#0 N399 P129 DWLD 15 -1 Int BE Pri
!#0 N400 P130 DWLD 26 -1 Int BE Pri
!#0 N401 P129 DWLD 15 -1 Int BE Pri
!#0 N402 P130 DWLD 26 -1 Int BE Pri
!#0 N403 P131 BSTC 20 0x3f80000d FP BE Pri
!#0 N404 P131 BSTC 21 0x3f80000e FP BE Pri
!#A N403 N404
!#0 N405 P131 BSTC 22 0x3f80000f FP BE Pri
!#0 N406 P131 BSTC 23 0x3f800010 FP BE Pri
!#0 N407 P132 BLD 4 -1 FP BE Pri
!#0 N408 P132 BLD 5 -1 FP BE Pri
!#A N407 N408
!#0 N409 P132 BLD 6 -1 FP BE Pri
!#0 N410 P132 BLD 7 -1 FP BE Pri
!#0 N411 P131 BSTC 20 0x3f800011 FP BE Pri
!#0 N412 P131 BSTC 21 0x3f800012 FP BE Pri
!#A N411 N412
!#0 N413 P131 BSTC 22 0x3f800013 FP BE Pri
!#0 N414 P131 BSTC 23 0x3f800014 FP BE Pri
!#0 N415 P132 BLD 4 -1 FP BE Pri
!#0 N416 P132 BLD 5 -1 FP BE Pri
!#A N415 N416
!#0 N417 P132 BLD 6 -1 FP BE Pri
!#0 N418 P132 BLD 7 -1 FP BE Pri
!#0 N419 P133 BLD 16 -1 FP BE Pri
!#0 N420 P133 BLD 17 -1 FP BE Pri
!#A N419 N420
!#0 N421 P133 BLD 18 -1 FP BE Pri
!#0 N422 P133 BLD 19 -1 FP BE Pri
!#0 N423 P134 DWLD 16 -1 Int BE Pri
!#0 N424 P134 DWLD 17 -1 Int BE Pri
!#A N423 N424
!#0 N425 P135 BLD 4 -1 FP BE Pri
!#0 N426 P135 BLD 5 -1 FP BE Pri
!#A N425 N426
!#0 N427 P135 BLD 6 -1 FP BE Pri
!#0 N428 P135 BLD 7 -1 FP BE Pri
!#0 N429 P136 DWLD 16 -1 Int LE Pri
!#0 N430 P136 DWLD 17 -1 Int LE Pri
!#A N429 N430
!#0 N431 P136 DWLD 16 -1 Int LE Pri
!#0 N432 P136 DWLD 17 -1 Int LE Pri
!#A N431 N432
!#0 N433 P137 DWLD 7 -1 Int BE Pri
!#0 N434 P138 LD 27 -1 Int BE Pri
!#0 N435 P139 LD 2 -1 Int BE Pri
!#0 N436 P140 LD 10 -1 FP BE Pri
!#0 N437 P141 LD 10 -1 Int BE Pri
!#0 N438 P142 LD 10 -1 Int LE Pri
!#0 N439 P143 LD 8 -1 Int BE Pri
!#0 N440 P142 LD 10 -1 Int LE Pri
!#0 N441 P143 LD 8 -1 Int BE Pri
!#0 N442 P144 BLD 24 -1 FP BE Pri
!#0 N443 P144 BLD 25 -1 FP BE Pri
!#A N442 N443
!#0 N444 P144 BLD 26 -1 FP BE Pri
!#0 N445 P144 BLD 27 -1 FP BE Pri
!#0 N446 P145 BLD 20 -1 FP BE Pri
!#0 N447 P145 BLD 21 -1 FP BE Pri
!#A N446 N447
!#0 N448 P145 BLD 22 -1 FP BE Pri
!#0 N449 P145 BLD 23 -1 FP BE Pri
!#0 N450 P146 BLD 20 -1 FP BE Pri
!#0 N451 P146 BLD 21 -1 FP BE Pri
!#A N450 N451
!#0 N452 P146 BLD 22 -1 FP BE Pri
!#0 N453 P146 BLD 23 -1 FP BE Pri
!#0 N454 P147 LD 12 -1 Int BE Pri
!#0 N455 P148 LD 14 -1 Int BE Pri
!#0 N456 P146 BLD 20 -1 FP BE Pri
!#0 N457 P146 BLD 21 -1 FP BE Pri
!#A N456 N457
!#0 N458 P146 BLD 22 -1 FP BE Pri
!#0 N459 P146 BLD 23 -1 FP BE Pri
!#0 N460 P147 LD 12 -1 Int BE Pri
!#0 N461 P148 LD 14 -1 Int BE Pri
!#0 N462 P149 SWAP 3 0xffffffff 0x14 Int BE Pri
!#0 N463 P150 DWLD 18 -1 Int BE Pri
!#0 N464 P151 LD 5 -1 Int BE Pri
!#0 N465 P151 CAS 5 -1 N464 0x15 Int BE Pri
!#0 N466 P152 BLD 0 -1 FP BE Pri
!#0 N467 P152 BLD 1 -1 FP BE Pri
!#A N466 N467
!#0 N468 P152 BLD 2 -1 FP BE Pri
!#0 N469 P152 BLD 3 -1 FP BE Pri
!#0 N470 P153 LD 28 -1 Int BE Pri
!#0 N471 P154 LD 5 -1 Int BE Pri
!#0 N472 P153 LD 28 -1 Int BE Pri
!#0 N473 P154 LD 5 -1 Int BE Pri
!#0 N474 P155 DWLD 31 -1,0x0 Int BE Pri
!#0 N475 P155 CASX 31 -1,0x0 N474 0x16 Int BE Pri
!#0 N476 P156 DWLD 20 -1 Int BE Pri
!#0 N477 P156 DWLD 21 -1 Int BE Pri
!#A N476 N477
!#0 N478 P157 BLD 20 -1 FP BE Pri
!#0 N479 P157 BLD 21 -1 FP BE Pri
!#A N478 N479
!#0 N480 P157 BLD 22 -1 FP BE Pri
!#0 N481 P157 BLD 23 -1 FP BE Pri
!#0 N482 P158 LD 25 -1 Int BE Pri
!#0 N483 P159 LD 2 -1 Int BE Pri
!#0 N484 P158 LD 25 -1 Int BE Pri
!#0 N485 P159 LD 2 -1 Int BE Pri
!#0 N486 P160 DWLD 15 -1,0x0 Int LE Pri
!#0 N487 P160 CASX 15 -1,0x0 N486 0x17 Int LE Pri
!#0 N488 P160 DWLD 15 -1,0x0 Int LE Pri
!#0 N489 P160 CASX 15 -1,0x0 N488 0x18 Int LE Pri
!#0 N490 P161 DWLD 24 -1 Int BE Pri
!#0 N491 P161 DWLD 25 -1 Int BE Pri
!#A N490 N491
!#0 N492 P162 BLD 4 -1 FP BE Pri
!#0 N493 P162 BLD 5 -1 FP BE Pri
!#A N492 N493
!#0 N494 P162 BLD 6 -1 FP BE Pri
!#0 N495 P162 BLD 7 -1 FP BE Pri
!#0 N496 P163 DWLD 27 -1,0x0 Int BE Pri
!#0 N497 P163 CASX 27 -1,0x0 N496 0x19 Int BE Pri
!#0 N498 P164 BLD 12 -1 FP BE Pri
!#0 N499 P164 BLD 13 -1 FP BE Pri
!#A N498 N499
!#0 N500 P164 BLD 14 -1 FP BE Pri
!#0 N501 P164 BLD 15 -1 FP BE Pri
!#0 N502 P163 DWLD 27 -1,0x0 Int BE Pri
!#0 N503 P163 CASX 27 -1,0x0 N502 0x1a Int BE Pri
!#0 N504 P164 BLD 12 -1 FP BE Pri
!#0 N505 P164 BLD 13 -1 FP BE Pri
!#A N504 N505
!#0 N506 P164 BLD 14 -1 FP BE Pri
!#0 N507 P164 BLD 15 -1 FP BE Pri
!#0 N508 P165 DWLD 8 -1 Int BE Pri
!#0 N509 P165 DWLD 9 -1 Int BE Pri
!#A N508 N509
!#0 N510 P166 BLD 0 -1 FP BE Pri
!#0 N511 P166 BLD 1 -1 FP BE Pri
!#A N510 N511
!#0 N512 P166 BLD 2 -1 FP BE Pri
!#0 N513 P166 BLD 3 -1 FP BE Pri
!#0 N514 P165 DWLD 8 -1 Int BE Pri
!#0 N515 P165 DWLD 9 -1 Int BE Pri
!#A N514 N515
!#0 N516 P166 BLD 0 -1 FP BE Pri
!#0 N517 P166 BLD 1 -1 FP BE Pri
!#A N516 N517
!#0 N518 P166 BLD 2 -1 FP BE Pri
!#0 N519 P166 BLD 3 -1 FP BE Pri
!#0 N520 P167 BLD 24 -1 FP BE Pri
!#0 N521 P167 BLD 25 -1 FP BE Pri
!#A N520 N521
!#0 N522 P167 BLD 26 -1 FP BE Pri
!#0 N523 P167 BLD 27 -1 FP BE Pri
!#0 N524 P168 LD 25 -1 Int BE Pri
!#0 N525 P169 BLD 12 -1 FP BE Pri
!#0 N526 P169 BLD 13 -1 FP BE Pri
!#A N525 N526
!#0 N527 P169 BLD 14 -1 FP BE Pri
!#0 N528 P169 BLD 15 -1 FP BE Pri
!#0 N529 P170 LD 30 -1 Int BE Pri
!#0 N530 P171 LD 13 -1 Int BE Pri
!#0 N531 P172 LD 30 -1 Int BE Pri
!#0 N532 P171 LD 13 -1 Int BE Pri
!#0 N533 P172 LD 30 -1 Int BE Pri
!#0 N534 P173 DWLD 31 -1 Int BE Pri
!#0 N535 P174 LD 29 -1 Int BE Pri
!#0 N536 P175 LD 19 -1 Int BE Pri
!#0 N537 P176 DWLD 28 -1 Int BE Pri
!#0 N538 P176 DWLD 29 -1 Int BE Pri
!#A N537 N538
!#0 N539 P177 LD 2 -1 Int BE Pri
!#0 N540 P178 LD 1 -1 Int BE Pri
!#0 N541 P179 LD 19 -1 Int BE Pri
!#0 N542 P178 LD 1 -1 Int BE Pri
!#0 N543 P179 LD 19 -1 Int BE Pri
!#0 N544 P180 DWLD 26 -1 Int BE Pri
!#0 N545 P181 LD 15 -1 Int BE Pri
!#0 N546 P182 LD 24 -1 Int BE Pri
!#0 N547 P183 LD 6 -1 Int BE Pri
!#0 N548 P182 LD 24 -1 Int BE Pri
!#0 N549 P183 LD 6 -1 Int BE Pri
!#0 N550 P184 DWLD 16 -1 Int BE Pri
!#0 N551 P184 DWLD 17 -1 Int BE Pri
!#A N550 N551
!#0 N552 P185 LD 3 -1 Int BE Pri
!#0 N553 P186 LD 20 -1 Int BE Pri
!#0 N554 P184 DWLD 16 -1 Int BE Pri
!#0 N555 P184 DWLD 17 -1 Int BE Pri
!#A N554 N555
!#0 N556 P185 LD 3 -1 Int BE Pri
!#0 N557 P186 LD 20 -1 Int BE Pri
!#0 N558 P187 LD 1 -1 Int BE Pri
!#0 N559 P188 LD 21 -1 Int BE Pri
!#0 N560 P189 BLD 4 -1 FP BE Pri
!#0 N561 P189 BLD 5 -1 FP BE Pri
!#A N560 N561
!#0 N562 P189 BLD 6 -1 FP BE Pri
!#0 N563 P189 BLD 7 -1 FP BE Pri
!#0 N564 P189 BLD 4 -1 FP BE Pri
!#0 N565 P189 BLD 5 -1 FP BE Pri
!#A N564 N565
!#0 N566 P189 BLD 6 -1 FP BE Pri
!#0 N567 P189 BLD 7 -1 FP BE Pri
!#0 N568 P190 LD 13 -1 Int BE Pri
!#0 N569 P191 LD 10 -1 Int BE Pri
!#0 N570 P192 BLD 20 -1 FP BE Pri
!#0 N571 P192 BLD 21 -1 FP BE Pri
!#A N570 N571
!#0 N572 P192 BLD 22 -1 FP BE Pri
!#0 N573 P192 BLD 23 -1 FP BE Pri
!#0 N574 P192 BLD 20 -1 FP BE Pri
!#0 N575 P192 BLD 21 -1 FP BE Pri
!#A N574 N575
!#0 N576 P192 BLD 22 -1 FP BE Pri
!#0 N577 P192 BLD 23 -1 FP BE Pri
!#0 N579 P194 BLD 20 -1 FP BE Pri
!#0 N580 P194 BLD 21 -1 FP BE Pri
!#A N579 N580
!#0 N581 P194 BLD 22 -1 FP BE Pri
!#0 N582 P194 BLD 23 -1 FP BE Pri
!#0 N583 P195 BLD 0 -1 FP BE Pri
!#0 N584 P195 BLD 1 -1 FP BE Pri
!#A N583 N584
!#0 N585 P195 BLD 2 -1 FP BE Pri
!#0 N586 P195 BLD 3 -1 FP BE Pri
!#0 N587 P196 LD 29 -1 Int BE Pri
!#0 N588 P197 LD 10 -1 Int BE Pri
!#0 N589 P198 DWLD 4 -1 Int BE Pri
!#0 N590 P198 DWLD 5 -1 Int BE Pri
!#A N589 N590
!#0 N591 P199 LD 13 -1 Int BE Pri
!#0 N592 P200 LD 30 -1 Int BE Pri
!#0 N593 P198 DWLD 4 -1 Int BE Pri
!#0 N594 P198 DWLD 5 -1 Int BE Pri
!#A N593 N594
!#0 N595 P199 LD 13 -1 Int BE Pri
!#0 N596 P200 LD 30 -1 Int BE Pri
!#0 N597 P201 BLD 0 -1 FP BE Pri
!#0 N598 P201 BLD 1 -1 FP BE Pri
!#A N597 N598
!#0 N599 P201 BLD 2 -1 FP BE Pri
!#0 N600 P201 BLD 3 -1 FP BE Pri
!#0 N601 P202 DWLD 4 -1 Int BE Pri
!#0 N602 P202 DWLD 5 -1 Int BE Pri
!#A N601 N602
!#0 N604 P204 DWLD 20 -1 Int BE Pri
!#0 N605 P204 DWLD 21 -1 Int BE Pri
!#A N604 N605
!#0 N606 P204 CASX 20 -1 N604 0x1b Int BE Pri
!#0 N607 P204 CASX 21 -1 N605 0x1c Int BE Pri
!#A N606 N607
!#0 N608 P204 DWLD 20 -1 Int BE Pri
!#0 N609 P204 DWLD 21 -1 Int BE Pri
!#A N608 N609
!#0 N610 P204 CASX 20 -1 N608 0x1d Int BE Pri
!#0 N611 P204 CASX 21 -1 N609 0x1e Int BE Pri
!#A N610 N611
!#0 N612 P205 DWLD 28 -1 Int BE Pri
!#0 N613 P205 DWLD 29 -1 Int BE Pri
!#A N612 N613
!#0 N614 P206 BLD 16 -1 FP BE Pri
!#0 N615 P206 BLD 17 -1 FP BE Pri
!#A N614 N615
!#0 N616 P206 BLD 18 -1 FP BE Pri
!#0 N617 P206 BLD 19 -1 FP BE Pri
!#0 N618 P207 BLD 4 -1 FP BE Pri
!#0 N619 P207 BLD 5 -1 FP BE Pri
!#A N618 N619
!#0 N620 P207 BLD 6 -1 FP BE Pri
!#0 N621 P207 BLD 7 -1 FP BE Pri
!#0 N622 P206 BLD 16 -1 FP BE Pri
!#0 N623 P206 BLD 17 -1 FP BE Pri
!#A N622 N623
!#0 N624 P206 BLD 18 -1 FP BE Pri
!#0 N625 P206 BLD 19 -1 FP BE Pri
!#0 N626 P207 BLD 4 -1 FP BE Pri
!#0 N627 P207 BLD 5 -1 FP BE Pri
!#A N626 N627
!#0 N628 P207 BLD 6 -1 FP BE Pri
!#0 N629 P207 BLD 7 -1 FP BE Pri
!#0 N630 P208 BLD 0 -1 FP BE Pri
!#0 N631 P208 BLD 1 -1 FP BE Pri
!#A N630 N631
!#0 N632 P208 BLD 2 -1 FP BE Pri
!#0 N633 P208 BLD 3 -1 FP BE Pri
!#0 N634 P208 BLD 0 -1 FP BE Pri
!#0 N635 P208 BLD 1 -1 FP BE Pri
!#A N634 N635
!#0 N636 P208 BLD 2 -1 FP BE Pri
!#0 N637 P208 BLD 3 -1 FP BE Pri
!#0 N638 P209 LD 31 -1 Int BE Pri
!#0 N639 P210 LD 16 -1 Int BE Pri
!#0 N640 P211 DWLD 3 -1 Int BE Pri
!#0 N641 P212 LD 9 -1 Int BE Pri
!#0 N642 P211 DWLD 3 -1 Int BE Pri
!#0 N643 P212 LD 9 -1 Int BE Pri
!#0 N644 P213 DWLD 19 -1 Int BE Pri
!#0 N645 P214 LD 16 -1 Int BE Pri
!#0 N646 P215 DWLD 12 -1 Int BE Pri
!#0 N647 P215 DWLD 13 -1 Int BE Pri
!#A N646 N647
!#0 N648 P216 BLD 12 -1 FP BE Pri
!#0 N649 P216 BLD 13 -1 FP BE Pri
!#A N648 N649
!#0 N650 P216 BLD 14 -1 FP BE Pri
!#0 N651 P216 BLD 15 -1 FP BE Pri
!#0 N652 P217 BLD 4 -1 FP BE Pri
!#0 N653 P217 BLD 5 -1 FP BE Pri
!#A N652 N653
!#0 N654 P217 BLD 6 -1 FP BE Pri
!#0 N655 P217 BLD 7 -1 FP BE Pri
!#0 N656 P216 BLD 12 -1 FP BE Pri
!#0 N657 P216 BLD 13 -1 FP BE Pri
!#A N656 N657
!#0 N658 P216 BLD 14 -1 FP BE Pri
!#0 N659 P216 BLD 15 -1 FP BE Pri
!#0 N660 P217 BLD 4 -1 FP BE Pri
!#0 N661 P217 BLD 5 -1 FP BE Pri
!#A N660 N661
!#0 N662 P217 BLD 6 -1 FP BE Pri
!#0 N663 P217 BLD 7 -1 FP BE Pri
!#0 N664 P218 BLD 4 -1 FP BE Pri
!#0 N665 P218 BLD 5 -1 FP BE Pri
!#A N664 N665
!#0 N666 P218 BLD 6 -1 FP BE Pri
!#0 N667 P218 BLD 7 -1 FP BE Pri
!#0 N668 P218 BLD 4 -1 FP BE Pri
!#0 N669 P218 BLD 5 -1 FP BE Pri
!#A N668 N669
!#0 N670 P218 BLD 6 -1 FP BE Pri
!#0 N671 P218 BLD 7 -1 FP BE Pri
!#0 N672 P219 DWST 4 0x1f Int BE Pri
!#0 N673 P219 DWST 5 0x20 Int BE Pri
!#A N672 N673
!#0 N674 P219 DWST 4 0x21 Int BE Pri
!#0 N675 P219 DWST 5 0x22 Int BE Pri
!#A N674 N675
!#0 N676 P220 LD 21 -1 Int BE Pri
!#0 N677 P221 DWLD 12 -1 Int BE Pri
!#0 N678 P221 DWLD 13 -1 Int BE Pri
!#A N677 N678
!#0 N679 P221 CASX 12 -1 N677 0x23 Int BE Pri
!#0 N680 P221 CASX 13 -1 N678 0x24 Int BE Pri
!#A N679 N680
!#0 N681 P222 LD 5 -1 Int BE Pri
!#0 N682 P220 LD 21 -1 Int BE Pri
!#0 N683 P221 DWLD 12 -1 Int BE Pri
!#0 N684 P221 DWLD 13 -1 Int BE Pri
!#A N683 N684
!#0 N685 P221 CASX 12 -1 N683 0x25 Int BE Pri
!#0 N686 P221 CASX 13 -1 N684 0x26 Int BE Pri
!#A N685 N686
!#0 N687 P222 LD 5 -1 Int BE Pri
!#0 N688 P223 DWLD 4 -1 Int BE Pri
!#0 N689 P223 DWLD 5 -1 Int BE Pri
!#A N688 N689
!#0 N690 P224 BLD 28 -1 FP BE Pri
!#0 N691 P224 BLD 29 -1 FP BE Pri
!#A N690 N691
!#0 N692 P224 BLD 30 -1 FP BE Pri
!#0 N693 P224 BLD 31 -1 FP BE Pri
!#0 N694 P225 DWLD 0 -1 Int BE Pri
!#0 N695 P225 DWLD 1 -1 Int BE Pri
!#A N694 N695
!#0 N696 P226 DWLD 0 -1 Int BE Pri
!#0 N697 P226 DWLD 1 -1 Int BE Pri
!#A N696 N697
!#0 N698 P227 DWLD 23 -1 Int BE Pri
!#0 N699 P228 LD 28 -1 Int BE Pri
!#0 N700 P226 DWLD 0 -1 Int BE Pri
!#0 N701 P226 DWLD 1 -1 Int BE Pri
!#A N700 N701
!#0 N702 P227 DWLD 23 -1 Int BE Pri
!#0 N703 P228 LD 28 -1 Int BE Pri
!#0 N704 P229 DWLD 0 -1 Int BE Pri
!#0 N705 P229 DWLD 1 -1 Int BE Pri
!#A N704 N705
!#0 N706 P230 LD 11 -1 Int BE Pri
!#0 N707 P230 CAS 11 -1 N706 0x27 Int BE Pri
!#0 N708 P231 DWLD 8 -1 Int BE Pri
!#0 N709 P231 DWLD 9 -1 Int BE Pri
!#A N708 N709
!#0 N710 P232 LD 6 -1 Int BE Pri
!#0 N711 P233 DWLD 16 -1 Int BE Pri
!#0 N712 P233 DWLD 17 -1 Int BE Pri
!#A N711 N712
!#0 N713 P234 LD 4 -1 Int BE Pri
!#0 N714 P232 LD 6 -1 Int BE Pri
!#0 N715 P233 DWLD 16 -1 Int BE Pri
!#0 N716 P233 DWLD 17 -1 Int BE Pri
!#A N715 N716
!#0 N717 P234 LD 4 -1 Int BE Pri
!#0 N718 P235 LD 25 -1 Int BE Pri
!#0 N719 P236 BLD 4 -1 FP BE Pri
!#0 N720 P236 BLD 5 -1 FP BE Pri
!#A N719 N720
!#0 N721 P236 BLD 6 -1 FP BE Pri
!#0 N722 P236 BLD 7 -1 FP BE Pri
!#0 N723 P237 LD 1 -1 Int BE Pri
!#0 N724 P238 BLD 12 -1 FP BE Pri
!#0 N725 P238 BLD 13 -1 FP BE Pri
!#A N724 N725
!#0 N726 P238 BLD 14 -1 FP BE Pri
!#0 N727 P238 BLD 15 -1 FP BE Pri
!#0 N728 P239 DWLD 4 -1 Int BE Pri
!#0 N729 P239 DWLD 5 -1 Int BE Pri
!#A N728 N729
!#0 N730 P238 BLD 12 -1 FP BE Pri
!#0 N731 P238 BLD 13 -1 FP BE Pri
!#A N730 N731
!#0 N732 P238 BLD 14 -1 FP BE Pri
!#0 N733 P238 BLD 15 -1 FP BE Pri
!#0 N734 P239 DWLD 4 -1 Int BE Pri
!#0 N735 P239 DWLD 5 -1 Int BE Pri
!#A N734 N735
!#0 N736 P240 LD 24 -1 Int BE Pri
!#0 N737 P241 LD 12 -1 Int BE Pri
!#0 N740 P243 DWST 28 0x28 Int BE Pri
!#0 N741 P243 DWST 29 0x29 Int BE Pri
!#A N740 N741
!#0 N742 P243 DWST 28 0x2a Int BE Pri
!#0 N743 P243 DWST 29 0x2b Int BE Pri
!#A N742 N743
!#0 N745 P245 BLD 4 -1 FP BE Pri
!#0 N746 P245 BLD 5 -1 FP BE Pri
!#A N745 N746
!#0 N747 P245 BLD 6 -1 FP BE Pri
!#0 N748 P245 BLD 7 -1 FP BE Pri
!#0 N750 P245 BLD 4 -1 FP BE Pri
!#0 N751 P245 BLD 5 -1 FP BE Pri
!#A N750 N751
!#0 N752 P245 BLD 6 -1 FP BE Pri
!#0 N753 P245 BLD 7 -1 FP BE Pri
!#0 N754 P246 LD 4 -1 Int BE Pri
!#0 N755 P247 LD 16 -1 Int BE Pri
!#0 N758 P249 MEMBAR
!#0 N759 P250 LD 17 -1 Int BE Pri
!#0 N760 P251 BLD 16 -1 FP BE Pri
!#0 N761 P251 BLD 17 -1 FP BE Pri
!#A N760 N761
!#0 N762 P251 BLD 18 -1 FP BE Pri
!#0 N763 P251 BLD 19 -1 FP BE Pri
!#0 N764 P252 LD 7 -1 Int BE Pri
!#0 N765 P253 DWLD 7 -1 Int BE Pri
!#0 N766 P254 BLD 12 -1 FP BE Pri
!#0 N767 P254 BLD 13 -1 FP BE Pri
!#A N766 N767
!#0 N768 P254 BLD 14 -1 FP BE Pri
!#0 N769 P254 BLD 15 -1 FP BE Pri
!#0 N770 P255 LD 2 -1 Int BE Pri
!#0 N771 P256 LD 14 -1 Int BE Pri
!#0 N772 P257 BLD 16 -1 FP BE Pri
!#0 N773 P257 BLD 17 -1 FP BE Pri
!#A N772 N773
!#0 N774 P257 BLD 18 -1 FP BE Pri
!#0 N775 P257 BLD 19 -1 FP BE Pri
!#0 N776 P258 LD 31 -1 Int BE Pri
!#0 N777 P256 LD 14 -1 Int BE Pri
!#0 N778 P257 BLD 16 -1 FP BE Pri
!#0 N779 P257 BLD 17 -1 FP BE Pri
!#A N778 N779
!#0 N780 P257 BLD 18 -1 FP BE Pri
!#0 N781 P257 BLD 19 -1 FP BE Pri
!#0 N782 P258 LD 31 -1 Int BE Pri
!#0 N783 P259 ST 3 0x2c Int LE Pri
!#0 N784 P260 LD 17 -1 Int BE Pri
!#0 N785 P261 LD 10 -1 Int BE Pri
!#0 N786 P262 DWLD 7 -1 Int BE Pri
!#0 N787 P263 LD 31 -1 Int BE Pri
!#0 N788 P262 DWLD 7 -1 Int BE Pri
!#0 N789 P263 LD 31 -1 Int BE Pri
!#0 N790 P264 MEMBAR
!#0 N791 P264 MEMBAR
!#0 N792 P265 DWLD 4 -1 Int BE Pri
!#0 N793 P265 DWLD 5 -1 Int BE Pri
!#A N792 N793
!#0 N794 P266 BLD 12 -1 FP BE Pri
!#0 N795 P266 BLD 13 -1 FP BE Pri
!#A N794 N795
!#0 N796 P266 BLD 14 -1 FP BE Pri
!#0 N797 P266 BLD 15 -1 FP BE Pri
!#0 N798 P265 DWLD 4 -1 Int BE Pri
!#0 N799 P265 DWLD 5 -1 Int BE Pri
!#A N798 N799
!#0 N800 P266 BLD 12 -1 FP BE Pri
!#0 N801 P266 BLD 13 -1 FP BE Pri
!#A N800 N801
!#0 N802 P266 BLD 14 -1 FP BE Pri
!#0 N803 P266 BLD 15 -1 FP BE Pri
!#0 N804 P267 DWST 24 0x2d Int BE Pri
!#0 N805 P267 DWST 25 0x2e Int BE Pri
!#A N804 N805
!#0 N806 P268 MEMBAR
!#0 N807 P268 MEMBAR
!#0 N808 P269 LD 27 -1 Int BE Pri
!#0 N809 P270 LD 1 -1 FP BE Pri
!#0 N810 P271 LD 14 -1 Int BE Pri
!#0 N811 P269 LD 27 -1 Int BE Pri
!#0 N812 P270 LD 1 -1 FP BE Pri
!#0 N813 P271 LD 14 -1 Int BE Pri
!#0 N814 P272 DWLD 0 -1 Int BE Pri
!#0 N815 P272 DWLD 1 -1 Int BE Pri
!#A N814 N815
!#0 N816 P273 LD 2 -1 FP BE Pri
!#0 N817 P274 DWLD 14 -1 Int BE Pri
!#0 N818 P275 LD 28 -1 Int BE Pri
!#0 N819 P274 DWLD 14 -1 Int BE Pri
!#0 N820 P275 LD 28 -1 Int BE Pri
!#0 N821 P276 DWLD 28 -1 Int BE Pri
!#0 N822 P276 DWLD 29 -1 Int BE Pri
!#A N821 N822
!#0 N823 P277 LD 31 -1 Int BE Pri
!#0 N824 P278 DWLD 16 -1 Int BE Pri
!#0 N825 P278 DWLD 17 -1 Int BE Pri
!#A N824 N825
!#0 N826 P279 LD 26 -1 Int BE Pri
!#0 N827 P277 LD 31 -1 Int BE Pri
!#0 N828 P278 DWLD 16 -1 Int BE Pri
!#0 N829 P278 DWLD 17 -1 Int BE Pri
!#A N828 N829
!#0 N830 P279 LD 26 -1 Int BE Pri
!#0 N831 P280 LD 9 -1 Int BE Pri
!#0 N833 P282 LD 2 -1 Int BE Pri
!#0 N834 P283 BLD 8 -1 FP BE Pri
!#0 N835 P283 BLD 9 -1 FP BE Pri
!#A N834 N835
!#0 N836 P283 BLD 10 -1 FP BE Pri
!#0 N837 P283 BLD 11 -1 FP BE Pri
!#0 N838 P284 DWLD 20 -1 Int BE Pri
!#0 N839 P284 DWLD 21 -1 Int BE Pri
!#A N838 N839
!#0 N840 P283 BLD 8 -1 FP BE Pri
!#0 N841 P283 BLD 9 -1 FP BE Pri
!#A N840 N841
!#0 N842 P283 BLD 10 -1 FP BE Pri
!#0 N843 P283 BLD 11 -1 FP BE Pri
!#0 N844 P284 DWLD 20 -1 Int BE Pri
!#0 N845 P284 DWLD 21 -1 Int BE Pri
!#A N844 N845
!#0 N846 P285 DWLD 14 -1 Int BE Pri
!#0 N848 P287 LD 6 -1 Int LE Pri
!#0 N849 P285 DWLD 14 -1 Int BE Pri
!#0 N851 P287 LD 6 -1 Int LE Pri
!#0 N852 P288 LD 10 -1 Int BE Pri
!#0 N853 P289 LD 26 -1 Int BE Pri
!#0 N854 P290 DWLD 11 -1 Int BE Pri
!#0 N855 P291 LD 5 -1 Int LE Pri
!#0 N856 P290 DWLD 11 -1 Int BE Pri
!#0 N857 P291 LD 5 -1 Int LE Pri
!#0 N858 P292 DWLD 28 -1 Int BE Pri
!#0 N859 P292 DWLD 29 -1 Int BE Pri
!#A N858 N859
!#0 N860 P292 DWLD 28 -1 Int BE Pri
!#0 N861 P292 DWLD 29 -1 Int BE Pri
!#A N860 N861
!#0 N862 P293 DWLD 20 -1 Int BE Pri
!#0 N863 P293 DWLD 21 -1 Int BE Pri
!#A N862 N863
!#0 N864 P293 CASX 20 -1 N862 0x2f Int BE Pri
!#0 N865 P293 CASX 21 -1 N863 0x30 Int BE Pri
!#A N864 N865
!#0 N866 P294 LD 20 -1 FP BE Pri
!#0 N867 P293 DWLD 20 -1 Int BE Pri
!#0 N868 P293 DWLD 21 -1 Int BE Pri
!#A N867 N868
!#0 N869 P293 CASX 20 -1 N867 0x31 Int BE Pri
!#0 N870 P293 CASX 21 -1 N868 0x32 Int BE Pri
!#A N869 N870
!#0 N871 P294 LD 20 -1 FP BE Pri
!#0 N872 P295 BLD 8 -1 FP BE Pri
!#0 N873 P295 BLD 9 -1 FP BE Pri
!#A N872 N873
!#0 N874 P295 BLD 10 -1 FP BE Pri
!#0 N875 P295 BLD 11 -1 FP BE Pri
!#0 N876 P296 BLD 0 -1 FP BE Pri
!#0 N877 P296 BLD 1 -1 FP BE Pri
!#A N876 N877
!#0 N878 P296 BLD 2 -1 FP BE Pri
!#0 N879 P296 BLD 3 -1 FP BE Pri
!#0 N880 P297 BLD 4 -1 FP BE Pri
!#0 N881 P297 BLD 5 -1 FP BE Pri
!#A N880 N881
!#0 N882 P297 BLD 6 -1 FP BE Pri
!#0 N883 P297 BLD 7 -1 FP BE Pri
!#0 N884 P298 DWLD 28 -1 Int BE Pri
!#0 N885 P298 DWLD 29 -1 Int BE Pri
!#A N884 N885
!#0 N886 P297 BLD 4 -1 FP BE Pri
!#0 N887 P297 BLD 5 -1 FP BE Pri
!#A N886 N887
!#0 N888 P297 BLD 6 -1 FP BE Pri
!#0 N889 P297 BLD 7 -1 FP BE Pri
!#0 N890 P298 DWLD 28 -1 Int BE Pri
!#0 N891 P298 DWLD 29 -1 Int BE Pri
!#A N890 N891
!#0 N894 P300 DWLD 23 -1 Int BE Pri
!#0 N895 P301 BLD 28 -1 FP BE Pri
!#0 N896 P301 BLD 29 -1 FP BE Pri
!#A N895 N896
!#0 N897 P301 BLD 30 -1 FP BE Pri
!#0 N898 P301 BLD 31 -1 FP BE Pri
!#0 N899 P302 LD 28 -1 Int BE Pri
!#0 N900 P303 DWLD 15 -1 FP BE Pri
!#0 N901 P304 ST 20 0x33 Int BE Pri
!#0 N902 P303 DWLD 15 -1 FP BE Pri
!#0 N903 P304 ST 20 0x34 Int BE Pri
!#0 N904 P305 BLD 24 -1 FP BE Pri
!#0 N905 P305 BLD 25 -1 FP BE Pri
!#A N904 N905
!#0 N906 P305 BLD 26 -1 FP BE Pri
!#0 N907 P305 BLD 27 -1 FP BE Pri
!#0 N908 P306 LD 26 -1 Int BE Pri
!#0 N909 P307 LD 6 -1 Int BE Pri
!#0 N910 P308 LD 18 -1 Int BE Pri
!#0 N911 P308 CAS 18 -1 N910 0x35 Int BE Pri
!#0 N913 P310 LD 29 -1 FP BE Pri
!#0 N914 P310 LD 29 -1 FP BE Pri
!#0 N915 P311 BLD 28 -1 FP BE Pri
!#0 N916 P311 BLD 29 -1 FP BE Pri
!#A N915 N916
!#0 N917 P311 BLD 30 -1 FP BE Pri
!#0 N918 P311 BLD 31 -1 FP BE Pri
!#0 N919 P312 DWLD 8 -1 Int LE Pri
!#0 N920 P312 DWLD 9 -1 Int LE Pri
!#A N919 N920
!#0 N921 P311 BLD 28 -1 FP BE Pri
!#0 N922 P311 BLD 29 -1 FP BE Pri
!#A N921 N922
!#0 N923 P311 BLD 30 -1 FP BE Pri
!#0 N924 P311 BLD 31 -1 FP BE Pri
!#0 N925 P312 DWLD 8 -1 Int LE Pri
!#0 N926 P312 DWLD 9 -1 Int LE Pri
!#A N925 N926
!#0 N927 P313 BLD 20 -1 FP BE Pri
!#0 N928 P313 BLD 21 -1 FP BE Pri
!#A N927 N928
!#0 N929 P313 BLD 22 -1 FP BE Pri
!#0 N930 P313 BLD 23 -1 FP BE Pri
!#0 N931 P314 DWLD 2 -1 FP BE Pri
!#0 N932 P315 BLD 16 -1 FP BE Pri
!#0 N933 P315 BLD 17 -1 FP BE Pri
!#A N932 N933
!#0 N934 P315 BLD 18 -1 FP BE Pri
!#0 N935 P315 BLD 19 -1 FP BE Pri
!#0 N936 P314 DWLD 2 -1 FP BE Pri
!#0 N937 P315 BLD 16 -1 FP BE Pri
!#0 N938 P315 BLD 17 -1 FP BE Pri
!#A N937 N938
!#0 N939 P315 BLD 18 -1 FP BE Pri
!#0 N940 P315 BLD 19 -1 FP BE Pri
!#0 N941 P316 LD 10 -1 Int BE Pri
!#0 N942 P317 LD 5 -1 Int BE Pri
!#0 N943 P316 LD 10 -1 Int BE Pri
!#0 N944 P317 LD 5 -1 Int BE Pri
!#0 N945 P318 LD 10 -1 Int BE Pri
!#0 N946 P319 LD 20 -1 Int BE Pri
!#0 N947 P318 LD 10 -1 Int BE Pri
!#0 N948 P319 LD 20 -1 Int BE Pri
!#0 N949 P320 DWLD 22 -1 Int BE Pri
!#0 N950 P321 LD 18 -1 Int BE Pri
!#0 N951 P320 DWLD 22 -1 Int BE Pri
!#0 N952 P321 LD 18 -1 Int BE Pri
!#0 N953 P322 DWLD 4 -1 Int BE Pri
!#0 N954 P322 DWLD 5 -1 Int BE Pri
!#A N953 N954
!#0 N955 P322 DWLD 4 -1 Int BE Pri
!#0 N956 P322 DWLD 5 -1 Int BE Pri
!#A N955 N956
!#0 N957 P323 LD 3 -1 FP BE Pri
!#0 N958 P323 LD 3 -1 FP BE Pri
!#0 N959 P324 DWLD 28 -1 Int BE Pri
!#0 N960 P324 DWLD 29 -1 Int BE Pri
!#A N959 N960
!#0 N961 P325 LD 21 -1 Int BE Pri
!#0 N962 P326 LD 10 -1 Int BE Pri
!#0 N963 P325 LD 21 -1 Int BE Pri
!#0 N964 P326 LD 10 -1 Int BE Pri
!#0 N967 P328 LD 18 -1 Int BE Pri
!#0 N968 P329 BLD 28 -1 FP BE Pri
!#0 N969 P329 BLD 29 -1 FP BE Pri
!#A N968 N969
!#0 N970 P329 BLD 30 -1 FP BE Pri
!#0 N971 P329 BLD 31 -1 FP BE Pri
!#0 N972 P330 LD 19 -1 Int BE Pri
!#0 N973 P331 BLD 8 -1 FP BE Pri
!#0 N974 P331 BLD 9 -1 FP BE Pri
!#A N973 N974
!#0 N975 P331 BLD 10 -1 FP BE Pri
!#0 N976 P331 BLD 11 -1 FP BE Pri
!#0 N977 P332 LD 17 -1 FP BE Pri
!#0 N978 P332 LD 17 -1 FP BE Pri
!#0 N979 P333 LD 15 -1 Int BE Pri
!#0 N980 P334 LD 4 -1 Int BE Pri
!#0 N981 P333 LD 15 -1 Int BE Pri
!#0 N982 P334 LD 4 -1 Int BE Pri
!#0 N983 P335 LD 17 -1 Int BE Pri
!#0 N984 P336 DWLD 19 -1 Int BE Pri
!#0 N985 P337 BLD 24 -1 FP BE Pri
!#0 N986 P337 BLD 25 -1 FP BE Pri
!#A N985 N986
!#0 N987 P337 BLD 26 -1 FP BE Pri
!#0 N988 P337 BLD 27 -1 FP BE Pri
!#0 N989 P337 BLD 24 -1 FP BE Pri
!#0 N990 P337 BLD 25 -1 FP BE Pri
!#A N989 N990
!#0 N991 P337 BLD 26 -1 FP BE Pri
!#0 N992 P337 BLD 27 -1 FP BE Pri
!#0 N993 P338 BLD 24 -1 FP BE Pri
!#0 N994 P338 BLD 25 -1 FP BE Pri
!#A N993 N994
!#0 N995 P338 BLD 26 -1 FP BE Pri
!#0 N996 P338 BLD 27 -1 FP BE Pri
!#0 N997 P339 DWLD 2 -1 Int BE Pri
!#0 N998 P340 LD 8 -1 Int BE Pri
!#0 N999 P341 BLD 12 -1 FP BE Pri
!#0 N1000 P341 BLD 13 -1 FP BE Pri
!#A N999 N1000
!#0 N1001 P341 BLD 14 -1 FP BE Pri
!#0 N1002 P341 BLD 15 -1 FP BE Pri
!#0 N1003 P342 BLD 24 -1 FP BE Pri
!#0 N1004 P342 BLD 25 -1 FP BE Pri
!#A N1003 N1004
!#0 N1005 P342 BLD 26 -1 FP BE Pri
!#0 N1006 P342 BLD 27 -1 FP BE Pri
!#0 N1007 P341 BLD 12 -1 FP BE Pri
!#0 N1008 P341 BLD 13 -1 FP BE Pri
!#A N1007 N1008
!#0 N1009 P341 BLD 14 -1 FP BE Pri
!#0 N1010 P341 BLD 15 -1 FP BE Pri
!#0 N1011 P342 BLD 24 -1 FP BE Pri
!#0 N1012 P342 BLD 25 -1 FP BE Pri
!#A N1011 N1012
!#0 N1013 P342 BLD 26 -1 FP BE Pri
!#0 N1014 P342 BLD 27 -1 FP BE Pri
!#0 N1016 P344 BLD 8 -1 FP BE Pri
!#0 N1017 P344 BLD 9 -1 FP BE Pri
!#A N1016 N1017
!#0 N1018 P344 BLD 10 -1 FP BE Pri
!#0 N1019 P344 BLD 11 -1 FP BE Pri
!#0 N1020 P344 BLD 8 -1 FP BE Pri
!#0 N1021 P344 BLD 9 -1 FP BE Pri
!#A N1020 N1021
!#0 N1022 P344 BLD 10 -1 FP BE Pri
!#0 N1023 P344 BLD 11 -1 FP BE Pri
!#0 N1024 P345 LD 16 -1 Int BE Pri
!#0 N1025 P346 LD 27 -1 Int BE Pri
!#0 N1026 P347 BST 16 0x3f800015 FP BE Pri
!#0 N1027 P347 BST 17 0x3f800016 FP BE Pri
!#A N1026 N1027
!#0 N1028 P347 BST 18 0x3f800017 FP BE Pri
!#0 N1029 P347 BST 19 0x3f800018 FP BE Pri
!#0 N1030 P347 BST 16 0x3f800019 FP BE Pri
!#0 N1031 P347 BST 17 0x3f80001a FP BE Pri
!#A N1030 N1031
!#0 N1032 P347 BST 18 0x3f80001b FP BE Pri
!#0 N1033 P347 BST 19 0x3f80001c FP BE Pri
!#0 N1034 P348 DWLD 0 -1 Int BE Pri
!#0 N1035 P348 DWLD 1 -1 Int BE Pri
!#A N1034 N1035
!#0 N1036 P349 BLD 24 -1 FP BE Pri
!#0 N1037 P349 BLD 25 -1 FP BE Pri
!#A N1036 N1037
!#0 N1038 P349 BLD 26 -1 FP BE Pri
!#0 N1039 P349 BLD 27 -1 FP BE Pri
!#0 N1040 P350 DWLD 28 -1 Int BE Pri
!#0 N1041 P350 DWLD 29 -1 Int BE Pri
!#A N1040 N1041
!#0 N1042 P351 LD 5 -1 Int BE Pri
!#0 N1043 P352 BLD 4 -1 FP BE Pri
!#0 N1044 P352 BLD 5 -1 FP BE Pri
!#A N1043 N1044
!#0 N1045 P352 BLD 6 -1 FP BE Pri
!#0 N1046 P352 BLD 7 -1 FP BE Pri
!#0 N1047 P353 LD 28 -1 Int BE Pri
!#0 N1048 P354 BLD 16 -1 FP BE Pri
!#0 N1049 P354 BLD 17 -1 FP BE Pri
!#A N1048 N1049
!#0 N1050 P354 BLD 18 -1 FP BE Pri
!#0 N1051 P354 BLD 19 -1 FP BE Pri
!#0 N1052 P355 BST 8 0x3f80001d FP BE Pri
!#0 N1053 P355 BST 9 0x3f80001e FP BE Pri
!#A N1052 N1053
!#0 N1054 P355 BST 10 0x3f80001f FP BE Pri
!#0 N1055 P355 BST 11 0x3f800020 FP BE Pri
!#0 N1056 P356 DWLD 6 -1 Int BE Pri
!#0 N1057 P357 LD 24 -1 Int BE Pri
!#0 N1058 P358 ST 21 0x36 Int BE Pri
!#0 N1059 P359 LD 12 -1 Int BE Pri
!#0 N1061 P361 LD 11 -1 Int BE Pri
!#0 N1062 P359 LD 12 -1 Int BE Pri
!#0 N1064 P361 LD 11 -1 Int BE Pri
!#0 N1065 P362 BLD 0 -1 FP BE Pri
!#0 N1066 P362 BLD 1 -1 FP BE Pri
!#A N1065 N1066
!#0 N1067 P362 BLD 2 -1 FP BE Pri
!#0 N1068 P362 BLD 3 -1 FP BE Pri
!#0 N1069 P363 SWAP 11 0xffffffff 0x37 Int BE Pri
!#0 N1070 P364 DWLD 7 -1 Int BE Pri
!#0 N1071 P363 SWAP 11 0xffffffff 0x38 Int BE Pri
!#0 N1072 P364 DWLD 7 -1 Int BE Pri
!#0 N1073 P365 MEMBAR
!#0 N1074 P365 MEMBAR
!#0 N1075 P366 BLD 20 -1 FP BE Pri
!#0 N1076 P366 BLD 21 -1 FP BE Pri
!#A N1075 N1076
!#0 N1077 P366 BLD 22 -1 FP BE Pri
!#0 N1078 P366 BLD 23 -1 FP BE Pri
!#0 N1079 P367 DWLD 12 -1 Int BE Pri
!#0 N1080 P367 DWLD 13 -1 Int BE Pri
!#A N1079 N1080
!#0 N1081 P366 BLD 20 -1 FP BE Pri
!#0 N1082 P366 BLD 21 -1 FP BE Pri
!#A N1081 N1082
!#0 N1083 P366 BLD 22 -1 FP BE Pri
!#0 N1084 P366 BLD 23 -1 FP BE Pri
!#0 N1085 P367 DWLD 12 -1 Int BE Pri
!#0 N1086 P367 DWLD 13 -1 Int BE Pri
!#A N1085 N1086
!#0 N1087 P368 BLD 16 -1 FP BE Pri
!#0 N1088 P368 BLD 17 -1 FP BE Pri
!#A N1087 N1088
!#0 N1089 P368 BLD 18 -1 FP BE Pri
!#0 N1090 P368 BLD 19 -1 FP BE Pri
!#0 N1091 P368 BLD 16 -1 FP BE Pri
!#0 N1092 P368 BLD 17 -1 FP BE Pri
!#A N1091 N1092
!#0 N1093 P368 BLD 18 -1 FP BE Pri
!#0 N1094 P368 BLD 19 -1 FP BE Pri
!#0 N1095 P369 LD 10 -1 Int BE Pri
!#0 N1096 P370 LD 23 -1 Int BE Pri
!#0 N1097 P371 BST 8 0x3f800021 FP BE Pri
!#0 N1098 P371 BST 9 0x3f800022 FP BE Pri
!#A N1097 N1098
!#0 N1099 P371 BST 10 0x3f800023 FP BE Pri
!#0 N1100 P371 BST 11 0x3f800024 FP BE Pri
!#0 N1101 P371 BST 8 0x3f800025 FP BE Pri
!#0 N1102 P371 BST 9 0x3f800026 FP BE Pri
!#A N1101 N1102
!#0 N1103 P371 BST 10 0x3f800027 FP BE Pri
!#0 N1104 P371 BST 11 0x3f800028 FP BE Pri
!#0 N1105 P372 MEMBAR
!#0 N1106 P373 LD 22 -1 Int BE Pri
!#0 N1107 P374 LD 20 -1 Int BE Pri
!#0 N1108 P375 BLD 16 -1 FP BE Pri
!#0 N1109 P375 BLD 17 -1 FP BE Pri
!#A N1108 N1109
!#0 N1110 P375 BLD 18 -1 FP BE Pri
!#0 N1111 P375 BLD 19 -1 FP BE Pri
!#0 N1112 P376 DWLD 31 -1 FP BE Pri
!#0 N1113 P375 BLD 16 -1 FP BE Pri
!#0 N1114 P375 BLD 17 -1 FP BE Pri
!#A N1113 N1114
!#0 N1115 P375 BLD 18 -1 FP BE Pri
!#0 N1116 P375 BLD 19 -1 FP BE Pri
!#0 N1117 P376 DWLD 31 -1 FP BE Pri
!#0 N1118 P377 DWLD 0 -1 Int BE Pri
!#0 N1119 P377 DWLD 1 -1 Int BE Pri
!#A N1118 N1119
!#0 N1120 P377 DWLD 0 -1 Int BE Pri
!#0 N1121 P377 DWLD 1 -1 Int BE Pri
!#A N1120 N1121
!#0 N1122 P378 BLD 4 -1 FP BE Pri
!#0 N1123 P378 BLD 5 -1 FP BE Pri
!#A N1122 N1123
!#0 N1124 P378 BLD 6 -1 FP BE Pri
!#0 N1125 P378 BLD 7 -1 FP BE Pri
!#0 N1126 P379 DWLD 0 -1 Int BE Pri
!#0 N1127 P379 DWLD 1 -1 Int BE Pri
!#A N1126 N1127
!#0 N1128 P380 LD 10 -1 Int BE Pri
!#0 N1129 P381 LD 22 -1 Int BE Pri
!#0 N1130 P382 BLD 12 -1 FP BE Pri
!#0 N1131 P382 BLD 13 -1 FP BE Pri
!#A N1130 N1131
!#0 N1132 P382 BLD 14 -1 FP BE Pri
!#0 N1133 P382 BLD 15 -1 FP BE Pri
!#0 N1134 P383 BLD 4 -1 FP BE Pri
!#0 N1135 P383 BLD 5 -1 FP BE Pri
!#A N1134 N1135
!#0 N1136 P383 BLD 6 -1 FP BE Pri
!#0 N1137 P383 BLD 7 -1 FP BE Pri
!#0 N1138 P383 BLD 4 -1 FP BE Pri
!#0 N1139 P383 BLD 5 -1 FP BE Pri
!#A N1138 N1139
!#0 N1140 P383 BLD 6 -1 FP BE Pri
!#0 N1141 P383 BLD 7 -1 FP BE Pri
!#0 N1142 P384 BLD 28 -1 FP BE Pri
!#0 N1143 P384 BLD 29 -1 FP BE Pri
!#A N1142 N1143
!#0 N1144 P384 BLD 30 -1 FP BE Pri
!#0 N1145 P384 BLD 31 -1 FP BE Pri
!#0 N1146 P385 LD 17 -1 Int BE Pri
!#0 N1147 P386 LD 18 -1 Int BE Pri
!#0 N1148 P384 BLD 28 -1 FP BE Pri
!#0 N1149 P384 BLD 29 -1 FP BE Pri
!#A N1148 N1149
!#0 N1150 P384 BLD 30 -1 FP BE Pri
!#0 N1151 P384 BLD 31 -1 FP BE Pri
!#0 N1152 P385 LD 17 -1 Int BE Pri
!#0 N1153 P386 LD 18 -1 Int BE Pri
!#0 N1154 P387 BLD 0 -1 FP BE Pri
!#0 N1155 P387 BLD 1 -1 FP BE Pri
!#A N1154 N1155
!#0 N1156 P387 BLD 2 -1 FP BE Pri
!#0 N1157 P387 BLD 3 -1 FP BE Pri
!#0 N1158 P388 LD 31 -1 Int BE Pri
!#0 N1159 P389 LD 9 -1 Int BE Pri
!#0 N1160 P388 LD 31 -1 Int BE Pri
!#0 N1161 P389 LD 9 -1 Int BE Pri
!#0 N1162 P390 BLD 20 -1 FP BE Pri
!#0 N1163 P390 BLD 21 -1 FP BE Pri
!#A N1162 N1163
!#0 N1164 P390 BLD 22 -1 FP BE Pri
!#0 N1165 P390 BLD 23 -1 FP BE Pri
!#0 N1166 P391 LD 29 -1 Int BE Pri
!#0 N1167 P392 LD 22 -1 Int BE Pri
!#0 N1168 P391 LD 29 -1 Int BE Pri
!#0 N1169 P392 LD 22 -1 Int BE Pri
!#0 N1170 P393 DWLD 2 -1 FP BE Pri
!#0 N1171 P394 LD 1 -1 Int BE Pri
!#0 N1172 P395 LD 7 -1 Int BE Pri
!#0 N1174 P397 LD 10 -1 Int BE Pri
!#0 N1175 P398 LD 10 -1 Int BE Pri
!#0 N1176 P397 LD 10 -1 Int BE Pri
!#0 N1177 P398 LD 10 -1 Int BE Pri
!#0 N1178 P399 BLD 4 -1 FP BE Pri
!#0 N1179 P399 BLD 5 -1 FP BE Pri
!#A N1178 N1179
!#0 N1180 P399 BLD 6 -1 FP BE Pri
!#0 N1181 P399 BLD 7 -1 FP BE Pri
!#0 N1182 P400 LD 25 -1 Int BE Pri
!#0 N1183 P401 LD 3 -1 FP BE Pri
!#0 N1184 P402 LD 22 -1 Int BE Pri
!#0 N1185 P403 DWLD 8 -1 Int BE Pri
!#0 N1186 P403 DWLD 9 -1 Int BE Pri
!#A N1185 N1186
!#0 N1187 P404 LD 19 -1 Int BE Pri
!#0 N1188 P405 LD 18 -1 Int BE Pri
!#0 N1189 P406 LD 26 -1 FP BE Pri
!#0 N1190 P406 LD 26 -1 FP BE Pri
!#0 N1191 P407 LD 13 -1 Int BE Pri
!#0 N1192 P408 DWLD 22 -1 Int BE Pri
!#0 N1193 P407 LD 13 -1 Int BE Pri
!#0 N1194 P408 DWLD 22 -1 Int BE Pri
!#0 N1195 P409 DWLD 26 -1 FP BE Pri
!#0 N1196 P410 DWLD 4 -1 Int BE Pri
!#0 N1197 P410 DWLD 5 -1 Int BE Pri
!#A N1196 N1197
!#0 N1198 P409 DWLD 26 -1 FP BE Pri
!#0 N1199 P410 DWLD 4 -1 Int BE Pri
!#0 N1200 P410 DWLD 5 -1 Int BE Pri
!#A N1199 N1200
!#0 N1201 P411 BLD 4 -1 FP BE Pri
!#0 N1202 P411 BLD 5 -1 FP BE Pri
!#A N1201 N1202
!#0 N1203 P411 BLD 6 -1 FP BE Pri
!#0 N1204 P411 BLD 7 -1 FP BE Pri
!#0 N1205 P412 DWLD 22 -1 Int BE Pri
!#0 N1206 P413 LD 7 -1 Int BE Pri
!#0 N1207 P414 LD 16 -1 FP BE Pri
!#0 N1208 P414 LD 16 -1 FP BE Pri
!#0 N1209 P415 LD 6 -1 Int BE Pri
!#0 N1210 P416 LD 28 -1 Int BE Pri
!#0 N1211 P415 LD 6 -1 Int BE Pri
!#0 N1212 P416 LD 28 -1 Int BE Pri
!#0 N1213 P417 LD 11 -1 Int BE Pri
!#0 N1214 P418 LD 3 -1 Int BE Pri
!#0 N1215 P419 DWLD 22 -1 Int BE Pri
!#0 N1216 P420 LD 26 -1 Int BE Pri
!#0 N1217 P421 DWLD 24 -1 Int BE Pri
!#0 N1218 P421 DWLD 25 -1 Int BE Pri
!#A N1217 N1218
!#0 N1219 P422 BLD 28 -1 FP BE Pri
!#0 N1220 P422 BLD 29 -1 FP BE Pri
!#A N1219 N1220
!#0 N1221 P422 BLD 30 -1 FP BE Pri
!#0 N1222 P422 BLD 31 -1 FP BE Pri
!#0 N1223 P423 BLD 24 -1 FP BE Pri
!#0 N1224 P423 BLD 25 -1 FP BE Pri
!#A N1223 N1224
!#0 N1225 P423 BLD 26 -1 FP BE Pri
!#0 N1226 P423 BLD 27 -1 FP BE Pri
!#0 N1227 P424 BLD 0 -1 FP BE Pri
!#0 N1228 P424 BLD 1 -1 FP BE Pri
!#A N1227 N1228
!#0 N1229 P424 BLD 2 -1 FP BE Pri
!#0 N1230 P424 BLD 3 -1 FP BE Pri
!#0 N1231 P425 LD 29 -1 Int BE Pri
!#0 N1232 P426 LD 29 -1 Int BE Pri
!#0 N1233 P425 LD 29 -1 Int BE Pri
!#0 N1234 P426 LD 29 -1 Int BE Pri
!#0 N1235 P427 BST 12 0x3f800029 FP BE Pri
!#0 N1236 P427 BST 13 0x3f80002a FP BE Pri
!#A N1235 N1236
!#0 N1237 P427 BST 14 0x3f80002b FP BE Pri
!#0 N1238 P427 BST 15 0x3f80002c FP BE Pri
!#0 N1239 P428 LD 4 -1 Int BE Pri
!#0 N1240 P429 LD 16 -1 Int BE Pri
!#0 N1241 P430 LD 8 -1 FP BE Pri
!#0 N1242 P431 LD 5 -1 Int BE Pri
!#0 N1243 P432 LD 8 -1 Int BE Pri
!#0 N1244 P430 LD 8 -1 FP BE Pri
!#0 N1245 P431 LD 5 -1 Int BE Pri
!#0 N1246 P432 LD 8 -1 Int BE Pri
!#0 N1247 P433 BLD 24 -1 FP BE Pri
!#0 N1248 P433 BLD 25 -1 FP BE Pri
!#A N1247 N1248
!#0 N1249 P433 BLD 26 -1 FP BE Pri
!#0 N1250 P433 BLD 27 -1 FP BE Pri
!#0 N1251 P434 DWLD 8 -1 Int BE Pri
!#0 N1252 P434 DWLD 9 -1 Int BE Pri
!#A N1251 N1252
!#0 N1253 P435 BLD 8 -1 FP BE Pri
!#0 N1254 P435 BLD 9 -1 FP BE Pri
!#A N1253 N1254
!#0 N1255 P435 BLD 10 -1 FP BE Pri
!#0 N1256 P435 BLD 11 -1 FP BE Pri
!#0 N1257 P436 LD 9 -1 Int BE Pri
!#0 N1258 P437 LD 13 -1 Int BE Pri
!#0 N1259 P435 BLD 8 -1 FP BE Pri
!#0 N1260 P435 BLD 9 -1 FP BE Pri
!#A N1259 N1260
!#0 N1261 P435 BLD 10 -1 FP BE Pri
!#0 N1262 P435 BLD 11 -1 FP BE Pri
!#0 N1263 P436 LD 9 -1 Int BE Pri
!#0 N1264 P437 LD 13 -1 Int BE Pri
!#0 N1265 P438 ST 22 0x39 Int BE Pri
!#0 N1266 P439 LD 13 -1 FP BE Pri
!#0 N1268 P439 LD 13 -1 FP BE Pri
!#0 N1270 P441 LD 2 -1 Int BE Pri
!#0 N1271 P442 ST 9 0x3f80002d FP BE Pri
!#0 N1272 P443 LD 15 -1 Int BE Pri
!#0 N1273 P444 ST 13 0x3a Int BE Pri
!#0 N1275 P444 ST 13 0x3b Int BE Pri
!#0 N1277 P446 BLD 16 -1 FP BE Pri
!#0 N1278 P446 BLD 17 -1 FP BE Pri
!#A N1277 N1278
!#0 N1279 P446 BLD 18 -1 FP BE Pri
!#0 N1280 P446 BLD 19 -1 FP BE Pri
!#0 N1281 P447 BLD 8 -1 FP BE Pri
!#0 N1282 P447 BLD 9 -1 FP BE Pri
!#A N1281 N1282
!#0 N1283 P447 BLD 10 -1 FP BE Pri
!#0 N1284 P447 BLD 11 -1 FP BE Pri
!#0 N1285 P448 DWLD 19 -1 Int BE Pri
!#0 N1286 P449 LD 3 -1 Int BE Pri
!#0 N1287 P448 DWLD 19 -1 Int BE Pri
!#0 N1288 P449 LD 3 -1 Int BE Pri
!#0 N1289 P450 LD 28 -1 Int BE Pri
!#0 N1290 P451 BLD 4 -1 FP BE Pri
!#0 N1291 P451 BLD 5 -1 FP BE Pri
!#A N1290 N1291
!#0 N1292 P451 BLD 6 -1 FP BE Pri
!#0 N1293 P451 BLD 7 -1 FP BE Pri
!#0 N1294 P452 LD 12 -1 Int BE Pri
!#0 N1295 P450 LD 28 -1 Int BE Pri
!#0 N1296 P451 BLD 4 -1 FP BE Pri
!#0 N1297 P451 BLD 5 -1 FP BE Pri
!#A N1296 N1297
!#0 N1298 P451 BLD 6 -1 FP BE Pri
!#0 N1299 P451 BLD 7 -1 FP BE Pri
!#0 N1300 P452 LD 12 -1 Int BE Pri
!#0 N1301 P453 DWLD 23 -1 Int BE Pri
!#0 N1302 P454 LD 9 -1 Int BE Pri
!#0 N1303 P455 LD 7 -1 Int BE Pri
!#0 N1304 P456 LD 7 -1 Int BE Pri
!#0 N1305 P455 LD 7 -1 Int BE Pri
!#0 N1306 P456 LD 7 -1 Int BE Pri
!#0 N1307 P457 BLD 8 -1 FP BE Pri
!#0 N1308 P457 BLD 9 -1 FP BE Pri
!#A N1307 N1308
!#0 N1309 P457 BLD 10 -1 FP BE Pri
!#0 N1310 P457 BLD 11 -1 FP BE Pri
!#0 N1311 P458 BLD 4 -1 FP BE Pri
!#0 N1312 P458 BLD 5 -1 FP BE Pri
!#A N1311 N1312
!#0 N1313 P458 BLD 6 -1 FP BE Pri
!#0 N1314 P458 BLD 7 -1 FP BE Pri
!#0 N1315 P459 BLD 12 -1 FP BE Pri
!#0 N1316 P459 BLD 13 -1 FP BE Pri
!#A N1315 N1316
!#0 N1317 P459 BLD 14 -1 FP BE Pri
!#0 N1318 P459 BLD 15 -1 FP BE Pri
!#0 N1319 P460 BLD 24 -1 FP BE Pri
!#0 N1320 P460 BLD 25 -1 FP BE Pri
!#A N1319 N1320
!#0 N1321 P460 BLD 26 -1 FP BE Pri
!#0 N1322 P460 BLD 27 -1 FP BE Pri
!#0 N1323 P461 BLD 12 -1 FP BE Pri
!#0 N1324 P461 BLD 13 -1 FP BE Pri
!#A N1323 N1324
!#0 N1325 P461 BLD 14 -1 FP BE Pri
!#0 N1326 P461 BLD 15 -1 FP BE Pri
!#0 N1327 P460 BLD 24 -1 FP BE Pri
!#0 N1328 P460 BLD 25 -1 FP BE Pri
!#A N1327 N1328
!#0 N1329 P460 BLD 26 -1 FP BE Pri
!#0 N1330 P460 BLD 27 -1 FP BE Pri
!#0 N1331 P461 BLD 12 -1 FP BE Pri
!#0 N1332 P461 BLD 13 -1 FP BE Pri
!#A N1331 N1332
!#0 N1333 P461 BLD 14 -1 FP BE Pri
!#0 N1334 P461 BLD 15 -1 FP BE Pri
!#0 N1335 P462 BLD 24 -1 FP BE Pri
!#0 N1336 P462 BLD 25 -1 FP BE Pri
!#A N1335 N1336
!#0 N1337 P462 BLD 26 -1 FP BE Pri
!#0 N1338 P462 BLD 27 -1 FP BE Pri
!#0 N1339 P463 BLD 28 -1 FP BE Pri
!#0 N1340 P463 BLD 29 -1 FP BE Pri
!#A N1339 N1340
!#0 N1341 P463 BLD 30 -1 FP BE Pri
!#0 N1342 P463 BLD 31 -1 FP BE Pri
!#0 N1343 P462 BLD 24 -1 FP BE Pri
!#0 N1344 P462 BLD 25 -1 FP BE Pri
!#A N1343 N1344
!#0 N1345 P462 BLD 26 -1 FP BE Pri
!#0 N1346 P462 BLD 27 -1 FP BE Pri
!#0 N1347 P463 BLD 28 -1 FP BE Pri
!#0 N1348 P463 BLD 29 -1 FP BE Pri
!#A N1347 N1348
!#0 N1349 P463 BLD 30 -1 FP BE Pri
!#0 N1350 P463 BLD 31 -1 FP BE Pri
!#0 N1351 P464 BLD 12 -1 FP BE Pri
!#0 N1352 P464 BLD 13 -1 FP BE Pri
!#A N1351 N1352
!#0 N1353 P464 BLD 14 -1 FP BE Pri
!#0 N1354 P464 BLD 15 -1 FP BE Pri
!#0 N1355 P465 BLD 28 -1 FP BE Pri
!#0 N1356 P465 BLD 29 -1 FP BE Pri
!#A N1355 N1356
!#0 N1357 P465 BLD 30 -1 FP BE Pri
!#0 N1358 P465 BLD 31 -1 FP BE Pri
!#0 N1359 P466 BLD 0 -1 FP BE Pri
!#0 N1360 P466 BLD 1 -1 FP BE Pri
!#A N1359 N1360
!#0 N1361 P466 BLD 2 -1 FP BE Pri
!#0 N1362 P466 BLD 3 -1 FP BE Pri
!#0 N1363 P466 BLD 0 -1 FP BE Pri
!#0 N1364 P466 BLD 1 -1 FP BE Pri
!#A N1363 N1364
!#0 N1365 P466 BLD 2 -1 FP BE Pri
!#0 N1366 P466 BLD 3 -1 FP BE Pri
!#0 N1367 P467 DWLD 10 -1 FP BE Pri
!#0 N1368 P468 DWLD 28 -1 Int BE Pri
!#0 N1369 P468 DWLD 29 -1 Int BE Pri
!#A N1368 N1369
!#0 N1370 P467 DWLD 10 -1 FP BE Pri
!#0 N1371 P468 DWLD 28 -1 Int BE Pri
!#0 N1372 P468 DWLD 29 -1 Int BE Pri
!#A N1371 N1372
!#0 N1373 P469 DWLD 20 -1 Int BE Pri
!#0 N1374 P469 DWLD 21 -1 Int BE Pri
!#A N1373 N1374
!#0 N1375 P470 BLD 20 -1 FP BE Pri
!#0 N1376 P470 BLD 21 -1 FP BE Pri
!#A N1375 N1376
!#0 N1377 P470 BLD 22 -1 FP BE Pri
!#0 N1378 P470 BLD 23 -1 FP BE Pri
!#0 N1379 P469 DWLD 20 -1 Int BE Pri
!#0 N1380 P469 DWLD 21 -1 Int BE Pri
!#A N1379 N1380
!#0 N1381 P470 BLD 20 -1 FP BE Pri
!#0 N1382 P470 BLD 21 -1 FP BE Pri
!#A N1381 N1382
!#0 N1383 P470 BLD 22 -1 FP BE Pri
!#0 N1384 P470 BLD 23 -1 FP BE Pri
!#0 N1385 P471 BLD 0 -1 FP BE Pri
!#0 N1386 P471 BLD 1 -1 FP BE Pri
!#A N1385 N1386
!#0 N1387 P471 BLD 2 -1 FP BE Pri
!#0 N1388 P471 BLD 3 -1 FP BE Pri
!#0 N1389 P472 LD 25 -1 Int BE Pri
!#0 N1390 P473 LD 30 -1 Int LE Pri
!#0 N1391 P471 BLD 0 -1 FP BE Pri
!#0 N1392 P471 BLD 1 -1 FP BE Pri
!#A N1391 N1392
!#0 N1393 P471 BLD 2 -1 FP BE Pri
!#0 N1394 P471 BLD 3 -1 FP BE Pri
!#0 N1395 P472 LD 25 -1 Int BE Pri
!#0 N1396 P473 LD 30 -1 Int LE Pri
!#0 N1397 P474 BLD 20 -1 FP BE Pri
!#0 N1398 P474 BLD 21 -1 FP BE Pri
!#A N1397 N1398
!#0 N1399 P474 BLD 22 -1 FP BE Pri
!#0 N1400 P474 BLD 23 -1 FP BE Pri
!#0 N1401 P474 BLD 20 -1 FP BE Pri
!#0 N1402 P474 BLD 21 -1 FP BE Pri
!#A N1401 N1402
!#0 N1403 P474 BLD 22 -1 FP BE Pri
!#0 N1404 P474 BLD 23 -1 FP BE Pri
!#0 N1405 P475 BLD 0 -1 FP BE Pri
!#0 N1406 P475 BLD 1 -1 FP BE Pri
!#A N1405 N1406
!#0 N1407 P475 BLD 2 -1 FP BE Pri
!#0 N1408 P475 BLD 3 -1 FP BE Pri
!#0 N1409 P475 BLD 0 -1 FP BE Pri
!#0 N1410 P475 BLD 1 -1 FP BE Pri
!#A N1409 N1410
!#0 N1411 P475 BLD 2 -1 FP BE Pri
!#0 N1412 P475 BLD 3 -1 FP BE Pri
!#0 N1413 P476 BLD 16 -1 FP BE Pri
!#0 N1414 P476 BLD 17 -1 FP BE Pri
!#A N1413 N1414
!#0 N1415 P476 BLD 18 -1 FP BE Pri
!#0 N1416 P476 BLD 19 -1 FP BE Pri
!#0 N1417 P477 BLD 28 -1 FP BE Pri
!#0 N1418 P477 BLD 29 -1 FP BE Pri
!#A N1417 N1418
!#0 N1419 P477 BLD 30 -1 FP BE Pri
!#0 N1420 P477 BLD 31 -1 FP BE Pri
!#0 N1421 P478 LD 24 -1 Int BE Pri
!#0 N1422 P479 DWST 16 0x3c Int BE Pri
!#0 N1423 P479 DWST 17 0x3d Int BE Pri
!#A N1422 N1423
!#0 N1424 P480 LD 26 -1 Int BE Pri
!#0 N1425 P481 DWLD 4 -1 Int BE Pri
!#0 N1426 P481 DWLD 5 -1 Int BE Pri
!#A N1425 N1426
!#0 N1427 P482 BLD 0 -1 FP BE Pri
!#0 N1428 P482 BLD 1 -1 FP BE Pri
!#A N1427 N1428
!#0 N1429 P482 BLD 2 -1 FP BE Pri
!#0 N1430 P482 BLD 3 -1 FP BE Pri
!#0 N1431 P483 DWLD 23 -1 FP BE Pri
!#0 N1432 P484 DWLD 16 -1 Int BE Pri
!#0 N1433 P484 DWLD 17 -1 Int BE Pri
!#A N1432 N1433
!#0 N1434 P485 DWLD 27 -1 FP BE Pri
!#0 N1435 P486 LD 31 -1 Int BE Pri
!#0 N1436 P486 CAS 31 -1 N1435 0x3e Int BE Pri
!#0 N1437 P487 LD 10 -1 Int BE Pri
!#0 N1438 P488 BLD 28 -1 FP BE Pri
!#0 N1439 P488 BLD 29 -1 FP BE Pri
!#A N1438 N1439
!#0 N1440 P488 BLD 30 -1 FP BE Pri
!#0 N1441 P488 BLD 31 -1 FP BE Pri
!#0 N1442 P489 LD 14 -1 Int BE Pri
!#0 N1443 P490 BLD 8 -1 FP BE Pri
!#0 N1444 P490 BLD 9 -1 FP BE Pri
!#A N1443 N1444
!#0 N1445 P490 BLD 10 -1 FP BE Pri
!#0 N1446 P490 BLD 11 -1 FP BE Pri
!#0 N1447 P491 BLD 16 -1 FP BE Pri
!#0 N1448 P491 BLD 17 -1 FP BE Pri
!#A N1447 N1448
!#0 N1449 P491 BLD 18 -1 FP BE Pri
!#0 N1450 P491 BLD 19 -1 FP BE Pri
!#0 N1451 P492 BST 28 0x3f80002e FP BE Pri
!#0 N1452 P492 BST 29 0x3f80002f FP BE Pri
!#A N1451 N1452
!#0 N1453 P492 BST 30 0x3f800030 FP BE Pri
!#0 N1454 P492 BST 31 0x3f800031 FP BE Pri
!#0 N1455 P491 BLD 16 -1 FP BE Pri
!#0 N1456 P491 BLD 17 -1 FP BE Pri
!#A N1455 N1456
!#0 N1457 P491 BLD 18 -1 FP BE Pri
!#0 N1458 P491 BLD 19 -1 FP BE Pri
!#0 N1459 P492 BST 28 0x3f800032 FP BE Pri
!#0 N1460 P492 BST 29 0x3f800033 FP BE Pri
!#A N1459 N1460
!#0 N1461 P492 BST 30 0x3f800034 FP BE Pri
!#0 N1462 P492 BST 31 0x3f800035 FP BE Pri
!#0 N1463 P493 DWLD 24 -1 Int LE Pri
!#0 N1464 P493 DWLD 25 -1 Int LE Pri
!#A N1463 N1464
!#0 N1465 P494 DWLD 20 -1 Int BE Pri
!#0 N1466 P494 DWLD 21 -1 Int BE Pri
!#A N1465 N1466
!#0 N1467 P494 CASX 20 -1 N1465 0x3f Int BE Pri
!#0 N1468 P494 CASX 21 -1 N1466 0x40 Int BE Pri
!#A N1467 N1468
!#0 N1469 P493 DWLD 24 -1 Int LE Pri
!#0 N1470 P493 DWLD 25 -1 Int LE Pri
!#A N1469 N1470
!#0 N1471 P494 DWLD 20 -1 Int BE Pri
!#0 N1472 P494 DWLD 21 -1 Int BE Pri
!#A N1471 N1472
!#0 N1473 P494 CASX 20 -1 N1471 0x41 Int BE Pri
!#0 N1474 P494 CASX 21 -1 N1472 0x42 Int BE Pri
!#A N1473 N1474
!#0 N1475 P495 DWLD 11 -1 Int BE Pri
!#0 N1476 P496 LD 25 -1 Int BE Pri
!#0 N1477 P497 LD 29 -1 Int BE Pri
!#0 N1478 P498 LD 2 -1 Int BE Pri
!#0 N1479 P499 LD 13 -1 Int BE Pri
!#0 N1480 P500 LD 27 -1 Int BE Pri
!#0 N1481 P499 LD 13 -1 Int BE Pri
!#0 N1482 P500 LD 27 -1 Int BE Pri
!#0 N1483 P501 BLD 8 -1 FP BE Pri
!#0 N1484 P501 BLD 9 -1 FP BE Pri
!#A N1483 N1484
!#0 N1485 P501 BLD 10 -1 FP BE Pri
!#0 N1486 P501 BLD 11 -1 FP BE Pri
!#0 N1487 P502 DWLD 30 -1 Int BE Pri
!#0 N1488 P503 LD 11 -1 Int BE Pri
!#0 N1489 P502 DWLD 30 -1 Int BE Pri
!#0 N1490 P503 LD 11 -1 Int BE Pri
!#0 N1491 P504 BLD 4 -1 FP BE Pri
!#0 N1492 P504 BLD 5 -1 FP BE Pri
!#A N1491 N1492
!#0 N1493 P504 BLD 6 -1 FP BE Pri
!#0 N1494 P504 BLD 7 -1 FP BE Pri
!#0 N1495 P505 DWLD 30 -1 Int BE Pri
!#0 N1496 P506 LD 4 -1 Int BE Pri
!#0 N1497 P504 BLD 4 -1 FP BE Pri
!#0 N1498 P504 BLD 5 -1 FP BE Pri
!#A N1497 N1498
!#0 N1499 P504 BLD 6 -1 FP BE Pri
!#0 N1500 P504 BLD 7 -1 FP BE Pri
!#0 N1501 P505 DWLD 30 -1 Int BE Pri
!#0 N1502 P506 LD 4 -1 Int BE Pri
!#0 N1503 P507 LD 23 -1 Int BE Pri
!#0 N1504 P508 BLD 24 -1 FP BE Pri
!#0 N1505 P508 BLD 25 -1 FP BE Pri
!#A N1504 N1505
!#0 N1506 P508 BLD 26 -1 FP BE Pri
!#0 N1507 P508 BLD 27 -1 FP BE Pri
!#0 N1508 P509 LD 3 -1 Int BE Pri
!#0 N1509 P510 DWLD 22 -1 Int BE Pri
!#0 N1510 P511 BLD 12 -1 FP BE Pri
!#0 N1511 P511 BLD 13 -1 FP BE Pri
!#A N1510 N1511
!#0 N1512 P511 BLD 14 -1 FP BE Pri
!#0 N1513 P511 BLD 15 -1 FP BE Pri
!#0 N1514 P512 LD 18 -1 Int LE Pri
!#0 N1515 P513 LD 28 -1 Int BE Pri
!#0 N1516 P514 LD 15 -1 Int BE Pri
!#0 N1517 P513 LD 28 -1 Int BE Pri
!#0 N1518 P514 LD 15 -1 Int BE Pri
!#0 N1519 P515 LD 25 -1 FP BE Pri
!#0 N1520 P515 LD 25 -1 FP BE Pri
!#0 N1521 P516 BLD 12 -1 FP BE Pri
!#0 N1522 P516 BLD 13 -1 FP BE Pri
!#A N1521 N1522
!#0 N1523 P516 BLD 14 -1 FP BE Pri
!#0 N1524 P516 BLD 15 -1 FP BE Pri
!#0 N1525 P517 BLD 8 -1 FP BE Pri
!#0 N1526 P517 BLD 9 -1 FP BE Pri
!#A N1525 N1526
!#0 N1527 P517 BLD 10 -1 FP BE Pri
!#0 N1528 P517 BLD 11 -1 FP BE Pri
!#0 N1529 P518 DWLD 0 -1 Int BE Pri
!#0 N1530 P518 DWLD 1 -1 Int BE Pri
!#A N1529 N1530
!#0 N1531 P519 DWLD 12 -1 Int BE Pri
!#0 N1532 P519 DWLD 13 -1 Int BE Pri
!#A N1531 N1532
!#0 N1533 P519 DWLD 12 -1 Int BE Pri
!#0 N1534 P519 DWLD 13 -1 Int BE Pri
!#A N1533 N1534
!#0 N1535 P520 BLD 8 -1 FP BE Pri
!#0 N1536 P520 BLD 9 -1 FP BE Pri
!#A N1535 N1536
!#0 N1537 P520 BLD 10 -1 FP BE Pri
!#0 N1538 P520 BLD 11 -1 FP BE Pri
!#0 N1539 P521 LD 22 -1 Int BE Pri
!#0 N1540 P522 LD 14 -1 Int BE Pri
!#0 N1541 P521 LD 22 -1 Int BE Pri
!#0 N1542 P522 LD 14 -1 Int BE Pri
!#0 N1543 P523 BLD 16 -1 FP BE Pri
!#0 N1544 P523 BLD 17 -1 FP BE Pri
!#A N1543 N1544
!#0 N1545 P523 BLD 18 -1 FP BE Pri
!#0 N1546 P523 BLD 19 -1 FP BE Pri
!#0 N1547 P524 DWLD 12 -1 Int BE Pri
!#0 N1548 P524 DWLD 13 -1 Int BE Pri
!#A N1547 N1548
!#0 N1549 P525 BLD 24 -1 FP BE Pri
!#0 N1550 P525 BLD 25 -1 FP BE Pri
!#A N1549 N1550
!#0 N1551 P525 BLD 26 -1 FP BE Pri
!#0 N1552 P525 BLD 27 -1 FP BE Pri
!#0 N1553 P526 LD 31 -1 Int BE Pri
!#0 N1554 P527 DWLD 10 -1 Int BE Pri
!#0 N1555 P528 DWST 16 0x43 Int BE Pri
!#0 N1556 P528 DWST 17 0x44 Int BE Pri
!#A N1555 N1556
!#0 N1557 P528 DWST 16 0x45 Int BE Pri
!#0 N1558 P528 DWST 17 0x46 Int BE Pri
!#A N1557 N1558
!#0 N1559 P529 LD 31 -1 Int BE Pri
!#0 N1560 P530 LD 2 -1 Int BE Pri
!#0 N1561 P531 ST 24 0x47 Int BE Pri
!#0 N1562 P532 BLD 4 -1 FP BE Pri
!#0 N1563 P532 BLD 5 -1 FP BE Pri
!#A N1562 N1563
!#0 N1564 P532 BLD 6 -1 FP BE Pri
!#0 N1565 P532 BLD 7 -1 FP BE Pri
!#0 N1566 P533 LD 22 -1 Int BE Pri
!#0 N1567 P534 LD 31 -1 Int BE Pri
!#0 N1568 P535 LD 22 -1 Int BE Pri
!#0 N1569 P535 CAS 22 -1 N1568 0x48 Int BE Pri
!#0 N1570 P536 LD 3 -1 Int BE Pri
!#0 N1571 P537 LD 15 -1 Int BE Pri
!#0 N1572 P538 DWLD 15 -1 Int BE Pri
!#0 N1573 P539 LD 29 -1 Int BE Pri
!#0 N1574 P540 ST 29 0x49 Int BE Pri
!#0 N1575 P541 LD 10 -1 Int BE Pri
!#0 N1576 P542 LD 11 -1 Int BE Pri
!#0 N1581 P545 SWAP 17 0xffffffff 0x4a Int BE Pri
!#0 N1582 P546 BLD 8 -1 FP BE Pri
!#0 N1583 P546 BLD 9 -1 FP BE Pri
!#A N1582 N1583
!#0 N1584 P546 BLD 10 -1 FP BE Pri
!#0 N1585 P546 BLD 11 -1 FP BE Pri
!#0 N1586 P547 LD 28 -1 Int LE Pri
!#0 N1587 P545 SWAP 17 0xffffffff 0x4b Int BE Pri
!#0 N1588 P546 BLD 8 -1 FP BE Pri
!#0 N1589 P546 BLD 9 -1 FP BE Pri
!#A N1588 N1589
!#0 N1590 P546 BLD 10 -1 FP BE Pri
!#0 N1591 P546 BLD 11 -1 FP BE Pri
!#0 N1592 P547 LD 28 -1 Int LE Pri
!#0 N1593 P548 DWLD 7 -1 Int BE Pri
!#0 N1594 P549 DWLD 11 -1 Int BE Pri
!#0 N1595 P548 DWLD 7 -1 Int BE Pri
!#0 N1596 P549 DWLD 11 -1 Int BE Pri
!#0 N1597 P550 BLD 12 -1 FP BE Pri
!#0 N1598 P550 BLD 13 -1 FP BE Pri
!#A N1597 N1598
!#0 N1599 P550 BLD 14 -1 FP BE Pri
!#0 N1600 P550 BLD 15 -1 FP BE Pri
!#0 N1601 P551 DWLD 8 -1 FP BE Pri
!#0 N1602 P551 DWLD 9 -1 FP BE Pri
!#A N1601 N1602
!#0 N1603 P550 BLD 12 -1 FP BE Pri
!#0 N1604 P550 BLD 13 -1 FP BE Pri
!#A N1603 N1604
!#0 N1605 P550 BLD 14 -1 FP BE Pri
!#0 N1606 P550 BLD 15 -1 FP BE Pri
!#0 N1607 P551 DWLD 8 -1 FP BE Pri
!#0 N1608 P551 DWLD 9 -1 FP BE Pri
!#A N1607 N1608
!#0 N1609 P552 DWLD 31 -1 Int BE Pri
!#0 N1610 P553 LD 4 -1 Int BE Pri
!#0 N1611 P552 DWLD 31 -1 Int BE Pri
!#0 N1612 P553 LD 4 -1 Int BE Pri
!#0 N1613 P554 ST 25 0x4c Int BE Pri
!#0 N1614 P554 ST 25 0x4d Int BE Pri
!#0 N1615 P555 DWLD 15 -1 Int BE Pri
!#0 N1616 P556 LD 24 -1 Int BE Pri
!#0 N1617 P555 DWLD 15 -1 Int BE Pri
!#0 N1618 P556 LD 24 -1 Int BE Pri
!#0 N1619 P557 LD 20 -1 Int BE Pri
!#0 N1620 P557 CAS 20 -1 N1619 0x4e Int BE Pri
!#0 N1621 P557 LD 20 -1 Int BE Pri
!#0 N1622 P557 CAS 20 -1 N1621 0x4f Int BE Pri
!#0 N1623 P558 BLD 8 -1 FP BE Pri
!#0 N1624 P558 BLD 9 -1 FP BE Pri
!#A N1623 N1624
!#0 N1625 P558 BLD 10 -1 FP BE Pri
!#0 N1626 P558 BLD 11 -1 FP BE Pri
!#0 N1627 P559 DWLD 12 -1 Int BE Pri
!#0 N1628 P559 DWLD 13 -1 Int BE Pri
!#A N1627 N1628
!#0 N1629 P558 BLD 8 -1 FP BE Pri
!#0 N1630 P558 BLD 9 -1 FP BE Pri
!#A N1629 N1630
!#0 N1631 P558 BLD 10 -1 FP BE Pri
!#0 N1632 P558 BLD 11 -1 FP BE Pri
!#0 N1633 P559 DWLD 12 -1 Int BE Pri
!#0 N1634 P559 DWLD 13 -1 Int BE Pri
!#A N1633 N1634
!#0 N1635 P560 BLD 4 -1 FP BE Pri
!#0 N1636 P560 BLD 5 -1 FP BE Pri
!#A N1635 N1636
!#0 N1637 P560 BLD 6 -1 FP BE Pri
!#0 N1638 P560 BLD 7 -1 FP BE Pri
!#0 N1639 P561 BLD 0 -1 FP BE Pri
!#0 N1640 P561 BLD 1 -1 FP BE Pri
!#A N1639 N1640
!#0 N1641 P561 BLD 2 -1 FP BE Pri
!#0 N1642 P561 BLD 3 -1 FP BE Pri
!#0 N1643 P562 LD 4 -1 Int BE Pri
!#0 N1644 P563 LD 8 -1 Int BE Pri
!#0 N1645 P564 BLD 0 -1 FP BE Pri
!#0 N1646 P564 BLD 1 -1 FP BE Pri
!#A N1645 N1646
!#0 N1647 P564 BLD 2 -1 FP BE Pri
!#0 N1648 P564 BLD 3 -1 FP BE Pri
!#0 N1649 P565 LD 0 -1 Int BE Pri
!#0 N1650 P566 LD 23 -1 Int BE Pri
!#0 N1651 P565 LD 0 -1 Int BE Pri
!#0 N1652 P566 LD 23 -1 Int BE Pri
!#0 N1653 P567 BLD 8 -1 FP BE Pri
!#0 N1654 P567 BLD 9 -1 FP BE Pri
!#A N1653 N1654
!#0 N1655 P567 BLD 10 -1 FP BE Pri
!#0 N1656 P567 BLD 11 -1 FP BE Pri
!#0 N1657 P568 LD 23 -1 Int LE Pri
!#0 N1659 P570 LD 21 -1 Int BE Pri
!#0 N1660 P568 LD 23 -1 Int LE Pri
!#0 N1662 P570 LD 21 -1 Int BE Pri
!#0 N1663 P571 BLD 4 -1 FP BE Pri
!#0 N1664 P571 BLD 5 -1 FP BE Pri
!#A N1663 N1664
!#0 N1665 P571 BLD 6 -1 FP BE Pri
!#0 N1666 P571 BLD 7 -1 FP BE Pri
!#0 N1667 P572 DWLD 4 -1 Int BE Pri
!#0 N1668 P572 DWLD 5 -1 Int BE Pri
!#A N1667 N1668
!#0 N1669 P571 BLD 4 -1 FP BE Pri
!#0 N1670 P571 BLD 5 -1 FP BE Pri
!#A N1669 N1670
!#0 N1671 P571 BLD 6 -1 FP BE Pri
!#0 N1672 P571 BLD 7 -1 FP BE Pri
!#0 N1673 P572 DWLD 4 -1 Int BE Pri
!#0 N1674 P572 DWLD 5 -1 Int BE Pri
!#A N1673 N1674
!#0 N1675 P573 LD 8 -1 Int BE Pri
!#0 N1676 P574 LD 24 -1 Int BE Pri
!#0 N1677 P573 LD 8 -1 Int BE Pri
!#0 N1678 P574 LD 24 -1 Int BE Pri
!#0 N1679 P575 DWLD 11 -1,0x0 Int BE Pri
!#0 N1680 P575 CASX 11 -1,0x0 N1679 0x50 Int BE Pri
!#0 N1681 P576 BLD 16 -1 FP BE Pri
!#0 N1682 P576 BLD 17 -1 FP BE Pri
!#A N1681 N1682
!#0 N1683 P576 BLD 18 -1 FP BE Pri
!#0 N1684 P576 BLD 19 -1 FP BE Pri
!#0 N1685 P577 LD 5 -1 Int BE Pri
!#0 N1686 P578 LD 3 -1 Int BE Pri
!#0 N1687 P577 LD 5 -1 Int BE Pri
!#0 N1688 P578 LD 3 -1 Int BE Pri
!#0 N1690 P580 DWLD 26 -1 Int BE Pri
!#0 N1691 P581 DWLD 24 -1 Int BE Pri
!#0 N1692 P581 DWLD 25 -1 Int BE Pri
!#A N1691 N1692
!#0 N1693 P582 LD 9 -1 Int BE Pri
!#0 N1694 P580 DWLD 26 -1 Int BE Pri
!#0 N1695 P581 DWLD 24 -1 Int BE Pri
!#0 N1696 P581 DWLD 25 -1 Int BE Pri
!#A N1695 N1696
!#0 N1697 P582 LD 9 -1 Int BE Pri
!#0 N1698 P583 DWLD 7 -1 Int LE Pri
!#0 N1699 P584 BLD 4 -1 FP BE Pri
!#0 N1700 P584 BLD 5 -1 FP BE Pri
!#A N1699 N1700
!#0 N1701 P584 BLD 6 -1 FP BE Pri
!#0 N1702 P584 BLD 7 -1 FP BE Pri
!#0 N1703 P585 LD 19 -1 Int BE Pri
!#0 N1704 P586 LD 8 -1 Int BE Pri
!#0 N1705 P587 LD 16 -1 Int BE Pri
!#0 N1706 P588 LD 2 -1 Int BE Pri
!#0 N1707 P589 DWLD 8 -1 Int BE Pri
!#0 N1708 P589 DWLD 9 -1 Int BE Pri
!#A N1707 N1708
!#0 N1709 P590 LD 19 -1 Int BE Pri
!#0 N1710 P591 BLD 20 -1 FP BE Pri
!#0 N1711 P591 BLD 21 -1 FP BE Pri
!#A N1710 N1711
!#0 N1712 P591 BLD 22 -1 FP BE Pri
!#0 N1713 P591 BLD 23 -1 FP BE Pri
!#0 N1714 P592 LD 11 -1 Int BE Pri
!#0 N1715 P593 LD 4 -1 Int BE Pri
!#0 N1716 P594 BLD 24 -1 FP BE Pri
!#0 N1717 P594 BLD 25 -1 FP BE Pri
!#A N1716 N1717
!#0 N1718 P594 BLD 26 -1 FP BE Pri
!#0 N1719 P594 BLD 27 -1 FP BE Pri
!#0 N1720 P595 BLD 12 -1 FP BE Pri
!#0 N1721 P595 BLD 13 -1 FP BE Pri
!#A N1720 N1721
!#0 N1722 P595 BLD 14 -1 FP BE Pri
!#0 N1723 P595 BLD 15 -1 FP BE Pri
!#0 N1724 P595 BLD 12 -1 FP BE Pri
!#0 N1725 P595 BLD 13 -1 FP BE Pri
!#A N1724 N1725
!#0 N1726 P595 BLD 14 -1 FP BE Pri
!#0 N1727 P595 BLD 15 -1 FP BE Pri
!#0 N1729 P597 DWLD 4 -1 Int BE Pri
!#0 N1730 P597 DWLD 5 -1 Int BE Pri
!#A N1729 N1730
!#0 N1732 P597 DWLD 4 -1 Int BE Pri
!#0 N1733 P597 DWLD 5 -1 Int BE Pri
!#A N1732 N1733
!#0 N1734 P598 LD 28 -1 Int BE Pri
!#0 N1735 P599 LD 9 -1 Int BE Pri
!#0 N1736 P600 BLD 4 -1 FP BE Pri
!#0 N1737 P600 BLD 5 -1 FP BE Pri
!#A N1736 N1737
!#0 N1738 P600 BLD 6 -1 FP BE Pri
!#0 N1739 P600 BLD 7 -1 FP BE Pri
!#0 N1740 P600 BLD 4 -1 FP BE Pri
!#0 N1741 P600 BLD 5 -1 FP BE Pri
!#A N1740 N1741
!#0 N1742 P600 BLD 6 -1 FP BE Pri
!#0 N1743 P600 BLD 7 -1 FP BE Pri
!#0 N1746 P602 DWLD 15 -1 Int BE Pri
!#0 N1747 P603 LD 28 -1 Int LE Pri
!#0 N1748 P604 BLD 12 -1 FP BE Pri
!#0 N1749 P604 BLD 13 -1 FP BE Pri
!#A N1748 N1749
!#0 N1750 P604 BLD 14 -1 FP BE Pri
!#0 N1751 P604 BLD 15 -1 FP BE Pri
!#0 N1752 P605 LD 0 -1 Int BE Pri
!#0 N1753 P606 LD 21 -1 Int BE Pri
!#0 N1754 P604 BLD 12 -1 FP BE Pri
!#0 N1755 P604 BLD 13 -1 FP BE Pri
!#A N1754 N1755
!#0 N1756 P604 BLD 14 -1 FP BE Pri
!#0 N1757 P604 BLD 15 -1 FP BE Pri
!#0 N1758 P605 LD 0 -1 Int BE Pri
!#0 N1759 P606 LD 21 -1 Int BE Pri
!#0 N1760 P607 BLD 4 -1 FP BE Pri
!#0 N1761 P607 BLD 5 -1 FP BE Pri
!#A N1760 N1761
!#0 N1762 P607 BLD 6 -1 FP BE Pri
!#0 N1763 P607 BLD 7 -1 FP BE Pri
!#0 N1764 P608 DWLD 27 -1 FP BE Pri
!#0 N1765 P609 BLD 16 -1 FP BE Pri
!#0 N1766 P609 BLD 17 -1 FP BE Pri
!#A N1765 N1766
!#0 N1767 P609 BLD 18 -1 FP BE Pri
!#0 N1768 P609 BLD 19 -1 FP BE Pri
!#0 N1769 P610 LD 12 -1 FP BE Pri
!#0 N1770 P609 BLD 16 -1 FP BE Pri
!#0 N1771 P609 BLD 17 -1 FP BE Pri
!#A N1770 N1771
!#0 N1772 P609 BLD 18 -1 FP BE Pri
!#0 N1773 P609 BLD 19 -1 FP BE Pri
!#0 N1774 P610 LD 12 -1 FP BE Pri
!#0 N1775 P611 DWLD 4 -1 Int BE Pri
!#0 N1776 P611 DWLD 5 -1 Int BE Pri
!#A N1775 N1776
!#0 N1777 P612 LD 10 -1 Int BE Pri
!#0 N1778 P613 LD 6 -1 Int LE Pri
!#0 N1779 P614 BSTC 8 0x3f800036 FP BE Pri
!#0 N1780 P614 BSTC 9 0x3f800037 FP BE Pri
!#A N1779 N1780
!#0 N1781 P614 BSTC 10 0x3f800038 FP BE Pri
!#0 N1782 P614 BSTC 11 0x3f800039 FP BE Pri
!#0 N1783 P615 BLD 28 -1 FP BE Pri
!#0 N1784 P615 BLD 29 -1 FP BE Pri
!#A N1783 N1784
!#0 N1785 P615 BLD 30 -1 FP BE Pri
!#0 N1786 P615 BLD 31 -1 FP BE Pri
!#0 N1787 P616 DWLD 18 -1,0x0 Int BE Pri
!#0 N1788 P616 CASX 18 -1,0x0 N1787 0x51 Int BE Pri
!#0 N1789 P617 DWLD 0 -1 Int LE Pri
!#0 N1790 P617 DWLD 1 -1 Int LE Pri
!#A N1789 N1790
!#0 N1791 P618 DWLD 15 -1 Int LE Pri
!#0 N1792 P619 LD 19 -1 Int BE Pri
!#0 N1793 P618 DWLD 15 -1 Int LE Pri
!#0 N1794 P619 LD 19 -1 Int BE Pri
!#0 N1795 P620 DWLD 12 -1 Int LE Pri
!#0 N1796 P620 DWLD 13 -1 Int LE Pri
!#A N1795 N1796
!#0 N1797 P621 LD 13 -1 Int BE Pri
!#0 N1798 P622 LD 28 -1 Int BE Pri
!#0 N1799 P620 DWLD 12 -1 Int LE Pri
!#0 N1800 P620 DWLD 13 -1 Int LE Pri
!#A N1799 N1800
!#0 N1801 P621 LD 13 -1 Int BE Pri
!#0 N1802 P622 LD 28 -1 Int BE Pri
!#0 N1805 P624 LD 0 -1 Int BE Pri
!#0 N1806 P625 BLD 8 -1 FP BE Pri
!#0 N1807 P625 BLD 9 -1 FP BE Pri
!#A N1806 N1807
!#0 N1808 P625 BLD 10 -1 FP BE Pri
!#0 N1809 P625 BLD 11 -1 FP BE Pri
!#0 N1810 P626 LD 15 -1 Int BE Pri
!#0 N1811 P624 LD 0 -1 Int BE Pri
!#0 N1812 P625 BLD 8 -1 FP BE Pri
!#0 N1813 P625 BLD 9 -1 FP BE Pri
!#A N1812 N1813
!#0 N1814 P625 BLD 10 -1 FP BE Pri
!#0 N1815 P625 BLD 11 -1 FP BE Pri
!#0 N1816 P626 LD 15 -1 Int BE Pri
!#0 N1817 P627 DWLD 12 -1 Int LE Pri
!#0 N1818 P627 DWLD 13 -1 Int LE Pri
!#A N1817 N1818
!#0 N1819 P628 LD 27 -1 Int BE Pri
!#0 N1820 P629 LD 30 -1 Int BE Pri
!#0 N1821 P630 LD 17 -1 FP BE Pri
!#0 N1822 P631 DWLD 4 -1 Int BE Pri
!#0 N1823 P631 DWLD 5 -1 Int BE Pri
!#A N1822 N1823
!#0 N1824 P632 BLD 8 -1 FP BE Pri
!#0 N1825 P632 BLD 9 -1 FP BE Pri
!#A N1824 N1825
!#0 N1826 P632 BLD 10 -1 FP BE Pri
!#0 N1827 P632 BLD 11 -1 FP BE Pri
!#0 N1828 P631 DWLD 4 -1 Int BE Pri
!#0 N1829 P631 DWLD 5 -1 Int BE Pri
!#A N1828 N1829
!#0 N1830 P632 BLD 8 -1 FP BE Pri
!#0 N1831 P632 BLD 9 -1 FP BE Pri
!#A N1830 N1831
!#0 N1832 P632 BLD 10 -1 FP BE Pri
!#0 N1833 P632 BLD 11 -1 FP BE Pri
!#0 N1834 P633 SWAP 7 0xffffffff 0x52 Int BE Pri
!#0 N1835 P634 LD 31 -1 Int BE Pri
!#0 N1836 P635 LD 13 -1 Int BE Pri
!#0 N1837 P636 BLD 0 -1 FP BE Pri
!#0 N1838 P636 BLD 1 -1 FP BE Pri
!#A N1837 N1838
!#0 N1839 P636 BLD 2 -1 FP BE Pri
!#0 N1840 P636 BLD 3 -1 FP BE Pri
!#0 N1841 P637 LD 27 -1 Int BE Pri
!#0 N1842 P638 BSTC 24 0x3f80003a FP BE Pri
!#0 N1843 P638 BSTC 25 0x3f80003b FP BE Pri
!#A N1842 N1843
!#0 N1844 P638 BSTC 26 0x3f80003c FP BE Pri
!#0 N1845 P638 BSTC 27 0x3f80003d FP BE Pri
!#0 N1847 P638 BSTC 24 0x3f80003e FP BE Pri
!#0 N1848 P638 BSTC 25 0x3f80003f FP BE Pri
!#A N1847 N1848
!#0 N1849 P638 BSTC 26 0x3f800040 FP BE Pri
!#0 N1850 P638 BSTC 27 0x3f800041 FP BE Pri
!#0 N1852 P640 BLD 24 -1 FP BE Pri
!#0 N1853 P640 BLD 25 -1 FP BE Pri
!#A N1852 N1853
!#0 N1854 P640 BLD 26 -1 FP BE Pri
!#0 N1855 P640 BLD 27 -1 FP BE Pri
!#0 N1856 P641 BLD 12 -1 FP BE Pri
!#0 N1857 P641 BLD 13 -1 FP BE Pri
!#A N1856 N1857
!#0 N1858 P641 BLD 14 -1 FP BE Pri
!#0 N1859 P641 BLD 15 -1 FP BE Pri
!#0 N1860 P640 BLD 24 -1 FP BE Pri
!#0 N1861 P640 BLD 25 -1 FP BE Pri
!#A N1860 N1861
!#0 N1862 P640 BLD 26 -1 FP BE Pri
!#0 N1863 P640 BLD 27 -1 FP BE Pri
!#0 N1864 P641 BLD 12 -1 FP BE Pri
!#0 N1865 P641 BLD 13 -1 FP BE Pri
!#A N1864 N1865
!#0 N1866 P641 BLD 14 -1 FP BE Pri
!#0 N1867 P641 BLD 15 -1 FP BE Pri
!#0 N1868 P642 DWLD 27 -1 Int BE Pri
!#0 N1869 P643 LD 10 -1 FP BE Pri
!#0 N1870 P644 LD 25 -1 Int BE Pri
!#0 N1871 P642 DWLD 27 -1 Int BE Pri
!#0 N1872 P643 LD 10 -1 FP BE Pri
!#0 N1873 P644 LD 25 -1 Int BE Pri
!#0 N1874 P645 DWLD 15 -1 Int BE Pri
!#0 N1875 P646 DWLD 10 -1 Int BE Pri
!#0 N1876 P647 DWLD 14 -1 FP BE Pri
!#0 N1877 P648 BLD 20 -1 FP BE Pri
!#0 N1878 P648 BLD 21 -1 FP BE Pri
!#A N1877 N1878
!#0 N1879 P648 BLD 22 -1 FP BE Pri
!#0 N1880 P648 BLD 23 -1 FP BE Pri
!#0 N1881 P649 DWST 28 0x53 Int LE Pri
!#0 N1882 P649 DWST 29 0x54 Int LE Pri
!#A N1881 N1882
!#0 N1883 P650 BLD 28 -1 FP BE Pri
!#0 N1884 P650 BLD 29 -1 FP BE Pri
!#A N1883 N1884
!#0 N1885 P650 BLD 30 -1 FP BE Pri
!#0 N1886 P650 BLD 31 -1 FP BE Pri
!#0 N1887 P649 DWST 28 0x55 Int LE Pri
!#0 N1888 P649 DWST 29 0x56 Int LE Pri
!#A N1887 N1888
!#0 N1889 P650 BLD 28 -1 FP BE Pri
!#0 N1890 P650 BLD 29 -1 FP BE Pri
!#A N1889 N1890
!#0 N1891 P650 BLD 30 -1 FP BE Pri
!#0 N1892 P650 BLD 31 -1 FP BE Pri
!#0 N1893 P651 LD 3 -1 Int LE Pri
!#0 N1894 P652 LD 14 -1 Int BE Pri
!#0 N1895 P651 LD 3 -1 Int LE Pri
!#0 N1896 P652 LD 14 -1 Int BE Pri
!#0 N1897 P653 BLD 24 -1 FP BE Pri
!#0 N1898 P653 BLD 25 -1 FP BE Pri
!#A N1897 N1898
!#0 N1899 P653 BLD 26 -1 FP BE Pri
!#0 N1900 P653 BLD 27 -1 FP BE Pri
!#0 N1901 P654 BLD 12 -1 FP BE Pri
!#0 N1902 P654 BLD 13 -1 FP BE Pri
!#A N1901 N1902
!#0 N1903 P654 BLD 14 -1 FP BE Pri
!#0 N1904 P654 BLD 15 -1 FP BE Pri
!#0 N1905 P655 DWLD 4 -1 Int BE Pri
!#0 N1906 P655 DWLD 5 -1 Int BE Pri
!#A N1905 N1906
!#0 N1907 P656 LD 25 -1 Int BE Pri
!#0 N1908 P657 BLD 20 -1 FP BE Pri
!#0 N1909 P657 BLD 21 -1 FP BE Pri
!#A N1908 N1909
!#0 N1910 P657 BLD 22 -1 FP BE Pri
!#0 N1911 P657 BLD 23 -1 FP BE Pri
!#0 N1912 P658 LD 0 -1 Int BE Pri
!#0 N1913 P659 MEMBAR
!#1 N1914 P660 BLD 0 -1 FP BE Pri
!#1 N1915 P660 BLD 1 -1 FP BE Pri
!#A N1914 N1915
!#1 N1916 P660 BLD 2 -1 FP BE Pri
!#1 N1917 P660 BLD 3 -1 FP BE Pri
!#1 N1918 P660 BLD 0 -1 FP BE Pri
!#1 N1919 P660 BLD 1 -1 FP BE Pri
!#A N1918 N1919
!#1 N1920 P660 BLD 2 -1 FP BE Pri
!#1 N1921 P660 BLD 3 -1 FP BE Pri
!#1 N1922 P661 LD 24 -1 Int BE Pri
!#1 N1923 P662 LD 20 -1 Int BE Pri
!#1 N1924 P663 BLD 16 -1 FP BE Pri
!#1 N1925 P663 BLD 17 -1 FP BE Pri
!#A N1924 N1925
!#1 N1926 P663 BLD 18 -1 FP BE Pri
!#1 N1927 P663 BLD 19 -1 FP BE Pri
!#1 N1928 P664 LD 18 -1 Int BE Pri
!#1 N1929 P665 LD 13 -1 Int BE Pri
!#1 N1931 P667 DWLD 3 -1 Int BE Pri
!#1 N1932 P668 LD 12 -1 Int BE Pri
!#1 N1933 P667 DWLD 3 -1 Int BE Pri
!#1 N1934 P668 LD 12 -1 Int BE Pri
!#1 N1935 P669 SWAP 17 0xffffffff 0x800001 Int BE Pri
!#1 N1936 P670 LD 9 -1 Int BE Pri
!#1 N1937 P671 DWLD 11 -1 Int BE Pri
!#1 N1938 P672 LD 2 -1 Int BE Pri
!#1 N1939 P673 DWLD 28 -1 Int LE Pri
!#1 N1940 P673 DWLD 29 -1 Int LE Pri
!#A N1939 N1940
!#1 N1941 P673 CASX 28 -1 N1939 0x800002 Int LE Pri
!#1 N1942 P673 CASX 29 -1 N1940 0x800003 Int LE Pri
!#A N1941 N1942
!#1 N1943 P673 DWLD 28 -1 Int LE Pri
!#1 N1944 P673 DWLD 29 -1 Int LE Pri
!#A N1943 N1944
!#1 N1945 P673 CASX 28 -1 N1943 0x800004 Int LE Pri
!#1 N1946 P673 CASX 29 -1 N1944 0x800005 Int LE Pri
!#A N1945 N1946
!#1 N1947 P674 BLD 0 -1 FP BE Pri
!#1 N1948 P674 BLD 1 -1 FP BE Pri
!#A N1947 N1948
!#1 N1949 P674 BLD 2 -1 FP BE Pri
!#1 N1950 P674 BLD 3 -1 FP BE Pri
!#1 N1952 P676 DWST 20 0x800006 Int BE Pri
!#1 N1953 P676 DWST 21 0x800007 Int BE Pri
!#A N1952 N1953
!#1 N1954 P677 BLD 16 -1 FP BE Pri
!#1 N1955 P677 BLD 17 -1 FP BE Pri
!#A N1954 N1955
!#1 N1956 P677 BLD 18 -1 FP BE Pri
!#1 N1957 P677 BLD 19 -1 FP BE Pri
!#1 N1958 P678 DWLD 3 -1 Int BE Pri
!#1 N1959 P679 LD 28 -1 Int BE Pri
!#1 N1960 P677 BLD 16 -1 FP BE Pri
!#1 N1961 P677 BLD 17 -1 FP BE Pri
!#A N1960 N1961
!#1 N1962 P677 BLD 18 -1 FP BE Pri
!#1 N1963 P677 BLD 19 -1 FP BE Pri
!#1 N1964 P678 DWLD 3 -1 Int BE Pri
!#1 N1965 P679 LD 28 -1 Int BE Pri
!#1 N1966 P680 LD 14 -1 Int BE Pri
!#1 N1967 P681 LD 23 -1 Int BE Pri
!#1 N1968 P682 BST 20 0x40000001 FP BE Pri
!#1 N1969 P682 BST 21 0x40000002 FP BE Pri
!#A N1968 N1969
!#1 N1970 P682 BST 22 0x40000003 FP BE Pri
!#1 N1971 P682 BST 23 0x40000004 FP BE Pri
!#1 N1972 P683 DWLD 22 -1 Int BE Pri
!#1 N1973 P684 LD 12 -1 Int BE Pri
!#1 N1974 P682 BST 20 0x40000005 FP BE Pri
!#1 N1975 P682 BST 21 0x40000006 FP BE Pri
!#A N1974 N1975
!#1 N1976 P682 BST 22 0x40000007 FP BE Pri
!#1 N1977 P682 BST 23 0x40000008 FP BE Pri
!#1 N1978 P683 DWLD 22 -1 Int BE Pri
!#1 N1979 P684 LD 12 -1 Int BE Pri
!#1 N1980 P685 LD 31 -1 Int BE Pri
!#1 N1981 P686 LD 30 -1 Int BE Pri
!#1 N1982 P687 LD 26 -1 FP BE Pri
!#1 N1983 P688 BLD 12 -1 FP BE Pri
!#1 N1984 P688 BLD 13 -1 FP BE Pri
!#A N1983 N1984
!#1 N1985 P688 BLD 14 -1 FP BE Pri
!#1 N1986 P688 BLD 15 -1 FP BE Pri
!#1 N1987 P689 LD 12 -1 Int BE Pri
!#1 N1988 P690 LD 2 -1 Int BE Pri
!#1 N1989 P688 BLD 12 -1 FP BE Pri
!#1 N1990 P688 BLD 13 -1 FP BE Pri
!#A N1989 N1990
!#1 N1991 P688 BLD 14 -1 FP BE Pri
!#1 N1992 P688 BLD 15 -1 FP BE Pri
!#1 N1993 P689 LD 12 -1 Int BE Pri
!#1 N1994 P690 LD 2 -1 Int BE Pri
!#1 N1995 P691 BLD 16 -1 FP BE Pri
!#1 N1996 P691 BLD 17 -1 FP BE Pri
!#A N1995 N1996
!#1 N1997 P691 BLD 18 -1 FP BE Pri
!#1 N1998 P691 BLD 19 -1 FP BE Pri
!#1 N1999 P692 LD 8 -1 Int BE Pri
!#1 N2000 P693 LD 2 -1 Int BE Pri
!#1 N2001 P692 LD 8 -1 Int BE Pri
!#1 N2002 P693 LD 2 -1 Int BE Pri
!#1 N2003 P694 BST 16 0x40000009 FP BE Pri
!#1 N2004 P694 BST 17 0x4000000a FP BE Pri
!#A N2003 N2004
!#1 N2005 P694 BST 18 0x4000000b FP BE Pri
!#1 N2006 P694 BST 19 0x4000000c FP BE Pri
!#1 N2007 P694 BST 16 0x4000000d FP BE Pri
!#1 N2008 P694 BST 17 0x4000000e FP BE Pri
!#A N2007 N2008
!#1 N2009 P694 BST 18 0x4000000f FP BE Pri
!#1 N2010 P694 BST 19 0x40000010 FP BE Pri
!#1 N2011 P695 DWST 16 0x800008 Int BE Pri
!#1 N2012 P695 DWST 17 0x800009 Int BE Pri
!#A N2011 N2012
!#1 N2013 P696 LD 2 -1 Int BE Pri
!#1 N2015 P698 LD 0 -1 Int BE Pri
!#1 N2016 P696 LD 2 -1 Int BE Pri
!#1 N2018 P698 LD 0 -1 Int BE Pri
!#1 N2019 P699 BLD 24 -1 FP BE Pri
!#1 N2020 P699 BLD 25 -1 FP BE Pri
!#A N2019 N2020
!#1 N2021 P699 BLD 26 -1 FP BE Pri
!#1 N2022 P699 BLD 27 -1 FP BE Pri
!#1 N2023 P700 DWLD 6 -1 Int BE Pri
!#1 N2024 P701 LD 24 -1 Int BE Pri
!#1 N2025 P702 DWLD 26 -1 Int BE Pri
!#1 N2026 P703 LD 20 -1 Int BE Pri
!#1 N2027 P702 DWLD 26 -1 Int BE Pri
!#1 N2028 P703 LD 20 -1 Int BE Pri
!#1 N2029 P704 BLD 12 -1 FP BE Pri
!#1 N2030 P704 BLD 13 -1 FP BE Pri
!#A N2029 N2030
!#1 N2031 P704 BLD 14 -1 FP BE Pri
!#1 N2032 P704 BLD 15 -1 FP BE Pri
!#1 N2033 P705 LD 29 -1 Int BE Pri
!#1 N2034 P706 LD 5 -1 Int BE Pri
!#1 N2035 P704 BLD 12 -1 FP BE Pri
!#1 N2036 P704 BLD 13 -1 FP BE Pri
!#A N2035 N2036
!#1 N2037 P704 BLD 14 -1 FP BE Pri
!#1 N2038 P704 BLD 15 -1 FP BE Pri
!#1 N2039 P705 LD 29 -1 Int BE Pri
!#1 N2040 P706 LD 5 -1 Int BE Pri
!#1 N2041 P707 LD 14 -1 Int LE Pri
!#1 N2042 P708 BLD 16 -1 FP BE Pri
!#1 N2043 P708 BLD 17 -1 FP BE Pri
!#A N2042 N2043
!#1 N2044 P708 BLD 18 -1 FP BE Pri
!#1 N2045 P708 BLD 19 -1 FP BE Pri
!#1 N2046 P709 LD 5 -1 Int BE Pri
!#1 N2047 P707 LD 14 -1 Int LE Pri
!#1 N2048 P708 BLD 16 -1 FP BE Pri
!#1 N2049 P708 BLD 17 -1 FP BE Pri
!#A N2048 N2049
!#1 N2050 P708 BLD 18 -1 FP BE Pri
!#1 N2051 P708 BLD 19 -1 FP BE Pri
!#1 N2052 P709 LD 5 -1 Int BE Pri
!#1 N2053 P710 DWLD 18 -1 Int BE Pri
!#1 N2054 P711 LD 23 -1 Int BE Pri
!#1 N2055 P710 DWLD 18 -1 Int BE Pri
!#1 N2056 P711 LD 23 -1 Int BE Pri
!#1 N2057 P712 BLD 24 -1 FP BE Pri
!#1 N2058 P712 BLD 25 -1 FP BE Pri
!#A N2057 N2058
!#1 N2059 P712 BLD 26 -1 FP BE Pri
!#1 N2060 P712 BLD 27 -1 FP BE Pri
!#1 N2061 P713 LD 18 -1 Int BE Pri
!#1 N2062 P714 LD 2 -1 Int BE Pri
!#1 N2063 P715 BLD 24 -1 FP BE Pri
!#1 N2064 P715 BLD 25 -1 FP BE Pri
!#A N2063 N2064
!#1 N2065 P715 BLD 26 -1 FP BE Pri
!#1 N2066 P715 BLD 27 -1 FP BE Pri
!#1 N2067 P716 LD 20 -1 Int BE Pri
!#1 N2068 P717 LD 10 -1 Int BE Pri
!#1 N2069 P715 BLD 24 -1 FP BE Pri
!#1 N2070 P715 BLD 25 -1 FP BE Pri
!#A N2069 N2070
!#1 N2071 P715 BLD 26 -1 FP BE Pri
!#1 N2072 P715 BLD 27 -1 FP BE Pri
!#1 N2073 P716 LD 20 -1 Int BE Pri
!#1 N2074 P717 LD 10 -1 Int BE Pri
!#1 N2075 P718 SWAP 22 0xffffffff 0x80000a Int BE Pri
!#1 N2076 P719 DWLD 4 -1 Int BE Pri
!#1 N2077 P719 DWLD 5 -1 Int BE Pri
!#A N2076 N2077
!#1 N2078 P720 LD 1 -1 Int BE Pri
!#1 N2079 P721 DWLD 4 -1 FP BE Pri
!#1 N2080 P721 DWLD 5 -1 FP BE Pri
!#A N2079 N2080
!#1 N2081 P722 LD 21 -1 Int BE Pri
!#1 N2082 P723 LD 2 -1 Int LE Pri
!#1 N2083 P722 LD 21 -1 Int BE Pri
!#1 N2084 P723 LD 2 -1 Int LE Pri
!#1 N2085 P724 DWLD 11 -1 FP BE Pri
!#1 N2086 P724 DWLD 11 -1 FP BE Pri
!#1 N2087 P725 DWLD 28 -1 FP BE Pri
!#1 N2088 P725 DWLD 29 -1 FP BE Pri
!#A N2087 N2088
!#1 N2089 P725 DWLD 28 -1 FP BE Pri
!#1 N2090 P725 DWLD 29 -1 FP BE Pri
!#A N2089 N2090
!#1 N2091 P726 LD 31 -1 Int BE Pri
!#1 N2092 P727 BLD 8 -1 FP BE Pri
!#1 N2093 P727 BLD 9 -1 FP BE Pri
!#A N2092 N2093
!#1 N2094 P727 BLD 10 -1 FP BE Pri
!#1 N2095 P727 BLD 11 -1 FP BE Pri
!#1 N2096 P728 LD 19 -1 Int BE Pri
!#1 N2097 P726 LD 31 -1 Int BE Pri
!#1 N2098 P727 BLD 8 -1 FP BE Pri
!#1 N2099 P727 BLD 9 -1 FP BE Pri
!#A N2098 N2099
!#1 N2100 P727 BLD 10 -1 FP BE Pri
!#1 N2101 P727 BLD 11 -1 FP BE Pri
!#1 N2102 P728 LD 19 -1 Int BE Pri
!#1 N2103 P729 LD 8 -1 Int BE Pri
!#1 N2104 P730 DWLD 27 -1 Int BE Pri
!#1 N2105 P731 DWLD 4 -1 Int BE Pri
!#1 N2106 P731 DWLD 5 -1 Int BE Pri
!#A N2105 N2106
!#1 N2107 P731 CASX 4 -1 N2105 0x80000b Int BE Pri
!#1 N2108 P731 CASX 5 -1 N2106 0x80000c Int BE Pri
!#A N2107 N2108
!#1 N2109 P732 ST 31 0x80000d Int BE Pri
!#1 N2110 P733 LD 25 -1 Int BE Pri
!#1 N2111 P733 CAS 25 -1 N2110 0x80000e Int BE Pri
!#1 N2112 P734 LD 3 -1 Int BE Pri
!#1 N2113 P735 LD 27 -1 Int BE Pri
!#1 N2114 P736 SWAP 18 0xffffffff 0x80000f Int BE Pri
!#1 N2115 P737 BLD 24 -1 FP BE Pri
!#1 N2116 P737 BLD 25 -1 FP BE Pri
!#A N2115 N2116
!#1 N2117 P737 BLD 26 -1 FP BE Pri
!#1 N2118 P737 BLD 27 -1 FP BE Pri
!#1 N2119 P738 LD 14 -1 Int BE Pri
!#1 N2120 P739 DWLD 4 -1 Int BE Pri
!#1 N2121 P739 DWLD 5 -1 Int BE Pri
!#A N2120 N2121
!#1 N2122 P740 BLD 4 -1 FP BE Pri
!#1 N2123 P740 BLD 5 -1 FP BE Pri
!#A N2122 N2123
!#1 N2124 P740 BLD 6 -1 FP BE Pri
!#1 N2125 P740 BLD 7 -1 FP BE Pri
!#1 N2126 P741 BLD 24 -1 FP BE Pri
!#1 N2127 P741 BLD 25 -1 FP BE Pri
!#A N2126 N2127
!#1 N2128 P741 BLD 26 -1 FP BE Pri
!#1 N2129 P741 BLD 27 -1 FP BE Pri
!#1 N2130 P742 DWST 6 0x800010 Int BE Pri
!#1 N2131 P743 LD 15 -1 Int BE Pri
!#1 N2132 P744 LD 15 -1 Int LE Pri
!#1 N2133 P742 DWST 6 0x800011 Int BE Pri
!#1 N2134 P743 LD 15 -1 Int BE Pri
!#1 N2135 P744 LD 15 -1 Int LE Pri
!#1 N2136 P745 LD 25 -1 Int BE Pri
!#1 N2137 P746 LD 2 -1 Int BE Pri
!#1 N2138 P747 DWLD 26 -1 Int BE Pri
!#1 N2139 P748 DWLD 18 -1 FP BE Pri
!#1 N2140 P749 LD 11 -1 Int BE Pri
!#1 N2141 P747 DWLD 26 -1 Int BE Pri
!#1 N2142 P748 DWLD 18 -1 FP BE Pri
!#1 N2143 P749 LD 11 -1 Int BE Pri
!#1 N2144 P750 LD 31 -1 Int BE Pri
!#1 N2145 P751 LD 4 -1 Int BE Pri
!#1 N2146 P750 LD 31 -1 Int BE Pri
!#1 N2147 P751 LD 4 -1 Int BE Pri
!#1 N2148 P752 DWLD 22 -1 FP BE Pri
!#1 N2149 P753 DWLD 15 -1 Int BE Pri
!#1 N2150 P754 LD 21 -1 Int BE Pri
!#1 N2151 P753 DWLD 15 -1 Int BE Pri
!#1 N2152 P754 LD 21 -1 Int BE Pri
!#1 N2153 P755 LD 29 -1 Int BE Pri
!#1 N2154 P756 LD 27 -1 Int BE Pri
!#1 N2155 P757 LD 26 -1 Int BE Pri
!#1 N2156 P758 LD 2 -1 Int BE Pri
!#1 N2157 P757 LD 26 -1 Int BE Pri
!#1 N2158 P758 LD 2 -1 Int BE Pri
!#1 N2159 P759 BLD 8 -1 FP BE Pri
!#1 N2160 P759 BLD 9 -1 FP BE Pri
!#A N2159 N2160
!#1 N2161 P759 BLD 10 -1 FP BE Pri
!#1 N2162 P759 BLD 11 -1 FP BE Pri
!#1 N2163 P760 MEMBAR
!#1 N2164 P761 DWLD 27 -1 Int BE Pri
!#1 N2165 P762 LD 1 -1 Int BE Pri
!#1 N2166 P763 LD 23 -1 Int BE Pri
!#1 N2167 P764 LD 15 -1 Int LE Pri
!#1 N2168 P763 LD 23 -1 Int BE Pri
!#1 N2169 P764 LD 15 -1 Int LE Pri
!#1 N2170 P765 LD 21 -1 Int BE Pri
!#1 N2171 P766 DWLD 6 -1 Int BE Pri
!#1 N2172 P765 LD 21 -1 Int BE Pri
!#1 N2173 P766 DWLD 6 -1 Int BE Pri
!#1 N2174 P767 BLD 28 -1 FP BE Pri
!#1 N2175 P767 BLD 29 -1 FP BE Pri
!#A N2174 N2175
!#1 N2176 P767 BLD 30 -1 FP BE Pri
!#1 N2177 P767 BLD 31 -1 FP BE Pri
!#1 N2178 P767 BLD 28 -1 FP BE Pri
!#1 N2179 P767 BLD 29 -1 FP BE Pri
!#A N2178 N2179
!#1 N2180 P767 BLD 30 -1 FP BE Pri
!#1 N2181 P767 BLD 31 -1 FP BE Pri
!#1 N2182 P768 LD 24 -1 Int BE Pri
!#1 N2183 P769 LD 29 -1 Int BE Pri
!#1 N2184 P768 LD 24 -1 Int BE Pri
!#1 N2185 P769 LD 29 -1 Int BE Pri
!#1 N2186 P770 LD 23 -1 FP BE Pri
!#1 N2187 P771 DWLD 4 -1 Int BE Pri
!#1 N2188 P771 DWLD 5 -1 Int BE Pri
!#A N2187 N2188
!#1 N2189 P772 BLD 8 -1 FP BE Pri
!#1 N2190 P772 BLD 9 -1 FP BE Pri
!#A N2189 N2190
!#1 N2191 P772 BLD 10 -1 FP BE Pri
!#1 N2192 P772 BLD 11 -1 FP BE Pri
!#1 N2193 P773 BLD 24 -1 FP BE Pri
!#1 N2194 P773 BLD 25 -1 FP BE Pri
!#A N2193 N2194
!#1 N2195 P773 BLD 26 -1 FP BE Pri
!#1 N2196 P773 BLD 27 -1 FP BE Pri
!#1 N2197 P772 BLD 8 -1 FP BE Pri
!#1 N2198 P772 BLD 9 -1 FP BE Pri
!#A N2197 N2198
!#1 N2199 P772 BLD 10 -1 FP BE Pri
!#1 N2200 P772 BLD 11 -1 FP BE Pri
!#1 N2201 P773 BLD 24 -1 FP BE Pri
!#1 N2202 P773 BLD 25 -1 FP BE Pri
!#A N2201 N2202
!#1 N2203 P773 BLD 26 -1 FP BE Pri
!#1 N2204 P773 BLD 27 -1 FP BE Pri
!#1 N2205 P774 DWLD 22 -1 Int BE Pri
!#1 N2206 P775 LD 7 -1 Int BE Pri
!#1 N2207 P776 BSTC 0 0x40000011 FP BE Pri
!#1 N2208 P776 BSTC 1 0x40000012 FP BE Pri
!#A N2207 N2208
!#1 N2209 P776 BSTC 2 0x40000013 FP BE Pri
!#1 N2210 P776 BSTC 3 0x40000014 FP BE Pri
!#1 N2211 P777 DWLD 30 -1 Int BE Pri
!#1 N2212 P778 LD 6 -1 Int BE Pri
!#1 N2213 P779 DWLD 6 -1 Int BE Pri
!#1 N2214 P780 LD 14 -1 Int BE Pri
!#1 N2215 P779 DWLD 6 -1 Int BE Pri
!#1 N2216 P780 LD 14 -1 Int BE Pri
!#1 N2217 P781 BLD 24 -1 FP BE Pri
!#1 N2218 P781 BLD 25 -1 FP BE Pri
!#A N2217 N2218
!#1 N2219 P781 BLD 26 -1 FP BE Pri
!#1 N2220 P781 BLD 27 -1 FP BE Pri
!#1 N2221 P782 LD 26 -1 Int BE Pri
!#1 N2223 P784 LD 4 -1 Int BE Pri
!#1 N2224 P785 DWLD 26 -1 Int BE Pri
!#1 N2225 P786 LD 12 -1 Int BE Pri
!#1 N2226 P786 CAS 12 -1 N2225 0x800012 Int BE Pri
!#1 N2227 P787 LD 30 -1 Int BE Pri
!#1 N2228 P788 DWLD 3 -1 FP BE Pri
!#1 N2229 P789 BLD 0 -1 FP BE Pri
!#1 N2230 P789 BLD 1 -1 FP BE Pri
!#A N2229 N2230
!#1 N2231 P789 BLD 2 -1 FP BE Pri
!#1 N2232 P789 BLD 3 -1 FP BE Pri
!#1 N2233 P788 DWLD 3 -1 FP BE Pri
!#1 N2234 P789 BLD 0 -1 FP BE Pri
!#1 N2235 P789 BLD 1 -1 FP BE Pri
!#A N2234 N2235
!#1 N2236 P789 BLD 2 -1 FP BE Pri
!#1 N2237 P789 BLD 3 -1 FP BE Pri
!#1 N2238 P790 LD 2 -1 Int BE Pri
!#1 N2239 P791 LD 23 -1 Int BE Pri
!#1 N2240 P790 LD 2 -1 Int BE Pri
!#1 N2241 P791 LD 23 -1 Int BE Pri
!#1 N2242 P792 BLD 4 -1 FP BE Pri
!#1 N2243 P792 BLD 5 -1 FP BE Pri
!#A N2242 N2243
!#1 N2244 P792 BLD 6 -1 FP BE Pri
!#1 N2245 P792 BLD 7 -1 FP BE Pri
!#1 N2246 P792 BLD 4 -1 FP BE Pri
!#1 N2247 P792 BLD 5 -1 FP BE Pri
!#A N2246 N2247
!#1 N2248 P792 BLD 6 -1 FP BE Pri
!#1 N2249 P792 BLD 7 -1 FP BE Pri
!#1 N2251 P794 BST 0 0x40000015 FP BE Pri
!#1 N2252 P794 BST 1 0x40000016 FP BE Pri
!#A N2251 N2252
!#1 N2253 P794 BST 2 0x40000017 FP BE Pri
!#1 N2254 P794 BST 3 0x40000018 FP BE Pri
!#1 N2256 P794 BST 0 0x40000019 FP BE Pri
!#1 N2257 P794 BST 1 0x4000001a FP BE Pri
!#A N2256 N2257
!#1 N2258 P794 BST 2 0x4000001b FP BE Pri
!#1 N2259 P794 BST 3 0x4000001c FP BE Pri
!#1 N2260 P795 DWLD 2 -1 Int BE Pri
!#1 N2261 P796 BLD 0 -1 FP BE Pri
!#1 N2262 P796 BLD 1 -1 FP BE Pri
!#A N2261 N2262
!#1 N2263 P796 BLD 2 -1 FP BE Pri
!#1 N2264 P796 BLD 3 -1 FP BE Pri
!#1 N2265 P797 LD 17 -1 Int BE Pri
!#1 N2266 P795 DWLD 2 -1 Int BE Pri
!#1 N2267 P796 BLD 0 -1 FP BE Pri
!#1 N2268 P796 BLD 1 -1 FP BE Pri
!#A N2267 N2268
!#1 N2269 P796 BLD 2 -1 FP BE Pri
!#1 N2270 P796 BLD 3 -1 FP BE Pri
!#1 N2271 P797 LD 17 -1 Int BE Pri
!#1 N2272 P798 BLD 16 -1 FP BE Pri
!#1 N2273 P798 BLD 17 -1 FP BE Pri
!#A N2272 N2273
!#1 N2274 P798 BLD 18 -1 FP BE Pri
!#1 N2275 P798 BLD 19 -1 FP BE Pri
!#1 N2276 P799 LD 16 -1 Int BE Pri
!#1 N2277 P800 LD 17 -1 Int BE Pri
!#1 N2278 P798 BLD 16 -1 FP BE Pri
!#1 N2279 P798 BLD 17 -1 FP BE Pri
!#A N2278 N2279
!#1 N2280 P798 BLD 18 -1 FP BE Pri
!#1 N2281 P798 BLD 19 -1 FP BE Pri
!#1 N2282 P799 LD 16 -1 Int BE Pri
!#1 N2283 P800 LD 17 -1 Int BE Pri
!#1 N2284 P801 BLD 8 -1 FP BE Pri
!#1 N2285 P801 BLD 9 -1 FP BE Pri
!#A N2284 N2285
!#1 N2286 P801 BLD 10 -1 FP BE Pri
!#1 N2287 P801 BLD 11 -1 FP BE Pri
!#1 N2288 P802 BLD 16 -1 FP BE Pri
!#1 N2289 P802 BLD 17 -1 FP BE Pri
!#A N2288 N2289
!#1 N2290 P802 BLD 18 -1 FP BE Pri
!#1 N2291 P802 BLD 19 -1 FP BE Pri
!#1 N2292 P801 BLD 8 -1 FP BE Pri
!#1 N2293 P801 BLD 9 -1 FP BE Pri
!#A N2292 N2293
!#1 N2294 P801 BLD 10 -1 FP BE Pri
!#1 N2295 P801 BLD 11 -1 FP BE Pri
!#1 N2296 P802 BLD 16 -1 FP BE Pri
!#1 N2297 P802 BLD 17 -1 FP BE Pri
!#A N2296 N2297
!#1 N2298 P802 BLD 18 -1 FP BE Pri
!#1 N2299 P802 BLD 19 -1 FP BE Pri
!#1 N2300 P803 BLD 12 -1 FP BE Pri
!#1 N2301 P803 BLD 13 -1 FP BE Pri
!#A N2300 N2301
!#1 N2302 P803 BLD 14 -1 FP BE Pri
!#1 N2303 P803 BLD 15 -1 FP BE Pri
!#1 N2304 P804 BLD 4 -1 FP BE Pri
!#1 N2305 P804 BLD 5 -1 FP BE Pri
!#A N2304 N2305
!#1 N2306 P804 BLD 6 -1 FP BE Pri
!#1 N2307 P804 BLD 7 -1 FP BE Pri
!#1 N2308 P804 BLD 4 -1 FP BE Pri
!#1 N2309 P804 BLD 5 -1 FP BE Pri
!#A N2308 N2309
!#1 N2310 P804 BLD 6 -1 FP BE Pri
!#1 N2311 P804 BLD 7 -1 FP BE Pri
!#1 N2312 P805 DWLD 4 -1 Int BE Pri
!#1 N2313 P805 DWLD 5 -1 Int BE Pri
!#A N2312 N2313
!#1 N2314 P806 DWLD 16 -1 Int BE Pri
!#1 N2315 P806 DWLD 17 -1 Int BE Pri
!#A N2314 N2315
!#1 N2316 P805 DWLD 4 -1 Int BE Pri
!#1 N2317 P805 DWLD 5 -1 Int BE Pri
!#A N2316 N2317
!#1 N2318 P806 DWLD 16 -1 Int BE Pri
!#1 N2319 P806 DWLD 17 -1 Int BE Pri
!#A N2318 N2319
!#1 N2320 P807 BLD 12 -1 FP BE Pri
!#1 N2321 P807 BLD 13 -1 FP BE Pri
!#A N2320 N2321
!#1 N2322 P807 BLD 14 -1 FP BE Pri
!#1 N2323 P807 BLD 15 -1 FP BE Pri
!#1 N2326 P809 DWLD 18 -1 Int BE Pri
!#1 N2327 P810 DWST 10 0x800013 Int BE Pri
!#1 N2328 P811 LD 9 -1 Int BE Pri
!#1 N2329 P812 BLD 4 -1 FP BE Pri
!#1 N2330 P812 BLD 5 -1 FP BE Pri
!#A N2329 N2330
!#1 N2331 P812 BLD 6 -1 FP BE Pri
!#1 N2332 P812 BLD 7 -1 FP BE Pri
!#1 N2333 P813 DWLD 28 -1 Int LE Pri
!#1 N2334 P813 DWLD 29 -1 Int LE Pri
!#A N2333 N2334
!#1 N2335 P813 CASX 28 -1 N2333 0x800014 Int LE Pri
!#1 N2336 P813 CASX 29 -1 N2334 0x800015 Int LE Pri
!#A N2335 N2336
!#1 N2337 P814 BLD 16 -1 FP BE Pri
!#1 N2338 P814 BLD 17 -1 FP BE Pri
!#A N2337 N2338
!#1 N2339 P814 BLD 18 -1 FP BE Pri
!#1 N2340 P814 BLD 19 -1 FP BE Pri
!#1 N2341 P815 BLD 16 -1 FP BE Pri
!#1 N2342 P815 BLD 17 -1 FP BE Pri
!#A N2341 N2342
!#1 N2343 P815 BLD 18 -1 FP BE Pri
!#1 N2344 P815 BLD 19 -1 FP BE Pri
!#1 N2345 P816 BLD 0 -1 FP BE Pri
!#1 N2346 P816 BLD 1 -1 FP BE Pri
!#A N2345 N2346
!#1 N2347 P816 BLD 2 -1 FP BE Pri
!#1 N2348 P816 BLD 3 -1 FP BE Pri
!#1 N2349 P817 BSTC 12 0x4000001d FP BE Pri
!#1 N2350 P817 BSTC 13 0x4000001e FP BE Pri
!#A N2349 N2350
!#1 N2351 P817 BSTC 14 0x4000001f FP BE Pri
!#1 N2352 P817 BSTC 15 0x40000020 FP BE Pri
!#1 N2353 P818 DWLD 12 -1 Int BE Pri
!#1 N2354 P818 DWLD 13 -1 Int BE Pri
!#A N2353 N2354
!#1 N2355 P818 DWLD 12 -1 Int BE Pri
!#1 N2356 P818 DWLD 13 -1 Int BE Pri
!#A N2355 N2356
!#1 N2357 P819 BLD 20 -1 FP BE Pri
!#1 N2358 P819 BLD 21 -1 FP BE Pri
!#A N2357 N2358
!#1 N2359 P819 BLD 22 -1 FP BE Pri
!#1 N2360 P819 BLD 23 -1 FP BE Pri
!#1 N2361 P820 BLD 28 -1 FP BE Pri
!#1 N2362 P820 BLD 29 -1 FP BE Pri
!#A N2361 N2362
!#1 N2363 P820 BLD 30 -1 FP BE Pri
!#1 N2364 P820 BLD 31 -1 FP BE Pri
!#1 N2365 P819 BLD 20 -1 FP BE Pri
!#1 N2366 P819 BLD 21 -1 FP BE Pri
!#A N2365 N2366
!#1 N2367 P819 BLD 22 -1 FP BE Pri
!#1 N2368 P819 BLD 23 -1 FP BE Pri
!#1 N2369 P820 BLD 28 -1 FP BE Pri
!#1 N2370 P820 BLD 29 -1 FP BE Pri
!#A N2369 N2370
!#1 N2371 P820 BLD 30 -1 FP BE Pri
!#1 N2372 P820 BLD 31 -1 FP BE Pri
!#1 N2373 P821 LD 21 -1 Int BE Pri
!#1 N2374 P822 DWLD 12 -1 Int BE Pri
!#1 N2375 P822 DWLD 13 -1 Int BE Pri
!#A N2374 N2375
!#1 N2376 P822 CASX 12 -1 N2374 0x800016 Int BE Pri
!#1 N2377 P822 CASX 13 -1 N2375 0x800017 Int BE Pri
!#A N2376 N2377
!#1 N2378 P823 LD 8 -1 Int BE Pri
!#1 N2379 P824 LD 17 -1 Int BE Pri
!#1 N2380 P825 SWAP 28 0xffffffff 0x800018 Int BE Pri
!#1 N2381 P826 DWLD 6 -1 Int BE Pri
!#1 N2382 P827 DWLD 12 -1 FP BE Pri
!#1 N2383 P827 DWLD 13 -1 FP BE Pri
!#A N2382 N2383
!#1 N2384 P828 LD 3 -1 Int BE Pri
!#1 N2385 P826 DWLD 6 -1 Int BE Pri
!#1 N2386 P827 DWLD 12 -1 FP BE Pri
!#1 N2387 P827 DWLD 13 -1 FP BE Pri
!#A N2386 N2387
!#1 N2388 P828 LD 3 -1 Int BE Pri
!#1 N2389 P829 DWLD 2 -1 FP BE Pri
!#1 N2391 P831 DWLD 15 -1 Int BE Pri
!#1 N2392 P832 LD 8 -1 Int BE Pri
!#1 N2393 P831 DWLD 15 -1 Int BE Pri
!#1 N2394 P832 LD 8 -1 Int BE Pri
!#1 N2395 P833 DWLD 16 -1 Int BE Pri
!#1 N2396 P833 DWLD 17 -1 Int BE Pri
!#A N2395 N2396
!#1 N2397 P834 LD 24 -1 Int BE Pri
!#1 N2398 P835 LD 17 -1 Int BE Pri
!#1 N2399 P833 DWLD 16 -1 Int BE Pri
!#1 N2400 P833 DWLD 17 -1 Int BE Pri
!#A N2399 N2400
!#1 N2401 P834 LD 24 -1 Int BE Pri
!#1 N2402 P835 LD 17 -1 Int BE Pri
!#1 N2403 P836 BLD 12 -1 FP BE Pri
!#1 N2404 P836 BLD 13 -1 FP BE Pri
!#A N2403 N2404
!#1 N2405 P836 BLD 14 -1 FP BE Pri
!#1 N2406 P836 BLD 15 -1 FP BE Pri
!#1 N2407 P837 LD 21 -1 Int BE Pri
!#1 N2408 P838 LD 14 -1 Int BE Pri
!#1 N2409 P836 BLD 12 -1 FP BE Pri
!#1 N2410 P836 BLD 13 -1 FP BE Pri
!#A N2409 N2410
!#1 N2411 P836 BLD 14 -1 FP BE Pri
!#1 N2412 P836 BLD 15 -1 FP BE Pri
!#1 N2413 P837 LD 21 -1 Int BE Pri
!#1 N2414 P838 LD 14 -1 Int BE Pri
!#1 N2415 P839 BLD 20 -1 FP BE Pri
!#1 N2416 P839 BLD 21 -1 FP BE Pri
!#A N2415 N2416
!#1 N2417 P839 BLD 22 -1 FP BE Pri
!#1 N2418 P839 BLD 23 -1 FP BE Pri
!#1 N2419 P840 BST 20 0x40000021 FP BE Pri
!#1 N2420 P840 BST 21 0x40000022 FP BE Pri
!#A N2419 N2420
!#1 N2421 P840 BST 22 0x40000023 FP BE Pri
!#1 N2422 P840 BST 23 0x40000024 FP BE Pri
!#1 N2423 P840 BST 20 0x40000025 FP BE Pri
!#1 N2424 P840 BST 21 0x40000026 FP BE Pri
!#A N2423 N2424
!#1 N2425 P840 BST 22 0x40000027 FP BE Pri
!#1 N2426 P840 BST 23 0x40000028 FP BE Pri
!#1 N2427 P841 LD 6 -1 Int BE Pri
!#1 N2428 P842 LD 4 -1 Int BE Pri
!#1 N2429 P841 LD 6 -1 Int BE Pri
!#1 N2430 P842 LD 4 -1 Int BE Pri
!#1 N2432 P844 BLD 28 -1 FP BE Pri
!#1 N2433 P844 BLD 29 -1 FP BE Pri
!#A N2432 N2433
!#1 N2434 P844 BLD 30 -1 FP BE Pri
!#1 N2435 P844 BLD 31 -1 FP BE Pri
!#1 N2437 P844 BLD 28 -1 FP BE Pri
!#1 N2438 P844 BLD 29 -1 FP BE Pri
!#A N2437 N2438
!#1 N2439 P844 BLD 30 -1 FP BE Pri
!#1 N2440 P844 BLD 31 -1 FP BE Pri
!#1 N2441 P845 DWLD 16 -1 Int BE Pri
!#1 N2442 P845 DWLD 17 -1 Int BE Pri
!#A N2441 N2442
!#1 N2443 P845 DWLD 16 -1 Int BE Pri
!#1 N2444 P845 DWLD 17 -1 Int BE Pri
!#A N2443 N2444
!#1 N2445 P846 DWLD 6 -1 FP BE Pri
!#1 N2446 P846 DWLD 6 -1 FP BE Pri
!#1 N2447 P847 BLD 12 -1 FP BE Pri
!#1 N2448 P847 BLD 13 -1 FP BE Pri
!#A N2447 N2448
!#1 N2449 P847 BLD 14 -1 FP BE Pri
!#1 N2450 P847 BLD 15 -1 FP BE Pri
!#1 N2451 P848 LD 3 -1 FP BE Pri
!#1 N2452 P849 DWLD 31 -1 Int BE Pri
!#1 N2453 P850 LD 1 -1 Int BE Pri
!#1 N2454 P848 LD 3 -1 FP BE Pri
!#1 N2455 P849 DWLD 31 -1 Int BE Pri
!#1 N2456 P850 LD 1 -1 Int BE Pri
!#1 N2457 P851 LD 25 -1 Int BE Pri
!#1 N2458 P852 LD 25 -1 Int BE Pri
!#1 N2459 P851 LD 25 -1 Int BE Pri
!#1 N2460 P852 LD 25 -1 Int BE Pri
!#1 N2461 P853 DWLD 4 -1 Int BE Pri
!#1 N2462 P853 DWLD 5 -1 Int BE Pri
!#A N2461 N2462
!#1 N2463 P854 DWLD 28 -1 Int BE Pri
!#1 N2464 P854 DWLD 29 -1 Int BE Pri
!#A N2463 N2464
!#1 N2465 P853 DWLD 4 -1 Int BE Pri
!#1 N2466 P853 DWLD 5 -1 Int BE Pri
!#A N2465 N2466
!#1 N2467 P854 DWLD 28 -1 Int BE Pri
!#1 N2468 P854 DWLD 29 -1 Int BE Pri
!#A N2467 N2468
!#1 N2473 P857 LD 21 -1 Int BE Pri
!#1 N2474 P858 LD 19 -1 Int BE Pri
!#1 N2475 P857 LD 21 -1 Int BE Pri
!#1 N2476 P858 LD 19 -1 Int BE Pri
!#1 N2477 P859 DWLD 3 -1,0x0 Int BE Pri
!#1 N2478 P859 CASX 3 -1,0x0 N2477 0x800019 Int BE Pri
!#1 N2479 P859 DWLD 3 -1,0x0 Int BE Pri
!#1 N2480 P859 CASX 3 -1,0x0 N2479 0x80001a Int BE Pri
!#1 N2481 P860 BLD 20 -1 FP BE Pri
!#1 N2482 P860 BLD 21 -1 FP BE Pri
!#A N2481 N2482
!#1 N2483 P860 BLD 22 -1 FP BE Pri
!#1 N2484 P860 BLD 23 -1 FP BE Pri
!#1 N2485 P860 BLD 20 -1 FP BE Pri
!#1 N2486 P860 BLD 21 -1 FP BE Pri
!#A N2485 N2486
!#1 N2487 P860 BLD 22 -1 FP BE Pri
!#1 N2488 P860 BLD 23 -1 FP BE Pri
!#1 N2489 P861 DWLD 6 -1 Int BE Pri
!#1 N2490 P862 LD 4 -1 Int BE Pri
!#1 N2491 P863 LD 0 -1 Int BE Pri
!#1 N2492 P864 LD 5 -1 Int BE Pri
!#1 N2493 P863 LD 0 -1 Int BE Pri
!#1 N2494 P864 LD 5 -1 Int BE Pri
!#1 N2495 P865 BLD 28 -1 FP BE Pri
!#1 N2496 P865 BLD 29 -1 FP BE Pri
!#A N2495 N2496
!#1 N2497 P865 BLD 30 -1 FP BE Pri
!#1 N2498 P865 BLD 31 -1 FP BE Pri
!#1 N2499 P865 BLD 28 -1 FP BE Pri
!#1 N2500 P865 BLD 29 -1 FP BE Pri
!#A N2499 N2500
!#1 N2501 P865 BLD 30 -1 FP BE Pri
!#1 N2502 P865 BLD 31 -1 FP BE Pri
!#1 N2503 P866 DWLD 3 -1 Int BE Pri
!#1 N2504 P867 LD 24 -1 Int LE Pri
!#1 N2505 P866 DWLD 3 -1 Int BE Pri
!#1 N2506 P867 LD 24 -1 Int LE Pri
!#1 N2507 P868 DWLD 14 -1 Int BE Pri
!#1 N2508 P869 BLD 8 -1 FP BE Pri
!#1 N2509 P869 BLD 9 -1 FP BE Pri
!#A N2508 N2509
!#1 N2510 P869 BLD 10 -1 FP BE Pri
!#1 N2511 P869 BLD 11 -1 FP BE Pri
!#1 N2512 P870 LD 23 -1 Int BE Pri
!#1 N2513 P871 LD 0 -1 Int BE Pri
!#1 N2514 P872 BLD 0 -1 FP BE Pri
!#1 N2515 P872 BLD 1 -1 FP BE Pri
!#A N2514 N2515
!#1 N2516 P872 BLD 2 -1 FP BE Pri
!#1 N2517 P872 BLD 3 -1 FP BE Pri
!#1 N2518 P873 LD 7 -1 Int BE Pri
!#1 N2519 P874 LD 0 -1 Int BE Pri
!#1 N2520 P875 LD 16 -1 Int BE Pri
!#1 N2521 P874 LD 0 -1 Int BE Pri
!#1 N2522 P875 LD 16 -1 Int BE Pri
!#1 N2523 P876 BLD 24 -1 FP BE Pri
!#1 N2524 P876 BLD 25 -1 FP BE Pri
!#A N2523 N2524
!#1 N2525 P876 BLD 26 -1 FP BE Pri
!#1 N2526 P876 BLD 27 -1 FP BE Pri
!#1 N2527 P876 BLD 24 -1 FP BE Pri
!#1 N2528 P876 BLD 25 -1 FP BE Pri
!#A N2527 N2528
!#1 N2529 P876 BLD 26 -1 FP BE Pri
!#1 N2530 P876 BLD 27 -1 FP BE Pri
!#1 N2531 P877 BLD 8 -1 FP BE Pri
!#1 N2532 P877 BLD 9 -1 FP BE Pri
!#A N2531 N2532
!#1 N2533 P877 BLD 10 -1 FP BE Pri
!#1 N2534 P877 BLD 11 -1 FP BE Pri
!#1 N2535 P877 BLD 8 -1 FP BE Pri
!#1 N2536 P877 BLD 9 -1 FP BE Pri
!#A N2535 N2536
!#1 N2537 P877 BLD 10 -1 FP BE Pri
!#1 N2538 P877 BLD 11 -1 FP BE Pri
!#1 N2539 P878 BLD 24 -1 FP BE Pri
!#1 N2540 P878 BLD 25 -1 FP BE Pri
!#A N2539 N2540
!#1 N2541 P878 BLD 26 -1 FP BE Pri
!#1 N2542 P878 BLD 27 -1 FP BE Pri
!#1 N2543 P879 LD 12 -1 Int BE Pri
!#1 N2544 P880 LD 16 -1 Int BE Pri
!#1 N2545 P878 BLD 24 -1 FP BE Pri
!#1 N2546 P878 BLD 25 -1 FP BE Pri
!#A N2545 N2546
!#1 N2547 P878 BLD 26 -1 FP BE Pri
!#1 N2548 P878 BLD 27 -1 FP BE Pri
!#1 N2549 P879 LD 12 -1 Int BE Pri
!#1 N2550 P880 LD 16 -1 Int BE Pri
!#1 N2551 P881 LD 16 -1 Int LE Pri
!#1 N2552 P882 BLD 12 -1 FP BE Pri
!#1 N2553 P882 BLD 13 -1 FP BE Pri
!#A N2552 N2553
!#1 N2554 P882 BLD 14 -1 FP BE Pri
!#1 N2555 P882 BLD 15 -1 FP BE Pri
!#1 N2556 P883 LD 23 -1 Int BE Pri
!#1 N2557 P881 LD 16 -1 Int LE Pri
!#1 N2558 P882 BLD 12 -1 FP BE Pri
!#1 N2559 P882 BLD 13 -1 FP BE Pri
!#A N2558 N2559
!#1 N2560 P882 BLD 14 -1 FP BE Pri
!#1 N2561 P882 BLD 15 -1 FP BE Pri
!#1 N2562 P883 LD 23 -1 Int BE Pri
!#1 N2563 P884 DWLD 16 -1 Int BE Pri
!#1 N2564 P884 DWLD 17 -1 Int BE Pri
!#A N2563 N2564
!#1 N2565 P885 BLD 28 -1 FP BE Pri
!#1 N2566 P885 BLD 29 -1 FP BE Pri
!#A N2565 N2566
!#1 N2567 P885 BLD 30 -1 FP BE Pri
!#1 N2568 P885 BLD 31 -1 FP BE Pri
!#1 N2569 P886 LD 20 -1 Int BE Pri
!#1 N2570 P886 CAS 20 -1 N2569 0x80001b Int BE Pri
!#1 N2571 P887 BLD 0 -1 FP BE Pri
!#1 N2572 P887 BLD 1 -1 FP BE Pri
!#A N2571 N2572
!#1 N2573 P887 BLD 2 -1 FP BE Pri
!#1 N2574 P887 BLD 3 -1 FP BE Pri
!#1 N2575 P887 BLD 0 -1 FP BE Pri
!#1 N2576 P887 BLD 1 -1 FP BE Pri
!#A N2575 N2576
!#1 N2577 P887 BLD 2 -1 FP BE Pri
!#1 N2578 P887 BLD 3 -1 FP BE Pri
!#1 N2579 P888 BLD 4 -1 FP BE Pri
!#1 N2580 P888 BLD 5 -1 FP BE Pri
!#A N2579 N2580
!#1 N2581 P888 BLD 6 -1 FP BE Pri
!#1 N2582 P888 BLD 7 -1 FP BE Pri
!#1 N2583 P888 BLD 4 -1 FP BE Pri
!#1 N2584 P888 BLD 5 -1 FP BE Pri
!#A N2583 N2584
!#1 N2585 P888 BLD 6 -1 FP BE Pri
!#1 N2586 P888 BLD 7 -1 FP BE Pri
!#1 N2587 P889 BLD 24 -1 FP BE Pri
!#1 N2588 P889 BLD 25 -1 FP BE Pri
!#A N2587 N2588
!#1 N2589 P889 BLD 26 -1 FP BE Pri
!#1 N2590 P889 BLD 27 -1 FP BE Pri
!#1 N2591 P889 BLD 24 -1 FP BE Pri
!#1 N2592 P889 BLD 25 -1 FP BE Pri
!#A N2591 N2592
!#1 N2593 P889 BLD 26 -1 FP BE Pri
!#1 N2594 P889 BLD 27 -1 FP BE Pri
!#1 N2596 P891 DWLD 31 -1 Int BE Pri
!#1 N2597 P892 LD 1 -1 Int BE Pri
!#1 N2598 P893 LD 28 -1 Int BE Pri
!#1 N2599 P894 BLD 0 -1 FP BE Pri
!#1 N2600 P894 BLD 1 -1 FP BE Pri
!#A N2599 N2600
!#1 N2601 P894 BLD 2 -1 FP BE Pri
!#1 N2602 P894 BLD 3 -1 FP BE Pri
!#1 N2603 P895 LD 29 -1 Int BE Pri
!#1 N2604 P893 LD 28 -1 Int BE Pri
!#1 N2605 P894 BLD 0 -1 FP BE Pri
!#1 N2606 P894 BLD 1 -1 FP BE Pri
!#A N2605 N2606
!#1 N2607 P894 BLD 2 -1 FP BE Pri
!#1 N2608 P894 BLD 3 -1 FP BE Pri
!#1 N2609 P895 LD 29 -1 Int BE Pri
!#1 N2610 P896 LD 2 -1 Int BE Pri
!#1 N2611 P897 LD 1 -1 Int BE Pri
!#1 N2612 P896 LD 2 -1 Int BE Pri
!#1 N2613 P897 LD 1 -1 Int BE Pri
!#1 N2614 P898 DWLD 12 -1 Int BE Pri
!#1 N2615 P898 DWLD 13 -1 Int BE Pri
!#A N2614 N2615
!#1 N2616 P899 BLD 20 -1 FP BE Pri
!#1 N2617 P899 BLD 21 -1 FP BE Pri
!#A N2616 N2617
!#1 N2618 P899 BLD 22 -1 FP BE Pri
!#1 N2619 P899 BLD 23 -1 FP BE Pri
!#1 N2620 P898 DWLD 12 -1 Int BE Pri
!#1 N2621 P898 DWLD 13 -1 Int BE Pri
!#A N2620 N2621
!#1 N2622 P899 BLD 20 -1 FP BE Pri
!#1 N2623 P899 BLD 21 -1 FP BE Pri
!#A N2622 N2623
!#1 N2624 P899 BLD 22 -1 FP BE Pri
!#1 N2625 P899 BLD 23 -1 FP BE Pri
!#1 N2626 P900 BLD 8 -1 FP BE Pri
!#1 N2627 P900 BLD 9 -1 FP BE Pri
!#A N2626 N2627
!#1 N2628 P900 BLD 10 -1 FP BE Pri
!#1 N2629 P900 BLD 11 -1 FP BE Pri
!#1 N2630 P900 BLD 8 -1 FP BE Pri
!#1 N2631 P900 BLD 9 -1 FP BE Pri
!#A N2630 N2631
!#1 N2632 P900 BLD 10 -1 FP BE Pri
!#1 N2633 P900 BLD 11 -1 FP BE Pri
!#1 N2634 P901 DWLD 2 -1 FP BE Pri
!#1 N2635 P902 DWST 19 0x80001c Int BE Pri
!#1 N2636 P903 LD 16 -1 FP BE Pri
!#1 N2637 P904 LD 30 -1 FP BE Pri
!#1 N2638 P905 LD 30 -1 FP BE Pri
!#1 N2639 P906 DWLD 0 -1 Int BE Pri
!#1 N2640 P906 DWLD 1 -1 Int BE Pri
!#A N2639 N2640
!#1 N2641 P906 DWLD 0 -1 Int BE Pri
!#1 N2642 P906 DWLD 1 -1 Int BE Pri
!#A N2641 N2642
!#1 N2643 P907 DWLD 2 -1 Int BE Pri
!#1 N2644 P908 LD 19 -1 Int BE Pri
!#1 N2645 P907 DWLD 2 -1 Int BE Pri
!#1 N2646 P908 LD 19 -1 Int BE Pri
!#1 N2647 P909 BLD 28 -1 FP BE Pri
!#1 N2648 P909 BLD 29 -1 FP BE Pri
!#A N2647 N2648
!#1 N2649 P909 BLD 30 -1 FP BE Pri
!#1 N2650 P909 BLD 31 -1 FP BE Pri
!#1 N2651 P910 BLD 12 -1 FP BE Pri
!#1 N2652 P910 BLD 13 -1 FP BE Pri
!#A N2651 N2652
!#1 N2653 P910 BLD 14 -1 FP BE Pri
!#1 N2654 P910 BLD 15 -1 FP BE Pri
!#1 N2655 P911 LD 22 -1 Int BE Pri
!#1 N2656 P912 LD 0 -1 Int BE Pri
!#1 N2657 P913 BLD 4 -1 FP BE Pri
!#1 N2658 P913 BLD 5 -1 FP BE Pri
!#A N2657 N2658
!#1 N2659 P913 BLD 6 -1 FP BE Pri
!#1 N2660 P913 BLD 7 -1 FP BE Pri
!#1 N2661 P913 BLD 4 -1 FP BE Pri
!#1 N2662 P913 BLD 5 -1 FP BE Pri
!#A N2661 N2662
!#1 N2663 P913 BLD 6 -1 FP BE Pri
!#1 N2664 P913 BLD 7 -1 FP BE Pri
!#1 N2665 P914 BLD 20 -1 FP BE Pri
!#1 N2666 P914 BLD 21 -1 FP BE Pri
!#A N2665 N2666
!#1 N2667 P914 BLD 22 -1 FP BE Pri
!#1 N2668 P914 BLD 23 -1 FP BE Pri
!#1 N2669 P915 DWST 12 0x80001d Int BE Pri
!#1 N2670 P915 DWST 13 0x80001e Int BE Pri
!#A N2669 N2670
!#1 N2671 P916 LD 25 -1 Int BE Pri
!#1 N2672 P917 BLD 4 -1 FP BE Pri
!#1 N2673 P917 BLD 5 -1 FP BE Pri
!#A N2672 N2673
!#1 N2674 P917 BLD 6 -1 FP BE Pri
!#1 N2675 P917 BLD 7 -1 FP BE Pri
!#1 N2676 P918 LD 20 -1 Int BE Pri
!#1 N2677 P916 LD 25 -1 Int BE Pri
!#1 N2678 P917 BLD 4 -1 FP BE Pri
!#1 N2679 P917 BLD 5 -1 FP BE Pri
!#A N2678 N2679
!#1 N2680 P917 BLD 6 -1 FP BE Pri
!#1 N2681 P917 BLD 7 -1 FP BE Pri
!#1 N2682 P918 LD 20 -1 Int BE Pri
!#1 N2683 P919 LD 13 -1 Int BE Pri
!#1 N2684 P920 LD 29 -1 Int BE Pri
!#1 N2685 P921 DWLD 7 -1 Int BE Pri
!#1 N2686 P922 LD 23 -1 Int BE Pri
!#1 N2687 P923 BLD 20 -1 FP BE Pri
!#1 N2688 P923 BLD 21 -1 FP BE Pri
!#A N2687 N2688
!#1 N2689 P923 BLD 22 -1 FP BE Pri
!#1 N2690 P923 BLD 23 -1 FP BE Pri
!#1 N2691 P924 DWLD 18 -1 Int BE Pri
!#1 N2692 P925 LD 2 -1 Int BE Pri
!#1 N2693 P923 BLD 20 -1 FP BE Pri
!#1 N2694 P923 BLD 21 -1 FP BE Pri
!#A N2693 N2694
!#1 N2695 P923 BLD 22 -1 FP BE Pri
!#1 N2696 P923 BLD 23 -1 FP BE Pri
!#1 N2697 P924 DWLD 18 -1 Int BE Pri
!#1 N2698 P925 LD 2 -1 Int BE Pri
!#1 N2700 P927 BLD 8 -1 FP BE Pri
!#1 N2701 P927 BLD 9 -1 FP BE Pri
!#A N2700 N2701
!#1 N2702 P927 BLD 10 -1 FP BE Pri
!#1 N2703 P927 BLD 11 -1 FP BE Pri
!#1 N2704 P928 DWLD 20 -1 Int LE Pri
!#1 N2705 P928 DWLD 21 -1 Int LE Pri
!#A N2704 N2705
!#1 N2706 P929 LD 14 -1 Int BE Pri
!#1 N2707 P930 BLD 4 -1 FP BE Pri
!#1 N2708 P930 BLD 5 -1 FP BE Pri
!#A N2707 N2708
!#1 N2709 P930 BLD 6 -1 FP BE Pri
!#1 N2710 P930 BLD 7 -1 FP BE Pri
!#1 N2711 P931 LD 11 -1 Int BE Pri
!#1 N2712 P932 LD 27 -1 Int BE Pri
!#1 N2713 P933 LD 16 -1 Int BE Pri
!#1 N2714 P934 LD 19 -1 Int BE Pri
!#1 N2715 P935 DWLD 2 -1 Int BE Pri
!#1 N2716 P936 LD 30 -1 Int LE Pri
!#1 N2717 P937 LD 28 -1 Int BE Pri
!#1 N2718 P938 DWLD 16 -1 Int BE Pri
!#1 N2719 P938 DWLD 17 -1 Int BE Pri
!#A N2718 N2719
!#1 N2720 P939 BLD 0 -1 FP BE Pri
!#1 N2721 P939 BLD 1 -1 FP BE Pri
!#A N2720 N2721
!#1 N2722 P939 BLD 2 -1 FP BE Pri
!#1 N2723 P939 BLD 3 -1 FP BE Pri
!#1 N2724 P938 DWLD 16 -1 Int BE Pri
!#1 N2725 P938 DWLD 17 -1 Int BE Pri
!#A N2724 N2725
!#1 N2726 P939 BLD 0 -1 FP BE Pri
!#1 N2727 P939 BLD 1 -1 FP BE Pri
!#A N2726 N2727
!#1 N2728 P939 BLD 2 -1 FP BE Pri
!#1 N2729 P939 BLD 3 -1 FP BE Pri
!#1 N2730 P940 BLD 20 -1 FP BE Pri
!#1 N2731 P940 BLD 21 -1 FP BE Pri
!#A N2730 N2731
!#1 N2732 P940 BLD 22 -1 FP BE Pri
!#1 N2733 P940 BLD 23 -1 FP BE Pri
!#1 N2734 P941 DWLD 27 -1 Int BE Pri
!#1 N2735 P942 LD 17 -1 Int BE Pri
!#1 N2736 P943 LD 24 -1 Int BE Pri
!#1 N2737 P944 LD 31 -1 Int BE Pri
!#1 N2738 P945 BLD 8 -1 FP BE Pri
!#1 N2739 P945 BLD 9 -1 FP BE Pri
!#A N2738 N2739
!#1 N2740 P945 BLD 10 -1 FP BE Pri
!#1 N2741 P945 BLD 11 -1 FP BE Pri
!#1 N2742 P946 BSTC 8 0x40000029 FP BE Pri
!#1 N2743 P946 BSTC 9 0x4000002a FP BE Pri
!#A N2742 N2743
!#1 N2744 P946 BSTC 10 0x4000002b FP BE Pri
!#1 N2745 P946 BSTC 11 0x4000002c FP BE Pri
!#1 N2746 P945 BLD 8 -1 FP BE Pri
!#1 N2747 P945 BLD 9 -1 FP BE Pri
!#A N2746 N2747
!#1 N2748 P945 BLD 10 -1 FP BE Pri
!#1 N2749 P945 BLD 11 -1 FP BE Pri
!#1 N2750 P946 BSTC 8 0x4000002d FP BE Pri
!#1 N2751 P946 BSTC 9 0x4000002e FP BE Pri
!#A N2750 N2751
!#1 N2752 P946 BSTC 10 0x4000002f FP BE Pri
!#1 N2753 P946 BSTC 11 0x40000030 FP BE Pri
!#1 N2754 P947 DWLD 8 -1 Int BE Pri
!#1 N2755 P947 DWLD 9 -1 Int BE Pri
!#A N2754 N2755
!#1 N2756 P948 DWLD 4 -1 Int BE Pri
!#1 N2757 P948 DWLD 5 -1 Int BE Pri
!#A N2756 N2757
!#1 N2758 P949 BLD 12 -1 FP BE Pri
!#1 N2759 P949 BLD 13 -1 FP BE Pri
!#A N2758 N2759
!#1 N2760 P949 BLD 14 -1 FP BE Pri
!#1 N2761 P949 BLD 15 -1 FP BE Pri
!#1 N2762 P950 BLD 0 -1 FP BE Pri
!#1 N2763 P950 BLD 1 -1 FP BE Pri
!#A N2762 N2763
!#1 N2764 P950 BLD 2 -1 FP BE Pri
!#1 N2765 P950 BLD 3 -1 FP BE Pri
!#1 N2766 P949 BLD 12 -1 FP BE Pri
!#1 N2767 P949 BLD 13 -1 FP BE Pri
!#A N2766 N2767
!#1 N2768 P949 BLD 14 -1 FP BE Pri
!#1 N2769 P949 BLD 15 -1 FP BE Pri
!#1 N2770 P950 BLD 0 -1 FP BE Pri
!#1 N2771 P950 BLD 1 -1 FP BE Pri
!#A N2770 N2771
!#1 N2772 P950 BLD 2 -1 FP BE Pri
!#1 N2773 P950 BLD 3 -1 FP BE Pri
!#1 N2775 P952 DWLD 0 -1 FP BE Pri
!#1 N2776 P952 DWLD 1 -1 FP BE Pri
!#A N2775 N2776
!#1 N2778 P952 DWLD 0 -1 FP BE Pri
!#1 N2779 P952 DWLD 1 -1 FP BE Pri
!#A N2778 N2779
!#1 N2780 P953 LD 2 -1 Int BE Pri
!#1 N2781 P953 CAS 2 -1 N2780 0x80001f Int BE Pri
!#1 N2782 P954 DWLD 31 -1 Int BE Pri
!#1 N2783 P955 LD 4 -1 Int BE Pri
!#1 N2784 P953 LD 2 -1 Int BE Pri
!#1 N2785 P953 CAS 2 -1 N2784 0x800020 Int BE Pri
!#1 N2786 P954 DWLD 31 -1 Int BE Pri
!#1 N2787 P955 LD 4 -1 Int BE Pri
!#1 N2788 P956 BLD 8 -1 FP BE Pri
!#1 N2789 P956 BLD 9 -1 FP BE Pri
!#A N2788 N2789
!#1 N2790 P956 BLD 10 -1 FP BE Pri
!#1 N2791 P956 BLD 11 -1 FP BE Pri
!#1 N2792 P957 SWAP 27 0xffffffff 0x800021 Int BE Pri
!#1 N2793 P958 LD 24 -1 Int BE Pri
!#1 N2794 P959 DWLD 15 -1 Int BE Pri
!#1 N2795 P960 BLD 24 -1 FP BE Pri
!#1 N2796 P960 BLD 25 -1 FP BE Pri
!#A N2795 N2796
!#1 N2797 P960 BLD 26 -1 FP BE Pri
!#1 N2798 P960 BLD 27 -1 FP BE Pri
!#1 N2799 P961 LD 24 -1 Int BE Pri
!#1 N2800 P962 LD 10 -1 Int BE Pri
!#1 N2801 P963 LD 5 -1 Int BE Pri
!#1 N2802 P964 BLD 20 -1 FP BE Pri
!#1 N2803 P964 BLD 21 -1 FP BE Pri
!#A N2802 N2803
!#1 N2804 P964 BLD 22 -1 FP BE Pri
!#1 N2805 P964 BLD 23 -1 FP BE Pri
!#1 N2806 P965 DWLD 2 -1 Int BE Pri
!#1 N2807 P966 LD 19 -1 Int BE Pri
!#1 N2808 P967 DWLD 14 -1 Int BE Pri
!#1 N2809 P968 LD 13 -1 Int BE Pri
!#1 N2810 P969 DWLD 11 -1 Int BE Pri
!#1 N2811 P970 DWLD 6 -1 Int BE Pri
!#1 N2812 P969 DWLD 11 -1 Int BE Pri
!#1 N2813 P970 DWLD 6 -1 Int BE Pri
!#1 N2814 P971 DWLD 16 -1 Int BE Pri
!#1 N2815 P971 DWLD 17 -1 Int BE Pri
!#A N2814 N2815
!#1 N2816 P972 BLD 0 -1 FP BE Pri
!#1 N2817 P972 BLD 1 -1 FP BE Pri
!#A N2816 N2817
!#1 N2818 P972 BLD 2 -1 FP BE Pri
!#1 N2819 P972 BLD 3 -1 FP BE Pri
!#1 N2820 P973 DWLD 30 -1 Int BE Pri
!#1 N2821 P974 LD 13 -1 Int BE Pri
!#1 N2822 P972 BLD 0 -1 FP BE Pri
!#1 N2823 P972 BLD 1 -1 FP BE Pri
!#A N2822 N2823
!#1 N2824 P972 BLD 2 -1 FP BE Pri
!#1 N2825 P972 BLD 3 -1 FP BE Pri
!#1 N2826 P973 DWLD 30 -1 Int BE Pri
!#1 N2827 P974 LD 13 -1 Int BE Pri
!#1 N2828 P975 BLD 4 -1 FP BE Pri
!#1 N2829 P975 BLD 5 -1 FP BE Pri
!#A N2828 N2829
!#1 N2830 P975 BLD 6 -1 FP BE Pri
!#1 N2831 P975 BLD 7 -1 FP BE Pri
!#1 N2832 P976 LD 13 -1 Int BE Pri
!#1 N2833 P977 LD 20 -1 Int BE Pri
!#1 N2834 P975 BLD 4 -1 FP BE Pri
!#1 N2835 P975 BLD 5 -1 FP BE Pri
!#A N2834 N2835
!#1 N2836 P975 BLD 6 -1 FP BE Pri
!#1 N2837 P975 BLD 7 -1 FP BE Pri
!#1 N2838 P976 LD 13 -1 Int BE Pri
!#1 N2839 P977 LD 20 -1 Int BE Pri
!#1 N2840 P978 BLD 28 -1 FP BE Pri
!#1 N2841 P978 BLD 29 -1 FP BE Pri
!#A N2840 N2841
!#1 N2842 P978 BLD 30 -1 FP BE Pri
!#1 N2843 P978 BLD 31 -1 FP BE Pri
!#1 N2844 P979 LD 29 -1 Int BE Pri
!#1 N2845 P980 LD 20 -1 Int BE Pri
!#1 N2846 P981 DWLD 28 -1 FP BE Pri
!#1 N2847 P981 DWLD 29 -1 FP BE Pri
!#A N2846 N2847
!#1 N2848 P982 DWLD 4 -1 Int BE Pri
!#1 N2849 P982 DWLD 5 -1 Int BE Pri
!#A N2848 N2849
!#1 N2850 P982 DWLD 4 -1 Int BE Pri
!#1 N2851 P982 DWLD 5 -1 Int BE Pri
!#A N2850 N2851
!#1 N2852 P983 DWLD 23 -1 Int BE Pri
!#1 N2853 P984 LD 17 -1 FP BE Pri
!#1 N2854 P985 LD 15 -1 Int BE Pri
!#1 N2855 P983 DWLD 23 -1 Int BE Pri
!#1 N2856 P984 LD 17 -1 FP BE Pri
!#1 N2857 P985 LD 15 -1 Int BE Pri
!#1 N2858 P986 LD 29 -1 FP BE Pri
!#1 N2859 P987 DWLD 20 -1 Int BE Pri
!#1 N2860 P987 DWLD 21 -1 Int BE Pri
!#A N2859 N2860
!#1 N2862 P989 LD 16 -1 Int BE Pri
!#1 N2863 P990 LD 24 -1 Int BE Pri
!#1 N2865 P989 LD 16 -1 Int BE Pri
!#1 N2866 P990 LD 24 -1 Int BE Pri
!#1 N2867 P991 LD 12 -1 Int BE Pri
!#1 N2868 P992 LD 29 -1 FP BE Pri
!#1 N2869 P993 LD 8 -1 Int BE Pri
!#1 N2870 P991 LD 12 -1 Int BE Pri
!#1 N2871 P992 LD 29 -1 FP BE Pri
!#1 N2872 P993 LD 8 -1 Int BE Pri
!#1 N2873 P994 BLD 4 -1 FP BE Pri
!#1 N2874 P994 BLD 5 -1 FP BE Pri
!#A N2873 N2874
!#1 N2875 P994 BLD 6 -1 FP BE Pri
!#1 N2876 P994 BLD 7 -1 FP BE Pri
!#1 N2877 P995 BSTC 20 0x40000031 FP BE Pri
!#1 N2878 P995 BSTC 21 0x40000032 FP BE Pri
!#A N2877 N2878
!#1 N2879 P995 BSTC 22 0x40000033 FP BE Pri
!#1 N2880 P995 BSTC 23 0x40000034 FP BE Pri
!#1 N2881 P996 DWLD 30 -1 Int BE Pri
!#1 N2882 P997 LD 24 -1 Int BE Pri
!#1 N2883 P998 DWLD 24 -1 Int BE Pri
!#1 N2884 P998 DWLD 25 -1 Int BE Pri
!#A N2883 N2884
!#1 N2885 P999 DWLD 16 -1 Int BE Pri
!#1 N2886 P999 DWLD 17 -1 Int BE Pri
!#A N2885 N2886
!#1 N2887 P998 DWLD 24 -1 Int BE Pri
!#1 N2888 P998 DWLD 25 -1 Int BE Pri
!#A N2887 N2888
!#1 N2889 P999 DWLD 16 -1 Int BE Pri
!#1 N2890 P999 DWLD 17 -1 Int BE Pri
!#A N2889 N2890
!#1 N2892 P1001 LD 26 -1 Int BE Pri
!#1 N2893 P1002 LD 27 -1 Int BE Pri
!#1 N2895 P1004 LD 9 -1 Int BE Pri
!#1 N2896 P1005 LD 9 -1 Int BE Pri
!#1 N2897 P1004 LD 9 -1 Int BE Pri
!#1 N2898 P1005 LD 9 -1 Int BE Pri
!#1 N2899 P1006 ST 30 0x800022 Int BE Pri
!#1 N2901 P1008 BLD 12 -1 FP BE Pri
!#1 N2902 P1008 BLD 13 -1 FP BE Pri
!#A N2901 N2902
!#1 N2903 P1008 BLD 14 -1 FP BE Pri
!#1 N2904 P1008 BLD 15 -1 FP BE Pri
!#1 N2905 P1008 BLD 12 -1 FP BE Pri
!#1 N2906 P1008 BLD 13 -1 FP BE Pri
!#A N2905 N2906
!#1 N2907 P1008 BLD 14 -1 FP BE Pri
!#1 N2908 P1008 BLD 15 -1 FP BE Pri
!#1 N2909 P1009 LD 12 -1 Int LE Pri
!#1 N2910 P1010 LD 1 -1 Int BE Pri
!#1 N2911 P1009 LD 12 -1 Int LE Pri
!#1 N2912 P1010 LD 1 -1 Int BE Pri
!#1 N2913 P1011 DWLD 11 -1 Int BE Pri
!#1 N2914 P1012 LD 22 -1 Int BE Pri
!#1 N2915 P1013 DWLD 20 -1 Int BE Pri
!#1 N2916 P1013 DWLD 21 -1 Int BE Pri
!#A N2915 N2916
!#1 N2917 P1013 CASX 20 -1 N2915 0x800023 Int BE Pri
!#1 N2918 P1013 CASX 21 -1 N2916 0x800024 Int BE Pri
!#A N2917 N2918
!#1 N2919 P1014 BLD 0 -1 FP BE Pri
!#1 N2920 P1014 BLD 1 -1 FP BE Pri
!#A N2919 N2920
!#1 N2921 P1014 BLD 2 -1 FP BE Pri
!#1 N2922 P1014 BLD 3 -1 FP BE Pri
!#1 N2923 P1013 DWLD 20 -1 Int BE Pri
!#1 N2924 P1013 DWLD 21 -1 Int BE Pri
!#A N2923 N2924
!#1 N2925 P1013 CASX 20 -1 N2923 0x800025 Int BE Pri
!#1 N2926 P1013 CASX 21 -1 N2924 0x800026 Int BE Pri
!#A N2925 N2926
!#1 N2927 P1014 BLD 0 -1 FP BE Pri
!#1 N2928 P1014 BLD 1 -1 FP BE Pri
!#A N2927 N2928
!#1 N2929 P1014 BLD 2 -1 FP BE Pri
!#1 N2930 P1014 BLD 3 -1 FP BE Pri
!#1 N2931 P1015 LD 16 -1 Int BE Pri
!#1 N2932 P1016 LD 17 -1 Int BE Pri
!#1 N2933 P1015 LD 16 -1 Int BE Pri
!#1 N2934 P1016 LD 17 -1 Int BE Pri
!#1 N2935 P1017 LD 14 -1 Int BE Pri
!#1 N2936 P1018 DWLD 4 -1 Int BE Pri
!#1 N2937 P1018 DWLD 5 -1 Int BE Pri
!#A N2936 N2937
!#1 N2938 P1019 LD 19 -1 Int BE Pri
!#1 N2939 P1020 BLD 0 -1 FP BE Pri
!#1 N2940 P1020 BLD 1 -1 FP BE Pri
!#A N2939 N2940
!#1 N2941 P1020 BLD 2 -1 FP BE Pri
!#1 N2942 P1020 BLD 3 -1 FP BE Pri
!#1 N2943 P1021 BLD 4 -1 FP BE Pri
!#1 N2944 P1021 BLD 5 -1 FP BE Pri
!#A N2943 N2944
!#1 N2945 P1021 BLD 6 -1 FP BE Pri
!#1 N2946 P1021 BLD 7 -1 FP BE Pri
!#1 N2947 P1022 LD 16 -1 Int BE Pri
!#1 N2948 P1023 LD 18 -1 Int LE Pri
!#1 N2949 P1024 MEMBAR
!#1 N2950 P1024 MEMBAR
!#1 N2951 P1025 BSTC 12 0x40000035 FP BE Pri
!#1 N2952 P1025 BSTC 13 0x40000036 FP BE Pri
!#A N2951 N2952
!#1 N2953 P1025 BSTC 14 0x40000037 FP BE Pri
!#1 N2954 P1025 BSTC 15 0x40000038 FP BE Pri
!#1 N2955 P1026 LD 2 -1 Int BE Pri
!#1 N2956 P1027 LD 19 -1 Int BE Pri
!#1 N2957 P1026 LD 2 -1 Int BE Pri
!#1 N2958 P1027 LD 19 -1 Int BE Pri
!#1 N2959 P1028 LD 15 -1 Int BE Pri
!#1 N2960 P1029 LD 25 -1 Int BE Pri
!#1 N2961 P1028 LD 15 -1 Int BE Pri
!#1 N2962 P1029 LD 25 -1 Int BE Pri
!#1 N2963 P1030 BLD 0 -1 FP BE Pri
!#1 N2964 P1030 BLD 1 -1 FP BE Pri
!#A N2963 N2964
!#1 N2965 P1030 BLD 2 -1 FP BE Pri
!#1 N2966 P1030 BLD 3 -1 FP BE Pri
!#1 N2967 P1031 BLD 8 -1 FP BE Pri
!#1 N2968 P1031 BLD 9 -1 FP BE Pri
!#A N2967 N2968
!#1 N2969 P1031 BLD 10 -1 FP BE Pri
!#1 N2970 P1031 BLD 11 -1 FP BE Pri
!#1 N2971 P1030 BLD 0 -1 FP BE Pri
!#1 N2972 P1030 BLD 1 -1 FP BE Pri
!#A N2971 N2972
!#1 N2973 P1030 BLD 2 -1 FP BE Pri
!#1 N2974 P1030 BLD 3 -1 FP BE Pri
!#1 N2975 P1031 BLD 8 -1 FP BE Pri
!#1 N2976 P1031 BLD 9 -1 FP BE Pri
!#A N2975 N2976
!#1 N2977 P1031 BLD 10 -1 FP BE Pri
!#1 N2978 P1031 BLD 11 -1 FP BE Pri
!#1 N2979 P1032 DWLD 27 -1 Int BE Pri
!#1 N2980 P1033 LD 15 -1 Int LE Pri
!#1 N2981 P1034 BLD 16 -1 FP BE Pri
!#1 N2982 P1034 BLD 17 -1 FP BE Pri
!#A N2981 N2982
!#1 N2983 P1034 BLD 18 -1 FP BE Pri
!#1 N2984 P1034 BLD 19 -1 FP BE Pri
!#1 N2985 P1035 LD 3 -1 Int BE Pri
!#1 N2986 P1036 BST 16 0x40000039 FP BE Pri
!#1 N2987 P1036 BST 17 0x4000003a FP BE Pri
!#A N2986 N2987
!#1 N2988 P1036 BST 18 0x4000003b FP BE Pri
!#1 N2989 P1036 BST 19 0x4000003c FP BE Pri
!#1 N2990 P1037 LD 19 -1 Int BE Pri
!#1 N2991 P1035 LD 3 -1 Int BE Pri
!#1 N2992 P1036 BST 16 0x4000003d FP BE Pri
!#1 N2993 P1036 BST 17 0x4000003e FP BE Pri
!#A N2992 N2993
!#1 N2994 P1036 BST 18 0x4000003f FP BE Pri
!#1 N2995 P1036 BST 19 0x40000040 FP BE Pri
!#1 N2996 P1037 LD 19 -1 Int BE Pri
!#1 N2997 P1038 LD 24 -1 Int BE Pri
!#1 N2998 P1039 BLD 8 -1 FP BE Pri
!#1 N2999 P1039 BLD 9 -1 FP BE Pri
!#A N2998 N2999
!#1 N3000 P1039 BLD 10 -1 FP BE Pri
!#1 N3001 P1039 BLD 11 -1 FP BE Pri
!#1 N3002 P1040 LD 10 -1 Int BE Pri
!#1 N3003 P1041 DWLD 8 -1 Int BE Pri
!#1 N3004 P1041 DWLD 9 -1 Int BE Pri
!#A N3003 N3004
!#1 N3005 P1042 DWLD 8 -1 Int BE Pri
!#1 N3006 P1042 DWLD 9 -1 Int BE Pri
!#A N3005 N3006
!#1 N3007 P1041 DWLD 8 -1 Int BE Pri
!#1 N3008 P1041 DWLD 9 -1 Int BE Pri
!#A N3007 N3008
!#1 N3009 P1042 DWLD 8 -1 Int BE Pri
!#1 N3010 P1042 DWLD 9 -1 Int BE Pri
!#A N3009 N3010
!#1 N3011 P1043 LD 20 -1 Int BE Pri
!#1 N3012 P1044 LD 4 -1 Int BE Pri
!#1 N3014 P1046 DWLD 24 -1 Int BE Pri
!#1 N3015 P1046 DWLD 25 -1 Int BE Pri
!#A N3014 N3015
!#1 N3017 P1046 DWLD 24 -1 Int BE Pri
!#1 N3018 P1046 DWLD 25 -1 Int BE Pri
!#A N3017 N3018
!#1 N3019 P1047 ST 12 0x40000041 FP BE Pri
!#1 N3020 P1048 DWLD 18 -1 Int BE Pri
!#1 N3021 P1049 LD 16 -1 Int BE Pri
!#1 N3022 P1047 ST 12 0x40000042 FP BE Pri
!#1 N3023 P1048 DWLD 18 -1 Int BE Pri
!#1 N3024 P1049 LD 16 -1 Int BE Pri
!#1 N3025 P1050 LD 25 -1 Int BE Pri
!#1 N3026 P1051 BLD 12 -1 FP BE Pri
!#1 N3027 P1051 BLD 13 -1 FP BE Pri
!#A N3026 N3027
!#1 N3028 P1051 BLD 14 -1 FP BE Pri
!#1 N3029 P1051 BLD 15 -1 FP BE Pri
!#1 N3030 P1052 LD 13 -1 Int BE Pri
!#1 N3031 P1053 ST 31 0x800027 Int BE Pri
!#1 N3032 P1054 BLD 20 -1 FP BE Pri
!#1 N3033 P1054 BLD 21 -1 FP BE Pri
!#A N3032 N3033
!#1 N3034 P1054 BLD 22 -1 FP BE Pri
!#1 N3035 P1054 BLD 23 -1 FP BE Pri
!#1 N3036 P1053 ST 31 0x800028 Int BE Pri
!#1 N3037 P1054 BLD 20 -1 FP BE Pri
!#1 N3038 P1054 BLD 21 -1 FP BE Pri
!#A N3037 N3038
!#1 N3039 P1054 BLD 22 -1 FP BE Pri
!#1 N3040 P1054 BLD 23 -1 FP BE Pri
!#1 N3041 P1055 BLD 0 -1 FP BE Pri
!#1 N3042 P1055 BLD 1 -1 FP BE Pri
!#A N3041 N3042
!#1 N3043 P1055 BLD 2 -1 FP BE Pri
!#1 N3044 P1055 BLD 3 -1 FP BE Pri
!#1 N3045 P1056 LD 14 -1 Int BE Pri
!#1 N3046 P1057 LD 14 -1 Int BE Pri
!#1 N3047 P1058 DWLD 23 -1 Int BE Pri
!#1 N3048 P1059 LD 3 -1 Int BE Pri
!#1 N3049 P1060 LD 13 -1 Int BE Pri
!#1 N3050 P1061 LD 7 -1 Int BE Pri
!#1 N3051 P1062 DWLD 7 -1 FP BE Pri
!#1 N3052 P1063 LD 6 -1 Int BE Pri
!#1 N3053 P1064 LD 26 -1 Int BE Pri
!#1 N3054 P1062 DWLD 7 -1 FP BE Pri
!#1 N3055 P1063 LD 6 -1 Int BE Pri
!#1 N3056 P1064 LD 26 -1 Int BE Pri
!#1 N3057 P1065 LD 4 -1 Int BE Pri
!#1 N3058 P1066 LD 19 -1 Int BE Pri
!#1 N3059 P1067 LD 16 -1 Int BE Pri
!#1 N3060 P1068 LD 18 -1 Int BE Pri
!#1 N3061 P1067 LD 16 -1 Int BE Pri
!#1 N3062 P1068 LD 18 -1 Int BE Pri
!#1 N3063 P1069 DWLD 3 -1 Int BE Pri
!#1 N3064 P1070 BLD 0 -1 FP BE Pri
!#1 N3065 P1070 BLD 1 -1 FP BE Pri
!#A N3064 N3065
!#1 N3066 P1070 BLD 2 -1 FP BE Pri
!#1 N3067 P1070 BLD 3 -1 FP BE Pri
!#1 N3068 P1071 LD 7 -1 Int BE Pri
!#1 N3069 P1072 BLD 8 -1 FP BE Pri
!#1 N3070 P1072 BLD 9 -1 FP BE Pri
!#A N3069 N3070
!#1 N3071 P1072 BLD 10 -1 FP BE Pri
!#1 N3072 P1072 BLD 11 -1 FP BE Pri
!#1 N3073 P1073 DWLD 15 -1 Int BE Pri
!#1 N3074 P1074 BLD 20 -1 FP BE Pri
!#1 N3075 P1074 BLD 21 -1 FP BE Pri
!#A N3074 N3075
!#1 N3076 P1074 BLD 22 -1 FP BE Pri
!#1 N3077 P1074 BLD 23 -1 FP BE Pri
!#1 N3078 P1075 LD 17 -1 Int BE Pri
!#1 N3079 P1073 DWLD 15 -1 Int BE Pri
!#1 N3080 P1074 BLD 20 -1 FP BE Pri
!#1 N3081 P1074 BLD 21 -1 FP BE Pri
!#A N3080 N3081
!#1 N3082 P1074 BLD 22 -1 FP BE Pri
!#1 N3083 P1074 BLD 23 -1 FP BE Pri
!#1 N3084 P1075 LD 17 -1 Int BE Pri
!#1 N3085 P1076 BLD 20 -1 FP BE Pri
!#1 N3086 P1076 BLD 21 -1 FP BE Pri
!#A N3085 N3086
!#1 N3087 P1076 BLD 22 -1 FP BE Pri
!#1 N3088 P1076 BLD 23 -1 FP BE Pri
!#1 N3089 P1077 BLD 16 -1 FP BE Pri
!#1 N3090 P1077 BLD 17 -1 FP BE Pri
!#A N3089 N3090
!#1 N3091 P1077 BLD 18 -1 FP BE Pri
!#1 N3092 P1077 BLD 19 -1 FP BE Pri
!#1 N3093 P1076 BLD 20 -1 FP BE Pri
!#1 N3094 P1076 BLD 21 -1 FP BE Pri
!#A N3093 N3094
!#1 N3095 P1076 BLD 22 -1 FP BE Pri
!#1 N3096 P1076 BLD 23 -1 FP BE Pri
!#1 N3097 P1077 BLD 16 -1 FP BE Pri
!#1 N3098 P1077 BLD 17 -1 FP BE Pri
!#A N3097 N3098
!#1 N3099 P1077 BLD 18 -1 FP BE Pri
!#1 N3100 P1077 BLD 19 -1 FP BE Pri
!#1 N3101 P1078 LD 8 -1 Int BE Pri
!#1 N3102 P1079 LD 18 -1 FP BE Pri
!#1 N3103 P1080 LD 16 -1 Int BE Pri
!#1 N3104 P1078 LD 8 -1 Int BE Pri
!#1 N3105 P1079 LD 18 -1 FP BE Pri
!#1 N3106 P1080 LD 16 -1 Int BE Pri
!#1 N3107 P1081 DWLD 26 -1 Int BE Pri
!#1 N3108 P1082 LD 16 -1 FP BE Pri
!#1 N3109 P1083 LD 4 -1 Int BE Pri
!#1 N3110 P1084 LD 19 -1 Int LE Pri
!#1 N3111 P1085 DWLD 14 -1 Int BE Pri
!#1 N3112 P1084 LD 19 -1 Int LE Pri
!#1 N3113 P1085 DWLD 14 -1 Int BE Pri
!#1 N3114 P1086 ST 28 0x800029 Int BE Pri
!#1 N3115 P1087 DWLD 26 -1 Int LE Pri
!#1 N3116 P1088 LD 22 -1 Int BE Pri
!#1 N3117 P1089 DWLD 4 -1 Int BE Pri
!#1 N3118 P1089 DWLD 5 -1 Int BE Pri
!#A N3117 N3118
!#1 N3119 P1090 BLD 28 -1 FP BE Pri
!#1 N3120 P1090 BLD 29 -1 FP BE Pri
!#A N3119 N3120
!#1 N3121 P1090 BLD 30 -1 FP BE Pri
!#1 N3122 P1090 BLD 31 -1 FP BE Pri
!#1 N3123 P1089 DWLD 4 -1 Int BE Pri
!#1 N3124 P1089 DWLD 5 -1 Int BE Pri
!#A N3123 N3124
!#1 N3125 P1090 BLD 28 -1 FP BE Pri
!#1 N3126 P1090 BLD 29 -1 FP BE Pri
!#A N3125 N3126
!#1 N3127 P1090 BLD 30 -1 FP BE Pri
!#1 N3128 P1090 BLD 31 -1 FP BE Pri
!#1 N3129 P1091 BSTC 24 0x40000043 FP BE Pri
!#1 N3130 P1091 BSTC 25 0x40000044 FP BE Pri
!#A N3129 N3130
!#1 N3131 P1091 BSTC 26 0x40000045 FP BE Pri
!#1 N3132 P1091 BSTC 27 0x40000046 FP BE Pri
!#1 N3133 P1091 BSTC 24 0x40000047 FP BE Pri
!#1 N3134 P1091 BSTC 25 0x40000048 FP BE Pri
!#A N3133 N3134
!#1 N3135 P1091 BSTC 26 0x40000049 FP BE Pri
!#1 N3136 P1091 BSTC 27 0x4000004a FP BE Pri
!#1 N3137 P1092 DWLD 28 -1 Int BE Pri
!#1 N3138 P1092 DWLD 29 -1 Int BE Pri
!#A N3137 N3138
!#1 N3139 P1092 CASX 28 -1 N3137 0x80002a Int BE Pri
!#1 N3140 P1092 CASX 29 -1 N3138 0x80002b Int BE Pri
!#A N3139 N3140
!#1 N3141 P1092 DWLD 28 -1 Int BE Pri
!#1 N3142 P1092 DWLD 29 -1 Int BE Pri
!#A N3141 N3142
!#1 N3143 P1092 CASX 28 -1 N3141 0x80002c Int BE Pri
!#1 N3144 P1092 CASX 29 -1 N3142 0x80002d Int BE Pri
!#A N3143 N3144
!#1 N3145 P1093 DWLD 14 -1 Int BE Pri
!#1 N3146 P1094 LD 30 -1 Int BE Pri
!#1 N3147 P1093 DWLD 14 -1 Int BE Pri
!#1 N3148 P1094 LD 30 -1 Int BE Pri
!#1 N3149 P1095 DWLD 28 -1 Int BE Pri
!#1 N3150 P1095 DWLD 29 -1 Int BE Pri
!#A N3149 N3150
!#1 N3151 P1096 DWLD 27 -1 Int BE Pri
!#1 N3152 P1097 LD 19 -1 Int BE Pri
!#1 N3153 P1095 DWLD 28 -1 Int BE Pri
!#1 N3154 P1095 DWLD 29 -1 Int BE Pri
!#A N3153 N3154
!#1 N3155 P1096 DWLD 27 -1 Int BE Pri
!#1 N3156 P1097 LD 19 -1 Int BE Pri
!#1 N3157 P1098 BLD 16 -1 FP BE Pri
!#1 N3158 P1098 BLD 17 -1 FP BE Pri
!#A N3157 N3158
!#1 N3159 P1098 BLD 18 -1 FP BE Pri
!#1 N3160 P1098 BLD 19 -1 FP BE Pri
!#1 N3161 P1099 LD 24 -1 Int BE Pri
!#1 N3162 P1100 LD 7 -1 Int BE Pri
!#1 N3163 P1101 LD 30 -1 Int BE Pri
!#1 N3165 P1103 LD 14 -1 Int BE Pri
!#1 N3166 P1101 LD 30 -1 Int BE Pri
!#1 N3168 P1103 LD 14 -1 Int BE Pri
!#1 N3169 P1104 DWLD 8 -1 Int BE Pri
!#1 N3170 P1104 DWLD 9 -1 Int BE Pri
!#A N3169 N3170
!#1 N3171 P1105 LD 9 -1 Int BE Pri
!#1 N3172 P1106 LD 27 -1 Int BE Pri
!#1 N3173 P1104 DWLD 8 -1 Int BE Pri
!#1 N3174 P1104 DWLD 9 -1 Int BE Pri
!#A N3173 N3174
!#1 N3175 P1105 LD 9 -1 Int BE Pri
!#1 N3176 P1106 LD 27 -1 Int BE Pri
!#1 N3177 P1107 LD 10 -1 Int BE Pri
!#1 N3178 P1108 BST 28 0x4000004b FP BE Pri
!#1 N3179 P1108 BST 29 0x4000004c FP BE Pri
!#A N3178 N3179
!#1 N3180 P1108 BST 30 0x4000004d FP BE Pri
!#1 N3181 P1108 BST 31 0x4000004e FP BE Pri
!#1 N3182 P1109 LD 25 -1 Int BE Pri
!#1 N3183 P1107 LD 10 -1 Int BE Pri
!#1 N3184 P1108 BST 28 0x4000004f FP BE Pri
!#1 N3185 P1108 BST 29 0x40000050 FP BE Pri
!#A N3184 N3185
!#1 N3186 P1108 BST 30 0x40000051 FP BE Pri
!#1 N3187 P1108 BST 31 0x40000052 FP BE Pri
!#1 N3188 P1109 LD 25 -1 Int BE Pri
!#1 N3189 P1110 BLD 8 -1 FP BE Pri
!#1 N3190 P1110 BLD 9 -1 FP BE Pri
!#A N3189 N3190
!#1 N3191 P1110 BLD 10 -1 FP BE Pri
!#1 N3192 P1110 BLD 11 -1 FP BE Pri
!#1 N3193 P1111 BLD 16 -1 FP BE Pri
!#1 N3194 P1111 BLD 17 -1 FP BE Pri
!#A N3193 N3194
!#1 N3195 P1111 BLD 18 -1 FP BE Pri
!#1 N3196 P1111 BLD 19 -1 FP BE Pri
!#1 N3197 P1112 LD 9 -1 Int BE Pri
!#1 N3198 P1113 LD 4 -1 Int BE Pri
!#1 N3199 P1112 LD 9 -1 Int BE Pri
!#1 N3200 P1113 LD 4 -1 Int BE Pri
!#1 N3201 P1114 LD 15 -1 Int BE Pri
!#1 N3202 P1115 LD 18 -1 Int BE Pri
!#1 N3203 P1116 BLD 12 -1 FP BE Pri
!#1 N3204 P1116 BLD 13 -1 FP BE Pri
!#A N3203 N3204
!#1 N3205 P1116 BLD 14 -1 FP BE Pri
!#1 N3206 P1116 BLD 15 -1 FP BE Pri
!#1 N3207 P1117 LD 28 -1 Int BE Pri
!#1 N3208 P1118 MEMBAR
!#1 N3209 P1119 LD 4 -1 Int BE Pri
!#1 N3210 P1117 LD 28 -1 Int BE Pri
!#1 N3211 P1118 MEMBAR
!#1 N3212 P1119 LD 4 -1 Int BE Pri
!#1 N3213 P1120 LD 7 -1 FP BE Pri
!#1 N3214 P1121 DWLD 8 -1 Int BE Pri
!#1 N3215 P1121 DWLD 9 -1 Int BE Pri
!#A N3214 N3215
!#1 N3216 P1121 CASX 8 -1 N3214 0x80002e Int BE Pri
!#1 N3217 P1121 CASX 9 -1 N3215 0x80002f Int BE Pri
!#A N3216 N3217
!#1 N3218 P1122 DWLD 30 -1 Int BE Pri
!#1 N3219 P1123 LD 28 -1 Int BE Pri
!#1 N3220 P1124 DWLD 10 -1 Int BE Pri
!#1 N3221 P1125 LD 15 -1 Int BE Pri
!#1 N3222 P1124 DWLD 10 -1 Int BE Pri
!#1 N3223 P1125 LD 15 -1 Int BE Pri
!#1 N3224 P1126 DWLD 12 -1 Int BE Pri
!#1 N3225 P1126 DWLD 13 -1 Int BE Pri
!#A N3224 N3225
!#1 N3226 P1126 DWLD 12 -1 Int BE Pri
!#1 N3227 P1126 DWLD 13 -1 Int BE Pri
!#A N3226 N3227
!#1 N3228 P1127 DWLD 24 -1 Int BE Pri
!#1 N3229 P1127 DWLD 25 -1 Int BE Pri
!#A N3228 N3229
!#1 N3230 P1127 DWLD 24 -1 Int BE Pri
!#1 N3231 P1127 DWLD 25 -1 Int BE Pri
!#A N3230 N3231
!#1 N3232 P1128 LD 16 -1 FP BE Pri
!#1 N3233 P1128 LD 16 -1 FP BE Pri
!#1 N3234 P1129 BLD 8 -1 FP BE Pri
!#1 N3235 P1129 BLD 9 -1 FP BE Pri
!#A N3234 N3235
!#1 N3236 P1129 BLD 10 -1 FP BE Pri
!#1 N3237 P1129 BLD 11 -1 FP BE Pri
!#1 N3238 P1130 BLD 16 -1 FP BE Pri
!#1 N3239 P1130 BLD 17 -1 FP BE Pri
!#A N3238 N3239
!#1 N3240 P1130 BLD 18 -1 FP BE Pri
!#1 N3241 P1130 BLD 19 -1 FP BE Pri
!#1 N3242 P1131 BLD 16 -1 FP BE Pri
!#1 N3243 P1131 BLD 17 -1 FP BE Pri
!#A N3242 N3243
!#1 N3244 P1131 BLD 18 -1 FP BE Pri
!#1 N3245 P1131 BLD 19 -1 FP BE Pri
!#1 N3246 P1132 LD 25 -1 Int BE Pri
!#1 N3247 P1133 LD 22 -1 Int BE Pri
!#1 N3248 P1131 BLD 16 -1 FP BE Pri
!#1 N3249 P1131 BLD 17 -1 FP BE Pri
!#A N3248 N3249
!#1 N3250 P1131 BLD 18 -1 FP BE Pri
!#1 N3251 P1131 BLD 19 -1 FP BE Pri
!#1 N3252 P1132 LD 25 -1 Int BE Pri
!#1 N3253 P1133 LD 22 -1 Int BE Pri
!#1 N3254 P1134 LD 28 -1 Int BE Pri
!#1 N3255 P1135 LD 3 -1 Int BE Pri
!#1 N3256 P1134 LD 28 -1 Int BE Pri
!#1 N3257 P1135 LD 3 -1 Int BE Pri
!#1 N3258 P1136 LD 9 -1 Int BE Pri
!#1 N3259 P1137 LD 0 -1 Int BE Pri
!#1 N3260 P1138 LD 0 -1 Int LE Pri
!#1 N3261 P1139 LD 2 -1 Int BE Pri
!#1 N3262 P1138 LD 0 -1 Int LE Pri
!#1 N3263 P1139 LD 2 -1 Int BE Pri
!#1 N3264 P1140 LD 21 -1 Int BE Pri
!#1 N3265 P1141 LD 2 -1 Int BE Pri
!#1 N3266 P1140 LD 21 -1 Int BE Pri
!#1 N3267 P1141 LD 2 -1 Int BE Pri
!#1 N3268 P1142 ST 25 0x800030 Int BE Pri
!#1 N3269 P1143 LD 11 -1 Int LE Pri
!#1 N3270 P1144 LD 0 -1 Int BE Pri
!#1 N3271 P1145 DWLD 3 -1 Int BE Pri
!#1 N3272 P1146 DWLD 23 -1 Int BE Pri
!#1 N3274 P1148 DWLD 0 -1 Int BE Pri
!#1 N3275 P1148 DWLD 1 -1 Int BE Pri
!#A N3274 N3275
!#1 N3277 P1148 DWLD 0 -1 Int BE Pri
!#1 N3278 P1148 DWLD 1 -1 Int BE Pri
!#A N3277 N3278
!#1 N3281 P1150 BLD 4 -1 FP BE Pri
!#1 N3282 P1150 BLD 5 -1 FP BE Pri
!#A N3281 N3282
!#1 N3283 P1150 BLD 6 -1 FP BE Pri
!#1 N3284 P1150 BLD 7 -1 FP BE Pri
!#1 N3285 P1151 DWLD 16 -1 Int BE Pri
!#1 N3286 P1151 DWLD 17 -1 Int BE Pri
!#A N3285 N3286
!#1 N3287 P1152 DWLD 8 -1 Int BE Pri
!#1 N3288 P1152 DWLD 9 -1 Int BE Pri
!#A N3287 N3288
!#1 N3289 P1153 DWLD 24 -1 Int BE Pri
!#1 N3290 P1153 DWLD 25 -1 Int BE Pri
!#A N3289 N3290
!#1 N3291 P1154 DWLD 11 -1 Int BE Pri
!#1 N3292 P1155 LD 22 -1 Int BE Pri
!#1 N3293 P1153 DWLD 24 -1 Int BE Pri
!#1 N3294 P1153 DWLD 25 -1 Int BE Pri
!#A N3293 N3294
!#1 N3295 P1154 DWLD 11 -1 Int BE Pri
!#1 N3296 P1155 LD 22 -1 Int BE Pri
!#1 N3297 P1156 DWLD 27 -1 Int BE Pri
!#1 N3298 P1157 LD 7 -1 Int BE Pri
!#1 N3299 P1156 DWLD 27 -1 Int BE Pri
!#1 N3300 P1157 LD 7 -1 Int BE Pri
!#1 N3301 P1158 MEMBAR
!#1 N3302 P1159 DWLD 8 -1 Int LE Pri
!#1 N3303 P1159 DWLD 9 -1 Int LE Pri
!#A N3302 N3303
!#1 N3304 P1158 MEMBAR
!#1 N3305 P1159 DWLD 8 -1 Int LE Pri
!#1 N3306 P1159 DWLD 9 -1 Int LE Pri
!#A N3305 N3306
!#1 N3308 P1161 BLD 4 -1 FP BE Pri
!#1 N3309 P1161 BLD 5 -1 FP BE Pri
!#A N3308 N3309
!#1 N3310 P1161 BLD 6 -1 FP BE Pri
!#1 N3311 P1161 BLD 7 -1 FP BE Pri
!#1 N3312 P1162 DWLD 28 -1 Int BE Pri
!#1 N3313 P1162 DWLD 29 -1 Int BE Pri
!#A N3312 N3313
!#1 N3314 P1162 DWLD 28 -1 Int BE Pri
!#1 N3315 P1162 DWLD 29 -1 Int BE Pri
!#A N3314 N3315
!#1 N3316 P1163 BLD 20 -1 FP BE Pri
!#1 N3317 P1163 BLD 21 -1 FP BE Pri
!#A N3316 N3317
!#1 N3318 P1163 BLD 22 -1 FP BE Pri
!#1 N3319 P1163 BLD 23 -1 FP BE Pri
!#1 N3320 P1164 DWLD 12 -1 Int BE Pri
!#1 N3321 P1164 DWLD 13 -1 Int BE Pri
!#A N3320 N3321
!#1 N3322 P1164 CASX 12 -1 N3320 0x800031 Int BE Pri
!#1 N3323 P1164 CASX 13 -1 N3321 0x800032 Int BE Pri
!#A N3322 N3323
!#1 N3324 P1163 BLD 20 -1 FP BE Pri
!#1 N3325 P1163 BLD 21 -1 FP BE Pri
!#A N3324 N3325
!#1 N3326 P1163 BLD 22 -1 FP BE Pri
!#1 N3327 P1163 BLD 23 -1 FP BE Pri
!#1 N3328 P1164 DWLD 12 -1 Int BE Pri
!#1 N3329 P1164 DWLD 13 -1 Int BE Pri
!#A N3328 N3329
!#1 N3330 P1164 CASX 12 -1 N3328 0x800033 Int BE Pri
!#1 N3331 P1164 CASX 13 -1 N3329 0x800034 Int BE Pri
!#A N3330 N3331
!#1 N3332 P1165 LD 1 -1 Int BE Pri
!#1 N3333 P1166 LD 22 -1 Int BE Pri
!#1 N3334 P1165 LD 1 -1 Int BE Pri
!#1 N3335 P1166 LD 22 -1 Int BE Pri
!#1 N3336 P1167 BLD 8 -1 FP BE Pri
!#1 N3337 P1167 BLD 9 -1 FP BE Pri
!#A N3336 N3337
!#1 N3338 P1167 BLD 10 -1 FP BE Pri
!#1 N3339 P1167 BLD 11 -1 FP BE Pri
!#1 N3340 P1168 LD 13 -1 Int BE Pri
!#1 N3341 P1169 LD 29 -1 Int BE Pri
!#1 N3342 P1168 LD 13 -1 Int BE Pri
!#1 N3343 P1169 LD 29 -1 Int BE Pri
!#1 N3344 P1170 BST 24 0x40000053 FP BE Pri
!#1 N3345 P1170 BST 25 0x40000054 FP BE Pri
!#A N3344 N3345
!#1 N3346 P1170 BST 26 0x40000055 FP BE Pri
!#1 N3347 P1170 BST 27 0x40000056 FP BE Pri
!#1 N3348 P1171 BLD 16 -1 FP BE Pri
!#1 N3349 P1171 BLD 17 -1 FP BE Pri
!#A N3348 N3349
!#1 N3350 P1171 BLD 18 -1 FP BE Pri
!#1 N3351 P1171 BLD 19 -1 FP BE Pri
!#1 N3352 P1170 BST 24 0x40000057 FP BE Pri
!#1 N3353 P1170 BST 25 0x40000058 FP BE Pri
!#A N3352 N3353
!#1 N3354 P1170 BST 26 0x40000059 FP BE Pri
!#1 N3355 P1170 BST 27 0x4000005a FP BE Pri
!#1 N3356 P1171 BLD 16 -1 FP BE Pri
!#1 N3357 P1171 BLD 17 -1 FP BE Pri
!#A N3356 N3357
!#1 N3358 P1171 BLD 18 -1 FP BE Pri
!#1 N3359 P1171 BLD 19 -1 FP BE Pri
!#1 N3360 P1172 BLD 12 -1 FP BE Pri
!#1 N3361 P1172 BLD 13 -1 FP BE Pri
!#A N3360 N3361
!#1 N3362 P1172 BLD 14 -1 FP BE Pri
!#1 N3363 P1172 BLD 15 -1 FP BE Pri
!#1 N3364 P1173 BLD 0 -1 FP BE Pri
!#1 N3365 P1173 BLD 1 -1 FP BE Pri
!#A N3364 N3365
!#1 N3366 P1173 BLD 2 -1 FP BE Pri
!#1 N3367 P1173 BLD 3 -1 FP BE Pri
!#1 N3368 P1174 BLD 12 -1 FP BE Pri
!#1 N3369 P1174 BLD 13 -1 FP BE Pri
!#A N3368 N3369
!#1 N3370 P1174 BLD 14 -1 FP BE Pri
!#1 N3371 P1174 BLD 15 -1 FP BE Pri
!#1 N3372 P1174 BLD 12 -1 FP BE Pri
!#1 N3373 P1174 BLD 13 -1 FP BE Pri
!#A N3372 N3373
!#1 N3374 P1174 BLD 14 -1 FP BE Pri
!#1 N3375 P1174 BLD 15 -1 FP BE Pri
!#1 N3376 P1175 LD 23 -1 Int BE Pri
!#1 N3377 P1175 CAS 23 -1 N3376 0x800035 Int BE Pri
!#1 N3378 P1175 LD 23 -1 Int BE Pri
!#1 N3379 P1175 CAS 23 -1 N3378 0x800036 Int BE Pri
!#1 N3380 P1176 DWLD 7 -1 Int BE Pri
!#1 N3381 P1177 DWLD 20 -1 Int BE Pri
!#1 N3382 P1177 DWLD 21 -1 Int BE Pri
!#A N3381 N3382
!#1 N3383 P1178 LD 9 -1 Int BE Pri
!#1 N3387 P1181 BLD 24 -1 FP BE Pri
!#1 N3388 P1181 BLD 25 -1 FP BE Pri
!#A N3387 N3388
!#1 N3389 P1181 BLD 26 -1 FP BE Pri
!#1 N3390 P1181 BLD 27 -1 FP BE Pri
!#1 N3392 P1181 BLD 24 -1 FP BE Pri
!#1 N3393 P1181 BLD 25 -1 FP BE Pri
!#A N3392 N3393
!#1 N3394 P1181 BLD 26 -1 FP BE Pri
!#1 N3395 P1181 BLD 27 -1 FP BE Pri
!#1 N3396 P1182 BLD 0 -1 FP BE Pri
!#1 N3397 P1182 BLD 1 -1 FP BE Pri
!#A N3396 N3397
!#1 N3398 P1182 BLD 2 -1 FP BE Pri
!#1 N3399 P1182 BLD 3 -1 FP BE Pri
!#1 N3400 P1183 ST 4 0x4000005b FP BE Pri
!#1 N3401 P1182 BLD 0 -1 FP BE Pri
!#1 N3402 P1182 BLD 1 -1 FP BE Pri
!#A N3401 N3402
!#1 N3403 P1182 BLD 2 -1 FP BE Pri
!#1 N3404 P1182 BLD 3 -1 FP BE Pri
!#1 N3405 P1183 ST 4 0x4000005c FP BE Pri
!#1 N3406 P1184 DWLD 4 -1 Int BE Pri
!#1 N3407 P1184 DWLD 5 -1 Int BE Pri
!#A N3406 N3407
!#1 N3408 P1185 BLD 8 -1 FP BE Pri
!#1 N3409 P1185 BLD 9 -1 FP BE Pri
!#A N3408 N3409
!#1 N3410 P1185 BLD 10 -1 FP BE Pri
!#1 N3411 P1185 BLD 11 -1 FP BE Pri
!#1 N3412 P1186 SWAP 29 0xffffffff 0x800037 Int BE Pri
!#1 N3413 P1187 BLD 20 -1 FP BE Pri
!#1 N3414 P1187 BLD 21 -1 FP BE Pri
!#A N3413 N3414
!#1 N3415 P1187 BLD 22 -1 FP BE Pri
!#1 N3416 P1187 BLD 23 -1 FP BE Pri
!#1 N3417 P1188 LD 30 -1 Int BE Pri
!#1 N3418 P1186 SWAP 29 0xffffffff 0x800038 Int BE Pri
!#1 N3419 P1187 BLD 20 -1 FP BE Pri
!#1 N3420 P1187 BLD 21 -1 FP BE Pri
!#A N3419 N3420
!#1 N3421 P1187 BLD 22 -1 FP BE Pri
!#1 N3422 P1187 BLD 23 -1 FP BE Pri
!#1 N3423 P1188 LD 30 -1 Int BE Pri
!#1 N3424 P1189 SWAP 28 0xffffffff 0x800039 Int BE Pri
!#1 N3425 P1190 BLD 28 -1 FP BE Pri
!#1 N3426 P1190 BLD 29 -1 FP BE Pri
!#A N3425 N3426
!#1 N3427 P1190 BLD 30 -1 FP BE Pri
!#1 N3428 P1190 BLD 31 -1 FP BE Pri
!#1 N3429 P1191 LD 19 -1 Int BE Pri
!#1 N3430 P1189 SWAP 28 0xffffffff 0x80003a Int BE Pri
!#1 N3431 P1190 BLD 28 -1 FP BE Pri
!#1 N3432 P1190 BLD 29 -1 FP BE Pri
!#A N3431 N3432
!#1 N3433 P1190 BLD 30 -1 FP BE Pri
!#1 N3434 P1190 BLD 31 -1 FP BE Pri
!#1 N3435 P1191 LD 19 -1 Int BE Pri
!#1 N3436 P1192 DWLD 14 -1 Int BE Pri
!#1 N3437 P1193 LD 0 -1 Int BE Pri
!#1 N3438 P1194 DWLD 26 -1 FP BE Pri
!#1 N3439 P1195 LD 31 -1 Int BE Pri
!#1 N3440 P1196 LD 8 -1 Int BE Pri
!#1 N3441 P1194 DWLD 26 -1 FP BE Pri
!#1 N3442 P1195 LD 31 -1 Int BE Pri
!#1 N3443 P1196 LD 8 -1 Int BE Pri
!#1 N3444 P1197 BLD 8 -1 FP BE Pri
!#1 N3445 P1197 BLD 9 -1 FP BE Pri
!#A N3444 N3445
!#1 N3446 P1197 BLD 10 -1 FP BE Pri
!#1 N3447 P1197 BLD 11 -1 FP BE Pri
!#1 N3448 P1198 DWLD 4 -1 Int BE Pri
!#1 N3449 P1198 DWLD 5 -1 Int BE Pri
!#A N3448 N3449
!#1 N3450 P1199 LD 29 -1 Int BE Pri
!#1 N3452 P1201 LD 31 -1 Int BE Pri
!#1 N3453 P1199 LD 29 -1 Int BE Pri
!#1 N3455 P1201 LD 31 -1 Int BE Pri
!#1 N3456 P1202 DWLD 6 -1 Int BE Pri
!#1 N3457 P1203 LD 10 -1 Int BE Pri
!#1 N3458 P1204 LD 11 -1 Int BE Pri
!#1 N3459 P1205 BLD 28 -1 FP BE Pri
!#1 N3460 P1205 BLD 29 -1 FP BE Pri
!#A N3459 N3460
!#1 N3461 P1205 BLD 30 -1 FP BE Pri
!#1 N3462 P1205 BLD 31 -1 FP BE Pri
!#1 N3463 P1206 LD 21 -1 Int LE Pri
!#1 N3464 P1204 LD 11 -1 Int BE Pri
!#1 N3465 P1205 BLD 28 -1 FP BE Pri
!#1 N3466 P1205 BLD 29 -1 FP BE Pri
!#A N3465 N3466
!#1 N3467 P1205 BLD 30 -1 FP BE Pri
!#1 N3468 P1205 BLD 31 -1 FP BE Pri
!#1 N3469 P1206 LD 21 -1 Int LE Pri
!#1 N3470 P1207 LD 31 -1 Int BE Pri
!#1 N3471 P1208 LD 30 -1 Int BE Pri
!#1 N3472 P1209 LD 1 -1 Int BE Pri
!#1 N3473 P1210 LD 11 -1 Int BE Pri
!#1 N3474 P1211 LD 27 -1 Int BE Pri
!#1 N3475 P1212 LD 19 -1 Int BE Pri
!#1 N3476 P1213 LD 27 -1 Int BE Pri
!#1 N3477 P1214 BLD 4 -1 FP BE Pri
!#1 N3478 P1214 BLD 5 -1 FP BE Pri
!#A N3477 N3478
!#1 N3479 P1214 BLD 6 -1 FP BE Pri
!#1 N3480 P1214 BLD 7 -1 FP BE Pri
!#1 N3481 P1215 LD 3 -1 Int BE Pri
!#1 N3482 P1213 LD 27 -1 Int BE Pri
!#1 N3483 P1214 BLD 4 -1 FP BE Pri
!#1 N3484 P1214 BLD 5 -1 FP BE Pri
!#A N3483 N3484
!#1 N3485 P1214 BLD 6 -1 FP BE Pri
!#1 N3486 P1214 BLD 7 -1 FP BE Pri
!#1 N3487 P1215 LD 3 -1 Int BE Pri
!#1 N3489 P1217 DWLD 22 -1 Int BE Pri
!#1 N3490 P1218 LD 11 -1 Int BE Pri
!#1 N3491 P1219 LD 26 -1 Int BE Pri
!#1 N3492 P1220 LD 1 -1 Int BE Pri
!#1 N3493 P1221 LD 17 -1 Int BE Pri
!#1 N3494 P1221 CAS 17 -1 N3493 0x80003b Int BE Pri
!#1 N3495 P1222 LD 23 -1 Int BE Pri
!#1 N3496 P1223 BLD 8 -1 FP BE Pri
!#1 N3497 P1223 BLD 9 -1 FP BE Pri
!#A N3496 N3497
!#1 N3498 P1223 BLD 10 -1 FP BE Pri
!#1 N3499 P1223 BLD 11 -1 FP BE Pri
!#1 N3500 P1224 LD 25 -1 Int BE Pri
!#1 N3501 P1225 DWLD 24 -1 Int BE Pri
!#1 N3502 P1225 DWLD 25 -1 Int BE Pri
!#A N3501 N3502
!#1 N3503 P1225 DWLD 24 -1 Int BE Pri
!#1 N3504 P1225 DWLD 25 -1 Int BE Pri
!#A N3503 N3504
!#1 N3505 P1226 BLD 28 -1 FP BE Pri
!#1 N3506 P1226 BLD 29 -1 FP BE Pri
!#A N3505 N3506
!#1 N3507 P1226 BLD 30 -1 FP BE Pri
!#1 N3508 P1226 BLD 31 -1 FP BE Pri
!#1 N3509 P1227 LD 14 -1 Int BE Pri
!#1 N3510 P1228 LD 28 -1 Int BE Pri
!#1 N3511 P1226 BLD 28 -1 FP BE Pri
!#1 N3512 P1226 BLD 29 -1 FP BE Pri
!#A N3511 N3512
!#1 N3513 P1226 BLD 30 -1 FP BE Pri
!#1 N3514 P1226 BLD 31 -1 FP BE Pri
!#1 N3515 P1227 LD 14 -1 Int BE Pri
!#1 N3516 P1228 LD 28 -1 Int BE Pri
!#1 N3517 P1229 LD 28 -1 Int BE Pri
!#1 N3518 P1230 DWLD 24 -1 Int BE Pri
!#1 N3519 P1230 DWLD 25 -1 Int BE Pri
!#A N3518 N3519
!#1 N3520 P1231 LD 26 -1 Int BE Pri
!#1 N3521 P1229 LD 28 -1 Int BE Pri
!#1 N3522 P1230 DWLD 24 -1 Int BE Pri
!#1 N3523 P1230 DWLD 25 -1 Int BE Pri
!#A N3522 N3523
!#1 N3524 P1231 LD 26 -1 Int BE Pri
!#1 N3525 P1232 DWLD 24 -1 Int BE Pri
!#1 N3526 P1232 DWLD 25 -1 Int BE Pri
!#A N3525 N3526
!#1 N3527 P1232 DWLD 24 -1 Int BE Pri
!#1 N3528 P1232 DWLD 25 -1 Int BE Pri
!#A N3527 N3528
!#1 N3529 P1233 LD 8 -1 FP BE Pri
!#1 N3530 P1234 BLD 8 -1 FP BE Pri
!#1 N3531 P1234 BLD 9 -1 FP BE Pri
!#A N3530 N3531
!#1 N3532 P1234 BLD 10 -1 FP BE Pri
!#1 N3533 P1234 BLD 11 -1 FP BE Pri
!#1 N3534 P1235 LD 31 -1 Int BE Pri
!#1 N3535 P1236 DWLD 7 -1 FP BE Pri
!#1 N3536 P1237 LD 3 -1 Int BE Pri
!#1 N3537 P1235 LD 31 -1 Int BE Pri
!#1 N3538 P1236 DWLD 7 -1 FP BE Pri
!#1 N3539 P1237 LD 3 -1 Int BE Pri
!#1 N3540 P1238 BLD 16 -1 FP BE Pri
!#1 N3541 P1238 BLD 17 -1 FP BE Pri
!#A N3540 N3541
!#1 N3542 P1238 BLD 18 -1 FP BE Pri
!#1 N3543 P1238 BLD 19 -1 FP BE Pri
!#1 N3544 P1239 LD 1 -1 Int BE Pri
!#1 N3545 P1240 LD 3 -1 Int BE Pri
!#1 N3546 P1238 BLD 16 -1 FP BE Pri
!#1 N3547 P1238 BLD 17 -1 FP BE Pri
!#A N3546 N3547
!#1 N3548 P1238 BLD 18 -1 FP BE Pri
!#1 N3549 P1238 BLD 19 -1 FP BE Pri
!#1 N3550 P1239 LD 1 -1 Int BE Pri
!#1 N3551 P1240 LD 3 -1 Int BE Pri
!#1 N3552 P1241 LD 17 -1 Int BE Pri
!#1 N3553 P1242 LD 28 -1 Int BE Pri
!#1 N3554 P1243 DWLD 24 -1 Int BE Pri
!#1 N3555 P1243 DWLD 25 -1 Int BE Pri
!#A N3554 N3555
!#1 N3556 P1244 DWLD 10 -1 Int BE Pri
!#1 N3557 P1245 LD 4 -1 Int BE Pri
!#1 N3558 P1246 LD 25 -1 Int BE Pri
!#1 N3559 P1247 LD 21 -1 Int BE Pri
!#1 N3560 P1246 LD 25 -1 Int BE Pri
!#1 N3561 P1247 LD 21 -1 Int BE Pri
!#1 N3562 P1248 DWLD 14 -1 Int BE Pri
!#1 N3563 P1249 BLD 0 -1 FP BE Pri
!#1 N3564 P1249 BLD 1 -1 FP BE Pri
!#A N3563 N3564
!#1 N3565 P1249 BLD 2 -1 FP BE Pri
!#1 N3566 P1249 BLD 3 -1 FP BE Pri
!#1 N3567 P1250 LD 25 -1 Int BE Pri
!#1 N3568 P1251 BLD 12 -1 FP BE Pri
!#1 N3569 P1251 BLD 13 -1 FP BE Pri
!#A N3568 N3569
!#1 N3570 P1251 BLD 14 -1 FP BE Pri
!#1 N3571 P1251 BLD 15 -1 FP BE Pri
!#1 N3572 P1252 DWLD 8 -1 Int BE Pri
!#1 N3573 P1252 DWLD 9 -1 Int BE Pri
!#A N3572 N3573
!#1 N3574 P1253 BLD 4 -1 FP BE Pri
!#1 N3575 P1253 BLD 5 -1 FP BE Pri
!#A N3574 N3575
!#1 N3576 P1253 BLD 6 -1 FP BE Pri
!#1 N3577 P1253 BLD 7 -1 FP BE Pri
!#1 N3578 P1252 DWLD 8 -1 Int BE Pri
!#1 N3579 P1252 DWLD 9 -1 Int BE Pri
!#A N3578 N3579
!#1 N3580 P1253 BLD 4 -1 FP BE Pri
!#1 N3581 P1253 BLD 5 -1 FP BE Pri
!#A N3580 N3581
!#1 N3582 P1253 BLD 6 -1 FP BE Pri
!#1 N3583 P1253 BLD 7 -1 FP BE Pri
!#1 N3584 P1254 LD 20 -1 Int BE Pri
!#1 N3585 P1254 CAS 20 -1 N3584 0x80003c Int BE Pri
!#1 N3586 P1255 DWLD 6 -1 Int LE Pri
!#1 N3587 P1256 LD 8 -1 Int BE Pri
!#1 N3588 P1255 DWLD 6 -1 Int LE Pri
!#1 N3589 P1256 LD 8 -1 Int BE Pri
!#1 N3590 P1257 DWLD 6 -1 Int BE Pri
!#1 N3591 P1258 BLD 0 -1 FP BE Pri
!#1 N3592 P1258 BLD 1 -1 FP BE Pri
!#A N3591 N3592
!#1 N3593 P1258 BLD 2 -1 FP BE Pri
!#1 N3594 P1258 BLD 3 -1 FP BE Pri
!#1 N3595 P1259 LD 19 -1 Int BE Pri
!#1 N3597 P1261 LD 29 -1 Int BE Pri
!#1 N3598 P1262 LD 20 -1 Int BE Pri
!#1 N3600 P1261 LD 29 -1 Int BE Pri
!#1 N3601 P1262 LD 20 -1 Int BE Pri
!#1 N3603 P1264 LD 2 -1 Int BE Pri
!#1 N3604 P1265 LD 0 -1 Int BE Pri
!#1 N3606 P1264 LD 2 -1 Int BE Pri
!#1 N3607 P1265 LD 0 -1 Int BE Pri
!#1 N3608 P1266 LD 11 -1 Int BE Pri
!#1 N3609 P1267 LD 3 -1 Int BE Pri
!#1 N3610 P1268 LD 14 -1 Int BE Pri
!#1 N3611 P1269 LD 22 -1 Int BE Pri
!#1 N3612 P1270 LD 7 -1 Int BE Pri
!#1 N3613 P1271 LD 30 -1 Int BE Pri
!#1 N3614 P1270 LD 7 -1 Int BE Pri
!#1 N3615 P1271 LD 30 -1 Int BE Pri
!#1 N3616 P1272 LD 27 -1 Int LE Pri
!#1 N3617 P1273 LD 4 -1 Int BE Pri
!#1 N3618 P1274 LD 6 -1 FP BE Pri
!#1 N3619 P1275 DWLD 27 -1 Int BE Pri
!#1 N3620 P1276 DWLD 14 -1 Int BE Pri
!#1 N3621 P1277 LD 18 -1 Int BE Pri
!#1 N3622 P1278 LD 13 -1 Int BE Pri
!#1 N3623 P1277 LD 18 -1 Int BE Pri
!#1 N3624 P1278 LD 13 -1 Int BE Pri
!#1 N3625 P1279 LD 11 -1 Int BE Pri
!#1 N3626 P1280 LD 19 -1 Int BE Pri
!#1 N3627 P1281 LD 1 -1 Int BE Pri
!#1 N3628 P1282 BLD 12 -1 FP BE Pri
!#1 N3629 P1282 BLD 13 -1 FP BE Pri
!#A N3628 N3629
!#1 N3630 P1282 BLD 14 -1 FP BE Pri
!#1 N3631 P1282 BLD 15 -1 FP BE Pri
!#1 N3632 P1283 LD 16 -1 Int BE Pri
!#1 N3633 P1281 LD 1 -1 Int BE Pri
!#1 N3634 P1282 BLD 12 -1 FP BE Pri
!#1 N3635 P1282 BLD 13 -1 FP BE Pri
!#A N3634 N3635
!#1 N3636 P1282 BLD 14 -1 FP BE Pri
!#1 N3637 P1282 BLD 15 -1 FP BE Pri
!#1 N3638 P1283 LD 16 -1 Int BE Pri
!#1 N3639 P1284 MEMBAR
!#1 N3640 P1284 MEMBAR
!#1 N3641 P1285 LD 18 -1 Int BE Pri
!#1 N3642 P1285 CAS 18 -1 N3641 0x80003d Int BE Pri
!#1 N3643 P1285 LD 18 -1 Int BE Pri
!#1 N3644 P1285 CAS 18 -1 N3643 0x80003e Int BE Pri
!#1 N3645 P1286 LD 16 -1 Int BE Pri
!#1 N3646 P1287 LD 16 -1 Int BE Pri
!#1 N3647 P1286 LD 16 -1 Int BE Pri
!#1 N3648 P1287 LD 16 -1 Int BE Pri
!#1 N3649 P1288 ST 14 0x80003f Int BE Pri
!#1 N3650 P1289 LD 7 -1 Int BE Pri
!#1 N3651 P1290 LD 22 -1 Int BE Pri
!#1 N3652 P1288 ST 14 0x800040 Int BE Pri
!#1 N3653 P1289 LD 7 -1 Int BE Pri
!#1 N3654 P1290 LD 22 -1 Int BE Pri
!#1 N3655 P1291 LD 11 -1 Int BE Pri
!#1 N3656 P1292 LD 15 -1 Int BE Pri
!#1 N3657 P1293 DWLD 16 -1 Int LE Pri
!#1 N3658 P1293 DWLD 17 -1 Int LE Pri
!#A N3657 N3658
!#1 N3659 P1294 BLD 8 -1 FP BE Pri
!#1 N3660 P1294 BLD 9 -1 FP BE Pri
!#A N3659 N3660
!#1 N3661 P1294 BLD 10 -1 FP BE Pri
!#1 N3662 P1294 BLD 11 -1 FP BE Pri
!#1 N3663 P1295 BLD 12 -1 FP BE Pri
!#1 N3664 P1295 BLD 13 -1 FP BE Pri
!#A N3663 N3664
!#1 N3665 P1295 BLD 14 -1 FP BE Pri
!#1 N3666 P1295 BLD 15 -1 FP BE Pri
!#1 N3667 P1296 DWLD 2 -1 Int BE Pri
!#1 N3668 P1297 LD 13 -1 Int BE Pri
!#1 N3669 P1298 BLD 12 -1 FP BE Pri
!#1 N3670 P1298 BLD 13 -1 FP BE Pri
!#A N3669 N3670
!#1 N3671 P1298 BLD 14 -1 FP BE Pri
!#1 N3672 P1298 BLD 15 -1 FP BE Pri
!#1 N3673 P1299 LD 3 -1 FP BE Pri
!#1 N3674 P1300 LD 30 -1 Int BE Pri
!#1 N3675 P1301 LD 30 -1 Int BE Pri
!#1 N3676 P1302 DWLD 22 -1 Int LE Pri
!#1 N3677 P1303 DWLD 14 -1 Int BE Pri
!#1 N3678 P1304 DWLD 0 -1 Int BE Pri
!#1 N3679 P1304 DWLD 1 -1 Int BE Pri
!#A N3678 N3679
!#1 N3680 P1305 BLD 0 -1 FP BE Pri
!#1 N3681 P1305 BLD 1 -1 FP BE Pri
!#A N3680 N3681
!#1 N3682 P1305 BLD 2 -1 FP BE Pri
!#1 N3683 P1305 BLD 3 -1 FP BE Pri
!#1 N3684 P1304 DWLD 0 -1 Int BE Pri
!#1 N3685 P1304 DWLD 1 -1 Int BE Pri
!#A N3684 N3685
!#1 N3686 P1305 BLD 0 -1 FP BE Pri
!#1 N3687 P1305 BLD 1 -1 FP BE Pri
!#A N3686 N3687
!#1 N3688 P1305 BLD 2 -1 FP BE Pri
!#1 N3689 P1305 BLD 3 -1 FP BE Pri
!#1 N3690 P1306 LD 12 -1 Int BE Pri
!#1 N3691 P1307 LD 21 -1 Int BE Pri
!#1 N3692 P1306 LD 12 -1 Int BE Pri
!#1 N3693 P1307 LD 21 -1 Int BE Pri
!#1 N3694 P1308 DWLD 28 -1 Int BE Pri
!#1 N3695 P1308 DWLD 29 -1 Int BE Pri
!#A N3694 N3695
!#1 N3696 P1308 DWLD 28 -1 Int BE Pri
!#1 N3697 P1308 DWLD 29 -1 Int BE Pri
!#A N3696 N3697
!#1 N3698 P1309 MEMBAR
!#2 N3699 P1310 DWLD 16 -1 Int LE Pri
!#2 N3700 P1310 DWLD 17 -1 Int LE Pri
!#A N3699 N3700
!#2 N3701 P1311 DWLD 28 -1 Int BE Pri
!#2 N3702 P1311 DWLD 29 -1 Int BE Pri
!#A N3701 N3702
!#2 N3703 P1310 DWLD 16 -1 Int LE Pri
!#2 N3704 P1310 DWLD 17 -1 Int LE Pri
!#A N3703 N3704
!#2 N3705 P1311 DWLD 28 -1 Int BE Pri
!#2 N3706 P1311 DWLD 29 -1 Int BE Pri
!#A N3705 N3706
!#2 N3707 P1312 BLD 16 -1 FP BE Pri
!#2 N3708 P1312 BLD 17 -1 FP BE Pri
!#A N3707 N3708
!#2 N3709 P1312 BLD 18 -1 FP BE Pri
!#2 N3710 P1312 BLD 19 -1 FP BE Pri
!#2 N3711 P1312 BLD 16 -1 FP BE Pri
!#2 N3712 P1312 BLD 17 -1 FP BE Pri
!#A N3711 N3712
!#2 N3713 P1312 BLD 18 -1 FP BE Pri
!#2 N3714 P1312 BLD 19 -1 FP BE Pri
!#2 N3715 P1313 LD 7 -1 Int BE Pri
!#2 N3716 P1314 LD 14 -1 Int BE Pri
!#2 N3717 P1313 LD 7 -1 Int BE Pri
!#2 N3718 P1314 LD 14 -1 Int BE Pri
!#2 N3719 P1315 DWLD 0 -1 Int BE Pri
!#2 N3720 P1315 DWLD 1 -1 Int BE Pri
!#A N3719 N3720
!#2 N3721 P1315 DWLD 0 -1 Int BE Pri
!#2 N3722 P1315 DWLD 1 -1 Int BE Pri
!#A N3721 N3722
!#2 N3723 P1316 BLD 8 -1 FP BE Pri
!#2 N3724 P1316 BLD 9 -1 FP BE Pri
!#A N3723 N3724
!#2 N3725 P1316 BLD 10 -1 FP BE Pri
!#2 N3726 P1316 BLD 11 -1 FP BE Pri
!#2 N3727 P1316 BLD 8 -1 FP BE Pri
!#2 N3728 P1316 BLD 9 -1 FP BE Pri
!#A N3727 N3728
!#2 N3729 P1316 BLD 10 -1 FP BE Pri
!#2 N3730 P1316 BLD 11 -1 FP BE Pri
!#2 N3731 P1317 DWLD 30 -1 Int BE Pri
!#2 N3732 P1318 LD 14 -1 Int BE Pri
!#2 N3733 P1317 DWLD 30 -1 Int BE Pri
!#2 N3734 P1318 LD 14 -1 Int BE Pri
!#2 N3735 P1319 DWLD 4 -1 Int BE Pri
!#2 N3736 P1319 DWLD 5 -1 Int BE Pri
!#A N3735 N3736
!#2 N3737 P1320 DWLD 12 -1 Int LE Pri
!#2 N3738 P1320 DWLD 13 -1 Int LE Pri
!#A N3737 N3738
!#2 N3739 P1321 LD 20 -1 Int BE Pri
!#2 N3740 P1322 DWLD 8 -1 Int BE Pri
!#2 N3741 P1322 DWLD 9 -1 Int BE Pri
!#A N3740 N3741
!#2 N3742 P1323 LD 7 -1 Int BE Pri
!#2 N3743 P1321 LD 20 -1 Int BE Pri
!#2 N3744 P1322 DWLD 8 -1 Int BE Pri
!#2 N3745 P1322 DWLD 9 -1 Int BE Pri
!#A N3744 N3745
!#2 N3746 P1323 LD 7 -1 Int BE Pri
!#2 N3747 P1324 DWLD 15 -1 Int LE Pri
!#2 N3748 P1325 LD 16 -1 Int BE Pri
!#2 N3749 P1324 DWLD 15 -1 Int LE Pri
!#2 N3750 P1325 LD 16 -1 Int BE Pri
!#2 N3751 P1326 BLD 12 -1 FP BE Pri
!#2 N3752 P1326 BLD 13 -1 FP BE Pri
!#A N3751 N3752
!#2 N3753 P1326 BLD 14 -1 FP BE Pri
!#2 N3754 P1326 BLD 15 -1 FP BE Pri
!#2 N3755 P1327 LD 31 -1 Int BE Pri
!#2 N3756 P1328 LD 14 -1 Int LE Pri
!#2 N3757 P1329 BLD 0 -1 FP BE Pri
!#2 N3758 P1329 BLD 1 -1 FP BE Pri
!#A N3757 N3758
!#2 N3759 P1329 BLD 2 -1 FP BE Pri
!#2 N3760 P1329 BLD 3 -1 FP BE Pri
!#2 N3761 P1330 LD 21 -1 Int BE Pri
!#2 N3762 P1331 LD 25 -1 Int BE Pri
!#2 N3763 P1329 BLD 0 -1 FP BE Pri
!#2 N3764 P1329 BLD 1 -1 FP BE Pri
!#A N3763 N3764
!#2 N3765 P1329 BLD 2 -1 FP BE Pri
!#2 N3766 P1329 BLD 3 -1 FP BE Pri
!#2 N3767 P1330 LD 21 -1 Int BE Pri
!#2 N3768 P1331 LD 25 -1 Int BE Pri
!#2 N3769 P1332 LD 24 -1 Int BE Pri
!#2 N3770 P1332 CAS 24 -1 N3769 0x1000001 Int BE Pri
!#2 N3771 P1333 BLD 8 -1 FP BE Pri
!#2 N3772 P1333 BLD 9 -1 FP BE Pri
!#A N3771 N3772
!#2 N3773 P1333 BLD 10 -1 FP BE Pri
!#2 N3774 P1333 BLD 11 -1 FP BE Pri
!#2 N3775 P1334 LD 20 -1 Int BE Pri
!#2 N3776 P1335 LD 28 -1 Int BE Pri
!#2 N3777 P1334 LD 20 -1 Int BE Pri
!#2 N3778 P1335 LD 28 -1 Int BE Pri
!#2 N3779 P1336 LD 4 -1 Int BE Pri
!#2 N3780 P1337 LD 30 -1 Int BE Pri
!#2 N3781 P1336 LD 4 -1 Int BE Pri
!#2 N3782 P1337 LD 30 -1 Int BE Pri
!#2 N3785 P1339 BSTC 28 0x40800001 FP BE Pri
!#2 N3786 P1339 BSTC 29 0x40800002 FP BE Pri
!#A N3785 N3786
!#2 N3787 P1339 BSTC 30 0x40800003 FP BE Pri
!#2 N3788 P1339 BSTC 31 0x40800004 FP BE Pri
!#2 N3789 P1340 ST 8 0x1000002 Int BE Pri
!#2 N3790 P1341 DWLD 19 -1 Int BE Pri
!#2 N3791 P1342 LD 16 -1 Int BE Pri
!#2 N3792 P1340 ST 8 0x1000003 Int BE Pri
!#2 N3793 P1341 DWLD 19 -1 Int BE Pri
!#2 N3794 P1342 LD 16 -1 Int BE Pri
!#2 N3795 P1343 DWLD 15 -1 Int BE Pri
!#2 N3796 P1344 LD 28 -1 Int BE Pri
!#2 N3797 P1345 DWLD 18 -1 FP BE Pri
!#2 N3798 P1346 LD 14 -1 Int BE Pri
!#2 N3799 P1347 LD 20 -1 Int BE Pri
!#2 N3800 P1345 DWLD 18 -1 FP BE Pri
!#2 N3801 P1346 LD 14 -1 Int BE Pri
!#2 N3802 P1347 LD 20 -1 Int BE Pri
!#2 N3803 P1348 BLD 24 -1 FP BE Pri
!#2 N3804 P1348 BLD 25 -1 FP BE Pri
!#A N3803 N3804
!#2 N3805 P1348 BLD 26 -1 FP BE Pri
!#2 N3806 P1348 BLD 27 -1 FP BE Pri
!#2 N3807 P1348 BLD 24 -1 FP BE Pri
!#2 N3808 P1348 BLD 25 -1 FP BE Pri
!#A N3807 N3808
!#2 N3809 P1348 BLD 26 -1 FP BE Pri
!#2 N3810 P1348 BLD 27 -1 FP BE Pri
!#2 N3811 P1349 DWLD 10 -1 Int BE Pri
!#2 N3812 P1350 LD 21 -1 Int BE Pri
!#2 N3813 P1351 SWAP 24 0xffffffff 0x1000004 Int BE Pri
!#2 N3814 P1352 LD 24 -1 Int BE Pri
!#2 N3815 P1353 SWAP 16 0xffffffff 0x1000005 Int BE Pri
!#2 N3816 P1354 LD 28 -1 Int BE Pri
!#2 N3817 P1355 BLD 8 -1 FP BE Pri
!#2 N3818 P1355 BLD 9 -1 FP BE Pri
!#A N3817 N3818
!#2 N3819 P1355 BLD 10 -1 FP BE Pri
!#2 N3820 P1355 BLD 11 -1 FP BE Pri
!#2 N3821 P1356 BLD 12 -1 FP BE Pri
!#2 N3822 P1356 BLD 13 -1 FP BE Pri
!#A N3821 N3822
!#2 N3823 P1356 BLD 14 -1 FP BE Pri
!#2 N3824 P1356 BLD 15 -1 FP BE Pri
!#2 N3825 P1355 BLD 8 -1 FP BE Pri
!#2 N3826 P1355 BLD 9 -1 FP BE Pri
!#A N3825 N3826
!#2 N3827 P1355 BLD 10 -1 FP BE Pri
!#2 N3828 P1355 BLD 11 -1 FP BE Pri
!#2 N3829 P1356 BLD 12 -1 FP BE Pri
!#2 N3830 P1356 BLD 13 -1 FP BE Pri
!#A N3829 N3830
!#2 N3831 P1356 BLD 14 -1 FP BE Pri
!#2 N3832 P1356 BLD 15 -1 FP BE Pri
!#2 N3833 P1357 BLD 16 -1 FP BE Pri
!#2 N3834 P1357 BLD 17 -1 FP BE Pri
!#A N3833 N3834
!#2 N3835 P1357 BLD 18 -1 FP BE Pri
!#2 N3836 P1357 BLD 19 -1 FP BE Pri
!#2 N3837 P1358 BLD 16 -1 FP BE Pri
!#2 N3838 P1358 BLD 17 -1 FP BE Pri
!#A N3837 N3838
!#2 N3839 P1358 BLD 18 -1 FP BE Pri
!#2 N3840 P1358 BLD 19 -1 FP BE Pri
!#2 N3841 P1357 BLD 16 -1 FP BE Pri
!#2 N3842 P1357 BLD 17 -1 FP BE Pri
!#A N3841 N3842
!#2 N3843 P1357 BLD 18 -1 FP BE Pri
!#2 N3844 P1357 BLD 19 -1 FP BE Pri
!#2 N3845 P1358 BLD 16 -1 FP BE Pri
!#2 N3846 P1358 BLD 17 -1 FP BE Pri
!#A N3845 N3846
!#2 N3847 P1358 BLD 18 -1 FP BE Pri
!#2 N3848 P1358 BLD 19 -1 FP BE Pri
!#2 N3849 P1359 BLD 28 -1 FP BE Pri
!#2 N3850 P1359 BLD 29 -1 FP BE Pri
!#A N3849 N3850
!#2 N3851 P1359 BLD 30 -1 FP BE Pri
!#2 N3852 P1359 BLD 31 -1 FP BE Pri
!#2 N3853 P1360 BLD 0 -1 FP BE Pri
!#2 N3854 P1360 BLD 1 -1 FP BE Pri
!#A N3853 N3854
!#2 N3855 P1360 BLD 2 -1 FP BE Pri
!#2 N3856 P1360 BLD 3 -1 FP BE Pri
!#2 N3857 P1359 BLD 28 -1 FP BE Pri
!#2 N3858 P1359 BLD 29 -1 FP BE Pri
!#A N3857 N3858
!#2 N3859 P1359 BLD 30 -1 FP BE Pri
!#2 N3860 P1359 BLD 31 -1 FP BE Pri
!#2 N3861 P1360 BLD 0 -1 FP BE Pri
!#2 N3862 P1360 BLD 1 -1 FP BE Pri
!#A N3861 N3862
!#2 N3863 P1360 BLD 2 -1 FP BE Pri
!#2 N3864 P1360 BLD 3 -1 FP BE Pri
!#2 N3865 P1361 LD 28 -1 Int LE Pri
!#2 N3866 P1362 LD 20 -1 Int BE Pri
!#2 N3867 P1363 DWLD 28 -1 Int BE Pri
!#2 N3868 P1363 DWLD 29 -1 Int BE Pri
!#A N3867 N3868
!#2 N3869 P1364 LD 4 -1 Int BE Pri
!#2 N3870 P1365 LD 5 -1 Int BE Pri
!#2 N3871 P1366 DWST 19 0x1000006 Int BE Pri
!#2 N3872 P1367 LD 3 -1 Int BE Pri
!#2 N3873 P1368 LD 30 -1 Int BE Pri
!#2 N3874 P1366 DWST 19 0x1000007 Int BE Pri
!#2 N3875 P1367 LD 3 -1 Int BE Pri
!#2 N3876 P1368 LD 30 -1 Int BE Pri
!#2 N3877 P1369 DWLD 14 -1 Int BE Pri
!#2 N3878 P1370 LD 27 -1 Int BE Pri
!#2 N3879 P1369 DWLD 14 -1 Int BE Pri
!#2 N3880 P1370 LD 27 -1 Int BE Pri
!#2 N3881 P1371 SWAP 1 0xffffffff 0x1000008 Int BE Pri
!#2 N3882 P1372 LD 16 -1 Int BE Pri
!#2 N3883 P1371 SWAP 1 0xffffffff 0x1000009 Int BE Pri
!#2 N3884 P1372 LD 16 -1 Int BE Pri
!#2 N3885 P1373 LD 11 -1 Int LE Pri
!#2 N3886 P1374 DWLD 28 -1 Int BE Pri
!#2 N3887 P1374 DWLD 29 -1 Int BE Pri
!#A N3886 N3887
!#2 N3888 P1375 LD 27 -1 Int BE Pri
!#2 N3889 P1376 DWLD 14 -1 Int BE Pri
!#2 N3890 P1377 LD 20 -1 Int LE Pri
!#2 N3891 P1376 DWLD 14 -1 Int BE Pri
!#2 N3892 P1377 LD 20 -1 Int LE Pri
!#2 N3893 P1378 DWLD 31 -1 Int BE Pri
!#2 N3894 P1379 LD 1 -1 Int LE Pri
!#2 N3895 P1378 DWLD 31 -1 Int BE Pri
!#2 N3896 P1379 LD 1 -1 Int LE Pri
!#2 N3897 P1380 DWLD 19 -1 Int BE Pri
!#2 N3898 P1381 DWLD 2 -1 Int BE Pri
!#2 N3899 P1380 DWLD 19 -1 Int BE Pri
!#2 N3900 P1381 DWLD 2 -1 Int BE Pri
!#2 N3901 P1382 LD 4 -1 Int BE Pri
!#2 N3902 P1383 DWLD 24 -1 Int BE Pri
!#2 N3903 P1383 DWLD 25 -1 Int BE Pri
!#A N3902 N3903
!#2 N3904 P1384 LD 21 -1 Int BE Pri
!#2 N3905 P1385 BLD 24 -1 FP BE Pri
!#2 N3906 P1385 BLD 25 -1 FP BE Pri
!#A N3905 N3906
!#2 N3907 P1385 BLD 26 -1 FP BE Pri
!#2 N3908 P1385 BLD 27 -1 FP BE Pri
!#2 N3909 P1385 BLD 24 -1 FP BE Pri
!#2 N3910 P1385 BLD 25 -1 FP BE Pri
!#A N3909 N3910
!#2 N3911 P1385 BLD 26 -1 FP BE Pri
!#2 N3912 P1385 BLD 27 -1 FP BE Pri
!#2 N3913 P1386 BLD 28 -1 FP BE Pri
!#2 N3914 P1386 BLD 29 -1 FP BE Pri
!#A N3913 N3914
!#2 N3915 P1386 BLD 30 -1 FP BE Pri
!#2 N3916 P1386 BLD 31 -1 FP BE Pri
!#2 N3917 P1386 BLD 28 -1 FP BE Pri
!#2 N3918 P1386 BLD 29 -1 FP BE Pri
!#A N3917 N3918
!#2 N3919 P1386 BLD 30 -1 FP BE Pri
!#2 N3920 P1386 BLD 31 -1 FP BE Pri
!#2 N3921 P1387 BLD 28 -1 FP BE Pri
!#2 N3922 P1387 BLD 29 -1 FP BE Pri
!#A N3921 N3922
!#2 N3923 P1387 BLD 30 -1 FP BE Pri
!#2 N3924 P1387 BLD 31 -1 FP BE Pri
!#2 N3925 P1387 BLD 28 -1 FP BE Pri
!#2 N3926 P1387 BLD 29 -1 FP BE Pri
!#A N3925 N3926
!#2 N3927 P1387 BLD 30 -1 FP BE Pri
!#2 N3928 P1387 BLD 31 -1 FP BE Pri
!#2 N3929 P1388 LD 8 -1 Int LE Pri
!#2 N3930 P1389 DWLD 28 -1 Int BE Pri
!#2 N3931 P1389 DWLD 29 -1 Int BE Pri
!#A N3930 N3931
!#2 N3932 P1390 LD 7 -1 Int BE Pri
!#2 N3933 P1391 LD 10 -1 Int BE Pri
!#2 N3934 P1392 BLD 8 -1 FP BE Pri
!#2 N3935 P1392 BLD 9 -1 FP BE Pri
!#A N3934 N3935
!#2 N3936 P1392 BLD 10 -1 FP BE Pri
!#2 N3937 P1392 BLD 11 -1 FP BE Pri
!#2 N3938 P1393 LD 5 -1 Int BE Pri
!#2 N3939 P1394 BLD 8 -1 FP BE Pri
!#2 N3940 P1394 BLD 9 -1 FP BE Pri
!#A N3939 N3940
!#2 N3941 P1394 BLD 10 -1 FP BE Pri
!#2 N3942 P1394 BLD 11 -1 FP BE Pri
!#2 N3943 P1394 BLD 8 -1 FP BE Pri
!#2 N3944 P1394 BLD 9 -1 FP BE Pri
!#A N3943 N3944
!#2 N3945 P1394 BLD 10 -1 FP BE Pri
!#2 N3946 P1394 BLD 11 -1 FP BE Pri
!#2 N3947 P1395 DWLD 6 -1 Int BE Pri
!#2 N3948 P1396 LD 27 -1 Int BE Pri
!#2 N3949 P1397 LD 7 -1 Int BE Pri
!#2 N3950 P1398 LD 31 -1 Int BE Pri
!#2 N3951 P1399 DWLD 15 -1,0x0 Int BE Pri
!#2 N3952 P1399 CASX 15 -1,0x0 N3951 0x100000a Int BE Pri
!#2 N3953 P1400 DWLD 3 -1 Int BE Pri
!#2 N3954 P1401 LD 6 -1 Int BE Pri
!#2 N3955 P1399 DWLD 15 -1,0x0 Int BE Pri
!#2 N3956 P1399 CASX 15 -1,0x0 N3955 0x100000b Int BE Pri
!#2 N3957 P1400 DWLD 3 -1 Int BE Pri
!#2 N3958 P1401 LD 6 -1 Int BE Pri
!#2 N3959 P1402 LD 31 -1 Int BE Pri
!#2 N3960 P1403 DWLD 0 -1 FP BE Pri
!#2 N3961 P1403 DWLD 1 -1 FP BE Pri
!#A N3960 N3961
!#2 N3962 P1404 LD 7 -1 Int BE Pri
!#2 N3963 P1402 LD 31 -1 Int BE Pri
!#2 N3964 P1403 DWLD 0 -1 FP BE Pri
!#2 N3965 P1403 DWLD 1 -1 FP BE Pri
!#A N3964 N3965
!#2 N3966 P1404 LD 7 -1 Int BE Pri
!#2 N3967 P1405 LD 8 -1 Int BE Pri
!#2 N3968 P1405 CAS 8 -1 N3967 0x100000c Int BE Pri
!#2 N3969 P1406 DWLD 31 -1 Int BE Pri
!#2 N3970 P1407 DWLD 20 -1 Int BE Pri
!#2 N3971 P1407 DWLD 21 -1 Int BE Pri
!#A N3970 N3971
!#2 N3972 P1408 LD 17 -1 Int BE Pri
!#2 N3973 P1406 DWLD 31 -1 Int BE Pri
!#2 N3974 P1407 DWLD 20 -1 Int BE Pri
!#2 N3975 P1407 DWLD 21 -1 Int BE Pri
!#A N3974 N3975
!#2 N3976 P1408 LD 17 -1 Int BE Pri
!#2 N3977 P1409 DWLD 4 -1 Int BE Pri
!#2 N3978 P1409 DWLD 5 -1 Int BE Pri
!#A N3977 N3978
!#2 N3979 P1410 BSTC 12 0x40800005 FP BE Pri
!#2 N3980 P1410 BSTC 13 0x40800006 FP BE Pri
!#A N3979 N3980
!#2 N3981 P1410 BSTC 14 0x40800007 FP BE Pri
!#2 N3982 P1410 BSTC 15 0x40800008 FP BE Pri
!#2 N3983 P1411 DWLD 28 -1 Int BE Pri
!#2 N3984 P1411 DWLD 29 -1 Int BE Pri
!#A N3983 N3984
!#2 N3985 P1411 CASX 28 -1 N3983 0x100000d Int BE Pri
!#2 N3986 P1411 CASX 29 -1 N3984 0x100000e Int BE Pri
!#A N3985 N3986
!#2 N3987 P1411 DWLD 28 -1 Int BE Pri
!#2 N3988 P1411 DWLD 29 -1 Int BE Pri
!#A N3987 N3988
!#2 N3989 P1411 CASX 28 -1 N3987 0x100000f Int BE Pri
!#2 N3990 P1411 CASX 29 -1 N3988 0x1000010 Int BE Pri
!#A N3989 N3990
!#2 N3991 P1412 SWAP 26 0xffffffff 0x1000011 Int BE Pri
!#2 N3992 P1413 LD 10 -1 Int BE Pri
!#2 N3993 P1414 DWLD 20 -1 Int BE Pri
!#2 N3994 P1414 DWLD 21 -1 Int BE Pri
!#A N3993 N3994
!#2 N3995 P1415 BLD 0 -1 FP BE Pri
!#2 N3996 P1415 BLD 1 -1 FP BE Pri
!#A N3995 N3996
!#2 N3997 P1415 BLD 2 -1 FP BE Pri
!#2 N3998 P1415 BLD 3 -1 FP BE Pri
!#2 N3999 P1414 DWLD 20 -1 Int BE Pri
!#2 N4000 P1414 DWLD 21 -1 Int BE Pri
!#A N3999 N4000
!#2 N4001 P1415 BLD 0 -1 FP BE Pri
!#2 N4002 P1415 BLD 1 -1 FP BE Pri
!#A N4001 N4002
!#2 N4003 P1415 BLD 2 -1 FP BE Pri
!#2 N4004 P1415 BLD 3 -1 FP BE Pri
!#2 N4005 P1416 LD 29 -1 FP BE Pri
!#2 N4006 P1416 LD 29 -1 FP BE Pri
!#2 N4007 P1417 BLD 12 -1 FP BE Pri
!#2 N4008 P1417 BLD 13 -1 FP BE Pri
!#A N4007 N4008
!#2 N4009 P1417 BLD 14 -1 FP BE Pri
!#2 N4010 P1417 BLD 15 -1 FP BE Pri
!#2 N4011 P1418 LD 19 -1 Int BE Pri
!#2 N4012 P1419 LD 17 -1 Int BE Pri
!#2 N4013 P1420 DWLD 14 -1 Int BE Pri
!#2 N4014 P1421 LD 22 -1 Int BE Pri
!#2 N4015 P1422 LD 8 -1 Int BE Pri
!#2 N4016 P1423 LD 27 -1 Int BE Pri
!#2 N4017 P1422 LD 8 -1 Int BE Pri
!#2 N4018 P1423 LD 27 -1 Int BE Pri
!#2 N4019 P1424 LD 8 -1 Int BE Pri
!#2 N4020 P1425 LD 10 -1 Int BE Pri
!#2 N4021 P1426 DWLD 19 -1 Int BE Pri
!#2 N4022 P1427 LD 6 -1 Int BE Pri
!#2 N4023 P1426 DWLD 19 -1 Int BE Pri
!#2 N4024 P1427 LD 6 -1 Int BE Pri
!#2 N4025 P1428 BLD 4 -1 FP BE Pri
!#2 N4026 P1428 BLD 5 -1 FP BE Pri
!#A N4025 N4026
!#2 N4027 P1428 BLD 6 -1 FP BE Pri
!#2 N4028 P1428 BLD 7 -1 FP BE Pri
!#2 N4029 P1429 BSTC 20 0x40800009 FP BE Pri
!#2 N4030 P1429 BSTC 21 0x4080000a FP BE Pri
!#A N4029 N4030
!#2 N4031 P1429 BSTC 22 0x4080000b FP BE Pri
!#2 N4032 P1429 BSTC 23 0x4080000c FP BE Pri
!#2 N4033 P1428 BLD 4 -1 FP BE Pri
!#2 N4034 P1428 BLD 5 -1 FP BE Pri
!#A N4033 N4034
!#2 N4035 P1428 BLD 6 -1 FP BE Pri
!#2 N4036 P1428 BLD 7 -1 FP BE Pri
!#2 N4037 P1429 BSTC 20 0x4080000d FP BE Pri
!#2 N4038 P1429 BSTC 21 0x4080000e FP BE Pri
!#A N4037 N4038
!#2 N4039 P1429 BSTC 22 0x4080000f FP BE Pri
!#2 N4040 P1429 BSTC 23 0x40800010 FP BE Pri
!#2 N4041 P1430 LD 23 -1 Int BE Pri
!#2 N4042 P1431 LD 26 -1 Int BE Pri
!#2 N4043 P1430 LD 23 -1 Int BE Pri
!#2 N4044 P1431 LD 26 -1 Int BE Pri
!#2 N4045 P1432 BSTC 24 0x40800011 FP BE Pri
!#2 N4046 P1432 BSTC 25 0x40800012 FP BE Pri
!#A N4045 N4046
!#2 N4047 P1432 BSTC 26 0x40800013 FP BE Pri
!#2 N4048 P1432 BSTC 27 0x40800014 FP BE Pri
!#2 N4049 P1433 BLD 8 -1 FP BE Pri
!#2 N4050 P1433 BLD 9 -1 FP BE Pri
!#A N4049 N4050
!#2 N4051 P1433 BLD 10 -1 FP BE Pri
!#2 N4052 P1433 BLD 11 -1 FP BE Pri
!#2 N4053 P1434 DWLD 22 -1 Int BE Pri
!#2 N4054 P1435 BLD 0 -1 FP BE Pri
!#2 N4055 P1435 BLD 1 -1 FP BE Pri
!#A N4054 N4055
!#2 N4056 P1435 BLD 2 -1 FP BE Pri
!#2 N4057 P1435 BLD 3 -1 FP BE Pri
!#2 N4058 P1436 LD 6 -1 Int BE Pri
!#2 N4059 P1437 BLD 24 -1 FP BE Pri
!#2 N4060 P1437 BLD 25 -1 FP BE Pri
!#A N4059 N4060
!#2 N4061 P1437 BLD 26 -1 FP BE Pri
!#2 N4062 P1437 BLD 27 -1 FP BE Pri
!#2 N4063 P1438 LD 2 -1 Int LE Pri
!#2 N4064 P1439 LD 27 -1 Int BE Pri
!#2 N4065 P1438 LD 2 -1 Int LE Pri
!#2 N4066 P1439 LD 27 -1 Int BE Pri
!#2 N4067 P1440 DWST 16 0x40800015 FP BE Pri
!#2 N4068 P1440 DWST 17 0x40800016 FP BE Pri
!#A N4067 N4068
!#2 N4069 P1441 DWLD 11 -1 Int BE Pri
!#2 N4070 P1442 LD 26 -1 Int BE Pri
!#2 N4071 P1440 DWST 16 0x40800017 FP BE Pri
!#2 N4072 P1440 DWST 17 0x40800018 FP BE Pri
!#A N4071 N4072
!#2 N4073 P1441 DWLD 11 -1 Int BE Pri
!#2 N4074 P1442 LD 26 -1 Int BE Pri
!#2 N4075 P1443 LD 9 -1 Int BE Pri
!#2 N4076 P1444 LD 16 -1 Int BE Pri
!#2 N4077 P1445 DWLD 20 -1 FP BE Pri
!#2 N4078 P1445 DWLD 21 -1 FP BE Pri
!#A N4077 N4078
!#2 N4079 P1445 DWLD 20 -1 FP BE Pri
!#2 N4080 P1445 DWLD 21 -1 FP BE Pri
!#A N4079 N4080
!#2 N4081 P1446 BLD 0 -1 FP BE Pri
!#2 N4082 P1446 BLD 1 -1 FP BE Pri
!#A N4081 N4082
!#2 N4083 P1446 BLD 2 -1 FP BE Pri
!#2 N4084 P1446 BLD 3 -1 FP BE Pri
!#2 N4085 P1447 LD 27 -1 Int BE Pri
!#2 N4086 P1447 CAS 27 -1 N4085 0x1000012 Int BE Pri
!#2 N4087 P1446 BLD 0 -1 FP BE Pri
!#2 N4088 P1446 BLD 1 -1 FP BE Pri
!#A N4087 N4088
!#2 N4089 P1446 BLD 2 -1 FP BE Pri
!#2 N4090 P1446 BLD 3 -1 FP BE Pri
!#2 N4091 P1447 LD 27 -1 Int BE Pri
!#2 N4092 P1447 CAS 27 -1 N4091 0x1000013 Int BE Pri
!#2 N4095 P1449 BLD 24 -1 FP BE Pri
!#2 N4096 P1449 BLD 25 -1 FP BE Pri
!#A N4095 N4096
!#2 N4097 P1449 BLD 26 -1 FP BE Pri
!#2 N4098 P1449 BLD 27 -1 FP BE Pri
!#2 N4099 P1450 LD 20 -1 Int BE Pri
!#2 N4100 P1451 LD 17 -1 Int BE Pri
!#2 N4101 P1452 BLD 0 -1 FP BE Pri
!#2 N4102 P1452 BLD 1 -1 FP BE Pri
!#A N4101 N4102
!#2 N4103 P1452 BLD 2 -1 FP BE Pri
!#2 N4104 P1452 BLD 3 -1 FP BE Pri
!#2 N4105 P1453 BLD 12 -1 FP BE Pri
!#2 N4106 P1453 BLD 13 -1 FP BE Pri
!#A N4105 N4106
!#2 N4107 P1453 BLD 14 -1 FP BE Pri
!#2 N4108 P1453 BLD 15 -1 FP BE Pri
!#2 N4109 P1454 LD 28 -1 Int BE Pri
!#2 N4110 P1455 LD 29 -1 Int BE Pri
!#2 N4111 P1456 LD 11 -1 Int BE Pri
!#2 N4112 P1457 LD 12 -1 Int BE Pri
!#2 N4113 P1456 LD 11 -1 Int BE Pri
!#2 N4114 P1457 LD 12 -1 Int BE Pri
!#2 N4115 P1458 BLD 24 -1 FP BE Pri
!#2 N4116 P1458 BLD 25 -1 FP BE Pri
!#A N4115 N4116
!#2 N4117 P1458 BLD 26 -1 FP BE Pri
!#2 N4118 P1458 BLD 27 -1 FP BE Pri
!#2 N4119 P1458 BLD 24 -1 FP BE Pri
!#2 N4120 P1458 BLD 25 -1 FP BE Pri
!#A N4119 N4120
!#2 N4121 P1458 BLD 26 -1 FP BE Pri
!#2 N4122 P1458 BLD 27 -1 FP BE Pri
!#2 N4123 P1459 DWLD 19 -1 Int BE Pri
!#2 N4124 P1460 LD 0 -1 Int BE Pri
!#2 N4125 P1461 LD 20 -1 FP BE Pri
!#2 N4126 P1462 BSTC 20 0x40800019 FP BE Pri
!#2 N4127 P1462 BSTC 21 0x4080001a FP BE Pri
!#A N4126 N4127
!#2 N4128 P1462 BSTC 22 0x4080001b FP BE Pri
!#2 N4129 P1462 BSTC 23 0x4080001c FP BE Pri
!#2 N4130 P1463 BLD 24 -1 FP BE Pri
!#2 N4131 P1463 BLD 25 -1 FP BE Pri
!#A N4130 N4131
!#2 N4132 P1463 BLD 26 -1 FP BE Pri
!#2 N4133 P1463 BLD 27 -1 FP BE Pri
!#2 N4134 P1464 BLD 28 -1 FP BE Pri
!#2 N4135 P1464 BLD 29 -1 FP BE Pri
!#A N4134 N4135
!#2 N4136 P1464 BLD 30 -1 FP BE Pri
!#2 N4137 P1464 BLD 31 -1 FP BE Pri
!#2 N4138 P1463 BLD 24 -1 FP BE Pri
!#2 N4139 P1463 BLD 25 -1 FP BE Pri
!#A N4138 N4139
!#2 N4140 P1463 BLD 26 -1 FP BE Pri
!#2 N4141 P1463 BLD 27 -1 FP BE Pri
!#2 N4142 P1464 BLD 28 -1 FP BE Pri
!#2 N4143 P1464 BLD 29 -1 FP BE Pri
!#A N4142 N4143
!#2 N4144 P1464 BLD 30 -1 FP BE Pri
!#2 N4145 P1464 BLD 31 -1 FP BE Pri
!#2 N4146 P1465 BLD 28 -1 FP BE Pri
!#2 N4147 P1465 BLD 29 -1 FP BE Pri
!#A N4146 N4147
!#2 N4148 P1465 BLD 30 -1 FP BE Pri
!#2 N4149 P1465 BLD 31 -1 FP BE Pri
!#2 N4150 P1466 BLD 0 -1 FP BE Pri
!#2 N4151 P1466 BLD 1 -1 FP BE Pri
!#A N4150 N4151
!#2 N4152 P1466 BLD 2 -1 FP BE Pri
!#2 N4153 P1466 BLD 3 -1 FP BE Pri
!#2 N4154 P1465 BLD 28 -1 FP BE Pri
!#2 N4155 P1465 BLD 29 -1 FP BE Pri
!#A N4154 N4155
!#2 N4156 P1465 BLD 30 -1 FP BE Pri
!#2 N4157 P1465 BLD 31 -1 FP BE Pri
!#2 N4158 P1466 BLD 0 -1 FP BE Pri
!#2 N4159 P1466 BLD 1 -1 FP BE Pri
!#A N4158 N4159
!#2 N4160 P1466 BLD 2 -1 FP BE Pri
!#2 N4161 P1466 BLD 3 -1 FP BE Pri
!#2 N4162 P1467 LD 6 -1 FP BE Pri
!#2 N4163 P1468 DWLD 27 -1,0x0 Int BE Pri
!#2 N4164 P1468 CASX 27 -1,0x0 N4163 0x1000014 Int BE Pri
!#2 N4165 P1467 LD 6 -1 FP BE Pri
!#2 N4166 P1468 DWLD 27 -1,0x0 Int BE Pri
!#2 N4167 P1468 CASX 27 -1,0x0 N4166 0x1000015 Int BE Pri
!#2 N4168 P1469 LD 15 -1 Int BE Pri
!#2 N4169 P1470 LD 4 -1 Int BE Pri
!#2 N4170 P1469 LD 15 -1 Int BE Pri
!#2 N4171 P1470 LD 4 -1 Int BE Pri
!#2 N4172 P1471 DWLD 3 -1 Int BE Pri
!#2 N4173 P1472 LD 20 -1 Int BE Pri
!#2 N4174 P1471 DWLD 3 -1 Int BE Pri
!#2 N4175 P1472 LD 20 -1 Int BE Pri
!#2 N4176 P1473 DWLD 16 -1 Int BE Pri
!#2 N4177 P1473 DWLD 17 -1 Int BE Pri
!#A N4176 N4177
!#2 N4178 P1474 DWLD 11 -1 Int BE Pri
!#2 N4179 P1475 LD 22 -1 Int BE Pri
!#2 N4180 P1473 DWLD 16 -1 Int BE Pri
!#2 N4181 P1473 DWLD 17 -1 Int BE Pri
!#A N4180 N4181
!#2 N4182 P1474 DWLD 11 -1 Int BE Pri
!#2 N4183 P1475 LD 22 -1 Int BE Pri
!#2 N4184 P1476 DWLD 18 -1 Int BE Pri
!#2 N4185 P1477 LD 11 -1 FP BE Pri
!#2 N4186 P1478 LD 4 -1 Int BE Pri
!#2 N4187 P1479 DWLD 0 -1 Int BE Pri
!#2 N4188 P1479 DWLD 1 -1 Int BE Pri
!#A N4187 N4188
!#2 N4189 P1480 DWLD 23 -1 Int BE Pri
!#2 N4190 P1481 LD 3 -1 Int BE Pri
!#2 N4191 P1480 DWLD 23 -1 Int BE Pri
!#2 N4192 P1481 LD 3 -1 Int BE Pri
!#2 N4193 P1482 BLD 28 -1 FP BE Pri
!#2 N4194 P1482 BLD 29 -1 FP BE Pri
!#A N4193 N4194
!#2 N4195 P1482 BLD 30 -1 FP BE Pri
!#2 N4196 P1482 BLD 31 -1 FP BE Pri
!#2 N4197 P1482 BLD 28 -1 FP BE Pri
!#2 N4198 P1482 BLD 29 -1 FP BE Pri
!#A N4197 N4198
!#2 N4199 P1482 BLD 30 -1 FP BE Pri
!#2 N4200 P1482 BLD 31 -1 FP BE Pri
!#2 N4201 P1483 LD 16 -1 Int LE Pri
!#2 N4202 P1484 LD 13 -1 Int BE Pri
!#2 N4203 P1485 DWLD 4 -1 Int BE Pri
!#2 N4204 P1485 DWLD 5 -1 Int BE Pri
!#A N4203 N4204
!#2 N4206 P1485 DWLD 4 -1 Int BE Pri
!#2 N4207 P1485 DWLD 5 -1 Int BE Pri
!#A N4206 N4207
!#2 N4209 P1487 DWLD 4 -1 Int BE Pri
!#2 N4210 P1487 DWLD 5 -1 Int BE Pri
!#A N4209 N4210
!#2 N4211 P1488 DWLD 27 -1 FP BE Pri
!#2 N4212 P1487 DWLD 4 -1 Int BE Pri
!#2 N4213 P1487 DWLD 5 -1 Int BE Pri
!#A N4212 N4213
!#2 N4214 P1488 DWLD 27 -1 FP BE Pri
!#2 N4215 P1489 LD 17 -1 Int BE Pri
!#2 N4216 P1490 LD 23 -1 Int LE Pri
!#2 N4217 P1489 LD 17 -1 Int BE Pri
!#2 N4218 P1490 LD 23 -1 Int LE Pri
!#2 N4219 P1491 LD 31 -1 FP BE Pri
!#2 N4220 P1492 BLD 20 -1 FP BE Pri
!#2 N4221 P1492 BLD 21 -1 FP BE Pri
!#A N4220 N4221
!#2 N4222 P1492 BLD 22 -1 FP BE Pri
!#2 N4223 P1492 BLD 23 -1 FP BE Pri
!#2 N4225 P1494 DWLD 22 -1 Int BE Pri
!#2 N4226 P1495 LD 18 -1 Int BE Pri
!#2 N4227 P1494 DWLD 22 -1 Int BE Pri
!#2 N4228 P1495 LD 18 -1 Int BE Pri
!#2 N4229 P1496 BLD 20 -1 FP BE Pri
!#2 N4230 P1496 BLD 21 -1 FP BE Pri
!#A N4229 N4230
!#2 N4231 P1496 BLD 22 -1 FP BE Pri
!#2 N4232 P1496 BLD 23 -1 FP BE Pri
!#2 N4233 P1496 BLD 20 -1 FP BE Pri
!#2 N4234 P1496 BLD 21 -1 FP BE Pri
!#A N4233 N4234
!#2 N4235 P1496 BLD 22 -1 FP BE Pri
!#2 N4236 P1496 BLD 23 -1 FP BE Pri
!#2 N4237 P1497 BLD 24 -1 FP BE Pri
!#2 N4238 P1497 BLD 25 -1 FP BE Pri
!#A N4237 N4238
!#2 N4239 P1497 BLD 26 -1 FP BE Pri
!#2 N4240 P1497 BLD 27 -1 FP BE Pri
!#2 N4241 P1498 LD 23 -1 Int BE Pri
!#2 N4242 P1498 CAS 23 -1 N4241 0x1000016 Int BE Pri
!#2 N4243 P1499 LD 28 -1 Int BE Pri
!#2 N4244 P1500 LD 5 -1 Int BE Pri
!#2 N4245 P1499 LD 28 -1 Int BE Pri
!#2 N4246 P1500 LD 5 -1 Int BE Pri
!#2 N4247 P1501 DWLD 7 -1 Int BE Pri
!#2 N4248 P1502 LD 3 -1 Int BE Pri
!#2 N4249 P1503 LD 14 -1 Int LE Pri
!#2 N4250 P1504 LD 9 -1 Int BE Pri
!#2 N4251 P1505 BLD 24 -1 FP BE Pri
!#2 N4252 P1505 BLD 25 -1 FP BE Pri
!#A N4251 N4252
!#2 N4253 P1505 BLD 26 -1 FP BE Pri
!#2 N4254 P1505 BLD 27 -1 FP BE Pri
!#2 N4255 P1505 BLD 24 -1 FP BE Pri
!#2 N4256 P1505 BLD 25 -1 FP BE Pri
!#A N4255 N4256
!#2 N4257 P1505 BLD 26 -1 FP BE Pri
!#2 N4258 P1505 BLD 27 -1 FP BE Pri
!#2 N4259 P1506 DWLD 28 -1 Int BE Pri
!#2 N4260 P1506 DWLD 29 -1 Int BE Pri
!#A N4259 N4260
!#2 N4261 P1507 DWLD 12 -1 Int BE Pri
!#2 N4262 P1507 DWLD 13 -1 Int BE Pri
!#A N4261 N4262
!#2 N4263 P1506 DWLD 28 -1 Int BE Pri
!#2 N4264 P1506 DWLD 29 -1 Int BE Pri
!#A N4263 N4264
!#2 N4265 P1507 DWLD 12 -1 Int BE Pri
!#2 N4266 P1507 DWLD 13 -1 Int BE Pri
!#A N4265 N4266
!#2 N4267 P1508 LD 17 -1 FP BE Pri
!#2 N4268 P1508 LD 17 -1 FP BE Pri
!#2 N4269 P1509 DWLD 2 -1 Int BE Pri
!#2 N4270 P1510 DWLD 7 -1 Int BE Pri
!#2 N4271 P1511 BLD 0 -1 FP BE Pri
!#2 N4272 P1511 BLD 1 -1 FP BE Pri
!#A N4271 N4272
!#2 N4273 P1511 BLD 2 -1 FP BE Pri
!#2 N4274 P1511 BLD 3 -1 FP BE Pri
!#2 N4275 P1511 BLD 0 -1 FP BE Pri
!#2 N4276 P1511 BLD 1 -1 FP BE Pri
!#A N4275 N4276
!#2 N4277 P1511 BLD 2 -1 FP BE Pri
!#2 N4278 P1511 BLD 3 -1 FP BE Pri
!#2 N4279 P1512 DWLD 31 -1 FP BE Pri
!#2 N4280 P1512 DWLD 31 -1 FP BE Pri
!#2 N4281 P1513 LD 16 -1 Int BE Pri
!#2 N4282 P1514 MEMBAR
!#2 N4283 P1515 LD 7 -1 Int BE Pri
!#2 N4284 P1516 LD 27 -1 FP BE Pri
!#2 N4285 P1517 LD 8 -1 Int BE Pri
!#2 N4286 P1518 LD 25 -1 Int BE Pri
!#2 N4287 P1517 LD 8 -1 Int BE Pri
!#2 N4288 P1518 LD 25 -1 Int BE Pri
!#2 N4289 P1519 BLD 4 -1 FP BE Pri
!#2 N4290 P1519 BLD 5 -1 FP BE Pri
!#A N4289 N4290
!#2 N4291 P1519 BLD 6 -1 FP BE Pri
!#2 N4292 P1519 BLD 7 -1 FP BE Pri
!#2 N4293 P1519 BLD 4 -1 FP BE Pri
!#2 N4294 P1519 BLD 5 -1 FP BE Pri
!#A N4293 N4294
!#2 N4295 P1519 BLD 6 -1 FP BE Pri
!#2 N4296 P1519 BLD 7 -1 FP BE Pri
!#2 N4297 P1520 LD 20 -1 Int BE Pri
!#2 N4298 P1521 LD 0 -1 Int BE Pri
!#2 N4299 P1520 LD 20 -1 Int BE Pri
!#2 N4300 P1521 LD 0 -1 Int BE Pri
!#2 N4301 P1522 LD 6 -1 Int BE Pri
!#2 N4302 P1523 LD 23 -1 Int BE Pri
!#2 N4303 P1524 LD 30 -1 Int BE Pri
!#2 N4304 P1525 LD 10 -1 Int BE Pri
!#2 N4305 P1526 BLD 12 -1 FP BE Pri
!#2 N4306 P1526 BLD 13 -1 FP BE Pri
!#A N4305 N4306
!#2 N4307 P1526 BLD 14 -1 FP BE Pri
!#2 N4308 P1526 BLD 15 -1 FP BE Pri
!#2 N4309 P1527 DWLD 3 -1 Int LE Pri
!#2 N4311 P1529 LD 28 -1 Int BE Pri
!#2 N4312 P1527 DWLD 3 -1 Int LE Pri
!#2 N4314 P1529 LD 28 -1 Int BE Pri
!#2 N4315 P1530 LD 24 -1 FP BE Pri
!#2 N4316 P1531 LD 30 -1 Int BE Pri
!#2 N4317 P1532 LD 17 -1 Int BE Pri
!#2 N4318 P1530 LD 24 -1 FP BE Pri
!#2 N4319 P1531 LD 30 -1 Int BE Pri
!#2 N4320 P1532 LD 17 -1 Int BE Pri
!#2 N4321 P1533 BLD 0 -1 FP BE Pri
!#2 N4322 P1533 BLD 1 -1 FP BE Pri
!#A N4321 N4322
!#2 N4323 P1533 BLD 2 -1 FP BE Pri
!#2 N4324 P1533 BLD 3 -1 FP BE Pri
!#2 N4325 P1534 DWLD 26 -1 Int BE Pri
!#2 N4326 P1535 BLD 12 -1 FP BE Pri
!#2 N4327 P1535 BLD 13 -1 FP BE Pri
!#A N4326 N4327
!#2 N4328 P1535 BLD 14 -1 FP BE Pri
!#2 N4329 P1535 BLD 15 -1 FP BE Pri
!#2 N4330 P1536 LD 16 -1 Int BE Pri
!#2 N4331 P1534 DWLD 26 -1 Int BE Pri
!#2 N4332 P1535 BLD 12 -1 FP BE Pri
!#2 N4333 P1535 BLD 13 -1 FP BE Pri
!#A N4332 N4333
!#2 N4334 P1535 BLD 14 -1 FP BE Pri
!#2 N4335 P1535 BLD 15 -1 FP BE Pri
!#2 N4336 P1536 LD 16 -1 Int BE Pri
!#2 N4337 P1537 LD 12 -1 Int BE Pri
!#2 N4338 P1538 LD 29 -1 Int BE Pri
!#2 N4339 P1539 DWLD 18 -1 Int BE Pri
!#2 N4340 P1540 LD 29 -1 Int BE Pri
!#2 N4341 P1539 DWLD 18 -1 Int BE Pri
!#2 N4342 P1540 LD 29 -1 Int BE Pri
!#2 N4343 P1541 BLD 0 -1 FP BE Pri
!#2 N4344 P1541 BLD 1 -1 FP BE Pri
!#A N4343 N4344
!#2 N4345 P1541 BLD 2 -1 FP BE Pri
!#2 N4346 P1541 BLD 3 -1 FP BE Pri
!#2 N4347 P1542 BLD 24 -1 FP BE Pri
!#2 N4348 P1542 BLD 25 -1 FP BE Pri
!#A N4347 N4348
!#2 N4349 P1542 BLD 26 -1 FP BE Pri
!#2 N4350 P1542 BLD 27 -1 FP BE Pri
!#2 N4351 P1541 BLD 0 -1 FP BE Pri
!#2 N4352 P1541 BLD 1 -1 FP BE Pri
!#A N4351 N4352
!#2 N4353 P1541 BLD 2 -1 FP BE Pri
!#2 N4354 P1541 BLD 3 -1 FP BE Pri
!#2 N4355 P1542 BLD 24 -1 FP BE Pri
!#2 N4356 P1542 BLD 25 -1 FP BE Pri
!#A N4355 N4356
!#2 N4357 P1542 BLD 26 -1 FP BE Pri
!#2 N4358 P1542 BLD 27 -1 FP BE Pri
!#2 N4359 P1543 LD 0 -1 Int BE Pri
!#2 N4360 P1544 DWLD 8 -1 Int BE Pri
!#2 N4361 P1544 DWLD 9 -1 Int BE Pri
!#A N4360 N4361
!#2 N4362 P1545 LD 10 -1 Int BE Pri
!#2 N4363 P1543 LD 0 -1 Int BE Pri
!#2 N4364 P1544 DWLD 8 -1 Int BE Pri
!#2 N4365 P1544 DWLD 9 -1 Int BE Pri
!#A N4364 N4365
!#2 N4366 P1545 LD 10 -1 Int BE Pri
!#2 N4367 P1546 LD 16 -1 Int BE Pri
!#2 N4368 P1547 LD 11 -1 Int BE Pri
!#2 N4369 P1548 BLD 12 -1 FP BE Pri
!#2 N4370 P1548 BLD 13 -1 FP BE Pri
!#A N4369 N4370
!#2 N4371 P1548 BLD 14 -1 FP BE Pri
!#2 N4372 P1548 BLD 15 -1 FP BE Pri
!#2 N4373 P1549 BLD 4 -1 FP BE Pri
!#2 N4374 P1549 BLD 5 -1 FP BE Pri
!#A N4373 N4374
!#2 N4375 P1549 BLD 6 -1 FP BE Pri
!#2 N4376 P1549 BLD 7 -1 FP BE Pri
!#2 N4377 P1548 BLD 12 -1 FP BE Pri
!#2 N4378 P1548 BLD 13 -1 FP BE Pri
!#A N4377 N4378
!#2 N4379 P1548 BLD 14 -1 FP BE Pri
!#2 N4380 P1548 BLD 15 -1 FP BE Pri
!#2 N4381 P1549 BLD 4 -1 FP BE Pri
!#2 N4382 P1549 BLD 5 -1 FP BE Pri
!#A N4381 N4382
!#2 N4383 P1549 BLD 6 -1 FP BE Pri
!#2 N4384 P1549 BLD 7 -1 FP BE Pri
!#2 N4385 P1550 BLD 4 -1 FP BE Pri
!#2 N4386 P1550 BLD 5 -1 FP BE Pri
!#A N4385 N4386
!#2 N4387 P1550 BLD 6 -1 FP BE Pri
!#2 N4388 P1550 BLD 7 -1 FP BE Pri
!#2 N4389 P1551 LD 20 -1 Int BE Pri
!#2 N4390 P1552 LD 5 -1 Int BE Pri
!#2 N4391 P1553 BLD 20 -1 FP BE Pri
!#2 N4392 P1553 BLD 21 -1 FP BE Pri
!#A N4391 N4392
!#2 N4393 P1553 BLD 22 -1 FP BE Pri
!#2 N4394 P1553 BLD 23 -1 FP BE Pri
!#2 N4395 P1554 LD 30 -1 FP BE Pri
!#2 N4396 P1554 LD 30 -1 FP BE Pri
!#2 N4397 P1555 DWLD 14 -1 Int BE Pri
!#2 N4398 P1556 BLD 4 -1 FP BE Pri
!#2 N4399 P1556 BLD 5 -1 FP BE Pri
!#A N4398 N4399
!#2 N4400 P1556 BLD 6 -1 FP BE Pri
!#2 N4401 P1556 BLD 7 -1 FP BE Pri
!#2 N4402 P1557 LD 5 -1 Int BE Pri
!#2 N4403 P1555 DWLD 14 -1 Int BE Pri
!#2 N4404 P1556 BLD 4 -1 FP BE Pri
!#2 N4405 P1556 BLD 5 -1 FP BE Pri
!#A N4404 N4405
!#2 N4406 P1556 BLD 6 -1 FP BE Pri
!#2 N4407 P1556 BLD 7 -1 FP BE Pri
!#2 N4408 P1557 LD 5 -1 Int BE Pri
!#2 N4409 P1558 ST 8 0x1000017 Int BE Pri
!#2 N4410 P1559 LD 25 -1 FP BE Pri
!#2 N4411 P1560 ST 1 0x1000018 Int BE Pri
!#2 N4412 P1561 DWLD 23 -1 FP BE Pri
!#2 N4413 P1562 DWLD 4 -1 Int LE Pri
!#2 N4414 P1562 DWLD 5 -1 Int LE Pri
!#A N4413 N4414
!#2 N4415 P1562 CASX 4 -1 N4413 0x1000019 Int LE Pri
!#2 N4416 P1562 CASX 5 -1 N4414 0x100001a Int LE Pri
!#A N4415 N4416
!#2 N4417 P1563 LD 30 -1 Int BE Pri
!#2 N4418 P1564 LD 10 -1 Int BE Pri
!#2 N4419 P1565 LD 21 -1 Int BE Pri
!#2 N4420 P1566 LD 29 -1 Int BE Pri
!#2 N4421 P1565 LD 21 -1 Int BE Pri
!#2 N4422 P1566 LD 29 -1 Int BE Pri
!#2 N4423 P1567 BLD 0 -1 FP BE Pri
!#2 N4424 P1567 BLD 1 -1 FP BE Pri
!#A N4423 N4424
!#2 N4425 P1567 BLD 2 -1 FP BE Pri
!#2 N4426 P1567 BLD 3 -1 FP BE Pri
!#2 N4427 P1568 LD 19 -1 Int BE Pri
!#2 N4428 P1569 BLD 0 -1 FP BE Pri
!#2 N4429 P1569 BLD 1 -1 FP BE Pri
!#A N4428 N4429
!#2 N4430 P1569 BLD 2 -1 FP BE Pri
!#2 N4431 P1569 BLD 3 -1 FP BE Pri
!#2 N4432 P1570 LD 31 -1 Int BE Pri
!#2 N4433 P1568 LD 19 -1 Int BE Pri
!#2 N4434 P1569 BLD 0 -1 FP BE Pri
!#2 N4435 P1569 BLD 1 -1 FP BE Pri
!#A N4434 N4435
!#2 N4436 P1569 BLD 2 -1 FP BE Pri
!#2 N4437 P1569 BLD 3 -1 FP BE Pri
!#2 N4438 P1570 LD 31 -1 Int BE Pri
!#2 N4439 P1571 LD 14 -1 Int BE Pri
!#2 N4440 P1572 LD 1 -1 Int LE Pri
!#2 N4441 P1573 DWLD 19 -1 Int BE Pri
!#2 N4442 P1574 BLD 8 -1 FP BE Pri
!#2 N4443 P1574 BLD 9 -1 FP BE Pri
!#A N4442 N4443
!#2 N4444 P1574 BLD 10 -1 FP BE Pri
!#2 N4445 P1574 BLD 11 -1 FP BE Pri
!#2 N4446 P1575 LD 11 -1 Int BE Pri
!#2 N4447 P1576 LD 27 -1 Int BE Pri
!#2 N4448 P1577 DWLD 28 -1 Int BE Pri
!#2 N4449 P1577 DWLD 29 -1 Int BE Pri
!#A N4448 N4449
!#2 N4450 P1578 LD 15 -1 Int BE Pri
!#2 N4451 P1579 DWLD 26 -1 Int BE Pri
!#2 N4452 P1580 DWLD 11 -1 Int BE Pri
!#2 N4453 P1581 LD 28 -1 Int BE Pri
!#2 N4454 P1582 DWST 12 0x100001b Int BE Pri
!#2 N4455 P1582 DWST 13 0x100001c Int BE Pri
!#A N4454 N4455
!#2 N4456 P1583 LD 17 -1 Int BE Pri
!#2 N4457 P1581 LD 28 -1 Int BE Pri
!#2 N4458 P1582 DWST 12 0x100001d Int BE Pri
!#2 N4459 P1582 DWST 13 0x100001e Int BE Pri
!#A N4458 N4459
!#2 N4460 P1583 LD 17 -1 Int BE Pri
!#2 N4461 P1584 LD 13 -1 FP BE Pri
!#2 N4462 P1584 LD 13 -1 FP BE Pri
!#2 N4463 P1585 BLD 24 -1 FP BE Pri
!#2 N4464 P1585 BLD 25 -1 FP BE Pri
!#A N4463 N4464
!#2 N4465 P1585 BLD 26 -1 FP BE Pri
!#2 N4466 P1585 BLD 27 -1 FP BE Pri
!#2 N4467 P1585 BLD 24 -1 FP BE Pri
!#2 N4468 P1585 BLD 25 -1 FP BE Pri
!#A N4467 N4468
!#2 N4469 P1585 BLD 26 -1 FP BE Pri
!#2 N4470 P1585 BLD 27 -1 FP BE Pri
!#2 N4471 P1586 BLD 8 -1 FP BE Pri
!#2 N4472 P1586 BLD 9 -1 FP BE Pri
!#A N4471 N4472
!#2 N4473 P1586 BLD 10 -1 FP BE Pri
!#2 N4474 P1586 BLD 11 -1 FP BE Pri
!#2 N4475 P1587 DWLD 24 -1 Int BE Pri
!#2 N4476 P1587 DWLD 25 -1 Int BE Pri
!#A N4475 N4476
!#2 N4477 P1588 DWLD 4 -1 Int LE Pri
!#2 N4478 P1588 DWLD 5 -1 Int LE Pri
!#A N4477 N4478
!#2 N4479 P1589 DWLD 16 -1 Int BE Pri
!#2 N4480 P1589 DWLD 17 -1 Int BE Pri
!#A N4479 N4480
!#2 N4481 P1590 LD 6 -1 Int BE Pri
!#2 N4482 P1591 LD 6 -1 Int BE Pri
!#2 N4483 P1592 ST 28 0x100001f Int BE Pri
!#2 N4484 P1593 ST 14 0x4080001d FP BE Pri
!#2 N4485 P1594 LD 5 -1 Int BE Pri
!#2 N4486 P1595 LD 15 -1 Int BE Pri
!#2 N4487 P1594 LD 5 -1 Int BE Pri
!#2 N4488 P1595 LD 15 -1 Int BE Pri
!#2 N4489 P1596 LD 27 -1 Int BE Pri
!#2 N4490 P1597 LD 25 -1 Int BE Pri
!#2 N4491 P1598 LD 9 -1 Int BE Pri
!#2 N4492 P1599 LD 6 -1 Int BE Pri
!#2 N4493 P1598 LD 9 -1 Int BE Pri
!#2 N4494 P1599 LD 6 -1 Int BE Pri
!#2 N4495 P1600 DWLD 20 -1 Int BE Pri
!#2 N4496 P1600 DWLD 21 -1 Int BE Pri
!#A N4495 N4496
!#2 N4497 P1601 BLD 20 -1 FP BE Pri
!#2 N4498 P1601 BLD 21 -1 FP BE Pri
!#A N4497 N4498
!#2 N4499 P1601 BLD 22 -1 FP BE Pri
!#2 N4500 P1601 BLD 23 -1 FP BE Pri
!#2 N4501 P1601 BLD 20 -1 FP BE Pri
!#2 N4502 P1601 BLD 21 -1 FP BE Pri
!#A N4501 N4502
!#2 N4503 P1601 BLD 22 -1 FP BE Pri
!#2 N4504 P1601 BLD 23 -1 FP BE Pri
!#2 N4506 P1603 DWLD 28 -1 Int BE Pri
!#2 N4507 P1603 DWLD 29 -1 Int BE Pri
!#A N4506 N4507
!#2 N4508 P1604 ST 14 0x1000020 Int BE Pri
!#2 N4509 P1605 LD 18 -1 Int BE Pri
!#2 N4510 P1606 LD 9 -1 Int BE Pri
!#2 N4511 P1607 ST 7 0x1000021 Int BE Pri
!#2 N4512 P1607 ST 7 0x1000022 Int BE Pri
!#2 N4513 P1608 LD 14 -1 Int BE Pri
!#2 N4514 P1609 BLD 20 -1 FP BE Pri
!#2 N4515 P1609 BLD 21 -1 FP BE Pri
!#A N4514 N4515
!#2 N4516 P1609 BLD 22 -1 FP BE Pri
!#2 N4517 P1609 BLD 23 -1 FP BE Pri
!#2 N4518 P1610 LD 15 -1 Int BE Pri
!#2 N4519 P1611 DWLD 10 -1 Int BE Pri
!#2 N4520 P1612 ST 4 0x1000023 Int BE Pri
!#2 N4521 P1613 LD 20 -1 Int BE Pri
!#2 N4522 P1614 LD 25 -1 Int BE Pri
!#2 N4523 P1615 BST 24 0x4080001e FP BE Pri
!#2 N4524 P1615 BST 25 0x4080001f FP BE Pri
!#A N4523 N4524
!#2 N4525 P1615 BST 26 0x40800020 FP BE Pri
!#2 N4526 P1615 BST 27 0x40800021 FP BE Pri
!#2 N4527 P1616 LD 7 -1 Int BE Pri
!#2 N4528 P1614 LD 25 -1 Int BE Pri
!#2 N4529 P1615 BST 24 0x40800022 FP BE Pri
!#2 N4530 P1615 BST 25 0x40800023 FP BE Pri
!#A N4529 N4530
!#2 N4531 P1615 BST 26 0x40800024 FP BE Pri
!#2 N4532 P1615 BST 27 0x40800025 FP BE Pri
!#2 N4533 P1616 LD 7 -1 Int BE Pri
!#2 N4534 P1617 DWLD 7 -1 Int BE Pri
!#2 N4535 P1618 DWLD 27 -1 Int BE Pri
!#2 N4536 P1619 DWLD 15 -1 Int BE Pri
!#2 N4537 P1620 LD 31 -1 Int BE Pri
!#2 N4538 P1619 DWLD 15 -1 Int BE Pri
!#2 N4539 P1620 LD 31 -1 Int BE Pri
!#2 N4540 P1621 LD 19 -1 Int BE Pri
!#2 N4541 P1622 LD 7 -1 Int BE Pri
!#2 N4542 P1621 LD 19 -1 Int BE Pri
!#2 N4543 P1622 LD 7 -1 Int BE Pri
!#2 N4544 P1623 DWLD 7 -1 Int BE Pri
!#2 N4545 P1624 LD 8 -1 Int BE Pri
!#2 N4546 P1623 DWLD 7 -1 Int BE Pri
!#2 N4547 P1624 LD 8 -1 Int BE Pri
!#2 N4548 P1625 DWLD 28 -1 FP BE Pri
!#2 N4549 P1625 DWLD 29 -1 FP BE Pri
!#A N4548 N4549
!#2 N4550 P1626 DWLD 14 -1 Int BE Pri
!#2 N4551 P1627 LD 16 -1 Int LE Pri
!#2 N4552 P1625 DWLD 28 -1 FP BE Pri
!#2 N4553 P1625 DWLD 29 -1 FP BE Pri
!#A N4552 N4553
!#2 N4554 P1626 DWLD 14 -1 Int BE Pri
!#2 N4555 P1627 LD 16 -1 Int LE Pri
!#2 N4556 P1628 BLD 4 -1 FP BE Pri
!#2 N4557 P1628 BLD 5 -1 FP BE Pri
!#A N4556 N4557
!#2 N4558 P1628 BLD 6 -1 FP BE Pri
!#2 N4559 P1628 BLD 7 -1 FP BE Pri
!#2 N4560 P1629 LD 11 -1 Int BE Pri
!#2 N4561 P1630 LD 12 -1 Int BE Pri
!#2 N4562 P1629 LD 11 -1 Int BE Pri
!#2 N4563 P1630 LD 12 -1 Int BE Pri
!#2 N4564 P1631 BLD 28 -1 FP BE Pri
!#2 N4565 P1631 BLD 29 -1 FP BE Pri
!#A N4564 N4565
!#2 N4566 P1631 BLD 30 -1 FP BE Pri
!#2 N4567 P1631 BLD 31 -1 FP BE Pri
!#2 N4568 P1632 BLD 16 -1 FP BE Pri
!#2 N4569 P1632 BLD 17 -1 FP BE Pri
!#A N4568 N4569
!#2 N4570 P1632 BLD 18 -1 FP BE Pri
!#2 N4571 P1632 BLD 19 -1 FP BE Pri
!#2 N4572 P1633 LD 23 -1 Int BE Pri
!#2 N4573 P1634 LD 21 -1 Int BE Pri
!#2 N4574 P1635 BLD 0 -1 FP BE Pri
!#2 N4575 P1635 BLD 1 -1 FP BE Pri
!#A N4574 N4575
!#2 N4576 P1635 BLD 2 -1 FP BE Pri
!#2 N4577 P1635 BLD 3 -1 FP BE Pri
!#2 N4578 P1636 BLD 20 -1 FP BE Pri
!#2 N4579 P1636 BLD 21 -1 FP BE Pri
!#A N4578 N4579
!#2 N4580 P1636 BLD 22 -1 FP BE Pri
!#2 N4581 P1636 BLD 23 -1 FP BE Pri
!#2 N4582 P1637 BLD 12 -1 FP BE Pri
!#2 N4583 P1637 BLD 13 -1 FP BE Pri
!#A N4582 N4583
!#2 N4584 P1637 BLD 14 -1 FP BE Pri
!#2 N4585 P1637 BLD 15 -1 FP BE Pri
!#2 N4587 P1639 LD 18 -1 Int BE Pri
!#2 N4588 P1640 BLD 4 -1 FP BE Pri
!#2 N4589 P1640 BLD 5 -1 FP BE Pri
!#A N4588 N4589
!#2 N4590 P1640 BLD 6 -1 FP BE Pri
!#2 N4591 P1640 BLD 7 -1 FP BE Pri
!#2 N4592 P1641 LD 29 -1 Int BE Pri
!#2 N4593 P1642 BLD 4 -1 FP BE Pri
!#2 N4594 P1642 BLD 5 -1 FP BE Pri
!#A N4593 N4594
!#2 N4595 P1642 BLD 6 -1 FP BE Pri
!#2 N4596 P1642 BLD 7 -1 FP BE Pri
!#2 N4597 P1643 LD 31 -1 Int BE Pri
!#2 N4598 P1644 BLD 20 -1 FP BE Pri
!#2 N4599 P1644 BLD 21 -1 FP BE Pri
!#A N4598 N4599
!#2 N4600 P1644 BLD 22 -1 FP BE Pri
!#2 N4601 P1644 BLD 23 -1 FP BE Pri
!#2 N4602 P1645 LD 5 -1 Int BE Pri
!#2 N4603 P1646 BLD 12 -1 FP BE Pri
!#2 N4604 P1646 BLD 13 -1 FP BE Pri
!#A N4603 N4604
!#2 N4605 P1646 BLD 14 -1 FP BE Pri
!#2 N4606 P1646 BLD 15 -1 FP BE Pri
!#2 N4607 P1647 BLD 8 -1 FP BE Pri
!#2 N4608 P1647 BLD 9 -1 FP BE Pri
!#A N4607 N4608
!#2 N4609 P1647 BLD 10 -1 FP BE Pri
!#2 N4610 P1647 BLD 11 -1 FP BE Pri
!#2 N4611 P1647 BLD 8 -1 FP BE Pri
!#2 N4612 P1647 BLD 9 -1 FP BE Pri
!#A N4611 N4612
!#2 N4613 P1647 BLD 10 -1 FP BE Pri
!#2 N4614 P1647 BLD 11 -1 FP BE Pri
!#2 N4615 P1648 BLD 4 -1 FP BE Pri
!#2 N4616 P1648 BLD 5 -1 FP BE Pri
!#A N4615 N4616
!#2 N4617 P1648 BLD 6 -1 FP BE Pri
!#2 N4618 P1648 BLD 7 -1 FP BE Pri
!#2 N4619 P1649 DWLD 18 -1 Int BE Pri
!#2 N4620 P1650 LD 23 -1 Int BE Pri
!#2 N4621 P1648 BLD 4 -1 FP BE Pri
!#2 N4622 P1648 BLD 5 -1 FP BE Pri
!#A N4621 N4622
!#2 N4623 P1648 BLD 6 -1 FP BE Pri
!#2 N4624 P1648 BLD 7 -1 FP BE Pri
!#2 N4625 P1649 DWLD 18 -1 Int BE Pri
!#2 N4626 P1650 LD 23 -1 Int BE Pri
!#2 N4627 P1651 DWLD 20 -1 Int BE Pri
!#2 N4628 P1651 DWLD 21 -1 Int BE Pri
!#A N4627 N4628
!#2 N4629 P1652 LD 21 -1 Int LE Pri
!#2 N4630 P1653 LD 16 -1 Int BE Pri
!#2 N4631 P1651 DWLD 20 -1 Int BE Pri
!#2 N4632 P1651 DWLD 21 -1 Int BE Pri
!#A N4631 N4632
!#2 N4633 P1652 LD 21 -1 Int LE Pri
!#2 N4634 P1653 LD 16 -1 Int BE Pri
!#2 N4635 P1654 DWLD 22 -1 Int BE Pri
!#2 N4636 P1655 LD 20 -1 Int BE Pri
!#2 N4637 P1656 LD 24 -1 Int BE Pri
!#2 N4638 P1657 LD 16 -1 Int BE Pri
!#2 N4639 P1658 DWLD 20 -1 Int BE Pri
!#2 N4640 P1658 DWLD 21 -1 Int BE Pri
!#A N4639 N4640
!#2 N4641 P1659 LD 2 -1 Int BE Pri
!#2 N4642 P1660 LD 31 -1 Int LE Pri
!#2 N4643 P1661 BLD 24 -1 FP BE Pri
!#2 N4644 P1661 BLD 25 -1 FP BE Pri
!#A N4643 N4644
!#2 N4645 P1661 BLD 26 -1 FP BE Pri
!#2 N4646 P1661 BLD 27 -1 FP BE Pri
!#2 N4647 P1662 LD 9 -1 FP BE Pri
!#2 N4648 P1663 LD 28 -1 Int BE Pri
!#2 N4649 P1664 LD 9 -1 Int BE Pri
!#2 N4650 P1663 LD 28 -1 Int BE Pri
!#2 N4651 P1664 LD 9 -1 Int BE Pri
!#2 N4652 P1665 LD 17 -1 Int BE Pri
!#2 N4653 P1666 LD 15 -1 Int BE Pri
!#2 N4654 P1665 LD 17 -1 Int BE Pri
!#2 N4655 P1666 LD 15 -1 Int BE Pri
!#2 N4656 P1667 BLD 28 -1 FP BE Pri
!#2 N4657 P1667 BLD 29 -1 FP BE Pri
!#A N4656 N4657
!#2 N4658 P1667 BLD 30 -1 FP BE Pri
!#2 N4659 P1667 BLD 31 -1 FP BE Pri
!#2 N4660 P1668 BLD 12 -1 FP BE Pri
!#2 N4661 P1668 BLD 13 -1 FP BE Pri
!#A N4660 N4661
!#2 N4662 P1668 BLD 14 -1 FP BE Pri
!#2 N4663 P1668 BLD 15 -1 FP BE Pri
!#2 N4664 P1668 BLD 12 -1 FP BE Pri
!#2 N4665 P1668 BLD 13 -1 FP BE Pri
!#A N4664 N4665
!#2 N4666 P1668 BLD 14 -1 FP BE Pri
!#2 N4667 P1668 BLD 15 -1 FP BE Pri
!#2 N4668 P1669 LD 27 -1 Int BE Pri
!#2 N4669 P1670 DWLD 8 -1 FP BE Pri
!#2 N4670 P1670 DWLD 9 -1 FP BE Pri
!#A N4669 N4670
!#2 N4671 P1671 LD 18 -1 Int BE Pri
!#2 N4672 P1672 LD 3 -1 Int BE Pri
!#2 N4673 P1673 DWLD 3 -1 Int BE Pri
!#2 N4674 P1672 LD 3 -1 Int BE Pri
!#2 N4675 P1673 DWLD 3 -1 Int BE Pri
!#2 N4676 P1674 BLD 20 -1 FP BE Pri
!#2 N4677 P1674 BLD 21 -1 FP BE Pri
!#A N4676 N4677
!#2 N4678 P1674 BLD 22 -1 FP BE Pri
!#2 N4679 P1674 BLD 23 -1 FP BE Pri
!#2 N4680 P1675 BLD 16 -1 FP BE Pri
!#2 N4681 P1675 BLD 17 -1 FP BE Pri
!#A N4680 N4681
!#2 N4682 P1675 BLD 18 -1 FP BE Pri
!#2 N4683 P1675 BLD 19 -1 FP BE Pri
!#2 N4684 P1674 BLD 20 -1 FP BE Pri
!#2 N4685 P1674 BLD 21 -1 FP BE Pri
!#A N4684 N4685
!#2 N4686 P1674 BLD 22 -1 FP BE Pri
!#2 N4687 P1674 BLD 23 -1 FP BE Pri
!#2 N4688 P1675 BLD 16 -1 FP BE Pri
!#2 N4689 P1675 BLD 17 -1 FP BE Pri
!#A N4688 N4689
!#2 N4690 P1675 BLD 18 -1 FP BE Pri
!#2 N4691 P1675 BLD 19 -1 FP BE Pri
!#2 N4692 P1676 DWLD 0 -1 Int BE Pri
!#2 N4693 P1676 DWLD 1 -1 Int BE Pri
!#A N4692 N4693
!#2 N4694 P1677 BLD 16 -1 FP BE Pri
!#2 N4695 P1677 BLD 17 -1 FP BE Pri
!#A N4694 N4695
!#2 N4696 P1677 BLD 18 -1 FP BE Pri
!#2 N4697 P1677 BLD 19 -1 FP BE Pri
!#2 N4698 P1676 DWLD 0 -1 Int BE Pri
!#2 N4699 P1676 DWLD 1 -1 Int BE Pri
!#A N4698 N4699
!#2 N4700 P1677 BLD 16 -1 FP BE Pri
!#2 N4701 P1677 BLD 17 -1 FP BE Pri
!#A N4700 N4701
!#2 N4702 P1677 BLD 18 -1 FP BE Pri
!#2 N4703 P1677 BLD 19 -1 FP BE Pri
!#2 N4704 P1678 BLD 28 -1 FP BE Pri
!#2 N4705 P1678 BLD 29 -1 FP BE Pri
!#A N4704 N4705
!#2 N4706 P1678 BLD 30 -1 FP BE Pri
!#2 N4707 P1678 BLD 31 -1 FP BE Pri
!#2 N4708 P1679 LD 16 -1 FP BE Pri
!#2 N4709 P1680 BLD 24 -1 FP BE Pri
!#2 N4710 P1680 BLD 25 -1 FP BE Pri
!#A N4709 N4710
!#2 N4711 P1680 BLD 26 -1 FP BE Pri
!#2 N4712 P1680 BLD 27 -1 FP BE Pri
!#2 N4713 P1681 LD 24 -1 Int BE Pri
!#2 N4714 P1681 CAS 24 -1 N4713 0x1000024 Int BE Pri
!#2 N4715 P1682 BLD 28 -1 FP BE Pri
!#2 N4716 P1682 BLD 29 -1 FP BE Pri
!#A N4715 N4716
!#2 N4717 P1682 BLD 30 -1 FP BE Pri
!#2 N4718 P1682 BLD 31 -1 FP BE Pri
!#2 N4719 P1683 BLD 4 -1 FP BE Pri
!#2 N4720 P1683 BLD 5 -1 FP BE Pri
!#A N4719 N4720
!#2 N4721 P1683 BLD 6 -1 FP BE Pri
!#2 N4722 P1683 BLD 7 -1 FP BE Pri
!#2 N4723 P1682 BLD 28 -1 FP BE Pri
!#2 N4724 P1682 BLD 29 -1 FP BE Pri
!#A N4723 N4724
!#2 N4725 P1682 BLD 30 -1 FP BE Pri
!#2 N4726 P1682 BLD 31 -1 FP BE Pri
!#2 N4727 P1683 BLD 4 -1 FP BE Pri
!#2 N4728 P1683 BLD 5 -1 FP BE Pri
!#A N4727 N4728
!#2 N4729 P1683 BLD 6 -1 FP BE Pri
!#2 N4730 P1683 BLD 7 -1 FP BE Pri
!#2 N4731 P1684 BST 12 0x40800026 FP BE Pri
!#2 N4732 P1684 BST 13 0x40800027 FP BE Pri
!#A N4731 N4732
!#2 N4733 P1684 BST 14 0x40800028 FP BE Pri
!#2 N4734 P1684 BST 15 0x40800029 FP BE Pri
!#2 N4735 P1685 BLD 20 -1 FP BE Pri
!#2 N4736 P1685 BLD 21 -1 FP BE Pri
!#A N4735 N4736
!#2 N4737 P1685 BLD 22 -1 FP BE Pri
!#2 N4738 P1685 BLD 23 -1 FP BE Pri
!#2 N4739 P1684 BST 12 0x4080002a FP BE Pri
!#2 N4740 P1684 BST 13 0x4080002b FP BE Pri
!#A N4739 N4740
!#2 N4741 P1684 BST 14 0x4080002c FP BE Pri
!#2 N4742 P1684 BST 15 0x4080002d FP BE Pri
!#2 N4743 P1685 BLD 20 -1 FP BE Pri
!#2 N4744 P1685 BLD 21 -1 FP BE Pri
!#A N4743 N4744
!#2 N4745 P1685 BLD 22 -1 FP BE Pri
!#2 N4746 P1685 BLD 23 -1 FP BE Pri
!#2 N4747 P1686 BLD 28 -1 FP BE Pri
!#2 N4748 P1686 BLD 29 -1 FP BE Pri
!#A N4747 N4748
!#2 N4749 P1686 BLD 30 -1 FP BE Pri
!#2 N4750 P1686 BLD 31 -1 FP BE Pri
!#2 N4751 P1687 DWST 16 0x1000025 Int BE Pri
!#2 N4752 P1687 DWST 17 0x1000026 Int BE Pri
!#A N4751 N4752
!#2 N4753 P1688 DWLD 26 -1 Int BE Pri
!#2 N4754 P1689 LD 31 -1 Int BE Pri
!#2 N4755 P1690 DWLD 12 -1 Int BE Pri
!#2 N4756 P1690 DWLD 13 -1 Int BE Pri
!#A N4755 N4756
!#2 N4757 P1691 LD 27 -1 Int BE Pri
!#2 N4758 P1692 LD 11 -1 Int BE Pri
!#2 N4759 P1691 LD 27 -1 Int BE Pri
!#2 N4760 P1692 LD 11 -1 Int BE Pri
!#2 N4761 P1693 ST 12 0x1000027 Int BE Pri
!#2 N4762 P1694 BST 0 0x4080002e FP BE Pri
!#2 N4763 P1694 BST 1 0x4080002f FP BE Pri
!#A N4762 N4763
!#2 N4764 P1694 BST 2 0x40800030 FP BE Pri
!#2 N4765 P1694 BST 3 0x40800031 FP BE Pri
!#2 N4766 P1695 LD 6 -1 Int BE Pri
!#2 N4767 P1696 LD 11 -1 Int BE Pri
!#2 N4768 P1694 BST 0 0x40800032 FP BE Pri
!#2 N4769 P1694 BST 1 0x40800033 FP BE Pri
!#A N4768 N4769
!#2 N4770 P1694 BST 2 0x40800034 FP BE Pri
!#2 N4771 P1694 BST 3 0x40800035 FP BE Pri
!#2 N4772 P1695 LD 6 -1 Int BE Pri
!#2 N4773 P1696 LD 11 -1 Int BE Pri
!#2 N4774 P1697 DWLD 10 -1 Int BE Pri
!#2 N4775 P1698 LD 6 -1 Int BE Pri
!#2 N4776 P1697 DWLD 10 -1 Int BE Pri
!#2 N4777 P1698 LD 6 -1 Int BE Pri
!#2 N4778 P1699 LD 7 -1 Int BE Pri
!#2 N4779 P1700 LD 10 -1 Int BE Pri
!#2 N4780 P1701 BLD 0 -1 FP BE Pri
!#2 N4781 P1701 BLD 1 -1 FP BE Pri
!#A N4780 N4781
!#2 N4782 P1701 BLD 2 -1 FP BE Pri
!#2 N4783 P1701 BLD 3 -1 FP BE Pri
!#2 N4784 P1702 DWLD 12 -1 Int BE Pri
!#2 N4785 P1702 DWLD 13 -1 Int BE Pri
!#A N4784 N4785
!#2 N4786 P1701 BLD 0 -1 FP BE Pri
!#2 N4787 P1701 BLD 1 -1 FP BE Pri
!#A N4786 N4787
!#2 N4788 P1701 BLD 2 -1 FP BE Pri
!#2 N4789 P1701 BLD 3 -1 FP BE Pri
!#2 N4790 P1702 DWLD 12 -1 Int BE Pri
!#2 N4791 P1702 DWLD 13 -1 Int BE Pri
!#A N4790 N4791
!#2 N4792 P1703 LD 6 -1 Int BE Pri
!#2 N4793 P1704 LD 22 -1 Int BE Pri
!#2 N4794 P1705 LD 30 -1 Int BE Pri
!#2 N4795 P1706 LD 8 -1 Int BE Pri
!#2 N4796 P1705 LD 30 -1 Int BE Pri
!#2 N4797 P1706 LD 8 -1 Int BE Pri
!#2 N4798 P1707 BLD 0 -1 FP BE Pri
!#2 N4799 P1707 BLD 1 -1 FP BE Pri
!#A N4798 N4799
!#2 N4800 P1707 BLD 2 -1 FP BE Pri
!#2 N4801 P1707 BLD 3 -1 FP BE Pri
!#2 N4802 P1708 BLD 28 -1 FP BE Pri
!#2 N4803 P1708 BLD 29 -1 FP BE Pri
!#A N4802 N4803
!#2 N4804 P1708 BLD 30 -1 FP BE Pri
!#2 N4805 P1708 BLD 31 -1 FP BE Pri
!#2 N4806 P1708 BLD 28 -1 FP BE Pri
!#2 N4807 P1708 BLD 29 -1 FP BE Pri
!#A N4806 N4807
!#2 N4808 P1708 BLD 30 -1 FP BE Pri
!#2 N4809 P1708 BLD 31 -1 FP BE Pri
!#2 N4810 P1709 BLD 16 -1 FP BE Pri
!#2 N4811 P1709 BLD 17 -1 FP BE Pri
!#A N4810 N4811
!#2 N4812 P1709 BLD 18 -1 FP BE Pri
!#2 N4813 P1709 BLD 19 -1 FP BE Pri
!#2 N4814 P1710 BLD 8 -1 FP BE Pri
!#2 N4815 P1710 BLD 9 -1 FP BE Pri
!#A N4814 N4815
!#2 N4816 P1710 BLD 10 -1 FP BE Pri
!#2 N4817 P1710 BLD 11 -1 FP BE Pri
!#2 N4818 P1711 SWAP 3 0xffffffff 0x1000028 Int BE Pri
!#2 N4819 P1712 LD 13 -1 Int BE Pri
!#2 N4820 P1713 BLD 4 -1 FP BE Pri
!#2 N4821 P1713 BLD 5 -1 FP BE Pri
!#A N4820 N4821
!#2 N4822 P1713 BLD 6 -1 FP BE Pri
!#2 N4823 P1713 BLD 7 -1 FP BE Pri
!#2 N4824 P1713 BLD 4 -1 FP BE Pri
!#2 N4825 P1713 BLD 5 -1 FP BE Pri
!#A N4824 N4825
!#2 N4826 P1713 BLD 6 -1 FP BE Pri
!#2 N4827 P1713 BLD 7 -1 FP BE Pri
!#2 N4828 P1714 LD 26 -1 Int BE Pri
!#2 N4829 P1715 BLD 16 -1 FP BE Pri
!#2 N4830 P1715 BLD 17 -1 FP BE Pri
!#A N4829 N4830
!#2 N4831 P1715 BLD 18 -1 FP BE Pri
!#2 N4832 P1715 BLD 19 -1 FP BE Pri
!#2 N4833 P1716 LD 17 -1 Int BE Pri
!#2 N4834 P1714 LD 26 -1 Int BE Pri
!#2 N4835 P1715 BLD 16 -1 FP BE Pri
!#2 N4836 P1715 BLD 17 -1 FP BE Pri
!#A N4835 N4836
!#2 N4837 P1715 BLD 18 -1 FP BE Pri
!#2 N4838 P1715 BLD 19 -1 FP BE Pri
!#2 N4839 P1716 LD 17 -1 Int BE Pri
!#2 N4840 P1717 DWLD 24 -1 FP BE Pri
!#2 N4841 P1717 DWLD 25 -1 FP BE Pri
!#A N4840 N4841
!#2 N4842 P1718 BLD 24 -1 FP BE Pri
!#2 N4843 P1718 BLD 25 -1 FP BE Pri
!#A N4842 N4843
!#2 N4844 P1718 BLD 26 -1 FP BE Pri
!#2 N4845 P1718 BLD 27 -1 FP BE Pri
!#2 N4846 P1719 BLD 4 -1 FP BE Pri
!#2 N4847 P1719 BLD 5 -1 FP BE Pri
!#A N4846 N4847
!#2 N4848 P1719 BLD 6 -1 FP BE Pri
!#2 N4849 P1719 BLD 7 -1 FP BE Pri
!#2 N4850 P1719 BLD 4 -1 FP BE Pri
!#2 N4851 P1719 BLD 5 -1 FP BE Pri
!#A N4850 N4851
!#2 N4852 P1719 BLD 6 -1 FP BE Pri
!#2 N4853 P1719 BLD 7 -1 FP BE Pri
!#2 N4854 P1720 LD 0 -1 Int BE Pri
!#2 N4855 P1721 DWLD 8 -1 Int BE Pri
!#2 N4856 P1721 DWLD 9 -1 Int BE Pri
!#A N4855 N4856
!#2 N4857 P1722 LD 3 -1 Int BE Pri
!#2 N4858 P1723 DWLD 14 -1 Int BE Pri
!#2 N4860 P1725 LD 16 -1 Int BE Pri
!#2 N4861 P1726 LD 21 -1 Int BE Pri
!#2 N4862 P1727 LD 28 -1 Int BE Pri
!#2 N4863 P1726 LD 21 -1 Int BE Pri
!#2 N4864 P1727 LD 28 -1 Int BE Pri
!#2 N4865 P1728 BLD 4 -1 FP BE Pri
!#2 N4866 P1728 BLD 5 -1 FP BE Pri
!#A N4865 N4866
!#2 N4867 P1728 BLD 6 -1 FP BE Pri
!#2 N4868 P1728 BLD 7 -1 FP BE Pri
!#2 N4869 P1728 BLD 4 -1 FP BE Pri
!#2 N4870 P1728 BLD 5 -1 FP BE Pri
!#A N4869 N4870
!#2 N4871 P1728 BLD 6 -1 FP BE Pri
!#2 N4872 P1728 BLD 7 -1 FP BE Pri
!#2 N4873 P1729 BST 20 0x40800036 FP BE Pri
!#2 N4874 P1729 BST 21 0x40800037 FP BE Pri
!#A N4873 N4874
!#2 N4875 P1729 BST 22 0x40800038 FP BE Pri
!#2 N4876 P1729 BST 23 0x40800039 FP BE Pri
!#2 N4877 P1730 LD 1 -1 Int BE Pri
!#2 N4878 P1731 LD 26 -1 Int BE Pri
!#2 N4879 P1729 BST 20 0x4080003a FP BE Pri
!#2 N4880 P1729 BST 21 0x4080003b FP BE Pri
!#A N4879 N4880
!#2 N4881 P1729 BST 22 0x4080003c FP BE Pri
!#2 N4882 P1729 BST 23 0x4080003d FP BE Pri
!#2 N4883 P1730 LD 1 -1 Int BE Pri
!#2 N4884 P1731 LD 26 -1 Int BE Pri
!#2 N4885 P1732 LD 4 -1 FP BE Pri
!#2 N4886 P1732 LD 4 -1 FP BE Pri
!#2 N4887 P1733 BLD 20 -1 FP BE Pri
!#2 N4888 P1733 BLD 21 -1 FP BE Pri
!#A N4887 N4888
!#2 N4889 P1733 BLD 22 -1 FP BE Pri
!#2 N4890 P1733 BLD 23 -1 FP BE Pri
!#2 N4891 P1734 BSTC 24 0x4080003e FP BE Pri
!#2 N4892 P1734 BSTC 25 0x4080003f FP BE Pri
!#A N4891 N4892
!#2 N4893 P1734 BSTC 26 0x40800040 FP BE Pri
!#2 N4894 P1734 BSTC 27 0x40800041 FP BE Pri
!#2 N4895 P1734 BSTC 24 0x40800042 FP BE Pri
!#2 N4896 P1734 BSTC 25 0x40800043 FP BE Pri
!#A N4895 N4896
!#2 N4897 P1734 BSTC 26 0x40800044 FP BE Pri
!#2 N4898 P1734 BSTC 27 0x40800045 FP BE Pri
!#2 N4899 P1735 BSTC 4 0x40800046 FP BE Pri
!#2 N4900 P1735 BSTC 5 0x40800047 FP BE Pri
!#A N4899 N4900
!#2 N4901 P1735 BSTC 6 0x40800048 FP BE Pri
!#2 N4902 P1735 BSTC 7 0x40800049 FP BE Pri
!#2 N4903 P1736 BLD 28 -1 FP BE Pri
!#2 N4904 P1736 BLD 29 -1 FP BE Pri
!#A N4903 N4904
!#2 N4905 P1736 BLD 30 -1 FP BE Pri
!#2 N4906 P1736 BLD 31 -1 FP BE Pri
!#2 N4907 P1735 BSTC 4 0x4080004a FP BE Pri
!#2 N4908 P1735 BSTC 5 0x4080004b FP BE Pri
!#A N4907 N4908
!#2 N4909 P1735 BSTC 6 0x4080004c FP BE Pri
!#2 N4910 P1735 BSTC 7 0x4080004d FP BE Pri
!#2 N4911 P1736 BLD 28 -1 FP BE Pri
!#2 N4912 P1736 BLD 29 -1 FP BE Pri
!#A N4911 N4912
!#2 N4913 P1736 BLD 30 -1 FP BE Pri
!#2 N4914 P1736 BLD 31 -1 FP BE Pri
!#2 N4915 P1737 DWLD 31 -1 Int BE Pri
!#2 N4916 P1738 BLD 0 -1 FP BE Pri
!#2 N4917 P1738 BLD 1 -1 FP BE Pri
!#A N4916 N4917
!#2 N4918 P1738 BLD 2 -1 FP BE Pri
!#2 N4919 P1738 BLD 3 -1 FP BE Pri
!#2 N4920 P1739 LD 29 -1 Int BE Pri
!#2 N4921 P1737 DWLD 31 -1 Int BE Pri
!#2 N4922 P1738 BLD 0 -1 FP BE Pri
!#2 N4923 P1738 BLD 1 -1 FP BE Pri
!#A N4922 N4923
!#2 N4924 P1738 BLD 2 -1 FP BE Pri
!#2 N4925 P1738 BLD 3 -1 FP BE Pri
!#2 N4926 P1739 LD 29 -1 Int BE Pri
!#2 N4928 P1741 BLD 12 -1 FP BE Pri
!#2 N4929 P1741 BLD 13 -1 FP BE Pri
!#A N4928 N4929
!#2 N4930 P1741 BLD 14 -1 FP BE Pri
!#2 N4931 P1741 BLD 15 -1 FP BE Pri
!#2 N4932 P1742 BLD 20 -1 FP BE Pri
!#2 N4933 P1742 BLD 21 -1 FP BE Pri
!#A N4932 N4933
!#2 N4934 P1742 BLD 22 -1 FP BE Pri
!#2 N4935 P1742 BLD 23 -1 FP BE Pri
!#2 N4936 P1741 BLD 12 -1 FP BE Pri
!#2 N4937 P1741 BLD 13 -1 FP BE Pri
!#A N4936 N4937
!#2 N4938 P1741 BLD 14 -1 FP BE Pri
!#2 N4939 P1741 BLD 15 -1 FP BE Pri
!#2 N4940 P1742 BLD 20 -1 FP BE Pri
!#2 N4941 P1742 BLD 21 -1 FP BE Pri
!#A N4940 N4941
!#2 N4942 P1742 BLD 22 -1 FP BE Pri
!#2 N4943 P1742 BLD 23 -1 FP BE Pri
!#2 N4945 P1744 LD 22 -1 Int BE Pri
!#2 N4946 P1745 LD 28 -1 Int BE Pri
!#2 N4948 P1744 LD 22 -1 Int BE Pri
!#2 N4949 P1745 LD 28 -1 Int BE Pri
!#2 N4950 P1746 DWLD 8 -1 Int BE Pri
!#2 N4951 P1746 DWLD 9 -1 Int BE Pri
!#A N4950 N4951
!#2 N4952 P1747 DWLD 4 -1 Int BE Pri
!#2 N4953 P1747 DWLD 5 -1 Int BE Pri
!#A N4952 N4953
!#2 N4954 P1748 LD 30 -1 Int BE Pri
!#2 N4955 P1749 LD 12 -1 Int BE Pri
!#2 N4956 P1750 LD 14 -1 Int BE Pri
!#2 N4957 P1751 LD 6 -1 Int BE Pri
!#2 N4958 P1752 ST 5 0x1000029 Int LE Pri
!#2 N4959 P1753 DWLD 8 -1 Int BE Pri
!#2 N4960 P1753 DWLD 9 -1 Int BE Pri
!#A N4959 N4960
!#2 N4961 P1753 CASX 8 -1 N4959 0x100002a Int BE Pri
!#2 N4962 P1753 CASX 9 -1 N4960 0x100002b Int BE Pri
!#A N4961 N4962
!#2 N4963 P1753 DWLD 8 -1 Int BE Pri
!#2 N4964 P1753 DWLD 9 -1 Int BE Pri
!#A N4963 N4964
!#2 N4965 P1753 CASX 8 -1 N4963 0x100002c Int BE Pri
!#2 N4966 P1753 CASX 9 -1 N4964 0x100002d Int BE Pri
!#A N4965 N4966
!#2 N4967 P1754 LD 19 -1 Int BE Pri
!#2 N4968 P1755 LD 6 -1 Int BE Pri
!#2 N4969 P1756 BSTC 4 0x4080004e FP BE Pri
!#2 N4970 P1756 BSTC 5 0x4080004f FP BE Pri
!#A N4969 N4970
!#2 N4971 P1756 BSTC 6 0x40800050 FP BE Pri
!#2 N4972 P1756 BSTC 7 0x40800051 FP BE Pri
!#2 N4973 P1757 LD 2 -1 Int BE Pri
!#2 N4974 P1758 LD 7 -1 Int BE Pri
!#2 N4975 P1756 BSTC 4 0x40800052 FP BE Pri
!#2 N4976 P1756 BSTC 5 0x40800053 FP BE Pri
!#A N4975 N4976
!#2 N4977 P1756 BSTC 6 0x40800054 FP BE Pri
!#2 N4978 P1756 BSTC 7 0x40800055 FP BE Pri
!#2 N4979 P1757 LD 2 -1 Int BE Pri
!#2 N4980 P1758 LD 7 -1 Int BE Pri
!#2 N4981 P1759 DWLD 31 -1 Int BE Pri
!#2 N4982 P1760 LD 26 -1 Int BE Pri
!#2 N4984 P1762 DWLD 27 -1 Int BE Pri
!#2 N4985 P1763 LD 16 -1 Int BE Pri
!#2 N4987 P1762 DWLD 27 -1 Int BE Pri
!#2 N4988 P1763 LD 16 -1 Int BE Pri
!#2 N4989 P1764 BLD 8 -1 FP BE Pri
!#2 N4990 P1764 BLD 9 -1 FP BE Pri
!#A N4989 N4990
!#2 N4991 P1764 BLD 10 -1 FP BE Pri
!#2 N4992 P1764 BLD 11 -1 FP BE Pri
!#2 N4993 P1765 BLD 4 -1 FP BE Pri
!#2 N4994 P1765 BLD 5 -1 FP BE Pri
!#A N4993 N4994
!#2 N4995 P1765 BLD 6 -1 FP BE Pri
!#2 N4996 P1765 BLD 7 -1 FP BE Pri
!#2 N4997 P1766 BLD 8 -1 FP BE Pri
!#2 N4998 P1766 BLD 9 -1 FP BE Pri
!#A N4997 N4998
!#2 N4999 P1766 BLD 10 -1 FP BE Pri
!#2 N5000 P1766 BLD 11 -1 FP BE Pri
!#2 N5001 P1767 DWLD 18 -1 Int BE Pri
!#2 N5002 P1768 LD 17 -1 Int BE Pri
!#2 N5003 P1766 BLD 8 -1 FP BE Pri
!#2 N5004 P1766 BLD 9 -1 FP BE Pri
!#A N5003 N5004
!#2 N5005 P1766 BLD 10 -1 FP BE Pri
!#2 N5006 P1766 BLD 11 -1 FP BE Pri
!#2 N5007 P1767 DWLD 18 -1 Int BE Pri
!#2 N5008 P1768 LD 17 -1 Int BE Pri
!#2 N5009 P1769 BLD 12 -1 FP BE Pri
!#2 N5010 P1769 BLD 13 -1 FP BE Pri
!#A N5009 N5010
!#2 N5011 P1769 BLD 14 -1 FP BE Pri
!#2 N5012 P1769 BLD 15 -1 FP BE Pri
!#2 N5013 P1770 DWLD 24 -1 Int BE Pri
!#2 N5014 P1770 DWLD 25 -1 Int BE Pri
!#A N5013 N5014
!#2 N5015 P1771 DWLD 16 -1 Int BE Pri
!#2 N5016 P1771 DWLD 17 -1 Int BE Pri
!#A N5015 N5016
!#2 N5017 P1771 DWLD 16 -1 Int BE Pri
!#2 N5018 P1771 DWLD 17 -1 Int BE Pri
!#A N5017 N5018
!#2 N5019 P1772 BLD 24 -1 FP BE Pri
!#2 N5020 P1772 BLD 25 -1 FP BE Pri
!#A N5019 N5020
!#2 N5021 P1772 BLD 26 -1 FP BE Pri
!#2 N5022 P1772 BLD 27 -1 FP BE Pri
!#2 N5023 P1773 DWLD 16 -1 Int BE Pri
!#2 N5024 P1773 DWLD 17 -1 Int BE Pri
!#A N5023 N5024
!#2 N5025 P1774 DWLD 19 -1,0x0 Int BE Pri
!#2 N5026 P1774 CASX 19 -1,0x0 N5025 0x100002e Int BE Pri
!#2 N5028 P1776 DWLD 19 -1 Int BE Pri
!#2 N5029 P1777 LD 25 -1 Int BE Pri
!#2 N5030 P1778 MEMBAR
!#2 N5032 P1780 BLD 8 -1 FP BE Pri
!#2 N5033 P1780 BLD 9 -1 FP BE Pri
!#A N5032 N5033
!#2 N5034 P1780 BLD 10 -1 FP BE Pri
!#2 N5035 P1780 BLD 11 -1 FP BE Pri
!#2 N5036 P1781 DWLD 8 -1 Int BE Pri
!#2 N5037 P1781 DWLD 9 -1 Int BE Pri
!#A N5036 N5037
!#2 N5038 P1782 DWLD 20 -1 Int BE Pri
!#2 N5039 P1782 DWLD 21 -1 Int BE Pri
!#A N5038 N5039
!#2 N5040 P1783 BLD 4 -1 FP BE Pri
!#2 N5041 P1783 BLD 5 -1 FP BE Pri
!#A N5040 N5041
!#2 N5042 P1783 BLD 6 -1 FP BE Pri
!#2 N5043 P1783 BLD 7 -1 FP BE Pri
!#2 N5044 P1784 MEMBAR
!#2 N5045 P1785 BLD 8 -1 FP BE Pri
!#2 N5046 P1785 BLD 9 -1 FP BE Pri
!#A N5045 N5046
!#2 N5047 P1785 BLD 10 -1 FP BE Pri
!#2 N5048 P1785 BLD 11 -1 FP BE Pri
!#2 N5049 P1786 BLD 0 -1 FP BE Pri
!#2 N5050 P1786 BLD 1 -1 FP BE Pri
!#A N5049 N5050
!#2 N5051 P1786 BLD 2 -1 FP BE Pri
!#2 N5052 P1786 BLD 3 -1 FP BE Pri
!#2 N5053 P1787 DWLD 23 -1 Int BE Pri
!#2 N5054 P1788 LD 26 -1 Int BE Pri
!#2 N5055 P1789 LD 14 -1 Int BE Pri
!#2 N5056 P1790 LD 26 -1 Int BE Pri
!#2 N5057 P1789 LD 14 -1 Int BE Pri
!#2 N5058 P1790 LD 26 -1 Int BE Pri
!#2 N5059 P1791 LD 0 -1 Int LE Pri
!#2 N5060 P1792 LD 17 -1 Int BE Pri
!#2 N5061 P1791 LD 0 -1 Int LE Pri
!#2 N5062 P1792 LD 17 -1 Int BE Pri
!#2 N5063 P1793 DWLD 18 -1 Int BE Pri
!#2 N5064 P1794 LD 29 -1 Int LE Pri
!#2 N5065 P1793 DWLD 18 -1 Int BE Pri
!#2 N5066 P1794 LD 29 -1 Int LE Pri
!#2 N5067 P1795 SWAP 8 0xffffffff 0x100002f Int BE Pri
!#2 N5068 P1796 LD 28 -1 Int BE Pri
!#2 N5069 P1795 SWAP 8 0xffffffff 0x1000030 Int BE Pri
!#2 N5070 P1796 LD 28 -1 Int BE Pri
!#2 N5071 P1797 BLD 4 -1 FP BE Pri
!#2 N5072 P1797 BLD 5 -1 FP BE Pri
!#A N5071 N5072
!#2 N5073 P1797 BLD 6 -1 FP BE Pri
!#2 N5074 P1797 BLD 7 -1 FP BE Pri
!#2 N5075 P1797 BLD 4 -1 FP BE Pri
!#2 N5076 P1797 BLD 5 -1 FP BE Pri
!#A N5075 N5076
!#2 N5077 P1797 BLD 6 -1 FP BE Pri
!#2 N5078 P1797 BLD 7 -1 FP BE Pri
!#2 N5079 P1798 DWLD 19 -1 Int BE Pri
!#2 N5080 P1799 LD 12 -1 Int BE Pri
!#2 N5081 P1800 LD 18 -1 Int BE Pri
!#2 N5082 P1801 LD 19 -1 Int BE Pri
!#2 N5083 P1800 LD 18 -1 Int BE Pri
!#2 N5084 P1801 LD 19 -1 Int BE Pri
!#2 N5085 P1802 DWLD 18 -1 Int BE Pri
!#2 N5086 P1803 LD 5 -1 Int BE Pri
!#2 N5087 P1804 BSTC 4 0x40800056 FP BE Pri
!#2 N5088 P1804 BSTC 5 0x40800057 FP BE Pri
!#A N5087 N5088
!#2 N5089 P1804 BSTC 6 0x40800058 FP BE Pri
!#2 N5090 P1804 BSTC 7 0x40800059 FP BE Pri
!#2 N5091 P1805 LD 6 -1 Int BE Pri
!#2 N5092 P1806 LD 30 -1 Int BE Pri
!#2 N5093 P1804 BSTC 4 0x4080005a FP BE Pri
!#2 N5094 P1804 BSTC 5 0x4080005b FP BE Pri
!#A N5093 N5094
!#2 N5095 P1804 BSTC 6 0x4080005c FP BE Pri
!#2 N5096 P1804 BSTC 7 0x4080005d FP BE Pri
!#2 N5097 P1805 LD 6 -1 Int BE Pri
!#2 N5098 P1806 LD 30 -1 Int BE Pri
!#2 N5099 P1807 DWLD 8 -1 Int BE Pri
!#2 N5100 P1807 DWLD 9 -1 Int BE Pri
!#A N5099 N5100
!#2 N5101 P1808 DWLD 28 -1 Int BE Pri
!#2 N5102 P1808 DWLD 29 -1 Int BE Pri
!#A N5101 N5102
!#2 N5103 P1807 DWLD 8 -1 Int BE Pri
!#2 N5104 P1807 DWLD 9 -1 Int BE Pri
!#A N5103 N5104
!#2 N5105 P1808 DWLD 28 -1 Int BE Pri
!#2 N5106 P1808 DWLD 29 -1 Int BE Pri
!#A N5105 N5106
!#2 N5107 P1809 DWLD 4 -1 Int BE Pri
!#2 N5108 P1809 DWLD 5 -1 Int BE Pri
!#A N5107 N5108
!#2 N5109 P1809 DWLD 4 -1 Int BE Pri
!#2 N5110 P1809 DWLD 5 -1 Int BE Pri
!#A N5109 N5110
!#2 N5111 P1810 BLD 16 -1 FP BE Pri
!#2 N5112 P1810 BLD 17 -1 FP BE Pri
!#A N5111 N5112
!#2 N5113 P1810 BLD 18 -1 FP BE Pri
!#2 N5114 P1810 BLD 19 -1 FP BE Pri
!#2 N5115 P1811 LD 7 -1 Int BE Pri
!#2 N5116 P1812 LD 27 -1 Int BE Pri
!#2 N5117 P1813 BLD 8 -1 FP BE Pri
!#2 N5118 P1813 BLD 9 -1 FP BE Pri
!#A N5117 N5118
!#2 N5119 P1813 BLD 10 -1 FP BE Pri
!#2 N5120 P1813 BLD 11 -1 FP BE Pri
!#2 N5121 P1814 BLD 24 -1 FP BE Pri
!#2 N5122 P1814 BLD 25 -1 FP BE Pri
!#A N5121 N5122
!#2 N5123 P1814 BLD 26 -1 FP BE Pri
!#2 N5124 P1814 BLD 27 -1 FP BE Pri
!#2 N5125 P1813 BLD 8 -1 FP BE Pri
!#2 N5126 P1813 BLD 9 -1 FP BE Pri
!#A N5125 N5126
!#2 N5127 P1813 BLD 10 -1 FP BE Pri
!#2 N5128 P1813 BLD 11 -1 FP BE Pri
!#2 N5129 P1814 BLD 24 -1 FP BE Pri
!#2 N5130 P1814 BLD 25 -1 FP BE Pri
!#A N5129 N5130
!#2 N5131 P1814 BLD 26 -1 FP BE Pri
!#2 N5132 P1814 BLD 27 -1 FP BE Pri
!#2 N5133 P1815 BST 4 0x4080005e FP BE Pri
!#2 N5134 P1815 BST 5 0x4080005f FP BE Pri
!#A N5133 N5134
!#2 N5135 P1815 BST 6 0x40800060 FP BE Pri
!#2 N5136 P1815 BST 7 0x40800061 FP BE Pri
!#2 N5137 P1816 LD 1 -1 Int BE Pri
!#2 N5138 P1817 LD 14 -1 Int BE Pri
!#2 N5139 P1818 DWLD 0 -1 Int BE Pri
!#2 N5140 P1818 DWLD 1 -1 Int BE Pri
!#A N5139 N5140
!#2 N5141 P1819 DWLD 12 -1 FP BE Pri
!#2 N5142 P1819 DWLD 13 -1 FP BE Pri
!#A N5141 N5142
!#2 N5143 P1820 BLD 12 -1 FP BE Pri
!#2 N5144 P1820 BLD 13 -1 FP BE Pri
!#A N5143 N5144
!#2 N5145 P1820 BLD 14 -1 FP BE Pri
!#2 N5146 P1820 BLD 15 -1 FP BE Pri
!#2 N5147 P1821 SWAP 29 0xffffffff 0x1000031 Int BE Pri
!#2 N5148 P1822 LD 26 -1 Int BE Pri
!#2 N5149 P1823 BLD 24 -1 FP BE Pri
!#2 N5150 P1823 BLD 25 -1 FP BE Pri
!#A N5149 N5150
!#2 N5151 P1823 BLD 26 -1 FP BE Pri
!#2 N5152 P1823 BLD 27 -1 FP BE Pri
!#2 N5153 P1824 DWLD 0 -1 Int BE Pri
!#2 N5154 P1824 DWLD 1 -1 Int BE Pri
!#A N5153 N5154
!#2 N5155 P1825 LD 30 -1 Int BE Pri
!#2 N5156 P1826 LD 9 -1 Int BE Pri
!#2 N5157 P1824 DWLD 0 -1 Int BE Pri
!#2 N5158 P1824 DWLD 1 -1 Int BE Pri
!#A N5157 N5158
!#2 N5159 P1825 LD 30 -1 Int BE Pri
!#2 N5160 P1826 LD 9 -1 Int BE Pri
!#2 N5161 P1827 DWLD 2 -1 Int BE Pri
!#2 N5162 P1828 BLD 16 -1 FP BE Pri
!#2 N5163 P1828 BLD 17 -1 FP BE Pri
!#A N5162 N5163
!#2 N5164 P1828 BLD 18 -1 FP BE Pri
!#2 N5165 P1828 BLD 19 -1 FP BE Pri
!#2 N5166 P1829 LD 19 -1 Int LE Pri
!#2 N5167 P1830 BLD 20 -1 FP BE Pri
!#2 N5168 P1830 BLD 21 -1 FP BE Pri
!#A N5167 N5168
!#2 N5169 P1830 BLD 22 -1 FP BE Pri
!#2 N5170 P1830 BLD 23 -1 FP BE Pri
!#2 N5171 P1831 MEMBAR
!#2 N5172 P1830 BLD 20 -1 FP BE Pri
!#2 N5173 P1830 BLD 21 -1 FP BE Pri
!#A N5172 N5173
!#2 N5174 P1830 BLD 22 -1 FP BE Pri
!#2 N5175 P1830 BLD 23 -1 FP BE Pri
!#2 N5176 P1831 MEMBAR
!#2 N5177 P1832 LD 1 -1 Int BE Pri
!#2 N5178 P1833 LD 21 -1 Int BE Pri
!#2 N5179 P1834 LD 23 -1 Int BE Pri
!#2 N5180 P1835 LD 25 -1 Int BE Pri
!#2 N5181 P1834 LD 23 -1 Int BE Pri
!#2 N5182 P1835 LD 25 -1 Int BE Pri
!#2 N5183 P1836 DWLD 28 -1 Int BE Pri
!#2 N5184 P1836 DWLD 29 -1 Int BE Pri
!#A N5183 N5184
!#2 N5185 P1836 DWLD 28 -1 Int BE Pri
!#2 N5186 P1836 DWLD 29 -1 Int BE Pri
!#A N5185 N5186
!#2 N5187 P1837 BLD 28 -1 FP BE Pri
!#2 N5188 P1837 BLD 29 -1 FP BE Pri
!#A N5187 N5188
!#2 N5189 P1837 BLD 30 -1 FP BE Pri
!#2 N5190 P1837 BLD 31 -1 FP BE Pri
!#2 N5191 P1838 BLD 8 -1 FP BE Pri
!#2 N5192 P1838 BLD 9 -1 FP BE Pri
!#A N5191 N5192
!#2 N5193 P1838 BLD 10 -1 FP BE Pri
!#2 N5194 P1838 BLD 11 -1 FP BE Pri
!#2 N5195 P1837 BLD 28 -1 FP BE Pri
!#2 N5196 P1837 BLD 29 -1 FP BE Pri
!#A N5195 N5196
!#2 N5197 P1837 BLD 30 -1 FP BE Pri
!#2 N5198 P1837 BLD 31 -1 FP BE Pri
!#2 N5199 P1838 BLD 8 -1 FP BE Pri
!#2 N5200 P1838 BLD 9 -1 FP BE Pri
!#A N5199 N5200
!#2 N5201 P1838 BLD 10 -1 FP BE Pri
!#2 N5202 P1838 BLD 11 -1 FP BE Pri
!#2 N5203 P1839 BLD 8 -1 FP BE Pri
!#2 N5204 P1839 BLD 9 -1 FP BE Pri
!#A N5203 N5204
!#2 N5205 P1839 BLD 10 -1 FP BE Pri
!#2 N5206 P1839 BLD 11 -1 FP BE Pri
!#2 N5208 P1841 BLD 16 -1 FP BE Pri
!#2 N5209 P1841 BLD 17 -1 FP BE Pri
!#A N5208 N5209
!#2 N5210 P1841 BLD 18 -1 FP BE Pri
!#2 N5211 P1841 BLD 19 -1 FP BE Pri
!#2 N5212 P1842 LD 25 -1 Int BE Pri
!#2 N5213 P1843 LD 25 -1 Int LE Pri
!#2 N5214 P1844 DWLD 12 -1 Int BE Pri
!#2 N5215 P1844 DWLD 13 -1 Int BE Pri
!#A N5214 N5215
!#2 N5216 P1845 DWLD 28 -1 Int BE Pri
!#2 N5217 P1845 DWLD 29 -1 Int BE Pri
!#A N5216 N5217
!#2 N5218 P1846 DWLD 4 -1 Int BE Pri
!#2 N5219 P1846 DWLD 5 -1 Int BE Pri
!#A N5218 N5219
!#2 N5220 P1847 LD 11 -1 Int BE Pri
!#2 N5221 P1848 DWLD 16 -1 Int BE Pri
!#2 N5222 P1848 DWLD 17 -1 Int BE Pri
!#A N5221 N5222
!#2 N5223 P1849 LD 13 -1 Int LE Pri
!#2 N5224 P1847 LD 11 -1 Int BE Pri
!#2 N5225 P1848 DWLD 16 -1 Int BE Pri
!#2 N5226 P1848 DWLD 17 -1 Int BE Pri
!#A N5225 N5226
!#2 N5227 P1849 LD 13 -1 Int LE Pri
!#2 N5228 P1850 LD 18 -1 Int BE Pri
!#2 N5229 P1851 BLD 12 -1 FP BE Pri
!#2 N5230 P1851 BLD 13 -1 FP BE Pri
!#A N5229 N5230
!#2 N5231 P1851 BLD 14 -1 FP BE Pri
!#2 N5232 P1851 BLD 15 -1 FP BE Pri
!#2 N5233 P1852 LD 0 -1 Int BE Pri
!#2 N5234 P1850 LD 18 -1 Int BE Pri
!#2 N5235 P1851 BLD 12 -1 FP BE Pri
!#2 N5236 P1851 BLD 13 -1 FP BE Pri
!#A N5235 N5236
!#2 N5237 P1851 BLD 14 -1 FP BE Pri
!#2 N5238 P1851 BLD 15 -1 FP BE Pri
!#2 N5239 P1852 LD 0 -1 Int BE Pri
!#2 N5240 P1853 LD 14 -1 Int BE Pri
!#2 N5241 P1854 DWLD 26 -1 Int BE Pri
!#2 N5242 P1855 BLD 28 -1 FP BE Pri
!#2 N5243 P1855 BLD 29 -1 FP BE Pri
!#A N5242 N5243
!#2 N5244 P1855 BLD 30 -1 FP BE Pri
!#2 N5245 P1855 BLD 31 -1 FP BE Pri
!#2 N5246 P1856 BLD 28 -1 FP BE Pri
!#2 N5247 P1856 BLD 29 -1 FP BE Pri
!#A N5246 N5247
!#2 N5248 P1856 BLD 30 -1 FP BE Pri
!#2 N5249 P1856 BLD 31 -1 FP BE Pri
!#2 N5250 P1855 BLD 28 -1 FP BE Pri
!#2 N5251 P1855 BLD 29 -1 FP BE Pri
!#A N5250 N5251
!#2 N5252 P1855 BLD 30 -1 FP BE Pri
!#2 N5253 P1855 BLD 31 -1 FP BE Pri
!#2 N5254 P1856 BLD 28 -1 FP BE Pri
!#2 N5255 P1856 BLD 29 -1 FP BE Pri
!#A N5254 N5255
!#2 N5256 P1856 BLD 30 -1 FP BE Pri
!#2 N5257 P1856 BLD 31 -1 FP BE Pri
!#2 N5258 P1857 ST 17 0x40800062 FP BE Pri
!#2 N5259 P1857 ST 17 0x40800063 FP BE Pri
!#2 N5260 P1858 LD 24 -1 Int BE Pri
!#2 N5261 P1859 LD 17 -1 Int BE Pri
!#2 N5262 P1858 LD 24 -1 Int BE Pri
!#2 N5263 P1859 LD 17 -1 Int BE Pri
!#2 N5264 P1860 DWLD 2 -1 Int BE Pri
!#2 N5265 P1861 LD 17 -1 Int LE Pri
!#2 N5266 P1860 DWLD 2 -1 Int BE Pri
!#2 N5267 P1861 LD 17 -1 Int LE Pri
!#2 N5268 P1862 BLD 20 -1 FP BE Pri
!#2 N5269 P1862 BLD 21 -1 FP BE Pri
!#A N5268 N5269
!#2 N5270 P1862 BLD 22 -1 FP BE Pri
!#2 N5271 P1862 BLD 23 -1 FP BE Pri
!#2 N5272 P1863 DWLD 7 -1 Int BE Pri
!#2 N5273 P1864 LD 11 -1 Int BE Pri
!#2 N5274 P1865 LD 19 -1 Int BE Pri
!#2 N5275 P1866 LD 14 -1 Int BE Pri
!#2 N5276 P1867 LD 23 -1 FP BE Pri
!#2 N5277 P1868 LD 2 -1 Int BE Pri
!#2 N5278 P1869 LD 5 -1 Int BE Pri
!#2 N5279 P1870 BLD 12 -1 FP BE Pri
!#2 N5280 P1870 BLD 13 -1 FP BE Pri
!#A N5279 N5280
!#2 N5281 P1870 BLD 14 -1 FP BE Pri
!#2 N5282 P1870 BLD 15 -1 FP BE Pri
!#2 N5283 P1871 BLD 4 -1 FP BE Pri
!#2 N5284 P1871 BLD 5 -1 FP BE Pri
!#A N5283 N5284
!#2 N5285 P1871 BLD 6 -1 FP BE Pri
!#2 N5286 P1871 BLD 7 -1 FP BE Pri
!#2 N5287 P1872 ST 7 0x1000032 Int BE Pri
!#2 N5288 P1873 LD 30 -1 Int BE Pri
!#2 N5289 P1874 DWLD 10 -1 Int BE Pri
!#2 N5290 P1873 LD 30 -1 Int BE Pri
!#2 N5291 P1874 DWLD 10 -1 Int BE Pri
!#2 N5292 P1875 DWLD 18 -1 Int BE Pri
!#2 N5293 P1876 BLD 12 -1 FP BE Pri
!#2 N5294 P1876 BLD 13 -1 FP BE Pri
!#A N5293 N5294
!#2 N5295 P1876 BLD 14 -1 FP BE Pri
!#2 N5296 P1876 BLD 15 -1 FP BE Pri
!#2 N5297 P1877 LD 29 -1 Int BE Pri
!#2 N5298 P1875 DWLD 18 -1 Int BE Pri
!#2 N5299 P1876 BLD 12 -1 FP BE Pri
!#2 N5300 P1876 BLD 13 -1 FP BE Pri
!#A N5299 N5300
!#2 N5301 P1876 BLD 14 -1 FP BE Pri
!#2 N5302 P1876 BLD 15 -1 FP BE Pri
!#2 N5303 P1877 LD 29 -1 Int BE Pri
!#2 N5304 P1878 BLD 4 -1 FP BE Pri
!#2 N5305 P1878 BLD 5 -1 FP BE Pri
!#A N5304 N5305
!#2 N5306 P1878 BLD 6 -1 FP BE Pri
!#2 N5307 P1878 BLD 7 -1 FP BE Pri
!#2 N5308 P1879 DWLD 28 -1 Int BE Pri
!#2 N5309 P1879 DWLD 29 -1 Int BE Pri
!#A N5308 N5309
!#2 N5310 P1880 LD 20 -1 Int BE Pri
!#2 N5311 P1881 BLD 8 -1 FP BE Pri
!#2 N5312 P1881 BLD 9 -1 FP BE Pri
!#A N5311 N5312
!#2 N5313 P1881 BLD 10 -1 FP BE Pri
!#2 N5314 P1881 BLD 11 -1 FP BE Pri
!#2 N5315 P1882 LD 24 -1 Int BE Pri
!#2 N5316 P1880 LD 20 -1 Int BE Pri
!#2 N5317 P1881 BLD 8 -1 FP BE Pri
!#2 N5318 P1881 BLD 9 -1 FP BE Pri
!#A N5317 N5318
!#2 N5319 P1881 BLD 10 -1 FP BE Pri
!#2 N5320 P1881 BLD 11 -1 FP BE Pri
!#2 N5321 P1882 LD 24 -1 Int BE Pri
!#2 N5322 P1883 DWLD 11 -1 FP BE Pri
!#2 N5323 P1884 DWLD 28 -1 Int BE Pri
!#2 N5324 P1884 DWLD 29 -1 Int BE Pri
!#A N5323 N5324
!#2 N5325 P1883 DWLD 11 -1 FP BE Pri
!#2 N5326 P1884 DWLD 28 -1 Int BE Pri
!#2 N5327 P1884 DWLD 29 -1 Int BE Pri
!#A N5326 N5327
!#2 N5328 P1885 DWLD 28 -1 Int BE Pri
!#2 N5329 P1885 DWLD 29 -1 Int BE Pri
!#A N5328 N5329
!#2 N5330 P1886 LD 20 -1 Int BE Pri
!#2 N5331 P1887 LD 11 -1 Int BE Pri
!#2 N5332 P1885 DWLD 28 -1 Int BE Pri
!#2 N5333 P1885 DWLD 29 -1 Int BE Pri
!#A N5332 N5333
!#2 N5334 P1886 LD 20 -1 Int BE Pri
!#2 N5335 P1887 LD 11 -1 Int BE Pri
!#2 N5336 P1888 DWLD 19 -1,0x0 Int BE Pri
!#2 N5337 P1888 CASX 19 -1,0x0 N5336 0x1000033 Int BE Pri
!#2 N5341 P1891 BLD 28 -1 FP BE Pri
!#2 N5342 P1891 BLD 29 -1 FP BE Pri
!#A N5341 N5342
!#2 N5343 P1891 BLD 30 -1 FP BE Pri
!#2 N5344 P1891 BLD 31 -1 FP BE Pri
!#2 N5345 P1891 BLD 28 -1 FP BE Pri
!#2 N5346 P1891 BLD 29 -1 FP BE Pri
!#A N5345 N5346
!#2 N5347 P1891 BLD 30 -1 FP BE Pri
!#2 N5348 P1891 BLD 31 -1 FP BE Pri
!#2 N5349 P1892 LD 20 -1 Int BE Pri
!#2 N5351 P1894 LD 0 -1 Int BE Pri
!#2 N5352 P1892 LD 20 -1 Int BE Pri
!#2 N5354 P1894 LD 0 -1 Int BE Pri
!#2 N5355 P1895 DWLD 0 -1 Int BE Pri
!#2 N5356 P1895 DWLD 1 -1 Int BE Pri
!#A N5355 N5356
!#2 N5357 P1895 DWLD 0 -1 Int BE Pri
!#2 N5358 P1895 DWLD 1 -1 Int BE Pri
!#A N5357 N5358
!#2 N5359 P1896 DWLD 18 -1 Int BE Pri
!#2 N5360 P1897 LD 19 -1 Int BE Pri
!#2 N5361 P1898 BLD 28 -1 FP BE Pri
!#2 N5362 P1898 BLD 29 -1 FP BE Pri
!#A N5361 N5362
!#2 N5363 P1898 BLD 30 -1 FP BE Pri
!#2 N5364 P1898 BLD 31 -1 FP BE Pri
!#2 N5365 P1899 LD 22 -1 Int BE Pri
!#2 N5366 P1900 BLD 28 -1 FP BE Pri
!#2 N5367 P1900 BLD 29 -1 FP BE Pri
!#A N5366 N5367
!#2 N5368 P1900 BLD 30 -1 FP BE Pri
!#2 N5369 P1900 BLD 31 -1 FP BE Pri
!#2 N5370 P1901 LD 8 -1 Int BE Pri
!#2 N5371 P1902 BSTC 12 0x40800064 FP BE Pri
!#2 N5372 P1902 BSTC 13 0x40800065 FP BE Pri
!#A N5371 N5372
!#2 N5373 P1902 BSTC 14 0x40800066 FP BE Pri
!#2 N5374 P1902 BSTC 15 0x40800067 FP BE Pri
!#2 N5375 P1903 BST 12 0x40800068 FP BE Pri
!#2 N5376 P1903 BST 13 0x40800069 FP BE Pri
!#A N5375 N5376
!#2 N5377 P1903 BST 14 0x4080006a FP BE Pri
!#2 N5378 P1903 BST 15 0x4080006b FP BE Pri
!#2 N5379 P1904 LD 22 -1 Int BE Pri
!#2 N5380 P1905 LD 15 -1 Int BE Pri
!#2 N5381 P1904 LD 22 -1 Int BE Pri
!#2 N5382 P1905 LD 15 -1 Int BE Pri
!#2 N5383 P1906 BLD 28 -1 FP BE Pri
!#2 N5384 P1906 BLD 29 -1 FP BE Pri
!#A N5383 N5384
!#2 N5385 P1906 BLD 30 -1 FP BE Pri
!#2 N5386 P1906 BLD 31 -1 FP BE Pri
!#2 N5387 P1907 DWLD 18 -1 Int BE Pri
!#2 N5388 P1908 LD 14 -1 Int BE Pri
!#2 N5389 P1907 DWLD 18 -1 Int BE Pri
!#2 N5390 P1908 LD 14 -1 Int BE Pri
!#2 N5391 P1909 DWLD 4 -1 Int BE Pri
!#2 N5392 P1909 DWLD 5 -1 Int BE Pri
!#A N5391 N5392
!#2 N5395 P1911 SWAP 22 0xffffffff 0x1000034 Int BE Pri
!#2 N5396 P1912 LD 10 -1 Int BE Pri
!#2 N5397 P1911 SWAP 22 0xffffffff 0x1000035 Int BE Pri
!#2 N5398 P1912 LD 10 -1 Int BE Pri
!#2 N5399 P1913 LD 0 -1 Int BE Pri
!#2 N5400 P1914 BLD 12 -1 FP BE Pri
!#2 N5401 P1914 BLD 13 -1 FP BE Pri
!#A N5400 N5401
!#2 N5402 P1914 BLD 14 -1 FP BE Pri
!#2 N5403 P1914 BLD 15 -1 FP BE Pri
!#2 N5404 P1915 LD 9 -1 Int BE Pri
!#2 N5405 P1916 DWLD 6 -1 Int BE Pri
!#2 N5406 P1917 LD 22 -1 Int BE Pri
!#2 N5407 P1918 LD 2 -1 Int BE Pri
!#2 N5408 P1919 LD 20 -1 Int BE Pri
!#2 N5409 P1920 LD 22 -1 Int BE Pri
!#2 N5410 P1921 DWLD 4 -1 FP BE Pri
!#2 N5411 P1921 DWLD 5 -1 FP BE Pri
!#A N5410 N5411
!#2 N5412 P1922 LD 2 -1 Int BE Pri
!#2 N5413 P1920 LD 22 -1 Int BE Pri
!#2 N5414 P1921 DWLD 4 -1 FP BE Pri
!#2 N5415 P1921 DWLD 5 -1 FP BE Pri
!#A N5414 N5415
!#2 N5416 P1922 LD 2 -1 Int BE Pri
!#2 N5417 P1923 DWLD 24 -1 FP BE Pri
!#2 N5418 P1923 DWLD 25 -1 FP BE Pri
!#A N5417 N5418
!#2 N5419 P1924 BLD 28 -1 FP BE Pri
!#2 N5420 P1924 BLD 29 -1 FP BE Pri
!#A N5419 N5420
!#2 N5421 P1924 BLD 30 -1 FP BE Pri
!#2 N5422 P1924 BLD 31 -1 FP BE Pri
!#2 N5423 P1925 BLD 28 -1 FP BE Pri
!#2 N5424 P1925 BLD 29 -1 FP BE Pri
!#A N5423 N5424
!#2 N5425 P1925 BLD 30 -1 FP BE Pri
!#2 N5426 P1925 BLD 31 -1 FP BE Pri
!#2 N5427 P1926 BLD 28 -1 FP BE Pri
!#2 N5428 P1926 BLD 29 -1 FP BE Pri
!#A N5427 N5428
!#2 N5429 P1926 BLD 30 -1 FP BE Pri
!#2 N5430 P1926 BLD 31 -1 FP BE Pri
!#2 N5431 P1927 BLD 0 -1 FP BE Pri
!#2 N5432 P1927 BLD 1 -1 FP BE Pri
!#A N5431 N5432
!#2 N5433 P1927 BLD 2 -1 FP BE Pri
!#2 N5434 P1927 BLD 3 -1 FP BE Pri
!#2 N5435 P1928 LD 10 -1 Int BE Pri
!#2 N5436 P1929 LD 28 -1 Int BE Pri
!#2 N5437 P1930 LD 1 -1 Int BE Pri
!#2 N5438 P1931 BLD 0 -1 FP BE Pri
!#2 N5439 P1931 BLD 1 -1 FP BE Pri
!#A N5438 N5439
!#2 N5440 P1931 BLD 2 -1 FP BE Pri
!#2 N5441 P1931 BLD 3 -1 FP BE Pri
!#2 N5442 P1932 LD 18 -1 Int BE Pri
!#2 N5443 P1930 LD 1 -1 Int BE Pri
!#2 N5444 P1931 BLD 0 -1 FP BE Pri
!#2 N5445 P1931 BLD 1 -1 FP BE Pri
!#A N5444 N5445
!#2 N5446 P1931 BLD 2 -1 FP BE Pri
!#2 N5447 P1931 BLD 3 -1 FP BE Pri
!#2 N5448 P1932 LD 18 -1 Int BE Pri
!#2 N5449 P1933 DWLD 12 -1 Int BE Pri
!#2 N5450 P1933 DWLD 13 -1 Int BE Pri
!#A N5449 N5450
!#2 N5451 P1933 DWLD 12 -1 Int BE Pri
!#2 N5452 P1933 DWLD 13 -1 Int BE Pri
!#A N5451 N5452
!#2 N5453 P1934 LD 31 -1 Int BE Pri
!#2 N5454 P1935 DWLD 14 -1 Int BE Pri
!#2 N5455 P1936 BLD 28 -1 FP BE Pri
!#2 N5456 P1936 BLD 29 -1 FP BE Pri
!#A N5455 N5456
!#2 N5457 P1936 BLD 30 -1 FP BE Pri
!#2 N5458 P1936 BLD 31 -1 FP BE Pri
!#2 N5459 P1936 BLD 28 -1 FP BE Pri
!#2 N5460 P1936 BLD 29 -1 FP BE Pri
!#A N5459 N5460
!#2 N5461 P1936 BLD 30 -1 FP BE Pri
!#2 N5462 P1936 BLD 31 -1 FP BE Pri
!#2 N5463 P1937 DWST 16 0x1000036 Int BE Pri
!#2 N5464 P1937 DWST 17 0x1000037 Int BE Pri
!#A N5463 N5464
!#2 N5465 P1938 LD 9 -1 Int BE Pri
!#2 N5466 P1939 LD 28 -1 Int BE Pri
!#2 N5467 P1940 DWLD 6 -1 Int BE Pri
!#2 N5468 P1941 LD 19 -1 Int BE Pri
!#2 N5469 P1940 DWLD 6 -1 Int BE Pri
!#2 N5470 P1941 LD 19 -1 Int BE Pri
!#2 N5472 P1943 LD 8 -1 Int BE Pri
!#2 N5473 P1944 BST 8 0x4080006c FP BE Pri
!#2 N5474 P1944 BST 9 0x4080006d FP BE Pri
!#A N5473 N5474
!#2 N5475 P1944 BST 10 0x4080006e FP BE Pri
!#2 N5476 P1944 BST 11 0x4080006f FP BE Pri
!#2 N5477 P1945 LD 19 -1 Int BE Pri
!#2 N5478 P1943 LD 8 -1 Int BE Pri
!#2 N5479 P1944 BST 8 0x40800070 FP BE Pri
!#2 N5480 P1944 BST 9 0x40800071 FP BE Pri
!#A N5479 N5480
!#2 N5481 P1944 BST 10 0x40800072 FP BE Pri
!#2 N5482 P1944 BST 11 0x40800073 FP BE Pri
!#2 N5483 P1945 LD 19 -1 Int BE Pri
!#2 N5484 P1946 DWLD 19 -1 Int LE Pri
!#2 N5485 P1947 LD 4 -1 Int BE Pri
!#2 N5488 P1949 ST 15 0x1000038 Int BE Pri
!#2 N5489 P1949 ST 15 0x1000039 Int BE Pri
!#2 N5490 P1950 LD 17 -1 Int BE Pri
!#2 N5491 P1951 LD 22 -1 Int BE Pri
!#2 N5492 P1950 LD 17 -1 Int BE Pri
!#2 N5493 P1951 LD 22 -1 Int BE Pri
!#2 N5494 P1952 DWLD 24 -1 Int BE Pri
!#2 N5495 P1952 DWLD 25 -1 Int BE Pri
!#A N5494 N5495
!#2 N5496 P1953 ST 21 0x100003a Int BE Pri
!#2 N5497 P1954 DWLD 6 -1 Int BE Pri
!#2 N5498 P1955 BLD 24 -1 FP BE Pri
!#2 N5499 P1955 BLD 25 -1 FP BE Pri
!#A N5498 N5499
!#2 N5500 P1955 BLD 26 -1 FP BE Pri
!#2 N5501 P1955 BLD 27 -1 FP BE Pri
!#2 N5502 P1956 LD 20 -1 Int BE Pri
!#2 N5503 P1954 DWLD 6 -1 Int BE Pri
!#2 N5504 P1955 BLD 24 -1 FP BE Pri
!#2 N5505 P1955 BLD 25 -1 FP BE Pri
!#A N5504 N5505
!#2 N5506 P1955 BLD 26 -1 FP BE Pri
!#2 N5507 P1955 BLD 27 -1 FP BE Pri
!#2 N5508 P1956 LD 20 -1 Int BE Pri
!#2 N5509 P1957 LD 14 -1 FP BE Pri
!#2 N5511 P1957 LD 14 -1 FP BE Pri
!#2 N5513 P1959 LD 6 -1 FP BE Pri
!#2 N5514 P1960 LD 25 -1 Int BE Pri
!#2 N5515 P1961 LD 4 -1 Int BE Pri
!#2 N5516 P1960 LD 25 -1 Int BE Pri
!#2 N5517 P1961 LD 4 -1 Int BE Pri
!#2 N5518 P1962 DWLD 31 -1 Int BE Pri
!#2 N5519 P1963 LD 18 -1 Int BE Pri
!#2 N5520 P1962 DWLD 31 -1 Int BE Pri
!#2 N5521 P1963 LD 18 -1 Int BE Pri
!#2 N5522 P1964 LD 20 -1 Int BE Pri
!#2 N5523 P1965 LD 4 -1 Int BE Pri
!#2 N5524 P1966 LD 13 -1 Int BE Pri
!#2 N5525 P1967 LD 16 -1 FP BE Pri
!#2 N5526 P1968 LD 13 -1 Int BE Pri
!#2 N5527 P1969 LD 26 -1 Int BE Pri
!#2 N5528 P1970 SWAP 4 0xffffffff 0x100003b Int BE Pri
!#2 N5529 P1969 LD 26 -1 Int BE Pri
!#2 N5530 P1970 SWAP 4 0xffffffff 0x100003c Int BE Pri
!#2 N5531 P1971 MEMBAR
!#3 N5532 P1972 LD 28 -1 Int BE Pri
!#3 N5533 P1973 BLD 24 -1 FP BE Pri
!#3 N5534 P1973 BLD 25 -1 FP BE Pri
!#A N5533 N5534
!#3 N5535 P1973 BLD 26 -1 FP BE Pri
!#3 N5536 P1973 BLD 27 -1 FP BE Pri
!#3 N5537 P1974 LD 9 -1 Int BE Pri
!#3 N5538 P1972 LD 28 -1 Int BE Pri
!#3 N5539 P1973 BLD 24 -1 FP BE Pri
!#3 N5540 P1973 BLD 25 -1 FP BE Pri
!#A N5539 N5540
!#3 N5541 P1973 BLD 26 -1 FP BE Pri
!#3 N5542 P1973 BLD 27 -1 FP BE Pri
!#3 N5543 P1974 LD 9 -1 Int BE Pri
!#3 N5544 P1975 DWLD 19 -1 Int BE Pri
!#3 N5545 P1976 DWLD 27 -1 Int BE Pri
!#3 N5546 P1977 LD 7 -1 Int BE Pri
!#3 N5547 P1978 BLD 0 -1 FP BE Pri
!#3 N5548 P1978 BLD 1 -1 FP BE Pri
!#A N5547 N5548
!#3 N5549 P1978 BLD 2 -1 FP BE Pri
!#3 N5550 P1978 BLD 3 -1 FP BE Pri
!#3 N5551 P1979 LD 6 -1 Int BE Pri
!#3 N5552 P1980 DWLD 11 -1 Int BE Pri
!#3 N5553 P1981 BLD 16 -1 FP BE Pri
!#3 N5554 P1981 BLD 17 -1 FP BE Pri
!#A N5553 N5554
!#3 N5555 P1981 BLD 18 -1 FP BE Pri
!#3 N5556 P1981 BLD 19 -1 FP BE Pri
!#3 N5557 P1982 LD 0 -1 Int BE Pri
!#3 N5558 P1983 BLD 12 -1 FP BE Pri
!#3 N5559 P1983 BLD 13 -1 FP BE Pri
!#A N5558 N5559
!#3 N5560 P1983 BLD 14 -1 FP BE Pri
!#3 N5561 P1983 BLD 15 -1 FP BE Pri
!#3 N5562 P1984 LD 16 -1 Int BE Pri
!#3 N5563 P1985 LD 6 -1 Int BE Pri
!#3 N5564 P1986 DWLD 4 -1 Int BE Pri
!#3 N5565 P1986 DWLD 5 -1 Int BE Pri
!#A N5564 N5565
!#3 N5566 P1987 BLD 24 -1 FP BE Pri
!#3 N5567 P1987 BLD 25 -1 FP BE Pri
!#A N5566 N5567
!#3 N5568 P1987 BLD 26 -1 FP BE Pri
!#3 N5569 P1987 BLD 27 -1 FP BE Pri
!#3 N5570 P1988 DWLD 3 -1 Int LE Pri
!#3 N5571 P1989 LD 20 -1 Int BE Pri
!#3 N5572 P1990 LD 29 -1 Int BE Pri
!#3 N5573 P1991 LD 12 -1 FP BE Pri
!#3 N5574 P1992 LD 31 -1 Int BE Pri
!#3 N5575 P1993 BLD 24 -1 FP BE Pri
!#3 N5576 P1993 BLD 25 -1 FP BE Pri
!#A N5575 N5576
!#3 N5577 P1993 BLD 26 -1 FP BE Pri
!#3 N5578 P1993 BLD 27 -1 FP BE Pri
!#3 N5579 P1994 LD 5 -1 Int BE Pri
!#3 N5580 P1995 ST 23 0x1800001 Int BE Pri
!#3 N5581 P1996 LD 0 -1 Int BE Pri
!#3 N5582 P1994 LD 5 -1 Int BE Pri
!#3 N5583 P1995 ST 23 0x1800002 Int BE Pri
!#3 N5584 P1996 LD 0 -1 Int BE Pri
!#3 N5585 P1997 LD 20 -1 Int BE Pri
!#3 N5586 P1998 BLD 24 -1 FP BE Pri
!#3 N5587 P1998 BLD 25 -1 FP BE Pri
!#A N5586 N5587
!#3 N5588 P1998 BLD 26 -1 FP BE Pri
!#3 N5589 P1998 BLD 27 -1 FP BE Pri
!#3 N5590 P1999 LD 2 -1 Int BE Pri
!#3 N5591 P2000 DWLD 23 -1 Int BE Pri
!#3 N5592 P2001 LD 7 -1 Int BE Pri
!#3 N5593 P2000 DWLD 23 -1 Int BE Pri
!#3 N5594 P2001 LD 7 -1 Int BE Pri
!#3 N5595 P2002 DWLD 28 -1 Int BE Pri
!#3 N5596 P2002 DWLD 29 -1 Int BE Pri
!#A N5595 N5596
!#3 N5597 P2003 SWAP 30 0xffffffff 0x1800003 Int BE Pri
!#3 N5598 P2004 LD 8 -1 Int BE Pri
!#3 N5599 P2005 SWAP 11 0xffffffff 0x1800004 Int BE Pri
!#3 N5600 P2006 LD 26 -1 Int BE Pri
!#3 N5601 P2007 LD 0 -1 Int BE Pri
!#3 N5602 P2008 LD 18 -1 Int BE Pri
!#3 N5603 P2009 LD 4 -1 FP BE Pri
!#3 N5604 P2010 BLD 8 -1 FP BE Pri
!#3 N5605 P2010 BLD 9 -1 FP BE Pri
!#A N5604 N5605
!#3 N5606 P2010 BLD 10 -1 FP BE Pri
!#3 N5607 P2010 BLD 11 -1 FP BE Pri
!#3 N5610 P2012 BLD 20 -1 FP BE Pri
!#3 N5611 P2012 BLD 21 -1 FP BE Pri
!#A N5610 N5611
!#3 N5612 P2012 BLD 22 -1 FP BE Pri
!#3 N5613 P2012 BLD 23 -1 FP BE Pri
!#3 N5614 P2013 DWLD 28 -1 Int BE Pri
!#3 N5615 P2013 DWLD 29 -1 Int BE Pri
!#A N5614 N5615
!#3 N5616 P2014 DWLD 24 -1 Int BE Pri
!#3 N5617 P2014 DWLD 25 -1 Int BE Pri
!#A N5616 N5617
!#3 N5618 P2015 LD 7 -1 Int BE Pri
!#3 N5619 P2016 LD 18 -1 Int BE Pri
!#3 N5620 P2014 DWLD 24 -1 Int BE Pri
!#3 N5621 P2014 DWLD 25 -1 Int BE Pri
!#A N5620 N5621
!#3 N5622 P2015 LD 7 -1 Int BE Pri
!#3 N5623 P2016 LD 18 -1 Int BE Pri
!#3 N5624 P2017 DWST 22 0x1800005 Int BE Pri
!#3 N5625 P2018 LD 16 -1 Int BE Pri
!#3 N5626 P2019 LD 23 -1 Int BE Pri
!#3 N5627 P2020 DWLD 15 -1 Int BE Pri
!#3 N5628 P2021 DWLD 19 -1 FP BE Pri
!#3 N5629 P2022 LD 28 -1 Int BE Pri
!#3 N5630 P2020 DWLD 15 -1 Int BE Pri
!#3 N5631 P2021 DWLD 19 -1 FP BE Pri
!#3 N5632 P2022 LD 28 -1 Int BE Pri
!#3 N5633 P2023 DWST 2 0x1800006 Int BE Pri
!#3 N5634 P2023 DWST 2 0x1800007 Int BE Pri
!#3 N5635 P2024 LD 18 -1 Int BE Pri
!#3 N5636 P2025 LD 0 -1 Int BE Pri
!#3 N5637 P2026 LD 1 -1 Int BE Pri
!#3 N5638 P2027 MEMBAR
!#3 N5639 P2028 LD 0 -1 Int BE Pri
!#3 N5640 P2026 LD 1 -1 Int BE Pri
!#3 N5641 P2027 MEMBAR
!#3 N5642 P2028 LD 0 -1 Int BE Pri
!#3 N5643 P2029 LD 17 -1 Int BE Pri
!#3 N5644 P2030 LD 10 -1 Int BE Pri
!#3 N5646 P2032 DWLD 8 -1 Int BE Pri
!#3 N5647 P2032 DWLD 9 -1 Int BE Pri
!#A N5646 N5647
!#3 N5649 P2032 DWLD 8 -1 Int BE Pri
!#3 N5650 P2032 DWLD 9 -1 Int BE Pri
!#A N5649 N5650
!#3 N5651 P2033 DWLD 4 -1 Int BE Pri
!#3 N5652 P2033 DWLD 5 -1 Int BE Pri
!#A N5651 N5652
!#3 N5653 P2034 BLD 28 -1 FP BE Pri
!#3 N5654 P2034 BLD 29 -1 FP BE Pri
!#A N5653 N5654
!#3 N5655 P2034 BLD 30 -1 FP BE Pri
!#3 N5656 P2034 BLD 31 -1 FP BE Pri
!#3 N5657 P2035 BLD 16 -1 FP BE Pri
!#3 N5658 P2035 BLD 17 -1 FP BE Pri
!#A N5657 N5658
!#3 N5659 P2035 BLD 18 -1 FP BE Pri
!#3 N5660 P2035 BLD 19 -1 FP BE Pri
!#3 N5662 P2037 LD 29 -1 Int BE Pri
!#3 N5663 P2038 LD 23 -1 Int BE Pri
!#3 N5664 P2039 BLD 4 -1 FP BE Pri
!#3 N5665 P2039 BLD 5 -1 FP BE Pri
!#A N5664 N5665
!#3 N5666 P2039 BLD 6 -1 FP BE Pri
!#3 N5667 P2039 BLD 7 -1 FP BE Pri
!#3 N5668 P2039 BLD 4 -1 FP BE Pri
!#3 N5669 P2039 BLD 5 -1 FP BE Pri
!#A N5668 N5669
!#3 N5670 P2039 BLD 6 -1 FP BE Pri
!#3 N5671 P2039 BLD 7 -1 FP BE Pri
!#3 N5672 P2040 DWLD 12 -1 Int BE Pri
!#3 N5673 P2040 DWLD 13 -1 Int BE Pri
!#A N5672 N5673
!#3 N5674 P2040 DWLD 12 -1 Int BE Pri
!#3 N5675 P2040 DWLD 13 -1 Int BE Pri
!#A N5674 N5675
!#3 N5676 P2041 DWLD 0 -1 Int BE Pri
!#3 N5677 P2041 DWLD 1 -1 Int BE Pri
!#A N5676 N5677
!#3 N5678 P2042 BSTC 20 0x41000001 FP BE Pri
!#3 N5679 P2042 BSTC 21 0x41000002 FP BE Pri
!#A N5678 N5679
!#3 N5680 P2042 BSTC 22 0x41000003 FP BE Pri
!#3 N5681 P2042 BSTC 23 0x41000004 FP BE Pri
!#3 N5682 P2042 BSTC 20 0x41000005 FP BE Pri
!#3 N5683 P2042 BSTC 21 0x41000006 FP BE Pri
!#A N5682 N5683
!#3 N5684 P2042 BSTC 22 0x41000007 FP BE Pri
!#3 N5685 P2042 BSTC 23 0x41000008 FP BE Pri
!#3 N5686 P2043 DWLD 18 -1 FP BE Pri
!#3 N5687 P2044 LD 16 -1 Int BE Pri
!#3 N5688 P2045 LD 21 -1 Int BE Pri
!#3 N5689 P2046 DWLD 23 -1 Int BE Pri
!#3 N5690 P2047 LD 19 -1 Int BE Pri
!#3 N5691 P2048 DWLD 15 -1,0x0 Int BE Pri
!#3 N5692 P2048 CASX 15 -1,0x0 N5691 0x1800008 Int BE Pri
!#3 N5693 P2048 DWLD 15 -1,0x0 Int BE Pri
!#3 N5694 P2048 CASX 15 -1,0x0 N5693 0x1800009 Int BE Pri
!#3 N5695 P2049 LD 12 -1 Int BE Pri
!#3 N5696 P2050 BLD 12 -1 FP BE Pri
!#3 N5697 P2050 BLD 13 -1 FP BE Pri
!#A N5696 N5697
!#3 N5698 P2050 BLD 14 -1 FP BE Pri
!#3 N5699 P2050 BLD 15 -1 FP BE Pri
!#3 N5700 P2051 LD 9 -1 Int LE Pri
!#3 N5701 P2052 LD 18 -1 Int BE Pri
!#3 N5702 P2053 LD 7 -1 Int BE Pri
!#3 N5703 P2052 LD 18 -1 Int BE Pri
!#3 N5704 P2053 LD 7 -1 Int BE Pri
!#3 N5705 P2054 LD 22 -1 Int BE Pri
!#3 N5706 P2055 LD 26 -1 Int BE Pri
!#3 N5707 P2054 LD 22 -1 Int BE Pri
!#3 N5708 P2055 LD 26 -1 Int BE Pri
!#3 N5709 P2056 BLD 4 -1 FP BE Pri
!#3 N5710 P2056 BLD 5 -1 FP BE Pri
!#A N5709 N5710
!#3 N5711 P2056 BLD 6 -1 FP BE Pri
!#3 N5712 P2056 BLD 7 -1 FP BE Pri
!#3 N5713 P2057 ST 13 0x180000a Int BE Pri
!#3 N5714 P2058 MEMBAR
!#3 N5715 P2059 LD 20 -1 FP BE Pri
!#3 N5716 P2060 DWLD 11 -1 Int BE Pri
!#3 N5717 P2061 LD 9 -1 Int BE Pri
!#3 N5718 P2060 DWLD 11 -1 Int BE Pri
!#3 N5719 P2061 LD 9 -1 Int BE Pri
!#3 N5720 P2062 LD 5 -1 Int BE Pri
!#3 N5721 P2063 BLD 24 -1 FP BE Pri
!#3 N5722 P2063 BLD 25 -1 FP BE Pri
!#A N5721 N5722
!#3 N5723 P2063 BLD 26 -1 FP BE Pri
!#3 N5724 P2063 BLD 27 -1 FP BE Pri
!#3 N5725 P2064 LD 0 -1 Int BE Pri
!#3 N5726 P2062 LD 5 -1 Int BE Pri
!#3 N5727 P2063 BLD 24 -1 FP BE Pri
!#3 N5728 P2063 BLD 25 -1 FP BE Pri
!#A N5727 N5728
!#3 N5729 P2063 BLD 26 -1 FP BE Pri
!#3 N5730 P2063 BLD 27 -1 FP BE Pri
!#3 N5731 P2064 LD 0 -1 Int BE Pri
!#3 N5732 P2065 DWLD 4 -1 Int BE Pri
!#3 N5733 P2065 DWLD 5 -1 Int BE Pri
!#A N5732 N5733
!#3 N5734 P2066 BLD 4 -1 FP BE Pri
!#3 N5735 P2066 BLD 5 -1 FP BE Pri
!#A N5734 N5735
!#3 N5736 P2066 BLD 6 -1 FP BE Pri
!#3 N5737 P2066 BLD 7 -1 FP BE Pri
!#3 N5738 P2065 DWLD 4 -1 Int BE Pri
!#3 N5739 P2065 DWLD 5 -1 Int BE Pri
!#A N5738 N5739
!#3 N5740 P2066 BLD 4 -1 FP BE Pri
!#3 N5741 P2066 BLD 5 -1 FP BE Pri
!#A N5740 N5741
!#3 N5742 P2066 BLD 6 -1 FP BE Pri
!#3 N5743 P2066 BLD 7 -1 FP BE Pri
!#3 N5744 P2067 DWLD 24 -1 Int BE Pri
!#3 N5745 P2067 DWLD 25 -1 Int BE Pri
!#A N5744 N5745
!#3 N5746 P2068 DWLD 19 -1 Int BE Pri
!#3 N5747 P2069 LD 27 -1 Int BE Pri
!#3 N5748 P2070 MEMBAR
!#3 N5749 P2070 MEMBAR
!#3 N5750 P2071 SWAP 29 0xffffffff 0x180000b Int BE Pri
!#3 N5751 P2072 BLD 0 -1 FP BE Pri
!#3 N5752 P2072 BLD 1 -1 FP BE Pri
!#A N5751 N5752
!#3 N5753 P2072 BLD 2 -1 FP BE Pri
!#3 N5754 P2072 BLD 3 -1 FP BE Pri
!#3 N5755 P2073 LD 18 -1 Int BE Pri
!#3 N5756 P2074 LD 26 -1 Int BE Pri
!#3 N5757 P2075 ST 4 0x180000c Int BE Pri
!#3 N5758 P2076 LD 17 -1 Int BE Pri
!#3 N5759 P2074 LD 26 -1 Int BE Pri
!#3 N5760 P2075 ST 4 0x180000d Int BE Pri
!#3 N5761 P2076 LD 17 -1 Int BE Pri
!#3 N5762 P2077 ST 8 0x180000e Int BE Pri
!#3 N5763 P2078 LD 29 -1 Int BE Pri
!#3 N5765 P2080 LD 24 -1 Int LE Pri
!#3 N5766 P2081 BLD 8 -1 FP BE Pri
!#3 N5767 P2081 BLD 9 -1 FP BE Pri
!#A N5766 N5767
!#3 N5768 P2081 BLD 10 -1 FP BE Pri
!#3 N5769 P2081 BLD 11 -1 FP BE Pri
!#3 N5770 P2081 BLD 8 -1 FP BE Pri
!#3 N5771 P2081 BLD 9 -1 FP BE Pri
!#A N5770 N5771
!#3 N5772 P2081 BLD 10 -1 FP BE Pri
!#3 N5773 P2081 BLD 11 -1 FP BE Pri
!#3 N5774 P2082 BLD 12 -1 FP BE Pri
!#3 N5775 P2082 BLD 13 -1 FP BE Pri
!#A N5774 N5775
!#3 N5776 P2082 BLD 14 -1 FP BE Pri
!#3 N5777 P2082 BLD 15 -1 FP BE Pri
!#3 N5778 P2083 DWLD 15 -1,0x0 Int BE Pri
!#3 N5779 P2083 CASX 15 -1,0x0 N5778 0x180000f Int BE Pri
!#3 N5780 P2082 BLD 12 -1 FP BE Pri
!#3 N5781 P2082 BLD 13 -1 FP BE Pri
!#A N5780 N5781
!#3 N5782 P2082 BLD 14 -1 FP BE Pri
!#3 N5783 P2082 BLD 15 -1 FP BE Pri
!#3 N5784 P2083 DWLD 15 -1,0x0 Int BE Pri
!#3 N5785 P2083 CASX 15 -1,0x0 N5784 0x1800010 Int BE Pri
!#3 N5786 P2084 BLD 20 -1 FP BE Pri
!#3 N5787 P2084 BLD 21 -1 FP BE Pri
!#A N5786 N5787
!#3 N5788 P2084 BLD 22 -1 FP BE Pri
!#3 N5789 P2084 BLD 23 -1 FP BE Pri
!#3 N5790 P2085 DWLD 28 -1 Int BE Pri
!#3 N5791 P2085 DWLD 29 -1 Int BE Pri
!#A N5790 N5791
!#3 N5792 P2084 BLD 20 -1 FP BE Pri
!#3 N5793 P2084 BLD 21 -1 FP BE Pri
!#A N5792 N5793
!#3 N5794 P2084 BLD 22 -1 FP BE Pri
!#3 N5795 P2084 BLD 23 -1 FP BE Pri
!#3 N5796 P2085 DWLD 28 -1 Int BE Pri
!#3 N5797 P2085 DWLD 29 -1 Int BE Pri
!#A N5796 N5797
!#3 N5798 P2086 DWLD 30 -1 Int BE Pri
!#3 N5799 P2087 BLD 8 -1 FP BE Pri
!#3 N5800 P2087 BLD 9 -1 FP BE Pri
!#A N5799 N5800
!#3 N5801 P2087 BLD 10 -1 FP BE Pri
!#3 N5802 P2087 BLD 11 -1 FP BE Pri
!#3 N5803 P2088 LD 3 -1 Int BE Pri
!#3 N5804 P2086 DWLD 30 -1 Int BE Pri
!#3 N5805 P2087 BLD 8 -1 FP BE Pri
!#3 N5806 P2087 BLD 9 -1 FP BE Pri
!#A N5805 N5806
!#3 N5807 P2087 BLD 10 -1 FP BE Pri
!#3 N5808 P2087 BLD 11 -1 FP BE Pri
!#3 N5809 P2088 LD 3 -1 Int BE Pri
!#3 N5810 P2089 BLD 12 -1 FP BE Pri
!#3 N5811 P2089 BLD 13 -1 FP BE Pri
!#A N5810 N5811
!#3 N5812 P2089 BLD 14 -1 FP BE Pri
!#3 N5813 P2089 BLD 15 -1 FP BE Pri
!#3 N5814 P2090 BLD 0 -1 FP BE Pri
!#3 N5815 P2090 BLD 1 -1 FP BE Pri
!#A N5814 N5815
!#3 N5816 P2090 BLD 2 -1 FP BE Pri
!#3 N5817 P2090 BLD 3 -1 FP BE Pri
!#3 N5818 P2091 BLD 8 -1 FP BE Pri
!#3 N5819 P2091 BLD 9 -1 FP BE Pri
!#A N5818 N5819
!#3 N5820 P2091 BLD 10 -1 FP BE Pri
!#3 N5821 P2091 BLD 11 -1 FP BE Pri
!#3 N5822 P2092 LD 2 -1 Int BE Pri
!#3 N5823 P2093 LD 28 -1 Int BE Pri
!#3 N5825 P2095 BLD 12 -1 FP BE Pri
!#3 N5826 P2095 BLD 13 -1 FP BE Pri
!#A N5825 N5826
!#3 N5827 P2095 BLD 14 -1 FP BE Pri
!#3 N5828 P2095 BLD 15 -1 FP BE Pri
!#3 N5829 P2096 LD 23 -1 Int BE Pri
!#3 N5830 P2097 DWLD 19 -1 Int BE Pri
!#3 N5831 P2096 LD 23 -1 Int BE Pri
!#3 N5832 P2097 DWLD 19 -1 Int BE Pri
!#3 N5833 P2098 DWLD 27 -1 Int BE Pri
!#3 N5834 P2099 LD 15 -1 Int BE Pri
!#3 N5835 P2098 DWLD 27 -1 Int BE Pri
!#3 N5836 P2099 LD 15 -1 Int BE Pri
!#3 N5837 P2100 LD 13 -1 Int BE Pri
!#3 N5839 P2102 LD 28 -1 Int BE Pri
!#3 N5840 P2103 DWLD 2 -1 Int BE Pri
!#3 N5841 P2104 LD 1 -1 Int BE Pri
!#3 N5842 P2103 DWLD 2 -1 Int BE Pri
!#3 N5843 P2104 LD 1 -1 Int BE Pri
!#3 N5844 P2105 BLD 12 -1 FP BE Pri
!#3 N5845 P2105 BLD 13 -1 FP BE Pri
!#A N5844 N5845
!#3 N5846 P2105 BLD 14 -1 FP BE Pri
!#3 N5847 P2105 BLD 15 -1 FP BE Pri
!#3 N5848 P2106 BLD 28 -1 FP BE Pri
!#3 N5849 P2106 BLD 29 -1 FP BE Pri
!#A N5848 N5849
!#3 N5850 P2106 BLD 30 -1 FP BE Pri
!#3 N5851 P2106 BLD 31 -1 FP BE Pri
!#3 N5852 P2107 DWLD 20 -1 Int LE Pri
!#3 N5853 P2107 DWLD 21 -1 Int LE Pri
!#A N5852 N5853
!#3 N5854 P2107 CASX 20 -1 N5852 0x1800011 Int LE Pri
!#3 N5855 P2107 CASX 21 -1 N5853 0x1800012 Int LE Pri
!#A N5854 N5855
!#3 N5856 P2108 DWLD 3 -1 Int BE Pri
!#3 N5857 P2109 LD 8 -1 Int BE Pri
!#3 N5858 P2107 DWLD 20 -1 Int LE Pri
!#3 N5859 P2107 DWLD 21 -1 Int LE Pri
!#A N5858 N5859
!#3 N5860 P2107 CASX 20 -1 N5858 0x1800013 Int LE Pri
!#3 N5861 P2107 CASX 21 -1 N5859 0x1800014 Int LE Pri
!#A N5860 N5861
!#3 N5862 P2108 DWLD 3 -1 Int BE Pri
!#3 N5863 P2109 LD 8 -1 Int BE Pri
!#3 N5864 P2110 DWLD 27 -1 Int LE Pri
!#3 N5865 P2111 LD 2 -1 Int BE Pri
!#3 N5866 P2112 DWLD 30 -1 Int BE Pri
!#3 N5867 P2113 LD 8 -1 Int BE Pri
!#3 N5868 P2112 DWLD 30 -1 Int BE Pri
!#3 N5869 P2113 LD 8 -1 Int BE Pri
!#3 N5870 P2114 LD 15 -1 Int BE Pri
!#3 N5871 P2114 CAS 15 -1 N5870 0x1800015 Int BE Pri
!#3 N5872 P2115 BLD 8 -1 FP BE Pri
!#3 N5873 P2115 BLD 9 -1 FP BE Pri
!#A N5872 N5873
!#3 N5874 P2115 BLD 10 -1 FP BE Pri
!#3 N5875 P2115 BLD 11 -1 FP BE Pri
!#3 N5876 P2116 DWLD 3 -1 Int BE Pri
!#3 N5877 P2117 BLD 8 -1 FP BE Pri
!#3 N5878 P2117 BLD 9 -1 FP BE Pri
!#A N5877 N5878
!#3 N5879 P2117 BLD 10 -1 FP BE Pri
!#3 N5880 P2117 BLD 11 -1 FP BE Pri
!#3 N5881 P2118 LD 25 -1 Int BE Pri
!#3 N5882 P2116 DWLD 3 -1 Int BE Pri
!#3 N5883 P2117 BLD 8 -1 FP BE Pri
!#3 N5884 P2117 BLD 9 -1 FP BE Pri
!#A N5883 N5884
!#3 N5885 P2117 BLD 10 -1 FP BE Pri
!#3 N5886 P2117 BLD 11 -1 FP BE Pri
!#3 N5887 P2118 LD 25 -1 Int BE Pri
!#3 N5888 P2119 LD 8 -1 Int BE Pri
!#3 N5889 P2120 LD 3 -1 Int BE Pri
!#3 N5890 P2121 LD 8 -1 Int LE Pri
!#3 N5891 P2122 BLD 24 -1 FP BE Pri
!#3 N5892 P2122 BLD 25 -1 FP BE Pri
!#A N5891 N5892
!#3 N5893 P2122 BLD 26 -1 FP BE Pri
!#3 N5894 P2122 BLD 27 -1 FP BE Pri
!#3 N5895 P2123 LD 18 -1 Int BE Pri
!#3 N5896 P2124 LD 9 -1 Int BE Pri
!#3 N5897 P2125 DWLD 10 -1 Int BE Pri
!#3 N5898 P2126 DWLD 4 -1 Int BE Pri
!#3 N5899 P2126 DWLD 5 -1 Int BE Pri
!#A N5898 N5899
!#3 N5900 P2127 BLD 4 -1 FP BE Pri
!#3 N5901 P2127 BLD 5 -1 FP BE Pri
!#A N5900 N5901
!#3 N5902 P2127 BLD 6 -1 FP BE Pri
!#3 N5903 P2127 BLD 7 -1 FP BE Pri
!#3 N5904 P2126 DWLD 4 -1 Int BE Pri
!#3 N5905 P2126 DWLD 5 -1 Int BE Pri
!#A N5904 N5905
!#3 N5906 P2127 BLD 4 -1 FP BE Pri
!#3 N5907 P2127 BLD 5 -1 FP BE Pri
!#A N5906 N5907
!#3 N5908 P2127 BLD 6 -1 FP BE Pri
!#3 N5909 P2127 BLD 7 -1 FP BE Pri
!#3 N5910 P2128 BLD 28 -1 FP BE Pri
!#3 N5911 P2128 BLD 29 -1 FP BE Pri
!#A N5910 N5911
!#3 N5912 P2128 BLD 30 -1 FP BE Pri
!#3 N5913 P2128 BLD 31 -1 FP BE Pri
!#3 N5914 P2129 BLD 8 -1 FP BE Pri
!#3 N5915 P2129 BLD 9 -1 FP BE Pri
!#A N5914 N5915
!#3 N5916 P2129 BLD 10 -1 FP BE Pri
!#3 N5917 P2129 BLD 11 -1 FP BE Pri
!#3 N5918 P2128 BLD 28 -1 FP BE Pri
!#3 N5919 P2128 BLD 29 -1 FP BE Pri
!#A N5918 N5919
!#3 N5920 P2128 BLD 30 -1 FP BE Pri
!#3 N5921 P2128 BLD 31 -1 FP BE Pri
!#3 N5922 P2129 BLD 8 -1 FP BE Pri
!#3 N5923 P2129 BLD 9 -1 FP BE Pri
!#A N5922 N5923
!#3 N5924 P2129 BLD 10 -1 FP BE Pri
!#3 N5925 P2129 BLD 11 -1 FP BE Pri
!#3 N5926 P2130 LD 27 -1 Int BE Pri
!#3 N5927 P2130 CAS 27 -1 N5926 0x1800016 Int BE Pri
!#3 N5928 P2131 DWLD 0 -1 Int BE Pri
!#3 N5929 P2131 DWLD 1 -1 Int BE Pri
!#A N5928 N5929
!#3 N5930 P2132 DWLD 7 -1 Int BE Pri
!#3 N5931 P2133 DWLD 24 -1 Int BE Pri
!#3 N5932 P2133 DWLD 25 -1 Int BE Pri
!#A N5931 N5932
!#3 N5933 P2134 LD 1 -1 Int BE Pri
!#3 N5934 P2132 DWLD 7 -1 Int BE Pri
!#3 N5935 P2133 DWLD 24 -1 Int BE Pri
!#3 N5936 P2133 DWLD 25 -1 Int BE Pri
!#A N5935 N5936
!#3 N5937 P2134 LD 1 -1 Int BE Pri
!#3 N5938 P2135 BLD 8 -1 FP BE Pri
!#3 N5939 P2135 BLD 9 -1 FP BE Pri
!#A N5938 N5939
!#3 N5940 P2135 BLD 10 -1 FP BE Pri
!#3 N5941 P2135 BLD 11 -1 FP BE Pri
!#3 N5942 P2136 LD 6 -1 Int BE Pri
!#3 N5943 P2136 CAS 6 -1 N5942 0x1800017 Int BE Pri
!#3 N5944 P2137 ST 7 0x1800018 Int LE Pri
!#3 N5945 P2138 LD 19 -1 Int BE Pri
!#3 N5946 P2139 MEMBAR
!#3 N5947 P2140 LD 14 -1 Int BE Pri
!#3 N5948 P2141 LD 18 -1 Int LE Pri
!#3 N5949 P2142 DWLD 27 -1 FP BE Pri
!#3 N5950 P2143 LD 13 -1 Int BE Pri
!#3 N5951 P2144 DWLD 16 -1 Int BE Pri
!#3 N5952 P2144 DWLD 17 -1 Int BE Pri
!#A N5951 N5952
!#3 N5953 P2144 CASX 16 -1 N5951 0x1800019 Int BE Pri
!#3 N5954 P2144 CASX 17 -1 N5952 0x180001a Int BE Pri
!#A N5953 N5954
!#3 N5955 P2144 DWLD 16 -1 Int BE Pri
!#3 N5956 P2144 DWLD 17 -1 Int BE Pri
!#A N5955 N5956
!#3 N5957 P2144 CASX 16 -1 N5955 0x180001b Int BE Pri
!#3 N5958 P2144 CASX 17 -1 N5956 0x180001c Int BE Pri
!#A N5957 N5958
!#3 N5959 P2145 BLD 24 -1 FP BE Pri
!#3 N5960 P2145 BLD 25 -1 FP BE Pri
!#A N5959 N5960
!#3 N5961 P2145 BLD 26 -1 FP BE Pri
!#3 N5962 P2145 BLD 27 -1 FP BE Pri
!#3 N5963 P2146 BLD 20 -1 FP BE Pri
!#3 N5964 P2146 BLD 21 -1 FP BE Pri
!#A N5963 N5964
!#3 N5965 P2146 BLD 22 -1 FP BE Pri
!#3 N5966 P2146 BLD 23 -1 FP BE Pri
!#3 N5967 P2145 BLD 24 -1 FP BE Pri
!#3 N5968 P2145 BLD 25 -1 FP BE Pri
!#A N5967 N5968
!#3 N5969 P2145 BLD 26 -1 FP BE Pri
!#3 N5970 P2145 BLD 27 -1 FP BE Pri
!#3 N5971 P2146 BLD 20 -1 FP BE Pri
!#3 N5972 P2146 BLD 21 -1 FP BE Pri
!#A N5971 N5972
!#3 N5973 P2146 BLD 22 -1 FP BE Pri
!#3 N5974 P2146 BLD 23 -1 FP BE Pri
!#3 N5975 P2147 BLD 0 -1 FP BE Pri
!#3 N5976 P2147 BLD 1 -1 FP BE Pri
!#A N5975 N5976
!#3 N5977 P2147 BLD 2 -1 FP BE Pri
!#3 N5978 P2147 BLD 3 -1 FP BE Pri
!#3 N5979 P2147 BLD 0 -1 FP BE Pri
!#3 N5980 P2147 BLD 1 -1 FP BE Pri
!#A N5979 N5980
!#3 N5981 P2147 BLD 2 -1 FP BE Pri
!#3 N5982 P2147 BLD 3 -1 FP BE Pri
!#3 N5983 P2148 DWLD 2 -1 Int BE Pri
!#3 N5984 P2149 LD 27 -1 Int BE Pri
!#3 N5985 P2150 LD 2 -1 Int BE Pri
!#3 N5986 P2151 DWLD 28 -1 Int BE Pri
!#3 N5987 P2151 DWLD 29 -1 Int BE Pri
!#A N5986 N5987
!#3 N5988 P2152 LD 27 -1 Int BE Pri
!#3 N5989 P2153 BLD 24 -1 FP BE Pri
!#3 N5990 P2153 BLD 25 -1 FP BE Pri
!#A N5989 N5990
!#3 N5991 P2153 BLD 26 -1 FP BE Pri
!#3 N5992 P2153 BLD 27 -1 FP BE Pri
!#3 N5993 P2154 BLD 8 -1 FP BE Pri
!#3 N5994 P2154 BLD 9 -1 FP BE Pri
!#A N5993 N5994
!#3 N5995 P2154 BLD 10 -1 FP BE Pri
!#3 N5996 P2154 BLD 11 -1 FP BE Pri
!#3 N5997 P2155 LD 6 -1 Int BE Pri
!#3 N5998 P2156 LD 20 -1 Int BE Pri
!#3 N5999 P2154 BLD 8 -1 FP BE Pri
!#3 N6000 P2154 BLD 9 -1 FP BE Pri
!#A N5999 N6000
!#3 N6001 P2154 BLD 10 -1 FP BE Pri
!#3 N6002 P2154 BLD 11 -1 FP BE Pri
!#3 N6003 P2155 LD 6 -1 Int BE Pri
!#3 N6004 P2156 LD 20 -1 Int BE Pri
!#3 N6005 P2157 DWLD 18 -1 Int BE Pri
!#3 N6006 P2158 BLD 8 -1 FP BE Pri
!#3 N6007 P2158 BLD 9 -1 FP BE Pri
!#A N6006 N6007
!#3 N6008 P2158 BLD 10 -1 FP BE Pri
!#3 N6009 P2158 BLD 11 -1 FP BE Pri
!#3 N6010 P2159 LD 7 -1 Int BE Pri
!#3 N6011 P2157 DWLD 18 -1 Int BE Pri
!#3 N6012 P2158 BLD 8 -1 FP BE Pri
!#3 N6013 P2158 BLD 9 -1 FP BE Pri
!#A N6012 N6013
!#3 N6014 P2158 BLD 10 -1 FP BE Pri
!#3 N6015 P2158 BLD 11 -1 FP BE Pri
!#3 N6016 P2159 LD 7 -1 Int BE Pri
!#3 N6017 P2160 BLD 28 -1 FP BE Pri
!#3 N6018 P2160 BLD 29 -1 FP BE Pri
!#A N6017 N6018
!#3 N6019 P2160 BLD 30 -1 FP BE Pri
!#3 N6020 P2160 BLD 31 -1 FP BE Pri
!#3 N6021 P2161 LD 26 -1 Int BE Pri
!#3 N6022 P2162 LD 11 -1 Int BE Pri
!#3 N6023 P2163 DWLD 16 -1 Int BE Pri
!#3 N6024 P2163 DWLD 17 -1 Int BE Pri
!#A N6023 N6024
!#3 N6025 P2164 LD 28 -1 Int BE Pri
!#3 N6026 P2165 LD 1 -1 Int BE Pri
!#3 N6027 P2166 BLD 0 -1 FP BE Pri
!#3 N6028 P2166 BLD 1 -1 FP BE Pri
!#A N6027 N6028
!#3 N6029 P2166 BLD 2 -1 FP BE Pri
!#3 N6030 P2166 BLD 3 -1 FP BE Pri
!#3 N6031 P2167 DWLD 7 -1 Int BE Pri
!#3 N6032 P2168 LD 13 -1 Int BE Pri
!#3 N6033 P2166 BLD 0 -1 FP BE Pri
!#3 N6034 P2166 BLD 1 -1 FP BE Pri
!#A N6033 N6034
!#3 N6035 P2166 BLD 2 -1 FP BE Pri
!#3 N6036 P2166 BLD 3 -1 FP BE Pri
!#3 N6037 P2167 DWLD 7 -1 Int BE Pri
!#3 N6038 P2168 LD 13 -1 Int BE Pri
!#3 N6039 P2169 BLD 20 -1 FP BE Pri
!#3 N6040 P2169 BLD 21 -1 FP BE Pri
!#A N6039 N6040
!#3 N6041 P2169 BLD 22 -1 FP BE Pri
!#3 N6042 P2169 BLD 23 -1 FP BE Pri
!#3 N6043 P2170 BLD 16 -1 FP BE Pri
!#3 N6044 P2170 BLD 17 -1 FP BE Pri
!#A N6043 N6044
!#3 N6045 P2170 BLD 18 -1 FP BE Pri
!#3 N6046 P2170 BLD 19 -1 FP BE Pri
!#3 N6047 P2171 BLD 28 -1 FP BE Pri
!#3 N6048 P2171 BLD 29 -1 FP BE Pri
!#A N6047 N6048
!#3 N6049 P2171 BLD 30 -1 FP BE Pri
!#3 N6050 P2171 BLD 31 -1 FP BE Pri
!#3 N6051 P2172 BLD 12 -1 FP BE Pri
!#3 N6052 P2172 BLD 13 -1 FP BE Pri
!#A N6051 N6052
!#3 N6053 P2172 BLD 14 -1 FP BE Pri
!#3 N6054 P2172 BLD 15 -1 FP BE Pri
!#3 N6055 P2173 LD 30 -1 Int BE Pri
!#3 N6056 P2174 LD 20 -1 Int BE Pri
!#3 N6057 P2175 LD 29 -1 Int BE Pri
!#3 N6058 P2176 LD 19 -1 Int BE Pri
!#3 N6059 P2177 LD 27 -1 Int BE Pri
!#3 N6060 P2178 DWLD 8 -1 Int BE Pri
!#3 N6061 P2178 DWLD 9 -1 Int BE Pri
!#A N6060 N6061
!#3 N6062 P2179 LD 27 -1 Int BE Pri
!#3 N6063 P2180 BLD 16 -1 FP BE Pri
!#3 N6064 P2180 BLD 17 -1 FP BE Pri
!#A N6063 N6064
!#3 N6065 P2180 BLD 18 -1 FP BE Pri
!#3 N6066 P2180 BLD 19 -1 FP BE Pri
!#3 N6067 P2180 BLD 16 -1 FP BE Pri
!#3 N6068 P2180 BLD 17 -1 FP BE Pri
!#A N6067 N6068
!#3 N6069 P2180 BLD 18 -1 FP BE Pri
!#3 N6070 P2180 BLD 19 -1 FP BE Pri
!#3 N6071 P2181 DWLD 2 -1 Int BE Pri
!#3 N6072 P2182 LD 0 -1 Int BE Pri
!#3 N6073 P2183 LD 6 -1 FP BE Pri
!#3 N6074 P2184 LD 20 -1 Int BE Pri
!#3 N6075 P2185 LD 22 -1 Int BE Pri
!#3 N6076 P2183 LD 6 -1 FP BE Pri
!#3 N6077 P2184 LD 20 -1 Int BE Pri
!#3 N6078 P2185 LD 22 -1 Int BE Pri
!#3 N6079 P2186 DWLD 20 -1 Int BE Pri
!#3 N6080 P2186 DWLD 21 -1 Int BE Pri
!#A N6079 N6080
!#3 N6081 P2187 BLD 24 -1 FP BE Pri
!#3 N6082 P2187 BLD 25 -1 FP BE Pri
!#A N6081 N6082
!#3 N6083 P2187 BLD 26 -1 FP BE Pri
!#3 N6084 P2187 BLD 27 -1 FP BE Pri
!#3 N6085 P2188 MEMBAR
!#3 N6086 P2189 BLD 28 -1 FP BE Pri
!#3 N6087 P2189 BLD 29 -1 FP BE Pri
!#A N6086 N6087
!#3 N6088 P2189 BLD 30 -1 FP BE Pri
!#3 N6089 P2189 BLD 31 -1 FP BE Pri
!#3 N6090 P2188 MEMBAR
!#3 N6091 P2189 BLD 28 -1 FP BE Pri
!#3 N6092 P2189 BLD 29 -1 FP BE Pri
!#A N6091 N6092
!#3 N6093 P2189 BLD 30 -1 FP BE Pri
!#3 N6094 P2189 BLD 31 -1 FP BE Pri
!#3 N6095 P2190 BLD 4 -1 FP BE Pri
!#3 N6096 P2190 BLD 5 -1 FP BE Pri
!#A N6095 N6096
!#3 N6097 P2190 BLD 6 -1 FP BE Pri
!#3 N6098 P2190 BLD 7 -1 FP BE Pri
!#3 N6099 P2191 BLD 4 -1 FP BE Pri
!#3 N6100 P2191 BLD 5 -1 FP BE Pri
!#A N6099 N6100
!#3 N6101 P2191 BLD 6 -1 FP BE Pri
!#3 N6102 P2191 BLD 7 -1 FP BE Pri
!#3 N6103 P2190 BLD 4 -1 FP BE Pri
!#3 N6104 P2190 BLD 5 -1 FP BE Pri
!#A N6103 N6104
!#3 N6105 P2190 BLD 6 -1 FP BE Pri
!#3 N6106 P2190 BLD 7 -1 FP BE Pri
!#3 N6107 P2191 BLD 4 -1 FP BE Pri
!#3 N6108 P2191 BLD 5 -1 FP BE Pri
!#A N6107 N6108
!#3 N6109 P2191 BLD 6 -1 FP BE Pri
!#3 N6110 P2191 BLD 7 -1 FP BE Pri
!#3 N6111 P2192 BLD 12 -1 FP BE Pri
!#3 N6112 P2192 BLD 13 -1 FP BE Pri
!#A N6111 N6112
!#3 N6113 P2192 BLD 14 -1 FP BE Pri
!#3 N6114 P2192 BLD 15 -1 FP BE Pri
!#3 N6115 P2193 BLD 24 -1 FP BE Pri
!#3 N6116 P2193 BLD 25 -1 FP BE Pri
!#A N6115 N6116
!#3 N6117 P2193 BLD 26 -1 FP BE Pri
!#3 N6118 P2193 BLD 27 -1 FP BE Pri
!#3 N6119 P2192 BLD 12 -1 FP BE Pri
!#3 N6120 P2192 BLD 13 -1 FP BE Pri
!#A N6119 N6120
!#3 N6121 P2192 BLD 14 -1 FP BE Pri
!#3 N6122 P2192 BLD 15 -1 FP BE Pri
!#3 N6123 P2193 BLD 24 -1 FP BE Pri
!#3 N6124 P2193 BLD 25 -1 FP BE Pri
!#A N6123 N6124
!#3 N6125 P2193 BLD 26 -1 FP BE Pri
!#3 N6126 P2193 BLD 27 -1 FP BE Pri
!#3 N6127 P2194 BSTC 28 0x41000009 FP BE Pri
!#3 N6128 P2194 BSTC 29 0x4100000a FP BE Pri
!#A N6127 N6128
!#3 N6129 P2194 BSTC 30 0x4100000b FP BE Pri
!#3 N6130 P2194 BSTC 31 0x4100000c FP BE Pri
!#3 N6131 P2195 LD 8 -1 Int BE Pri
!#3 N6132 P2196 LD 17 -1 Int BE Pri
!#3 N6133 P2197 BLD 16 -1 FP BE Pri
!#3 N6134 P2197 BLD 17 -1 FP BE Pri
!#A N6133 N6134
!#3 N6135 P2197 BLD 18 -1 FP BE Pri
!#3 N6136 P2197 BLD 19 -1 FP BE Pri
!#3 N6137 P2197 BLD 16 -1 FP BE Pri
!#3 N6138 P2197 BLD 17 -1 FP BE Pri
!#A N6137 N6138
!#3 N6139 P2197 BLD 18 -1 FP BE Pri
!#3 N6140 P2197 BLD 19 -1 FP BE Pri
!#3 N6141 P2198 LD 6 -1 FP BE Pri
!#3 N6142 P2198 LD 6 -1 FP BE Pri
!#3 N6143 P2199 BLD 16 -1 FP BE Pri
!#3 N6144 P2199 BLD 17 -1 FP BE Pri
!#A N6143 N6144
!#3 N6145 P2199 BLD 18 -1 FP BE Pri
!#3 N6146 P2199 BLD 19 -1 FP BE Pri
!#3 N6147 P2200 LD 30 -1 Int BE Pri
!#3 N6148 P2201 BLD 0 -1 FP BE Pri
!#3 N6149 P2201 BLD 1 -1 FP BE Pri
!#A N6148 N6149
!#3 N6150 P2201 BLD 2 -1 FP BE Pri
!#3 N6151 P2201 BLD 3 -1 FP BE Pri
!#3 N6152 P2202 LD 18 -1 Int BE Pri
!#3 N6153 P2200 LD 30 -1 Int BE Pri
!#3 N6154 P2201 BLD 0 -1 FP BE Pri
!#3 N6155 P2201 BLD 1 -1 FP BE Pri
!#A N6154 N6155
!#3 N6156 P2201 BLD 2 -1 FP BE Pri
!#3 N6157 P2201 BLD 3 -1 FP BE Pri
!#3 N6158 P2202 LD 18 -1 Int BE Pri
!#3 N6159 P2203 BLD 24 -1 FP BE Pri
!#3 N6160 P2203 BLD 25 -1 FP BE Pri
!#A N6159 N6160
!#3 N6161 P2203 BLD 26 -1 FP BE Pri
!#3 N6162 P2203 BLD 27 -1 FP BE Pri
!#3 N6164 P2205 LD 29 -1 Int BE Pri
!#3 N6165 P2206 LD 29 -1 Int BE Pri
!#3 N6168 P2208 BLD 20 -1 FP BE Pri
!#3 N6169 P2208 BLD 21 -1 FP BE Pri
!#A N6168 N6169
!#3 N6170 P2208 BLD 22 -1 FP BE Pri
!#3 N6171 P2208 BLD 23 -1 FP BE Pri
!#3 N6173 P2208 BLD 20 -1 FP BE Pri
!#3 N6174 P2208 BLD 21 -1 FP BE Pri
!#A N6173 N6174
!#3 N6175 P2208 BLD 22 -1 FP BE Pri
!#3 N6176 P2208 BLD 23 -1 FP BE Pri
!#3 N6178 P2210 LD 6 -1 Int BE Pri
!#3 N6179 P2211 LD 17 -1 Int BE Pri
!#3 N6180 P2210 LD 6 -1 Int BE Pri
!#3 N6181 P2211 LD 17 -1 Int BE Pri
!#3 N6182 P2212 LD 31 -1 Int BE Pri
!#3 N6183 P2213 LD 19 -1 Int BE Pri
!#3 N6184 P2212 LD 31 -1 Int BE Pri
!#3 N6185 P2213 LD 19 -1 Int BE Pri
!#3 N6186 P2214 DWLD 16 -1 Int BE Pri
!#3 N6187 P2214 DWLD 17 -1 Int BE Pri
!#A N6186 N6187
!#3 N6188 P2215 LD 12 -1 Int BE Pri
!#3 N6189 P2216 LD 13 -1 Int BE Pri
!#3 N6190 P2217 DWLD 23 -1 Int BE Pri
!#3 N6192 P2219 LD 24 -1 Int LE Pri
!#3 N6193 P2217 DWLD 23 -1 Int BE Pri
!#3 N6195 P2219 LD 24 -1 Int LE Pri
!#3 N6196 P2220 BSTC 8 0x4100000d FP BE Pri
!#3 N6197 P2220 BSTC 9 0x4100000e FP BE Pri
!#A N6196 N6197
!#3 N6198 P2220 BSTC 10 0x4100000f FP BE Pri
!#3 N6199 P2220 BSTC 11 0x41000010 FP BE Pri
!#3 N6200 P2221 DWLD 19 -1 Int BE Pri
!#3 N6201 P2222 LD 29 -1 Int BE Pri
!#3 N6202 P2223 BLD 20 -1 FP BE Pri
!#3 N6203 P2223 BLD 21 -1 FP BE Pri
!#A N6202 N6203
!#3 N6204 P2223 BLD 22 -1 FP BE Pri
!#3 N6205 P2223 BLD 23 -1 FP BE Pri
!#3 N6207 P2225 BLD 4 -1 FP BE Pri
!#3 N6208 P2225 BLD 5 -1 FP BE Pri
!#A N6207 N6208
!#3 N6209 P2225 BLD 6 -1 FP BE Pri
!#3 N6210 P2225 BLD 7 -1 FP BE Pri
!#3 N6211 P2226 LD 18 -1 Int BE Pri
!#3 N6212 P2227 LD 10 -1 Int BE Pri
!#3 N6213 P2226 LD 18 -1 Int BE Pri
!#3 N6214 P2227 LD 10 -1 Int BE Pri
!#3 N6215 P2228 DWLD 22 -1 Int BE Pri
!#3 N6216 P2229 LD 25 -1 Int BE Pri
!#3 N6217 P2228 DWLD 22 -1 Int BE Pri
!#3 N6218 P2229 LD 25 -1 Int BE Pri
!#3 N6219 P2230 LD 24 -1 Int BE Pri
!#3 N6220 P2231 LD 1 -1 Int BE Pri
!#3 N6221 P2232 BLD 24 -1 FP BE Pri
!#3 N6222 P2232 BLD 25 -1 FP BE Pri
!#A N6221 N6222
!#3 N6223 P2232 BLD 26 -1 FP BE Pri
!#3 N6224 P2232 BLD 27 -1 FP BE Pri
!#3 N6225 P2233 ST 21 0x180001d Int BE Pri
!#3 N6226 P2232 BLD 24 -1 FP BE Pri
!#3 N6227 P2232 BLD 25 -1 FP BE Pri
!#A N6226 N6227
!#3 N6228 P2232 BLD 26 -1 FP BE Pri
!#3 N6229 P2232 BLD 27 -1 FP BE Pri
!#3 N6230 P2233 ST 21 0x180001e Int BE Pri
!#3 N6231 P2234 BLD 8 -1 FP BE Pri
!#3 N6232 P2234 BLD 9 -1 FP BE Pri
!#A N6231 N6232
!#3 N6233 P2234 BLD 10 -1 FP BE Pri
!#3 N6234 P2234 BLD 11 -1 FP BE Pri
!#3 N6235 P2235 BLD 20 -1 FP BE Pri
!#3 N6236 P2235 BLD 21 -1 FP BE Pri
!#A N6235 N6236
!#3 N6237 P2235 BLD 22 -1 FP BE Pri
!#3 N6238 P2235 BLD 23 -1 FP BE Pri
!#3 N6239 P2234 BLD 8 -1 FP BE Pri
!#3 N6240 P2234 BLD 9 -1 FP BE Pri
!#A N6239 N6240
!#3 N6241 P2234 BLD 10 -1 FP BE Pri
!#3 N6242 P2234 BLD 11 -1 FP BE Pri
!#3 N6243 P2235 BLD 20 -1 FP BE Pri
!#3 N6244 P2235 BLD 21 -1 FP BE Pri
!#A N6243 N6244
!#3 N6245 P2235 BLD 22 -1 FP BE Pri
!#3 N6246 P2235 BLD 23 -1 FP BE Pri
!#3 N6247 P2236 DWLD 15 -1 Int BE Pri
!#3 N6248 P2237 LD 26 -1 Int BE Pri
!#3 N6250 P2239 LD 9 -1 Int BE Pri
!#3 N6251 P2240 LD 9 -1 Int BE Pri
!#3 N6252 P2241 DWLD 16 -1 FP BE Pri
!#3 N6253 P2241 DWLD 17 -1 FP BE Pri
!#A N6252 N6253
!#3 N6254 P2242 DWLD 4 -1 Int BE Pri
!#3 N6255 P2242 DWLD 5 -1 Int BE Pri
!#A N6254 N6255
!#3 N6256 P2241 DWLD 16 -1 FP BE Pri
!#3 N6257 P2241 DWLD 17 -1 FP BE Pri
!#A N6256 N6257
!#3 N6258 P2242 DWLD 4 -1 Int BE Pri
!#3 N6259 P2242 DWLD 5 -1 Int BE Pri
!#A N6258 N6259
!#3 N6260 P2243 LD 30 -1 Int BE Pri
!#3 N6261 P2244 LD 2 -1 Int BE Pri
!#3 N6262 P2245 DWLD 28 -1 Int BE Pri
!#3 N6263 P2245 DWLD 29 -1 Int BE Pri
!#A N6262 N6263
!#3 N6264 P2245 DWLD 28 -1 Int BE Pri
!#3 N6265 P2245 DWLD 29 -1 Int BE Pri
!#A N6264 N6265
!#3 N6266 P2246 DWLD 10 -1 Int BE Pri
!#3 N6267 P2247 LD 21 -1 Int BE Pri
!#3 N6269 P2249 BLD 0 -1 FP BE Pri
!#3 N6270 P2249 BLD 1 -1 FP BE Pri
!#A N6269 N6270
!#3 N6271 P2249 BLD 2 -1 FP BE Pri
!#3 N6272 P2249 BLD 3 -1 FP BE Pri
!#3 N6274 P2249 BLD 0 -1 FP BE Pri
!#3 N6275 P2249 BLD 1 -1 FP BE Pri
!#A N6274 N6275
!#3 N6276 P2249 BLD 2 -1 FP BE Pri
!#3 N6277 P2249 BLD 3 -1 FP BE Pri
!#3 N6278 P2250 DWLD 7 -1 Int BE Pri
!#3 N6279 P2251 LD 25 -1 Int BE Pri
!#3 N6280 P2252 LD 18 -1 Int BE Pri
!#3 N6281 P2253 BLD 8 -1 FP BE Pri
!#3 N6282 P2253 BLD 9 -1 FP BE Pri
!#A N6281 N6282
!#3 N6283 P2253 BLD 10 -1 FP BE Pri
!#3 N6284 P2253 BLD 11 -1 FP BE Pri
!#3 N6285 P2254 LD 0 -1 Int BE Pri
!#3 N6286 P2252 LD 18 -1 Int BE Pri
!#3 N6287 P2253 BLD 8 -1 FP BE Pri
!#3 N6288 P2253 BLD 9 -1 FP BE Pri
!#A N6287 N6288
!#3 N6289 P2253 BLD 10 -1 FP BE Pri
!#3 N6290 P2253 BLD 11 -1 FP BE Pri
!#3 N6291 P2254 LD 0 -1 Int BE Pri
!#3 N6292 P2255 SWAP 31 0xffffffff 0x180001f Int BE Pri
!#3 N6293 P2256 DWLD 24 -1 Int BE Pri
!#3 N6294 P2256 DWLD 25 -1 Int BE Pri
!#A N6293 N6294
!#3 N6295 P2257 LD 16 -1 Int BE Pri
!#3 N6296 P2255 SWAP 31 0xffffffff 0x1800020 Int BE Pri
!#3 N6297 P2256 DWLD 24 -1 Int BE Pri
!#3 N6298 P2256 DWLD 25 -1 Int BE Pri
!#A N6297 N6298
!#3 N6299 P2257 LD 16 -1 Int BE Pri
!#3 N6300 P2258 BLD 24 -1 FP BE Pri
!#3 N6301 P2258 BLD 25 -1 FP BE Pri
!#A N6300 N6301
!#3 N6302 P2258 BLD 26 -1 FP BE Pri
!#3 N6303 P2258 BLD 27 -1 FP BE Pri
!#3 N6304 P2258 BLD 24 -1 FP BE Pri
!#3 N6305 P2258 BLD 25 -1 FP BE Pri
!#A N6304 N6305
!#3 N6306 P2258 BLD 26 -1 FP BE Pri
!#3 N6307 P2258 BLD 27 -1 FP BE Pri
!#3 N6308 P2259 LD 27 -1 Int BE Pri
!#3 N6309 P2260 DWLD 27 -1 Int BE Pri
!#3 N6310 P2259 LD 27 -1 Int BE Pri
!#3 N6311 P2260 DWLD 27 -1 Int BE Pri
!#3 N6312 P2261 DWLD 4 -1 Int BE Pri
!#3 N6313 P2261 DWLD 5 -1 Int BE Pri
!#A N6312 N6313
!#3 N6314 P2261 CASX 4 -1 N6312 0x1800021 Int BE Pri
!#3 N6315 P2261 CASX 5 -1 N6313 0x1800022 Int BE Pri
!#A N6314 N6315
!#3 N6316 P2262 DWLD 28 -1 Int BE Pri
!#3 N6317 P2262 DWLD 29 -1 Int BE Pri
!#A N6316 N6317
!#3 N6318 P2263 DWLD 8 -1 Int BE Pri
!#3 N6319 P2263 DWLD 9 -1 Int BE Pri
!#A N6318 N6319
!#3 N6320 P2262 DWLD 28 -1 Int BE Pri
!#3 N6321 P2262 DWLD 29 -1 Int BE Pri
!#A N6320 N6321
!#3 N6322 P2263 DWLD 8 -1 Int BE Pri
!#3 N6323 P2263 DWLD 9 -1 Int BE Pri
!#A N6322 N6323
!#3 N6324 P2264 BLD 0 -1 FP BE Pri
!#3 N6325 P2264 BLD 1 -1 FP BE Pri
!#A N6324 N6325
!#3 N6326 P2264 BLD 2 -1 FP BE Pri
!#3 N6327 P2264 BLD 3 -1 FP BE Pri
!#3 N6328 P2265 LD 20 -1 Int BE Pri
!#3 N6329 P2266 LD 16 -1 Int BE Pri
!#3 N6330 P2267 DWLD 15 -1 Int BE Pri
!#3 N6331 P2268 BLD 0 -1 FP BE Pri
!#3 N6332 P2268 BLD 1 -1 FP BE Pri
!#A N6331 N6332
!#3 N6333 P2268 BLD 2 -1 FP BE Pri
!#3 N6334 P2268 BLD 3 -1 FP BE Pri
!#3 N6335 P2269 LD 31 -1 Int BE Pri
!#3 N6336 P2267 DWLD 15 -1 Int BE Pri
!#3 N6337 P2268 BLD 0 -1 FP BE Pri
!#3 N6338 P2268 BLD 1 -1 FP BE Pri
!#A N6337 N6338
!#3 N6339 P2268 BLD 2 -1 FP BE Pri
!#3 N6340 P2268 BLD 3 -1 FP BE Pri
!#3 N6341 P2269 LD 31 -1 Int BE Pri
!#3 N6342 P2270 DWLD 24 -1 Int BE Pri
!#3 N6343 P2270 DWLD 25 -1 Int BE Pri
!#A N6342 N6343
!#3 N6344 P2271 LD 11 -1 Int BE Pri
!#3 N6345 P2271 CAS 11 -1 N6344 0x1800023 Int BE Pri
!#3 N6346 P2270 DWLD 24 -1 Int BE Pri
!#3 N6347 P2270 DWLD 25 -1 Int BE Pri
!#A N6346 N6347
!#3 N6348 P2271 LD 11 -1 Int BE Pri
!#3 N6349 P2271 CAS 11 -1 N6348 0x1800024 Int BE Pri
!#3 N6350 P2272 LD 31 -1 Int LE Pri
!#3 N6351 P2273 LD 31 -1 Int BE Pri
!#3 N6352 P2272 LD 31 -1 Int LE Pri
!#3 N6353 P2273 LD 31 -1 Int BE Pri
!#3 N6354 P2274 LD 9 -1 Int BE Pri
!#3 N6355 P2275 DWLD 18 -1 FP BE Pri
!#3 N6356 P2276 LD 17 -1 Int BE Pri
!#3 N6357 P2277 DWLD 27 -1 Int BE Pri
!#3 N6358 P2278 DWLD 15 -1 Int BE Pri
!#3 N6359 P2279 BSTC 12 0x41000011 FP BE Pri
!#3 N6360 P2279 BSTC 13 0x41000012 FP BE Pri
!#A N6359 N6360
!#3 N6361 P2279 BSTC 14 0x41000013 FP BE Pri
!#3 N6362 P2279 BSTC 15 0x41000014 FP BE Pri
!#3 N6363 P2280 BLD 0 -1 FP BE Pri
!#3 N6364 P2280 BLD 1 -1 FP BE Pri
!#A N6363 N6364
!#3 N6365 P2280 BLD 2 -1 FP BE Pri
!#3 N6366 P2280 BLD 3 -1 FP BE Pri
!#3 N6367 P2279 BSTC 12 0x41000015 FP BE Pri
!#3 N6368 P2279 BSTC 13 0x41000016 FP BE Pri
!#A N6367 N6368
!#3 N6369 P2279 BSTC 14 0x41000017 FP BE Pri
!#3 N6370 P2279 BSTC 15 0x41000018 FP BE Pri
!#3 N6371 P2280 BLD 0 -1 FP BE Pri
!#3 N6372 P2280 BLD 1 -1 FP BE Pri
!#A N6371 N6372
!#3 N6373 P2280 BLD 2 -1 FP BE Pri
!#3 N6374 P2280 BLD 3 -1 FP BE Pri
!#3 N6375 P2281 BLD 4 -1 FP BE Pri
!#3 N6376 P2281 BLD 5 -1 FP BE Pri
!#A N6375 N6376
!#3 N6377 P2281 BLD 6 -1 FP BE Pri
!#3 N6378 P2281 BLD 7 -1 FP BE Pri
!#3 N6379 P2282 LD 10 -1 Int BE Pri
!#3 N6380 P2283 LD 23 -1 Int BE Pri
!#3 N6381 P2281 BLD 4 -1 FP BE Pri
!#3 N6382 P2281 BLD 5 -1 FP BE Pri
!#A N6381 N6382
!#3 N6383 P2281 BLD 6 -1 FP BE Pri
!#3 N6384 P2281 BLD 7 -1 FP BE Pri
!#3 N6385 P2282 LD 10 -1 Int BE Pri
!#3 N6386 P2283 LD 23 -1 Int BE Pri
!#3 N6387 P2284 BLD 0 -1 FP BE Pri
!#3 N6388 P2284 BLD 1 -1 FP BE Pri
!#A N6387 N6388
!#3 N6389 P2284 BLD 2 -1 FP BE Pri
!#3 N6390 P2284 BLD 3 -1 FP BE Pri
!#3 N6391 P2285 DWLD 30 -1 Int BE Pri
!#3 N6392 P2286 LD 24 -1 Int BE Pri
!#3 N6393 P2287 DWLD 4 -1 Int BE Pri
!#3 N6394 P2287 DWLD 5 -1 Int BE Pri
!#A N6393 N6394
!#3 N6395 P2288 BLD 16 -1 FP BE Pri
!#3 N6396 P2288 BLD 17 -1 FP BE Pri
!#A N6395 N6396
!#3 N6397 P2288 BLD 18 -1 FP BE Pri
!#3 N6398 P2288 BLD 19 -1 FP BE Pri
!#3 N6399 P2289 DWLD 31 -1 Int BE Pri
!#3 N6400 P2290 LD 29 -1 Int BE Pri
!#3 N6401 P2291 DWLD 7 -1 Int BE Pri
!#3 N6402 P2292 LD 15 -1 Int BE Pri
!#3 N6403 P2291 DWLD 7 -1 Int BE Pri
!#3 N6404 P2292 LD 15 -1 Int BE Pri
!#3 N6405 P2293 LD 12 -1 Int BE Pri
!#3 N6406 P2294 LD 9 -1 Int BE Pri
!#3 N6407 P2295 BLD 12 -1 FP BE Pri
!#3 N6408 P2295 BLD 13 -1 FP BE Pri
!#A N6407 N6408
!#3 N6409 P2295 BLD 14 -1 FP BE Pri
!#3 N6410 P2295 BLD 15 -1 FP BE Pri
!#3 N6411 P2296 DWLD 8 -1 Int BE Pri
!#3 N6412 P2296 DWLD 9 -1 Int BE Pri
!#A N6411 N6412
!#3 N6413 P2297 DWLD 12 -1 Int BE Pri
!#3 N6414 P2297 DWLD 13 -1 Int BE Pri
!#A N6413 N6414
!#3 N6415 P2298 BLD 28 -1 FP BE Pri
!#3 N6416 P2298 BLD 29 -1 FP BE Pri
!#A N6415 N6416
!#3 N6417 P2298 BLD 30 -1 FP BE Pri
!#3 N6418 P2298 BLD 31 -1 FP BE Pri
!#3 N6419 P2298 BLD 28 -1 FP BE Pri
!#3 N6420 P2298 BLD 29 -1 FP BE Pri
!#A N6419 N6420
!#3 N6421 P2298 BLD 30 -1 FP BE Pri
!#3 N6422 P2298 BLD 31 -1 FP BE Pri
!#3 N6423 P2299 DWST 4 0x1800025 Int BE Pri
!#3 N6424 P2299 DWST 5 0x1800026 Int BE Pri
!#A N6423 N6424
!#3 N6425 P2300 LD 22 -1 Int BE Pri
!#3 N6426 P2301 LD 2 -1 Int BE Pri
!#3 N6427 P2299 DWST 4 0x1800027 Int BE Pri
!#3 N6428 P2299 DWST 5 0x1800028 Int BE Pri
!#A N6427 N6428
!#3 N6429 P2300 LD 22 -1 Int BE Pri
!#3 N6430 P2301 LD 2 -1 Int BE Pri
!#3 N6431 P2302 BLD 20 -1 FP BE Pri
!#3 N6432 P2302 BLD 21 -1 FP BE Pri
!#A N6431 N6432
!#3 N6433 P2302 BLD 22 -1 FP BE Pri
!#3 N6434 P2302 BLD 23 -1 FP BE Pri
!#3 N6435 P2303 DWLD 28 -1 Int BE Pri
!#3 N6436 P2303 DWLD 29 -1 Int BE Pri
!#A N6435 N6436
!#3 N6437 P2304 BLD 16 -1 FP BE Pri
!#3 N6438 P2304 BLD 17 -1 FP BE Pri
!#A N6437 N6438
!#3 N6439 P2304 BLD 18 -1 FP BE Pri
!#3 N6440 P2304 BLD 19 -1 FP BE Pri
!#3 N6442 P2306 BLD 0 -1 FP BE Pri
!#3 N6443 P2306 BLD 1 -1 FP BE Pri
!#A N6442 N6443
!#3 N6444 P2306 BLD 2 -1 FP BE Pri
!#3 N6445 P2306 BLD 3 -1 FP BE Pri
!#3 N6447 P2306 BLD 0 -1 FP BE Pri
!#3 N6448 P2306 BLD 1 -1 FP BE Pri
!#A N6447 N6448
!#3 N6449 P2306 BLD 2 -1 FP BE Pri
!#3 N6450 P2306 BLD 3 -1 FP BE Pri
!#3 N6452 P2308 BLD 4 -1 FP BE Pri
!#3 N6453 P2308 BLD 5 -1 FP BE Pri
!#A N6452 N6453
!#3 N6454 P2308 BLD 6 -1 FP BE Pri
!#3 N6455 P2308 BLD 7 -1 FP BE Pri
!#3 N6456 P2308 BLD 4 -1 FP BE Pri
!#3 N6457 P2308 BLD 5 -1 FP BE Pri
!#A N6456 N6457
!#3 N6458 P2308 BLD 6 -1 FP BE Pri
!#3 N6459 P2308 BLD 7 -1 FP BE Pri
!#3 N6460 P2309 DWLD 12 -1 Int BE Pri
!#3 N6461 P2309 DWLD 13 -1 Int BE Pri
!#A N6460 N6461
!#3 N6462 P2310 LD 23 -1 Int BE Pri
!#3 N6463 P2311 LD 23 -1 Int BE Pri
!#3 N6464 P2309 DWLD 12 -1 Int BE Pri
!#3 N6465 P2309 DWLD 13 -1 Int BE Pri
!#A N6464 N6465
!#3 N6466 P2310 LD 23 -1 Int BE Pri
!#3 N6467 P2311 LD 23 -1 Int BE Pri
!#3 N6468 P2312 LD 2 -1 Int BE Pri
!#3 N6469 P2313 DWLD 6 -1 Int BE Pri
!#3 N6470 P2314 DWLD 0 -1 FP BE Pri
!#3 N6471 P2314 DWLD 1 -1 FP BE Pri
!#A N6470 N6471
!#3 N6472 P2314 DWLD 0 -1 FP BE Pri
!#3 N6473 P2314 DWLD 1 -1 FP BE Pri
!#A N6472 N6473
!#3 N6474 P2315 LD 9 -1 Int BE Pri
!#3 N6475 P2316 LD 11 -1 Int BE Pri
!#3 N6476 P2317 BLD 4 -1 FP BE Pri
!#3 N6477 P2317 BLD 5 -1 FP BE Pri
!#A N6476 N6477
!#3 N6478 P2317 BLD 6 -1 FP BE Pri
!#3 N6479 P2317 BLD 7 -1 FP BE Pri
!#3 N6480 P2318 LD 21 -1 Int BE Pri
!#3 N6481 P2319 LD 17 -1 Int BE Pri
!#3 N6482 P2320 BLD 12 -1 FP BE Pri
!#3 N6483 P2320 BLD 13 -1 FP BE Pri
!#A N6482 N6483
!#3 N6484 P2320 BLD 14 -1 FP BE Pri
!#3 N6485 P2320 BLD 15 -1 FP BE Pri
!#3 N6486 P2321 LD 9 -1 Int BE Pri
!#3 N6487 P2322 LD 3 -1 Int BE Pri
!#3 N6488 P2323 LD 0 -1 Int BE Pri
!#3 N6489 P2324 LD 19 -1 Int BE Pri
!#3 N6491 P2326 DWLD 6 -1,0x0 Int BE Pri
!#3 N6492 P2326 CASX 6 -1,0x0 N6491 0x1800029 Int BE Pri
!#3 N6494 P2326 DWLD 6 -1,0x0 Int BE Pri
!#3 N6495 P2326 CASX 6 -1,0x0 N6494 0x180002a Int BE Pri
!#3 N6496 P2327 DWLD 6 -1 Int BE Pri
!#3 N6497 P2328 LD 5 -1 Int BE Pri
!#3 N6498 P2327 DWLD 6 -1 Int BE Pri
!#3 N6499 P2328 LD 5 -1 Int BE Pri
!#3 N6500 P2329 BLD 4 -1 FP BE Pri
!#3 N6501 P2329 BLD 5 -1 FP BE Pri
!#A N6500 N6501
!#3 N6502 P2329 BLD 6 -1 FP BE Pri
!#3 N6503 P2329 BLD 7 -1 FP BE Pri
!#3 N6504 P2330 LD 22 -1 FP BE Pri
!#3 N6506 P2332 BLD 8 -1 FP BE Pri
!#3 N6507 P2332 BLD 9 -1 FP BE Pri
!#A N6506 N6507
!#3 N6508 P2332 BLD 10 -1 FP BE Pri
!#3 N6509 P2332 BLD 11 -1 FP BE Pri
!#3 N6510 P2333 DWLD 18 -1 Int BE Pri
!#3 N6511 P2334 LD 15 -1 Int BE Pri
!#3 N6512 P2335 LD 1 -1 Int BE Pri
!#3 N6513 P2336 LD 12 -1 Int BE Pri
!#3 N6514 P2335 LD 1 -1 Int BE Pri
!#3 N6515 P2336 LD 12 -1 Int BE Pri
!#3 N6516 P2337 DWLD 23 -1 Int BE Pri
!#3 N6517 P2338 DWLD 16 -1 Int BE Pri
!#3 N6518 P2338 DWLD 17 -1 Int BE Pri
!#A N6517 N6518
!#3 N6519 P2339 LD 31 -1 Int BE Pri
!#3 N6520 P2337 DWLD 23 -1 Int BE Pri
!#3 N6521 P2338 DWLD 16 -1 Int BE Pri
!#3 N6522 P2338 DWLD 17 -1 Int BE Pri
!#A N6521 N6522
!#3 N6523 P2339 LD 31 -1 Int BE Pri
!#3 N6525 P2341 BLD 8 -1 FP BE Pri
!#3 N6526 P2341 BLD 9 -1 FP BE Pri
!#A N6525 N6526
!#3 N6527 P2341 BLD 10 -1 FP BE Pri
!#3 N6528 P2341 BLD 11 -1 FP BE Pri
!#3 N6529 P2342 LD 17 -1 Int BE Pri
!#3 N6530 P2343 LD 9 -1 Int BE Pri
!#3 N6531 P2341 BLD 8 -1 FP BE Pri
!#3 N6532 P2341 BLD 9 -1 FP BE Pri
!#A N6531 N6532
!#3 N6533 P2341 BLD 10 -1 FP BE Pri
!#3 N6534 P2341 BLD 11 -1 FP BE Pri
!#3 N6535 P2342 LD 17 -1 Int BE Pri
!#3 N6536 P2343 LD 9 -1 Int BE Pri
!#3 N6538 P2345 DWLD 19 -1 Int BE Pri
!#3 N6539 P2346 LD 24 -1 Int BE Pri
!#3 N6540 P2345 DWLD 19 -1 Int BE Pri
!#3 N6541 P2346 LD 24 -1 Int BE Pri
!#3 N6542 P2347 LD 28 -1 Int BE Pri
!#3 N6543 P2347 CAS 28 -1 N6542 0x180002b Int BE Pri
!#3 N6544 P2348 DWLD 7 -1 Int BE Pri
!#3 N6545 P2349 LD 2 -1 Int BE Pri
!#3 N6547 P2351 DWLD 3 -1 FP BE Pri
!#3 N6549 P2351 DWLD 3 -1 FP BE Pri
!#3 N6550 P2352 DWLD 20 -1 Int LE Pri
!#3 N6551 P2352 DWLD 21 -1 Int LE Pri
!#A N6550 N6551
!#3 N6552 P2353 LD 1 -1 FP BE Pri
!#3 N6553 P2354 LD 30 -1 FP BE Pri
!#3 N6554 P2355 BLD 4 -1 FP BE Pri
!#3 N6555 P2355 BLD 5 -1 FP BE Pri
!#A N6554 N6555
!#3 N6556 P2355 BLD 6 -1 FP BE Pri
!#3 N6557 P2355 BLD 7 -1 FP BE Pri
!#3 N6558 P2356 BLD 28 -1 FP BE Pri
!#3 N6559 P2356 BLD 29 -1 FP BE Pri
!#A N6558 N6559
!#3 N6560 P2356 BLD 30 -1 FP BE Pri
!#3 N6561 P2356 BLD 31 -1 FP BE Pri
!#3 N6562 P2355 BLD 4 -1 FP BE Pri
!#3 N6563 P2355 BLD 5 -1 FP BE Pri
!#A N6562 N6563
!#3 N6564 P2355 BLD 6 -1 FP BE Pri
!#3 N6565 P2355 BLD 7 -1 FP BE Pri
!#3 N6566 P2356 BLD 28 -1 FP BE Pri
!#3 N6567 P2356 BLD 29 -1 FP BE Pri
!#A N6566 N6567
!#3 N6568 P2356 BLD 30 -1 FP BE Pri
!#3 N6569 P2356 BLD 31 -1 FP BE Pri
!#3 N6570 P2357 DWLD 30 -1 Int BE Pri
!#3 N6571 P2358 LD 24 -1 Int BE Pri
!#3 N6573 P2360 SWAP 23 0xffffffff 0x180002c Int LE Pri
!#3 N6574 P2361 LD 28 -1 Int BE Pri
!#3 N6575 P2362 LD 15 -1 Int BE Pri
!#3 N6576 P2363 BLD 20 -1 FP BE Pri
!#3 N6577 P2363 BLD 21 -1 FP BE Pri
!#A N6576 N6577
!#3 N6578 P2363 BLD 22 -1 FP BE Pri
!#3 N6579 P2363 BLD 23 -1 FP BE Pri
!#3 N6580 P2364 LD 13 -1 Int BE Pri
!#3 N6581 P2362 LD 15 -1 Int BE Pri
!#3 N6582 P2363 BLD 20 -1 FP BE Pri
!#3 N6583 P2363 BLD 21 -1 FP BE Pri
!#A N6582 N6583
!#3 N6584 P2363 BLD 22 -1 FP BE Pri
!#3 N6585 P2363 BLD 23 -1 FP BE Pri
!#3 N6586 P2364 LD 13 -1 Int BE Pri
!#3 N6587 P2365 BSTC 20 0x41000019 FP BE Pri
!#3 N6588 P2365 BSTC 21 0x4100001a FP BE Pri
!#A N6587 N6588
!#3 N6589 P2365 BSTC 22 0x4100001b FP BE Pri
!#3 N6590 P2365 BSTC 23 0x4100001c FP BE Pri
!#3 N6591 P2366 DWLD 15 -1 Int BE Pri
!#3 N6592 P2367 LD 27 -1 Int BE Pri
!#3 N6593 P2368 BLD 8 -1 FP BE Pri
!#3 N6594 P2368 BLD 9 -1 FP BE Pri
!#A N6593 N6594
!#3 N6595 P2368 BLD 10 -1 FP BE Pri
!#3 N6596 P2368 BLD 11 -1 FP BE Pri
!#3 N6597 P2369 DWLD 3 -1 Int BE Pri
!#3 N6598 P2370 LD 22 -1 Int BE Pri
!#3 N6599 P2368 BLD 8 -1 FP BE Pri
!#3 N6600 P2368 BLD 9 -1 FP BE Pri
!#A N6599 N6600
!#3 N6601 P2368 BLD 10 -1 FP BE Pri
!#3 N6602 P2368 BLD 11 -1 FP BE Pri
!#3 N6603 P2369 DWLD 3 -1 Int BE Pri
!#3 N6604 P2370 LD 22 -1 Int BE Pri
!#3 N6605 P2371 DWLD 31 -1 Int BE Pri
!#3 N6606 P2372 LD 26 -1 Int BE Pri
!#3 N6607 P2371 DWLD 31 -1 Int BE Pri
!#3 N6608 P2372 LD 26 -1 Int BE Pri
!#3 N6609 P2373 BLD 24 -1 FP BE Pri
!#3 N6610 P2373 BLD 25 -1 FP BE Pri
!#A N6609 N6610
!#3 N6611 P2373 BLD 26 -1 FP BE Pri
!#3 N6612 P2373 BLD 27 -1 FP BE Pri
!#3 N6613 P2374 BLD 4 -1 FP BE Pri
!#3 N6614 P2374 BLD 5 -1 FP BE Pri
!#A N6613 N6614
!#3 N6615 P2374 BLD 6 -1 FP BE Pri
!#3 N6616 P2374 BLD 7 -1 FP BE Pri
!#3 N6617 P2375 LD 4 -1 Int BE Pri
!#3 N6618 P2376 LD 6 -1 Int BE Pri
!#3 N6619 P2377 LD 31 -1 FP BE Pri
!#3 N6620 P2378 LD 3 -1 Int BE Pri
!#3 N6621 P2379 LD 3 -1 Int BE Pri
!#3 N6622 P2380 DWLD 6 -1 Int BE Pri
!#3 N6623 P2381 LD 12 -1 Int BE Pri
!#3 N6624 P2382 DWLD 0 -1 FP BE Pri
!#3 N6625 P2382 DWLD 1 -1 FP BE Pri
!#A N6624 N6625
!#3 N6626 P2383 BLD 16 -1 FP BE Pri
!#3 N6627 P2383 BLD 17 -1 FP BE Pri
!#A N6626 N6627
!#3 N6628 P2383 BLD 18 -1 FP BE Pri
!#3 N6629 P2383 BLD 19 -1 FP BE Pri
!#3 N6630 P2384 LD 5 -1 FP BE Pri
!#3 N6631 P2385 BLD 0 -1 FP BE Pri
!#3 N6632 P2385 BLD 1 -1 FP BE Pri
!#A N6631 N6632
!#3 N6633 P2385 BLD 2 -1 FP BE Pri
!#3 N6634 P2385 BLD 3 -1 FP BE Pri
!#3 N6635 P2385 BLD 0 -1 FP BE Pri
!#3 N6636 P2385 BLD 1 -1 FP BE Pri
!#A N6635 N6636
!#3 N6637 P2385 BLD 2 -1 FP BE Pri
!#3 N6638 P2385 BLD 3 -1 FP BE Pri
!#3 N6639 P2386 DWLD 11 -1 Int BE Pri
!#3 N6640 P2387 DWLD 24 -1 Int BE Pri
!#3 N6641 P2387 DWLD 25 -1 Int BE Pri
!#A N6640 N6641
!#3 N6642 P2388 LD 5 -1 Int BE Pri
!#3 N6643 P2389 LD 25 -1 Int BE Pri
!#3 N6644 P2390 DWLD 24 -1 Int BE Pri
!#3 N6645 P2390 DWLD 25 -1 Int BE Pri
!#A N6644 N6645
!#3 N6646 P2391 LD 14 -1 Int BE Pri
!#3 N6647 P2392 DWLD 15 -1 Int BE Pri
!#3 N6648 P2393 LD 4 -1 Int BE Pri
!#3 N6649 P2392 DWLD 15 -1 Int BE Pri
!#3 N6650 P2393 LD 4 -1 Int BE Pri
!#3 N6651 P2394 BLD 20 -1 FP BE Pri
!#3 N6652 P2394 BLD 21 -1 FP BE Pri
!#A N6651 N6652
!#3 N6653 P2394 BLD 22 -1 FP BE Pri
!#3 N6654 P2394 BLD 23 -1 FP BE Pri
!#3 N6655 P2394 BLD 20 -1 FP BE Pri
!#3 N6656 P2394 BLD 21 -1 FP BE Pri
!#A N6655 N6656
!#3 N6657 P2394 BLD 22 -1 FP BE Pri
!#3 N6658 P2394 BLD 23 -1 FP BE Pri
!#3 N6659 P2395 BLD 24 -1 FP BE Pri
!#3 N6660 P2395 BLD 25 -1 FP BE Pri
!#A N6659 N6660
!#3 N6661 P2395 BLD 26 -1 FP BE Pri
!#3 N6662 P2395 BLD 27 -1 FP BE Pri
!#3 N6663 P2396 BLD 12 -1 FP BE Pri
!#3 N6664 P2396 BLD 13 -1 FP BE Pri
!#A N6663 N6664
!#3 N6665 P2396 BLD 14 -1 FP BE Pri
!#3 N6666 P2396 BLD 15 -1 FP BE Pri
!#3 N6667 P2395 BLD 24 -1 FP BE Pri
!#3 N6668 P2395 BLD 25 -1 FP BE Pri
!#A N6667 N6668
!#3 N6669 P2395 BLD 26 -1 FP BE Pri
!#3 N6670 P2395 BLD 27 -1 FP BE Pri
!#3 N6671 P2396 BLD 12 -1 FP BE Pri
!#3 N6672 P2396 BLD 13 -1 FP BE Pri
!#A N6671 N6672
!#3 N6673 P2396 BLD 14 -1 FP BE Pri
!#3 N6674 P2396 BLD 15 -1 FP BE Pri
!#3 N6675 P2397 DWLD 28 -1 Int BE Pri
!#3 N6676 P2397 DWLD 29 -1 Int BE Pri
!#A N6675 N6676
!#3 N6677 P2398 BLD 12 -1 FP BE Pri
!#3 N6678 P2398 BLD 13 -1 FP BE Pri
!#A N6677 N6678
!#3 N6679 P2398 BLD 14 -1 FP BE Pri
!#3 N6680 P2398 BLD 15 -1 FP BE Pri
!#3 N6681 P2397 DWLD 28 -1 Int BE Pri
!#3 N6682 P2397 DWLD 29 -1 Int BE Pri
!#A N6681 N6682
!#3 N6683 P2398 BLD 12 -1 FP BE Pri
!#3 N6684 P2398 BLD 13 -1 FP BE Pri
!#A N6683 N6684
!#3 N6685 P2398 BLD 14 -1 FP BE Pri
!#3 N6686 P2398 BLD 15 -1 FP BE Pri
!#3 N6689 P2400 DWLD 31 -1 Int BE Pri
!#3 N6690 P2401 BLD 28 -1 FP BE Pri
!#3 N6691 P2401 BLD 29 -1 FP BE Pri
!#A N6690 N6691
!#3 N6692 P2401 BLD 30 -1 FP BE Pri
!#3 N6693 P2401 BLD 31 -1 FP BE Pri
!#3 N6694 P2402 LD 2 -1 Int BE Pri
!#3 N6695 P2403 LD 10 -1 Int BE Pri
!#3 N6696 P2404 DWLD 3 -1 Int BE Pri
!#3 N6697 P2403 LD 10 -1 Int BE Pri
!#3 N6698 P2404 DWLD 3 -1 Int BE Pri
!#3 N6699 P2405 LD 10 -1 Int BE Pri
!#3 N6700 P2406 LD 9 -1 Int BE Pri
!#3 N6701 P2405 LD 10 -1 Int BE Pri
!#3 N6702 P2406 LD 9 -1 Int BE Pri
!#3 N6703 P2407 DWLD 20 -1 Int BE Pri
!#3 N6704 P2407 DWLD 21 -1 Int BE Pri
!#A N6703 N6704
!#3 N6705 P2408 DWLD 30 -1 Int BE Pri
!#3 N6706 P2409 LD 0 -1 Int BE Pri
!#3 N6707 P2410 DWLD 23 -1 Int BE Pri
!#3 N6708 P2411 LD 24 -1 Int BE Pri
!#3 N6709 P2412 BLD 12 -1 FP BE Pri
!#3 N6710 P2412 BLD 13 -1 FP BE Pri
!#A N6709 N6710
!#3 N6711 P2412 BLD 14 -1 FP BE Pri
!#3 N6712 P2412 BLD 15 -1 FP BE Pri
!#3 N6713 P2413 DWLD 8 -1 Int BE Pri
!#3 N6714 P2413 DWLD 9 -1 Int BE Pri
!#A N6713 N6714
!#3 N6715 P2412 BLD 12 -1 FP BE Pri
!#3 N6716 P2412 BLD 13 -1 FP BE Pri
!#A N6715 N6716
!#3 N6717 P2412 BLD 14 -1 FP BE Pri
!#3 N6718 P2412 BLD 15 -1 FP BE Pri
!#3 N6719 P2413 DWLD 8 -1 Int BE Pri
!#3 N6720 P2413 DWLD 9 -1 Int BE Pri
!#A N6719 N6720
!#3 N6721 P2414 LD 4 -1 Int BE Pri
!#3 N6722 P2415 DWLD 30 -1 Int BE Pri
!#3 N6723 P2416 DWLD 18 -1 Int BE Pri
!#3 N6724 P2417 BLD 16 -1 FP BE Pri
!#3 N6725 P2417 BLD 17 -1 FP BE Pri
!#A N6724 N6725
!#3 N6726 P2417 BLD 18 -1 FP BE Pri
!#3 N6727 P2417 BLD 19 -1 FP BE Pri
!#3 N6728 P2418 LD 26 -1 Int LE Pri
!#3 N6729 P2416 DWLD 18 -1 Int BE Pri
!#3 N6730 P2417 BLD 16 -1 FP BE Pri
!#3 N6731 P2417 BLD 17 -1 FP BE Pri
!#A N6730 N6731
!#3 N6732 P2417 BLD 18 -1 FP BE Pri
!#3 N6733 P2417 BLD 19 -1 FP BE Pri
!#3 N6734 P2418 LD 26 -1 Int LE Pri
!#3 N6735 P2419 LD 17 -1 Int BE Pri
!#3 N6736 P2420 LD 9 -1 Int BE Pri
!#3 N6737 P2419 LD 17 -1 Int BE Pri
!#3 N6738 P2420 LD 9 -1 Int BE Pri
!#3 N6739 P2421 DWLD 0 -1 Int BE Pri
!#3 N6740 P2421 DWLD 1 -1 Int BE Pri
!#A N6739 N6740
!#3 N6741 P2421 DWLD 0 -1 Int BE Pri
!#3 N6742 P2421 DWLD 1 -1 Int BE Pri
!#A N6741 N6742
!#3 N6743 P2422 DWLD 12 -1 FP BE Pri
!#3 N6744 P2422 DWLD 13 -1 FP BE Pri
!#A N6743 N6744
!#3 N6745 P2422 DWLD 12 -1 FP BE Pri
!#3 N6746 P2422 DWLD 13 -1 FP BE Pri
!#A N6745 N6746
!#3 N6747 P2423 BLD 20 -1 FP BE Pri
!#3 N6748 P2423 BLD 21 -1 FP BE Pri
!#A N6747 N6748
!#3 N6749 P2423 BLD 22 -1 FP BE Pri
!#3 N6750 P2423 BLD 23 -1 FP BE Pri
!#3 N6751 P2424 LD 8 -1 FP BE Pri
!#3 N6752 P2425 SWAP 1 0xffffffff 0x180002d Int BE Pri
!#3 N6753 P2426 LD 15 -1 Int BE Pri
!#3 N6754 P2425 SWAP 1 0xffffffff 0x180002e Int BE Pri
!#3 N6755 P2426 LD 15 -1 Int BE Pri
!#3 N6756 P2427 LD 8 -1 FP BE Pri
!#3 N6757 P2427 LD 8 -1 FP BE Pri
!#3 N6758 P2428 LD 13 -1 Int BE Pri
!#3 N6759 P2429 LD 17 -1 Int BE Pri
!#3 N6760 P2428 LD 13 -1 Int BE Pri
!#3 N6761 P2429 LD 17 -1 Int BE Pri
!#3 N6762 P2430 BLD 16 -1 FP BE Pri
!#3 N6763 P2430 BLD 17 -1 FP BE Pri
!#A N6762 N6763
!#3 N6764 P2430 BLD 18 -1 FP BE Pri
!#3 N6765 P2430 BLD 19 -1 FP BE Pri
!#3 N6766 P2431 DWLD 4 -1 Int BE Pri
!#3 N6767 P2431 DWLD 5 -1 Int BE Pri
!#A N6766 N6767
!#3 N6768 P2432 BLD 16 -1 FP BE Pri
!#3 N6769 P2432 BLD 17 -1 FP BE Pri
!#A N6768 N6769
!#3 N6770 P2432 BLD 18 -1 FP BE Pri
!#3 N6771 P2432 BLD 19 -1 FP BE Pri
!#3 N6772 P2433 DWLD 26 -1 Int BE Pri
!#3 N6773 P2434 LD 27 -1 Int BE Pri
!#3 N6774 P2435 LD 4 -1 Int BE Pri
!#3 N6775 P2436 DWLD 0 -1 Int BE Pri
!#3 N6776 P2436 DWLD 1 -1 Int BE Pri
!#A N6775 N6776
!#3 N6777 P2437 LD 14 -1 Int BE Pri
!#3 N6778 P2438 BLD 16 -1 FP BE Pri
!#3 N6779 P2438 BLD 17 -1 FP BE Pri
!#A N6778 N6779
!#3 N6780 P2438 BLD 18 -1 FP BE Pri
!#3 N6781 P2438 BLD 19 -1 FP BE Pri
!#3 N6782 P2438 BLD 16 -1 FP BE Pri
!#3 N6783 P2438 BLD 17 -1 FP BE Pri
!#A N6782 N6783
!#3 N6784 P2438 BLD 18 -1 FP BE Pri
!#3 N6785 P2438 BLD 19 -1 FP BE Pri
!#3 N6786 P2439 DWLD 30 -1 Int BE Pri
!#3 N6787 P2440 MEMBAR
!#3 N6788 P2441 LD 24 -1 Int BE Pri
!#3 N6789 P2442 BLD 0 -1 FP BE Pri
!#3 N6790 P2442 BLD 1 -1 FP BE Pri
!#A N6789 N6790
!#3 N6791 P2442 BLD 2 -1 FP BE Pri
!#3 N6792 P2442 BLD 3 -1 FP BE Pri
!#3 N6793 P2443 DWLD 10 -1 Int BE Pri
!#3 N6794 P2444 LD 1 -1 Int BE Pri
!#3 N6795 P2445 LD 26 -1 Int BE Pri
!#3 N6796 P2446 LD 25 -1 Int BE Pri
!#3 N6797 P2445 LD 26 -1 Int BE Pri
!#3 N6798 P2446 LD 25 -1 Int BE Pri
!#3 N6799 P2447 LD 14 -1 Int LE Pri
!#3 N6800 P2448 LD 27 -1 Int BE Pri
!#3 N6801 P2447 LD 14 -1 Int LE Pri
!#3 N6802 P2448 LD 27 -1 Int BE Pri
!#3 N6803 P2449 BLD 16 -1 FP BE Pri
!#3 N6804 P2449 BLD 17 -1 FP BE Pri
!#A N6803 N6804
!#3 N6805 P2449 BLD 18 -1 FP BE Pri
!#3 N6806 P2449 BLD 19 -1 FP BE Pri
!#3 N6807 P2450 DWLD 7 -1 Int BE Pri
!#3 N6808 P2451 LD 31 -1 Int BE Pri
!#3 N6809 P2452 BSTC 4 0x4100001d FP BE Pri
!#3 N6810 P2452 BSTC 5 0x4100001e FP BE Pri
!#A N6809 N6810
!#3 N6811 P2452 BSTC 6 0x4100001f FP BE Pri
!#3 N6812 P2452 BSTC 7 0x41000020 FP BE Pri
!#3 N6813 P2453 LD 30 -1 Int BE Pri
!#3 N6815 P2455 LD 5 -1 Int BE Pri
!#3 N6816 P2453 LD 30 -1 Int BE Pri
!#3 N6818 P2455 LD 5 -1 Int BE Pri
!#3 N6819 P2456 LD 8 -1 FP BE Pri
!#3 N6820 P2457 MEMBAR
!#3 N6821 P2458 BST 0 0x41000021 FP BE Pri
!#3 N6822 P2458 BST 1 0x41000022 FP BE Pri
!#A N6821 N6822
!#3 N6823 P2458 BST 2 0x41000023 FP BE Pri
!#3 N6824 P2458 BST 3 0x41000024 FP BE Pri
!#3 N6825 P2458 BST 0 0x41000025 FP BE Pri
!#3 N6826 P2458 BST 1 0x41000026 FP BE Pri
!#A N6825 N6826
!#3 N6827 P2458 BST 2 0x41000027 FP BE Pri
!#3 N6828 P2458 BST 3 0x41000028 FP BE Pri
!#3 N6829 P2459 DWLD 2 -1 Int BE Pri
!#3 N6830 P2460 LD 15 -1 Int BE Pri
!#3 N6831 P2460 CAS 15 -1 N6830 0x180002f Int BE Pri
!#3 N6832 P2461 LD 31 -1 Int BE Pri
!#3 N6833 P2459 DWLD 2 -1 Int BE Pri
!#3 N6834 P2460 LD 15 -1 Int BE Pri
!#3 N6835 P2460 CAS 15 -1 N6834 0x1800030 Int BE Pri
!#3 N6836 P2461 LD 31 -1 Int BE Pri
!#3 N6837 P2462 DWLD 0 -1 Int BE Pri
!#3 N6838 P2462 DWLD 1 -1 Int BE Pri
!#A N6837 N6838
!#3 N6839 P2463 BLD 4 -1 FP BE Pri
!#3 N6840 P2463 BLD 5 -1 FP BE Pri
!#A N6839 N6840
!#3 N6841 P2463 BLD 6 -1 FP BE Pri
!#3 N6842 P2463 BLD 7 -1 FP BE Pri
!#3 N6843 P2462 DWLD 0 -1 Int BE Pri
!#3 N6844 P2462 DWLD 1 -1 Int BE Pri
!#A N6843 N6844
!#3 N6845 P2463 BLD 4 -1 FP BE Pri
!#3 N6846 P2463 BLD 5 -1 FP BE Pri
!#A N6845 N6846
!#3 N6847 P2463 BLD 6 -1 FP BE Pri
!#3 N6848 P2463 BLD 7 -1 FP BE Pri
!#3 N6849 P2464 DWLD 31 -1 Int BE Pri
!#3 N6850 P2465 LD 29 -1 Int LE Pri
!#3 N6851 P2465 CAS 29 -1 N6850 0x1800031 Int LE Pri
!#3 N6852 P2466 LD 1 -1 Int BE Pri
!#3 N6853 P2464 DWLD 31 -1 Int BE Pri
!#3 N6854 P2465 LD 29 -1 Int LE Pri
!#3 N6855 P2465 CAS 29 -1 N6854 0x1800032 Int LE Pri
!#3 N6856 P2466 LD 1 -1 Int BE Pri
!#3 N6857 P2467 BLD 20 -1 FP BE Pri
!#3 N6858 P2467 BLD 21 -1 FP BE Pri
!#A N6857 N6858
!#3 N6859 P2467 BLD 22 -1 FP BE Pri
!#3 N6860 P2467 BLD 23 -1 FP BE Pri
!#3 N6861 P2468 LD 13 -1 Int BE Pri
!#3 N6862 P2469 LD 17 -1 Int BE Pri
!#3 N6863 P2468 LD 13 -1 Int BE Pri
!#3 N6864 P2469 LD 17 -1 Int BE Pri
!#3 N6865 P2470 DWLD 11 -1 Int BE Pri
!#3 N6866 P2471 LD 0 -1 Int BE Pri
!#3 N6867 P2472 DWLD 0 -1 Int BE Pri
!#3 N6868 P2472 DWLD 1 -1 Int BE Pri
!#A N6867 N6868
!#3 N6869 P2473 LD 28 -1 Int BE Pri
!#3 N6870 P2474 LD 5 -1 Int BE Pri
!#3 N6871 P2475 LD 15 -1 Int BE Pri
!#3 N6872 P2476 LD 14 -1 Int BE Pri
!#3 N6873 P2475 LD 15 -1 Int BE Pri
!#3 N6874 P2476 LD 14 -1 Int BE Pri
!#3 N6875 P2477 SWAP 0 0xffffffff 0x1800033 Int BE Pri
!#3 N6876 P2478 BLD 4 -1 FP BE Pri
!#3 N6877 P2478 BLD 5 -1 FP BE Pri
!#A N6876 N6877
!#3 N6878 P2478 BLD 6 -1 FP BE Pri
!#3 N6879 P2478 BLD 7 -1 FP BE Pri
!#3 N6880 P2479 LD 15 -1 Int BE Pri
!#3 N6881 P2480 BSTC 20 0x41000029 FP BE Pri
!#3 N6882 P2480 BSTC 21 0x4100002a FP BE Pri
!#A N6881 N6882
!#3 N6883 P2480 BSTC 22 0x4100002b FP BE Pri
!#3 N6884 P2480 BSTC 23 0x4100002c FP BE Pri
!#3 N6885 P2481 BLD 24 -1 FP BE Pri
!#3 N6886 P2481 BLD 25 -1 FP BE Pri
!#A N6885 N6886
!#3 N6887 P2481 BLD 26 -1 FP BE Pri
!#3 N6888 P2481 BLD 27 -1 FP BE Pri
!#3 N6889 P2481 BLD 24 -1 FP BE Pri
!#3 N6890 P2481 BLD 25 -1 FP BE Pri
!#A N6889 N6890
!#3 N6891 P2481 BLD 26 -1 FP BE Pri
!#3 N6892 P2481 BLD 27 -1 FP BE Pri
!#3 N6893 P2482 LD 25 -1 Int BE Pri
!#3 N6894 P2483 LD 31 -1 Int BE Pri
!#3 N6895 P2484 BLD 24 -1 FP BE Pri
!#3 N6896 P2484 BLD 25 -1 FP BE Pri
!#A N6895 N6896
!#3 N6897 P2484 BLD 26 -1 FP BE Pri
!#3 N6898 P2484 BLD 27 -1 FP BE Pri
!#3 N6899 P2485 DWLD 10 -1 Int BE Pri
!#3 N6900 P2486 LD 23 -1 Int BE Pri
!#3 N6901 P2487 LD 26 -1 Int BE Pri
!#3 N6902 P2488 LD 30 -1 Int BE Pri
!#3 N6903 P2489 SWAP 17 0xffffffff 0x1800034 Int BE Pri
!#3 N6904 P2490 DWLD 11 -1 Int BE Pri
!#3 N6905 P2489 SWAP 17 0xffffffff 0x1800035 Int BE Pri
!#3 N6906 P2490 DWLD 11 -1 Int BE Pri
!#3 N6907 P2491 DWLD 20 -1 Int BE Pri
!#3 N6908 P2491 DWLD 21 -1 Int BE Pri
!#A N6907 N6908
!#3 N6909 P2492 LD 7 -1 Int BE Pri
!#3 N6910 P2493 LD 24 -1 Int BE Pri
!#3 N6911 P2492 LD 7 -1 Int BE Pri
!#3 N6912 P2493 LD 24 -1 Int BE Pri
!#3 N6914 P2495 LD 30 -1 Int BE Pri
!#3 N6915 P2496 LD 18 -1 Int BE Pri
!#3 N6916 P2497 LD 28 -1 Int BE Pri
!#3 N6917 P2498 DWLD 0 -1 FP BE Pri
!#3 N6918 P2498 DWLD 1 -1 FP BE Pri
!#A N6917 N6918
!#3 N6919 P2499 LD 4 -1 Int BE Pri
!#3 N6920 P2497 LD 28 -1 Int BE Pri
!#3 N6921 P2498 DWLD 0 -1 FP BE Pri
!#3 N6922 P2498 DWLD 1 -1 FP BE Pri
!#A N6921 N6922
!#3 N6923 P2499 LD 4 -1 Int BE Pri
!#3 N6924 P2500 BLD 8 -1 FP BE Pri
!#3 N6925 P2500 BLD 9 -1 FP BE Pri
!#A N6924 N6925
!#3 N6926 P2500 BLD 10 -1 FP BE Pri
!#3 N6927 P2500 BLD 11 -1 FP BE Pri
!#3 N6928 P2501 BLD 28 -1 FP BE Pri
!#3 N6929 P2501 BLD 29 -1 FP BE Pri
!#A N6928 N6929
!#3 N6930 P2501 BLD 30 -1 FP BE Pri
!#3 N6931 P2501 BLD 31 -1 FP BE Pri
!#3 N6932 P2500 BLD 8 -1 FP BE Pri
!#3 N6933 P2500 BLD 9 -1 FP BE Pri
!#A N6932 N6933
!#3 N6934 P2500 BLD 10 -1 FP BE Pri
!#3 N6935 P2500 BLD 11 -1 FP BE Pri
!#3 N6936 P2501 BLD 28 -1 FP BE Pri
!#3 N6937 P2501 BLD 29 -1 FP BE Pri
!#A N6936 N6937
!#3 N6938 P2501 BLD 30 -1 FP BE Pri
!#3 N6939 P2501 BLD 31 -1 FP BE Pri
!#3 N6940 P2502 LD 4 -1 Int BE Pri
!#3 N6941 P2503 LD 24 -1 Int BE Pri
!#3 N6942 P2504 LD 15 -1 Int BE Pri
!#3 N6943 P2505 BLD 20 -1 FP BE Pri
!#3 N6944 P2505 BLD 21 -1 FP BE Pri
!#A N6943 N6944
!#3 N6945 P2505 BLD 22 -1 FP BE Pri
!#3 N6946 P2505 BLD 23 -1 FP BE Pri
!#3 N6947 P2506 LD 1 -1 Int BE Pri
!#3 N6948 P2504 LD 15 -1 Int BE Pri
!#3 N6949 P2505 BLD 20 -1 FP BE Pri
!#3 N6950 P2505 BLD 21 -1 FP BE Pri
!#A N6949 N6950
!#3 N6951 P2505 BLD 22 -1 FP BE Pri
!#3 N6952 P2505 BLD 23 -1 FP BE Pri
!#3 N6953 P2506 LD 1 -1 Int BE Pri
!#3 N6954 P2507 LD 30 -1 Int BE Pri
!#3 N6955 P2508 LD 8 -1 Int BE Pri
!#3 N6956 P2507 LD 30 -1 Int BE Pri
!#3 N6957 P2508 LD 8 -1 Int BE Pri
!#3 N6958 P2509 MEMBAR
!#3 N6959 P2510 BLD 20 -1 FP BE Pri
!#3 N6960 P2510 BLD 21 -1 FP BE Pri
!#A N6959 N6960
!#3 N6961 P2510 BLD 22 -1 FP BE Pri
!#3 N6962 P2510 BLD 23 -1 FP BE Pri
!#3 N6963 P2509 MEMBAR
!#3 N6964 P2510 BLD 20 -1 FP BE Pri
!#3 N6965 P2510 BLD 21 -1 FP BE Pri
!#A N6964 N6965
!#3 N6966 P2510 BLD 22 -1 FP BE Pri
!#3 N6967 P2510 BLD 23 -1 FP BE Pri
!#3 N6968 P2511 BST 28 0x4100002d FP BE Pri
!#3 N6969 P2511 BST 29 0x4100002e FP BE Pri
!#A N6968 N6969
!#3 N6970 P2511 BST 30 0x4100002f FP BE Pri
!#3 N6971 P2511 BST 31 0x41000030 FP BE Pri
!#3 N6972 P2512 DWLD 22 -1 Int BE Pri
!#3 N6973 P2513 LD 4 -1 Int BE Pri
!#3 N6974 P2514 SWAP 12 0xffffffff 0x1800036 Int BE Pri
!#3 N6975 P2515 BLD 16 -1 FP BE Pri
!#3 N6976 P2515 BLD 17 -1 FP BE Pri
!#A N6975 N6976
!#3 N6977 P2515 BLD 18 -1 FP BE Pri
!#3 N6978 P2515 BLD 19 -1 FP BE Pri
!#3 N6979 P2516 LD 20 -1 Int BE Pri
!#3 N6980 P2517 BLD 24 -1 FP BE Pri
!#3 N6981 P2517 BLD 25 -1 FP BE Pri
!#A N6980 N6981
!#3 N6982 P2517 BLD 26 -1 FP BE Pri
!#3 N6983 P2517 BLD 27 -1 FP BE Pri
!#3 N6984 P2518 LD 1 -1 Int BE Pri
!#3 N6985 P2519 BLD 8 -1 FP BE Pri
!#3 N6986 P2519 BLD 9 -1 FP BE Pri
!#A N6985 N6986
!#3 N6987 P2519 BLD 10 -1 FP BE Pri
!#3 N6988 P2519 BLD 11 -1 FP BE Pri
!#3 N6989 P2520 LD 21 -1 Int BE Pri
!#3 N6990 P2521 DWLD 28 -1 Int BE Pri
!#3 N6991 P2521 DWLD 29 -1 Int BE Pri
!#A N6990 N6991
!#3 N6992 P2522 LD 5 -1 Int BE Pri
!#3 N6993 P2523 LD 8 -1 Int BE Pri
!#3 N6994 P2521 DWLD 28 -1 Int BE Pri
!#3 N6995 P2521 DWLD 29 -1 Int BE Pri
!#A N6994 N6995
!#3 N6996 P2522 LD 5 -1 Int BE Pri
!#3 N6997 P2523 LD 8 -1 Int BE Pri
!#3 N6998 P2524 BLD 4 -1 FP BE Pri
!#3 N6999 P2524 BLD 5 -1 FP BE Pri
!#A N6998 N6999
!#3 N7000 P2524 BLD 6 -1 FP BE Pri
!#3 N7001 P2524 BLD 7 -1 FP BE Pri
!#3 N7002 P2525 LD 31 -1 Int BE Pri
!#3 N7003 P2526 LD 10 -1 Int BE Pri
!#3 N7004 P2524 BLD 4 -1 FP BE Pri
!#3 N7005 P2524 BLD 5 -1 FP BE Pri
!#A N7004 N7005
!#3 N7006 P2524 BLD 6 -1 FP BE Pri
!#3 N7007 P2524 BLD 7 -1 FP BE Pri
!#3 N7008 P2525 LD 31 -1 Int BE Pri
!#3 N7009 P2526 LD 10 -1 Int BE Pri
!#3 N7010 P2527 BST 12 0x41000031 FP BE Pri
!#3 N7011 P2527 BST 13 0x41000032 FP BE Pri
!#A N7010 N7011
!#3 N7012 P2527 BST 14 0x41000033 FP BE Pri
!#3 N7013 P2527 BST 15 0x41000034 FP BE Pri
!#3 N7014 P2528 MEMBAR
!#3 N7015 P2527 BST 12 0x41000035 FP BE Pri
!#3 N7016 P2527 BST 13 0x41000036 FP BE Pri
!#A N7015 N7016
!#3 N7017 P2527 BST 14 0x41000037 FP BE Pri
!#3 N7018 P2527 BST 15 0x41000038 FP BE Pri
!#3 N7019 P2528 MEMBAR
!#3 N7020 P2529 ST 4 0x41000039 FP BE Pri
!#3 N7021 P2529 ST 4 0x4100003a FP BE Pri
!#3 N7023 P2531 DWLD 0 -1 Int BE Pri
!#3 N7024 P2531 DWLD 1 -1 Int BE Pri
!#A N7023 N7024
!#3 N7026 P2531 DWLD 0 -1 Int BE Pri
!#3 N7027 P2531 DWLD 1 -1 Int BE Pri
!#A N7026 N7027
!#3 N7029 P2533 ST 3 0x1800037 Int BE Pri
!#3 N7030 P2534 DWLD 24 -1 Int BE Pri
!#3 N7031 P2534 DWLD 25 -1 Int BE Pri
!#A N7030 N7031
!#3 N7032 P2535 BLD 24 -1 FP BE Pri
!#3 N7033 P2535 BLD 25 -1 FP BE Pri
!#A N7032 N7033
!#3 N7034 P2535 BLD 26 -1 FP BE Pri
!#3 N7035 P2535 BLD 27 -1 FP BE Pri
!#3 N7036 P2534 DWLD 24 -1 Int BE Pri
!#3 N7037 P2534 DWLD 25 -1 Int BE Pri
!#A N7036 N7037
!#3 N7038 P2535 BLD 24 -1 FP BE Pri
!#3 N7039 P2535 BLD 25 -1 FP BE Pri
!#A N7038 N7039
!#3 N7040 P2535 BLD 26 -1 FP BE Pri
!#3 N7041 P2535 BLD 27 -1 FP BE Pri
!#3 N7042 P2536 LD 0 -1 Int BE Pri
!#3 N7043 P2537 LD 31 -1 Int BE Pri
!#3 N7044 P2538 LD 22 -1 Int BE Pri
!#3 N7045 P2539 DWLD 26 -1 Int BE Pri
!#3 N7046 P2538 LD 22 -1 Int BE Pri
!#3 N7047 P2539 DWLD 26 -1 Int BE Pri
!#3 N7049 P2541 LD 31 -1 Int BE Pri
!#3 N7050 P2542 LD 12 -1 Int BE Pri
!#3 N7052 P2541 LD 31 -1 Int BE Pri
!#3 N7053 P2542 LD 12 -1 Int BE Pri
!#3 N7054 P2543 ST 9 0x1800038 Int BE Pri
!#3 N7055 P2544 BLD 4 -1 FP BE Pri
!#3 N7056 P2544 BLD 5 -1 FP BE Pri
!#A N7055 N7056
!#3 N7057 P2544 BLD 6 -1 FP BE Pri
!#3 N7058 P2544 BLD 7 -1 FP BE Pri
!#3 N7059 P2544 BLD 4 -1 FP BE Pri
!#3 N7060 P2544 BLD 5 -1 FP BE Pri
!#A N7059 N7060
!#3 N7061 P2544 BLD 6 -1 FP BE Pri
!#3 N7062 P2544 BLD 7 -1 FP BE Pri
!#3 N7063 P2545 LD 21 -1 Int BE Pri
!#3 N7064 P2545 CAS 21 -1 N7063 0x1800039 Int BE Pri
!#3 N7065 P2545 LD 21 -1 Int BE Pri
!#3 N7066 P2545 CAS 21 -1 N7065 0x180003a Int BE Pri
!#3 N7067 P2546 DWLD 26 -1,0x0 Int LE Pri
!#3 N7068 P2546 CASX 26 -1,0x0 N7067 0x180003b Int LE Pri
!#3 N7069 P2546 DWLD 26 -1,0x0 Int LE Pri
!#3 N7070 P2546 CASX 26 -1,0x0 N7069 0x180003c Int LE Pri
!#3 N7071 P2547 LD 14 -1 Int BE Pri
!#3 N7072 P2548 LD 26 -1 Int BE Pri
!#3 N7073 P2549 LD 31 -1 Int LE Pri
!#3 N7074 P2550 LD 8 -1 Int BE Pri
!#3 N7075 P2549 LD 31 -1 Int LE Pri
!#3 N7076 P2550 LD 8 -1 Int BE Pri
!#3 N7077 P2551 BLD 24 -1 FP BE Pri
!#3 N7078 P2551 BLD 25 -1 FP BE Pri
!#A N7077 N7078
!#3 N7079 P2551 BLD 26 -1 FP BE Pri
!#3 N7080 P2551 BLD 27 -1 FP BE Pri
!#3 N7081 P2552 BSTC 28 0x4100003b FP BE Pri
!#3 N7082 P2552 BSTC 29 0x4100003c FP BE Pri
!#A N7081 N7082
!#3 N7083 P2552 BSTC 30 0x4100003d FP BE Pri
!#3 N7084 P2552 BSTC 31 0x4100003e FP BE Pri
!#3 N7085 P2551 BLD 24 -1 FP BE Pri
!#3 N7086 P2551 BLD 25 -1 FP BE Pri
!#A N7085 N7086
!#3 N7087 P2551 BLD 26 -1 FP BE Pri
!#3 N7088 P2551 BLD 27 -1 FP BE Pri
!#3 N7089 P2552 BSTC 28 0x4100003f FP BE Pri
!#3 N7090 P2552 BSTC 29 0x41000040 FP BE Pri
!#A N7089 N7090
!#3 N7091 P2552 BSTC 30 0x41000041 FP BE Pri
!#3 N7092 P2552 BSTC 31 0x41000042 FP BE Pri
!#3 N7093 P2553 DWLD 24 -1 Int BE Pri
!#3 N7094 P2553 DWLD 25 -1 Int BE Pri
!#A N7093 N7094
!#3 N7095 P2553 DWLD 24 -1 Int BE Pri
!#3 N7096 P2553 DWLD 25 -1 Int BE Pri
!#A N7095 N7096
!#3 N7097 P2554 MEMBAR
!#3 N7098 P2555 BLD 16 -1 FP BE Pri
!#3 N7099 P2555 BLD 17 -1 FP BE Pri
!#A N7098 N7099
!#3 N7100 P2555 BLD 18 -1 FP BE Pri
!#3 N7101 P2555 BLD 19 -1 FP BE Pri
!#3 N7102 P2556 DWLD 31 -1 Int BE Pri
!#3 N7103 P2557 LD 19 -1 Int BE Pri
!#3 N7104 P2556 DWLD 31 -1 Int BE Pri
!#3 N7105 P2557 LD 19 -1 Int BE Pri
!#3 N7106 P2558 DWLD 8 -1 Int BE Pri
!#3 N7107 P2558 DWLD 9 -1 Int BE Pri
!#A N7106 N7107
!#3 N7108 P2559 BLD 12 -1 FP BE Pri
!#3 N7109 P2559 BLD 13 -1 FP BE Pri
!#A N7108 N7109
!#3 N7110 P2559 BLD 14 -1 FP BE Pri
!#3 N7111 P2559 BLD 15 -1 FP BE Pri
!#3 N7112 P2560 ST 24 0x180003d Int BE Pri
!#3 N7113 P2561 DWLD 0 -1 Int BE Pri
!#3 N7114 P2561 DWLD 1 -1 Int BE Pri
!#A N7113 N7114
!#3 N7115 P2561 DWLD 0 -1 Int BE Pri
!#3 N7116 P2561 DWLD 1 -1 Int BE Pri
!#A N7115 N7116
!#3 N7117 P2562 SWAP 18 0xffffffff 0x180003e Int BE Pri
!#3 N7118 P2563 DWLD 8 -1 Int BE Pri
!#3 N7119 P2563 DWLD 9 -1 Int BE Pri
!#A N7118 N7119
!#3 N7120 P2564 LD 3 -1 Int BE Pri
!#3 N7121 P2565 DWLD 4 -1 Int BE Pri
!#3 N7122 P2565 DWLD 5 -1 Int BE Pri
!#A N7121 N7122
!#3 N7124 P2567 DWLD 15 -1 Int BE Pri
!#3 N7125 P2568 LD 6 -1 Int BE Pri
!#3 N7126 P2569 LD 27 -1 Int BE Pri
!#3 N7127 P2570 LD 31 -1 Int BE Pri
!#3 N7128 P2569 LD 27 -1 Int BE Pri
!#3 N7129 P2570 LD 31 -1 Int BE Pri
!#3 N7130 P2571 LD 19 -1 Int BE Pri
!#3 N7131 P2572 LD 21 -1 Int BE Pri
!#3 N7132 P2573 LD 7 -1 Int BE Pri
!#3 N7133 P2574 BLD 12 -1 FP BE Pri
!#3 N7134 P2574 BLD 13 -1 FP BE Pri
!#A N7133 N7134
!#3 N7135 P2574 BLD 14 -1 FP BE Pri
!#3 N7136 P2574 BLD 15 -1 FP BE Pri
!#3 N7137 P2575 LD 11 -1 Int BE Pri
!#3 N7138 P2576 SWAP 18 0xffffffff 0x180003f Int BE Pri
!#3 N7139 P2577 LD 21 -1 FP BE Pri
!#3 N7140 P2578 LD 14 -1 Int BE Pri
!#3 N7141 P2579 BLD 8 -1 FP BE Pri
!#3 N7142 P2579 BLD 9 -1 FP BE Pri
!#A N7141 N7142
!#3 N7143 P2579 BLD 10 -1 FP BE Pri
!#3 N7144 P2579 BLD 11 -1 FP BE Pri
!#3 N7145 P2580 BLD 20 -1 FP BE Pri
!#3 N7146 P2580 BLD 21 -1 FP BE Pri
!#A N7145 N7146
!#3 N7147 P2580 BLD 22 -1 FP BE Pri
!#3 N7148 P2580 BLD 23 -1 FP BE Pri
!#3 N7149 P2581 BLD 28 -1 FP BE Pri
!#3 N7150 P2581 BLD 29 -1 FP BE Pri
!#A N7149 N7150
!#3 N7151 P2581 BLD 30 -1 FP BE Pri
!#3 N7152 P2581 BLD 31 -1 FP BE Pri
!#3 N7153 P2580 BLD 20 -1 FP BE Pri
!#3 N7154 P2580 BLD 21 -1 FP BE Pri
!#A N7153 N7154
!#3 N7155 P2580 BLD 22 -1 FP BE Pri
!#3 N7156 P2580 BLD 23 -1 FP BE Pri
!#3 N7157 P2581 BLD 28 -1 FP BE Pri
!#3 N7158 P2581 BLD 29 -1 FP BE Pri
!#A N7157 N7158
!#3 N7159 P2581 BLD 30 -1 FP BE Pri
!#3 N7160 P2581 BLD 31 -1 FP BE Pri
!#3 N7161 P2582 DWLD 28 -1 Int BE Pri
!#3 N7162 P2582 DWLD 29 -1 Int BE Pri
!#A N7161 N7162
!#3 N7163 P2583 BLD 12 -1 FP BE Pri
!#3 N7164 P2583 BLD 13 -1 FP BE Pri
!#A N7163 N7164
!#3 N7165 P2583 BLD 14 -1 FP BE Pri
!#3 N7166 P2583 BLD 15 -1 FP BE Pri
!#3 N7167 P2582 DWLD 28 -1 Int BE Pri
!#3 N7168 P2582 DWLD 29 -1 Int BE Pri
!#A N7167 N7168
!#3 N7169 P2583 BLD 12 -1 FP BE Pri
!#3 N7170 P2583 BLD 13 -1 FP BE Pri
!#A N7169 N7170
!#3 N7171 P2583 BLD 14 -1 FP BE Pri
!#3 N7172 P2583 BLD 15 -1 FP BE Pri
!#3 N7173 P2584 LD 11 -1 Int LE Pri
!#3 N7174 P2585 LD 13 -1 Int BE Pri
!#3 N7175 P2584 LD 11 -1 Int LE Pri
!#3 N7176 P2585 LD 13 -1 Int BE Pri
!#3 N7177 P2586 LD 30 -1 Int BE Pri
!#3 N7178 P2587 LD 2 -1 Int BE Pri
!#3 N7179 P2586 LD 30 -1 Int BE Pri
!#3 N7180 P2587 LD 2 -1 Int BE Pri
!#3 N7181 P2588 DWLD 22 -1 Int BE Pri
!#3 N7182 P2589 LD 1 -1 Int BE Pri
!#3 N7183 P2588 DWLD 22 -1 Int BE Pri
!#3 N7184 P2589 LD 1 -1 Int BE Pri
!#3 N7185 P2590 BSTC 0 0x41000043 FP BE Pri
!#3 N7186 P2590 BSTC 1 0x41000044 FP BE Pri
!#A N7185 N7186
!#3 N7187 P2590 BSTC 2 0x41000045 FP BE Pri
!#3 N7188 P2590 BSTC 3 0x41000046 FP BE Pri
!#3 N7189 P2591 DWLD 2 -1 Int LE Pri
!#3 N7190 P2592 LD 27 -1 Int BE Pri
!#3 N7191 P2593 LD 6 -1 Int BE Pri
!#3 N7192 P2594 BLD 0 -1 FP BE Pri
!#3 N7193 P2594 BLD 1 -1 FP BE Pri
!#A N7192 N7193
!#3 N7194 P2594 BLD 2 -1 FP BE Pri
!#3 N7195 P2594 BLD 3 -1 FP BE Pri
!#3 N7196 P2595 LD 4 -1 Int BE Pri
!#3 N7197 P2593 LD 6 -1 Int BE Pri
!#3 N7198 P2594 BLD 0 -1 FP BE Pri
!#3 N7199 P2594 BLD 1 -1 FP BE Pri
!#A N7198 N7199
!#3 N7200 P2594 BLD 2 -1 FP BE Pri
!#3 N7201 P2594 BLD 3 -1 FP BE Pri
!#3 N7202 P2595 LD 4 -1 Int BE Pri
!#3 N7203 P2596 DWLD 15 -1 FP BE Pri
!#3 N7204 P2597 DWLD 6 -1 Int BE Pri
!#3 N7205 P2598 LD 21 -1 Int BE Pri
!#3 N7206 P2599 DWLD 15 -1 Int BE Pri
!#3 N7207 P2600 LD 3 -1 Int BE Pri
!#3 N7208 P2599 DWLD 15 -1 Int BE Pri
!#3 N7209 P2600 LD 3 -1 Int BE Pri
!#3 N7211 P2602 BLD 28 -1 FP BE Pri
!#3 N7212 P2602 BLD 29 -1 FP BE Pri
!#A N7211 N7212
!#3 N7213 P2602 BLD 30 -1 FP BE Pri
!#3 N7214 P2602 BLD 31 -1 FP BE Pri
!#3 N7215 P2603 BLD 4 -1 FP BE Pri
!#3 N7216 P2603 BLD 5 -1 FP BE Pri
!#A N7215 N7216
!#3 N7217 P2603 BLD 6 -1 FP BE Pri
!#3 N7218 P2603 BLD 7 -1 FP BE Pri
!#3 N7219 P2602 BLD 28 -1 FP BE Pri
!#3 N7220 P2602 BLD 29 -1 FP BE Pri
!#A N7219 N7220
!#3 N7221 P2602 BLD 30 -1 FP BE Pri
!#3 N7222 P2602 BLD 31 -1 FP BE Pri
!#3 N7223 P2603 BLD 4 -1 FP BE Pri
!#3 N7224 P2603 BLD 5 -1 FP BE Pri
!#A N7223 N7224
!#3 N7225 P2603 BLD 6 -1 FP BE Pri
!#3 N7226 P2603 BLD 7 -1 FP BE Pri
!#3 N7227 P2604 LD 1 -1 Int BE Pri
!#3 N7228 P2605 LD 19 -1 Int BE Pri
!#3 N7229 P2604 LD 1 -1 Int BE Pri
!#3 N7230 P2605 LD 19 -1 Int BE Pri
!#3 N7231 P2606 BST 20 0x41000047 FP BE Pri
!#3 N7232 P2606 BST 21 0x41000048 FP BE Pri
!#A N7231 N7232
!#3 N7233 P2606 BST 22 0x41000049 FP BE Pri
!#3 N7234 P2606 BST 23 0x4100004a FP BE Pri
!#3 N7235 P2607 LD 30 -1 Int BE Pri
!#3 N7236 P2608 LD 18 -1 Int BE Pri
!#3 N7237 P2606 BST 20 0x4100004b FP BE Pri
!#3 N7238 P2606 BST 21 0x4100004c FP BE Pri
!#A N7237 N7238
!#3 N7239 P2606 BST 22 0x4100004d FP BE Pri
!#3 N7240 P2606 BST 23 0x4100004e FP BE Pri
!#3 N7241 P2607 LD 30 -1 Int BE Pri
!#3 N7242 P2608 LD 18 -1 Int BE Pri
!#3 N7243 P2609 BLD 8 -1 FP BE Pri
!#3 N7244 P2609 BLD 9 -1 FP BE Pri
!#A N7243 N7244
!#3 N7245 P2609 BLD 10 -1 FP BE Pri
!#3 N7246 P2609 BLD 11 -1 FP BE Pri
!#3 N7247 P2610 LD 26 -1 Int BE Pri
!#3 N7248 P2611 BLD 4 -1 FP BE Pri
!#3 N7249 P2611 BLD 5 -1 FP BE Pri
!#A N7248 N7249
!#3 N7250 P2611 BLD 6 -1 FP BE Pri
!#3 N7251 P2611 BLD 7 -1 FP BE Pri
!#3 N7252 P2612 LD 4 -1 Int BE Pri
!#3 N7253 P2610 LD 26 -1 Int BE Pri
!#3 N7254 P2611 BLD 4 -1 FP BE Pri
!#3 N7255 P2611 BLD 5 -1 FP BE Pri
!#A N7254 N7255
!#3 N7256 P2611 BLD 6 -1 FP BE Pri
!#3 N7257 P2611 BLD 7 -1 FP BE Pri
!#3 N7258 P2612 LD 4 -1 Int BE Pri
!#3 N7259 P2613 BLD 20 -1 FP BE Pri
!#3 N7260 P2613 BLD 21 -1 FP BE Pri
!#A N7259 N7260
!#3 N7261 P2613 BLD 22 -1 FP BE Pri
!#3 N7262 P2613 BLD 23 -1 FP BE Pri
!#3 N7263 P2614 LD 22 -1 Int BE Pri
!#3 N7264 P2615 LD 2 -1 Int BE Pri
!#3 N7265 P2613 BLD 20 -1 FP BE Pri
!#3 N7266 P2613 BLD 21 -1 FP BE Pri
!#A N7265 N7266
!#3 N7267 P2613 BLD 22 -1 FP BE Pri
!#3 N7268 P2613 BLD 23 -1 FP BE Pri
!#3 N7269 P2614 LD 22 -1 Int BE Pri
!#3 N7270 P2615 LD 2 -1 Int BE Pri
!#3 N7271 P2616 DWLD 0 -1 Int BE Pri
!#3 N7272 P2616 DWLD 1 -1 Int BE Pri
!#A N7271 N7272
!#3 N7273 P2616 DWLD 0 -1 Int BE Pri
!#3 N7274 P2616 DWLD 1 -1 Int BE Pri
!#A N7273 N7274
!#3 N7275 P2617 DWLD 24 -1 FP BE Pri
!#3 N7276 P2617 DWLD 25 -1 FP BE Pri
!#A N7275 N7276
!#3 N7277 P2617 DWLD 24 -1 FP BE Pri
!#3 N7278 P2617 DWLD 25 -1 FP BE Pri
!#A N7277 N7278
!#3 N7279 P2618 BLD 16 -1 FP BE Pri
!#3 N7280 P2618 BLD 17 -1 FP BE Pri
!#A N7279 N7280
!#3 N7281 P2618 BLD 18 -1 FP BE Pri
!#3 N7282 P2618 BLD 19 -1 FP BE Pri
!#3 N7283 P2618 BLD 16 -1 FP BE Pri
!#3 N7284 P2618 BLD 17 -1 FP BE Pri
!#A N7283 N7284
!#3 N7285 P2618 BLD 18 -1 FP BE Pri
!#3 N7286 P2618 BLD 19 -1 FP BE Pri
!#3 N7287 P2619 DWLD 24 -1 Int BE Pri
!#3 N7288 P2619 DWLD 25 -1 Int BE Pri
!#A N7287 N7288
!#3 N7289 P2620 DWLD 6 -1 Int BE Pri
!#3 N7290 P2621 BLD 12 -1 FP BE Pri
!#3 N7291 P2621 BLD 13 -1 FP BE Pri
!#A N7290 N7291
!#3 N7292 P2621 BLD 14 -1 FP BE Pri
!#3 N7293 P2621 BLD 15 -1 FP BE Pri
!#3 N7294 P2622 LD 7 -1 Int BE Pri
!#3 N7295 P2623 DWLD 4 -1 Int BE Pri
!#3 N7296 P2623 DWLD 5 -1 Int BE Pri
!#A N7295 N7296
!#3 N7297 P2623 CASX 4 -1 N7295 0x1800040 Int BE Pri
!#3 N7298 P2623 CASX 5 -1 N7296 0x1800041 Int BE Pri
!#A N7297 N7298
!#3 N7299 P2624 BLD 28 -1 FP BE Pri
!#3 N7300 P2624 BLD 29 -1 FP BE Pri
!#A N7299 N7300
!#3 N7301 P2624 BLD 30 -1 FP BE Pri
!#3 N7302 P2624 BLD 31 -1 FP BE Pri
!#3 N7303 P2625 BLD 4 -1 FP BE Pri
!#3 N7304 P2625 BLD 5 -1 FP BE Pri
!#A N7303 N7304
!#3 N7305 P2625 BLD 6 -1 FP BE Pri
!#3 N7306 P2625 BLD 7 -1 FP BE Pri
!#3 N7307 P2626 LD 8 -1 Int BE Pri
!#3 N7308 P2627 LD 12 -1 Int BE Pri
!#3 N7309 P2628 LD 30 -1 Int BE Pri
!#3 N7310 P2629 LD 12 -1 Int BE Pri
!#3 N7311 P2628 LD 30 -1 Int BE Pri
!#3 N7312 P2629 LD 12 -1 Int BE Pri
!#3 N7313 P2630 BLD 8 -1 FP BE Pri
!#3 N7314 P2630 BLD 9 -1 FP BE Pri
!#A N7313 N7314
!#3 N7315 P2630 BLD 10 -1 FP BE Pri
!#3 N7316 P2630 BLD 11 -1 FP BE Pri
!#3 N7317 P2631 LD 20 -1 Int BE Pri
!#3 N7318 P2632 LD 24 -1 Int BE Pri
!#3 N7319 P2630 BLD 8 -1 FP BE Pri
!#3 N7320 P2630 BLD 9 -1 FP BE Pri
!#A N7319 N7320
!#3 N7321 P2630 BLD 10 -1 FP BE Pri
!#3 N7322 P2630 BLD 11 -1 FP BE Pri
!#3 N7323 P2631 LD 20 -1 Int BE Pri
!#3 N7324 P2632 LD 24 -1 Int BE Pri
!#3 N7325 P2633 DWLD 12 -1 Int BE Pri
!#3 N7326 P2633 DWLD 13 -1 Int BE Pri
!#A N7325 N7326
!#3 N7327 P2634 LD 30 -1 Int BE Pri
!#3 N7328 P2635 LD 19 -1 Int BE Pri
!#3 N7329 P2636 BLD 8 -1 FP BE Pri
!#3 N7330 P2636 BLD 9 -1 FP BE Pri
!#A N7329 N7330
!#3 N7331 P2636 BLD 10 -1 FP BE Pri
!#3 N7332 P2636 BLD 11 -1 FP BE Pri
!#3 N7333 P2637 DWLD 0 -1 Int BE Pri
!#3 N7334 P2637 DWLD 1 -1 Int BE Pri
!#A N7333 N7334
!#3 N7335 P2636 BLD 8 -1 FP BE Pri
!#3 N7336 P2636 BLD 9 -1 FP BE Pri
!#A N7335 N7336
!#3 N7337 P2636 BLD 10 -1 FP BE Pri
!#3 N7338 P2636 BLD 11 -1 FP BE Pri
!#3 N7339 P2637 DWLD 0 -1 Int BE Pri
!#3 N7340 P2637 DWLD 1 -1 Int BE Pri
!#A N7339 N7340
!#3 N7341 P2638 LD 18 -1 Int BE Pri
!#3 N7342 P2639 BLD 8 -1 FP BE Pri
!#3 N7343 P2639 BLD 9 -1 FP BE Pri
!#A N7342 N7343
!#3 N7344 P2639 BLD 10 -1 FP BE Pri
!#3 N7345 P2639 BLD 11 -1 FP BE Pri
!#3 N7346 P2640 LD 30 -1 Int BE Pri
!#3 N7347 P2641 BLD 4 -1 FP BE Pri
!#3 N7348 P2641 BLD 5 -1 FP BE Pri
!#A N7347 N7348
!#3 N7349 P2641 BLD 6 -1 FP BE Pri
!#3 N7350 P2641 BLD 7 -1 FP BE Pri
!#3 N7351 P2641 BLD 4 -1 FP BE Pri
!#3 N7352 P2641 BLD 5 -1 FP BE Pri
!#A N7351 N7352
!#3 N7353 P2641 BLD 6 -1 FP BE Pri
!#3 N7354 P2641 BLD 7 -1 FP BE Pri
!#3 N7355 P2642 LD 8 -1 Int BE Pri
!#3 N7356 P2643 LD 15 -1 Int BE Pri
!#3 N7357 P2644 DWLD 4 -1 Int BE Pri
!#3 N7358 P2644 DWLD 5 -1 Int BE Pri
!#A N7357 N7358
!#3 N7359 P2645 BSTC 28 0x4100004f FP BE Pri
!#3 N7360 P2645 BSTC 29 0x41000050 FP BE Pri
!#A N7359 N7360
!#3 N7361 P2645 BSTC 30 0x41000051 FP BE Pri
!#3 N7362 P2645 BSTC 31 0x41000052 FP BE Pri
!#3 N7363 P2646 LD 10 -1 Int BE Pri
!#3 N7364 P2647 LD 15 -1 Int BE Pri
!#3 N7365 P2648 DWLD 15 -1 FP BE Pri
!#3 N7366 P2649 LD 21 -1 Int BE Pri
!#3 N7367 P2650 LD 21 -1 Int BE Pri
!#3 N7368 P2648 DWLD 15 -1 FP BE Pri
!#3 N7369 P2649 LD 21 -1 Int BE Pri
!#3 N7370 P2650 LD 21 -1 Int BE Pri
!#3 N7371 P2651 LD 26 -1 Int BE Pri
!#3 N7372 P2652 LD 17 -1 Int BE Pri
!#3 N7373 P2653 MEMBAR
!#4 N7374 P2654 LD 19 -1 Int BE Pri
!#4 N7375 P2655 LD 23 -1 Int BE Pri
!#4 N7376 P2654 LD 19 -1 Int BE Pri
!#4 N7377 P2655 LD 23 -1 Int BE Pri
!#4 N7378 P2656 LD 3 -1 Int BE Pri
!#4 N7379 P2657 DWLD 12 -1 Int BE Pri
!#4 N7380 P2657 DWLD 13 -1 Int BE Pri
!#A N7379 N7380
!#4 N7381 P2658 LD 6 -1 Int BE Pri
!#4 N7382 P2659 DWLD 23 -1 Int BE Pri
!#4 N7383 P2660 LD 5 -1 Int BE Pri
!#4 N7384 P2659 DWLD 23 -1 Int BE Pri
!#4 N7385 P2660 LD 5 -1 Int BE Pri
!#4 N7386 P2661 ST 8 0x41800001 FP BE Pri
!#4 N7387 P2662 DWLD 30 -1 FP BE Pri
!#4 N7389 P2664 BLD 0 -1 FP BE Pri
!#4 N7390 P2664 BLD 1 -1 FP BE Pri
!#A N7389 N7390
!#4 N7391 P2664 BLD 2 -1 FP BE Pri
!#4 N7392 P2664 BLD 3 -1 FP BE Pri
!#4 N7394 P2664 BLD 0 -1 FP BE Pri
!#4 N7395 P2664 BLD 1 -1 FP BE Pri
!#A N7394 N7395
!#4 N7396 P2664 BLD 2 -1 FP BE Pri
!#4 N7397 P2664 BLD 3 -1 FP BE Pri
!#4 N7398 P2665 LD 14 -1 Int BE Pri
!#4 N7399 P2666 BLD 8 -1 FP BE Pri
!#4 N7400 P2666 BLD 9 -1 FP BE Pri
!#A N7399 N7400
!#4 N7401 P2666 BLD 10 -1 FP BE Pri
!#4 N7402 P2666 BLD 11 -1 FP BE Pri
!#4 N7403 P2667 LD 5 -1 Int BE Pri
!#4 N7404 P2668 BLD 20 -1 FP BE Pri
!#4 N7405 P2668 BLD 21 -1 FP BE Pri
!#A N7404 N7405
!#4 N7406 P2668 BLD 22 -1 FP BE Pri
!#4 N7407 P2668 BLD 23 -1 FP BE Pri
!#4 N7408 P2668 BLD 20 -1 FP BE Pri
!#4 N7409 P2668 BLD 21 -1 FP BE Pri
!#A N7408 N7409
!#4 N7410 P2668 BLD 22 -1 FP BE Pri
!#4 N7411 P2668 BLD 23 -1 FP BE Pri
!#4 N7412 P2669 BLD 8 -1 FP BE Pri
!#4 N7413 P2669 BLD 9 -1 FP BE Pri
!#A N7412 N7413
!#4 N7414 P2669 BLD 10 -1 FP BE Pri
!#4 N7415 P2669 BLD 11 -1 FP BE Pri
!#4 N7416 P2670 MEMBAR
!#4 N7417 P2671 DWLD 8 -1 Int BE Pri
!#4 N7418 P2671 DWLD 9 -1 Int BE Pri
!#A N7417 N7418
!#4 N7419 P2671 DWLD 8 -1 Int BE Pri
!#4 N7420 P2671 DWLD 9 -1 Int BE Pri
!#A N7419 N7420
!#4 N7421 P2672 BLD 28 -1 FP BE Pri
!#4 N7422 P2672 BLD 29 -1 FP BE Pri
!#A N7421 N7422
!#4 N7423 P2672 BLD 30 -1 FP BE Pri
!#4 N7424 P2672 BLD 31 -1 FP BE Pri
!#4 N7425 P2673 BLD 16 -1 FP BE Pri
!#4 N7426 P2673 BLD 17 -1 FP BE Pri
!#A N7425 N7426
!#4 N7427 P2673 BLD 18 -1 FP BE Pri
!#4 N7428 P2673 BLD 19 -1 FP BE Pri
!#4 N7429 P2672 BLD 28 -1 FP BE Pri
!#4 N7430 P2672 BLD 29 -1 FP BE Pri
!#A N7429 N7430
!#4 N7431 P2672 BLD 30 -1 FP BE Pri
!#4 N7432 P2672 BLD 31 -1 FP BE Pri
!#4 N7433 P2673 BLD 16 -1 FP BE Pri
!#4 N7434 P2673 BLD 17 -1 FP BE Pri
!#A N7433 N7434
!#4 N7435 P2673 BLD 18 -1 FP BE Pri
!#4 N7436 P2673 BLD 19 -1 FP BE Pri
!#4 N7437 P2674 BLD 24 -1 FP BE Pri
!#4 N7438 P2674 BLD 25 -1 FP BE Pri
!#A N7437 N7438
!#4 N7439 P2674 BLD 26 -1 FP BE Pri
!#4 N7440 P2674 BLD 27 -1 FP BE Pri
!#4 N7441 P2675 LD 16 -1 Int BE Pri
!#4 N7442 P2676 LD 19 -1 Int BE Pri
!#4 N7443 P2677 BLD 20 -1 FP BE Pri
!#4 N7444 P2677 BLD 21 -1 FP BE Pri
!#A N7443 N7444
!#4 N7445 P2677 BLD 22 -1 FP BE Pri
!#4 N7446 P2677 BLD 23 -1 FP BE Pri
!#4 N7447 P2678 BLD 20 -1 FP BE Pri
!#4 N7448 P2678 BLD 21 -1 FP BE Pri
!#A N7447 N7448
!#4 N7449 P2678 BLD 22 -1 FP BE Pri
!#4 N7450 P2678 BLD 23 -1 FP BE Pri
!#4 N7451 P2677 BLD 20 -1 FP BE Pri
!#4 N7452 P2677 BLD 21 -1 FP BE Pri
!#A N7451 N7452
!#4 N7453 P2677 BLD 22 -1 FP BE Pri
!#4 N7454 P2677 BLD 23 -1 FP BE Pri
!#4 N7455 P2678 BLD 20 -1 FP BE Pri
!#4 N7456 P2678 BLD 21 -1 FP BE Pri
!#A N7455 N7456
!#4 N7457 P2678 BLD 22 -1 FP BE Pri
!#4 N7458 P2678 BLD 23 -1 FP BE Pri
!#4 N7459 P2679 LD 25 -1 Int LE Pri
!#4 N7460 P2680 LD 31 -1 Int BE Pri
!#4 N7461 P2681 LD 11 -1 Int BE Pri
!#4 N7462 P2682 LD 27 -1 Int BE Pri
!#4 N7463 P2681 LD 11 -1 Int BE Pri
!#4 N7464 P2682 LD 27 -1 Int BE Pri
!#4 N7465 P2683 LD 5 -1 Int BE Pri
!#4 N7466 P2684 LD 19 -1 Int BE Pri
!#4 N7467 P2685 BLD 24 -1 FP BE Pri
!#4 N7468 P2685 BLD 25 -1 FP BE Pri
!#A N7467 N7468
!#4 N7469 P2685 BLD 26 -1 FP BE Pri
!#4 N7470 P2685 BLD 27 -1 FP BE Pri
!#4 N7471 P2686 DWLD 28 -1 Int BE Pri
!#4 N7472 P2686 DWLD 29 -1 Int BE Pri
!#A N7471 N7472
!#4 N7473 P2687 LD 23 -1 Int LE Pri
!#4 N7474 P2688 LD 15 -1 Int LE Pri
!#4 N7475 P2686 DWLD 28 -1 Int BE Pri
!#4 N7476 P2686 DWLD 29 -1 Int BE Pri
!#A N7475 N7476
!#4 N7477 P2687 LD 23 -1 Int LE Pri
!#4 N7478 P2688 LD 15 -1 Int LE Pri
!#4 N7479 P2689 BLD 16 -1 FP BE Pri
!#4 N7480 P2689 BLD 17 -1 FP BE Pri
!#A N7479 N7480
!#4 N7481 P2689 BLD 18 -1 FP BE Pri
!#4 N7482 P2689 BLD 19 -1 FP BE Pri
!#4 N7483 P2690 DWLD 2 -1 Int BE Pri
!#4 N7484 P2691 LD 24 -1 Int BE Pri
!#4 N7485 P2689 BLD 16 -1 FP BE Pri
!#4 N7486 P2689 BLD 17 -1 FP BE Pri
!#A N7485 N7486
!#4 N7487 P2689 BLD 18 -1 FP BE Pri
!#4 N7488 P2689 BLD 19 -1 FP BE Pri
!#4 N7489 P2690 DWLD 2 -1 Int BE Pri
!#4 N7490 P2691 LD 24 -1 Int BE Pri
!#4 N7491 P2692 BLD 24 -1 FP BE Pri
!#4 N7492 P2692 BLD 25 -1 FP BE Pri
!#A N7491 N7492
!#4 N7493 P2692 BLD 26 -1 FP BE Pri
!#4 N7494 P2692 BLD 27 -1 FP BE Pri
!#4 N7495 P2693 LD 28 -1 Int BE Pri
!#4 N7496 P2694 LD 2 -1 Int BE Pri
!#4 N7497 P2692 BLD 24 -1 FP BE Pri
!#4 N7498 P2692 BLD 25 -1 FP BE Pri
!#A N7497 N7498
!#4 N7499 P2692 BLD 26 -1 FP BE Pri
!#4 N7500 P2692 BLD 27 -1 FP BE Pri
!#4 N7501 P2693 LD 28 -1 Int BE Pri
!#4 N7502 P2694 LD 2 -1 Int BE Pri
!#4 N7503 P2695 BLD 28 -1 FP BE Pri
!#4 N7504 P2695 BLD 29 -1 FP BE Pri
!#A N7503 N7504
!#4 N7505 P2695 BLD 30 -1 FP BE Pri
!#4 N7506 P2695 BLD 31 -1 FP BE Pri
!#4 N7507 P2695 BLD 28 -1 FP BE Pri
!#4 N7508 P2695 BLD 29 -1 FP BE Pri
!#A N7507 N7508
!#4 N7509 P2695 BLD 30 -1 FP BE Pri
!#4 N7510 P2695 BLD 31 -1 FP BE Pri
!#4 N7511 P2696 BLD 20 -1 FP BE Pri
!#4 N7512 P2696 BLD 21 -1 FP BE Pri
!#A N7511 N7512
!#4 N7513 P2696 BLD 22 -1 FP BE Pri
!#4 N7514 P2696 BLD 23 -1 FP BE Pri
!#4 N7515 P2697 DWLD 12 -1 Int BE Pri
!#4 N7516 P2697 DWLD 13 -1 Int BE Pri
!#A N7515 N7516
!#4 N7517 P2698 DWLD 0 -1 Int BE Pri
!#4 N7518 P2698 DWLD 1 -1 Int BE Pri
!#A N7517 N7518
!#4 N7519 P2698 DWLD 0 -1 Int BE Pri
!#4 N7520 P2698 DWLD 1 -1 Int BE Pri
!#A N7519 N7520
!#4 N7521 P2699 LD 27 -1 Int BE Pri
!#4 N7522 P2700 LD 25 -1 Int BE Pri
!#4 N7523 P2701 BLD 4 -1 FP BE Pri
!#4 N7524 P2701 BLD 5 -1 FP BE Pri
!#A N7523 N7524
!#4 N7525 P2701 BLD 6 -1 FP BE Pri
!#4 N7526 P2701 BLD 7 -1 FP BE Pri
!#4 N7527 P2702 BLD 12 -1 FP BE Pri
!#4 N7528 P2702 BLD 13 -1 FP BE Pri
!#A N7527 N7528
!#4 N7529 P2702 BLD 14 -1 FP BE Pri
!#4 N7530 P2702 BLD 15 -1 FP BE Pri
!#4 N7531 P2701 BLD 4 -1 FP BE Pri
!#4 N7532 P2701 BLD 5 -1 FP BE Pri
!#A N7531 N7532
!#4 N7533 P2701 BLD 6 -1 FP BE Pri
!#4 N7534 P2701 BLD 7 -1 FP BE Pri
!#4 N7535 P2702 BLD 12 -1 FP BE Pri
!#4 N7536 P2702 BLD 13 -1 FP BE Pri
!#A N7535 N7536
!#4 N7537 P2702 BLD 14 -1 FP BE Pri
!#4 N7538 P2702 BLD 15 -1 FP BE Pri
!#4 N7539 P2703 BLD 28 -1 FP BE Pri
!#4 N7540 P2703 BLD 29 -1 FP BE Pri
!#A N7539 N7540
!#4 N7541 P2703 BLD 30 -1 FP BE Pri
!#4 N7542 P2703 BLD 31 -1 FP BE Pri
!#4 N7543 P2704 DWLD 15 -1 Int BE Pri
!#4 N7544 P2705 LD 0 -1 Int BE Pri
!#4 N7545 P2706 LD 23 -1 Int BE Pri
!#4 N7546 P2707 LD 23 -1 Int BE Pri
!#4 N7547 P2706 LD 23 -1 Int BE Pri
!#4 N7548 P2707 LD 23 -1 Int BE Pri
!#4 N7549 P2708 LD 1 -1 Int BE Pri
!#4 N7550 P2709 DWLD 4 -1 Int BE Pri
!#4 N7551 P2709 DWLD 5 -1 Int BE Pri
!#A N7550 N7551
!#4 N7552 P2710 LD 22 -1 Int BE Pri
!#4 N7553 P2708 LD 1 -1 Int BE Pri
!#4 N7554 P2709 DWLD 4 -1 Int BE Pri
!#4 N7555 P2709 DWLD 5 -1 Int BE Pri
!#A N7554 N7555
!#4 N7556 P2710 LD 22 -1 Int BE Pri
!#4 N7557 P2711 BLD 28 -1 FP BE Pri
!#4 N7558 P2711 BLD 29 -1 FP BE Pri
!#A N7557 N7558
!#4 N7559 P2711 BLD 30 -1 FP BE Pri
!#4 N7560 P2711 BLD 31 -1 FP BE Pri
!#4 N7561 P2712 DWLD 12 -1 Int BE Pri
!#4 N7562 P2712 DWLD 13 -1 Int BE Pri
!#A N7561 N7562
!#4 N7563 P2712 CASX 12 -1 N7561 0x2000001 Int BE Pri
!#4 N7564 P2712 CASX 13 -1 N7562 0x2000002 Int BE Pri
!#A N7563 N7564
!#4 N7565 P2713 LD 16 -1 Int BE Pri
!#4 N7566 P2714 LD 1 -1 Int BE Pri
!#4 N7567 P2713 LD 16 -1 Int BE Pri
!#4 N7568 P2714 LD 1 -1 Int BE Pri
!#4 N7569 P2715 BSTC 24 0x41800002 FP BE Pri
!#4 N7570 P2715 BSTC 25 0x41800003 FP BE Pri
!#A N7569 N7570
!#4 N7571 P2715 BSTC 26 0x41800004 FP BE Pri
!#4 N7572 P2715 BSTC 27 0x41800005 FP BE Pri
!#4 N7573 P2716 BLD 12 -1 FP BE Pri
!#4 N7574 P2716 BLD 13 -1 FP BE Pri
!#A N7573 N7574
!#4 N7575 P2716 BLD 14 -1 FP BE Pri
!#4 N7576 P2716 BLD 15 -1 FP BE Pri
!#4 N7577 P2717 LD 26 -1 Int BE Pri
!#4 N7578 P2718 BST 28 0x41800006 FP BE Pri
!#4 N7579 P2718 BST 29 0x41800007 FP BE Pri
!#A N7578 N7579
!#4 N7580 P2718 BST 30 0x41800008 FP BE Pri
!#4 N7581 P2718 BST 31 0x41800009 FP BE Pri
!#4 N7582 P2719 LD 15 -1 Int BE Pri
!#4 N7583 P2720 LD 3 -1 Int BE Pri
!#4 N7584 P2721 LD 13 -1 Int BE Pri
!#4 N7585 P2722 DWLD 3 -1 Int BE Pri
!#4 N7586 P2723 LD 16 -1 Int BE Pri
!#4 N7587 P2724 DWLD 0 -1 Int BE Pri
!#4 N7588 P2724 DWLD 1 -1 Int BE Pri
!#A N7587 N7588
!#4 N7589 P2725 BLD 20 -1 FP BE Pri
!#4 N7590 P2725 BLD 21 -1 FP BE Pri
!#A N7589 N7590
!#4 N7591 P2725 BLD 22 -1 FP BE Pri
!#4 N7592 P2725 BLD 23 -1 FP BE Pri
!#4 N7593 P2726 DWLD 28 -1 Int BE Pri
!#4 N7594 P2726 DWLD 29 -1 Int BE Pri
!#A N7593 N7594
!#4 N7595 P2727 DWLD 26 -1 Int BE Pri
!#4 N7596 P2728 DWLD 24 -1 Int BE Pri
!#4 N7597 P2728 DWLD 25 -1 Int BE Pri
!#A N7596 N7597
!#4 N7598 P2729 LD 24 -1 Int BE Pri
!#4 N7599 P2727 DWLD 26 -1 Int BE Pri
!#4 N7600 P2728 DWLD 24 -1 Int BE Pri
!#4 N7601 P2728 DWLD 25 -1 Int BE Pri
!#A N7600 N7601
!#4 N7602 P2729 LD 24 -1 Int BE Pri
!#4 N7603 P2730 LD 21 -1 Int BE Pri
!#4 N7604 P2731 BLD 20 -1 FP BE Pri
!#4 N7605 P2731 BLD 21 -1 FP BE Pri
!#A N7604 N7605
!#4 N7606 P2731 BLD 22 -1 FP BE Pri
!#4 N7607 P2731 BLD 23 -1 FP BE Pri
!#4 N7608 P2732 LD 29 -1 Int BE Pri
!#4 N7609 P2733 DWLD 4 -1 Int BE Pri
!#4 N7610 P2733 DWLD 5 -1 Int BE Pri
!#A N7609 N7610
!#4 N7611 P2734 LD 20 -1 Int BE Pri
!#4 N7612 P2735 LD 8 -1 Int BE Pri
!#4 N7613 P2733 DWLD 4 -1 Int BE Pri
!#4 N7614 P2733 DWLD 5 -1 Int BE Pri
!#A N7613 N7614
!#4 N7615 P2734 LD 20 -1 Int BE Pri
!#4 N7616 P2735 LD 8 -1 Int BE Pri
!#4 N7617 P2736 BLD 0 -1 FP BE Pri
!#4 N7618 P2736 BLD 1 -1 FP BE Pri
!#A N7617 N7618
!#4 N7619 P2736 BLD 2 -1 FP BE Pri
!#4 N7620 P2736 BLD 3 -1 FP BE Pri
!#4 N7621 P2737 DWLD 22 -1 FP BE Pri
!#4 N7622 P2737 DWLD 22 -1 FP BE Pri
!#4 N7624 P2739 BLD 28 -1 FP BE Pri
!#4 N7625 P2739 BLD 29 -1 FP BE Pri
!#A N7624 N7625
!#4 N7626 P2739 BLD 30 -1 FP BE Pri
!#4 N7627 P2739 BLD 31 -1 FP BE Pri
!#4 N7628 P2740 LD 31 -1 Int BE Pri
!#4 N7629 P2741 LD 24 -1 Int BE Pri
!#4 N7630 P2740 LD 31 -1 Int BE Pri
!#4 N7631 P2741 LD 24 -1 Int BE Pri
!#4 N7632 P2742 LD 10 -1 FP BE Pri
!#4 N7633 P2743 BLD 28 -1 FP BE Pri
!#4 N7634 P2743 BLD 29 -1 FP BE Pri
!#A N7633 N7634
!#4 N7635 P2743 BLD 30 -1 FP BE Pri
!#4 N7636 P2743 BLD 31 -1 FP BE Pri
!#4 N7637 P2742 LD 10 -1 FP BE Pri
!#4 N7638 P2743 BLD 28 -1 FP BE Pri
!#4 N7639 P2743 BLD 29 -1 FP BE Pri
!#A N7638 N7639
!#4 N7640 P2743 BLD 30 -1 FP BE Pri
!#4 N7641 P2743 BLD 31 -1 FP BE Pri
!#4 N7643 P2745 DWLD 24 -1 Int LE Pri
!#4 N7644 P2745 DWLD 25 -1 Int LE Pri
!#A N7643 N7644
!#4 N7646 P2745 DWLD 24 -1 Int LE Pri
!#4 N7647 P2745 DWLD 25 -1 Int LE Pri
!#A N7646 N7647
!#4 N7648 P2746 BLD 20 -1 FP BE Pri
!#4 N7649 P2746 BLD 21 -1 FP BE Pri
!#A N7648 N7649
!#4 N7650 P2746 BLD 22 -1 FP BE Pri
!#4 N7651 P2746 BLD 23 -1 FP BE Pri
!#4 N7652 P2746 BLD 20 -1 FP BE Pri
!#4 N7653 P2746 BLD 21 -1 FP BE Pri
!#A N7652 N7653
!#4 N7654 P2746 BLD 22 -1 FP BE Pri
!#4 N7655 P2746 BLD 23 -1 FP BE Pri
!#4 N7656 P2747 LD 3 -1 Int BE Pri
!#4 N7657 P2748 BLD 4 -1 FP BE Pri
!#4 N7658 P2748 BLD 5 -1 FP BE Pri
!#A N7657 N7658
!#4 N7659 P2748 BLD 6 -1 FP BE Pri
!#4 N7660 P2748 BLD 7 -1 FP BE Pri
!#4 N7661 P2749 LD 2 -1 Int BE Pri
!#4 N7662 P2750 ST 18 0x2000003 Int BE Pri
!#4 N7663 P2751 BLD 4 -1 FP BE Pri
!#4 N7664 P2751 BLD 5 -1 FP BE Pri
!#A N7663 N7664
!#4 N7665 P2751 BLD 6 -1 FP BE Pri
!#4 N7666 P2751 BLD 7 -1 FP BE Pri
!#4 N7667 P2750 ST 18 0x2000004 Int BE Pri
!#4 N7668 P2751 BLD 4 -1 FP BE Pri
!#4 N7669 P2751 BLD 5 -1 FP BE Pri
!#A N7668 N7669
!#4 N7670 P2751 BLD 6 -1 FP BE Pri
!#4 N7671 P2751 BLD 7 -1 FP BE Pri
!#4 N7672 P2752 DWLD 16 -1 Int BE Pri
!#4 N7673 P2752 DWLD 17 -1 Int BE Pri
!#A N7672 N7673
!#4 N7674 P2752 DWLD 16 -1 Int BE Pri
!#4 N7675 P2752 DWLD 17 -1 Int BE Pri
!#A N7674 N7675
!#4 N7676 P2753 DWLD 20 -1 Int BE Pri
!#4 N7677 P2753 DWLD 21 -1 Int BE Pri
!#A N7676 N7677
!#4 N7678 P2754 LD 2 -1 Int BE Pri
!#4 N7679 P2755 LD 17 -1 Int BE Pri
!#4 N7680 P2756 LD 26 -1 Int BE Pri
!#4 N7681 P2757 LD 18 -1 Int BE Pri
!#4 N7682 P2756 LD 26 -1 Int BE Pri
!#4 N7683 P2757 LD 18 -1 Int BE Pri
!#4 N7684 P2758 DWLD 0 -1 Int BE Pri
!#4 N7685 P2758 DWLD 1 -1 Int BE Pri
!#A N7684 N7685
!#4 N7686 P2759 DWLD 24 -1 Int BE Pri
!#4 N7687 P2759 DWLD 25 -1 Int BE Pri
!#A N7686 N7687
!#4 N7688 P2760 LD 29 -1 Int BE Pri
!#4 N7689 P2761 LD 20 -1 Int BE Pri
!#4 N7690 P2762 DWLD 28 -1 Int BE Pri
!#4 N7691 P2762 DWLD 29 -1 Int BE Pri
!#A N7690 N7691
!#4 N7692 P2763 BLD 28 -1 FP BE Pri
!#4 N7693 P2763 BLD 29 -1 FP BE Pri
!#A N7692 N7693
!#4 N7694 P2763 BLD 30 -1 FP BE Pri
!#4 N7695 P2763 BLD 31 -1 FP BE Pri
!#4 N7696 P2762 DWLD 28 -1 Int BE Pri
!#4 N7697 P2762 DWLD 29 -1 Int BE Pri
!#A N7696 N7697
!#4 N7698 P2763 BLD 28 -1 FP BE Pri
!#4 N7699 P2763 BLD 29 -1 FP BE Pri
!#A N7698 N7699
!#4 N7700 P2763 BLD 30 -1 FP BE Pri
!#4 N7701 P2763 BLD 31 -1 FP BE Pri
!#4 N7702 P2764 DWLD 28 -1 Int BE Pri
!#4 N7703 P2764 DWLD 29 -1 Int BE Pri
!#A N7702 N7703
!#4 N7704 P2765 DWLD 0 -1 Int BE Pri
!#4 N7705 P2765 DWLD 1 -1 Int BE Pri
!#A N7704 N7705
!#4 N7706 P2765 CASX 0 -1 N7704 0x2000005 Int BE Pri
!#4 N7707 P2765 CASX 1 -1 N7705 0x2000006 Int BE Pri
!#A N7706 N7707
!#4 N7708 P2764 DWLD 28 -1 Int BE Pri
!#4 N7709 P2764 DWLD 29 -1 Int BE Pri
!#A N7708 N7709
!#4 N7710 P2765 DWLD 0 -1 Int BE Pri
!#4 N7711 P2765 DWLD 1 -1 Int BE Pri
!#A N7710 N7711
!#4 N7712 P2765 CASX 0 -1 N7710 0x2000007 Int BE Pri
!#4 N7713 P2765 CASX 1 -1 N7711 0x2000008 Int BE Pri
!#A N7712 N7713
!#4 N7714 P2766 DWLD 18 -1 Int BE Pri
!#4 N7715 P2767 LD 18 -1 Int BE Pri
!#4 N7716 P2766 DWLD 18 -1 Int BE Pri
!#4 N7717 P2767 LD 18 -1 Int BE Pri
!#4 N7718 P2768 BLD 12 -1 FP BE Pri
!#4 N7719 P2768 BLD 13 -1 FP BE Pri
!#A N7718 N7719
!#4 N7720 P2768 BLD 14 -1 FP BE Pri
!#4 N7721 P2768 BLD 15 -1 FP BE Pri
!#4 N7722 P2769 BLD 8 -1 FP BE Pri
!#4 N7723 P2769 BLD 9 -1 FP BE Pri
!#A N7722 N7723
!#4 N7724 P2769 BLD 10 -1 FP BE Pri
!#4 N7725 P2769 BLD 11 -1 FP BE Pri
!#4 N7726 P2770 DWLD 30 -1 Int BE Pri
!#4 N7727 P2771 LD 7 -1 Int BE Pri
!#4 N7728 P2772 ST 24 0x2000009 Int BE Pri
!#4 N7729 P2773 BLD 8 -1 FP BE Pri
!#4 N7730 P2773 BLD 9 -1 FP BE Pri
!#A N7729 N7730
!#4 N7731 P2773 BLD 10 -1 FP BE Pri
!#4 N7732 P2773 BLD 11 -1 FP BE Pri
!#4 N7733 P2774 BLD 20 -1 FP BE Pri
!#4 N7734 P2774 BLD 21 -1 FP BE Pri
!#A N7733 N7734
!#4 N7735 P2774 BLD 22 -1 FP BE Pri
!#4 N7736 P2774 BLD 23 -1 FP BE Pri
!#4 N7737 P2775 BLD 28 -1 FP BE Pri
!#4 N7738 P2775 BLD 29 -1 FP BE Pri
!#A N7737 N7738
!#4 N7739 P2775 BLD 30 -1 FP BE Pri
!#4 N7740 P2775 BLD 31 -1 FP BE Pri
!#4 N7741 P2775 BLD 28 -1 FP BE Pri
!#4 N7742 P2775 BLD 29 -1 FP BE Pri
!#A N7741 N7742
!#4 N7743 P2775 BLD 30 -1 FP BE Pri
!#4 N7744 P2775 BLD 31 -1 FP BE Pri
!#4 N7745 P2776 LD 19 -1 Int BE Pri
!#4 N7746 P2777 ST 0 0x4180000a FP BE Pri
!#4 N7747 P2778 LD 6 -1 Int BE Pri
!#4 N7748 P2776 LD 19 -1 Int BE Pri
!#4 N7749 P2777 ST 0 0x4180000b FP BE Pri
!#4 N7750 P2778 LD 6 -1 Int BE Pri
!#4 N7751 P2779 LD 10 -1 Int BE Pri
!#4 N7752 P2780 BLD 16 -1 FP BE Pri
!#4 N7753 P2780 BLD 17 -1 FP BE Pri
!#A N7752 N7753
!#4 N7754 P2780 BLD 18 -1 FP BE Pri
!#4 N7755 P2780 BLD 19 -1 FP BE Pri
!#4 N7756 P2781 LD 3 -1 Int LE Pri
!#4 N7757 P2782 DWLD 6 -1 Int BE Pri
!#4 N7758 P2783 DWLD 28 -1 Int BE Pri
!#4 N7759 P2783 DWLD 29 -1 Int BE Pri
!#A N7758 N7759
!#4 N7760 P2784 LD 5 -1 Int BE Pri
!#4 N7761 P2785 ST 31 0x200000a Int BE Pri
!#4 N7762 P2786 DWLD 16 -1 FP BE Pri
!#4 N7763 P2786 DWLD 17 -1 FP BE Pri
!#A N7762 N7763
!#4 N7764 P2785 ST 31 0x200000b Int BE Pri
!#4 N7765 P2786 DWLD 16 -1 FP BE Pri
!#4 N7766 P2786 DWLD 17 -1 FP BE Pri
!#A N7765 N7766
!#4 N7767 P2787 LD 20 -1 Int BE Pri
!#4 N7768 P2788 LD 21 -1 Int BE Pri
!#4 N7769 P2789 LD 5 -1 Int LE Pri
!#4 N7770 P2790 LD 22 -1 Int BE Pri
!#4 N7771 P2791 BLD 20 -1 FP BE Pri
!#4 N7772 P2791 BLD 21 -1 FP BE Pri
!#A N7771 N7772
!#4 N7773 P2791 BLD 22 -1 FP BE Pri
!#4 N7774 P2791 BLD 23 -1 FP BE Pri
!#4 N7775 P2791 BLD 20 -1 FP BE Pri
!#4 N7776 P2791 BLD 21 -1 FP BE Pri
!#A N7775 N7776
!#4 N7777 P2791 BLD 22 -1 FP BE Pri
!#4 N7778 P2791 BLD 23 -1 FP BE Pri
!#4 N7779 P2792 LD 27 -1 Int BE Pri
!#4 N7780 P2793 BST 8 0x4180000c FP BE Pri
!#4 N7781 P2793 BST 9 0x4180000d FP BE Pri
!#A N7780 N7781
!#4 N7782 P2793 BST 10 0x4180000e FP BE Pri
!#4 N7783 P2793 BST 11 0x4180000f FP BE Pri
!#4 N7784 P2794 LD 10 -1 Int BE Pri
!#4 N7785 P2792 LD 27 -1 Int BE Pri
!#4 N7786 P2793 BST 8 0x41800010 FP BE Pri
!#4 N7787 P2793 BST 9 0x41800011 FP BE Pri
!#A N7786 N7787
!#4 N7788 P2793 BST 10 0x41800012 FP BE Pri
!#4 N7789 P2793 BST 11 0x41800013 FP BE Pri
!#4 N7790 P2794 LD 10 -1 Int BE Pri
!#4 N7791 P2795 BLD 4 -1 FP BE Pri
!#4 N7792 P2795 BLD 5 -1 FP BE Pri
!#A N7791 N7792
!#4 N7793 P2795 BLD 6 -1 FP BE Pri
!#4 N7794 P2795 BLD 7 -1 FP BE Pri
!#4 N7795 P2796 BLD 0 -1 FP BE Pri
!#4 N7796 P2796 BLD 1 -1 FP BE Pri
!#A N7795 N7796
!#4 N7797 P2796 BLD 2 -1 FP BE Pri
!#4 N7798 P2796 BLD 3 -1 FP BE Pri
!#4 N7799 P2797 DWLD 26 -1 Int BE Pri
!#4 N7800 P2798 LD 15 -1 FP BE Pri
!#4 N7801 P2799 LD 14 -1 Int BE Pri
!#4 N7802 P2797 DWLD 26 -1 Int BE Pri
!#4 N7803 P2798 LD 15 -1 FP BE Pri
!#4 N7804 P2799 LD 14 -1 Int BE Pri
!#4 N7805 P2800 LD 11 -1 Int BE Pri
!#4 N7806 P2801 LD 1 -1 Int BE Pri
!#4 N7807 P2800 LD 11 -1 Int BE Pri
!#4 N7808 P2801 LD 1 -1 Int BE Pri
!#4 N7809 P2802 DWLD 24 -1 Int BE Pri
!#4 N7810 P2802 DWLD 25 -1 Int BE Pri
!#A N7809 N7810
!#4 N7811 P2802 DWLD 24 -1 Int BE Pri
!#4 N7812 P2802 DWLD 25 -1 Int BE Pri
!#A N7811 N7812
!#4 N7813 P2803 LD 13 -1 Int BE Pri
!#4 N7814 P2804 LD 31 -1 Int BE Pri
!#4 N7815 P2803 LD 13 -1 Int BE Pri
!#4 N7816 P2804 LD 31 -1 Int BE Pri
!#4 N7817 P2805 LD 19 -1 Int BE Pri
!#4 N7818 P2806 LD 8 -1 Int BE Pri
!#4 N7819 P2805 LD 19 -1 Int BE Pri
!#4 N7820 P2806 LD 8 -1 Int BE Pri
!#4 N7821 P2807 BLD 16 -1 FP BE Pri
!#4 N7822 P2807 BLD 17 -1 FP BE Pri
!#A N7821 N7822
!#4 N7823 P2807 BLD 18 -1 FP BE Pri
!#4 N7824 P2807 BLD 19 -1 FP BE Pri
!#4 N7825 P2808 DWLD 22 -1 Int BE Pri
!#4 N7826 P2809 LD 22 -1 Int BE Pri
!#4 N7827 P2808 DWLD 22 -1 Int BE Pri
!#4 N7828 P2809 LD 22 -1 Int BE Pri
!#4 N7829 P2810 BLD 0 -1 FP BE Pri
!#4 N7830 P2810 BLD 1 -1 FP BE Pri
!#A N7829 N7830
!#4 N7831 P2810 BLD 2 -1 FP BE Pri
!#4 N7832 P2810 BLD 3 -1 FP BE Pri
!#4 N7833 P2811 DWST 12 0x200000c Int BE Pri
!#4 N7834 P2811 DWST 13 0x200000d Int BE Pri
!#A N7833 N7834
!#4 N7835 P2811 DWST 12 0x200000e Int BE Pri
!#4 N7836 P2811 DWST 13 0x200000f Int BE Pri
!#A N7835 N7836
!#4 N7837 P2812 BLD 4 -1 FP BE Pri
!#4 N7838 P2812 BLD 5 -1 FP BE Pri
!#A N7837 N7838
!#4 N7839 P2812 BLD 6 -1 FP BE Pri
!#4 N7840 P2812 BLD 7 -1 FP BE Pri
!#4 N7841 P2813 MEMBAR
!#4 N7842 P2814 LD 20 -1 Int BE Pri
!#4 N7843 P2815 SWAP 27 0xffffffff 0x2000010 Int BE Pri
!#4 N7844 P2814 LD 20 -1 Int BE Pri
!#4 N7845 P2815 SWAP 27 0xffffffff 0x2000011 Int BE Pri
!#4 N7846 P2816 BLD 16 -1 FP BE Pri
!#4 N7847 P2816 BLD 17 -1 FP BE Pri
!#A N7846 N7847
!#4 N7848 P2816 BLD 18 -1 FP BE Pri
!#4 N7849 P2816 BLD 19 -1 FP BE Pri
!#4 N7850 P2817 LD 22 -1 Int BE Pri
!#4 N7851 P2818 LD 17 -1 Int BE Pri
!#4 N7852 P2819 LD 6 -1 Int BE Pri
!#4 N7853 P2820 LD 12 -1 Int BE Pri
!#4 N7854 P2821 BLD 28 -1 FP BE Pri
!#4 N7855 P2821 BLD 29 -1 FP BE Pri
!#A N7854 N7855
!#4 N7856 P2821 BLD 30 -1 FP BE Pri
!#4 N7857 P2821 BLD 31 -1 FP BE Pri
!#4 N7858 P2821 BLD 28 -1 FP BE Pri
!#4 N7859 P2821 BLD 29 -1 FP BE Pri
!#A N7858 N7859
!#4 N7860 P2821 BLD 30 -1 FP BE Pri
!#4 N7861 P2821 BLD 31 -1 FP BE Pri
!#4 N7862 P2822 LD 5 -1 Int BE Pri
!#4 N7863 P2823 LD 13 -1 Int BE Pri
!#4 N7864 P2824 DWLD 24 -1 Int BE Pri
!#4 N7865 P2824 DWLD 25 -1 Int BE Pri
!#A N7864 N7865
!#4 N7866 P2824 DWLD 24 -1 Int BE Pri
!#4 N7867 P2824 DWLD 25 -1 Int BE Pri
!#A N7866 N7867
!#4 N7868 P2825 DWLD 20 -1 Int BE Pri
!#4 N7869 P2825 DWLD 21 -1 Int BE Pri
!#A N7868 N7869
!#4 N7870 P2826 BLD 28 -1 FP BE Pri
!#4 N7871 P2826 BLD 29 -1 FP BE Pri
!#A N7870 N7871
!#4 N7872 P2826 BLD 30 -1 FP BE Pri
!#4 N7873 P2826 BLD 31 -1 FP BE Pri
!#4 N7874 P2827 BLD 24 -1 FP BE Pri
!#4 N7875 P2827 BLD 25 -1 FP BE Pri
!#A N7874 N7875
!#4 N7876 P2827 BLD 26 -1 FP BE Pri
!#4 N7877 P2827 BLD 27 -1 FP BE Pri
!#4 N7878 P2828 DWLD 6 -1 Int BE Pri
!#4 N7879 P2829 LD 15 -1 Int BE Pri
!#4 N7880 P2830 DWLD 12 -1 Int BE Pri
!#4 N7881 P2830 DWLD 13 -1 Int BE Pri
!#A N7880 N7881
!#4 N7882 P2831 LD 9 -1 Int BE Pri
!#4 N7883 P2832 LD 6 -1 Int BE Pri
!#4 N7884 P2833 DWLD 24 -1 Int BE Pri
!#4 N7885 P2833 DWLD 25 -1 Int BE Pri
!#A N7884 N7885
!#4 N7886 P2834 DWLD 0 -1 Int BE Pri
!#4 N7887 P2834 DWLD 1 -1 Int BE Pri
!#A N7886 N7887
!#4 N7888 P2833 DWLD 24 -1 Int BE Pri
!#4 N7889 P2833 DWLD 25 -1 Int BE Pri
!#A N7888 N7889
!#4 N7890 P2834 DWLD 0 -1 Int BE Pri
!#4 N7891 P2834 DWLD 1 -1 Int BE Pri
!#A N7890 N7891
!#4 N7892 P2835 BLD 16 -1 FP BE Pri
!#4 N7893 P2835 BLD 17 -1 FP BE Pri
!#A N7892 N7893
!#4 N7894 P2835 BLD 18 -1 FP BE Pri
!#4 N7895 P2835 BLD 19 -1 FP BE Pri
!#4 N7896 P2836 DWST 15 0x41800014 FP BE Pri
!#4 N7897 P2837 DWLD 4 -1 Int BE Pri
!#4 N7898 P2837 DWLD 5 -1 Int BE Pri
!#A N7897 N7898
!#4 N7899 P2838 BST 0 0x41800015 FP BE Pri
!#4 N7900 P2838 BST 1 0x41800016 FP BE Pri
!#A N7899 N7900
!#4 N7901 P2838 BST 2 0x41800017 FP BE Pri
!#4 N7902 P2838 BST 3 0x41800018 FP BE Pri
!#4 N7903 P2838 BST 0 0x41800019 FP BE Pri
!#4 N7904 P2838 BST 1 0x4180001a FP BE Pri
!#A N7903 N7904
!#4 N7905 P2838 BST 2 0x4180001b FP BE Pri
!#4 N7906 P2838 BST 3 0x4180001c FP BE Pri
!#4 N7907 P2839 BLD 8 -1 FP BE Pri
!#4 N7908 P2839 BLD 9 -1 FP BE Pri
!#A N7907 N7908
!#4 N7909 P2839 BLD 10 -1 FP BE Pri
!#4 N7910 P2839 BLD 11 -1 FP BE Pri
!#4 N7911 P2840 DWLD 4 -1 Int BE Pri
!#4 N7912 P2840 DWLD 5 -1 Int BE Pri
!#A N7911 N7912
!#4 N7913 P2841 DWLD 8 -1 Int BE Pri
!#4 N7914 P2841 DWLD 9 -1 Int BE Pri
!#A N7913 N7914
!#4 N7915 P2842 LD 31 -1 Int BE Pri
!#4 N7916 P2843 LD 26 -1 Int BE Pri
!#4 N7917 P2842 LD 31 -1 Int BE Pri
!#4 N7918 P2843 LD 26 -1 Int BE Pri
!#4 N7919 P2844 DWLD 0 -1 Int BE Pri
!#4 N7920 P2844 DWLD 1 -1 Int BE Pri
!#A N7919 N7920
!#4 N7921 P2845 DWLD 20 -1 Int BE Pri
!#4 N7922 P2845 DWLD 21 -1 Int BE Pri
!#A N7921 N7922
!#4 N7923 P2846 DWST 15 0x2000012 Int BE Pri
!#4 N7924 P2846 DWST 15 0x2000013 Int BE Pri
!#4 N7925 P2847 BLD 28 -1 FP BE Pri
!#4 N7926 P2847 BLD 29 -1 FP BE Pri
!#A N7925 N7926
!#4 N7927 P2847 BLD 30 -1 FP BE Pri
!#4 N7928 P2847 BLD 31 -1 FP BE Pri
!#4 N7929 P2848 DWST 18 0x2000014 Int BE Pri
!#4 N7930 P2849 BLD 4 -1 FP BE Pri
!#4 N7931 P2849 BLD 5 -1 FP BE Pri
!#A N7930 N7931
!#4 N7932 P2849 BLD 6 -1 FP BE Pri
!#4 N7933 P2849 BLD 7 -1 FP BE Pri
!#4 N7934 P2850 LD 30 -1 Int BE Pri
!#4 N7935 P2851 LD 18 -1 Int BE Pri
!#4 N7936 P2849 BLD 4 -1 FP BE Pri
!#4 N7937 P2849 BLD 5 -1 FP BE Pri
!#A N7936 N7937
!#4 N7938 P2849 BLD 6 -1 FP BE Pri
!#4 N7939 P2849 BLD 7 -1 FP BE Pri
!#4 N7940 P2850 LD 30 -1 Int BE Pri
!#4 N7941 P2851 LD 18 -1 Int BE Pri
!#4 N7942 P2852 DWLD 28 -1 Int BE Pri
!#4 N7943 P2852 DWLD 29 -1 Int BE Pri
!#A N7942 N7943
!#4 N7944 P2852 DWLD 28 -1 Int BE Pri
!#4 N7945 P2852 DWLD 29 -1 Int BE Pri
!#A N7944 N7945
!#4 N7946 P2853 DWLD 0 -1 Int BE Pri
!#4 N7947 P2853 DWLD 1 -1 Int BE Pri
!#A N7946 N7947
!#4 N7948 P2854 BLD 8 -1 FP BE Pri
!#4 N7949 P2854 BLD 9 -1 FP BE Pri
!#A N7948 N7949
!#4 N7950 P2854 BLD 10 -1 FP BE Pri
!#4 N7951 P2854 BLD 11 -1 FP BE Pri
!#4 N7952 P2855 BLD 16 -1 FP BE Pri
!#4 N7953 P2855 BLD 17 -1 FP BE Pri
!#A N7952 N7953
!#4 N7954 P2855 BLD 18 -1 FP BE Pri
!#4 N7955 P2855 BLD 19 -1 FP BE Pri
!#4 N7956 P2856 BLD 16 -1 FP BE Pri
!#4 N7957 P2856 BLD 17 -1 FP BE Pri
!#A N7956 N7957
!#4 N7958 P2856 BLD 18 -1 FP BE Pri
!#4 N7959 P2856 BLD 19 -1 FP BE Pri
!#4 N7960 P2857 BSTC 12 0x4180001d FP BE Pri
!#4 N7961 P2857 BSTC 13 0x4180001e FP BE Pri
!#A N7960 N7961
!#4 N7962 P2857 BSTC 14 0x4180001f FP BE Pri
!#4 N7963 P2857 BSTC 15 0x41800020 FP BE Pri
!#4 N7964 P2858 DWLD 16 -1 Int BE Pri
!#4 N7965 P2858 DWLD 17 -1 Int BE Pri
!#A N7964 N7965
!#4 N7966 P2857 BSTC 12 0x41800021 FP BE Pri
!#4 N7967 P2857 BSTC 13 0x41800022 FP BE Pri
!#A N7966 N7967
!#4 N7968 P2857 BSTC 14 0x41800023 FP BE Pri
!#4 N7969 P2857 BSTC 15 0x41800024 FP BE Pri
!#4 N7970 P2858 DWLD 16 -1 Int BE Pri
!#4 N7971 P2858 DWLD 17 -1 Int BE Pri
!#A N7970 N7971
!#4 N7972 P2859 DWLD 20 -1 Int BE Pri
!#4 N7973 P2859 DWLD 21 -1 Int BE Pri
!#A N7972 N7973
!#4 N7974 P2860 DWLD 28 -1 Int BE Pri
!#4 N7975 P2860 DWLD 29 -1 Int BE Pri
!#A N7974 N7975
!#4 N7976 P2861 BLD 8 -1 FP BE Pri
!#4 N7977 P2861 BLD 9 -1 FP BE Pri
!#A N7976 N7977
!#4 N7978 P2861 BLD 10 -1 FP BE Pri
!#4 N7979 P2861 BLD 11 -1 FP BE Pri
!#4 N7980 P2861 BLD 8 -1 FP BE Pri
!#4 N7981 P2861 BLD 9 -1 FP BE Pri
!#A N7980 N7981
!#4 N7982 P2861 BLD 10 -1 FP BE Pri
!#4 N7983 P2861 BLD 11 -1 FP BE Pri
!#4 N7984 P2862 LD 6 -1 Int BE Pri
!#4 N7985 P2863 BLD 28 -1 FP BE Pri
!#4 N7986 P2863 BLD 29 -1 FP BE Pri
!#A N7985 N7986
!#4 N7987 P2863 BLD 30 -1 FP BE Pri
!#4 N7988 P2863 BLD 31 -1 FP BE Pri
!#4 N7989 P2864 LD 3 -1 Int BE Pri
!#4 N7990 P2862 LD 6 -1 Int BE Pri
!#4 N7991 P2863 BLD 28 -1 FP BE Pri
!#4 N7992 P2863 BLD 29 -1 FP BE Pri
!#A N7991 N7992
!#4 N7993 P2863 BLD 30 -1 FP BE Pri
!#4 N7994 P2863 BLD 31 -1 FP BE Pri
!#4 N7995 P2864 LD 3 -1 Int BE Pri
!#4 N7996 P2865 BST 8 0x41800025 FP BE Pri
!#4 N7997 P2865 BST 9 0x41800026 FP BE Pri
!#A N7996 N7997
!#4 N7998 P2865 BST 10 0x41800027 FP BE Pri
!#4 N7999 P2865 BST 11 0x41800028 FP BE Pri
!#4 N8000 P2866 BLD 4 -1 FP BE Pri
!#4 N8001 P2866 BLD 5 -1 FP BE Pri
!#A N8000 N8001
!#4 N8002 P2866 BLD 6 -1 FP BE Pri
!#4 N8003 P2866 BLD 7 -1 FP BE Pri
!#4 N8004 P2865 BST 8 0x41800029 FP BE Pri
!#4 N8005 P2865 BST 9 0x4180002a FP BE Pri
!#A N8004 N8005
!#4 N8006 P2865 BST 10 0x4180002b FP BE Pri
!#4 N8007 P2865 BST 11 0x4180002c FP BE Pri
!#4 N8008 P2866 BLD 4 -1 FP BE Pri
!#4 N8009 P2866 BLD 5 -1 FP BE Pri
!#A N8008 N8009
!#4 N8010 P2866 BLD 6 -1 FP BE Pri
!#4 N8011 P2866 BLD 7 -1 FP BE Pri
!#4 N8012 P2867 DWLD 6 -1 Int BE Pri
!#4 N8013 P2868 DWLD 12 -1 Int BE Pri
!#4 N8014 P2868 DWLD 13 -1 Int BE Pri
!#A N8013 N8014
!#4 N8015 P2869 LD 11 -1 Int BE Pri
!#4 N8016 P2867 DWLD 6 -1 Int BE Pri
!#4 N8017 P2868 DWLD 12 -1 Int BE Pri
!#4 N8018 P2868 DWLD 13 -1 Int BE Pri
!#A N8017 N8018
!#4 N8019 P2869 LD 11 -1 Int BE Pri
!#4 N8020 P2870 DWLD 7 -1 Int BE Pri
!#4 N8021 P2871 DWLD 28 -1 Int BE Pri
!#4 N8022 P2871 DWLD 29 -1 Int BE Pri
!#A N8021 N8022
!#4 N8023 P2872 LD 2 -1 Int BE Pri
!#4 N8024 P2870 DWLD 7 -1 Int BE Pri
!#4 N8025 P2871 DWLD 28 -1 Int BE Pri
!#4 N8026 P2871 DWLD 29 -1 Int BE Pri
!#A N8025 N8026
!#4 N8027 P2872 LD 2 -1 Int BE Pri
!#4 N8028 P2873 DWLD 8 -1 Int BE Pri
!#4 N8029 P2873 DWLD 9 -1 Int BE Pri
!#A N8028 N8029
!#4 N8030 P2873 CASX 8 -1 N8028 0x2000015 Int BE Pri
!#4 N8031 P2873 CASX 9 -1 N8029 0x2000016 Int BE Pri
!#A N8030 N8031
!#4 N8032 P2873 DWLD 8 -1 Int BE Pri
!#4 N8033 P2873 DWLD 9 -1 Int BE Pri
!#A N8032 N8033
!#4 N8034 P2873 CASX 8 -1 N8032 0x2000017 Int BE Pri
!#4 N8035 P2873 CASX 9 -1 N8033 0x2000018 Int BE Pri
!#A N8034 N8035
!#4 N8036 P2874 DWLD 19 -1 Int BE Pri
!#4 N8037 P2875 LD 28 -1 Int BE Pri
!#4 N8038 P2874 DWLD 19 -1 Int BE Pri
!#4 N8039 P2875 LD 28 -1 Int BE Pri
!#4 N8040 P2876 LD 11 -1 Int BE Pri
!#4 N8041 P2877 BLD 0 -1 FP BE Pri
!#4 N8042 P2877 BLD 1 -1 FP BE Pri
!#A N8041 N8042
!#4 N8043 P2877 BLD 2 -1 FP BE Pri
!#4 N8044 P2877 BLD 3 -1 FP BE Pri
!#4 N8045 P2878 LD 8 -1 Int BE Pri
!#4 N8046 P2876 LD 11 -1 Int BE Pri
!#4 N8047 P2877 BLD 0 -1 FP BE Pri
!#4 N8048 P2877 BLD 1 -1 FP BE Pri
!#A N8047 N8048
!#4 N8049 P2877 BLD 2 -1 FP BE Pri
!#4 N8050 P2877 BLD 3 -1 FP BE Pri
!#4 N8051 P2878 LD 8 -1 Int BE Pri
!#4 N8052 P2879 DWLD 31 -1 Int BE Pri
!#4 N8053 P2880 LD 4 -1 Int BE Pri
!#4 N8054 P2880 CAS 4 -1 N8053 0x2000019 Int BE Pri
!#4 N8055 P2881 LD 21 -1 Int BE Pri
!#4 N8056 P2882 LD 7 -1 Int BE Pri
!#4 N8057 P2883 LD 0 -1 Int BE Pri
!#4 N8058 P2882 LD 7 -1 Int BE Pri
!#4 N8059 P2883 LD 0 -1 Int BE Pri
!#4 N8060 P2884 BLD 0 -1 FP BE Pri
!#4 N8061 P2884 BLD 1 -1 FP BE Pri
!#A N8060 N8061
!#4 N8062 P2884 BLD 2 -1 FP BE Pri
!#4 N8063 P2884 BLD 3 -1 FP BE Pri
!#4 N8064 P2884 BLD 0 -1 FP BE Pri
!#4 N8065 P2884 BLD 1 -1 FP BE Pri
!#A N8064 N8065
!#4 N8066 P2884 BLD 2 -1 FP BE Pri
!#4 N8067 P2884 BLD 3 -1 FP BE Pri
!#4 N8068 P2885 LD 28 -1 Int BE Pri
!#4 N8069 P2886 DWLD 31 -1 Int BE Pri
!#4 N8070 P2887 BLD 16 -1 FP BE Pri
!#4 N8071 P2887 BLD 17 -1 FP BE Pri
!#A N8070 N8071
!#4 N8072 P2887 BLD 18 -1 FP BE Pri
!#4 N8073 P2887 BLD 19 -1 FP BE Pri
!#4 N8074 P2887 BLD 16 -1 FP BE Pri
!#4 N8075 P2887 BLD 17 -1 FP BE Pri
!#A N8074 N8075
!#4 N8076 P2887 BLD 18 -1 FP BE Pri
!#4 N8077 P2887 BLD 19 -1 FP BE Pri
!#4 N8078 P2888 BLD 20 -1 FP BE Pri
!#4 N8079 P2888 BLD 21 -1 FP BE Pri
!#A N8078 N8079
!#4 N8080 P2888 BLD 22 -1 FP BE Pri
!#4 N8081 P2888 BLD 23 -1 FP BE Pri
!#4 N8082 P2889 LD 20 -1 Int BE Pri
!#4 N8083 P2890 LD 17 -1 Int BE Pri
!#4 N8084 P2891 DWLD 23 -1 Int BE Pri
!#4 N8085 P2892 LD 28 -1 Int BE Pri
!#4 N8086 P2891 DWLD 23 -1 Int BE Pri
!#4 N8087 P2892 LD 28 -1 Int BE Pri
!#4 N8088 P2893 DWLD 14 -1 Int BE Pri
!#4 N8089 P2894 LD 24 -1 Int BE Pri
!#4 N8090 P2893 DWLD 14 -1 Int BE Pri
!#4 N8091 P2894 LD 24 -1 Int BE Pri
!#4 N8092 P2895 DWLD 30 -1 Int BE Pri
!#4 N8093 P2896 BLD 8 -1 FP BE Pri
!#4 N8094 P2896 BLD 9 -1 FP BE Pri
!#A N8093 N8094
!#4 N8095 P2896 BLD 10 -1 FP BE Pri
!#4 N8096 P2896 BLD 11 -1 FP BE Pri
!#4 N8097 P2897 LD 21 -1 Int BE Pri
!#4 N8098 P2898 BLD 12 -1 FP BE Pri
!#4 N8099 P2898 BLD 13 -1 FP BE Pri
!#A N8098 N8099
!#4 N8100 P2898 BLD 14 -1 FP BE Pri
!#4 N8101 P2898 BLD 15 -1 FP BE Pri
!#4 N8102 P2899 BLD 28 -1 FP BE Pri
!#4 N8103 P2899 BLD 29 -1 FP BE Pri
!#A N8102 N8103
!#4 N8104 P2899 BLD 30 -1 FP BE Pri
!#4 N8105 P2899 BLD 31 -1 FP BE Pri
!#4 N8106 P2898 BLD 12 -1 FP BE Pri
!#4 N8107 P2898 BLD 13 -1 FP BE Pri
!#A N8106 N8107
!#4 N8108 P2898 BLD 14 -1 FP BE Pri
!#4 N8109 P2898 BLD 15 -1 FP BE Pri
!#4 N8110 P2899 BLD 28 -1 FP BE Pri
!#4 N8111 P2899 BLD 29 -1 FP BE Pri
!#A N8110 N8111
!#4 N8112 P2899 BLD 30 -1 FP BE Pri
!#4 N8113 P2899 BLD 31 -1 FP BE Pri
!#4 N8114 P2900 BLD 4 -1 FP BE Pri
!#4 N8115 P2900 BLD 5 -1 FP BE Pri
!#A N8114 N8115
!#4 N8116 P2900 BLD 6 -1 FP BE Pri
!#4 N8117 P2900 BLD 7 -1 FP BE Pri
!#4 N8118 P2901 DWLD 12 -1 FP BE Pri
!#4 N8119 P2901 DWLD 13 -1 FP BE Pri
!#A N8118 N8119
!#4 N8120 P2901 DWLD 12 -1 FP BE Pri
!#4 N8121 P2901 DWLD 13 -1 FP BE Pri
!#A N8120 N8121
!#4 N8122 P2902 BLD 28 -1 FP BE Pri
!#4 N8123 P2902 BLD 29 -1 FP BE Pri
!#A N8122 N8123
!#4 N8124 P2902 BLD 30 -1 FP BE Pri
!#4 N8125 P2902 BLD 31 -1 FP BE Pri
!#4 N8126 P2903 BLD 8 -1 FP BE Pri
!#4 N8127 P2903 BLD 9 -1 FP BE Pri
!#A N8126 N8127
!#4 N8128 P2903 BLD 10 -1 FP BE Pri
!#4 N8129 P2903 BLD 11 -1 FP BE Pri
!#4 N8130 P2903 BLD 8 -1 FP BE Pri
!#4 N8131 P2903 BLD 9 -1 FP BE Pri
!#A N8130 N8131
!#4 N8132 P2903 BLD 10 -1 FP BE Pri
!#4 N8133 P2903 BLD 11 -1 FP BE Pri
!#4 N8134 P2904 BLD 8 -1 FP BE Pri
!#4 N8135 P2904 BLD 9 -1 FP BE Pri
!#A N8134 N8135
!#4 N8136 P2904 BLD 10 -1 FP BE Pri
!#4 N8137 P2904 BLD 11 -1 FP BE Pri
!#4 N8138 P2905 SWAP 19 0xffffffff 0x200001a Int BE Pri
!#4 N8139 P2906 LD 20 -1 Int BE Pri
!#4 N8140 P2907 LD 15 -1 Int BE Pri
!#4 N8142 P2909 LD 28 -1 Int BE Pri
!#4 N8143 P2907 LD 15 -1 Int BE Pri
!#4 N8145 P2909 LD 28 -1 Int BE Pri
!#4 N8146 P2910 LD 3 -1 Int BE Pri
!#4 N8147 P2911 ST 19 0x200001b Int BE Pri
!#4 N8148 P2912 LD 7 -1 Int BE Pri
!#4 N8149 P2910 LD 3 -1 Int BE Pri
!#4 N8150 P2911 ST 19 0x200001c Int BE Pri
!#4 N8151 P2912 LD 7 -1 Int BE Pri
!#4 N8152 P2913 ST 5 0x200001d Int LE Pri
!#4 N8153 P2914 LD 25 -1 FP BE Pri
!#4 N8154 P2913 ST 5 0x200001e Int LE Pri
!#4 N8155 P2914 LD 25 -1 FP BE Pri
!#4 N8156 P2915 DWLD 7 -1 Int BE Pri
!#4 N8157 P2916 LD 18 -1 Int BE Pri
!#4 N8158 P2915 DWLD 7 -1 Int BE Pri
!#4 N8159 P2916 LD 18 -1 Int BE Pri
!#4 N8164 P2919 LD 8 -1 Int BE Pri
!#4 N8165 P2920 DWLD 3 -1 Int LE Pri
!#4 N8166 P2919 LD 8 -1 Int BE Pri
!#4 N8167 P2920 DWLD 3 -1 Int LE Pri
!#4 N8168 P2921 DWLD 22 -1 Int BE Pri
!#4 N8169 P2922 LD 9 -1 Int BE Pri
!#4 N8170 P2921 DWLD 22 -1 Int BE Pri
!#4 N8171 P2922 LD 9 -1 Int BE Pri
!#4 N8172 P2923 BLD 28 -1 FP BE Pri
!#4 N8173 P2923 BLD 29 -1 FP BE Pri
!#A N8172 N8173
!#4 N8174 P2923 BLD 30 -1 FP BE Pri
!#4 N8175 P2923 BLD 31 -1 FP BE Pri
!#4 N8176 P2923 BLD 28 -1 FP BE Pri
!#4 N8177 P2923 BLD 29 -1 FP BE Pri
!#A N8176 N8177
!#4 N8178 P2923 BLD 30 -1 FP BE Pri
!#4 N8179 P2923 BLD 31 -1 FP BE Pri
!#4 N8181 P2925 DWLD 27 -1 Int BE Pri
!#4 N8182 P2926 LD 20 -1 Int BE Pri
!#4 N8183 P2927 BLD 4 -1 FP BE Pri
!#4 N8184 P2927 BLD 5 -1 FP BE Pri
!#A N8183 N8184
!#4 N8185 P2927 BLD 6 -1 FP BE Pri
!#4 N8186 P2927 BLD 7 -1 FP BE Pri
!#4 N8187 P2927 BLD 4 -1 FP BE Pri
!#4 N8188 P2927 BLD 5 -1 FP BE Pri
!#A N8187 N8188
!#4 N8189 P2927 BLD 6 -1 FP BE Pri
!#4 N8190 P2927 BLD 7 -1 FP BE Pri
!#4 N8191 P2928 DWLD 31 -1 Int BE Pri
!#4 N8192 P2929 LD 19 -1 Int BE Pri
!#4 N8193 P2930 LD 1 -1 Int BE Pri
!#4 N8194 P2931 DWLD 2 -1 Int BE Pri
!#4 N8195 P2930 LD 1 -1 Int BE Pri
!#4 N8196 P2931 DWLD 2 -1 Int BE Pri
!#4 N8198 P2933 LD 6 -1 Int BE Pri
!#4 N8199 P2934 LD 25 -1 Int BE Pri
!#4 N8201 P2933 LD 6 -1 Int BE Pri
!#4 N8202 P2934 LD 25 -1 Int BE Pri
!#4 N8203 P2935 BLD 4 -1 FP BE Pri
!#4 N8204 P2935 BLD 5 -1 FP BE Pri
!#A N8203 N8204
!#4 N8205 P2935 BLD 6 -1 FP BE Pri
!#4 N8206 P2935 BLD 7 -1 FP BE Pri
!#4 N8207 P2936 LD 21 -1 Int BE Pri
!#4 N8208 P2937 LD 13 -1 Int BE Pri
!#4 N8209 P2936 LD 21 -1 Int BE Pri
!#4 N8210 P2937 LD 13 -1 Int BE Pri
!#4 N8211 P2938 DWLD 24 -1 Int BE Pri
!#4 N8212 P2938 DWLD 25 -1 Int BE Pri
!#A N8211 N8212
!#4 N8213 P2938 DWLD 24 -1 Int BE Pri
!#4 N8214 P2938 DWLD 25 -1 Int BE Pri
!#A N8213 N8214
!#4 N8215 P2939 LD 16 -1 Int BE Pri
!#4 N8216 P2940 BLD 24 -1 FP BE Pri
!#4 N8217 P2940 BLD 25 -1 FP BE Pri
!#A N8216 N8217
!#4 N8218 P2940 BLD 26 -1 FP BE Pri
!#4 N8219 P2940 BLD 27 -1 FP BE Pri
!#4 N8220 P2941 LD 26 -1 Int BE Pri
!#4 N8221 P2939 LD 16 -1 Int BE Pri
!#4 N8222 P2940 BLD 24 -1 FP BE Pri
!#4 N8223 P2940 BLD 25 -1 FP BE Pri
!#A N8222 N8223
!#4 N8224 P2940 BLD 26 -1 FP BE Pri
!#4 N8225 P2940 BLD 27 -1 FP BE Pri
!#4 N8226 P2941 LD 26 -1 Int BE Pri
!#4 N8227 P2942 DWLD 27 -1 Int BE Pri
!#4 N8228 P2943 DWLD 28 -1 Int BE Pri
!#4 N8229 P2943 DWLD 29 -1 Int BE Pri
!#A N8228 N8229
!#4 N8230 P2944 LD 4 -1 Int BE Pri
!#4 N8231 P2942 DWLD 27 -1 Int BE Pri
!#4 N8232 P2943 DWLD 28 -1 Int BE Pri
!#4 N8233 P2943 DWLD 29 -1 Int BE Pri
!#A N8232 N8233
!#4 N8234 P2944 LD 4 -1 Int BE Pri
!#4 N8235 P2945 LD 10 -1 Int LE Pri
!#4 N8236 P2946 LD 14 -1 Int BE Pri
!#4 N8237 P2945 LD 10 -1 Int LE Pri
!#4 N8238 P2946 LD 14 -1 Int BE Pri
!#4 N8239 P2947 LD 29 -1 Int BE Pri
!#4 N8240 P2948 LD 24 -1 Int BE Pri
!#4 N8241 P2949 DWLD 12 -1 Int BE Pri
!#4 N8242 P2949 DWLD 13 -1 Int BE Pri
!#A N8241 N8242
!#4 N8243 P2949 DWLD 12 -1 Int BE Pri
!#4 N8244 P2949 DWLD 13 -1 Int BE Pri
!#A N8243 N8244
!#4 N8245 P2950 DWLD 28 -1 Int BE Pri
!#4 N8246 P2950 DWLD 29 -1 Int BE Pri
!#A N8245 N8246
!#4 N8247 P2951 LD 7 -1 Int BE Pri
!#4 N8248 P2952 LD 7 -1 Int BE Pri
!#4 N8249 P2950 DWLD 28 -1 Int BE Pri
!#4 N8250 P2950 DWLD 29 -1 Int BE Pri
!#A N8249 N8250
!#4 N8251 P2951 LD 7 -1 Int BE Pri
!#4 N8252 P2952 LD 7 -1 Int BE Pri
!#4 N8253 P2953 DWLD 22 -1 Int BE Pri
!#4 N8254 P2954 LD 0 -1 Int BE Pri
!#4 N8255 P2955 LD 16 -1 Int BE Pri
!#4 N8256 P2956 LD 12 -1 Int BE Pri
!#4 N8257 P2955 LD 16 -1 Int BE Pri
!#4 N8258 P2956 LD 12 -1 Int BE Pri
!#4 N8260 P2958 LD 22 -1 Int BE Pri
!#4 N8261 P2959 LD 10 -1 Int BE Pri
!#4 N8262 P2960 BLD 28 -1 FP BE Pri
!#4 N8263 P2960 BLD 29 -1 FP BE Pri
!#A N8262 N8263
!#4 N8264 P2960 BLD 30 -1 FP BE Pri
!#4 N8265 P2960 BLD 31 -1 FP BE Pri
!#4 N8266 P2960 BLD 28 -1 FP BE Pri
!#4 N8267 P2960 BLD 29 -1 FP BE Pri
!#A N8266 N8267
!#4 N8268 P2960 BLD 30 -1 FP BE Pri
!#4 N8269 P2960 BLD 31 -1 FP BE Pri
!#4 N8270 P2961 BLD 4 -1 FP BE Pri
!#4 N8271 P2961 BLD 5 -1 FP BE Pri
!#A N8270 N8271
!#4 N8272 P2961 BLD 6 -1 FP BE Pri
!#4 N8273 P2961 BLD 7 -1 FP BE Pri
!#4 N8274 P2962 DWLD 10 -1 Int BE Pri
!#4 N8275 P2963 LD 30 -1 Int BE Pri
!#4 N8276 P2964 LD 21 -1 FP BE Pri
!#4 N8277 P2965 BLD 8 -1 FP BE Pri
!#4 N8278 P2965 BLD 9 -1 FP BE Pri
!#A N8277 N8278
!#4 N8279 P2965 BLD 10 -1 FP BE Pri
!#4 N8280 P2965 BLD 11 -1 FP BE Pri
!#4 N8281 P2966 LD 14 -1 Int BE Pri
!#4 N8282 P2967 LD 27 -1 Int BE Pri
!#4 N8283 P2965 BLD 8 -1 FP BE Pri
!#4 N8284 P2965 BLD 9 -1 FP BE Pri
!#A N8283 N8284
!#4 N8285 P2965 BLD 10 -1 FP BE Pri
!#4 N8286 P2965 BLD 11 -1 FP BE Pri
!#4 N8287 P2966 LD 14 -1 Int BE Pri
!#4 N8288 P2967 LD 27 -1 Int BE Pri
!#4 N8289 P2968 DWLD 10 -1 Int BE Pri
!#4 N8290 P2969 LD 13 -1 Int LE Pri
!#4 N8291 P2968 DWLD 10 -1 Int BE Pri
!#4 N8292 P2969 LD 13 -1 Int LE Pri
!#4 N8293 P2970 DWLD 8 -1 Int BE Pri
!#4 N8294 P2970 DWLD 9 -1 Int BE Pri
!#A N8293 N8294
!#4 N8295 P2970 DWLD 8 -1 Int BE Pri
!#4 N8296 P2970 DWLD 9 -1 Int BE Pri
!#A N8295 N8296
!#4 N8297 P2971 BLD 24 -1 FP BE Pri
!#4 N8298 P2971 BLD 25 -1 FP BE Pri
!#A N8297 N8298
!#4 N8299 P2971 BLD 26 -1 FP BE Pri
!#4 N8300 P2971 BLD 27 -1 FP BE Pri
!#4 N8301 P2972 DWLD 24 -1 Int BE Pri
!#4 N8302 P2972 DWLD 25 -1 Int BE Pri
!#A N8301 N8302
!#4 N8303 P2973 DWLD 19 -1 FP BE Pri
!#4 N8304 P2974 LD 8 -1 Int BE Pri
!#4 N8305 P2975 LD 6 -1 Int BE Pri
!#4 N8306 P2974 LD 8 -1 Int BE Pri
!#4 N8307 P2975 LD 6 -1 Int BE Pri
!#4 N8308 P2976 BLD 16 -1 FP BE Pri
!#4 N8309 P2976 BLD 17 -1 FP BE Pri
!#A N8308 N8309
!#4 N8310 P2976 BLD 18 -1 FP BE Pri
!#4 N8311 P2976 BLD 19 -1 FP BE Pri
!#4 N8312 P2976 BLD 16 -1 FP BE Pri
!#4 N8313 P2976 BLD 17 -1 FP BE Pri
!#A N8312 N8313
!#4 N8314 P2976 BLD 18 -1 FP BE Pri
!#4 N8315 P2976 BLD 19 -1 FP BE Pri
!#4 N8316 P2977 BLD 8 -1 FP BE Pri
!#4 N8317 P2977 BLD 9 -1 FP BE Pri
!#A N8316 N8317
!#4 N8318 P2977 BLD 10 -1 FP BE Pri
!#4 N8319 P2977 BLD 11 -1 FP BE Pri
!#4 N8320 P2978 BLD 20 -1 FP BE Pri
!#4 N8321 P2978 BLD 21 -1 FP BE Pri
!#A N8320 N8321
!#4 N8322 P2978 BLD 22 -1 FP BE Pri
!#4 N8323 P2978 BLD 23 -1 FP BE Pri
!#4 N8324 P2977 BLD 8 -1 FP BE Pri
!#4 N8325 P2977 BLD 9 -1 FP BE Pri
!#A N8324 N8325
!#4 N8326 P2977 BLD 10 -1 FP BE Pri
!#4 N8327 P2977 BLD 11 -1 FP BE Pri
!#4 N8328 P2978 BLD 20 -1 FP BE Pri
!#4 N8329 P2978 BLD 21 -1 FP BE Pri
!#A N8328 N8329
!#4 N8330 P2978 BLD 22 -1 FP BE Pri
!#4 N8331 P2978 BLD 23 -1 FP BE Pri
!#4 N8332 P2979 DWLD 10 -1 Int BE Pri
!#4 N8333 P2980 LD 26 -1 Int BE Pri
!#4 N8334 P2979 DWLD 10 -1 Int BE Pri
!#4 N8335 P2980 LD 26 -1 Int BE Pri
!#4 N8336 P2981 BLD 24 -1 FP BE Pri
!#4 N8337 P2981 BLD 25 -1 FP BE Pri
!#A N8336 N8337
!#4 N8338 P2981 BLD 26 -1 FP BE Pri
!#4 N8339 P2981 BLD 27 -1 FP BE Pri
!#4 N8340 P2981 BLD 24 -1 FP BE Pri
!#4 N8341 P2981 BLD 25 -1 FP BE Pri
!#A N8340 N8341
!#4 N8342 P2981 BLD 26 -1 FP BE Pri
!#4 N8343 P2981 BLD 27 -1 FP BE Pri
!#4 N8344 P2982 BLD 0 -1 FP BE Pri
!#4 N8345 P2982 BLD 1 -1 FP BE Pri
!#A N8344 N8345
!#4 N8346 P2982 BLD 2 -1 FP BE Pri
!#4 N8347 P2982 BLD 3 -1 FP BE Pri
!#4 N8348 P2983 LD 2 -1 Int BE Pri
!#4 N8349 P2984 LD 30 -1 Int BE Pri
!#4 N8350 P2985 MEMBAR
!#4 N8351 P2985 MEMBAR
!#4 N8352 P2986 DWLD 12 -1 Int BE Pri
!#4 N8353 P2986 DWLD 13 -1 Int BE Pri
!#A N8352 N8353
!#4 N8354 P2987 BLD 0 -1 FP BE Pri
!#4 N8355 P2987 BLD 1 -1 FP BE Pri
!#A N8354 N8355
!#4 N8356 P2987 BLD 2 -1 FP BE Pri
!#4 N8357 P2987 BLD 3 -1 FP BE Pri
!#4 N8358 P2988 LD 1 -1 Int BE Pri
!#4 N8359 P2989 LD 7 -1 Int BE Pri
!#4 N8360 P2990 DWLD 8 -1 Int BE Pri
!#4 N8361 P2990 DWLD 9 -1 Int BE Pri
!#A N8360 N8361
!#4 N8362 P2991 DWLD 28 -1 Int BE Pri
!#4 N8363 P2991 DWLD 29 -1 Int BE Pri
!#A N8362 N8363
!#4 N8364 P2990 DWLD 8 -1 Int BE Pri
!#4 N8365 P2990 DWLD 9 -1 Int BE Pri
!#A N8364 N8365
!#4 N8366 P2991 DWLD 28 -1 Int BE Pri
!#4 N8367 P2991 DWLD 29 -1 Int BE Pri
!#A N8366 N8367
!#4 N8368 P2992 LD 19 -1 Int BE Pri
!#4 N8369 P2993 BLD 0 -1 FP BE Pri
!#4 N8370 P2993 BLD 1 -1 FP BE Pri
!#A N8369 N8370
!#4 N8371 P2993 BLD 2 -1 FP BE Pri
!#4 N8372 P2993 BLD 3 -1 FP BE Pri
!#4 N8373 P2994 LD 3 -1 Int BE Pri
!#4 N8374 P2995 DWLD 7 -1 Int BE Pri
!#4 N8375 P2996 LD 18 -1 Int BE Pri
!#4 N8376 P2997 DWLD 16 -1 FP BE Pri
!#4 N8377 P2997 DWLD 17 -1 FP BE Pri
!#A N8376 N8377
!#4 N8378 P2998 LD 2 -1 Int BE Pri
!#4 N8379 P2999 LD 18 -1 Int BE Pri
!#4 N8380 P2997 DWLD 16 -1 FP BE Pri
!#4 N8381 P2997 DWLD 17 -1 FP BE Pri
!#A N8380 N8381
!#4 N8382 P2998 LD 2 -1 Int BE Pri
!#4 N8383 P2999 LD 18 -1 Int BE Pri
!#4 N8384 P3000 DWLD 6 -1 Int BE Pri
!#4 N8385 P3001 BLD 12 -1 FP BE Pri
!#4 N8386 P3001 BLD 13 -1 FP BE Pri
!#A N8385 N8386
!#4 N8387 P3001 BLD 14 -1 FP BE Pri
!#4 N8388 P3001 BLD 15 -1 FP BE Pri
!#4 N8389 P3002 LD 5 -1 Int BE Pri
!#4 N8390 P3003 DWLD 2 -1 Int BE Pri
!#4 N8391 P3004 LD 9 -1 Int BE Pri
!#4 N8392 P3003 DWLD 2 -1 Int BE Pri
!#4 N8393 P3004 LD 9 -1 Int BE Pri
!#4 N8394 P3005 DWLD 0 -1 Int BE Pri
!#4 N8395 P3005 DWLD 1 -1 Int BE Pri
!#A N8394 N8395
!#4 N8396 P3006 DWLD 20 -1 Int BE Pri
!#4 N8397 P3006 DWLD 21 -1 Int BE Pri
!#A N8396 N8397
!#4 N8398 P3005 DWLD 0 -1 Int BE Pri
!#4 N8399 P3005 DWLD 1 -1 Int BE Pri
!#A N8398 N8399
!#4 N8400 P3006 DWLD 20 -1 Int BE Pri
!#4 N8401 P3006 DWLD 21 -1 Int BE Pri
!#A N8400 N8401
!#4 N8402 P3007 BLD 4 -1 FP BE Pri
!#4 N8403 P3007 BLD 5 -1 FP BE Pri
!#A N8402 N8403
!#4 N8404 P3007 BLD 6 -1 FP BE Pri
!#4 N8405 P3007 BLD 7 -1 FP BE Pri
!#4 N8408 P3009 LD 1 -1 Int BE Pri
!#4 N8410 P3011 LD 18 -1 Int BE Pri
!#4 N8411 P3009 LD 1 -1 Int BE Pri
!#4 N8413 P3011 LD 18 -1 Int BE Pri
!#4 N8414 P3012 BLD 24 -1 FP BE Pri
!#4 N8415 P3012 BLD 25 -1 FP BE Pri
!#A N8414 N8415
!#4 N8416 P3012 BLD 26 -1 FP BE Pri
!#4 N8417 P3012 BLD 27 -1 FP BE Pri
!#4 N8418 P3013 DWLD 28 -1 Int BE Pri
!#4 N8419 P3013 DWLD 29 -1 Int BE Pri
!#A N8418 N8419
!#4 N8420 P3014 LD 19 -1 Int BE Pri
!#4 N8421 P3015 LD 0 -1 Int BE Pri
!#4 N8422 P3016 LD 1 -1 Int BE Pri
!#4 N8423 P3017 LD 22 -1 Int BE Pri
!#4 N8424 P3016 LD 1 -1 Int BE Pri
!#4 N8425 P3017 LD 22 -1 Int BE Pri
!#4 N8426 P3018 DWLD 18 -1 Int LE Pri
!#4 N8427 P3019 LD 6 -1 Int BE Pri
!#4 N8428 P3018 DWLD 18 -1 Int LE Pri
!#4 N8429 P3019 LD 6 -1 Int BE Pri
!#4 N8430 P3020 DWLD 0 -1 FP BE Pri
!#4 N8431 P3020 DWLD 1 -1 FP BE Pri
!#A N8430 N8431
!#4 N8432 P3021 DWLD 12 -1 Int BE Pri
!#4 N8433 P3021 DWLD 13 -1 Int BE Pri
!#A N8432 N8433
!#4 N8434 P3020 DWLD 0 -1 FP BE Pri
!#4 N8435 P3020 DWLD 1 -1 FP BE Pri
!#A N8434 N8435
!#4 N8436 P3021 DWLD 12 -1 Int BE Pri
!#4 N8437 P3021 DWLD 13 -1 Int BE Pri
!#A N8436 N8437
!#4 N8438 P3022 DWLD 28 -1 Int BE Pri
!#4 N8439 P3022 DWLD 29 -1 Int BE Pri
!#A N8438 N8439
!#4 N8440 P3022 DWLD 28 -1 Int BE Pri
!#4 N8441 P3022 DWLD 29 -1 Int BE Pri
!#A N8440 N8441
!#4 N8443 P3024 LD 28 -1 Int BE Pri
!#4 N8444 P3025 LD 24 -1 Int BE Pri
!#4 N8446 P3024 LD 28 -1 Int BE Pri
!#4 N8447 P3025 LD 24 -1 Int BE Pri
!#4 N8448 P3026 DWLD 18 -1 Int BE Pri
!#4 N8449 P3027 LD 13 -1 FP BE Pri
!#4 N8450 P3028 LD 27 -1 Int BE Pri
!#4 N8451 P3026 DWLD 18 -1 Int BE Pri
!#4 N8452 P3027 LD 13 -1 FP BE Pri
!#4 N8453 P3028 LD 27 -1 Int BE Pri
!#4 N8454 P3029 BST 28 0x4180002d FP BE Pri
!#4 N8455 P3029 BST 29 0x4180002e FP BE Pri
!#A N8454 N8455
!#4 N8456 P3029 BST 30 0x4180002f FP BE Pri
!#4 N8457 P3029 BST 31 0x41800030 FP BE Pri
!#4 N8458 P3030 BLD 28 -1 FP BE Pri
!#4 N8459 P3030 BLD 29 -1 FP BE Pri
!#A N8458 N8459
!#4 N8460 P3030 BLD 30 -1 FP BE Pri
!#4 N8461 P3030 BLD 31 -1 FP BE Pri
!#4 N8462 P3029 BST 28 0x41800031 FP BE Pri
!#4 N8463 P3029 BST 29 0x41800032 FP BE Pri
!#A N8462 N8463
!#4 N8464 P3029 BST 30 0x41800033 FP BE Pri
!#4 N8465 P3029 BST 31 0x41800034 FP BE Pri
!#4 N8466 P3030 BLD 28 -1 FP BE Pri
!#4 N8467 P3030 BLD 29 -1 FP BE Pri
!#A N8466 N8467
!#4 N8468 P3030 BLD 30 -1 FP BE Pri
!#4 N8469 P3030 BLD 31 -1 FP BE Pri
!#4 N8470 P3031 DWLD 10 -1 Int BE Pri
!#4 N8471 P3032 LD 29 -1 Int BE Pri
!#4 N8472 P3033 LD 4 -1 Int BE Pri
!#4 N8473 P3034 DWLD 10 -1 Int BE Pri
!#4 N8474 P3033 LD 4 -1 Int BE Pri
!#4 N8475 P3034 DWLD 10 -1 Int BE Pri
!#4 N8476 P3035 LD 24 -1 Int BE Pri
!#4 N8477 P3036 LD 14 -1 Int BE Pri
!#4 N8478 P3035 LD 24 -1 Int BE Pri
!#4 N8479 P3036 LD 14 -1 Int BE Pri
!#4 N8480 P3037 BLD 12 -1 FP BE Pri
!#4 N8481 P3037 BLD 13 -1 FP BE Pri
!#A N8480 N8481
!#4 N8482 P3037 BLD 14 -1 FP BE Pri
!#4 N8483 P3037 BLD 15 -1 FP BE Pri
!#4 N8484 P3037 BLD 12 -1 FP BE Pri
!#4 N8485 P3037 BLD 13 -1 FP BE Pri
!#A N8484 N8485
!#4 N8486 P3037 BLD 14 -1 FP BE Pri
!#4 N8487 P3037 BLD 15 -1 FP BE Pri
!#4 N8488 P3038 LD 14 -1 Int BE Pri
!#4 N8489 P3039 LD 29 -1 Int BE Pri
!#4 N8490 P3038 LD 14 -1 Int BE Pri
!#4 N8491 P3039 LD 29 -1 Int BE Pri
!#4 N8492 P3040 DWLD 31 -1 Int BE Pri
!#4 N8493 P3041 DWLD 8 -1 Int BE Pri
!#4 N8494 P3041 DWLD 9 -1 Int BE Pri
!#A N8493 N8494
!#4 N8495 P3042 LD 2 -1 Int BE Pri
!#4 N8496 P3040 DWLD 31 -1 Int BE Pri
!#4 N8497 P3041 DWLD 8 -1 Int BE Pri
!#4 N8498 P3041 DWLD 9 -1 Int BE Pri
!#A N8497 N8498
!#4 N8499 P3042 LD 2 -1 Int BE Pri
!#4 N8500 P3043 LD 25 -1 FP BE Pri
!#4 N8501 P3043 LD 25 -1 FP BE Pri
!#4 N8502 P3044 DWLD 4 -1 Int BE Pri
!#4 N8503 P3044 DWLD 5 -1 Int BE Pri
!#A N8502 N8503
!#4 N8504 P3045 LD 7 -1 Int BE Pri
!#4 N8505 P3046 LD 22 -1 Int BE Pri
!#4 N8506 P3044 DWLD 4 -1 Int BE Pri
!#4 N8507 P3044 DWLD 5 -1 Int BE Pri
!#A N8506 N8507
!#4 N8508 P3045 LD 7 -1 Int BE Pri
!#4 N8509 P3046 LD 22 -1 Int BE Pri
!#4 N8510 P3047 LD 31 -1 Int BE Pri
!#4 N8512 P3049 LD 8 -1 Int BE Pri
!#4 N8513 P3047 LD 31 -1 Int BE Pri
!#4 N8515 P3049 LD 8 -1 Int BE Pri
!#4 N8516 P3050 DWLD 6 -1 Int BE Pri
!#4 N8517 P3051 LD 31 -1 Int BE Pri
!#4 N8518 P3050 DWLD 6 -1 Int BE Pri
!#4 N8519 P3051 LD 31 -1 Int BE Pri
!#4 N8520 P3052 LD 29 -1 Int BE Pri
!#4 N8521 P3053 LD 3 -1 Int LE Pri
!#4 N8522 P3054 DWST 16 0x200001f Int BE Pri
!#4 N8523 P3054 DWST 17 0x2000020 Int BE Pri
!#A N8522 N8523
!#4 N8524 P3055 LD 18 -1 FP BE Pri
!#4 N8525 P3056 BLD 4 -1 FP BE Pri
!#4 N8526 P3056 BLD 5 -1 FP BE Pri
!#A N8525 N8526
!#4 N8527 P3056 BLD 6 -1 FP BE Pri
!#4 N8528 P3056 BLD 7 -1 FP BE Pri
!#4 N8529 P3057 BST 20 0x41800035 FP BE Pri
!#4 N8530 P3057 BST 21 0x41800036 FP BE Pri
!#A N8529 N8530
!#4 N8531 P3057 BST 22 0x41800037 FP BE Pri
!#4 N8532 P3057 BST 23 0x41800038 FP BE Pri
!#4 N8533 P3058 BLD 4 -1 FP BE Pri
!#4 N8534 P3058 BLD 5 -1 FP BE Pri
!#A N8533 N8534
!#4 N8535 P3058 BLD 6 -1 FP BE Pri
!#4 N8536 P3058 BLD 7 -1 FP BE Pri
!#4 N8537 P3059 DWLD 16 -1 Int BE Pri
!#4 N8538 P3059 DWLD 17 -1 Int BE Pri
!#A N8537 N8538
!#4 N8539 P3058 BLD 4 -1 FP BE Pri
!#4 N8540 P3058 BLD 5 -1 FP BE Pri
!#A N8539 N8540
!#4 N8541 P3058 BLD 6 -1 FP BE Pri
!#4 N8542 P3058 BLD 7 -1 FP BE Pri
!#4 N8543 P3059 DWLD 16 -1 Int BE Pri
!#4 N8544 P3059 DWLD 17 -1 Int BE Pri
!#A N8543 N8544
!#4 N8545 P3060 BLD 24 -1 FP BE Pri
!#4 N8546 P3060 BLD 25 -1 FP BE Pri
!#A N8545 N8546
!#4 N8547 P3060 BLD 26 -1 FP BE Pri
!#4 N8548 P3060 BLD 27 -1 FP BE Pri
!#4 N8549 P3061 LD 25 -1 Int BE Pri
!#4 N8550 P3062 LD 5 -1 Int BE Pri
!#4 N8551 P3060 BLD 24 -1 FP BE Pri
!#4 N8552 P3060 BLD 25 -1 FP BE Pri
!#A N8551 N8552
!#4 N8553 P3060 BLD 26 -1 FP BE Pri
!#4 N8554 P3060 BLD 27 -1 FP BE Pri
!#4 N8555 P3061 LD 25 -1 Int BE Pri
!#4 N8556 P3062 LD 5 -1 Int BE Pri
!#4 N8557 P3063 MEMBAR
!#4 N8558 P3064 DWLD 3 -1 FP BE Pri
!#4 N8559 P3065 LD 26 -1 Int BE Pri
!#4 N8560 P3066 LD 31 -1 Int BE Pri
!#4 N8562 P3068 LD 27 -1 Int BE Pri
!#4 N8563 P3069 LD 24 -1 Int BE Pri
!#4 N8565 P3068 LD 27 -1 Int BE Pri
!#4 N8566 P3069 LD 24 -1 Int BE Pri
!#4 N8567 P3070 DWLD 8 -1 Int BE Pri
!#4 N8568 P3070 DWLD 9 -1 Int BE Pri
!#A N8567 N8568
!#4 N8570 P3072 DWLD 6 -1 Int BE Pri
!#4 N8571 P3073 LD 25 -1 Int BE Pri
!#4 N8572 P3072 DWLD 6 -1 Int BE Pri
!#4 N8573 P3073 LD 25 -1 Int BE Pri
!#4 N8574 P3074 DWLD 28 -1 Int BE Pri
!#4 N8575 P3074 DWLD 29 -1 Int BE Pri
!#A N8574 N8575
!#4 N8576 P3075 DWLD 8 -1 Int BE Pri
!#4 N8577 P3075 DWLD 9 -1 Int BE Pri
!#A N8576 N8577
!#4 N8579 P3077 LD 28 -1 Int BE Pri
!#4 N8580 P3078 LD 13 -1 Int BE Pri
!#4 N8582 P3077 LD 28 -1 Int BE Pri
!#4 N8583 P3078 LD 13 -1 Int BE Pri
!#4 N8584 P3079 DWLD 22 -1 Int BE Pri
!#4 N8585 P3080 LD 20 -1 Int BE Pri
!#4 N8586 P3081 LD 2 -1 Int BE Pri
!#4 N8587 P3082 LD 29 -1 Int BE Pri
!#4 N8588 P3083 DWLD 31 -1,0x0 Int LE Pri
!#4 N8589 P3083 CASX 31 -1,0x0 N8588 0x2000021 Int LE Pri
!#4 N8590 P3083 DWLD 31 -1,0x0 Int LE Pri
!#4 N8591 P3083 CASX 31 -1,0x0 N8590 0x2000022 Int LE Pri
!#4 N8592 P3084 DWLD 11 -1 Int BE Pri
!#4 N8593 P3085 BLD 20 -1 FP BE Pri
!#4 N8594 P3085 BLD 21 -1 FP BE Pri
!#A N8593 N8594
!#4 N8595 P3085 BLD 22 -1 FP BE Pri
!#4 N8596 P3085 BLD 23 -1 FP BE Pri
!#4 N8597 P3086 LD 24 -1 Int BE Pri
!#4 N8598 P3084 DWLD 11 -1 Int BE Pri
!#4 N8599 P3085 BLD 20 -1 FP BE Pri
!#4 N8600 P3085 BLD 21 -1 FP BE Pri
!#A N8599 N8600
!#4 N8601 P3085 BLD 22 -1 FP BE Pri
!#4 N8602 P3085 BLD 23 -1 FP BE Pri
!#4 N8603 P3086 LD 24 -1 Int BE Pri
!#4 N8605 P3088 LD 22 -1 Int BE Pri
!#4 N8606 P3089 LD 26 -1 Int BE Pri
!#4 N8608 P3088 LD 22 -1 Int BE Pri
!#4 N8609 P3089 LD 26 -1 Int BE Pri
!#4 N8610 P3090 DWLD 19 -1 Int BE Pri
!#4 N8611 P3091 DWLD 12 -1 Int BE Pri
!#4 N8612 P3091 DWLD 13 -1 Int BE Pri
!#A N8611 N8612
!#4 N8613 P3092 LD 27 -1 Int BE Pri
!#4 N8614 P3090 DWLD 19 -1 Int BE Pri
!#4 N8615 P3091 DWLD 12 -1 Int BE Pri
!#4 N8616 P3091 DWLD 13 -1 Int BE Pri
!#A N8615 N8616
!#4 N8617 P3092 LD 27 -1 Int BE Pri
!#4 N8618 P3093 BLD 0 -1 FP BE Pri
!#4 N8619 P3093 BLD 1 -1 FP BE Pri
!#A N8618 N8619
!#4 N8620 P3093 BLD 2 -1 FP BE Pri
!#4 N8621 P3093 BLD 3 -1 FP BE Pri
!#4 N8622 P3093 BLD 0 -1 FP BE Pri
!#4 N8623 P3093 BLD 1 -1 FP BE Pri
!#A N8622 N8623
!#4 N8624 P3093 BLD 2 -1 FP BE Pri
!#4 N8625 P3093 BLD 3 -1 FP BE Pri
!#4 N8626 P3094 LD 28 -1 Int BE Pri
!#4 N8627 P3095 LD 28 -1 Int BE Pri
!#4 N8628 P3096 BLD 24 -1 FP BE Pri
!#4 N8629 P3096 BLD 25 -1 FP BE Pri
!#A N8628 N8629
!#4 N8630 P3096 BLD 26 -1 FP BE Pri
!#4 N8631 P3096 BLD 27 -1 FP BE Pri
!#4 N8632 P3097 BLD 28 -1 FP BE Pri
!#4 N8633 P3097 BLD 29 -1 FP BE Pri
!#A N8632 N8633
!#4 N8634 P3097 BLD 30 -1 FP BE Pri
!#4 N8635 P3097 BLD 31 -1 FP BE Pri
!#4 N8636 P3098 LD 30 -1 Int BE Pri
!#4 N8637 P3099 LD 28 -1 Int BE Pri
!#4 N8638 P3098 LD 30 -1 Int BE Pri
!#4 N8639 P3099 LD 28 -1 Int BE Pri
!#4 N8640 P3100 BLD 12 -1 FP BE Pri
!#4 N8641 P3100 BLD 13 -1 FP BE Pri
!#A N8640 N8641
!#4 N8642 P3100 BLD 14 -1 FP BE Pri
!#4 N8643 P3100 BLD 15 -1 FP BE Pri
!#4 N8644 P3100 BLD 12 -1 FP BE Pri
!#4 N8645 P3100 BLD 13 -1 FP BE Pri
!#A N8644 N8645
!#4 N8646 P3100 BLD 14 -1 FP BE Pri
!#4 N8647 P3100 BLD 15 -1 FP BE Pri
!#4 N8648 P3101 BLD 8 -1 FP BE Pri
!#4 N8649 P3101 BLD 9 -1 FP BE Pri
!#A N8648 N8649
!#4 N8650 P3101 BLD 10 -1 FP BE Pri
!#4 N8651 P3101 BLD 11 -1 FP BE Pri
!#4 N8652 P3102 LD 28 -1 Int BE Pri
!#4 N8653 P3103 LD 31 -1 Int BE Pri
!#4 N8654 P3102 LD 28 -1 Int BE Pri
!#4 N8655 P3103 LD 31 -1 Int BE Pri
!#4 N8656 P3104 DWLD 31 -1 Int BE Pri
!#4 N8657 P3105 DWLD 14 -1 Int BE Pri
!#4 N8658 P3104 DWLD 31 -1 Int BE Pri
!#4 N8659 P3105 DWLD 14 -1 Int BE Pri
!#4 N8660 P3106 BLD 16 -1 FP BE Pri
!#4 N8661 P3106 BLD 17 -1 FP BE Pri
!#A N8660 N8661
!#4 N8662 P3106 BLD 18 -1 FP BE Pri
!#4 N8663 P3106 BLD 19 -1 FP BE Pri
!#4 N8666 P3108 DWLD 15 -1 Int BE Pri
!#4 N8667 P3109 DWLD 16 -1 Int BE Pri
!#4 N8668 P3109 DWLD 17 -1 Int BE Pri
!#A N8667 N8668
!#4 N8669 P3110 LD 4 -1 Int BE Pri
!#4 N8670 P3111 LD 17 -1 Int BE Pri
!#4 N8671 P3111 CAS 17 -1 N8670 0x2000023 Int BE Pri
!#4 N8672 P3112 LD 25 -1 FP BE Pri
!#4 N8673 P3113 BLD 0 -1 FP BE Pri
!#4 N8674 P3113 BLD 1 -1 FP BE Pri
!#A N8673 N8674
!#4 N8675 P3113 BLD 2 -1 FP BE Pri
!#4 N8676 P3113 BLD 3 -1 FP BE Pri
!#4 N8677 P3114 BLD 12 -1 FP BE Pri
!#4 N8678 P3114 BLD 13 -1 FP BE Pri
!#A N8677 N8678
!#4 N8679 P3114 BLD 14 -1 FP BE Pri
!#4 N8680 P3114 BLD 15 -1 FP BE Pri
!#4 N8681 P3115 DWLD 11 -1 Int BE Pri
!#4 N8682 P3116 LD 24 -1 Int BE Pri
!#4 N8683 P3114 BLD 12 -1 FP BE Pri
!#4 N8684 P3114 BLD 13 -1 FP BE Pri
!#A N8683 N8684
!#4 N8685 P3114 BLD 14 -1 FP BE Pri
!#4 N8686 P3114 BLD 15 -1 FP BE Pri
!#4 N8687 P3115 DWLD 11 -1 Int BE Pri
!#4 N8688 P3116 LD 24 -1 Int BE Pri
!#4 N8689 P3117 DWLD 4 -1 Int BE Pri
!#4 N8690 P3117 DWLD 5 -1 Int BE Pri
!#A N8689 N8690
!#4 N8691 P3117 DWLD 4 -1 Int BE Pri
!#4 N8692 P3117 DWLD 5 -1 Int BE Pri
!#A N8691 N8692
!#4 N8693 P3118 BLD 0 -1 FP BE Pri
!#4 N8694 P3118 BLD 1 -1 FP BE Pri
!#A N8693 N8694
!#4 N8695 P3118 BLD 2 -1 FP BE Pri
!#4 N8696 P3118 BLD 3 -1 FP BE Pri
!#4 N8697 P3119 BLD 16 -1 FP BE Pri
!#4 N8698 P3119 BLD 17 -1 FP BE Pri
!#A N8697 N8698
!#4 N8699 P3119 BLD 18 -1 FP BE Pri
!#4 N8700 P3119 BLD 19 -1 FP BE Pri
!#4 N8701 P3119 BLD 16 -1 FP BE Pri
!#4 N8702 P3119 BLD 17 -1 FP BE Pri
!#A N8701 N8702
!#4 N8703 P3119 BLD 18 -1 FP BE Pri
!#4 N8704 P3119 BLD 19 -1 FP BE Pri
!#4 N8706 P3121 LD 27 -1 Int BE Pri
!#4 N8708 P3123 LD 17 -1 Int BE Pri
!#4 N8709 P3121 LD 27 -1 Int BE Pri
!#4 N8711 P3123 LD 17 -1 Int BE Pri
!#4 N8712 P3124 LD 10 -1 Int BE Pri
!#4 N8713 P3125 LD 14 -1 Int BE Pri
!#4 N8714 P3124 LD 10 -1 Int BE Pri
!#4 N8715 P3125 LD 14 -1 Int BE Pri
!#4 N8716 P3126 DWLD 2 -1 Int BE Pri
!#4 N8717 P3127 LD 16 -1 Int BE Pri
!#4 N8718 P3128 BLD 8 -1 FP BE Pri
!#4 N8719 P3128 BLD 9 -1 FP BE Pri
!#A N8718 N8719
!#4 N8720 P3128 BLD 10 -1 FP BE Pri
!#4 N8721 P3128 BLD 11 -1 FP BE Pri
!#4 N8722 P3129 LD 4 -1 Int BE Pri
!#4 N8723 P3130 BST 16 0x41800039 FP BE Pri
!#4 N8724 P3130 BST 17 0x4180003a FP BE Pri
!#A N8723 N8724
!#4 N8725 P3130 BST 18 0x4180003b FP BE Pri
!#4 N8726 P3130 BST 19 0x4180003c FP BE Pri
!#4 N8727 P3131 LD 29 -1 Int BE Pri
!#4 N8728 P3129 LD 4 -1 Int BE Pri
!#4 N8729 P3130 BST 16 0x4180003d FP BE Pri
!#4 N8730 P3130 BST 17 0x4180003e FP BE Pri
!#A N8729 N8730
!#4 N8731 P3130 BST 18 0x4180003f FP BE Pri
!#4 N8732 P3130 BST 19 0x41800040 FP BE Pri
!#4 N8733 P3131 LD 29 -1 Int BE Pri
!#4 N8735 P3133 BLD 8 -1 FP BE Pri
!#4 N8736 P3133 BLD 9 -1 FP BE Pri
!#A N8735 N8736
!#4 N8737 P3133 BLD 10 -1 FP BE Pri
!#4 N8738 P3133 BLD 11 -1 FP BE Pri
!#4 N8739 P3134 DWLD 0 -1 Int BE Pri
!#4 N8740 P3134 DWLD 1 -1 Int BE Pri
!#A N8739 N8740
!#4 N8741 P3135 LD 18 -1 Int LE Pri
!#4 N8742 P3136 LD 21 -1 Int BE Pri
!#4 N8743 P3134 DWLD 0 -1 Int BE Pri
!#4 N8744 P3134 DWLD 1 -1 Int BE Pri
!#A N8743 N8744
!#4 N8745 P3135 LD 18 -1 Int LE Pri
!#4 N8746 P3136 LD 21 -1 Int BE Pri
!#4 N8747 P3137 BLD 4 -1 FP BE Pri
!#4 N8748 P3137 BLD 5 -1 FP BE Pri
!#A N8747 N8748
!#4 N8749 P3137 BLD 6 -1 FP BE Pri
!#4 N8750 P3137 BLD 7 -1 FP BE Pri
!#4 N8751 P3138 DWLD 19 -1 Int BE Pri
!#4 N8752 P3139 LD 23 -1 Int BE Pri
!#4 N8753 P3140 BLD 8 -1 FP BE Pri
!#4 N8754 P3140 BLD 9 -1 FP BE Pri
!#A N8753 N8754
!#4 N8755 P3140 BLD 10 -1 FP BE Pri
!#4 N8756 P3140 BLD 11 -1 FP BE Pri
!#4 N8757 P3141 BLD 20 -1 FP BE Pri
!#4 N8758 P3141 BLD 21 -1 FP BE Pri
!#A N8757 N8758
!#4 N8759 P3141 BLD 22 -1 FP BE Pri
!#4 N8760 P3141 BLD 23 -1 FP BE Pri
!#4 N8761 P3142 DWLD 12 -1 Int BE Pri
!#4 N8762 P3142 DWLD 13 -1 Int BE Pri
!#A N8761 N8762
!#4 N8763 P3143 DWLD 27 -1 Int BE Pri
!#4 N8764 P3144 LD 11 -1 Int BE Pri
!#4 N8765 P3142 DWLD 12 -1 Int BE Pri
!#4 N8766 P3142 DWLD 13 -1 Int BE Pri
!#A N8765 N8766
!#4 N8767 P3143 DWLD 27 -1 Int BE Pri
!#4 N8768 P3144 LD 11 -1 Int BE Pri
!#4 N8769 P3145 BLD 16 -1 FP BE Pri
!#4 N8770 P3145 BLD 17 -1 FP BE Pri
!#A N8769 N8770
!#4 N8771 P3145 BLD 18 -1 FP BE Pri
!#4 N8772 P3145 BLD 19 -1 FP BE Pri
!#4 N8773 P3146 BLD 28 -1 FP BE Pri
!#4 N8774 P3146 BLD 29 -1 FP BE Pri
!#A N8773 N8774
!#4 N8775 P3146 BLD 30 -1 FP BE Pri
!#4 N8776 P3146 BLD 31 -1 FP BE Pri
!#4 N8777 P3146 BLD 28 -1 FP BE Pri
!#4 N8778 P3146 BLD 29 -1 FP BE Pri
!#A N8777 N8778
!#4 N8779 P3146 BLD 30 -1 FP BE Pri
!#4 N8780 P3146 BLD 31 -1 FP BE Pri
!#4 N8781 P3147 LD 10 -1 Int BE Pri
!#4 N8782 P3148 LD 25 -1 Int BE Pri
!#4 N8783 P3147 LD 10 -1 Int BE Pri
!#4 N8784 P3148 LD 25 -1 Int BE Pri
!#4 N8785 P3149 DWLD 23 -1 Int BE Pri
!#4 N8786 P3150 LD 18 -1 Int BE Pri
!#4 N8787 P3149 DWLD 23 -1 Int BE Pri
!#4 N8788 P3150 LD 18 -1 Int BE Pri
!#4 N8789 P3151 DWLD 18 -1 Int BE Pri
!#4 N8790 P3152 LD 19 -1 Int BE Pri
!#4 N8791 P3153 BLD 24 -1 FP BE Pri
!#4 N8792 P3153 BLD 25 -1 FP BE Pri
!#A N8791 N8792
!#4 N8793 P3153 BLD 26 -1 FP BE Pri
!#4 N8794 P3153 BLD 27 -1 FP BE Pri
!#4 N8795 P3153 BLD 24 -1 FP BE Pri
!#4 N8796 P3153 BLD 25 -1 FP BE Pri
!#A N8795 N8796
!#4 N8797 P3153 BLD 26 -1 FP BE Pri
!#4 N8798 P3153 BLD 27 -1 FP BE Pri
!#4 N8799 P3154 LD 18 -1 Int BE Pri
!#4 N8800 P3155 LD 0 -1 Int BE Pri
!#4 N8801 P3154 LD 18 -1 Int BE Pri
!#4 N8802 P3155 LD 0 -1 Int BE Pri
!#4 N8803 P3156 BLD 20 -1 FP BE Pri
!#4 N8804 P3156 BLD 21 -1 FP BE Pri
!#A N8803 N8804
!#4 N8805 P3156 BLD 22 -1 FP BE Pri
!#4 N8806 P3156 BLD 23 -1 FP BE Pri
!#4 N8807 P3157 DWLD 7 -1 Int BE Pri
!#4 N8808 P3158 LD 23 -1 Int BE Pri
!#4 N8809 P3159 MEMBAR
!#4 N8810 P3160 LD 25 -1 Int BE Pri
!#4 N8811 P3161 LD 2 -1 Int BE Pri
!#4 N8812 P3162 BLD 28 -1 FP BE Pri
!#4 N8813 P3162 BLD 29 -1 FP BE Pri
!#A N8812 N8813
!#4 N8814 P3162 BLD 30 -1 FP BE Pri
!#4 N8815 P3162 BLD 31 -1 FP BE Pri
!#4 N8816 P3163 BLD 28 -1 FP BE Pri
!#4 N8817 P3163 BLD 29 -1 FP BE Pri
!#A N8816 N8817
!#4 N8818 P3163 BLD 30 -1 FP BE Pri
!#4 N8819 P3163 BLD 31 -1 FP BE Pri
!#4 N8820 P3164 DWST 28 0x2000024 Int BE Pri
!#4 N8821 P3164 DWST 29 0x2000025 Int BE Pri
!#A N8820 N8821
!#4 N8822 P3165 LD 25 -1 Int LE Pri
!#4 N8823 P3166 LD 13 -1 Int BE Pri
!#4 N8824 P3167 BLD 24 -1 FP BE Pri
!#4 N8825 P3167 BLD 25 -1 FP BE Pri
!#A N8824 N8825
!#4 N8826 P3167 BLD 26 -1 FP BE Pri
!#4 N8827 P3167 BLD 27 -1 FP BE Pri
!#4 N8828 P3168 LD 30 -1 Int BE Pri
!#4 N8829 P3169 LD 30 -1 Int BE Pri
!#4 N8830 P3168 LD 30 -1 Int BE Pri
!#4 N8831 P3169 LD 30 -1 Int BE Pri
!#4 N8832 P3170 LD 28 -1 Int BE Pri
!#4 N8833 P3171 LD 4 -1 Int BE Pri
!#4 N8834 P3170 LD 28 -1 Int BE Pri
!#4 N8835 P3171 LD 4 -1 Int BE Pri
!#4 N8836 P3172 LD 17 -1 Int BE Pri
!#4 N8837 P3173 LD 31 -1 Int BE Pri
!#4 N8838 P3172 LD 17 -1 Int BE Pri
!#4 N8839 P3173 LD 31 -1 Int BE Pri
!#4 N8840 P3174 MEMBAR
!#4 N8841 P3175 BLD 12 -1 FP BE Pri
!#4 N8842 P3175 BLD 13 -1 FP BE Pri
!#A N8841 N8842
!#4 N8843 P3175 BLD 14 -1 FP BE Pri
!#4 N8844 P3175 BLD 15 -1 FP BE Pri
!#4 N8845 P3174 MEMBAR
!#4 N8846 P3175 BLD 12 -1 FP BE Pri
!#4 N8847 P3175 BLD 13 -1 FP BE Pri
!#A N8846 N8847
!#4 N8848 P3175 BLD 14 -1 FP BE Pri
!#4 N8849 P3175 BLD 15 -1 FP BE Pri
!#4 N8850 P3176 DWLD 10 -1 Int BE Pri
!#4 N8851 P3177 LD 2 -1 Int BE Pri
!#4 N8852 P3178 DWLD 16 -1 Int BE Pri
!#4 N8853 P3178 DWLD 17 -1 Int BE Pri
!#A N8852 N8853
!#4 N8854 P3179 DWLD 6 -1 Int BE Pri
!#4 N8855 P3180 LD 21 -1 Int BE Pri
!#4 N8857 P3182 LD 30 -1 FP BE Pri
!#4 N8858 P3183 DWLD 31 -1 Int BE Pri
!#4 N8859 P3184 DWLD 23 -1 Int BE Pri
!#4 N8860 P3185 LD 5 -1 Int LE Pri
!#4 N8861 P3186 LD 9 -1 Int BE Pri
!#4 N8862 P3187 LD 22 -1 Int LE Pri
!#4 N8863 P3188 DWLD 31 -1 Int BE Pri
!#4 N8864 P3189 DWLD 22 -1 Int BE Pri
!#4 N8865 P3190 LD 24 -1 Int BE Pri
!#4 N8866 P3191 LD 17 -1 Int BE Pri
!#4 N8867 P3192 DWLD 30 -1 Int BE Pri
!#4 N8868 P3191 LD 17 -1 Int BE Pri
!#4 N8869 P3192 DWLD 30 -1 Int BE Pri
!#4 N8870 P3193 DWLD 31 -1 Int LE Pri
!#4 N8871 P3194 LD 31 -1 Int BE Pri
!#4 N8872 P3195 DWLD 19 -1 Int BE Pri
!#4 N8873 P3196 LD 30 -1 Int BE Pri
!#4 N8874 P3195 DWLD 19 -1 Int BE Pri
!#4 N8875 P3196 LD 30 -1 Int BE Pri
!#4 N8876 P3197 DWLD 26 -1 Int BE Pri
!#4 N8877 P3198 BLD 12 -1 FP BE Pri
!#4 N8878 P3198 BLD 13 -1 FP BE Pri
!#A N8877 N8878
!#4 N8879 P3198 BLD 14 -1 FP BE Pri
!#4 N8880 P3198 BLD 15 -1 FP BE Pri
!#4 N8881 P3199 LD 10 -1 Int BE Pri
!#4 N8882 P3197 DWLD 26 -1 Int BE Pri
!#4 N8883 P3198 BLD 12 -1 FP BE Pri
!#4 N8884 P3198 BLD 13 -1 FP BE Pri
!#A N8883 N8884
!#4 N8885 P3198 BLD 14 -1 FP BE Pri
!#4 N8886 P3198 BLD 15 -1 FP BE Pri
!#4 N8887 P3199 LD 10 -1 Int BE Pri
!#4 N8888 P3200 ST 14 0x2000026 Int BE Pri
!#4 N8889 P3201 LD 28 -1 Int BE Pri
!#4 N8890 P3202 LD 6 -1 Int BE Pri
!#4 N8891 P3200 ST 14 0x2000027 Int BE Pri
!#4 N8892 P3201 LD 28 -1 Int BE Pri
!#4 N8893 P3202 LD 6 -1 Int BE Pri
!#4 N8894 P3203 BLD 4 -1 FP BE Pri
!#4 N8895 P3203 BLD 5 -1 FP BE Pri
!#A N8894 N8895
!#4 N8896 P3203 BLD 6 -1 FP BE Pri
!#4 N8897 P3203 BLD 7 -1 FP BE Pri
!#4 N8898 P3204 DWLD 26 -1 Int BE Pri
!#4 N8899 P3205 LD 11 -1 Int BE Pri
!#4 N8900 P3206 BLD 8 -1 FP BE Pri
!#4 N8901 P3206 BLD 9 -1 FP BE Pri
!#A N8900 N8901
!#4 N8902 P3206 BLD 10 -1 FP BE Pri
!#4 N8903 P3206 BLD 11 -1 FP BE Pri
!#4 N8904 P3207 LD 14 -1 Int BE Pri
!#4 N8905 P3208 LD 24 -1 Int BE Pri
!#4 N8906 P3209 LD 8 -1 Int BE Pri
!#4 N8907 P3210 LD 8 -1 Int BE Pri
!#4 N8908 P3211 DWLD 7 -1 FP BE Pri
!#4 N8909 P3212 DWLD 27 -1 FP BE Pri
!#4 N8910 P3213 BLD 20 -1 FP BE Pri
!#4 N8911 P3213 BLD 21 -1 FP BE Pri
!#A N8910 N8911
!#4 N8912 P3213 BLD 22 -1 FP BE Pri
!#4 N8913 P3213 BLD 23 -1 FP BE Pri
!#4 N8914 P3213 BLD 20 -1 FP BE Pri
!#4 N8915 P3213 BLD 21 -1 FP BE Pri
!#A N8914 N8915
!#4 N8916 P3213 BLD 22 -1 FP BE Pri
!#4 N8917 P3213 BLD 23 -1 FP BE Pri
!#4 N8918 P3214 BLD 28 -1 FP BE Pri
!#4 N8919 P3214 BLD 29 -1 FP BE Pri
!#A N8918 N8919
!#4 N8920 P3214 BLD 30 -1 FP BE Pri
!#4 N8921 P3214 BLD 31 -1 FP BE Pri
!#4 N8922 P3215 DWLD 7 -1 Int BE Pri
!#4 N8923 P3216 LD 1 -1 Int BE Pri
!#4 N8924 P3217 BLD 20 -1 FP BE Pri
!#4 N8925 P3217 BLD 21 -1 FP BE Pri
!#A N8924 N8925
!#4 N8926 P3217 BLD 22 -1 FP BE Pri
!#4 N8927 P3217 BLD 23 -1 FP BE Pri
!#4 N8928 P3218 DWLD 10 -1 Int BE Pri
!#4 N8929 P3219 LD 30 -1 Int BE Pri
!#4 N8930 P3217 BLD 20 -1 FP BE Pri
!#4 N8931 P3217 BLD 21 -1 FP BE Pri
!#A N8930 N8931
!#4 N8932 P3217 BLD 22 -1 FP BE Pri
!#4 N8933 P3217 BLD 23 -1 FP BE Pri
!#4 N8934 P3218 DWLD 10 -1 Int BE Pri
!#4 N8935 P3219 LD 30 -1 Int BE Pri
!#4 N8937 P3221 MEMBAR
!#4 N8938 P3222 DWLD 30 -1 FP BE Pri
!#4 N8939 P3222 DWLD 30 -1 FP BE Pri
!#4 N8941 P3224 LD 3 -1 Int BE Pri
!#4 N8942 P3225 LD 23 -1 Int LE Pri
!#4 N8944 P3224 LD 3 -1 Int BE Pri
!#4 N8945 P3225 LD 23 -1 Int LE Pri
!#4 N8946 P3226 LD 30 -1 FP BE Pri
!#4 N8947 P3227 ST 22 0x2000028 Int BE Pri
!#4 N8948 P3226 LD 30 -1 FP BE Pri
!#4 N8949 P3227 ST 22 0x2000029 Int BE Pri
!#4 N8950 P3228 DWLD 26 -1 FP BE Pri
!#4 N8951 P3229 BLD 4 -1 FP BE Pri
!#4 N8952 P3229 BLD 5 -1 FP BE Pri
!#A N8951 N8952
!#4 N8953 P3229 BLD 6 -1 FP BE Pri
!#4 N8954 P3229 BLD 7 -1 FP BE Pri
!#4 N8955 P3230 BLD 12 -1 FP BE Pri
!#4 N8956 P3230 BLD 13 -1 FP BE Pri
!#A N8955 N8956
!#4 N8957 P3230 BLD 14 -1 FP BE Pri
!#4 N8958 P3230 BLD 15 -1 FP BE Pri
!#4 N8959 P3231 BLD 16 -1 FP BE Pri
!#4 N8960 P3231 BLD 17 -1 FP BE Pri
!#A N8959 N8960
!#4 N8961 P3231 BLD 18 -1 FP BE Pri
!#4 N8962 P3231 BLD 19 -1 FP BE Pri
!#4 N8963 P3232 DWLD 28 -1 Int BE Pri
!#4 N8964 P3232 DWLD 29 -1 Int BE Pri
!#A N8963 N8964
!#4 N8965 P3231 BLD 16 -1 FP BE Pri
!#4 N8966 P3231 BLD 17 -1 FP BE Pri
!#A N8965 N8966
!#4 N8967 P3231 BLD 18 -1 FP BE Pri
!#4 N8968 P3231 BLD 19 -1 FP BE Pri
!#4 N8969 P3232 DWLD 28 -1 Int BE Pri
!#4 N8970 P3232 DWLD 29 -1 Int BE Pri
!#A N8969 N8970
!#4 N8971 P3233 DWLD 22 -1 Int BE Pri
!#4 N8972 P3234 DWLD 26 -1 Int BE Pri
!#4 N8973 P3235 LD 22 -1 Int BE Pri
!#4 N8974 P3236 BLD 28 -1 FP BE Pri
!#4 N8975 P3236 BLD 29 -1 FP BE Pri
!#A N8974 N8975
!#4 N8976 P3236 BLD 30 -1 FP BE Pri
!#4 N8977 P3236 BLD 31 -1 FP BE Pri
!#4 N8978 P3237 LD 11 -1 Int BE Pri
!#4 N8979 P3238 SWAP 4 0xffffffff 0x200002a Int BE Pri
!#4 N8980 P3239 LD 5 -1 Int BE Pri
!#4 N8981 P3240 DWLD 18 -1 Int BE Pri
!#4 N8982 P3241 LD 0 -1 Int LE Pri
!#4 N8983 P3240 DWLD 18 -1 Int BE Pri
!#4 N8984 P3241 LD 0 -1 Int LE Pri
!#4 N8985 P3242 DWLD 20 -1 Int BE Pri
!#4 N8986 P3242 DWLD 21 -1 Int BE Pri
!#A N8985 N8986
!#4 N8987 P3242 DWLD 20 -1 Int BE Pri
!#4 N8988 P3242 DWLD 21 -1 Int BE Pri
!#A N8987 N8988
!#4 N8991 P3244 LD 24 -1 FP BE Pri
!#4 N8992 P3245 BLD 20 -1 FP BE Pri
!#4 N8993 P3245 BLD 21 -1 FP BE Pri
!#A N8992 N8993
!#4 N8994 P3245 BLD 22 -1 FP BE Pri
!#4 N8995 P3245 BLD 23 -1 FP BE Pri
!#4 N8996 P3246 BLD 28 -1 FP BE Pri
!#4 N8997 P3246 BLD 29 -1 FP BE Pri
!#A N8996 N8997
!#4 N8998 P3246 BLD 30 -1 FP BE Pri
!#4 N8999 P3246 BLD 31 -1 FP BE Pri
!#4 N9000 P3247 LD 30 -1 Int BE Pri
!#4 N9001 P3248 LD 0 -1 Int BE Pri
!#4 N9002 P3246 BLD 28 -1 FP BE Pri
!#4 N9003 P3246 BLD 29 -1 FP BE Pri
!#A N9002 N9003
!#4 N9004 P3246 BLD 30 -1 FP BE Pri
!#4 N9005 P3246 BLD 31 -1 FP BE Pri
!#4 N9006 P3247 LD 30 -1 Int BE Pri
!#4 N9007 P3248 LD 0 -1 Int BE Pri
!#4 N9008 P3249 LD 15 -1 FP BE Pri
!#4 N9009 P3249 LD 15 -1 FP BE Pri
!#4 N9010 P3250 BST 24 0x41800041 FP BE Pri
!#4 N9011 P3250 BST 25 0x41800042 FP BE Pri
!#A N9010 N9011
!#4 N9012 P3250 BST 26 0x41800043 FP BE Pri
!#4 N9013 P3250 BST 27 0x41800044 FP BE Pri
!#4 N9014 P3251 DWLD 12 -1 Int BE Pri
!#4 N9015 P3251 DWLD 13 -1 Int BE Pri
!#A N9014 N9015
!#4 N9016 P3250 BST 24 0x41800045 FP BE Pri
!#4 N9017 P3250 BST 25 0x41800046 FP BE Pri
!#A N9016 N9017
!#4 N9018 P3250 BST 26 0x41800047 FP BE Pri
!#4 N9019 P3250 BST 27 0x41800048 FP BE Pri
!#4 N9020 P3251 DWLD 12 -1 Int BE Pri
!#4 N9021 P3251 DWLD 13 -1 Int BE Pri
!#A N9020 N9021
!#4 N9022 P3252 LD 21 -1 Int BE Pri
!#4 N9023 P3253 BLD 12 -1 FP BE Pri
!#4 N9024 P3253 BLD 13 -1 FP BE Pri
!#A N9023 N9024
!#4 N9025 P3253 BLD 14 -1 FP BE Pri
!#4 N9026 P3253 BLD 15 -1 FP BE Pri
!#4 N9027 P3254 LD 3 -1 Int BE Pri
!#4 N9028 P3255 DWLD 15 -1 Int BE Pri
!#4 N9029 P3256 LD 10 -1 FP BE Pri
!#4 N9030 P3257 LD 7 -1 Int BE Pri
!#4 N9031 P3258 BLD 12 -1 FP BE Pri
!#4 N9032 P3258 BLD 13 -1 FP BE Pri
!#A N9031 N9032
!#4 N9033 P3258 BLD 14 -1 FP BE Pri
!#4 N9034 P3258 BLD 15 -1 FP BE Pri
!#4 N9035 P3259 BLD 16 -1 FP BE Pri
!#4 N9036 P3259 BLD 17 -1 FP BE Pri
!#A N9035 N9036
!#4 N9037 P3259 BLD 18 -1 FP BE Pri
!#4 N9038 P3259 BLD 19 -1 FP BE Pri
!#4 N9039 P3260 DWLD 12 -1 Int BE Pri
!#4 N9040 P3260 DWLD 13 -1 Int BE Pri
!#A N9039 N9040
!#4 N9041 P3261 BLD 28 -1 FP BE Pri
!#4 N9042 P3261 BLD 29 -1 FP BE Pri
!#A N9041 N9042
!#4 N9043 P3261 BLD 30 -1 FP BE Pri
!#4 N9044 P3261 BLD 31 -1 FP BE Pri
!#4 N9046 P3261 BLD 28 -1 FP BE Pri
!#4 N9047 P3261 BLD 29 -1 FP BE Pri
!#A N9046 N9047
!#4 N9048 P3261 BLD 30 -1 FP BE Pri
!#4 N9049 P3261 BLD 31 -1 FP BE Pri
!#4 N9051 P3263 DWLD 18 -1 Int LE Pri
!#4 N9052 P3264 BLD 0 -1 FP BE Pri
!#4 N9053 P3264 BLD 1 -1 FP BE Pri
!#A N9052 N9053
!#4 N9054 P3264 BLD 2 -1 FP BE Pri
!#4 N9055 P3264 BLD 3 -1 FP BE Pri
!#4 N9056 P3265 LD 6 -1 Int BE Pri
!#4 N9057 P3263 DWLD 18 -1 Int LE Pri
!#4 N9058 P3264 BLD 0 -1 FP BE Pri
!#4 N9059 P3264 BLD 1 -1 FP BE Pri
!#A N9058 N9059
!#4 N9060 P3264 BLD 2 -1 FP BE Pri
!#4 N9061 P3264 BLD 3 -1 FP BE Pri
!#4 N9062 P3265 LD 6 -1 Int BE Pri
!#4 N9063 P3266 BLD 8 -1 FP BE Pri
!#4 N9064 P3266 BLD 9 -1 FP BE Pri
!#A N9063 N9064
!#4 N9065 P3266 BLD 10 -1 FP BE Pri
!#4 N9066 P3266 BLD 11 -1 FP BE Pri
!#4 N9067 P3267 LD 14 -1 FP BE Pri
!#4 N9068 P3267 LD 14 -1 FP BE Pri
!#4 N9069 P3268 LD 17 -1 Int BE Pri
!#4 N9070 P3269 DWLD 20 -1 Int BE Pri
!#4 N9071 P3269 DWLD 21 -1 Int BE Pri
!#A N9070 N9071
!#4 N9072 P3270 LD 19 -1 Int BE Pri
!#4 N9073 P3271 LD 31 -1 Int BE Pri
!#4 N9074 P3272 BLD 24 -1 FP BE Pri
!#4 N9075 P3272 BLD 25 -1 FP BE Pri
!#A N9074 N9075
!#4 N9076 P3272 BLD 26 -1 FP BE Pri
!#4 N9077 P3272 BLD 27 -1 FP BE Pri
!#4 N9078 P3273 LD 4 -1 Int BE Pri
!#4 N9079 P3271 LD 31 -1 Int BE Pri
!#4 N9080 P3272 BLD 24 -1 FP BE Pri
!#4 N9081 P3272 BLD 25 -1 FP BE Pri
!#A N9080 N9081
!#4 N9082 P3272 BLD 26 -1 FP BE Pri
!#4 N9083 P3272 BLD 27 -1 FP BE Pri
!#4 N9084 P3273 LD 4 -1 Int BE Pri
!#4 N9085 P3274 BLD 8 -1 FP BE Pri
!#4 N9086 P3274 BLD 9 -1 FP BE Pri
!#A N9085 N9086
!#4 N9087 P3274 BLD 10 -1 FP BE Pri
!#4 N9088 P3274 BLD 11 -1 FP BE Pri
!#4 N9089 P3275 BLD 16 -1 FP BE Pri
!#4 N9090 P3275 BLD 17 -1 FP BE Pri
!#A N9089 N9090
!#4 N9091 P3275 BLD 18 -1 FP BE Pri
!#4 N9092 P3275 BLD 19 -1 FP BE Pri
!#4 N9093 P3276 BLD 28 -1 FP BE Pri
!#4 N9094 P3276 BLD 29 -1 FP BE Pri
!#A N9093 N9094
!#4 N9095 P3276 BLD 30 -1 FP BE Pri
!#4 N9096 P3276 BLD 31 -1 FP BE Pri
!#4 N9097 P3277 BLD 16 -1 FP BE Pri
!#4 N9098 P3277 BLD 17 -1 FP BE Pri
!#A N9097 N9098
!#4 N9099 P3277 BLD 18 -1 FP BE Pri
!#4 N9100 P3277 BLD 19 -1 FP BE Pri
!#4 N9101 P3276 BLD 28 -1 FP BE Pri
!#4 N9102 P3276 BLD 29 -1 FP BE Pri
!#A N9101 N9102
!#4 N9103 P3276 BLD 30 -1 FP BE Pri
!#4 N9104 P3276 BLD 31 -1 FP BE Pri
!#4 N9105 P3277 BLD 16 -1 FP BE Pri
!#4 N9106 P3277 BLD 17 -1 FP BE Pri
!#A N9105 N9106
!#4 N9107 P3277 BLD 18 -1 FP BE Pri
!#4 N9108 P3277 BLD 19 -1 FP BE Pri
!#4 N9109 P3278 BLD 12 -1 FP BE Pri
!#4 N9110 P3278 BLD 13 -1 FP BE Pri
!#A N9109 N9110
!#4 N9111 P3278 BLD 14 -1 FP BE Pri
!#4 N9112 P3278 BLD 15 -1 FP BE Pri
!#4 N9113 P3278 BLD 12 -1 FP BE Pri
!#4 N9114 P3278 BLD 13 -1 FP BE Pri
!#A N9113 N9114
!#4 N9115 P3278 BLD 14 -1 FP BE Pri
!#4 N9116 P3278 BLD 15 -1 FP BE Pri
!#4 N9117 P3279 DWLD 31 -1 Int BE Pri
!#4 N9118 P3280 LD 12 -1 Int BE Pri
!#4 N9119 P3279 DWLD 31 -1 Int BE Pri
!#4 N9120 P3280 LD 12 -1 Int BE Pri
!#4 N9121 P3281 LD 1 -1 Int BE Pri
!#4 N9122 P3282 LD 6 -1 Int BE Pri
!#4 N9123 P3281 LD 1 -1 Int BE Pri
!#4 N9124 P3282 LD 6 -1 Int BE Pri
!#4 N9125 P3283 LD 17 -1 Int BE Pri
!#4 N9126 P3284 LD 4 -1 Int BE Pri
!#4 N9127 P3283 LD 17 -1 Int BE Pri
!#4 N9128 P3284 LD 4 -1 Int BE Pri
!#4 N9129 P3285 BLD 28 -1 FP BE Pri
!#4 N9130 P3285 BLD 29 -1 FP BE Pri
!#A N9129 N9130
!#4 N9131 P3285 BLD 30 -1 FP BE Pri
!#4 N9132 P3285 BLD 31 -1 FP BE Pri
!#4 N9133 P3286 BLD 20 -1 FP BE Pri
!#4 N9134 P3286 BLD 21 -1 FP BE Pri
!#A N9133 N9134
!#4 N9135 P3286 BLD 22 -1 FP BE Pri
!#4 N9136 P3286 BLD 23 -1 FP BE Pri
!#4 N9137 P3285 BLD 28 -1 FP BE Pri
!#4 N9138 P3285 BLD 29 -1 FP BE Pri
!#A N9137 N9138
!#4 N9139 P3285 BLD 30 -1 FP BE Pri
!#4 N9140 P3285 BLD 31 -1 FP BE Pri
!#4 N9141 P3286 BLD 20 -1 FP BE Pri
!#4 N9142 P3286 BLD 21 -1 FP BE Pri
!#A N9141 N9142
!#4 N9143 P3286 BLD 22 -1 FP BE Pri
!#4 N9144 P3286 BLD 23 -1 FP BE Pri
!#4 N9145 P3287 BLD 28 -1 FP BE Pri
!#4 N9146 P3287 BLD 29 -1 FP BE Pri
!#A N9145 N9146
!#4 N9147 P3287 BLD 30 -1 FP BE Pri
!#4 N9148 P3287 BLD 31 -1 FP BE Pri
!#4 N9149 P3288 LD 9 -1 Int BE Pri
!#4 N9150 P3289 LD 25 -1 Int BE Pri
!#4 N9151 P3290 BLD 0 -1 FP BE Pri
!#4 N9152 P3290 BLD 1 -1 FP BE Pri
!#A N9151 N9152
!#4 N9153 P3290 BLD 2 -1 FP BE Pri
!#4 N9154 P3290 BLD 3 -1 FP BE Pri
!#4 N9155 P3291 LD 31 -1 Int BE Pri
!#4 N9156 P3292 LD 4 -1 Int BE Pri
!#4 N9157 P3291 LD 31 -1 Int BE Pri
!#4 N9158 P3292 LD 4 -1 Int BE Pri
!#4 N9159 P3293 LD 10 -1 Int BE Pri
!#4 N9160 P3293 CAS 10 -1 N9159 0x200002b Int BE Pri
!#4 N9161 P3293 LD 10 -1 Int BE Pri
!#4 N9162 P3293 CAS 10 -1 N9161 0x200002c Int BE Pri
!#4 N9163 P3294 BLD 16 -1 FP BE Pri
!#4 N9164 P3294 BLD 17 -1 FP BE Pri
!#A N9163 N9164
!#4 N9165 P3294 BLD 18 -1 FP BE Pri
!#4 N9166 P3294 BLD 19 -1 FP BE Pri
!#4 N9167 P3295 DWLD 16 -1 Int BE Pri
!#4 N9168 P3295 DWLD 17 -1 Int BE Pri
!#A N9167 N9168
!#4 N9169 P3296 BLD 4 -1 FP BE Pri
!#4 N9170 P3296 BLD 5 -1 FP BE Pri
!#A N9169 N9170
!#4 N9171 P3296 BLD 6 -1 FP BE Pri
!#4 N9172 P3296 BLD 7 -1 FP BE Pri
!#4 N9173 P3297 DWLD 2 -1 Int BE Pri
!#4 N9174 P3298 DWLD 0 -1 Int BE Pri
!#4 N9175 P3298 DWLD 1 -1 Int BE Pri
!#A N9174 N9175
!#4 N9176 P3299 LD 27 -1 Int BE Pri
!#4 N9177 P3300 DWLD 2 -1 FP BE Pri
!#4 N9178 P3301 MEMBAR
!#5 N9179 P3302 LD 15 -1 Int LE Pri
!#5 N9180 P3303 MEMBAR
!#5 N9181 P3304 LD 24 -1 Int BE Pri
!#5 N9182 P3302 LD 15 -1 Int LE Pri
!#5 N9183 P3303 MEMBAR
!#5 N9184 P3304 LD 24 -1 Int BE Pri
!#5 N9185 P3305 ST 1 0x2800001 Int BE Pri
!#5 N9186 P3306 BSTC 12 0x42000001 FP BE Pri
!#5 N9187 P3306 BSTC 13 0x42000002 FP BE Pri
!#A N9186 N9187
!#5 N9188 P3306 BSTC 14 0x42000003 FP BE Pri
!#5 N9189 P3306 BSTC 15 0x42000004 FP BE Pri
!#5 N9190 P3307 BLD 4 -1 FP BE Pri
!#5 N9191 P3307 BLD 5 -1 FP BE Pri
!#A N9190 N9191
!#5 N9192 P3307 BLD 6 -1 FP BE Pri
!#5 N9193 P3307 BLD 7 -1 FP BE Pri
!#5 N9194 P3308 DWLD 8 -1 FP BE Pri
!#5 N9195 P3308 DWLD 9 -1 FP BE Pri
!#A N9194 N9195
!#5 N9196 P3309 LD 19 -1 Int BE Pri
!#5 N9197 P3310 LD 17 -1 Int LE Pri
!#5 N9198 P3310 CAS 17 -1 N9197 0x2800002 Int LE Pri
!#5 N9199 P3311 LD 30 -1 Int BE Pri
!#5 N9200 P3309 LD 19 -1 Int BE Pri
!#5 N9201 P3310 LD 17 -1 Int LE Pri
!#5 N9202 P3310 CAS 17 -1 N9201 0x2800003 Int LE Pri
!#5 N9203 P3311 LD 30 -1 Int BE Pri
!#5 N9204 P3312 DWLD 4 -1 Int BE Pri
!#5 N9205 P3312 DWLD 5 -1 Int BE Pri
!#A N9204 N9205
!#5 N9209 P3315 DWLD 15 -1 Int BE Pri
!#5 N9210 P3316 BLD 28 -1 FP BE Pri
!#5 N9211 P3316 BLD 29 -1 FP BE Pri
!#A N9210 N9211
!#5 N9212 P3316 BLD 30 -1 FP BE Pri
!#5 N9213 P3316 BLD 31 -1 FP BE Pri
!#5 N9214 P3317 LD 30 -1 Int BE Pri
!#5 N9215 P3315 DWLD 15 -1 Int BE Pri
!#5 N9216 P3316 BLD 28 -1 FP BE Pri
!#5 N9217 P3316 BLD 29 -1 FP BE Pri
!#A N9216 N9217
!#5 N9218 P3316 BLD 30 -1 FP BE Pri
!#5 N9219 P3316 BLD 31 -1 FP BE Pri
!#5 N9220 P3317 LD 30 -1 Int BE Pri
!#5 N9221 P3318 LD 15 -1 Int BE Pri
!#5 N9222 P3319 LD 13 -1 Int BE Pri
!#5 N9223 P3320 BLD 8 -1 FP BE Pri
!#5 N9224 P3320 BLD 9 -1 FP BE Pri
!#A N9223 N9224
!#5 N9225 P3320 BLD 10 -1 FP BE Pri
!#5 N9226 P3320 BLD 11 -1 FP BE Pri
!#5 N9227 P3321 LD 28 -1 Int BE Pri
!#5 N9228 P3322 LD 12 -1 Int BE Pri
!#5 N9229 P3323 DWLD 18 -1 Int LE Pri
!#5 N9230 P3324 LD 29 -1 Int BE Pri
!#5 N9231 P3323 DWLD 18 -1 Int LE Pri
!#5 N9232 P3324 LD 29 -1 Int BE Pri
!#5 N9233 P3325 LD 25 -1 Int BE Pri
!#5 N9234 P3326 DWLD 30 -1 Int BE Pri
!#5 N9235 P3327 LD 20 -1 Int BE Pri
!#5 N9236 P3328 LD 5 -1 Int BE Pri
!#5 N9237 P3329 BLD 0 -1 FP BE Pri
!#5 N9238 P3329 BLD 1 -1 FP BE Pri
!#A N9237 N9238
!#5 N9239 P3329 BLD 2 -1 FP BE Pri
!#5 N9240 P3329 BLD 3 -1 FP BE Pri
!#5 N9241 P3330 DWLD 28 -1 Int BE Pri
!#5 N9242 P3330 DWLD 29 -1 Int BE Pri
!#A N9241 N9242
!#5 N9243 P3329 BLD 0 -1 FP BE Pri
!#5 N9244 P3329 BLD 1 -1 FP BE Pri
!#A N9243 N9244
!#5 N9245 P3329 BLD 2 -1 FP BE Pri
!#5 N9246 P3329 BLD 3 -1 FP BE Pri
!#5 N9247 P3330 DWLD 28 -1 Int BE Pri
!#5 N9248 P3330 DWLD 29 -1 Int BE Pri
!#A N9247 N9248
!#5 N9249 P3331 DWLD 18 -1 FP BE Pri
!#5 N9250 P3331 DWLD 18 -1 FP BE Pri
!#5 N9251 P3332 BLD 24 -1 FP BE Pri
!#5 N9252 P3332 BLD 25 -1 FP BE Pri
!#A N9251 N9252
!#5 N9253 P3332 BLD 26 -1 FP BE Pri
!#5 N9254 P3332 BLD 27 -1 FP BE Pri
!#5 N9255 P3333 BLD 8 -1 FP BE Pri
!#5 N9256 P3333 BLD 9 -1 FP BE Pri
!#A N9255 N9256
!#5 N9257 P3333 BLD 10 -1 FP BE Pri
!#5 N9258 P3333 BLD 11 -1 FP BE Pri
!#5 N9259 P3334 DWLD 30 -1 Int BE Pri
!#5 N9260 P3335 LD 28 -1 Int BE Pri
!#5 N9261 P3336 BST 24 0x42000005 FP BE Pri
!#5 N9262 P3336 BST 25 0x42000006 FP BE Pri
!#A N9261 N9262
!#5 N9263 P3336 BST 26 0x42000007 FP BE Pri
!#5 N9264 P3336 BST 27 0x42000008 FP BE Pri
!#5 N9265 P3337 DWLD 10 -1 Int LE Pri
!#5 N9266 P3338 LD 25 -1 Int BE Pri
!#5 N9267 P3339 DWLD 20 -1 Int BE Pri
!#5 N9268 P3339 DWLD 21 -1 Int BE Pri
!#A N9267 N9268
!#5 N9269 P3340 LD 28 -1 Int BE Pri
!#5 N9270 P3341 LD 20 -1 Int BE Pri
!#5 N9271 P3339 DWLD 20 -1 Int BE Pri
!#5 N9272 P3339 DWLD 21 -1 Int BE Pri
!#A N9271 N9272
!#5 N9273 P3340 LD 28 -1 Int BE Pri
!#5 N9274 P3341 LD 20 -1 Int BE Pri
!#5 N9275 P3342 BLD 0 -1 FP BE Pri
!#5 N9276 P3342 BLD 1 -1 FP BE Pri
!#A N9275 N9276
!#5 N9277 P3342 BLD 2 -1 FP BE Pri
!#5 N9278 P3342 BLD 3 -1 FP BE Pri
!#5 N9279 P3342 BLD 0 -1 FP BE Pri
!#5 N9280 P3342 BLD 1 -1 FP BE Pri
!#A N9279 N9280
!#5 N9281 P3342 BLD 2 -1 FP BE Pri
!#5 N9282 P3342 BLD 3 -1 FP BE Pri
!#5 N9283 P3343 LD 6 -1 Int BE Pri
!#5 N9284 P3344 BLD 8 -1 FP BE Pri
!#5 N9285 P3344 BLD 9 -1 FP BE Pri
!#A N9284 N9285
!#5 N9286 P3344 BLD 10 -1 FP BE Pri
!#5 N9287 P3344 BLD 11 -1 FP BE Pri
!#5 N9288 P3345 LD 17 -1 Int BE Pri
!#5 N9289 P3346 LD 20 -1 Int BE Pri
!#5 N9290 P3347 BLD 4 -1 FP BE Pri
!#5 N9291 P3347 BLD 5 -1 FP BE Pri
!#A N9290 N9291
!#5 N9292 P3347 BLD 6 -1 FP BE Pri
!#5 N9293 P3347 BLD 7 -1 FP BE Pri
!#5 N9294 P3348 LD 0 -1 Int BE Pri
!#5 N9295 P3346 LD 20 -1 Int BE Pri
!#5 N9296 P3347 BLD 4 -1 FP BE Pri
!#5 N9297 P3347 BLD 5 -1 FP BE Pri
!#A N9296 N9297
!#5 N9298 P3347 BLD 6 -1 FP BE Pri
!#5 N9299 P3347 BLD 7 -1 FP BE Pri
!#5 N9300 P3348 LD 0 -1 Int BE Pri
!#5 N9301 P3349 BLD 16 -1 FP BE Pri
!#5 N9302 P3349 BLD 17 -1 FP BE Pri
!#A N9301 N9302
!#5 N9303 P3349 BLD 18 -1 FP BE Pri
!#5 N9304 P3349 BLD 19 -1 FP BE Pri
!#5 N9305 P3349 BLD 16 -1 FP BE Pri
!#5 N9306 P3349 BLD 17 -1 FP BE Pri
!#A N9305 N9306
!#5 N9307 P3349 BLD 18 -1 FP BE Pri
!#5 N9308 P3349 BLD 19 -1 FP BE Pri
!#5 N9309 P3350 LD 26 -1 Int BE Pri
!#5 N9310 P3351 LD 11 -1 Int BE Pri
!#5 N9311 P3352 DWLD 31 -1 Int BE Pri
!#5 N9312 P3353 LD 19 -1 Int BE Pri
!#5 N9313 P3354 DWST 11 0x2800004 Int BE Pri
!#5 N9314 P3355 LD 9 -1 Int BE Pri
!#5 N9315 P3356 LD 10 -1 Int BE Pri
!#5 N9316 P3354 DWST 11 0x2800005 Int BE Pri
!#5 N9317 P3355 LD 9 -1 Int BE Pri
!#5 N9318 P3356 LD 10 -1 Int BE Pri
!#5 N9319 P3357 LD 20 -1 Int BE Pri
!#5 N9320 P3358 LD 29 -1 Int BE Pri
!#5 N9321 P3359 BLD 4 -1 FP BE Pri
!#5 N9322 P3359 BLD 5 -1 FP BE Pri
!#A N9321 N9322
!#5 N9323 P3359 BLD 6 -1 FP BE Pri
!#5 N9324 P3359 BLD 7 -1 FP BE Pri
!#5 N9325 P3360 LD 28 -1 Int BE Pri
!#5 N9326 P3361 LD 16 -1 Int BE Pri
!#5 N9327 P3362 DWLD 8 -1 Int BE Pri
!#5 N9328 P3362 DWLD 9 -1 Int BE Pri
!#A N9327 N9328
!#5 N9329 P3363 ST 14 0x2800006 Int BE Pri
!#5 N9330 P3364 LD 4 -1 Int BE Pri
!#5 N9331 P3365 LD 17 -1 Int BE Pri
!#5 N9332 P3364 LD 4 -1 Int BE Pri
!#5 N9333 P3365 LD 17 -1 Int BE Pri
!#5 N9334 P3366 DWLD 12 -1 Int BE Pri
!#5 N9335 P3366 DWLD 13 -1 Int BE Pri
!#A N9334 N9335
!#5 N9336 P3367 BLD 4 -1 FP BE Pri
!#5 N9337 P3367 BLD 5 -1 FP BE Pri
!#A N9336 N9337
!#5 N9338 P3367 BLD 6 -1 FP BE Pri
!#5 N9339 P3367 BLD 7 -1 FP BE Pri
!#5 N9340 P3368 BLD 4 -1 FP BE Pri
!#5 N9341 P3368 BLD 5 -1 FP BE Pri
!#A N9340 N9341
!#5 N9342 P3368 BLD 6 -1 FP BE Pri
!#5 N9343 P3368 BLD 7 -1 FP BE Pri
!#5 N9344 P3369 BLD 24 -1 FP BE Pri
!#5 N9345 P3369 BLD 25 -1 FP BE Pri
!#A N9344 N9345
!#5 N9346 P3369 BLD 26 -1 FP BE Pri
!#5 N9347 P3369 BLD 27 -1 FP BE Pri
!#5 N9348 P3369 BLD 24 -1 FP BE Pri
!#5 N9349 P3369 BLD 25 -1 FP BE Pri
!#A N9348 N9349
!#5 N9350 P3369 BLD 26 -1 FP BE Pri
!#5 N9351 P3369 BLD 27 -1 FP BE Pri
!#5 N9352 P3370 LD 26 -1 Int BE Pri
!#5 N9353 P3371 SWAP 31 0xffffffff 0x2800007 Int BE Pri
!#5 N9354 P3372 DWST 0 0x2800008 Int BE Pri
!#5 N9355 P3372 DWST 1 0x2800009 Int BE Pri
!#A N9354 N9355
!#5 N9356 P3373 SWAP 3 0xffffffff 0x280000a Int BE Pri
!#5 N9357 P3374 LD 1 -1 Int BE Pri
!#5 N9358 P3375 DWLD 15 -1 Int BE Pri
!#5 N9359 P3376 DWLD 22 -1 Int BE Pri
!#5 N9360 P3375 DWLD 15 -1 Int BE Pri
!#5 N9361 P3376 DWLD 22 -1 Int BE Pri
!#5 N9362 P3377 LD 12 -1 Int BE Pri
!#5 N9363 P3378 LD 18 -1 Int BE Pri
!#5 N9364 P3377 LD 12 -1 Int BE Pri
!#5 N9365 P3378 LD 18 -1 Int BE Pri
!#5 N9366 P3379 BLD 24 -1 FP BE Pri
!#5 N9367 P3379 BLD 25 -1 FP BE Pri
!#A N9366 N9367
!#5 N9368 P3379 BLD 26 -1 FP BE Pri
!#5 N9369 P3379 BLD 27 -1 FP BE Pri
!#5 N9370 P3380 SWAP 13 0xffffffff 0x280000b Int BE Pri
!#5 N9371 P3381 LD 11 -1 Int BE Pri
!#5 N9372 P3382 LD 16 -1 Int BE Pri
!#5 N9373 P3383 LD 9 -1 Int BE Pri
!#5 N9374 P3382 LD 16 -1 Int BE Pri
!#5 N9375 P3383 LD 9 -1 Int BE Pri
!#5 N9376 P3384 BLD 0 -1 FP BE Pri
!#5 N9377 P3384 BLD 1 -1 FP BE Pri
!#A N9376 N9377
!#5 N9378 P3384 BLD 2 -1 FP BE Pri
!#5 N9379 P3384 BLD 3 -1 FP BE Pri
!#5 N9380 P3385 BLD 28 -1 FP BE Pri
!#5 N9381 P3385 BLD 29 -1 FP BE Pri
!#A N9380 N9381
!#5 N9382 P3385 BLD 30 -1 FP BE Pri
!#5 N9383 P3385 BLD 31 -1 FP BE Pri
!#5 N9384 P3384 BLD 0 -1 FP BE Pri
!#5 N9385 P3384 BLD 1 -1 FP BE Pri
!#A N9384 N9385
!#5 N9386 P3384 BLD 2 -1 FP BE Pri
!#5 N9387 P3384 BLD 3 -1 FP BE Pri
!#5 N9388 P3385 BLD 28 -1 FP BE Pri
!#5 N9389 P3385 BLD 29 -1 FP BE Pri
!#A N9388 N9389
!#5 N9390 P3385 BLD 30 -1 FP BE Pri
!#5 N9391 P3385 BLD 31 -1 FP BE Pri
!#5 N9392 P3386 DWLD 0 -1 Int BE Pri
!#5 N9393 P3386 DWLD 1 -1 Int BE Pri
!#A N9392 N9393
!#5 N9394 P3386 DWLD 0 -1 Int BE Pri
!#5 N9395 P3386 DWLD 1 -1 Int BE Pri
!#A N9394 N9395
!#5 N9396 P3387 DWLD 16 -1 Int BE Pri
!#5 N9397 P3387 DWLD 17 -1 Int BE Pri
!#A N9396 N9397
!#5 N9398 P3387 DWLD 16 -1 Int BE Pri
!#5 N9399 P3387 DWLD 17 -1 Int BE Pri
!#A N9398 N9399
!#5 N9400 P3388 BLD 8 -1 FP BE Pri
!#5 N9401 P3388 BLD 9 -1 FP BE Pri
!#A N9400 N9401
!#5 N9402 P3388 BLD 10 -1 FP BE Pri
!#5 N9403 P3388 BLD 11 -1 FP BE Pri
!#5 N9404 P3388 BLD 8 -1 FP BE Pri
!#5 N9405 P3388 BLD 9 -1 FP BE Pri
!#A N9404 N9405
!#5 N9406 P3388 BLD 10 -1 FP BE Pri
!#5 N9407 P3388 BLD 11 -1 FP BE Pri
!#5 N9408 P3389 BLD 4 -1 FP BE Pri
!#5 N9409 P3389 BLD 5 -1 FP BE Pri
!#A N9408 N9409
!#5 N9410 P3389 BLD 6 -1 FP BE Pri
!#5 N9411 P3389 BLD 7 -1 FP BE Pri
!#5 N9412 P3390 DWLD 24 -1 Int BE Pri
!#5 N9413 P3390 DWLD 25 -1 Int BE Pri
!#A N9412 N9413
!#5 N9414 P3391 DWLD 24 -1 Int BE Pri
!#5 N9415 P3391 DWLD 25 -1 Int BE Pri
!#A N9414 N9415
!#5 N9416 P3391 CASX 24 -1 N9414 0x280000c Int BE Pri
!#5 N9417 P3391 CASX 25 -1 N9415 0x280000d Int BE Pri
!#A N9416 N9417
!#5 N9418 P3390 DWLD 24 -1 Int BE Pri
!#5 N9419 P3390 DWLD 25 -1 Int BE Pri
!#A N9418 N9419
!#5 N9420 P3391 DWLD 24 -1 Int BE Pri
!#5 N9421 P3391 DWLD 25 -1 Int BE Pri
!#A N9420 N9421
!#5 N9422 P3391 CASX 24 -1 N9420 0x280000e Int BE Pri
!#5 N9423 P3391 CASX 25 -1 N9421 0x280000f Int BE Pri
!#A N9422 N9423
!#5 N9424 P3392 BLD 20 -1 FP BE Pri
!#5 N9425 P3392 BLD 21 -1 FP BE Pri
!#A N9424 N9425
!#5 N9426 P3392 BLD 22 -1 FP BE Pri
!#5 N9427 P3392 BLD 23 -1 FP BE Pri
!#5 N9428 P3393 DWLD 20 -1 Int BE Pri
!#5 N9429 P3393 DWLD 21 -1 Int BE Pri
!#A N9428 N9429
!#5 N9430 P3394 DWLD 28 -1 Int BE Pri
!#5 N9431 P3394 DWLD 29 -1 Int BE Pri
!#A N9430 N9431
!#5 N9432 P3394 DWLD 28 -1 Int BE Pri
!#5 N9433 P3394 DWLD 29 -1 Int BE Pri
!#A N9432 N9433
!#5 N9434 P3395 BLD 24 -1 FP BE Pri
!#5 N9435 P3395 BLD 25 -1 FP BE Pri
!#A N9434 N9435
!#5 N9436 P3395 BLD 26 -1 FP BE Pri
!#5 N9437 P3395 BLD 27 -1 FP BE Pri
!#5 N9438 P3396 BLD 28 -1 FP BE Pri
!#5 N9439 P3396 BLD 29 -1 FP BE Pri
!#A N9438 N9439
!#5 N9440 P3396 BLD 30 -1 FP BE Pri
!#5 N9441 P3396 BLD 31 -1 FP BE Pri
!#5 N9442 P3397 LD 29 -1 Int BE Pri
!#5 N9443 P3398 LD 10 -1 Int BE Pri
!#5 N9444 P3397 LD 29 -1 Int BE Pri
!#5 N9445 P3398 LD 10 -1 Int BE Pri
!#5 N9446 P3399 BLD 8 -1 FP BE Pri
!#5 N9447 P3399 BLD 9 -1 FP BE Pri
!#A N9446 N9447
!#5 N9448 P3399 BLD 10 -1 FP BE Pri
!#5 N9449 P3399 BLD 11 -1 FP BE Pri
!#5 N9450 P3400 LD 22 -1 Int BE Pri
!#5 N9451 P3401 LD 14 -1 Int BE Pri
!#5 N9452 P3399 BLD 8 -1 FP BE Pri
!#5 N9453 P3399 BLD 9 -1 FP BE Pri
!#A N9452 N9453
!#5 N9454 P3399 BLD 10 -1 FP BE Pri
!#5 N9455 P3399 BLD 11 -1 FP BE Pri
!#5 N9456 P3400 LD 22 -1 Int BE Pri
!#5 N9457 P3401 LD 14 -1 Int BE Pri
!#5 N9458 P3402 BLD 0 -1 FP BE Pri
!#5 N9459 P3402 BLD 1 -1 FP BE Pri
!#A N9458 N9459
!#5 N9460 P3402 BLD 2 -1 FP BE Pri
!#5 N9461 P3402 BLD 3 -1 FP BE Pri
!#5 N9462 P3403 LD 23 -1 Int BE Pri
!#5 N9463 P3404 LD 20 -1 Int BE Pri
!#5 N9464 P3405 BLD 16 -1 FP BE Pri
!#5 N9465 P3405 BLD 17 -1 FP BE Pri
!#A N9464 N9465
!#5 N9466 P3405 BLD 18 -1 FP BE Pri
!#5 N9467 P3405 BLD 19 -1 FP BE Pri
!#5 N9468 P3406 LD 12 -1 Int BE Pri
!#5 N9469 P3407 LD 4 -1 Int BE Pri
!#5 N9470 P3405 BLD 16 -1 FP BE Pri
!#5 N9471 P3405 BLD 17 -1 FP BE Pri
!#A N9470 N9471
!#5 N9472 P3405 BLD 18 -1 FP BE Pri
!#5 N9473 P3405 BLD 19 -1 FP BE Pri
!#5 N9474 P3406 LD 12 -1 Int BE Pri
!#5 N9475 P3407 LD 4 -1 Int BE Pri
!#5 N9478 P3409 DWLD 20 -1 Int BE Pri
!#5 N9479 P3409 DWLD 21 -1 Int BE Pri
!#A N9478 N9479
!#5 N9480 P3410 ST 1 0x2800010 Int BE Pri
!#5 N9481 P3410 ST 1 0x2800011 Int BE Pri
!#5 N9482 P3411 LD 30 -1 Int BE Pri
!#5 N9483 P3412 LD 9 -1 Int BE Pri
!#5 N9484 P3413 LD 15 -1 Int BE Pri
!#5 N9486 P3415 LD 25 -1 Int BE Pri
!#5 N9487 P3416 BLD 4 -1 FP BE Pri
!#5 N9488 P3416 BLD 5 -1 FP BE Pri
!#A N9487 N9488
!#5 N9489 P3416 BLD 6 -1 FP BE Pri
!#5 N9490 P3416 BLD 7 -1 FP BE Pri
!#5 N9491 P3417 BLD 12 -1 FP BE Pri
!#5 N9492 P3417 BLD 13 -1 FP BE Pri
!#A N9491 N9492
!#5 N9493 P3417 BLD 14 -1 FP BE Pri
!#5 N9494 P3417 BLD 15 -1 FP BE Pri
!#5 N9495 P3418 DWLD 28 -1 Int BE Pri
!#5 N9496 P3418 DWLD 29 -1 Int BE Pri
!#A N9495 N9496
!#5 N9497 P3419 BSTC 12 0x42000009 FP BE Pri
!#5 N9498 P3419 BSTC 13 0x4200000a FP BE Pri
!#A N9497 N9498
!#5 N9499 P3419 BSTC 14 0x4200000b FP BE Pri
!#5 N9500 P3419 BSTC 15 0x4200000c FP BE Pri
!#5 N9501 P3420 LD 31 -1 Int LE Pri
!#5 N9502 P3421 LD 21 -1 Int BE Pri
!#5 N9503 P3420 LD 31 -1 Int LE Pri
!#5 N9504 P3421 LD 21 -1 Int BE Pri
!#5 N9505 P3422 DWLD 20 -1 FP BE Pri
!#5 N9506 P3422 DWLD 21 -1 FP BE Pri
!#A N9505 N9506
!#5 N9507 P3423 DWLD 12 -1 Int BE Pri
!#5 N9508 P3423 DWLD 13 -1 Int BE Pri
!#A N9507 N9508
!#5 N9509 P3424 DWLD 16 -1 FP BE Pri
!#5 N9510 P3424 DWLD 17 -1 FP BE Pri
!#A N9509 N9510
!#5 N9511 P3425 BLD 16 -1 FP BE Pri
!#5 N9512 P3425 BLD 17 -1 FP BE Pri
!#A N9511 N9512
!#5 N9513 P3425 BLD 18 -1 FP BE Pri
!#5 N9514 P3425 BLD 19 -1 FP BE Pri
!#5 N9515 P3424 DWLD 16 -1 FP BE Pri
!#5 N9516 P3424 DWLD 17 -1 FP BE Pri
!#A N9515 N9516
!#5 N9517 P3425 BLD 16 -1 FP BE Pri
!#5 N9518 P3425 BLD 17 -1 FP BE Pri
!#A N9517 N9518
!#5 N9519 P3425 BLD 18 -1 FP BE Pri
!#5 N9520 P3425 BLD 19 -1 FP BE Pri
!#5 N9521 P3426 DWLD 20 -1 Int BE Pri
!#5 N9522 P3426 DWLD 21 -1 Int BE Pri
!#A N9521 N9522
!#5 N9523 P3427 DWLD 12 -1 Int BE Pri
!#5 N9524 P3427 DWLD 13 -1 Int BE Pri
!#A N9523 N9524
!#5 N9525 P3428 BLD 24 -1 FP BE Pri
!#5 N9526 P3428 BLD 25 -1 FP BE Pri
!#A N9525 N9526
!#5 N9527 P3428 BLD 26 -1 FP BE Pri
!#5 N9528 P3428 BLD 27 -1 FP BE Pri
!#5 N9529 P3429 LD 26 -1 Int LE Pri
!#5 N9530 P3430 LD 22 -1 Int BE Pri
!#5 N9531 P3429 LD 26 -1 Int LE Pri
!#5 N9532 P3430 LD 22 -1 Int BE Pri
!#5 N9533 P3431 BLD 24 -1 FP BE Pri
!#5 N9534 P3431 BLD 25 -1 FP BE Pri
!#A N9533 N9534
!#5 N9535 P3431 BLD 26 -1 FP BE Pri
!#5 N9536 P3431 BLD 27 -1 FP BE Pri
!#5 N9537 P3432 BLD 12 -1 FP BE Pri
!#5 N9538 P3432 BLD 13 -1 FP BE Pri
!#A N9537 N9538
!#5 N9539 P3432 BLD 14 -1 FP BE Pri
!#5 N9540 P3432 BLD 15 -1 FP BE Pri
!#5 N9541 P3433 DWLD 4 -1 Int BE Pri
!#5 N9542 P3433 DWLD 5 -1 Int BE Pri
!#A N9541 N9542
!#5 N9543 P3434 DWLD 22 -1 Int BE Pri
!#5 N9544 P3435 BLD 16 -1 FP BE Pri
!#5 N9545 P3435 BLD 17 -1 FP BE Pri
!#A N9544 N9545
!#5 N9546 P3435 BLD 18 -1 FP BE Pri
!#5 N9547 P3435 BLD 19 -1 FP BE Pri
!#5 N9548 P3436 LD 4 -1 Int BE Pri
!#5 N9549 P3434 DWLD 22 -1 Int BE Pri
!#5 N9550 P3435 BLD 16 -1 FP BE Pri
!#5 N9551 P3435 BLD 17 -1 FP BE Pri
!#A N9550 N9551
!#5 N9552 P3435 BLD 18 -1 FP BE Pri
!#5 N9553 P3435 BLD 19 -1 FP BE Pri
!#5 N9554 P3436 LD 4 -1 Int BE Pri
!#5 N9555 P3437 BLD 0 -1 FP BE Pri
!#5 N9556 P3437 BLD 1 -1 FP BE Pri
!#A N9555 N9556
!#5 N9557 P3437 BLD 2 -1 FP BE Pri
!#5 N9558 P3437 BLD 3 -1 FP BE Pri
!#5 N9559 P3437 BLD 0 -1 FP BE Pri
!#5 N9560 P3437 BLD 1 -1 FP BE Pri
!#A N9559 N9560
!#5 N9561 P3437 BLD 2 -1 FP BE Pri
!#5 N9562 P3437 BLD 3 -1 FP BE Pri
!#5 N9563 P3438 BLD 16 -1 FP BE Pri
!#5 N9564 P3438 BLD 17 -1 FP BE Pri
!#A N9563 N9564
!#5 N9565 P3438 BLD 18 -1 FP BE Pri
!#5 N9566 P3438 BLD 19 -1 FP BE Pri
!#5 N9567 P3439 DWLD 15 -1 Int BE Pri
!#5 N9568 P3440 LD 28 -1 Int BE Pri
!#5 N9569 P3438 BLD 16 -1 FP BE Pri
!#5 N9570 P3438 BLD 17 -1 FP BE Pri
!#A N9569 N9570
!#5 N9571 P3438 BLD 18 -1 FP BE Pri
!#5 N9572 P3438 BLD 19 -1 FP BE Pri
!#5 N9573 P3439 DWLD 15 -1 Int BE Pri
!#5 N9574 P3440 LD 28 -1 Int BE Pri
!#5 N9575 P3441 LD 22 -1 Int BE Pri
!#5 N9576 P3441 CAS 22 -1 N9575 0x2800012 Int BE Pri
!#5 N9577 P3441 LD 22 -1 Int BE Pri
!#5 N9578 P3441 CAS 22 -1 N9577 0x2800013 Int BE Pri
!#5 N9579 P3442 BLD 8 -1 FP BE Pri
!#5 N9580 P3442 BLD 9 -1 FP BE Pri
!#A N9579 N9580
!#5 N9581 P3442 BLD 10 -1 FP BE Pri
!#5 N9582 P3442 BLD 11 -1 FP BE Pri
!#5 N9583 P3443 LD 8 -1 Int BE Pri
!#5 N9584 P3444 LD 11 -1 Int BE Pri
!#5 N9585 P3445 DWLD 12 -1 FP BE Pri
!#5 N9586 P3445 DWLD 13 -1 FP BE Pri
!#A N9585 N9586
!#5 N9587 P3446 BLD 12 -1 FP BE Pri
!#5 N9588 P3446 BLD 13 -1 FP BE Pri
!#A N9587 N9588
!#5 N9589 P3446 BLD 14 -1 FP BE Pri
!#5 N9590 P3446 BLD 15 -1 FP BE Pri
!#5 N9591 P3445 DWLD 12 -1 FP BE Pri
!#5 N9592 P3445 DWLD 13 -1 FP BE Pri
!#A N9591 N9592
!#5 N9593 P3446 BLD 12 -1 FP BE Pri
!#5 N9594 P3446 BLD 13 -1 FP BE Pri
!#A N9593 N9594
!#5 N9595 P3446 BLD 14 -1 FP BE Pri
!#5 N9596 P3446 BLD 15 -1 FP BE Pri
!#5 N9597 P3447 LD 11 -1 Int BE Pri
!#5 N9598 P3448 LD 0 -1 Int BE Pri
!#5 N9599 P3447 LD 11 -1 Int BE Pri
!#5 N9600 P3448 LD 0 -1 Int BE Pri
!#5 N9601 P3449 BLD 4 -1 FP BE Pri
!#5 N9602 P3449 BLD 5 -1 FP BE Pri
!#A N9601 N9602
!#5 N9603 P3449 BLD 6 -1 FP BE Pri
!#5 N9604 P3449 BLD 7 -1 FP BE Pri
!#5 N9605 P3450 DWLD 6 -1 Int BE Pri
!#5 N9606 P3451 LD 17 -1 Int BE Pri
!#5 N9607 P3452 DWLD 24 -1 Int BE Pri
!#5 N9608 P3452 DWLD 25 -1 Int BE Pri
!#A N9607 N9608
!#5 N9609 P3453 DWLD 22 -1 Int BE Pri
!#5 N9610 P3454 LD 14 -1 Int BE Pri
!#5 N9613 P3456 LD 2 -1 Int BE Pri
!#5 N9614 P3457 LD 26 -1 Int BE Pri
!#5 N9615 P3458 BLD 28 -1 FP BE Pri
!#5 N9616 P3458 BLD 29 -1 FP BE Pri
!#A N9615 N9616
!#5 N9617 P3458 BLD 30 -1 FP BE Pri
!#5 N9618 P3458 BLD 31 -1 FP BE Pri
!#5 N9619 P3458 BLD 28 -1 FP BE Pri
!#5 N9620 P3458 BLD 29 -1 FP BE Pri
!#A N9619 N9620
!#5 N9621 P3458 BLD 30 -1 FP BE Pri
!#5 N9622 P3458 BLD 31 -1 FP BE Pri
!#5 N9623 P3459 SWAP 2 0xffffffff 0x2800014 Int BE Pri
!#5 N9624 P3460 LD 7 -1 Int BE Pri
!#5 N9625 P3459 SWAP 2 0xffffffff 0x2800015 Int BE Pri
!#5 N9626 P3460 LD 7 -1 Int BE Pri
!#5 N9627 P3461 BLD 20 -1 FP BE Pri
!#5 N9628 P3461 BLD 21 -1 FP BE Pri
!#A N9627 N9628
!#5 N9629 P3461 BLD 22 -1 FP BE Pri
!#5 N9630 P3461 BLD 23 -1 FP BE Pri
!#5 N9631 P3462 BLD 0 -1 FP BE Pri
!#5 N9632 P3462 BLD 1 -1 FP BE Pri
!#A N9631 N9632
!#5 N9633 P3462 BLD 2 -1 FP BE Pri
!#5 N9634 P3462 BLD 3 -1 FP BE Pri
!#5 N9635 P3463 LD 12 -1 Int BE Pri
!#5 N9636 P3464 LD 16 -1 Int BE Pri
!#5 N9637 P3465 DWLD 12 -1 Int BE Pri
!#5 N9638 P3465 DWLD 13 -1 Int BE Pri
!#A N9637 N9638
!#5 N9639 P3466 LD 2 -1 Int BE Pri
!#5 N9640 P3467 LD 13 -1 Int LE Pri
!#5 N9641 P3465 DWLD 12 -1 Int BE Pri
!#5 N9642 P3465 DWLD 13 -1 Int BE Pri
!#A N9641 N9642
!#5 N9643 P3466 LD 2 -1 Int BE Pri
!#5 N9644 P3467 LD 13 -1 Int LE Pri
!#5 N9645 P3468 BLD 8 -1 FP BE Pri
!#5 N9646 P3468 BLD 9 -1 FP BE Pri
!#A N9645 N9646
!#5 N9647 P3468 BLD 10 -1 FP BE Pri
!#5 N9648 P3468 BLD 11 -1 FP BE Pri
!#5 N9649 P3469 BLD 0 -1 FP BE Pri
!#5 N9650 P3469 BLD 1 -1 FP BE Pri
!#A N9649 N9650
!#5 N9651 P3469 BLD 2 -1 FP BE Pri
!#5 N9652 P3469 BLD 3 -1 FP BE Pri
!#5 N9653 P3468 BLD 8 -1 FP BE Pri
!#5 N9654 P3468 BLD 9 -1 FP BE Pri
!#A N9653 N9654
!#5 N9655 P3468 BLD 10 -1 FP BE Pri
!#5 N9656 P3468 BLD 11 -1 FP BE Pri
!#5 N9657 P3469 BLD 0 -1 FP BE Pri
!#5 N9658 P3469 BLD 1 -1 FP BE Pri
!#A N9657 N9658
!#5 N9659 P3469 BLD 2 -1 FP BE Pri
!#5 N9660 P3469 BLD 3 -1 FP BE Pri
!#5 N9662 P3471 DWLD 20 -1 FP BE Pri
!#5 N9663 P3471 DWLD 21 -1 FP BE Pri
!#A N9662 N9663
!#5 N9664 P3472 BLD 28 -1 FP BE Pri
!#5 N9665 P3472 BLD 29 -1 FP BE Pri
!#A N9664 N9665
!#5 N9666 P3472 BLD 30 -1 FP BE Pri
!#5 N9667 P3472 BLD 31 -1 FP BE Pri
!#5 N9668 P3473 DWLD 2 -1 Int BE Pri
!#5 N9669 P3474 LD 11 -1 Int BE Pri
!#5 N9670 P3473 DWLD 2 -1 Int BE Pri
!#5 N9671 P3474 LD 11 -1 Int BE Pri
!#5 N9672 P3475 BLD 24 -1 FP BE Pri
!#5 N9673 P3475 BLD 25 -1 FP BE Pri
!#A N9672 N9673
!#5 N9674 P3475 BLD 26 -1 FP BE Pri
!#5 N9675 P3475 BLD 27 -1 FP BE Pri
!#5 N9676 P3476 LD 24 -1 Int BE Pri
!#5 N9677 P3477 LD 8 -1 Int BE Pri
!#5 N9678 P3475 BLD 24 -1 FP BE Pri
!#5 N9679 P3475 BLD 25 -1 FP BE Pri
!#A N9678 N9679
!#5 N9680 P3475 BLD 26 -1 FP BE Pri
!#5 N9681 P3475 BLD 27 -1 FP BE Pri
!#5 N9682 P3476 LD 24 -1 Int BE Pri
!#5 N9683 P3477 LD 8 -1 Int BE Pri
!#5 N9684 P3478 LD 17 -1 Int BE Pri
!#5 N9685 P3479 LD 20 -1 Int BE Pri
!#5 N9686 P3480 DWLD 15 -1 Int BE Pri
!#5 N9687 P3481 LD 8 -1 Int BE Pri
!#5 N9688 P3482 BLD 4 -1 FP BE Pri
!#5 N9689 P3482 BLD 5 -1 FP BE Pri
!#A N9688 N9689
!#5 N9690 P3482 BLD 6 -1 FP BE Pri
!#5 N9691 P3482 BLD 7 -1 FP BE Pri
!#5 N9692 P3483 MEMBAR
!#5 N9693 P3482 BLD 4 -1 FP BE Pri
!#5 N9694 P3482 BLD 5 -1 FP BE Pri
!#A N9693 N9694
!#5 N9695 P3482 BLD 6 -1 FP BE Pri
!#5 N9696 P3482 BLD 7 -1 FP BE Pri
!#5 N9697 P3483 MEMBAR
!#5 N9698 P3484 DWLD 20 -1 Int BE Pri
!#5 N9699 P3484 DWLD 21 -1 Int BE Pri
!#A N9698 N9699
!#5 N9700 P3485 DWLD 2 -1 FP BE Pri
!#5 N9701 P3486 BSTC 0 0x4200000d FP BE Pri
!#5 N9702 P3486 BSTC 1 0x4200000e FP BE Pri
!#A N9701 N9702
!#5 N9703 P3486 BSTC 2 0x4200000f FP BE Pri
!#5 N9704 P3486 BSTC 3 0x42000010 FP BE Pri
!#5 N9705 P3487 DWLD 4 -1 FP BE Pri
!#5 N9706 P3487 DWLD 5 -1 FP BE Pri
!#A N9705 N9706
!#5 N9707 P3488 DWLD 19 -1 Int BE Pri
!#5 N9708 P3489 BLD 24 -1 FP BE Pri
!#5 N9709 P3489 BLD 25 -1 FP BE Pri
!#A N9708 N9709
!#5 N9710 P3489 BLD 26 -1 FP BE Pri
!#5 N9711 P3489 BLD 27 -1 FP BE Pri
!#5 N9712 P3490 LD 19 -1 Int BE Pri
!#5 N9713 P3488 DWLD 19 -1 Int BE Pri
!#5 N9714 P3489 BLD 24 -1 FP BE Pri
!#5 N9715 P3489 BLD 25 -1 FP BE Pri
!#A N9714 N9715
!#5 N9716 P3489 BLD 26 -1 FP BE Pri
!#5 N9717 P3489 BLD 27 -1 FP BE Pri
!#5 N9718 P3490 LD 19 -1 Int BE Pri
!#5 N9719 P3491 LD 17 -1 Int BE Pri
!#5 N9720 P3492 LD 17 -1 Int BE Pri
!#5 N9721 P3493 BLD 24 -1 FP BE Pri
!#5 N9722 P3493 BLD 25 -1 FP BE Pri
!#A N9721 N9722
!#5 N9723 P3493 BLD 26 -1 FP BE Pri
!#5 N9724 P3493 BLD 27 -1 FP BE Pri
!#5 N9725 P3494 DWLD 0 -1 Int BE Pri
!#5 N9726 P3494 DWLD 1 -1 Int BE Pri
!#A N9725 N9726
!#5 N9727 P3493 BLD 24 -1 FP BE Pri
!#5 N9728 P3493 BLD 25 -1 FP BE Pri
!#A N9727 N9728
!#5 N9729 P3493 BLD 26 -1 FP BE Pri
!#5 N9730 P3493 BLD 27 -1 FP BE Pri
!#5 N9731 P3494 DWLD 0 -1 Int BE Pri
!#5 N9732 P3494 DWLD 1 -1 Int BE Pri
!#A N9731 N9732
!#5 N9733 P3495 DWLD 2 -1 Int BE Pri
!#5 N9734 P3496 LD 11 -1 Int BE Pri
!#5 N9735 P3495 DWLD 2 -1 Int BE Pri
!#5 N9736 P3496 LD 11 -1 Int BE Pri
!#5 N9737 P3497 LD 29 -1 Int BE Pri
!#5 N9738 P3498 LD 11 -1 FP BE Pri
!#5 N9739 P3499 LD 9 -1 Int BE Pri
!#5 N9740 P3500 BLD 20 -1 FP BE Pri
!#5 N9741 P3500 BLD 21 -1 FP BE Pri
!#A N9740 N9741
!#5 N9742 P3500 BLD 22 -1 FP BE Pri
!#5 N9743 P3500 BLD 23 -1 FP BE Pri
!#5 N9744 P3500 BLD 20 -1 FP BE Pri
!#5 N9745 P3500 BLD 21 -1 FP BE Pri
!#A N9744 N9745
!#5 N9746 P3500 BLD 22 -1 FP BE Pri
!#5 N9747 P3500 BLD 23 -1 FP BE Pri
!#5 N9748 P3501 LD 14 -1 FP BE Pri
!#5 N9749 P3502 LD 8 -1 Int BE Pri
!#5 N9750 P3503 LD 18 -1 Int BE Pri
!#5 N9751 P3501 LD 14 -1 FP BE Pri
!#5 N9752 P3502 LD 8 -1 Int BE Pri
!#5 N9753 P3503 LD 18 -1 Int BE Pri
!#5 N9754 P3504 DWLD 19 -1 Int BE Pri
!#5 N9755 P3505 LD 8 -1 Int LE Pri
!#5 N9756 P3504 DWLD 19 -1 Int BE Pri
!#5 N9757 P3505 LD 8 -1 Int LE Pri
!#5 N9758 P3506 MEMBAR
!#5 N9759 P3507 LD 28 -1 Int BE Pri
!#5 N9760 P3508 LD 29 -1 Int BE Pri
!#5 N9761 P3506 MEMBAR
!#5 N9762 P3507 LD 28 -1 Int BE Pri
!#5 N9763 P3508 LD 29 -1 Int BE Pri
!#5 N9764 P3509 LD 15 -1 Int BE Pri
!#5 N9765 P3510 LD 31 -1 Int BE Pri
!#5 N9766 P3509 LD 15 -1 Int BE Pri
!#5 N9767 P3510 LD 31 -1 Int BE Pri
!#5 N9768 P3511 DWLD 15 -1 Int BE Pri
!#5 N9769 P3512 LD 12 -1 Int BE Pri
!#5 N9770 P3511 DWLD 15 -1 Int BE Pri
!#5 N9771 P3512 LD 12 -1 Int BE Pri
!#5 N9772 P3513 DWLD 22 -1 Int BE Pri
!#5 N9773 P3514 LD 22 -1 Int BE Pri
!#5 N9774 P3515 LD 5 -1 Int BE Pri
!#5 N9775 P3516 DWLD 4 -1 Int BE Pri
!#5 N9776 P3516 DWLD 5 -1 Int BE Pri
!#A N9775 N9776
!#5 N9777 P3517 LD 2 -1 Int BE Pri
!#5 N9778 P3518 LD 23 -1 Int BE Pri
!#5 N9779 P3519 LD 2 -1 Int BE Pri
!#5 N9780 P3520 LD 31 -1 Int BE Pri
!#5 N9781 P3521 LD 20 -1 Int BE Pri
!#5 N9782 P3522 BLD 16 -1 FP BE Pri
!#5 N9783 P3522 BLD 17 -1 FP BE Pri
!#A N9782 N9783
!#5 N9784 P3522 BLD 18 -1 FP BE Pri
!#5 N9785 P3522 BLD 19 -1 FP BE Pri
!#5 N9786 P3523 BLD 20 -1 FP BE Pri
!#5 N9787 P3523 BLD 21 -1 FP BE Pri
!#A N9786 N9787
!#5 N9788 P3523 BLD 22 -1 FP BE Pri
!#5 N9789 P3523 BLD 23 -1 FP BE Pri
!#5 N9794 P3526 MEMBAR
!#5 N9795 P3526 MEMBAR
!#5 N9796 P3527 DWLD 24 -1 Int BE Pri
!#5 N9797 P3527 DWLD 25 -1 Int BE Pri
!#A N9796 N9797
!#5 N9798 P3528 LD 9 -1 Int BE Pri
!#5 N9799 P3529 LD 29 -1 Int BE Pri
!#5 N9800 P3528 LD 9 -1 Int BE Pri
!#5 N9801 P3529 LD 29 -1 Int BE Pri
!#5 N9803 P3531 DWLD 28 -1 Int BE Pri
!#5 N9804 P3531 DWLD 29 -1 Int BE Pri
!#A N9803 N9804
!#5 N9805 P3532 BLD 4 -1 FP BE Pri
!#5 N9806 P3532 BLD 5 -1 FP BE Pri
!#A N9805 N9806
!#5 N9807 P3532 BLD 6 -1 FP BE Pri
!#5 N9808 P3532 BLD 7 -1 FP BE Pri
!#5 N9809 P3531 DWLD 28 -1 Int BE Pri
!#5 N9810 P3531 DWLD 29 -1 Int BE Pri
!#A N9809 N9810
!#5 N9811 P3532 BLD 4 -1 FP BE Pri
!#5 N9812 P3532 BLD 5 -1 FP BE Pri
!#A N9811 N9812
!#5 N9813 P3532 BLD 6 -1 FP BE Pri
!#5 N9814 P3532 BLD 7 -1 FP BE Pri
!#5 N9815 P3533 BLD 24 -1 FP BE Pri
!#5 N9816 P3533 BLD 25 -1 FP BE Pri
!#A N9815 N9816
!#5 N9817 P3533 BLD 26 -1 FP BE Pri
!#5 N9818 P3533 BLD 27 -1 FP BE Pri
!#5 N9819 P3534 BSTC 4 0x42000011 FP BE Pri
!#5 N9820 P3534 BSTC 5 0x42000012 FP BE Pri
!#A N9819 N9820
!#5 N9821 P3534 BSTC 6 0x42000013 FP BE Pri
!#5 N9822 P3534 BSTC 7 0x42000014 FP BE Pri
!#5 N9823 P3533 BLD 24 -1 FP BE Pri
!#5 N9824 P3533 BLD 25 -1 FP BE Pri
!#A N9823 N9824
!#5 N9825 P3533 BLD 26 -1 FP BE Pri
!#5 N9826 P3533 BLD 27 -1 FP BE Pri
!#5 N9827 P3534 BSTC 4 0x42000015 FP BE Pri
!#5 N9828 P3534 BSTC 5 0x42000016 FP BE Pri
!#A N9827 N9828
!#5 N9829 P3534 BSTC 6 0x42000017 FP BE Pri
!#5 N9830 P3534 BSTC 7 0x42000018 FP BE Pri
!#5 N9831 P3535 BLD 12 -1 FP BE Pri
!#5 N9832 P3535 BLD 13 -1 FP BE Pri
!#A N9831 N9832
!#5 N9833 P3535 BLD 14 -1 FP BE Pri
!#5 N9834 P3535 BLD 15 -1 FP BE Pri
!#5 N9835 P3536 BLD 16 -1 FP BE Pri
!#5 N9836 P3536 BLD 17 -1 FP BE Pri
!#A N9835 N9836
!#5 N9837 P3536 BLD 18 -1 FP BE Pri
!#5 N9838 P3536 BLD 19 -1 FP BE Pri
!#5 N9839 P3535 BLD 12 -1 FP BE Pri
!#5 N9840 P3535 BLD 13 -1 FP BE Pri
!#A N9839 N9840
!#5 N9841 P3535 BLD 14 -1 FP BE Pri
!#5 N9842 P3535 BLD 15 -1 FP BE Pri
!#5 N9843 P3536 BLD 16 -1 FP BE Pri
!#5 N9844 P3536 BLD 17 -1 FP BE Pri
!#A N9843 N9844
!#5 N9845 P3536 BLD 18 -1 FP BE Pri
!#5 N9846 P3536 BLD 19 -1 FP BE Pri
!#5 N9847 P3537 BLD 28 -1 FP BE Pri
!#5 N9848 P3537 BLD 29 -1 FP BE Pri
!#A N9847 N9848
!#5 N9849 P3537 BLD 30 -1 FP BE Pri
!#5 N9850 P3537 BLD 31 -1 FP BE Pri
!#5 N9851 P3538 ST 13 0x2800016 Int LE Pri
!#5 N9852 P3539 BLD 4 -1 FP BE Pri
!#5 N9853 P3539 BLD 5 -1 FP BE Pri
!#A N9852 N9853
!#5 N9854 P3539 BLD 6 -1 FP BE Pri
!#5 N9855 P3539 BLD 7 -1 FP BE Pri
!#5 N9856 P3538 ST 13 0x2800017 Int LE Pri
!#5 N9857 P3539 BLD 4 -1 FP BE Pri
!#5 N9858 P3539 BLD 5 -1 FP BE Pri
!#A N9857 N9858
!#5 N9859 P3539 BLD 6 -1 FP BE Pri
!#5 N9860 P3539 BLD 7 -1 FP BE Pri
!#5 N9861 P3540 DWLD 28 -1 Int BE Pri
!#5 N9862 P3540 DWLD 29 -1 Int BE Pri
!#A N9861 N9862
!#5 N9863 P3541 BLD 16 -1 FP BE Pri
!#5 N9864 P3541 BLD 17 -1 FP BE Pri
!#A N9863 N9864
!#5 N9865 P3541 BLD 18 -1 FP BE Pri
!#5 N9866 P3541 BLD 19 -1 FP BE Pri
!#5 N9867 P3542 DWLD 2 -1 Int BE Pri
!#5 N9868 P3543 DWLD 4 -1 Int BE Pri
!#5 N9869 P3543 DWLD 5 -1 Int BE Pri
!#A N9868 N9869
!#5 N9870 P3544 LD 10 -1 Int BE Pri
!#5 N9871 P3545 BLD 12 -1 FP BE Pri
!#5 N9872 P3545 BLD 13 -1 FP BE Pri
!#A N9871 N9872
!#5 N9873 P3545 BLD 14 -1 FP BE Pri
!#5 N9874 P3545 BLD 15 -1 FP BE Pri
!#5 N9875 P3546 DWLD 27 -1 Int BE Pri
!#5 N9876 P3547 DWLD 2 -1 FP BE Pri
!#5 N9877 P3548 LD 24 -1 Int BE Pri
!#5 N9878 P3546 DWLD 27 -1 Int BE Pri
!#5 N9879 P3547 DWLD 2 -1 FP BE Pri
!#5 N9880 P3548 LD 24 -1 Int BE Pri
!#5 N9881 P3549 SWAP 10 0xffffffff 0x2800018 Int BE Pri
!#5 N9882 P3550 BLD 0 -1 FP BE Pri
!#5 N9883 P3550 BLD 1 -1 FP BE Pri
!#A N9882 N9883
!#5 N9884 P3550 BLD 2 -1 FP BE Pri
!#5 N9885 P3550 BLD 3 -1 FP BE Pri
!#5 N9886 P3551 LD 9 -1 Int BE Pri
!#5 N9887 P3549 SWAP 10 0xffffffff 0x2800019 Int BE Pri
!#5 N9888 P3550 BLD 0 -1 FP BE Pri
!#5 N9889 P3550 BLD 1 -1 FP BE Pri
!#A N9888 N9889
!#5 N9890 P3550 BLD 2 -1 FP BE Pri
!#5 N9891 P3550 BLD 3 -1 FP BE Pri
!#5 N9892 P3551 LD 9 -1 Int BE Pri
!#5 N9893 P3552 LD 20 -1 Int BE Pri
!#5 N9894 P3553 LD 19 -1 Int BE Pri
!#5 N9895 P3552 LD 20 -1 Int BE Pri
!#5 N9896 P3553 LD 19 -1 Int BE Pri
!#5 N9897 P3554 BLD 12 -1 FP BE Pri
!#5 N9898 P3554 BLD 13 -1 FP BE Pri
!#A N9897 N9898
!#5 N9899 P3554 BLD 14 -1 FP BE Pri
!#5 N9900 P3554 BLD 15 -1 FP BE Pri
!#5 N9901 P3555 DWLD 7 -1 Int BE Pri
!#5 N9902 P3556 LD 9 -1 Int BE Pri
!#5 N9903 P3557 DWLD 8 -1 Int BE Pri
!#5 N9904 P3557 DWLD 9 -1 Int BE Pri
!#A N9903 N9904
!#5 N9905 P3557 DWLD 8 -1 Int BE Pri
!#5 N9906 P3557 DWLD 9 -1 Int BE Pri
!#A N9905 N9906
!#5 N9907 P3558 LD 1 -1 Int BE Pri
!#5 N9908 P3559 LD 17 -1 Int LE Pri
!#5 N9909 P3558 LD 1 -1 Int BE Pri
!#5 N9910 P3559 LD 17 -1 Int LE Pri
!#5 N9913 P3561 DWLD 28 -1 Int BE Pri
!#5 N9914 P3561 DWLD 29 -1 Int BE Pri
!#A N9913 N9914
!#5 N9915 P3562 BLD 8 -1 FP BE Pri
!#5 N9916 P3562 BLD 9 -1 FP BE Pri
!#A N9915 N9916
!#5 N9917 P3562 BLD 10 -1 FP BE Pri
!#5 N9918 P3562 BLD 11 -1 FP BE Pri
!#5 N9919 P3561 DWLD 28 -1 Int BE Pri
!#5 N9920 P3561 DWLD 29 -1 Int BE Pri
!#A N9919 N9920
!#5 N9921 P3562 BLD 8 -1 FP BE Pri
!#5 N9922 P3562 BLD 9 -1 FP BE Pri
!#A N9921 N9922
!#5 N9923 P3562 BLD 10 -1 FP BE Pri
!#5 N9924 P3562 BLD 11 -1 FP BE Pri
!#5 N9925 P3563 LD 26 -1 Int BE Pri
!#5 N9926 P3564 LD 23 -1 Int BE Pri
!#5 N9927 P3563 LD 26 -1 Int BE Pri
!#5 N9928 P3564 LD 23 -1 Int BE Pri
!#5 N9929 P3565 DWLD 26 -1 Int BE Pri
!#5 N9930 P3566 LD 16 -1 Int BE Pri
!#5 N9931 P3565 DWLD 26 -1 Int BE Pri
!#5 N9932 P3566 LD 16 -1 Int BE Pri
!#5 N9933 P3567 BLD 8 -1 FP BE Pri
!#5 N9934 P3567 BLD 9 -1 FP BE Pri
!#A N9933 N9934
!#5 N9935 P3567 BLD 10 -1 FP BE Pri
!#5 N9936 P3567 BLD 11 -1 FP BE Pri
!#5 N9937 P3568 BLD 16 -1 FP BE Pri
!#5 N9938 P3568 BLD 17 -1 FP BE Pri
!#A N9937 N9938
!#5 N9939 P3568 BLD 18 -1 FP BE Pri
!#5 N9940 P3568 BLD 19 -1 FP BE Pri
!#5 N9941 P3569 BLD 16 -1 FP BE Pri
!#5 N9942 P3569 BLD 17 -1 FP BE Pri
!#A N9941 N9942
!#5 N9943 P3569 BLD 18 -1 FP BE Pri
!#5 N9944 P3569 BLD 19 -1 FP BE Pri
!#5 N9945 P3569 BLD 16 -1 FP BE Pri
!#5 N9946 P3569 BLD 17 -1 FP BE Pri
!#A N9945 N9946
!#5 N9947 P3569 BLD 18 -1 FP BE Pri
!#5 N9948 P3569 BLD 19 -1 FP BE Pri
!#5 N9949 P3570 BLD 20 -1 FP BE Pri
!#5 N9950 P3570 BLD 21 -1 FP BE Pri
!#A N9949 N9950
!#5 N9951 P3570 BLD 22 -1 FP BE Pri
!#5 N9952 P3570 BLD 23 -1 FP BE Pri
!#5 N9953 P3571 BLD 0 -1 FP BE Pri
!#5 N9954 P3571 BLD 1 -1 FP BE Pri
!#A N9953 N9954
!#5 N9955 P3571 BLD 2 -1 FP BE Pri
!#5 N9956 P3571 BLD 3 -1 FP BE Pri
!#5 N9957 P3572 BLD 8 -1 FP BE Pri
!#5 N9958 P3572 BLD 9 -1 FP BE Pri
!#A N9957 N9958
!#5 N9959 P3572 BLD 10 -1 FP BE Pri
!#5 N9960 P3572 BLD 11 -1 FP BE Pri
!#5 N9962 P3574 DWLD 14 -1 Int BE Pri
!#5 N9963 P3575 BLD 12 -1 FP BE Pri
!#5 N9964 P3575 BLD 13 -1 FP BE Pri
!#A N9963 N9964
!#5 N9965 P3575 BLD 14 -1 FP BE Pri
!#5 N9966 P3575 BLD 15 -1 FP BE Pri
!#5 N9967 P3576 LD 1 -1 Int BE Pri
!#5 N9968 P3577 DWLD 18 -1 Int BE Pri
!#5 N9969 P3578 LD 26 -1 Int BE Pri
!#5 N9970 P3579 LD 5 -1 Int BE Pri
!#5 N9971 P3580 SWAP 31 0xffffffff 0x280001a Int BE Pri
!#5 N9972 P3579 LD 5 -1 Int BE Pri
!#5 N9973 P3580 SWAP 31 0xffffffff 0x280001b Int BE Pri
!#5 N9975 P3582 BLD 28 -1 FP BE Pri
!#5 N9976 P3582 BLD 29 -1 FP BE Pri
!#A N9975 N9976
!#5 N9977 P3582 BLD 30 -1 FP BE Pri
!#5 N9978 P3582 BLD 31 -1 FP BE Pri
!#5 N9979 P3583 LD 8 -1 Int BE Pri
!#5 N9980 P3584 LD 18 -1 Int BE Pri
!#5 N9981 P3583 LD 8 -1 Int BE Pri
!#5 N9982 P3584 LD 18 -1 Int BE Pri
!#5 N9983 P3585 LD 14 -1 Int BE Pri
!#5 N9984 P3586 LD 21 -1 Int BE Pri
!#5 N9985 P3585 LD 14 -1 Int BE Pri
!#5 N9986 P3586 LD 21 -1 Int BE Pri
!#5 N9987 P3587 LD 12 -1 Int BE Pri
!#5 N9988 P3588 LD 9 -1 Int BE Pri
!#5 N9989 P3587 LD 12 -1 Int BE Pri
!#5 N9990 P3588 LD 9 -1 Int BE Pri
!#5 N9991 P3589 DWLD 30 -1 Int BE Pri
!#5 N9992 P3590 LD 22 -1 Int BE Pri
!#5 N9993 P3591 DWLD 15 -1 Int BE Pri
!#5 N9994 P3592 BLD 12 -1 FP BE Pri
!#5 N9995 P3592 BLD 13 -1 FP BE Pri
!#A N9994 N9995
!#5 N9996 P3592 BLD 14 -1 FP BE Pri
!#5 N9997 P3592 BLD 15 -1 FP BE Pri
!#5 N9998 P3593 LD 20 -1 Int BE Pri
!#5 N9999 P3594 BLD 8 -1 FP BE Pri
!#5 N10000 P3594 BLD 9 -1 FP BE Pri
!#A N9999 N10000
!#5 N10001 P3594 BLD 10 -1 FP BE Pri
!#5 N10002 P3594 BLD 11 -1 FP BE Pri
!#5 N10003 P3595 DWLD 2 -1,0x0 Int BE Pri
!#5 N10004 P3595 CASX 2 -1,0x0 N10003 0x280001c Int BE Pri
!#5 N10005 P3595 DWLD 2 -1,0x0 Int BE Pri
!#5 N10006 P3595 CASX 2 -1,0x0 N10005 0x280001d Int BE Pri
!#5 N10007 P3596 DWLD 15 -1 Int BE Pri
!#5 N10008 P3597 DWLD 11 -1 Int BE Pri
!#5 N10009 P3598 LD 27 -1 FP BE Pri
!#5 N10010 P3599 DWLD 12 -1 Int BE Pri
!#5 N10011 P3599 DWLD 13 -1 Int BE Pri
!#A N10010 N10011
!#5 N10012 P3600 BLD 20 -1 FP BE Pri
!#5 N10013 P3600 BLD 21 -1 FP BE Pri
!#A N10012 N10013
!#5 N10014 P3600 BLD 22 -1 FP BE Pri
!#5 N10015 P3600 BLD 23 -1 FP BE Pri
!#5 N10016 P3600 BLD 20 -1 FP BE Pri
!#5 N10017 P3600 BLD 21 -1 FP BE Pri
!#A N10016 N10017
!#5 N10018 P3600 BLD 22 -1 FP BE Pri
!#5 N10019 P3600 BLD 23 -1 FP BE Pri
!#5 N10020 P3601 DWLD 4 -1 Int BE Pri
!#5 N10021 P3601 DWLD 5 -1 Int BE Pri
!#A N10020 N10021
!#5 N10022 P3602 BST 24 0x42000019 FP BE Pri
!#5 N10023 P3602 BST 25 0x4200001a FP BE Pri
!#A N10022 N10023
!#5 N10024 P3602 BST 26 0x4200001b FP BE Pri
!#5 N10025 P3602 BST 27 0x4200001c FP BE Pri
!#5 N10026 P3603 LD 25 -1 Int BE Pri
!#5 N10027 P3604 BLD 12 -1 FP BE Pri
!#5 N10028 P3604 BLD 13 -1 FP BE Pri
!#A N10027 N10028
!#5 N10029 P3604 BLD 14 -1 FP BE Pri
!#5 N10030 P3604 BLD 15 -1 FP BE Pri
!#5 N10031 P3605 LD 2 -1 Int BE Pri
!#5 N10032 P3603 LD 25 -1 Int BE Pri
!#5 N10033 P3604 BLD 12 -1 FP BE Pri
!#5 N10034 P3604 BLD 13 -1 FP BE Pri
!#A N10033 N10034
!#5 N10035 P3604 BLD 14 -1 FP BE Pri
!#5 N10036 P3604 BLD 15 -1 FP BE Pri
!#5 N10037 P3605 LD 2 -1 Int BE Pri
!#5 N10038 P3606 BLD 16 -1 FP BE Pri
!#5 N10039 P3606 BLD 17 -1 FP BE Pri
!#A N10038 N10039
!#5 N10040 P3606 BLD 18 -1 FP BE Pri
!#5 N10041 P3606 BLD 19 -1 FP BE Pri
!#5 N10042 P3606 BLD 16 -1 FP BE Pri
!#5 N10043 P3606 BLD 17 -1 FP BE Pri
!#A N10042 N10043
!#5 N10044 P3606 BLD 18 -1 FP BE Pri
!#5 N10045 P3606 BLD 19 -1 FP BE Pri
!#5 N10046 P3607 DWLD 16 -1 Int BE Pri
!#5 N10047 P3607 DWLD 17 -1 Int BE Pri
!#A N10046 N10047
!#5 N10048 P3607 DWLD 16 -1 Int BE Pri
!#5 N10049 P3607 DWLD 17 -1 Int BE Pri
!#A N10048 N10049
!#5 N10050 P3608 DWLD 8 -1 Int BE Pri
!#5 N10051 P3608 DWLD 9 -1 Int BE Pri
!#A N10050 N10051
!#5 N10052 P3608 DWLD 8 -1 Int BE Pri
!#5 N10053 P3608 DWLD 9 -1 Int BE Pri
!#A N10052 N10053
!#5 N10054 P3609 DWLD 0 -1 Int BE Pri
!#5 N10055 P3609 DWLD 1 -1 Int BE Pri
!#A N10054 N10055
!#5 N10056 P3609 CASX 0 -1 N10054 0x280001e Int BE Pri
!#5 N10057 P3609 CASX 1 -1 N10055 0x280001f Int BE Pri
!#A N10056 N10057
!#5 N10058 P3610 LD 14 -1 FP BE Pri
!#5 N10059 P3610 LD 14 -1 FP BE Pri
!#5 N10060 P3611 LD 0 -1 Int BE Pri
!#5 N10062 P3613 LD 2 -1 Int BE Pri
!#5 N10063 P3611 LD 0 -1 Int BE Pri
!#5 N10065 P3613 LD 2 -1 Int BE Pri
!#5 N10066 P3614 LD 16 -1 Int BE Pri
!#5 N10067 P3615 LD 19 -1 Int BE Pri
!#5 N10068 P3616 LD 11 -1 Int BE Pri
!#5 N10069 P3616 CAS 11 -1 N10068 0x2800020 Int BE Pri
!#5 N10070 P3617 BLD 12 -1 FP BE Pri
!#5 N10071 P3617 BLD 13 -1 FP BE Pri
!#A N10070 N10071
!#5 N10072 P3617 BLD 14 -1 FP BE Pri
!#5 N10073 P3617 BLD 15 -1 FP BE Pri
!#5 N10074 P3618 BLD 16 -1 FP BE Pri
!#5 N10075 P3618 BLD 17 -1 FP BE Pri
!#A N10074 N10075
!#5 N10076 P3618 BLD 18 -1 FP BE Pri
!#5 N10077 P3618 BLD 19 -1 FP BE Pri
!#5 N10078 P3619 DWLD 16 -1 Int BE Pri
!#5 N10079 P3619 DWLD 17 -1 Int BE Pri
!#A N10078 N10079
!#5 N10080 P3618 BLD 16 -1 FP BE Pri
!#5 N10081 P3618 BLD 17 -1 FP BE Pri
!#A N10080 N10081
!#5 N10082 P3618 BLD 18 -1 FP BE Pri
!#5 N10083 P3618 BLD 19 -1 FP BE Pri
!#5 N10084 P3619 DWLD 16 -1 Int BE Pri
!#5 N10085 P3619 DWLD 17 -1 Int BE Pri
!#A N10084 N10085
!#5 N10086 P3620 DWLD 16 -1 Int BE Pri
!#5 N10087 P3620 DWLD 17 -1 Int BE Pri
!#A N10086 N10087
!#5 N10088 P3621 DWLD 0 -1 Int BE Pri
!#5 N10089 P3621 DWLD 1 -1 Int BE Pri
!#A N10088 N10089
!#5 N10090 P3622 LD 21 -1 Int BE Pri
!#5 N10091 P3623 LD 18 -1 Int BE Pri
!#5 N10092 P3622 LD 21 -1 Int BE Pri
!#5 N10093 P3623 LD 18 -1 Int BE Pri
!#5 N10096 P3625 LD 10 -1 Int BE Pri
!#5 N10097 P3625 CAS 10 -1 N10096 0x2800021 Int BE Pri
!#5 N10098 P3625 LD 10 -1 Int BE Pri
!#5 N10099 P3625 CAS 10 -1 N10098 0x2800022 Int BE Pri
!#5 N10100 P3626 DWLD 15 -1 Int BE Pri
!#5 N10101 P3627 LD 18 -1 Int BE Pri
!#5 N10102 P3628 DWLD 11 -1 FP BE Pri
!#5 N10103 P3629 DWLD 27 -1 Int BE Pri
!#5 N10104 P3630 MEMBAR
!#5 N10105 P3631 LD 2 -1 Int BE Pri
!#5 N10106 P3632 LD 31 -1 Int BE Pri
!#5 N10107 P3633 LD 16 -1 Int BE Pri
!#5 N10110 P3636 BLD 8 -1 FP BE Pri
!#5 N10111 P3636 BLD 9 -1 FP BE Pri
!#A N10110 N10111
!#5 N10112 P3636 BLD 10 -1 FP BE Pri
!#5 N10113 P3636 BLD 11 -1 FP BE Pri
!#5 N10114 P3637 DWLD 24 -1 Int BE Pri
!#5 N10115 P3637 DWLD 25 -1 Int BE Pri
!#A N10114 N10115
!#5 N10116 P3636 BLD 8 -1 FP BE Pri
!#5 N10117 P3636 BLD 9 -1 FP BE Pri
!#A N10116 N10117
!#5 N10118 P3636 BLD 10 -1 FP BE Pri
!#5 N10119 P3636 BLD 11 -1 FP BE Pri
!#5 N10120 P3637 DWLD 24 -1 Int BE Pri
!#5 N10121 P3637 DWLD 25 -1 Int BE Pri
!#A N10120 N10121
!#5 N10122 P3638 LD 31 -1 Int BE Pri
!#5 N10123 P3639 LD 0 -1 Int BE Pri
!#5 N10124 P3640 BLD 0 -1 FP BE Pri
!#5 N10125 P3640 BLD 1 -1 FP BE Pri
!#A N10124 N10125
!#5 N10126 P3640 BLD 2 -1 FP BE Pri
!#5 N10127 P3640 BLD 3 -1 FP BE Pri
!#5 N10128 P3641 BLD 16 -1 FP BE Pri
!#5 N10129 P3641 BLD 17 -1 FP BE Pri
!#A N10128 N10129
!#5 N10130 P3641 BLD 18 -1 FP BE Pri
!#5 N10131 P3641 BLD 19 -1 FP BE Pri
!#5 N10132 P3641 BLD 16 -1 FP BE Pri
!#5 N10133 P3641 BLD 17 -1 FP BE Pri
!#A N10132 N10133
!#5 N10134 P3641 BLD 18 -1 FP BE Pri
!#5 N10135 P3641 BLD 19 -1 FP BE Pri
!#5 N10136 P3642 BLD 24 -1 FP BE Pri
!#5 N10137 P3642 BLD 25 -1 FP BE Pri
!#A N10136 N10137
!#5 N10138 P3642 BLD 26 -1 FP BE Pri
!#5 N10139 P3642 BLD 27 -1 FP BE Pri
!#5 N10140 P3643 BLD 20 -1 FP BE Pri
!#5 N10141 P3643 BLD 21 -1 FP BE Pri
!#A N10140 N10141
!#5 N10142 P3643 BLD 22 -1 FP BE Pri
!#5 N10143 P3643 BLD 23 -1 FP BE Pri
!#5 N10144 P3644 LD 13 -1 Int BE Pri
!#5 N10145 P3645 LD 28 -1 Int BE Pri
!#5 N10146 P3643 BLD 20 -1 FP BE Pri
!#5 N10147 P3643 BLD 21 -1 FP BE Pri
!#A N10146 N10147
!#5 N10148 P3643 BLD 22 -1 FP BE Pri
!#5 N10149 P3643 BLD 23 -1 FP BE Pri
!#5 N10150 P3644 LD 13 -1 Int BE Pri
!#5 N10151 P3645 LD 28 -1 Int BE Pri
!#5 N10152 P3646 DWLD 15 -1 Int BE Pri
!#5 N10153 P3647 LD 22 -1 Int BE Pri
!#5 N10154 P3646 DWLD 15 -1 Int BE Pri
!#5 N10155 P3647 LD 22 -1 Int BE Pri
!#5 N10156 P3648 BLD 20 -1 FP BE Pri
!#5 N10157 P3648 BLD 21 -1 FP BE Pri
!#A N10156 N10157
!#5 N10158 P3648 BLD 22 -1 FP BE Pri
!#5 N10159 P3648 BLD 23 -1 FP BE Pri
!#5 N10160 P3649 DWLD 10 -1 Int BE Pri
!#5 N10161 P3650 LD 26 -1 Int BE Pri
!#5 N10162 P3648 BLD 20 -1 FP BE Pri
!#5 N10163 P3648 BLD 21 -1 FP BE Pri
!#A N10162 N10163
!#5 N10164 P3648 BLD 22 -1 FP BE Pri
!#5 N10165 P3648 BLD 23 -1 FP BE Pri
!#5 N10166 P3649 DWLD 10 -1 Int BE Pri
!#5 N10167 P3650 LD 26 -1 Int BE Pri
!#5 N10168 P3651 BLD 0 -1 FP BE Pri
!#5 N10169 P3651 BLD 1 -1 FP BE Pri
!#A N10168 N10169
!#5 N10170 P3651 BLD 2 -1 FP BE Pri
!#5 N10171 P3651 BLD 3 -1 FP BE Pri
!#5 N10172 P3652 DWLD 0 -1 Int BE Pri
!#5 N10173 P3652 DWLD 1 -1 Int BE Pri
!#A N10172 N10173
!#5 N10174 P3653 LD 21 -1 FP BE Pri
!#5 N10175 P3653 LD 21 -1 FP BE Pri
!#5 N10176 P3654 DWLD 23 -1 Int BE Pri
!#5 N10177 P3655 LD 30 -1 Int BE Pri
!#5 N10178 P3654 DWLD 23 -1 Int BE Pri
!#5 N10179 P3655 LD 30 -1 Int BE Pri
!#5 N10180 P3656 LD 27 -1 Int BE Pri
!#5 N10181 P3657 LD 13 -1 Int BE Pri
!#5 N10182 P3658 LD 25 -1 Int BE Pri
!#5 N10183 P3659 LD 23 -1 Int BE Pri
!#5 N10184 P3658 LD 25 -1 Int BE Pri
!#5 N10185 P3659 LD 23 -1 Int BE Pri
!#5 N10187 P3661 DWLD 23 -1 Int BE Pri
!#5 N10188 P3662 LD 24 -1 Int BE Pri
!#5 N10189 P3663 LD 0 -1 Int BE Pri
!#5 N10190 P3664 DWLD 4 -1 Int BE Pri
!#5 N10191 P3664 DWLD 5 -1 Int BE Pri
!#A N10190 N10191
!#5 N10192 P3665 LD 20 -1 Int BE Pri
!#5 N10193 P3666 DWLD 28 -1 Int BE Pri
!#5 N10194 P3666 DWLD 29 -1 Int BE Pri
!#A N10193 N10194
!#5 N10195 P3667 DWLD 24 -1 Int BE Pri
!#5 N10196 P3667 DWLD 25 -1 Int BE Pri
!#A N10195 N10196
!#5 N10197 P3666 DWLD 28 -1 Int BE Pri
!#5 N10198 P3666 DWLD 29 -1 Int BE Pri
!#A N10197 N10198
!#5 N10199 P3667 DWLD 24 -1 Int BE Pri
!#5 N10200 P3667 DWLD 25 -1 Int BE Pri
!#A N10199 N10200
!#5 N10201 P3668 LD 19 -1 Int BE Pri
!#5 N10202 P3669 DWLD 4 -1 Int BE Pri
!#5 N10203 P3669 DWLD 5 -1 Int BE Pri
!#A N10202 N10203
!#5 N10204 P3670 LD 0 -1 Int BE Pri
!#5 N10205 P3671 BLD 24 -1 FP BE Pri
!#5 N10206 P3671 BLD 25 -1 FP BE Pri
!#A N10205 N10206
!#5 N10207 P3671 BLD 26 -1 FP BE Pri
!#5 N10208 P3671 BLD 27 -1 FP BE Pri
!#5 N10209 P3671 BLD 24 -1 FP BE Pri
!#5 N10210 P3671 BLD 25 -1 FP BE Pri
!#A N10209 N10210
!#5 N10211 P3671 BLD 26 -1 FP BE Pri
!#5 N10212 P3671 BLD 27 -1 FP BE Pri
!#5 N10213 P3672 BLD 24 -1 FP BE Pri
!#5 N10214 P3672 BLD 25 -1 FP BE Pri
!#A N10213 N10214
!#5 N10215 P3672 BLD 26 -1 FP BE Pri
!#5 N10216 P3672 BLD 27 -1 FP BE Pri
!#5 N10217 P3673 BLD 28 -1 FP BE Pri
!#5 N10218 P3673 BLD 29 -1 FP BE Pri
!#A N10217 N10218
!#5 N10219 P3673 BLD 30 -1 FP BE Pri
!#5 N10220 P3673 BLD 31 -1 FP BE Pri
!#5 N10221 P3674 BLD 16 -1 FP BE Pri
!#5 N10222 P3674 BLD 17 -1 FP BE Pri
!#A N10221 N10222
!#5 N10223 P3674 BLD 18 -1 FP BE Pri
!#5 N10224 P3674 BLD 19 -1 FP BE Pri
!#5 N10225 P3675 LD 19 -1 Int BE Pri
!#5 N10226 P3676 LD 7 -1 Int BE Pri
!#5 N10227 P3675 LD 19 -1 Int BE Pri
!#5 N10228 P3676 LD 7 -1 Int BE Pri
!#5 N10229 P3677 LD 20 -1 FP BE Pri
!#5 N10230 P3678 LD 15 -1 FP BE Pri
!#5 N10231 P3679 DWLD 26 -1 Int BE Pri
!#5 N10232 P3680 LD 19 -1 Int BE Pri
!#5 N10233 P3679 DWLD 26 -1 Int BE Pri
!#5 N10234 P3680 LD 19 -1 Int BE Pri
!#5 N10235 P3681 LD 1 -1 Int BE Pri
!#5 N10236 P3682 LD 27 -1 Int BE Pri
!#5 N10237 P3681 LD 1 -1 Int BE Pri
!#5 N10238 P3682 LD 27 -1 Int BE Pri
!#5 N10239 P3683 LD 11 -1 Int BE Pri
!#5 N10240 P3684 BLD 0 -1 FP BE Pri
!#5 N10241 P3684 BLD 1 -1 FP BE Pri
!#A N10240 N10241
!#5 N10242 P3684 BLD 2 -1 FP BE Pri
!#5 N10243 P3684 BLD 3 -1 FP BE Pri
!#5 N10244 P3685 LD 22 -1 Int BE Pri
!#5 N10245 P3686 BLD 4 -1 FP BE Pri
!#5 N10246 P3686 BLD 5 -1 FP BE Pri
!#A N10245 N10246
!#5 N10247 P3686 BLD 6 -1 FP BE Pri
!#5 N10248 P3686 BLD 7 -1 FP BE Pri
!#5 N10249 P3687 LD 13 -1 Int BE Pri
!#5 N10250 P3688 LD 26 -1 Int BE Pri
!#5 N10251 P3686 BLD 4 -1 FP BE Pri
!#5 N10252 P3686 BLD 5 -1 FP BE Pri
!#A N10251 N10252
!#5 N10253 P3686 BLD 6 -1 FP BE Pri
!#5 N10254 P3686 BLD 7 -1 FP BE Pri
!#5 N10255 P3687 LD 13 -1 Int BE Pri
!#5 N10256 P3688 LD 26 -1 Int BE Pri
!#5 N10257 P3689 BLD 12 -1 FP BE Pri
!#5 N10258 P3689 BLD 13 -1 FP BE Pri
!#A N10257 N10258
!#5 N10259 P3689 BLD 14 -1 FP BE Pri
!#5 N10260 P3689 BLD 15 -1 FP BE Pri
!#5 N10261 P3690 LD 26 -1 Int BE Pri
!#5 N10262 P3691 LD 4 -1 Int LE Pri
!#5 N10263 P3692 LD 27 -1 Int BE Pri
!#5 N10264 P3693 LD 25 -1 Int BE Pri
!#5 N10266 P3695 DWLD 2 -1 Int BE Pri
!#5 N10267 P3696 LD 2 -1 Int BE Pri
!#5 N10268 P3697 ST 9 0x2800023 Int BE Pri
!#5 N10270 P3697 ST 9 0x2800024 Int BE Pri
!#5 N10272 P3699 DWLD 0 -1 Int BE Pri
!#5 N10273 P3699 DWLD 1 -1 Int BE Pri
!#A N10272 N10273
!#5 N10274 P3700 BLD 8 -1 FP BE Pri
!#5 N10275 P3700 BLD 9 -1 FP BE Pri
!#A N10274 N10275
!#5 N10276 P3700 BLD 10 -1 FP BE Pri
!#5 N10277 P3700 BLD 11 -1 FP BE Pri
!#5 N10278 P3699 DWLD 0 -1 Int BE Pri
!#5 N10279 P3699 DWLD 1 -1 Int BE Pri
!#A N10278 N10279
!#5 N10280 P3700 BLD 8 -1 FP BE Pri
!#5 N10281 P3700 BLD 9 -1 FP BE Pri
!#A N10280 N10281
!#5 N10282 P3700 BLD 10 -1 FP BE Pri
!#5 N10283 P3700 BLD 11 -1 FP BE Pri
!#5 N10284 P3701 BLD 12 -1 FP BE Pri
!#5 N10285 P3701 BLD 13 -1 FP BE Pri
!#A N10284 N10285
!#5 N10286 P3701 BLD 14 -1 FP BE Pri
!#5 N10287 P3701 BLD 15 -1 FP BE Pri
!#5 N10288 P3702 DWLD 4 -1 Int LE Pri
!#5 N10289 P3702 DWLD 5 -1 Int LE Pri
!#A N10288 N10289
!#5 N10290 P3703 DWLD 16 -1 Int BE Pri
!#5 N10291 P3703 DWLD 17 -1 Int BE Pri
!#A N10290 N10291
!#5 N10292 P3704 DWLD 24 -1 Int BE Pri
!#5 N10293 P3704 DWLD 25 -1 Int BE Pri
!#A N10292 N10293
!#5 N10294 P3705 DWLD 12 -1 Int BE Pri
!#5 N10295 P3705 DWLD 13 -1 Int BE Pri
!#A N10294 N10295
!#5 N10296 P3706 DWLD 26 -1 Int BE Pri
!#5 N10297 P3707 LD 26 -1 Int BE Pri
!#5 N10298 P3708 DWLD 12 -1 Int BE Pri
!#5 N10299 P3708 DWLD 13 -1 Int BE Pri
!#A N10298 N10299
!#5 N10300 P3709 BLD 20 -1 FP BE Pri
!#5 N10301 P3709 BLD 21 -1 FP BE Pri
!#A N10300 N10301
!#5 N10302 P3709 BLD 22 -1 FP BE Pri
!#5 N10303 P3709 BLD 23 -1 FP BE Pri
!#5 N10304 P3708 DWLD 12 -1 Int BE Pri
!#5 N10305 P3708 DWLD 13 -1 Int BE Pri
!#A N10304 N10305
!#5 N10306 P3709 BLD 20 -1 FP BE Pri
!#5 N10307 P3709 BLD 21 -1 FP BE Pri
!#A N10306 N10307
!#5 N10308 P3709 BLD 22 -1 FP BE Pri
!#5 N10309 P3709 BLD 23 -1 FP BE Pri
!#5 N10310 P3710 LD 28 -1 Int BE Pri
!#5 N10312 P3712 LD 26 -1 Int BE Pri
!#5 N10313 P3713 BLD 20 -1 FP BE Pri
!#5 N10314 P3713 BLD 21 -1 FP BE Pri
!#A N10313 N10314
!#5 N10315 P3713 BLD 22 -1 FP BE Pri
!#5 N10316 P3713 BLD 23 -1 FP BE Pri
!#5 N10317 P3714 DWLD 7 -1 Int BE Pri
!#5 N10318 P3715 LD 29 -1 Int BE Pri
!#5 N10319 P3716 BLD 28 -1 FP BE Pri
!#5 N10320 P3716 BLD 29 -1 FP BE Pri
!#A N10319 N10320
!#5 N10321 P3716 BLD 30 -1 FP BE Pri
!#5 N10322 P3716 BLD 31 -1 FP BE Pri
!#5 N10323 P3717 BLD 20 -1 FP BE Pri
!#5 N10324 P3717 BLD 21 -1 FP BE Pri
!#A N10323 N10324
!#5 N10325 P3717 BLD 22 -1 FP BE Pri
!#5 N10326 P3717 BLD 23 -1 FP BE Pri
!#5 N10327 P3716 BLD 28 -1 FP BE Pri
!#5 N10328 P3716 BLD 29 -1 FP BE Pri
!#A N10327 N10328
!#5 N10329 P3716 BLD 30 -1 FP BE Pri
!#5 N10330 P3716 BLD 31 -1 FP BE Pri
!#5 N10331 P3717 BLD 20 -1 FP BE Pri
!#5 N10332 P3717 BLD 21 -1 FP BE Pri
!#A N10331 N10332
!#5 N10333 P3717 BLD 22 -1 FP BE Pri
!#5 N10334 P3717 BLD 23 -1 FP BE Pri
!#5 N10335 P3718 LD 10 -1 Int BE Pri
!#5 N10336 P3719 DWLD 14 -1 Int BE Pri
!#5 N10337 P3720 BLD 0 -1 FP BE Pri
!#5 N10338 P3720 BLD 1 -1 FP BE Pri
!#A N10337 N10338
!#5 N10339 P3720 BLD 2 -1 FP BE Pri
!#5 N10340 P3720 BLD 3 -1 FP BE Pri
!#5 N10341 P3720 BLD 0 -1 FP BE Pri
!#5 N10342 P3720 BLD 1 -1 FP BE Pri
!#A N10341 N10342
!#5 N10343 P3720 BLD 2 -1 FP BE Pri
!#5 N10344 P3720 BLD 3 -1 FP BE Pri
!#5 N10345 P3721 BLD 4 -1 FP BE Pri
!#5 N10346 P3721 BLD 5 -1 FP BE Pri
!#A N10345 N10346
!#5 N10347 P3721 BLD 6 -1 FP BE Pri
!#5 N10348 P3721 BLD 7 -1 FP BE Pri
!#5 N10349 P3722 BST 20 0x4200001d FP BE Pri
!#5 N10350 P3722 BST 21 0x4200001e FP BE Pri
!#A N10349 N10350
!#5 N10351 P3722 BST 22 0x4200001f FP BE Pri
!#5 N10352 P3722 BST 23 0x42000020 FP BE Pri
!#5 N10353 P3723 DWLD 16 -1 Int BE Pri
!#5 N10354 P3723 DWLD 17 -1 Int BE Pri
!#A N10353 N10354
!#5 N10355 P3724 LD 24 -1 Int BE Pri
!#5 N10356 P3725 LD 27 -1 Int BE Pri
!#5 N10357 P3726 LD 31 -1 Int BE Pri
!#5 N10358 P3727 LD 21 -1 Int BE Pri
!#5 N10359 P3728 DWLD 24 -1 Int BE Pri
!#5 N10360 P3728 DWLD 25 -1 Int BE Pri
!#A N10359 N10360
!#5 N10361 P3729 BLD 16 -1 FP BE Pri
!#5 N10362 P3729 BLD 17 -1 FP BE Pri
!#A N10361 N10362
!#5 N10363 P3729 BLD 18 -1 FP BE Pri
!#5 N10364 P3729 BLD 19 -1 FP BE Pri
!#5 N10365 P3729 BLD 16 -1 FP BE Pri
!#5 N10366 P3729 BLD 17 -1 FP BE Pri
!#A N10365 N10366
!#5 N10367 P3729 BLD 18 -1 FP BE Pri
!#5 N10368 P3729 BLD 19 -1 FP BE Pri
!#5 N10369 P3730 DWLD 28 -1 Int BE Pri
!#5 N10370 P3730 DWLD 29 -1 Int BE Pri
!#A N10369 N10370
!#5 N10371 P3731 BLD 16 -1 FP BE Pri
!#5 N10372 P3731 BLD 17 -1 FP BE Pri
!#A N10371 N10372
!#5 N10373 P3731 BLD 18 -1 FP BE Pri
!#5 N10374 P3731 BLD 19 -1 FP BE Pri
!#5 N10375 P3732 LD 28 -1 Int BE Pri
!#5 N10376 P3732 CAS 28 -1 N10375 0x2800025 Int BE Pri
!#5 N10377 P3733 BLD 0 -1 FP BE Pri
!#5 N10378 P3733 BLD 1 -1 FP BE Pri
!#A N10377 N10378
!#5 N10379 P3733 BLD 2 -1 FP BE Pri
!#5 N10380 P3733 BLD 3 -1 FP BE Pri
!#5 N10381 P3733 BLD 0 -1 FP BE Pri
!#5 N10382 P3733 BLD 1 -1 FP BE Pri
!#A N10381 N10382
!#5 N10383 P3733 BLD 2 -1 FP BE Pri
!#5 N10384 P3733 BLD 3 -1 FP BE Pri
!#5 N10385 P3734 BLD 20 -1 FP BE Pri
!#5 N10386 P3734 BLD 21 -1 FP BE Pri
!#A N10385 N10386
!#5 N10387 P3734 BLD 22 -1 FP BE Pri
!#5 N10388 P3734 BLD 23 -1 FP BE Pri
!#5 N10389 P3735 BLD 12 -1 FP BE Pri
!#5 N10390 P3735 BLD 13 -1 FP BE Pri
!#A N10389 N10390
!#5 N10391 P3735 BLD 14 -1 FP BE Pri
!#5 N10392 P3735 BLD 15 -1 FP BE Pri
!#5 N10393 P3736 BLD 24 -1 FP BE Pri
!#5 N10394 P3736 BLD 25 -1 FP BE Pri
!#A N10393 N10394
!#5 N10395 P3736 BLD 26 -1 FP BE Pri
!#5 N10396 P3736 BLD 27 -1 FP BE Pri
!#5 N10397 P3735 BLD 12 -1 FP BE Pri
!#5 N10398 P3735 BLD 13 -1 FP BE Pri
!#A N10397 N10398
!#5 N10399 P3735 BLD 14 -1 FP BE Pri
!#5 N10400 P3735 BLD 15 -1 FP BE Pri
!#5 N10401 P3736 BLD 24 -1 FP BE Pri
!#5 N10402 P3736 BLD 25 -1 FP BE Pri
!#A N10401 N10402
!#5 N10403 P3736 BLD 26 -1 FP BE Pri
!#5 N10404 P3736 BLD 27 -1 FP BE Pri
!#5 N10405 P3737 DWST 11 0x2800026 Int BE Pri
!#5 N10406 P3738 DWLD 12 -1 Int BE Pri
!#5 N10407 P3738 DWLD 13 -1 Int BE Pri
!#A N10406 N10407
!#5 N10408 P3739 BLD 16 -1 FP BE Pri
!#5 N10409 P3739 BLD 17 -1 FP BE Pri
!#A N10408 N10409
!#5 N10410 P3739 BLD 18 -1 FP BE Pri
!#5 N10411 P3739 BLD 19 -1 FP BE Pri
!#5 N10412 P3740 LD 26 -1 Int BE Pri
!#5 N10413 P3741 LD 13 -1 Int BE Pri
!#5 N10414 P3739 BLD 16 -1 FP BE Pri
!#5 N10415 P3739 BLD 17 -1 FP BE Pri
!#A N10414 N10415
!#5 N10416 P3739 BLD 18 -1 FP BE Pri
!#5 N10417 P3739 BLD 19 -1 FP BE Pri
!#5 N10418 P3740 LD 26 -1 Int BE Pri
!#5 N10419 P3741 LD 13 -1 Int BE Pri
!#5 N10420 P3742 LD 13 -1 Int LE Pri
!#5 N10421 P3743 DWLD 19 -1 Int BE Pri
!#5 N10422 P3742 LD 13 -1 Int LE Pri
!#5 N10423 P3743 DWLD 19 -1 Int BE Pri
!#5 N10425 P3745 LD 20 -1 Int BE Pri
!#5 N10426 P3746 LD 23 -1 Int BE Pri
!#5 N10428 P3745 LD 20 -1 Int BE Pri
!#5 N10429 P3746 LD 23 -1 Int BE Pri
!#5 N10430 P3747 BLD 4 -1 FP BE Pri
!#5 N10431 P3747 BLD 5 -1 FP BE Pri
!#A N10430 N10431
!#5 N10432 P3747 BLD 6 -1 FP BE Pri
!#5 N10433 P3747 BLD 7 -1 FP BE Pri
!#5 N10434 P3748 LD 7 -1 FP BE Pri
!#5 N10435 P3748 LD 7 -1 FP BE Pri
!#5 N10437 P3750 BLD 24 -1 FP BE Pri
!#5 N10438 P3750 BLD 25 -1 FP BE Pri
!#A N10437 N10438
!#5 N10439 P3750 BLD 26 -1 FP BE Pri
!#5 N10440 P3750 BLD 27 -1 FP BE Pri
!#5 N10441 P3751 BLD 20 -1 FP BE Pri
!#5 N10442 P3751 BLD 21 -1 FP BE Pri
!#A N10441 N10442
!#5 N10443 P3751 BLD 22 -1 FP BE Pri
!#5 N10444 P3751 BLD 23 -1 FP BE Pri
!#5 N10445 P3750 BLD 24 -1 FP BE Pri
!#5 N10446 P3750 BLD 25 -1 FP BE Pri
!#A N10445 N10446
!#5 N10447 P3750 BLD 26 -1 FP BE Pri
!#5 N10448 P3750 BLD 27 -1 FP BE Pri
!#5 N10449 P3751 BLD 20 -1 FP BE Pri
!#5 N10450 P3751 BLD 21 -1 FP BE Pri
!#A N10449 N10450
!#5 N10451 P3751 BLD 22 -1 FP BE Pri
!#5 N10452 P3751 BLD 23 -1 FP BE Pri
!#5 N10453 P3752 LD 1 -1 Int BE Pri
!#5 N10454 P3753 BLD 16 -1 FP BE Pri
!#5 N10455 P3753 BLD 17 -1 FP BE Pri
!#A N10454 N10455
!#5 N10456 P3753 BLD 18 -1 FP BE Pri
!#5 N10457 P3753 BLD 19 -1 FP BE Pri
!#5 N10458 P3754 LD 3 -1 Int BE Pri
!#5 N10459 P3752 LD 1 -1 Int BE Pri
!#5 N10460 P3753 BLD 16 -1 FP BE Pri
!#5 N10461 P3753 BLD 17 -1 FP BE Pri
!#A N10460 N10461
!#5 N10462 P3753 BLD 18 -1 FP BE Pri
!#5 N10463 P3753 BLD 19 -1 FP BE Pri
!#5 N10464 P3754 LD 3 -1 Int BE Pri
!#5 N10465 P3755 DWLD 31 -1 Int BE Pri
!#5 N10466 P3756 LD 8 -1 Int BE Pri
!#5 N10467 P3757 BLD 0 -1 FP BE Pri
!#5 N10468 P3757 BLD 1 -1 FP BE Pri
!#A N10467 N10468
!#5 N10469 P3757 BLD 2 -1 FP BE Pri
!#5 N10470 P3757 BLD 3 -1 FP BE Pri
!#5 N10471 P3757 BLD 0 -1 FP BE Pri
!#5 N10472 P3757 BLD 1 -1 FP BE Pri
!#A N10471 N10472
!#5 N10473 P3757 BLD 2 -1 FP BE Pri
!#5 N10474 P3757 BLD 3 -1 FP BE Pri
!#5 N10475 P3758 BLD 28 -1 FP BE Pri
!#5 N10476 P3758 BLD 29 -1 FP BE Pri
!#A N10475 N10476
!#5 N10477 P3758 BLD 30 -1 FP BE Pri
!#5 N10478 P3758 BLD 31 -1 FP BE Pri
!#5 N10479 P3759 LD 13 -1 Int BE Pri
!#5 N10480 P3760 LD 6 -1 Int BE Pri
!#5 N10481 P3761 LD 14 -1 Int BE Pri
!#5 N10482 P3762 LD 2 -1 Int BE Pri
!#5 N10483 P3761 LD 14 -1 Int BE Pri
!#5 N10484 P3762 LD 2 -1 Int BE Pri
!#5 N10485 P3763 LD 9 -1 FP BE Pri
!#5 N10486 P3763 LD 9 -1 FP BE Pri
!#5 N10487 P3764 LD 27 -1 FP BE Pri
!#5 N10488 P3765 SWAP 21 0xffffffff 0x2800027 Int BE Pri
!#5 N10489 P3766 LD 9 -1 Int BE Pri
!#5 N10490 P3764 LD 27 -1 FP BE Pri
!#5 N10491 P3765 SWAP 21 0xffffffff 0x2800028 Int BE Pri
!#5 N10492 P3766 LD 9 -1 Int BE Pri
!#5 N10493 P3767 LD 31 -1 Int BE Pri
!#5 N10494 P3768 LD 17 -1 Int BE Pri
!#5 N10495 P3769 BLD 4 -1 FP BE Pri
!#5 N10496 P3769 BLD 5 -1 FP BE Pri
!#A N10495 N10496
!#5 N10497 P3769 BLD 6 -1 FP BE Pri
!#5 N10498 P3769 BLD 7 -1 FP BE Pri
!#5 N10499 P3769 BLD 4 -1 FP BE Pri
!#5 N10500 P3769 BLD 5 -1 FP BE Pri
!#A N10499 N10500
!#5 N10501 P3769 BLD 6 -1 FP BE Pri
!#5 N10502 P3769 BLD 7 -1 FP BE Pri
!#5 N10503 P3770 DWLD 20 -1 Int BE Pri
!#5 N10504 P3770 DWLD 21 -1 Int BE Pri
!#A N10503 N10504
!#5 N10505 P3770 DWLD 20 -1 Int BE Pri
!#5 N10506 P3770 DWLD 21 -1 Int BE Pri
!#A N10505 N10506
!#5 N10507 P3771 DWLD 19 -1 Int BE Pri
!#5 N10508 P3772 LD 0 -1 Int LE Pri
!#5 N10509 P3773 BLD 12 -1 FP BE Pri
!#5 N10510 P3773 BLD 13 -1 FP BE Pri
!#A N10509 N10510
!#5 N10511 P3773 BLD 14 -1 FP BE Pri
!#5 N10512 P3773 BLD 15 -1 FP BE Pri
!#5 N10513 P3774 MEMBAR
!#5 N10514 P3775 DWLD 11 -1 Int BE Pri
!#5 N10515 P3776 LD 0 -1 Int BE Pri
!#5 N10516 P3777 LD 23 -1 Int BE Pri
!#5 N10517 P3778 LD 17 -1 Int BE Pri
!#5 N10518 P3777 LD 23 -1 Int BE Pri
!#5 N10519 P3778 LD 17 -1 Int BE Pri
!#5 N10520 P3779 BST 20 0x42000021 FP BE Pri
!#5 N10521 P3779 BST 21 0x42000022 FP BE Pri
!#A N10520 N10521
!#5 N10522 P3779 BST 22 0x42000023 FP BE Pri
!#5 N10523 P3779 BST 23 0x42000024 FP BE Pri
!#5 N10524 P3780 LD 26 -1 Int BE Pri
!#5 N10525 P3781 LD 17 -1 Int BE Pri
!#5 N10526 P3782 BLD 0 -1 FP BE Pri
!#5 N10527 P3782 BLD 1 -1 FP BE Pri
!#A N10526 N10527
!#5 N10528 P3782 BLD 2 -1 FP BE Pri
!#5 N10529 P3782 BLD 3 -1 FP BE Pri
!#5 N10530 P3783 DWLD 6 -1 Int BE Pri
!#5 N10531 P3784 LD 20 -1 Int BE Pri
!#5 N10532 P3783 DWLD 6 -1 Int BE Pri
!#5 N10533 P3784 LD 20 -1 Int BE Pri
!#5 N10534 P3785 LD 25 -1 Int BE Pri
!#5 N10535 P3786 LD 27 -1 Int BE Pri
!#5 N10536 P3785 LD 25 -1 Int BE Pri
!#5 N10537 P3786 LD 27 -1 Int BE Pri
!#5 N10538 P3787 BLD 16 -1 FP BE Pri
!#5 N10539 P3787 BLD 17 -1 FP BE Pri
!#A N10538 N10539
!#5 N10540 P3787 BLD 18 -1 FP BE Pri
!#5 N10541 P3787 BLD 19 -1 FP BE Pri
!#5 N10542 P3787 BLD 16 -1 FP BE Pri
!#5 N10543 P3787 BLD 17 -1 FP BE Pri
!#A N10542 N10543
!#5 N10544 P3787 BLD 18 -1 FP BE Pri
!#5 N10545 P3787 BLD 19 -1 FP BE Pri
!#5 N10546 P3788 BLD 24 -1 FP BE Pri
!#5 N10547 P3788 BLD 25 -1 FP BE Pri
!#A N10546 N10547
!#5 N10548 P3788 BLD 26 -1 FP BE Pri
!#5 N10549 P3788 BLD 27 -1 FP BE Pri
!#5 N10550 P3789 DWLD 4 -1 Int BE Pri
!#5 N10551 P3789 DWLD 5 -1 Int BE Pri
!#A N10550 N10551
!#5 N10552 P3790 LD 16 -1 Int BE Pri
!#5 N10553 P3791 BLD 8 -1 FP BE Pri
!#5 N10554 P3791 BLD 9 -1 FP BE Pri
!#A N10553 N10554
!#5 N10555 P3791 BLD 10 -1 FP BE Pri
!#5 N10556 P3791 BLD 11 -1 FP BE Pri
!#5 N10557 P3792 LD 1 -1 Int BE Pri
!#5 N10558 P3793 BLD 28 -1 FP BE Pri
!#5 N10559 P3793 BLD 29 -1 FP BE Pri
!#A N10558 N10559
!#5 N10560 P3793 BLD 30 -1 FP BE Pri
!#5 N10561 P3793 BLD 31 -1 FP BE Pri
!#5 N10562 P3793 BLD 28 -1 FP BE Pri
!#5 N10563 P3793 BLD 29 -1 FP BE Pri
!#A N10562 N10563
!#5 N10564 P3793 BLD 30 -1 FP BE Pri
!#5 N10565 P3793 BLD 31 -1 FP BE Pri
!#5 N10566 P3794 DWLD 0 -1 Int BE Pri
!#5 N10567 P3794 DWLD 1 -1 Int BE Pri
!#A N10566 N10567
!#5 N10568 P3795 LD 31 -1 Int BE Pri
!#5 N10569 P3796 LD 8 -1 Int BE Pri
!#5 N10570 P3794 DWLD 0 -1 Int BE Pri
!#5 N10571 P3794 DWLD 1 -1 Int BE Pri
!#A N10570 N10571
!#5 N10572 P3795 LD 31 -1 Int BE Pri
!#5 N10573 P3796 LD 8 -1 Int BE Pri
!#5 N10574 P3797 LD 4 -1 Int BE Pri
!#5 N10575 P3798 BLD 16 -1 FP BE Pri
!#5 N10576 P3798 BLD 17 -1 FP BE Pri
!#A N10575 N10576
!#5 N10577 P3798 BLD 18 -1 FP BE Pri
!#5 N10578 P3798 BLD 19 -1 FP BE Pri
!#5 N10579 P3799 LD 17 -1 Int BE Pri
!#5 N10580 P3797 LD 4 -1 Int BE Pri
!#5 N10581 P3798 BLD 16 -1 FP BE Pri
!#5 N10582 P3798 BLD 17 -1 FP BE Pri
!#A N10581 N10582
!#5 N10583 P3798 BLD 18 -1 FP BE Pri
!#5 N10584 P3798 BLD 19 -1 FP BE Pri
!#5 N10585 P3799 LD 17 -1 Int BE Pri
!#5 N10586 P3800 LD 24 -1 Int BE Pri
!#5 N10587 P3801 LD 25 -1 Int LE Pri
!#5 N10588 P3802 BST 24 0x42000025 FP BE Pri
!#5 N10589 P3802 BST 25 0x42000026 FP BE Pri
!#A N10588 N10589
!#5 N10590 P3802 BST 26 0x42000027 FP BE Pri
!#5 N10591 P3802 BST 27 0x42000028 FP BE Pri
!#5 N10592 P3803 DWLD 12 -1 Int BE Pri
!#5 N10593 P3803 DWLD 13 -1 Int BE Pri
!#A N10592 N10593
!#5 N10594 P3802 BST 24 0x42000029 FP BE Pri
!#5 N10595 P3802 BST 25 0x4200002a FP BE Pri
!#A N10594 N10595
!#5 N10596 P3802 BST 26 0x4200002b FP BE Pri
!#5 N10597 P3802 BST 27 0x4200002c FP BE Pri
!#5 N10598 P3803 DWLD 12 -1 Int BE Pri
!#5 N10599 P3803 DWLD 13 -1 Int BE Pri
!#A N10598 N10599
!#5 N10600 P3804 DWLD 4 -1 Int BE Pri
!#5 N10601 P3804 DWLD 5 -1 Int BE Pri
!#A N10600 N10601
!#5 N10602 P3804 DWLD 4 -1 Int BE Pri
!#5 N10603 P3804 DWLD 5 -1 Int BE Pri
!#A N10602 N10603
!#5 N10604 P3805 DWLD 4 -1 Int BE Pri
!#5 N10605 P3805 DWLD 5 -1 Int BE Pri
!#A N10604 N10605
!#5 N10606 P3806 LD 16 -1 Int BE Pri
!#5 N10607 P3807 LD 1 -1 Int BE Pri
!#5 N10608 P3807 CAS 1 -1 N10607 0x2800029 Int BE Pri
!#5 N10609 P3808 LD 16 -1 Int BE Pri
!#5 N10610 P3809 BLD 0 -1 FP BE Pri
!#5 N10611 P3809 BLD 1 -1 FP BE Pri
!#A N10610 N10611
!#5 N10612 P3809 BLD 2 -1 FP BE Pri
!#5 N10613 P3809 BLD 3 -1 FP BE Pri
!#5 N10614 P3810 LD 11 -1 Int BE Pri
!#5 N10615 P3811 DWLD 31 -1 FP BE Pri
!#5 N10616 P3812 LD 29 -1 Int LE Pri
!#5 N10617 P3813 BLD 16 -1 FP BE Pri
!#5 N10618 P3813 BLD 17 -1 FP BE Pri
!#A N10617 N10618
!#5 N10619 P3813 BLD 18 -1 FP BE Pri
!#5 N10620 P3813 BLD 19 -1 FP BE Pri
!#5 N10621 P3814 LD 17 -1 Int BE Pri
!#5 N10622 P3815 LD 16 -1 Int BE Pri
!#5 N10623 P3816 LD 19 -1 Int BE Pri
!#5 N10624 P3817 LD 26 -1 Int BE Pri
!#5 N10625 P3816 LD 19 -1 Int BE Pri
!#5 N10626 P3817 LD 26 -1 Int BE Pri
!#5 N10627 P3818 BLD 16 -1 FP BE Pri
!#5 N10628 P3818 BLD 17 -1 FP BE Pri
!#A N10627 N10628
!#5 N10629 P3818 BLD 18 -1 FP BE Pri
!#5 N10630 P3818 BLD 19 -1 FP BE Pri
!#5 N10631 P3819 DWLD 11 -1 Int BE Pri
!#5 N10632 P3820 LD 23 -1 Int BE Pri
!#5 N10633 P3821 LD 14 -1 Int BE Pri
!#5 N10634 P3822 LD 28 -1 Int BE Pri
!#5 N10635 P3821 LD 14 -1 Int BE Pri
!#5 N10636 P3822 LD 28 -1 Int BE Pri
!#5 N10637 P3823 BLD 12 -1 FP BE Pri
!#5 N10638 P3823 BLD 13 -1 FP BE Pri
!#A N10637 N10638
!#5 N10639 P3823 BLD 14 -1 FP BE Pri
!#5 N10640 P3823 BLD 15 -1 FP BE Pri
!#5 N10641 P3824 LD 0 -1 Int BE Pri
!#5 N10642 P3825 BLD 0 -1 FP BE Pri
!#5 N10643 P3825 BLD 1 -1 FP BE Pri
!#A N10642 N10643
!#5 N10644 P3825 BLD 2 -1 FP BE Pri
!#5 N10645 P3825 BLD 3 -1 FP BE Pri
!#5 N10646 P3826 LD 25 -1 Int BE Pri
!#5 N10647 P3824 LD 0 -1 Int BE Pri
!#5 N10648 P3825 BLD 0 -1 FP BE Pri
!#5 N10649 P3825 BLD 1 -1 FP BE Pri
!#A N10648 N10649
!#5 N10650 P3825 BLD 2 -1 FP BE Pri
!#5 N10651 P3825 BLD 3 -1 FP BE Pri
!#5 N10652 P3826 LD 25 -1 Int BE Pri
!#5 N10653 P3827 LD 3 -1 Int BE Pri
!#5 N10654 P3828 LD 30 -1 Int BE Pri
!#5 N10655 P3827 LD 3 -1 Int BE Pri
!#5 N10656 P3828 LD 30 -1 Int BE Pri
!#5 N10657 P3829 BLD 8 -1 FP BE Pri
!#5 N10658 P3829 BLD 9 -1 FP BE Pri
!#A N10657 N10658
!#5 N10659 P3829 BLD 10 -1 FP BE Pri
!#5 N10660 P3829 BLD 11 -1 FP BE Pri
!#5 N10661 P3830 DWLD 18 -1 Int BE Pri
!#5 N10662 P3831 LD 13 -1 Int BE Pri
!#5 N10663 P3829 BLD 8 -1 FP BE Pri
!#5 N10664 P3829 BLD 9 -1 FP BE Pri
!#A N10663 N10664
!#5 N10665 P3829 BLD 10 -1 FP BE Pri
!#5 N10666 P3829 BLD 11 -1 FP BE Pri
!#5 N10667 P3830 DWLD 18 -1 Int BE Pri
!#5 N10668 P3831 LD 13 -1 Int BE Pri
!#5 N10669 P3832 BLD 0 -1 FP BE Pri
!#5 N10670 P3832 BLD 1 -1 FP BE Pri
!#A N10669 N10670
!#5 N10671 P3832 BLD 2 -1 FP BE Pri
!#5 N10672 P3832 BLD 3 -1 FP BE Pri
!#5 N10673 P3832 BLD 0 -1 FP BE Pri
!#5 N10674 P3832 BLD 1 -1 FP BE Pri
!#A N10673 N10674
!#5 N10675 P3832 BLD 2 -1 FP BE Pri
!#5 N10676 P3832 BLD 3 -1 FP BE Pri
!#5 N10677 P3833 SWAP 22 0xffffffff 0x280002a Int BE Pri
!#5 N10678 P3834 LD 3 -1 Int BE Pri
!#5 N10679 P3835 LD 2 -1 Int BE Pri
!#5 N10680 P3836 LD 14 -1 Int BE Pri
!#5 N10681 P3835 LD 2 -1 Int BE Pri
!#5 N10682 P3836 LD 14 -1 Int BE Pri
!#5 N10683 P3837 BLD 20 -1 FP BE Pri
!#5 N10684 P3837 BLD 21 -1 FP BE Pri
!#A N10683 N10684
!#5 N10685 P3837 BLD 22 -1 FP BE Pri
!#5 N10686 P3837 BLD 23 -1 FP BE Pri
!#5 N10687 P3838 BLD 28 -1 FP BE Pri
!#5 N10688 P3838 BLD 29 -1 FP BE Pri
!#A N10687 N10688
!#5 N10689 P3838 BLD 30 -1 FP BE Pri
!#5 N10690 P3838 BLD 31 -1 FP BE Pri
!#5 N10693 P3840 BLD 4 -1 FP BE Pri
!#5 N10694 P3840 BLD 5 -1 FP BE Pri
!#A N10693 N10694
!#5 N10695 P3840 BLD 6 -1 FP BE Pri
!#5 N10696 P3840 BLD 7 -1 FP BE Pri
!#5 N10697 P3840 BLD 4 -1 FP BE Pri
!#5 N10698 P3840 BLD 5 -1 FP BE Pri
!#A N10697 N10698
!#5 N10699 P3840 BLD 6 -1 FP BE Pri
!#5 N10700 P3840 BLD 7 -1 FP BE Pri
!#5 N10701 P3841 BLD 24 -1 FP BE Pri
!#5 N10702 P3841 BLD 25 -1 FP BE Pri
!#A N10701 N10702
!#5 N10703 P3841 BLD 26 -1 FP BE Pri
!#5 N10704 P3841 BLD 27 -1 FP BE Pri
!#5 N10705 P3841 BLD 24 -1 FP BE Pri
!#5 N10706 P3841 BLD 25 -1 FP BE Pri
!#A N10705 N10706
!#5 N10707 P3841 BLD 26 -1 FP BE Pri
!#5 N10708 P3841 BLD 27 -1 FP BE Pri
!#5 N10709 P3842 ST 30 0x280002b Int BE Pri
!#5 N10710 P3843 DWLD 4 -1 Int BE Pri
!#5 N10711 P3843 DWLD 5 -1 Int BE Pri
!#A N10710 N10711
!#5 N10712 P3842 ST 30 0x280002c Int BE Pri
!#5 N10713 P3843 DWLD 4 -1 Int BE Pri
!#5 N10714 P3843 DWLD 5 -1 Int BE Pri
!#A N10713 N10714
!#5 N10715 P3844 LD 8 -1 Int BE Pri
!#5 N10716 P3845 LD 28 -1 Int BE Pri
!#5 N10717 P3844 LD 8 -1 Int BE Pri
!#5 N10718 P3845 LD 28 -1 Int BE Pri
!#5 N10719 P3846 LD 27 -1 Int BE Pri
!#5 N10720 P3847 LD 22 -1 Int BE Pri
!#5 N10721 P3846 LD 27 -1 Int BE Pri
!#5 N10722 P3847 LD 22 -1 Int BE Pri
!#5 N10723 P3848 BLD 8 -1 FP BE Pri
!#5 N10724 P3848 BLD 9 -1 FP BE Pri
!#A N10723 N10724
!#5 N10725 P3848 BLD 10 -1 FP BE Pri
!#5 N10726 P3848 BLD 11 -1 FP BE Pri
!#5 N10727 P3849 DWLD 3 -1 Int BE Pri
!#5 N10728 P3850 LD 15 -1 Int BE Pri
!#5 N10729 P3848 BLD 8 -1 FP BE Pri
!#5 N10730 P3848 BLD 9 -1 FP BE Pri
!#A N10729 N10730
!#5 N10731 P3848 BLD 10 -1 FP BE Pri
!#5 N10732 P3848 BLD 11 -1 FP BE Pri
!#5 N10733 P3849 DWLD 3 -1 Int BE Pri
!#5 N10734 P3850 LD 15 -1 Int BE Pri
!#5 N10735 P3851 LD 22 -1 Int BE Pri
!#5 N10736 P3852 BLD 12 -1 FP BE Pri
!#5 N10737 P3852 BLD 13 -1 FP BE Pri
!#A N10736 N10737
!#5 N10738 P3852 BLD 14 -1 FP BE Pri
!#5 N10739 P3852 BLD 15 -1 FP BE Pri
!#5 N10740 P3853 LD 20 -1 Int BE Pri
!#5 N10741 P3854 LD 15 -1 Int BE Pri
!#5 N10742 P3854 CAS 15 -1 N10741 0x280002d Int BE Pri
!#5 N10743 P3855 DWLD 12 -1 FP BE Pri
!#5 N10744 P3855 DWLD 13 -1 FP BE Pri
!#A N10743 N10744
!#5 N10745 P3854 LD 15 -1 Int BE Pri
!#5 N10746 P3854 CAS 15 -1 N10745 0x280002e Int BE Pri
!#5 N10747 P3855 DWLD 12 -1 FP BE Pri
!#5 N10748 P3855 DWLD 13 -1 FP BE Pri
!#A N10747 N10748
!#5 N10749 P3856 SWAP 26 0xffffffff 0x280002f Int BE Pri
!#5 N10750 P3857 BSTC 20 0x4200002d FP BE Pri
!#5 N10751 P3857 BSTC 21 0x4200002e FP BE Pri
!#A N10750 N10751
!#5 N10752 P3857 BSTC 22 0x4200002f FP BE Pri
!#5 N10753 P3857 BSTC 23 0x42000030 FP BE Pri
!#5 N10754 P3858 LD 15 -1 Int BE Pri
!#5 N10755 P3859 DWLD 24 -1 Int BE Pri
!#5 N10756 P3859 DWLD 25 -1 Int BE Pri
!#A N10755 N10756
!#5 N10757 P3860 DWLD 19 -1 Int BE Pri
!#5 N10758 P3861 LD 25 -1 Int BE Pri
!#5 N10759 P3862 BLD 16 -1 FP BE Pri
!#5 N10760 P3862 BLD 17 -1 FP BE Pri
!#A N10759 N10760
!#5 N10761 P3862 BLD 18 -1 FP BE Pri
!#5 N10762 P3862 BLD 19 -1 FP BE Pri
!#5 N10763 P3862 BLD 16 -1 FP BE Pri
!#5 N10764 P3862 BLD 17 -1 FP BE Pri
!#A N10763 N10764
!#5 N10765 P3862 BLD 18 -1 FP BE Pri
!#5 N10766 P3862 BLD 19 -1 FP BE Pri
!#5 N10768 P3864 LD 18 -1 Int BE Pri
!#5 N10769 P3865 LD 5 -1 Int BE Pri
!#5 N10770 P3866 BLD 4 -1 FP BE Pri
!#5 N10771 P3866 BLD 5 -1 FP BE Pri
!#A N10770 N10771
!#5 N10772 P3866 BLD 6 -1 FP BE Pri
!#5 N10773 P3866 BLD 7 -1 FP BE Pri
!#5 N10774 P3867 LD 1 -1 Int BE Pri
!#5 N10775 P3868 LD 29 -1 Int LE Pri
!#5 N10776 P3866 BLD 4 -1 FP BE Pri
!#5 N10777 P3866 BLD 5 -1 FP BE Pri
!#A N10776 N10777
!#5 N10778 P3866 BLD 6 -1 FP BE Pri
!#5 N10779 P3866 BLD 7 -1 FP BE Pri
!#5 N10780 P3867 LD 1 -1 Int BE Pri
!#5 N10781 P3868 LD 29 -1 Int LE Pri
!#5 N10782 P3869 SWAP 1 0xffffffff 0x2800030 Int BE Pri
!#5 N10783 P3870 BLD 12 -1 FP BE Pri
!#5 N10784 P3870 BLD 13 -1 FP BE Pri
!#A N10783 N10784
!#5 N10785 P3870 BLD 14 -1 FP BE Pri
!#5 N10786 P3870 BLD 15 -1 FP BE Pri
!#5 N10787 P3871 LD 1 -1 Int BE Pri
!#5 N10788 P3872 LD 16 -1 Int BE Pri
!#5 N10789 P3873 LD 12 -1 Int BE Pri
!#5 N10790 P3874 BLD 4 -1 FP BE Pri
!#5 N10791 P3874 BLD 5 -1 FP BE Pri
!#A N10790 N10791
!#5 N10792 P3874 BLD 6 -1 FP BE Pri
!#5 N10793 P3874 BLD 7 -1 FP BE Pri
!#5 N10794 P3875 LD 27 -1 Int BE Pri
!#5 N10795 P3876 LD 10 -1 Int BE Pri
!#5 N10796 P3875 LD 27 -1 Int BE Pri
!#5 N10797 P3876 LD 10 -1 Int BE Pri
!#5 N10798 P3877 DWLD 20 -1 Int BE Pri
!#5 N10799 P3877 DWLD 21 -1 Int BE Pri
!#A N10798 N10799
!#5 N10800 P3878 DWLD 3 -1 Int BE Pri
!#5 N10801 P3879 LD 31 -1 Int BE Pri
!#5 N10802 P3877 DWLD 20 -1 Int BE Pri
!#5 N10803 P3877 DWLD 21 -1 Int BE Pri
!#A N10802 N10803
!#5 N10804 P3878 DWLD 3 -1 Int BE Pri
!#5 N10805 P3879 LD 31 -1 Int BE Pri
!#5 N10806 P3880 BST 24 0x42000031 FP BE Pri
!#5 N10807 P3880 BST 25 0x42000032 FP BE Pri
!#A N10806 N10807
!#5 N10808 P3880 BST 26 0x42000033 FP BE Pri
!#5 N10809 P3880 BST 27 0x42000034 FP BE Pri
!#5 N10810 P3881 BLD 4 -1 FP BE Pri
!#5 N10811 P3881 BLD 5 -1 FP BE Pri
!#A N10810 N10811
!#5 N10812 P3881 BLD 6 -1 FP BE Pri
!#5 N10813 P3881 BLD 7 -1 FP BE Pri
!#5 N10814 P3882 DWLD 12 -1 Int BE Pri
!#5 N10815 P3882 DWLD 13 -1 Int BE Pri
!#A N10814 N10815
!#5 N10816 P3882 DWLD 12 -1 Int BE Pri
!#5 N10817 P3882 DWLD 13 -1 Int BE Pri
!#A N10816 N10817
!#5 N10818 P3883 LD 24 -1 Int BE Pri
!#5 N10819 P3883 CAS 24 -1 N10818 0x2800031 Int BE Pri
!#5 N10820 P3884 BLD 28 -1 FP BE Pri
!#5 N10821 P3884 BLD 29 -1 FP BE Pri
!#A N10820 N10821
!#5 N10822 P3884 BLD 30 -1 FP BE Pri
!#5 N10823 P3884 BLD 31 -1 FP BE Pri
!#5 N10824 P3885 BLD 24 -1 FP BE Pri
!#5 N10825 P3885 BLD 25 -1 FP BE Pri
!#A N10824 N10825
!#5 N10826 P3885 BLD 26 -1 FP BE Pri
!#5 N10827 P3885 BLD 27 -1 FP BE Pri
!#5 N10828 P3886 DWLD 23 -1 Int BE Pri
!#5 N10829 P3887 DWLD 7 -1 Int BE Pri
!#5 N10830 P3886 DWLD 23 -1 Int BE Pri
!#5 N10831 P3887 DWLD 7 -1 Int BE Pri
!#5 N10832 P3888 LD 2 -1 Int BE Pri
!#5 N10833 P3889 LD 9 -1 FP BE Pri
!#5 N10834 P3890 LD 9 -1 Int BE Pri
!#5 N10835 P3891 DWLD 12 -1 Int BE Pri
!#5 N10836 P3891 DWLD 13 -1 Int BE Pri
!#A N10835 N10836
!#5 N10837 P3892 LD 2 -1 Int BE Pri
!#5 N10838 P3893 LD 17 -1 Int BE Pri
!#5 N10839 P3891 DWLD 12 -1 Int BE Pri
!#5 N10840 P3891 DWLD 13 -1 Int BE Pri
!#A N10839 N10840
!#5 N10841 P3892 LD 2 -1 Int BE Pri
!#5 N10842 P3893 LD 17 -1 Int BE Pri
!#5 N10843 P3894 LD 18 -1 Int BE Pri
!#5 N10845 P3896 LD 28 -1 Int BE Pri
!#5 N10846 P3897 BLD 8 -1 FP BE Pri
!#5 N10847 P3897 BLD 9 -1 FP BE Pri
!#A N10846 N10847
!#5 N10848 P3897 BLD 10 -1 FP BE Pri
!#5 N10849 P3897 BLD 11 -1 FP BE Pri
!#5 N10850 P3897 BLD 8 -1 FP BE Pri
!#5 N10851 P3897 BLD 9 -1 FP BE Pri
!#A N10850 N10851
!#5 N10852 P3897 BLD 10 -1 FP BE Pri
!#5 N10853 P3897 BLD 11 -1 FP BE Pri
!#5 N10854 P3898 MEMBAR
!#5 N10855 P3899 DWLD 28 -1 Int BE Pri
!#5 N10856 P3899 DWLD 29 -1 Int BE Pri
!#A N10855 N10856
!#5 N10857 P3900 LD 8 -1 Int BE Pri
!#5 N10858 P3901 LD 16 -1 Int BE Pri
!#5 N10859 P3902 DWLD 30 -1 Int BE Pri
!#5 N10860 P3903 LD 18 -1 Int BE Pri
!#5 N10861 P3902 DWLD 30 -1 Int BE Pri
!#5 N10862 P3903 LD 18 -1 Int BE Pri
!#5 N10863 P3904 BLD 4 -1 FP BE Pri
!#5 N10864 P3904 BLD 5 -1 FP BE Pri
!#A N10863 N10864
!#5 N10865 P3904 BLD 6 -1 FP BE Pri
!#5 N10866 P3904 BLD 7 -1 FP BE Pri
!#5 N10867 P3905 BLD 24 -1 FP BE Pri
!#5 N10868 P3905 BLD 25 -1 FP BE Pri
!#A N10867 N10868
!#5 N10869 P3905 BLD 26 -1 FP BE Pri
!#5 N10870 P3905 BLD 27 -1 FP BE Pri
!#5 N10871 P3904 BLD 4 -1 FP BE Pri
!#5 N10872 P3904 BLD 5 -1 FP BE Pri
!#A N10871 N10872
!#5 N10873 P3904 BLD 6 -1 FP BE Pri
!#5 N10874 P3904 BLD 7 -1 FP BE Pri
!#5 N10875 P3905 BLD 24 -1 FP BE Pri
!#5 N10876 P3905 BLD 25 -1 FP BE Pri
!#A N10875 N10876
!#5 N10877 P3905 BLD 26 -1 FP BE Pri
!#5 N10878 P3905 BLD 27 -1 FP BE Pri
!#5 N10879 P3906 MEMBAR
!#5 N10880 P3907 BST 16 0x42000035 FP BE Pri
!#5 N10881 P3907 BST 17 0x42000036 FP BE Pri
!#A N10880 N10881
!#5 N10882 P3907 BST 18 0x42000037 FP BE Pri
!#5 N10883 P3907 BST 19 0x42000038 FP BE Pri
!#5 N10885 P3909 BLD 16 -1 FP BE Pri
!#5 N10886 P3909 BLD 17 -1 FP BE Pri
!#A N10885 N10886
!#5 N10887 P3909 BLD 18 -1 FP BE Pri
!#5 N10888 P3909 BLD 19 -1 FP BE Pri
!#5 N10889 P3910 BLD 24 -1 FP BE Pri
!#5 N10890 P3910 BLD 25 -1 FP BE Pri
!#A N10889 N10890
!#5 N10891 P3910 BLD 26 -1 FP BE Pri
!#5 N10892 P3910 BLD 27 -1 FP BE Pri
!#5 N10893 P3911 LD 11 -1 Int BE Pri
!#5 N10894 P3911 CAS 11 -1 N10893 0x2800032 Int BE Pri
!#5 N10895 P3912 LD 25 -1 Int BE Pri
!#5 N10896 P3913 LD 2 -1 Int LE Pri
!#5 N10897 P3912 LD 25 -1 Int BE Pri
!#5 N10898 P3913 LD 2 -1 Int LE Pri
!#5 N10899 P3914 LD 26 -1 FP BE Pri
!#5 N10900 P3915 BLD 16 -1 FP BE Pri
!#5 N10901 P3915 BLD 17 -1 FP BE Pri
!#A N10900 N10901
!#5 N10902 P3915 BLD 18 -1 FP BE Pri
!#5 N10903 P3915 BLD 19 -1 FP BE Pri
!#5 N10904 P3916 LD 11 -1 Int BE Pri
!#5 N10905 P3917 LD 3 -1 Int BE Pri
!#5 N10906 P3916 LD 11 -1 Int BE Pri
!#5 N10907 P3917 LD 3 -1 Int BE Pri
!#5 N10909 P3919 LD 20 -1 Int BE Pri
!#5 N10910 P3920 LD 31 -1 Int BE Pri
!#5 N10911 P3919 LD 20 -1 Int BE Pri
!#5 N10912 P3920 LD 31 -1 Int BE Pri
!#5 N10913 P3921 DWLD 31 -1 Int BE Pri
!#5 N10914 P3922 LD 18 -1 Int BE Pri
!#5 N10915 P3923 BLD 4 -1 FP BE Pri
!#5 N10916 P3923 BLD 5 -1 FP BE Pri
!#A N10915 N10916
!#5 N10917 P3923 BLD 6 -1 FP BE Pri
!#5 N10918 P3923 BLD 7 -1 FP BE Pri
!#5 N10919 P3924 BLD 12 -1 FP BE Pri
!#5 N10920 P3924 BLD 13 -1 FP BE Pri
!#A N10919 N10920
!#5 N10921 P3924 BLD 14 -1 FP BE Pri
!#5 N10922 P3924 BLD 15 -1 FP BE Pri
!#5 N10923 P3925 DWLD 12 -1 Int BE Pri
!#5 N10924 P3925 DWLD 13 -1 Int BE Pri
!#A N10923 N10924
!#5 N10925 P3926 LD 13 -1 Int BE Pri
!#5 N10926 P3927 LD 15 -1 Int BE Pri
!#5 N10927 P3928 DWLD 28 -1 FP BE Pri
!#5 N10928 P3928 DWLD 29 -1 FP BE Pri
!#A N10927 N10928
!#5 N10929 P3929 DWLD 8 -1 Int BE Pri
!#5 N10930 P3929 DWLD 9 -1 Int BE Pri
!#A N10929 N10930
!#5 N10931 P3930 DWLD 2 -1 Int BE Pri
!#5 N10932 P3931 LD 6 -1 Int BE Pri
!#5 N10933 P3932 BLD 4 -1 FP BE Pri
!#5 N10934 P3932 BLD 5 -1 FP BE Pri
!#A N10933 N10934
!#5 N10935 P3932 BLD 6 -1 FP BE Pri
!#5 N10936 P3932 BLD 7 -1 FP BE Pri
!#5 N10937 P3933 DWLD 19 -1,0x0 Int BE Pri
!#5 N10938 P3933 CASX 19 -1,0x0 N10937 0x2800033 Int BE Pri
!#5 N10939 P3934 BLD 4 -1 FP BE Pri
!#5 N10940 P3934 BLD 5 -1 FP BE Pri
!#A N10939 N10940
!#5 N10941 P3934 BLD 6 -1 FP BE Pri
!#5 N10942 P3934 BLD 7 -1 FP BE Pri
!#5 N10943 P3935 LD 15 -1 Int BE Pri
!#5 N10944 P3936 DWLD 28 -1 FP BE Pri
!#5 N10945 P3936 DWLD 29 -1 FP BE Pri
!#A N10944 N10945
!#5 N10946 P3937 LD 27 -1 Int BE Pri
!#5 N10947 P3938 SWAP 27 0xffffffff 0x2800034 Int BE Pri
!#5 N10948 P3939 BLD 0 -1 FP BE Pri
!#5 N10949 P3939 BLD 1 -1 FP BE Pri
!#A N10948 N10949
!#5 N10950 P3939 BLD 2 -1 FP BE Pri
!#5 N10951 P3939 BLD 3 -1 FP BE Pri
!#5 N10952 P3940 LD 23 -1 Int BE Pri
!#5 N10953 P3938 SWAP 27 0xffffffff 0x2800035 Int BE Pri
!#5 N10954 P3939 BLD 0 -1 FP BE Pri
!#5 N10955 P3939 BLD 1 -1 FP BE Pri
!#A N10954 N10955
!#5 N10956 P3939 BLD 2 -1 FP BE Pri
!#5 N10957 P3939 BLD 3 -1 FP BE Pri
!#5 N10958 P3940 LD 23 -1 Int BE Pri
!#5 N10959 P3941 BLD 0 -1 FP BE Pri
!#5 N10960 P3941 BLD 1 -1 FP BE Pri
!#A N10959 N10960
!#5 N10961 P3941 BLD 2 -1 FP BE Pri
!#5 N10962 P3941 BLD 3 -1 FP BE Pri
!#5 N10963 P3942 DWLD 3 -1 FP BE Pri
!#5 N10964 P3943 LD 2 -1 Int BE Pri
!#5 N10965 P3944 DWLD 12 -1 Int BE Pri
!#5 N10966 P3944 DWLD 13 -1 Int BE Pri
!#A N10965 N10966
!#5 N10967 P3945 LD 2 -1 Int BE Pri
!#5 N10968 P3943 LD 2 -1 Int BE Pri
!#5 N10969 P3944 DWLD 12 -1 Int BE Pri
!#5 N10970 P3944 DWLD 13 -1 Int BE Pri
!#A N10969 N10970
!#5 N10971 P3945 LD 2 -1 Int BE Pri
!#5 N10972 P3946 LD 9 -1 Int BE Pri
!#5 N10973 P3947 BLD 12 -1 FP BE Pri
!#5 N10974 P3947 BLD 13 -1 FP BE Pri
!#A N10973 N10974
!#5 N10975 P3947 BLD 14 -1 FP BE Pri
!#5 N10976 P3947 BLD 15 -1 FP BE Pri
!#5 N10977 P3948 LD 17 -1 Int BE Pri
!#5 N10979 P3950 DWLD 15 -1 Int BE Pri
!#5 N10980 P3951 LD 28 -1 Int BE Pri
!#5 N10981 P3952 DWLD 12 -1 FP BE Pri
!#5 N10982 P3952 DWLD 13 -1 FP BE Pri
!#A N10981 N10982
!#5 N10983 P3953 DWLD 6 -1 Int BE Pri
!#5 N10984 P3954 LD 30 -1 Int BE Pri
!#5 N10985 P3953 DWLD 6 -1 Int BE Pri
!#5 N10986 P3954 LD 30 -1 Int BE Pri
!#5 N10987 P3955 DWLD 15 -1 Int BE Pri
!#5 N10988 P3956 LD 16 -1 Int BE Pri
!#5 N10989 P3955 DWLD 15 -1 Int BE Pri
!#5 N10990 P3956 LD 16 -1 Int BE Pri
!#5 N10991 P3957 BLD 20 -1 FP BE Pri
!#5 N10992 P3957 BLD 21 -1 FP BE Pri
!#A N10991 N10992
!#5 N10993 P3957 BLD 22 -1 FP BE Pri
!#5 N10994 P3957 BLD 23 -1 FP BE Pri
!#5 N10995 P3958 LD 23 -1 Int LE Pri
!#5 N10996 P3959 LD 23 -1 Int BE Pri
!#5 N10997 P3957 BLD 20 -1 FP BE Pri
!#5 N10998 P3957 BLD 21 -1 FP BE Pri
!#A N10997 N10998
!#5 N10999 P3957 BLD 22 -1 FP BE Pri
!#5 N11000 P3957 BLD 23 -1 FP BE Pri
!#5 N11001 P3958 LD 23 -1 Int LE Pri
!#5 N11002 P3959 LD 23 -1 Int BE Pri
!#5 N11003 P3960 BLD 28 -1 FP BE Pri
!#5 N11004 P3960 BLD 29 -1 FP BE Pri
!#A N11003 N11004
!#5 N11005 P3960 BLD 30 -1 FP BE Pri
!#5 N11006 P3960 BLD 31 -1 FP BE Pri
!#5 N11007 P3961 MEMBAR
!#5 N11008 P3962 DWLD 7 -1 Int BE Pri
!#5 N11009 P3963 LD 0 -1 Int BE Pri
!#5 N11010 P3964 LD 21 -1 FP BE Pri
!#5 N11011 P3965 LD 25 -1 Int BE Pri
!#5 N11012 P3966 LD 0 -1 Int BE Pri
!#5 N11013 P3964 LD 21 -1 FP BE Pri
!#5 N11014 P3965 LD 25 -1 Int BE Pri
!#5 N11015 P3966 LD 0 -1 Int BE Pri
!#5 N11016 P3967 BLD 24 -1 FP BE Pri
!#5 N11017 P3967 BLD 25 -1 FP BE Pri
!#A N11016 N11017
!#5 N11018 P3967 BLD 26 -1 FP BE Pri
!#5 N11019 P3967 BLD 27 -1 FP BE Pri
!#5 N11020 P3968 DWST 0 0x42000039 FP BE Pri
!#5 N11021 P3968 DWST 1 0x4200003a FP BE Pri
!#A N11020 N11021
!#5 N11022 P3968 DWST 0 0x4200003b FP BE Pri
!#5 N11023 P3968 DWST 1 0x4200003c FP BE Pri
!#A N11022 N11023
!#5 N11024 P3969 BLD 0 -1 FP BE Pri
!#5 N11025 P3969 BLD 1 -1 FP BE Pri
!#A N11024 N11025
!#5 N11026 P3969 BLD 2 -1 FP BE Pri
!#5 N11027 P3969 BLD 3 -1 FP BE Pri
!#5 N11029 P3971 BLD 8 -1 FP BE Pri
!#5 N11030 P3971 BLD 9 -1 FP BE Pri
!#A N11029 N11030
!#5 N11031 P3971 BLD 10 -1 FP BE Pri
!#5 N11032 P3971 BLD 11 -1 FP BE Pri
!#5 N11034 P3971 BLD 8 -1 FP BE Pri
!#5 N11035 P3971 BLD 9 -1 FP BE Pri
!#A N11034 N11035
!#5 N11036 P3971 BLD 10 -1 FP BE Pri
!#5 N11037 P3971 BLD 11 -1 FP BE Pri
!#5 N11038 P3972 DWLD 8 -1 Int BE Pri
!#5 N11039 P3972 DWLD 9 -1 Int BE Pri
!#A N11038 N11039
!#5 N11040 P3973 LD 18 -1 Int BE Pri
!#5 N11041 P3974 LD 23 -1 Int BE Pri
!#5 N11042 P3975 BLD 24 -1 FP BE Pri
!#5 N11043 P3975 BLD 25 -1 FP BE Pri
!#A N11042 N11043
!#5 N11044 P3975 BLD 26 -1 FP BE Pri
!#5 N11045 P3975 BLD 27 -1 FP BE Pri
!#5 N11046 P3976 LD 22 -1 Int LE Pri
!#5 N11047 P3977 LD 28 -1 Int BE Pri
!#5 N11048 P3978 BLD 12 -1 FP BE Pri
!#5 N11049 P3978 BLD 13 -1 FP BE Pri
!#A N11048 N11049
!#5 N11050 P3978 BLD 14 -1 FP BE Pri
!#5 N11051 P3978 BLD 15 -1 FP BE Pri
!#5 N11052 P3979 LD 16 -1 Int BE Pri
!#5 N11053 P3980 LD 31 -1 Int BE Pri
!#5 N11054 P3981 LD 27 -1 Int BE Pri
!#5 N11055 P3982 LD 1 -1 Int BE Pri
!#5 N11056 P3983 MEMBAR
!#6 N11057 P3984 LD 1 -1 Int BE Pri
!#6 N11058 P3984 CAS 1 -1 N11057 0x3000001 Int BE Pri
!#6 N11059 P3984 LD 1 -1 Int BE Pri
!#6 N11060 P3984 CAS 1 -1 N11059 0x3000002 Int BE Pri
!#6 N11061 P3985 ST 0 0x3000003 Int BE Pri
!#6 N11062 P3986 BLD 16 -1 FP BE Pri
!#6 N11063 P3986 BLD 17 -1 FP BE Pri
!#A N11062 N11063
!#6 N11064 P3986 BLD 18 -1 FP BE Pri
!#6 N11065 P3986 BLD 19 -1 FP BE Pri
!#6 N11066 P3987 BLD 0 -1 FP BE Pri
!#6 N11067 P3987 BLD 1 -1 FP BE Pri
!#A N11066 N11067
!#6 N11068 P3987 BLD 2 -1 FP BE Pri
!#6 N11069 P3987 BLD 3 -1 FP BE Pri
!#6 N11070 P3988 LD 29 -1 Int BE Pri
!#6 N11071 P3988 CAS 29 -1 N11070 0x3000004 Int BE Pri
!#6 N11072 P3989 LD 27 -1 Int BE Pri
!#6 N11073 P3990 LD 0 -1 Int BE Pri
!#6 N11074 P3988 LD 29 -1 Int BE Pri
!#6 N11075 P3988 CAS 29 -1 N11074 0x3000005 Int BE Pri
!#6 N11076 P3989 LD 27 -1 Int BE Pri
!#6 N11077 P3990 LD 0 -1 Int BE Pri
!#6 N11078 P3991 LD 12 -1 Int BE Pri
!#6 N11079 P3991 CAS 12 -1 N11078 0x3000006 Int BE Pri
!#6 N11080 P3992 BLD 20 -1 FP BE Pri
!#6 N11081 P3992 BLD 21 -1 FP BE Pri
!#A N11080 N11081
!#6 N11082 P3992 BLD 22 -1 FP BE Pri
!#6 N11083 P3992 BLD 23 -1 FP BE Pri
!#6 N11084 P3993 DWLD 20 -1 Int BE Pri
!#6 N11085 P3993 DWLD 21 -1 Int BE Pri
!#A N11084 N11085
!#6 N11086 P3994 LD 15 -1 Int BE Pri
!#6 N11087 P3995 LD 12 -1 Int BE Pri
!#6 N11088 P3996 BLD 24 -1 FP BE Pri
!#6 N11089 P3996 BLD 25 -1 FP BE Pri
!#A N11088 N11089
!#6 N11090 P3996 BLD 26 -1 FP BE Pri
!#6 N11091 P3996 BLD 27 -1 FP BE Pri
!#6 N11092 P3996 BLD 24 -1 FP BE Pri
!#6 N11093 P3996 BLD 25 -1 FP BE Pri
!#A N11092 N11093
!#6 N11094 P3996 BLD 26 -1 FP BE Pri
!#6 N11095 P3996 BLD 27 -1 FP BE Pri
!#6 N11096 P3997 BST 8 0x42800001 FP BE Pri
!#6 N11097 P3997 BST 9 0x42800002 FP BE Pri
!#A N11096 N11097
!#6 N11098 P3997 BST 10 0x42800003 FP BE Pri
!#6 N11099 P3997 BST 11 0x42800004 FP BE Pri
!#6 N11100 P3997 BST 8 0x42800005 FP BE Pri
!#6 N11101 P3997 BST 9 0x42800006 FP BE Pri
!#A N11100 N11101
!#6 N11102 P3997 BST 10 0x42800007 FP BE Pri
!#6 N11103 P3997 BST 11 0x42800008 FP BE Pri
!#6 N11104 P3998 DWLD 28 -1 Int BE Pri
!#6 N11105 P3998 DWLD 29 -1 Int BE Pri
!#A N11104 N11105
!#6 N11106 P3998 DWLD 28 -1 Int BE Pri
!#6 N11107 P3998 DWLD 29 -1 Int BE Pri
!#A N11106 N11107
!#6 N11108 P3999 BLD 28 -1 FP BE Pri
!#6 N11109 P3999 BLD 29 -1 FP BE Pri
!#A N11108 N11109
!#6 N11110 P3999 BLD 30 -1 FP BE Pri
!#6 N11111 P3999 BLD 31 -1 FP BE Pri
!#6 N11112 P4000 SWAP 23 0xffffffff 0x3000007 Int BE Pri
!#6 N11113 P4001 LD 14 -1 Int BE Pri
!#6 N11114 P4002 LD 2 -1 Int BE Pri
!#6 N11115 P4003 BLD 28 -1 FP BE Pri
!#6 N11116 P4003 BLD 29 -1 FP BE Pri
!#A N11115 N11116
!#6 N11117 P4003 BLD 30 -1 FP BE Pri
!#6 N11118 P4003 BLD 31 -1 FP BE Pri
!#6 N11119 P4004 LD 21 -1 Int BE Pri
!#6 N11120 P4002 LD 2 -1 Int BE Pri
!#6 N11121 P4003 BLD 28 -1 FP BE Pri
!#6 N11122 P4003 BLD 29 -1 FP BE Pri
!#A N11121 N11122
!#6 N11123 P4003 BLD 30 -1 FP BE Pri
!#6 N11124 P4003 BLD 31 -1 FP BE Pri
!#6 N11125 P4004 LD 21 -1 Int BE Pri
!#6 N11126 P4005 DWLD 10 -1 Int BE Pri
!#6 N11127 P4006 LD 8 -1 Int BE Pri
!#6 N11128 P4005 DWLD 10 -1 Int BE Pri
!#6 N11129 P4006 LD 8 -1 Int BE Pri
!#6 N11130 P4007 LD 23 -1 Int BE Pri
!#6 N11131 P4008 SWAP 5 0xffffffff 0x3000008 Int LE Pri
!#6 N11132 P4009 DWST 14 0x3000009 Int BE Pri
!#6 N11133 P4010 BLD 28 -1 FP BE Pri
!#6 N11134 P4010 BLD 29 -1 FP BE Pri
!#A N11133 N11134
!#6 N11135 P4010 BLD 30 -1 FP BE Pri
!#6 N11136 P4010 BLD 31 -1 FP BE Pri
!#6 N11137 P4011 LD 8 -1 Int BE Pri
!#6 N11138 P4012 LD 13 -1 Int BE Pri
!#6 N11139 P4011 LD 8 -1 Int BE Pri
!#6 N11140 P4012 LD 13 -1 Int BE Pri
!#6 N11141 P4013 LD 28 -1 Int BE Pri
!#6 N11142 P4014 LD 7 -1 Int BE Pri
!#6 N11143 P4015 LD 7 -1 FP BE Pri
!#6 N11144 P4016 LD 31 -1 Int BE Pri
!#6 N11145 P4017 LD 0 -1 Int BE Pri
!#6 N11147 P4019 BLD 8 -1 FP BE Pri
!#6 N11148 P4019 BLD 9 -1 FP BE Pri
!#A N11147 N11148
!#6 N11149 P4019 BLD 10 -1 FP BE Pri
!#6 N11150 P4019 BLD 11 -1 FP BE Pri
!#6 N11151 P4020 DWST 8 0x300000a Int BE Pri
!#6 N11152 P4020 DWST 9 0x300000b Int BE Pri
!#A N11151 N11152
!#6 N11153 P4021 LD 17 -1 Int BE Pri
!#6 N11154 P4022 DWLD 6 -1 FP BE Pri
!#6 N11155 P4023 LD 3 -1 Int BE Pri
!#6 N11156 P4021 LD 17 -1 Int BE Pri
!#6 N11157 P4022 DWLD 6 -1 FP BE Pri
!#6 N11158 P4023 LD 3 -1 Int BE Pri
!#6 N11159 P4024 BLD 12 -1 FP BE Pri
!#6 N11160 P4024 BLD 13 -1 FP BE Pri
!#A N11159 N11160
!#6 N11161 P4024 BLD 14 -1 FP BE Pri
!#6 N11162 P4024 BLD 15 -1 FP BE Pri
!#6 N11163 P4024 BLD 12 -1 FP BE Pri
!#6 N11164 P4024 BLD 13 -1 FP BE Pri
!#A N11163 N11164
!#6 N11165 P4024 BLD 14 -1 FP BE Pri
!#6 N11166 P4024 BLD 15 -1 FP BE Pri
!#6 N11167 P4025 DWLD 2 -1 Int BE Pri
!#6 N11168 P4026 LD 11 -1 Int BE Pri
!#6 N11169 P4027 DWLD 16 -1 Int BE Pri
!#6 N11170 P4027 DWLD 17 -1 Int BE Pri
!#A N11169 N11170
!#6 N11171 P4028 BST 16 0x42800009 FP BE Pri
!#6 N11172 P4028 BST 17 0x4280000a FP BE Pri
!#A N11171 N11172
!#6 N11173 P4028 BST 18 0x4280000b FP BE Pri
!#6 N11174 P4028 BST 19 0x4280000c FP BE Pri
!#6 N11175 P4027 DWLD 16 -1 Int BE Pri
!#6 N11176 P4027 DWLD 17 -1 Int BE Pri
!#A N11175 N11176
!#6 N11177 P4028 BST 16 0x4280000d FP BE Pri
!#6 N11178 P4028 BST 17 0x4280000e FP BE Pri
!#A N11177 N11178
!#6 N11179 P4028 BST 18 0x4280000f FP BE Pri
!#6 N11180 P4028 BST 19 0x42800010 FP BE Pri
!#6 N11181 P4029 DWLD 2 -1 Int BE Pri
!#6 N11182 P4030 LD 9 -1 Int BE Pri
!#6 N11183 P4029 DWLD 2 -1 Int BE Pri
!#6 N11184 P4030 LD 9 -1 Int BE Pri
!#6 N11185 P4031 BLD 8 -1 FP BE Pri
!#6 N11186 P4031 BLD 9 -1 FP BE Pri
!#A N11185 N11186
!#6 N11187 P4031 BLD 10 -1 FP BE Pri
!#6 N11188 P4031 BLD 11 -1 FP BE Pri
!#6 N11189 P4031 BLD 8 -1 FP BE Pri
!#6 N11190 P4031 BLD 9 -1 FP BE Pri
!#A N11189 N11190
!#6 N11191 P4031 BLD 10 -1 FP BE Pri
!#6 N11192 P4031 BLD 11 -1 FP BE Pri
!#6 N11193 P4032 DWLD 15 -1 Int BE Pri
!#6 N11194 P4033 LD 23 -1 Int BE Pri
!#6 N11195 P4032 DWLD 15 -1 Int BE Pri
!#6 N11196 P4033 LD 23 -1 Int BE Pri
!#6 N11197 P4034 BLD 20 -1 FP BE Pri
!#6 N11198 P4034 BLD 21 -1 FP BE Pri
!#A N11197 N11198
!#6 N11199 P4034 BLD 22 -1 FP BE Pri
!#6 N11200 P4034 BLD 23 -1 FP BE Pri
!#6 N11201 P4035 ST 29 0x42800011 FP BE Pri
!#6 N11202 P4034 BLD 20 -1 FP BE Pri
!#6 N11203 P4034 BLD 21 -1 FP BE Pri
!#A N11202 N11203
!#6 N11204 P4034 BLD 22 -1 FP BE Pri
!#6 N11205 P4034 BLD 23 -1 FP BE Pri
!#6 N11206 P4035 ST 29 0x42800012 FP BE Pri
!#6 N11207 P4036 BLD 28 -1 FP BE Pri
!#6 N11208 P4036 BLD 29 -1 FP BE Pri
!#A N11207 N11208
!#6 N11209 P4036 BLD 30 -1 FP BE Pri
!#6 N11210 P4036 BLD 31 -1 FP BE Pri
!#6 N11211 P4037 DWLD 20 -1 Int BE Pri
!#6 N11212 P4037 DWLD 21 -1 Int BE Pri
!#A N11211 N11212
!#6 N11213 P4038 BLD 4 -1 FP BE Pri
!#6 N11214 P4038 BLD 5 -1 FP BE Pri
!#A N11213 N11214
!#6 N11215 P4038 BLD 6 -1 FP BE Pri
!#6 N11216 P4038 BLD 7 -1 FP BE Pri
!#6 N11217 P4039 BLD 20 -1 FP BE Pri
!#6 N11218 P4039 BLD 21 -1 FP BE Pri
!#A N11217 N11218
!#6 N11219 P4039 BLD 22 -1 FP BE Pri
!#6 N11220 P4039 BLD 23 -1 FP BE Pri
!#6 N11221 P4040 DWST 0 0x300000c Int BE Pri
!#6 N11222 P4040 DWST 1 0x300000d Int BE Pri
!#A N11221 N11222
!#6 N11223 P4041 LD 13 -1 Int BE Pri
!#6 N11224 P4041 CAS 13 -1 N11223 0x300000e Int BE Pri
!#6 N11225 P4040 DWST 0 0x300000f Int BE Pri
!#6 N11226 P4040 DWST 1 0x3000010 Int BE Pri
!#A N11225 N11226
!#6 N11227 P4041 LD 13 -1 Int BE Pri
!#6 N11228 P4041 CAS 13 -1 N11227 0x3000011 Int BE Pri
!#6 N11229 P4042 DWLD 12 -1 Int BE Pri
!#6 N11230 P4042 DWLD 13 -1 Int BE Pri
!#A N11229 N11230
!#6 N11231 P4042 DWLD 12 -1 Int BE Pri
!#6 N11232 P4042 DWLD 13 -1 Int BE Pri
!#A N11231 N11232
!#6 N11233 P4043 BLD 24 -1 FP BE Pri
!#6 N11234 P4043 BLD 25 -1 FP BE Pri
!#A N11233 N11234
!#6 N11235 P4043 BLD 26 -1 FP BE Pri
!#6 N11236 P4043 BLD 27 -1 FP BE Pri
!#6 N11237 P4044 DWLD 18 -1 Int BE Pri
!#6 N11238 P4045 LD 28 -1 Int BE Pri
!#6 N11239 P4043 BLD 24 -1 FP BE Pri
!#6 N11240 P4043 BLD 25 -1 FP BE Pri
!#A N11239 N11240
!#6 N11241 P4043 BLD 26 -1 FP BE Pri
!#6 N11242 P4043 BLD 27 -1 FP BE Pri
!#6 N11243 P4044 DWLD 18 -1 Int BE Pri
!#6 N11244 P4045 LD 28 -1 Int BE Pri
!#6 N11245 P4046 BLD 16 -1 FP BE Pri
!#6 N11246 P4046 BLD 17 -1 FP BE Pri
!#A N11245 N11246
!#6 N11247 P4046 BLD 18 -1 FP BE Pri
!#6 N11248 P4046 BLD 19 -1 FP BE Pri
!#6 N11249 P4047 LD 8 -1 Int BE Pri
!#6 N11250 P4048 LD 7 -1 Int BE Pri
!#6 N11251 P4046 BLD 16 -1 FP BE Pri
!#6 N11252 P4046 BLD 17 -1 FP BE Pri
!#A N11251 N11252
!#6 N11253 P4046 BLD 18 -1 FP BE Pri
!#6 N11254 P4046 BLD 19 -1 FP BE Pri
!#6 N11255 P4047 LD 8 -1 Int BE Pri
!#6 N11256 P4048 LD 7 -1 Int BE Pri
!#6 N11257 P4049 LD 26 -1 Int BE Pri
!#6 N11258 P4050 LD 15 -1 Int BE Pri
!#6 N11259 P4051 DWLD 19 -1 Int BE Pri
!#6 N11260 P4052 LD 31 -1 Int BE Pri
!#6 N11261 P4051 DWLD 19 -1 Int BE Pri
!#6 N11262 P4052 LD 31 -1 Int BE Pri
!#6 N11263 P4053 LD 9 -1 Int BE Pri
!#6 N11264 P4054 LD 18 -1 Int BE Pri
!#6 N11265 P4053 LD 9 -1 Int BE Pri
!#6 N11266 P4054 LD 18 -1 Int BE Pri
!#6 N11267 P4055 BLD 12 -1 FP BE Pri
!#6 N11268 P4055 BLD 13 -1 FP BE Pri
!#A N11267 N11268
!#6 N11269 P4055 BLD 14 -1 FP BE Pri
!#6 N11270 P4055 BLD 15 -1 FP BE Pri
!#6 N11271 P4055 BLD 12 -1 FP BE Pri
!#6 N11272 P4055 BLD 13 -1 FP BE Pri
!#A N11271 N11272
!#6 N11273 P4055 BLD 14 -1 FP BE Pri
!#6 N11274 P4055 BLD 15 -1 FP BE Pri
!#6 N11276 P4057 LD 5 -1 Int BE Pri
!#6 N11277 P4058 LD 26 -1 Int BE Pri
!#6 N11279 P4057 LD 5 -1 Int BE Pri
!#6 N11280 P4058 LD 26 -1 Int BE Pri
!#6 N11281 P4059 BLD 8 -1 FP BE Pri
!#6 N11282 P4059 BLD 9 -1 FP BE Pri
!#A N11281 N11282
!#6 N11283 P4059 BLD 10 -1 FP BE Pri
!#6 N11284 P4059 BLD 11 -1 FP BE Pri
!#6 N11285 P4059 BLD 8 -1 FP BE Pri
!#6 N11286 P4059 BLD 9 -1 FP BE Pri
!#A N11285 N11286
!#6 N11287 P4059 BLD 10 -1 FP BE Pri
!#6 N11288 P4059 BLD 11 -1 FP BE Pri
!#6 N11289 P4060 LD 24 -1 Int BE Pri
!#6 N11290 P4061 BLD 24 -1 FP BE Pri
!#6 N11291 P4061 BLD 25 -1 FP BE Pri
!#A N11290 N11291
!#6 N11292 P4061 BLD 26 -1 FP BE Pri
!#6 N11293 P4061 BLD 27 -1 FP BE Pri
!#6 N11294 P4062 LD 9 -1 Int BE Pri
!#6 N11295 P4060 LD 24 -1 Int BE Pri
!#6 N11296 P4061 BLD 24 -1 FP BE Pri
!#6 N11297 P4061 BLD 25 -1 FP BE Pri
!#A N11296 N11297
!#6 N11298 P4061 BLD 26 -1 FP BE Pri
!#6 N11299 P4061 BLD 27 -1 FP BE Pri
!#6 N11300 P4062 LD 9 -1 Int BE Pri
!#6 N11301 P4063 LD 4 -1 Int BE Pri
!#6 N11302 P4064 LD 21 -1 Int BE Pri
!#6 N11303 P4065 SWAP 4 0xffffffff 0x3000012 Int BE Pri
!#6 N11304 P4066 LD 30 -1 Int BE Pri
!#6 N11305 P4067 BLD 24 -1 FP BE Pri
!#6 N11306 P4067 BLD 25 -1 FP BE Pri
!#A N11305 N11306
!#6 N11307 P4067 BLD 26 -1 FP BE Pri
!#6 N11308 P4067 BLD 27 -1 FP BE Pri
!#6 N11309 P4068 BLD 20 -1 FP BE Pri
!#6 N11310 P4068 BLD 21 -1 FP BE Pri
!#A N11309 N11310
!#6 N11311 P4068 BLD 22 -1 FP BE Pri
!#6 N11312 P4068 BLD 23 -1 FP BE Pri
!#6 N11313 P4069 BLD 4 -1 FP BE Pri
!#6 N11314 P4069 BLD 5 -1 FP BE Pri
!#A N11313 N11314
!#6 N11315 P4069 BLD 6 -1 FP BE Pri
!#6 N11316 P4069 BLD 7 -1 FP BE Pri
!#6 N11317 P4070 BLD 12 -1 FP BE Pri
!#6 N11318 P4070 BLD 13 -1 FP BE Pri
!#A N11317 N11318
!#6 N11319 P4070 BLD 14 -1 FP BE Pri
!#6 N11320 P4070 BLD 15 -1 FP BE Pri
!#6 N11321 P4071 BSTC 16 0x42800013 FP BE Pri
!#6 N11322 P4071 BSTC 17 0x42800014 FP BE Pri
!#A N11321 N11322
!#6 N11323 P4071 BSTC 18 0x42800015 FP BE Pri
!#6 N11324 P4071 BSTC 19 0x42800016 FP BE Pri
!#6 N11325 P4071 BSTC 16 0x42800017 FP BE Pri
!#6 N11326 P4071 BSTC 17 0x42800018 FP BE Pri
!#A N11325 N11326
!#6 N11327 P4071 BSTC 18 0x42800019 FP BE Pri
!#6 N11328 P4071 BSTC 19 0x4280001a FP BE Pri
!#6 N11329 P4072 LD 31 -1 Int BE Pri
!#6 N11330 P4073 LD 19 -1 Int LE Pri
!#6 N11331 P4074 BLD 8 -1 FP BE Pri
!#6 N11332 P4074 BLD 9 -1 FP BE Pri
!#A N11331 N11332
!#6 N11333 P4074 BLD 10 -1 FP BE Pri
!#6 N11334 P4074 BLD 11 -1 FP BE Pri
!#6 N11335 P4074 BLD 8 -1 FP BE Pri
!#6 N11336 P4074 BLD 9 -1 FP BE Pri
!#A N11335 N11336
!#6 N11337 P4074 BLD 10 -1 FP BE Pri
!#6 N11338 P4074 BLD 11 -1 FP BE Pri
!#6 N11339 P4075 BLD 24 -1 FP BE Pri
!#6 N11340 P4075 BLD 25 -1 FP BE Pri
!#A N11339 N11340
!#6 N11341 P4075 BLD 26 -1 FP BE Pri
!#6 N11342 P4075 BLD 27 -1 FP BE Pri
!#6 N11343 P4076 BLD 12 -1 FP BE Pri
!#6 N11344 P4076 BLD 13 -1 FP BE Pri
!#A N11343 N11344
!#6 N11345 P4076 BLD 14 -1 FP BE Pri
!#6 N11346 P4076 BLD 15 -1 FP BE Pri
!#6 N11347 P4075 BLD 24 -1 FP BE Pri
!#6 N11348 P4075 BLD 25 -1 FP BE Pri
!#A N11347 N11348
!#6 N11349 P4075 BLD 26 -1 FP BE Pri
!#6 N11350 P4075 BLD 27 -1 FP BE Pri
!#6 N11351 P4076 BLD 12 -1 FP BE Pri
!#6 N11352 P4076 BLD 13 -1 FP BE Pri
!#A N11351 N11352
!#6 N11353 P4076 BLD 14 -1 FP BE Pri
!#6 N11354 P4076 BLD 15 -1 FP BE Pri
!#6 N11355 P4077 DWLD 24 -1 Int BE Pri
!#6 N11356 P4077 DWLD 25 -1 Int BE Pri
!#A N11355 N11356
!#6 N11357 P4078 BLD 0 -1 FP BE Pri
!#6 N11358 P4078 BLD 1 -1 FP BE Pri
!#A N11357 N11358
!#6 N11359 P4078 BLD 2 -1 FP BE Pri
!#6 N11360 P4078 BLD 3 -1 FP BE Pri
!#6 N11361 P4079 BLD 8 -1 FP BE Pri
!#6 N11362 P4079 BLD 9 -1 FP BE Pri
!#A N11361 N11362
!#6 N11363 P4079 BLD 10 -1 FP BE Pri
!#6 N11364 P4079 BLD 11 -1 FP BE Pri
!#6 N11365 P4079 BLD 8 -1 FP BE Pri
!#6 N11366 P4079 BLD 9 -1 FP BE Pri
!#A N11365 N11366
!#6 N11367 P4079 BLD 10 -1 FP BE Pri
!#6 N11368 P4079 BLD 11 -1 FP BE Pri
!#6 N11369 P4080 LD 23 -1 Int BE Pri
!#6 N11370 P4081 LD 17 -1 Int BE Pri
!#6 N11371 P4082 LD 3 -1 Int BE Pri
!#6 N11372 P4083 DWLD 6 -1 Int BE Pri
!#6 N11373 P4082 LD 3 -1 Int BE Pri
!#6 N11374 P4083 DWLD 6 -1 Int BE Pri
!#6 N11375 P4084 DWLD 24 -1 Int BE Pri
!#6 N11376 P4084 DWLD 25 -1 Int BE Pri
!#A N11375 N11376
!#6 N11377 P4085 SWAP 14 0xffffffff 0x3000013 Int BE Pri
!#6 N11378 P4086 LD 6 -1 Int BE Pri
!#6 N11379 P4085 SWAP 14 0xffffffff 0x3000014 Int BE Pri
!#6 N11380 P4086 LD 6 -1 Int BE Pri
!#6 N11381 P4087 BLD 16 -1 FP BE Pri
!#6 N11382 P4087 BLD 17 -1 FP BE Pri
!#A N11381 N11382
!#6 N11383 P4087 BLD 18 -1 FP BE Pri
!#6 N11384 P4087 BLD 19 -1 FP BE Pri
!#6 N11385 P4088 DWLD 16 -1 Int BE Pri
!#6 N11386 P4088 DWLD 17 -1 Int BE Pri
!#A N11385 N11386
!#6 N11387 P4087 BLD 16 -1 FP BE Pri
!#6 N11388 P4087 BLD 17 -1 FP BE Pri
!#A N11387 N11388
!#6 N11389 P4087 BLD 18 -1 FP BE Pri
!#6 N11390 P4087 BLD 19 -1 FP BE Pri
!#6 N11391 P4088 DWLD 16 -1 Int BE Pri
!#6 N11392 P4088 DWLD 17 -1 Int BE Pri
!#A N11391 N11392
!#6 N11393 P4089 LD 22 -1 Int BE Pri
!#6 N11394 P4090 LD 12 -1 Int BE Pri
!#6 N11395 P4089 LD 22 -1 Int BE Pri
!#6 N11396 P4090 LD 12 -1 Int BE Pri
!#6 N11397 P4091 DWLD 3 -1 Int BE Pri
!#6 N11398 P4092 LD 12 -1 Int BE Pri
!#6 N11399 P4093 BLD 4 -1 FP BE Pri
!#6 N11400 P4093 BLD 5 -1 FP BE Pri
!#A N11399 N11400
!#6 N11401 P4093 BLD 6 -1 FP BE Pri
!#6 N11402 P4093 BLD 7 -1 FP BE Pri
!#6 N11403 P4094 MEMBAR
!#6 N11404 P4095 LD 11 -1 Int BE Pri
!#6 N11405 P4096 BLD 16 -1 FP BE Pri
!#6 N11406 P4096 BLD 17 -1 FP BE Pri
!#A N11405 N11406
!#6 N11407 P4096 BLD 18 -1 FP BE Pri
!#6 N11408 P4096 BLD 19 -1 FP BE Pri
!#6 N11409 P4097 LD 18 -1 Int BE Pri
!#6 N11410 P4098 DWLD 6 -1 Int BE Pri
!#6 N11411 P4099 BLD 0 -1 FP BE Pri
!#6 N11412 P4099 BLD 1 -1 FP BE Pri
!#A N11411 N11412
!#6 N11413 P4099 BLD 2 -1 FP BE Pri
!#6 N11414 P4099 BLD 3 -1 FP BE Pri
!#6 N11415 P4100 LD 21 -1 Int BE Pri
!#6 N11416 P4101 DWLD 19 -1 FP BE Pri
!#6 N11417 P4102 LD 21 -1 Int BE Pri
!#6 N11418 P4103 LD 25 -1 Int BE Pri
!#6 N11419 P4104 LD 3 -1 Int BE Pri
!#6 N11420 P4105 LD 25 -1 Int BE Pri
!#6 N11421 P4104 LD 3 -1 Int BE Pri
!#6 N11422 P4105 LD 25 -1 Int BE Pri
!#6 N11423 P4106 LD 2 -1 Int BE Pri
!#6 N11424 P4107 LD 4 -1 Int BE Pri
!#6 N11425 P4108 LD 28 -1 Int BE Pri
!#6 N11426 P4109 DWLD 15 -1 Int BE Pri
!#6 N11427 P4110 DWLD 19 -1 Int BE Pri
!#6 N11428 P4111 LD 13 -1 Int BE Pri
!#6 N11429 P4110 DWLD 19 -1 Int BE Pri
!#6 N11430 P4111 LD 13 -1 Int BE Pri
!#6 N11431 P4112 BLD 24 -1 FP BE Pri
!#6 N11432 P4112 BLD 25 -1 FP BE Pri
!#A N11431 N11432
!#6 N11433 P4112 BLD 26 -1 FP BE Pri
!#6 N11434 P4112 BLD 27 -1 FP BE Pri
!#6 N11435 P4113 ST 26 0x3000015 Int BE Pri
!#6 N11436 P4112 BLD 24 -1 FP BE Pri
!#6 N11437 P4112 BLD 25 -1 FP BE Pri
!#A N11436 N11437
!#6 N11438 P4112 BLD 26 -1 FP BE Pri
!#6 N11439 P4112 BLD 27 -1 FP BE Pri
!#6 N11440 P4113 ST 26 0x3000016 Int BE Pri
!#6 N11441 P4114 BLD 0 -1 FP BE Pri
!#6 N11442 P4114 BLD 1 -1 FP BE Pri
!#A N11441 N11442
!#6 N11443 P4114 BLD 2 -1 FP BE Pri
!#6 N11444 P4114 BLD 3 -1 FP BE Pri
!#6 N11445 P4114 BLD 0 -1 FP BE Pri
!#6 N11446 P4114 BLD 1 -1 FP BE Pri
!#A N11445 N11446
!#6 N11447 P4114 BLD 2 -1 FP BE Pri
!#6 N11448 P4114 BLD 3 -1 FP BE Pri
!#6 N11449 P4115 DWLD 14 -1 Int BE Pri
!#6 N11450 P4116 LD 26 -1 Int LE Pri
!#6 N11451 P4117 DWLD 14 -1 Int BE Pri
!#6 N11452 P4118 LD 27 -1 Int BE Pri
!#6 N11453 P4117 DWLD 14 -1 Int BE Pri
!#6 N11454 P4118 LD 27 -1 Int BE Pri
!#6 N11455 P4119 ST 12 0x3000017 Int BE Pri
!#6 N11456 P4119 ST 12 0x3000018 Int BE Pri
!#6 N11457 P4120 DWLD 2 -1 Int BE Pri
!#6 N11458 P4121 BSTC 16 0x4280001b FP BE Pri
!#6 N11459 P4121 BSTC 17 0x4280001c FP BE Pri
!#A N11458 N11459
!#6 N11460 P4121 BSTC 18 0x4280001d FP BE Pri
!#6 N11461 P4121 BSTC 19 0x4280001e FP BE Pri
!#6 N11462 P4122 LD 21 -1 Int BE Pri
!#6 N11463 P4123 DWLD 16 -1 Int BE Pri
!#6 N11464 P4123 DWLD 17 -1 Int BE Pri
!#A N11463 N11464
!#6 N11465 P4124 BLD 16 -1 FP BE Pri
!#6 N11466 P4124 BLD 17 -1 FP BE Pri
!#A N11465 N11466
!#6 N11467 P4124 BLD 18 -1 FP BE Pri
!#6 N11468 P4124 BLD 19 -1 FP BE Pri
!#6 N11469 P4124 BLD 16 -1 FP BE Pri
!#6 N11470 P4124 BLD 17 -1 FP BE Pri
!#A N11469 N11470
!#6 N11471 P4124 BLD 18 -1 FP BE Pri
!#6 N11472 P4124 BLD 19 -1 FP BE Pri
!#6 N11473 P4125 DWLD 31 -1 FP BE Pri
!#6 N11474 P4126 BLD 12 -1 FP BE Pri
!#6 N11475 P4126 BLD 13 -1 FP BE Pri
!#A N11474 N11475
!#6 N11476 P4126 BLD 14 -1 FP BE Pri
!#6 N11477 P4126 BLD 15 -1 FP BE Pri
!#6 N11478 P4127 LD 4 -1 Int BE Pri
!#6 N11479 P4128 LD 19 -1 Int BE Pri
!#6 N11480 P4129 BLD 20 -1 FP BE Pri
!#6 N11481 P4129 BLD 21 -1 FP BE Pri
!#A N11480 N11481
!#6 N11482 P4129 BLD 22 -1 FP BE Pri
!#6 N11483 P4129 BLD 23 -1 FP BE Pri
!#6 N11484 P4130 DWLD 22 -1 Int BE Pri
!#6 N11485 P4131 LD 28 -1 Int BE Pri
!#6 N11486 P4129 BLD 20 -1 FP BE Pri
!#6 N11487 P4129 BLD 21 -1 FP BE Pri
!#A N11486 N11487
!#6 N11488 P4129 BLD 22 -1 FP BE Pri
!#6 N11489 P4129 BLD 23 -1 FP BE Pri
!#6 N11490 P4130 DWLD 22 -1 Int BE Pri
!#6 N11491 P4131 LD 28 -1 Int BE Pri
!#6 N11492 P4132 DWLD 24 -1 Int BE Pri
!#6 N11493 P4132 DWLD 25 -1 Int BE Pri
!#A N11492 N11493
!#6 N11494 P4132 DWLD 24 -1 Int BE Pri
!#6 N11495 P4132 DWLD 25 -1 Int BE Pri
!#A N11494 N11495
!#6 N11496 P4133 BLD 20 -1 FP BE Pri
!#6 N11497 P4133 BLD 21 -1 FP BE Pri
!#A N11496 N11497
!#6 N11498 P4133 BLD 22 -1 FP BE Pri
!#6 N11499 P4133 BLD 23 -1 FP BE Pri
!#6 N11500 P4133 BLD 20 -1 FP BE Pri
!#6 N11501 P4133 BLD 21 -1 FP BE Pri
!#A N11500 N11501
!#6 N11502 P4133 BLD 22 -1 FP BE Pri
!#6 N11503 P4133 BLD 23 -1 FP BE Pri
!#6 N11505 P4135 BLD 12 -1 FP BE Pri
!#6 N11506 P4135 BLD 13 -1 FP BE Pri
!#A N11505 N11506
!#6 N11507 P4135 BLD 14 -1 FP BE Pri
!#6 N11508 P4135 BLD 15 -1 FP BE Pri
!#6 N11509 P4136 BLD 8 -1 FP BE Pri
!#6 N11510 P4136 BLD 9 -1 FP BE Pri
!#A N11509 N11510
!#6 N11511 P4136 BLD 10 -1 FP BE Pri
!#6 N11512 P4136 BLD 11 -1 FP BE Pri
!#6 N11513 P4135 BLD 12 -1 FP BE Pri
!#6 N11514 P4135 BLD 13 -1 FP BE Pri
!#A N11513 N11514
!#6 N11515 P4135 BLD 14 -1 FP BE Pri
!#6 N11516 P4135 BLD 15 -1 FP BE Pri
!#6 N11517 P4136 BLD 8 -1 FP BE Pri
!#6 N11518 P4136 BLD 9 -1 FP BE Pri
!#A N11517 N11518
!#6 N11519 P4136 BLD 10 -1 FP BE Pri
!#6 N11520 P4136 BLD 11 -1 FP BE Pri
!#6 N11521 P4137 BLD 28 -1 FP BE Pri
!#6 N11522 P4137 BLD 29 -1 FP BE Pri
!#A N11521 N11522
!#6 N11523 P4137 BLD 30 -1 FP BE Pri
!#6 N11524 P4137 BLD 31 -1 FP BE Pri
!#6 N11525 P4138 DWLD 16 -1 Int BE Pri
!#6 N11526 P4138 DWLD 17 -1 Int BE Pri
!#A N11525 N11526
!#6 N11527 P4139 DWLD 22 -1 Int BE Pri
!#6 N11528 P4140 DWLD 7 -1 Int BE Pri
!#6 N11529 P4139 DWLD 22 -1 Int BE Pri
!#6 N11530 P4140 DWLD 7 -1 Int BE Pri
!#6 N11531 P4141 DWLD 16 -1 Int BE Pri
!#6 N11532 P4141 DWLD 17 -1 Int BE Pri
!#A N11531 N11532
!#6 N11533 P4141 DWLD 16 -1 Int BE Pri
!#6 N11534 P4141 DWLD 17 -1 Int BE Pri
!#A N11533 N11534
!#6 N11535 P4142 BLD 16 -1 FP BE Pri
!#6 N11536 P4142 BLD 17 -1 FP BE Pri
!#A N11535 N11536
!#6 N11537 P4142 BLD 18 -1 FP BE Pri
!#6 N11538 P4142 BLD 19 -1 FP BE Pri
!#6 N11539 P4143 LD 17 -1 Int BE Pri
!#6 N11540 P4144 LD 16 -1 Int BE Pri
!#6 N11541 P4145 BLD 16 -1 FP BE Pri
!#6 N11542 P4145 BLD 17 -1 FP BE Pri
!#A N11541 N11542
!#6 N11543 P4145 BLD 18 -1 FP BE Pri
!#6 N11544 P4145 BLD 19 -1 FP BE Pri
!#6 N11545 P4146 DWLD 20 -1 Int BE Pri
!#6 N11546 P4146 DWLD 21 -1 Int BE Pri
!#A N11545 N11546
!#6 N11547 P4147 BLD 16 -1 FP BE Pri
!#6 N11548 P4147 BLD 17 -1 FP BE Pri
!#A N11547 N11548
!#6 N11549 P4147 BLD 18 -1 FP BE Pri
!#6 N11550 P4147 BLD 19 -1 FP BE Pri
!#6 N11551 P4148 DWLD 28 -1 Int BE Pri
!#6 N11552 P4148 DWLD 29 -1 Int BE Pri
!#A N11551 N11552
!#6 N11553 P4149 BLD 24 -1 FP BE Pri
!#6 N11554 P4149 BLD 25 -1 FP BE Pri
!#A N11553 N11554
!#6 N11555 P4149 BLD 26 -1 FP BE Pri
!#6 N11556 P4149 BLD 27 -1 FP BE Pri
!#6 N11557 P4150 BLD 16 -1 FP BE Pri
!#6 N11558 P4150 BLD 17 -1 FP BE Pri
!#A N11557 N11558
!#6 N11559 P4150 BLD 18 -1 FP BE Pri
!#6 N11560 P4150 BLD 19 -1 FP BE Pri
!#6 N11561 P4149 BLD 24 -1 FP BE Pri
!#6 N11562 P4149 BLD 25 -1 FP BE Pri
!#A N11561 N11562
!#6 N11563 P4149 BLD 26 -1 FP BE Pri
!#6 N11564 P4149 BLD 27 -1 FP BE Pri
!#6 N11565 P4150 BLD 16 -1 FP BE Pri
!#6 N11566 P4150 BLD 17 -1 FP BE Pri
!#A N11565 N11566
!#6 N11567 P4150 BLD 18 -1 FP BE Pri
!#6 N11568 P4150 BLD 19 -1 FP BE Pri
!#6 N11569 P4151 BLD 16 -1 FP BE Pri
!#6 N11570 P4151 BLD 17 -1 FP BE Pri
!#A N11569 N11570
!#6 N11571 P4151 BLD 18 -1 FP BE Pri
!#6 N11572 P4151 BLD 19 -1 FP BE Pri
!#6 N11573 P4152 LD 10 -1 Int BE Pri
!#6 N11574 P4153 LD 2 -1 Int BE Pri
!#6 N11575 P4154 DWLD 0 -1 Int BE Pri
!#6 N11576 P4154 DWLD 1 -1 Int BE Pri
!#A N11575 N11576
!#6 N11577 P4154 DWLD 0 -1 Int BE Pri
!#6 N11578 P4154 DWLD 1 -1 Int BE Pri
!#A N11577 N11578
!#6 N11579 P4155 BLD 0 -1 FP BE Pri
!#6 N11580 P4155 BLD 1 -1 FP BE Pri
!#A N11579 N11580
!#6 N11581 P4155 BLD 2 -1 FP BE Pri
!#6 N11582 P4155 BLD 3 -1 FP BE Pri
!#6 N11583 P4155 BLD 0 -1 FP BE Pri
!#6 N11584 P4155 BLD 1 -1 FP BE Pri
!#A N11583 N11584
!#6 N11585 P4155 BLD 2 -1 FP BE Pri
!#6 N11586 P4155 BLD 3 -1 FP BE Pri
!#6 N11587 P4156 BSTC 8 0x4280001f FP BE Pri
!#6 N11588 P4156 BSTC 9 0x42800020 FP BE Pri
!#A N11587 N11588
!#6 N11589 P4156 BSTC 10 0x42800021 FP BE Pri
!#6 N11590 P4156 BSTC 11 0x42800022 FP BE Pri
!#6 N11591 P4157 LD 8 -1 Int BE Pri
!#6 N11592 P4158 LD 31 -1 Int BE Pri
!#6 N11593 P4159 BLD 28 -1 FP BE Pri
!#6 N11594 P4159 BLD 29 -1 FP BE Pri
!#A N11593 N11594
!#6 N11595 P4159 BLD 30 -1 FP BE Pri
!#6 N11596 P4159 BLD 31 -1 FP BE Pri
!#6 N11597 P4160 DWLD 4 -1 Int BE Pri
!#6 N11598 P4160 DWLD 5 -1 Int BE Pri
!#A N11597 N11598
!#6 N11599 P4161 LD 18 -1 Int BE Pri
!#6 N11600 P4162 LD 7 -1 Int BE Pri
!#6 N11601 P4163 LD 9 -1 Int BE Pri
!#6 N11602 P4164 LD 6 -1 Int BE Pri
!#6 N11603 P4165 LD 2 -1 Int BE Pri
!#6 N11604 P4166 LD 27 -1 Int BE Pri
!#6 N11605 P4167 LD 17 -1 Int BE Pri
!#6 N11606 P4168 LD 12 -1 Int BE Pri
!#6 N11607 P4167 LD 17 -1 Int BE Pri
!#6 N11608 P4168 LD 12 -1 Int BE Pri
!#6 N11609 P4169 LD 19 -1 Int BE Pri
!#6 N11610 P4170 BLD 16 -1 FP BE Pri
!#6 N11611 P4170 BLD 17 -1 FP BE Pri
!#A N11610 N11611
!#6 N11612 P4170 BLD 18 -1 FP BE Pri
!#6 N11613 P4170 BLD 19 -1 FP BE Pri
!#6 N11614 P4171 LD 0 -1 Int BE Pri
!#6 N11615 P4172 LD 16 -1 Int BE Pri
!#6 N11616 P4173 DWLD 4 -1 FP BE Pri
!#6 N11617 P4173 DWLD 5 -1 FP BE Pri
!#A N11616 N11617
!#6 N11618 P4174 LD 6 -1 Int BE Pri
!#6 N11619 P4172 LD 16 -1 Int BE Pri
!#6 N11620 P4173 DWLD 4 -1 FP BE Pri
!#6 N11621 P4173 DWLD 5 -1 FP BE Pri
!#A N11620 N11621
!#6 N11622 P4174 LD 6 -1 Int BE Pri
!#6 N11623 P4175 DWLD 19 -1 Int BE Pri
!#6 N11624 P4176 LD 5 -1 Int BE Pri
!#6 N11625 P4177 LD 27 -1 Int BE Pri
!#6 N11626 P4178 LD 18 -1 Int BE Pri
!#6 N11627 P4177 LD 27 -1 Int BE Pri
!#6 N11628 P4178 LD 18 -1 Int BE Pri
!#6 N11629 P4179 LD 26 -1 Int BE Pri
!#6 N11630 P4180 BLD 0 -1 FP BE Pri
!#6 N11631 P4180 BLD 1 -1 FP BE Pri
!#A N11630 N11631
!#6 N11632 P4180 BLD 2 -1 FP BE Pri
!#6 N11633 P4180 BLD 3 -1 FP BE Pri
!#6 N11634 P4181 LD 21 -1 Int BE Pri
!#6 N11635 P4179 LD 26 -1 Int BE Pri
!#6 N11636 P4180 BLD 0 -1 FP BE Pri
!#6 N11637 P4180 BLD 1 -1 FP BE Pri
!#A N11636 N11637
!#6 N11638 P4180 BLD 2 -1 FP BE Pri
!#6 N11639 P4180 BLD 3 -1 FP BE Pri
!#6 N11640 P4181 LD 21 -1 Int BE Pri
!#6 N11641 P4182 DWLD 30 -1 Int BE Pri
!#6 N11642 P4183 BLD 28 -1 FP BE Pri
!#6 N11643 P4183 BLD 29 -1 FP BE Pri
!#A N11642 N11643
!#6 N11644 P4183 BLD 30 -1 FP BE Pri
!#6 N11645 P4183 BLD 31 -1 FP BE Pri
!#6 N11646 P4184 LD 2 -1 Int BE Pri
!#6 N11647 P4182 DWLD 30 -1 Int BE Pri
!#6 N11648 P4183 BLD 28 -1 FP BE Pri
!#6 N11649 P4183 BLD 29 -1 FP BE Pri
!#A N11648 N11649
!#6 N11650 P4183 BLD 30 -1 FP BE Pri
!#6 N11651 P4183 BLD 31 -1 FP BE Pri
!#6 N11652 P4184 LD 2 -1 Int BE Pri
!#6 N11653 P4185 DWLD 22 -1 Int BE Pri
!#6 N11654 P4186 LD 1 -1 Int BE Pri
!#6 N11655 P4187 BLD 28 -1 FP BE Pri
!#6 N11656 P4187 BLD 29 -1 FP BE Pri
!#A N11655 N11656
!#6 N11657 P4187 BLD 30 -1 FP BE Pri
!#6 N11658 P4187 BLD 31 -1 FP BE Pri
!#6 N11659 P4188 MEMBAR
!#6 N11660 P4187 BLD 28 -1 FP BE Pri
!#6 N11661 P4187 BLD 29 -1 FP BE Pri
!#A N11660 N11661
!#6 N11662 P4187 BLD 30 -1 FP BE Pri
!#6 N11663 P4187 BLD 31 -1 FP BE Pri
!#6 N11664 P4188 MEMBAR
!#6 N11665 P4189 BLD 16 -1 FP BE Pri
!#6 N11666 P4189 BLD 17 -1 FP BE Pri
!#A N11665 N11666
!#6 N11667 P4189 BLD 18 -1 FP BE Pri
!#6 N11668 P4189 BLD 19 -1 FP BE Pri
!#6 N11669 P4190 LD 28 -1 Int BE Pri
!#6 N11670 P4191 LD 29 -1 Int BE Pri
!#6 N11671 P4192 BLD 16 -1 FP BE Pri
!#6 N11672 P4192 BLD 17 -1 FP BE Pri
!#A N11671 N11672
!#6 N11673 P4192 BLD 18 -1 FP BE Pri
!#6 N11674 P4192 BLD 19 -1 FP BE Pri
!#6 N11675 P4193 BLD 12 -1 FP BE Pri
!#6 N11676 P4193 BLD 13 -1 FP BE Pri
!#A N11675 N11676
!#6 N11677 P4193 BLD 14 -1 FP BE Pri
!#6 N11678 P4193 BLD 15 -1 FP BE Pri
!#6 N11679 P4193 BLD 12 -1 FP BE Pri
!#6 N11680 P4193 BLD 13 -1 FP BE Pri
!#A N11679 N11680
!#6 N11681 P4193 BLD 14 -1 FP BE Pri
!#6 N11682 P4193 BLD 15 -1 FP BE Pri
!#6 N11683 P4194 DWLD 24 -1 Int BE Pri
!#6 N11684 P4194 DWLD 25 -1 Int BE Pri
!#A N11683 N11684
!#6 N11685 P4195 DWLD 23 -1 Int BE Pri
!#6 N11686 P4196 LD 21 -1 Int BE Pri
!#6 N11687 P4197 BST 8 0x42800023 FP BE Pri
!#6 N11688 P4197 BST 9 0x42800024 FP BE Pri
!#A N11687 N11688
!#6 N11689 P4197 BST 10 0x42800025 FP BE Pri
!#6 N11690 P4197 BST 11 0x42800026 FP BE Pri
!#6 N11691 P4197 BST 8 0x42800027 FP BE Pri
!#6 N11692 P4197 BST 9 0x42800028 FP BE Pri
!#A N11691 N11692
!#6 N11693 P4197 BST 10 0x42800029 FP BE Pri
!#6 N11694 P4197 BST 11 0x4280002a FP BE Pri
!#6 N11695 P4198 BLD 0 -1 FP BE Pri
!#6 N11696 P4198 BLD 1 -1 FP BE Pri
!#A N11695 N11696
!#6 N11697 P4198 BLD 2 -1 FP BE Pri
!#6 N11698 P4198 BLD 3 -1 FP BE Pri
!#6 N11699 P4199 DWLD 23 -1 Int BE Pri
!#6 N11700 P4200 BLD 8 -1 FP BE Pri
!#6 N11701 P4200 BLD 9 -1 FP BE Pri
!#A N11700 N11701
!#6 N11702 P4200 BLD 10 -1 FP BE Pri
!#6 N11703 P4200 BLD 11 -1 FP BE Pri
!#6 N11704 P4201 LD 21 -1 Int BE Pri
!#6 N11705 P4202 DWLD 24 -1 Int BE Pri
!#6 N11706 P4202 DWLD 25 -1 Int BE Pri
!#A N11705 N11706
!#6 N11707 P4203 LD 26 -1 Int BE Pri
!#6 N11708 P4204 LD 29 -1 Int BE Pri
!#6 N11709 P4202 DWLD 24 -1 Int BE Pri
!#6 N11710 P4202 DWLD 25 -1 Int BE Pri
!#A N11709 N11710
!#6 N11711 P4203 LD 26 -1 Int BE Pri
!#6 N11712 P4204 LD 29 -1 Int BE Pri
!#6 N11713 P4205 DWLD 10 -1 Int BE Pri
!#6 N11714 P4206 LD 9 -1 Int BE Pri
!#6 N11715 P4207 LD 6 -1 Int BE Pri
!#6 N11716 P4208 ST 5 0x3000019 Int BE Pri
!#6 N11717 P4209 LD 3 -1 Int BE Pri
!#6 N11718 P4207 LD 6 -1 Int BE Pri
!#6 N11719 P4208 ST 5 0x300001a Int BE Pri
!#6 N11720 P4209 LD 3 -1 Int BE Pri
!#6 N11721 P4210 DWLD 12 -1 Int BE Pri
!#6 N11722 P4210 DWLD 13 -1 Int BE Pri
!#A N11721 N11722
!#6 N11723 P4210 DWLD 12 -1 Int BE Pri
!#6 N11724 P4210 DWLD 13 -1 Int BE Pri
!#A N11723 N11724
!#6 N11725 P4211 DWLD 14 -1 Int BE Pri
!#6 N11726 P4212 LD 9 -1 Int BE Pri
!#6 N11727 P4213 BLD 28 -1 FP BE Pri
!#6 N11728 P4213 BLD 29 -1 FP BE Pri
!#A N11727 N11728
!#6 N11729 P4213 BLD 30 -1 FP BE Pri
!#6 N11730 P4213 BLD 31 -1 FP BE Pri
!#6 N11731 P4214 DWLD 15 -1 Int BE Pri
!#6 N11732 P4215 DWST 14 0x300001b Int BE Pri
!#6 N11733 P4216 LD 5 -1 Int BE Pri
!#6 N11734 P4214 DWLD 15 -1 Int BE Pri
!#6 N11735 P4215 DWST 14 0x300001c Int BE Pri
!#6 N11736 P4216 LD 5 -1 Int BE Pri
!#6 N11737 P4217 BLD 4 -1 FP BE Pri
!#6 N11738 P4217 BLD 5 -1 FP BE Pri
!#A N11737 N11738
!#6 N11739 P4217 BLD 6 -1 FP BE Pri
!#6 N11740 P4217 BLD 7 -1 FP BE Pri
!#6 N11741 P4218 LD 19 -1 Int LE Pri
!#6 N11742 P4219 DWLD 15 -1 Int BE Pri
!#6 N11743 P4220 BLD 20 -1 FP BE Pri
!#6 N11744 P4220 BLD 21 -1 FP BE Pri
!#A N11743 N11744
!#6 N11745 P4220 BLD 22 -1 FP BE Pri
!#6 N11746 P4220 BLD 23 -1 FP BE Pri
!#6 N11747 P4221 LD 1 -1 Int BE Pri
!#6 N11748 P4222 DWLD 12 -1 Int BE Pri
!#6 N11749 P4222 DWLD 13 -1 Int BE Pri
!#A N11748 N11749
!#6 N11750 P4223 LD 30 -1 Int BE Pri
!#6 N11751 P4224 LD 6 -1 Int BE Pri
!#6 N11752 P4225 LD 4 -1 Int BE Pri
!#6 N11753 P4226 LD 3 -1 FP BE Pri
!#6 N11754 P4226 LD 3 -1 FP BE Pri
!#6 N11755 P4227 LD 11 -1 Int BE Pri
!#6 N11756 P4228 DWLD 7 -1 Int BE Pri
!#6 N11757 P4227 LD 11 -1 Int BE Pri
!#6 N11758 P4228 DWLD 7 -1 Int BE Pri
!#6 N11759 P4229 BLD 20 -1 FP BE Pri
!#6 N11760 P4229 BLD 21 -1 FP BE Pri
!#A N11759 N11760
!#6 N11761 P4229 BLD 22 -1 FP BE Pri
!#6 N11762 P4229 BLD 23 -1 FP BE Pri
!#6 N11763 P4230 LD 27 -1 Int BE Pri
!#6 N11764 P4231 LD 22 -1 Int BE Pri
!#6 N11766 P4233 DWLD 19 -1 Int BE Pri
!#6 N11767 P4234 LD 24 -1 Int BE Pri
!#6 N11768 P4235 LD 31 -1 Int LE Pri
!#6 N11769 P4236 LD 13 -1 Int BE Pri
!#6 N11770 P4235 LD 31 -1 Int LE Pri
!#6 N11771 P4236 LD 13 -1 Int BE Pri
!#6 N11772 P4237 DWLD 10 -1 FP BE Pri
!#6 N11773 P4237 DWLD 10 -1 FP BE Pri
!#6 N11774 P4238 DWLD 26 -1 Int BE Pri
!#6 N11775 P4239 LD 2 -1 Int BE Pri
!#6 N11776 P4238 DWLD 26 -1 Int BE Pri
!#6 N11777 P4239 LD 2 -1 Int BE Pri
!#6 N11778 P4240 LD 12 -1 Int BE Pri
!#6 N11779 P4241 LD 7 -1 Int BE Pri
!#6 N11780 P4240 LD 12 -1 Int BE Pri
!#6 N11781 P4241 LD 7 -1 Int BE Pri
!#6 N11782 P4242 DWLD 8 -1 Int BE Pri
!#6 N11783 P4242 DWLD 9 -1 Int BE Pri
!#A N11782 N11783
!#6 N11784 P4243 LD 6 -1 Int BE Pri
!#6 N11785 P4244 LD 30 -1 Int BE Pri
!#6 N11786 P4242 DWLD 8 -1 Int BE Pri
!#6 N11787 P4242 DWLD 9 -1 Int BE Pri
!#A N11786 N11787
!#6 N11788 P4243 LD 6 -1 Int BE Pri
!#6 N11789 P4244 LD 30 -1 Int BE Pri
!#6 N11790 P4245 LD 27 -1 FP BE Pri
!#6 N11791 P4246 BLD 16 -1 FP BE Pri
!#6 N11792 P4246 BLD 17 -1 FP BE Pri
!#A N11791 N11792
!#6 N11793 P4246 BLD 18 -1 FP BE Pri
!#6 N11794 P4246 BLD 19 -1 FP BE Pri
!#6 N11795 P4247 BLD 28 -1 FP BE Pri
!#6 N11796 P4247 BLD 29 -1 FP BE Pri
!#A N11795 N11796
!#6 N11797 P4247 BLD 30 -1 FP BE Pri
!#6 N11798 P4247 BLD 31 -1 FP BE Pri
!#6 N11799 P4248 BLD 16 -1 FP BE Pri
!#6 N11800 P4248 BLD 17 -1 FP BE Pri
!#A N11799 N11800
!#6 N11801 P4248 BLD 18 -1 FP BE Pri
!#6 N11802 P4248 BLD 19 -1 FP BE Pri
!#6 N11803 P4249 LD 22 -1 Int BE Pri
!#6 N11804 P4250 LD 13 -1 Int BE Pri
!#6 N11805 P4248 BLD 16 -1 FP BE Pri
!#6 N11806 P4248 BLD 17 -1 FP BE Pri
!#A N11805 N11806
!#6 N11807 P4248 BLD 18 -1 FP BE Pri
!#6 N11808 P4248 BLD 19 -1 FP BE Pri
!#6 N11809 P4249 LD 22 -1 Int BE Pri
!#6 N11810 P4250 LD 13 -1 Int BE Pri
!#6 N11811 P4251 DWLD 20 -1 Int BE Pri
!#6 N11812 P4251 DWLD 21 -1 Int BE Pri
!#A N11811 N11812
!#6 N11813 P4252 DWLD 6 -1 Int BE Pri
!#6 N11814 P4253 LD 19 -1 Int BE Pri
!#6 N11815 P4254 BLD 12 -1 FP BE Pri
!#6 N11816 P4254 BLD 13 -1 FP BE Pri
!#A N11815 N11816
!#6 N11817 P4254 BLD 14 -1 FP BE Pri
!#6 N11818 P4254 BLD 15 -1 FP BE Pri
!#6 N11819 P4255 LD 31 -1 Int BE Pri
!#6 N11820 P4256 LD 20 -1 Int BE Pri
!#6 N11821 P4254 BLD 12 -1 FP BE Pri
!#6 N11822 P4254 BLD 13 -1 FP BE Pri
!#A N11821 N11822
!#6 N11823 P4254 BLD 14 -1 FP BE Pri
!#6 N11824 P4254 BLD 15 -1 FP BE Pri
!#6 N11825 P4255 LD 31 -1 Int BE Pri
!#6 N11826 P4256 LD 20 -1 Int BE Pri
!#6 N11827 P4257 LD 25 -1 Int BE Pri
!#6 N11828 P4258 LD 20 -1 Int BE Pri
!#6 N11829 P4257 LD 25 -1 Int BE Pri
!#6 N11830 P4258 LD 20 -1 Int BE Pri
!#6 N11831 P4259 LD 3 -1 Int BE Pri
!#6 N11832 P4260 LD 1 -1 Int BE Pri
!#6 N11833 P4261 BLD 12 -1 FP BE Pri
!#6 N11834 P4261 BLD 13 -1 FP BE Pri
!#A N11833 N11834
!#6 N11835 P4261 BLD 14 -1 FP BE Pri
!#6 N11836 P4261 BLD 15 -1 FP BE Pri
!#6 N11837 P4261 BLD 12 -1 FP BE Pri
!#6 N11838 P4261 BLD 13 -1 FP BE Pri
!#A N11837 N11838
!#6 N11839 P4261 BLD 14 -1 FP BE Pri
!#6 N11840 P4261 BLD 15 -1 FP BE Pri
!#6 N11841 P4262 BLD 20 -1 FP BE Pri
!#6 N11842 P4262 BLD 21 -1 FP BE Pri
!#A N11841 N11842
!#6 N11843 P4262 BLD 22 -1 FP BE Pri
!#6 N11844 P4262 BLD 23 -1 FP BE Pri
!#6 N11845 P4263 LD 16 -1 Int BE Pri
!#6 N11846 P4264 DWLD 14 -1 Int BE Pri
!#6 N11847 P4265 BLD 4 -1 FP BE Pri
!#6 N11848 P4265 BLD 5 -1 FP BE Pri
!#A N11847 N11848
!#6 N11849 P4265 BLD 6 -1 FP BE Pri
!#6 N11850 P4265 BLD 7 -1 FP BE Pri
!#6 N11851 P4266 BLD 24 -1 FP BE Pri
!#6 N11852 P4266 BLD 25 -1 FP BE Pri
!#A N11851 N11852
!#6 N11853 P4266 BLD 26 -1 FP BE Pri
!#6 N11854 P4266 BLD 27 -1 FP BE Pri
!#6 N11855 P4267 BLD 24 -1 FP BE Pri
!#6 N11856 P4267 BLD 25 -1 FP BE Pri
!#A N11855 N11856
!#6 N11857 P4267 BLD 26 -1 FP BE Pri
!#6 N11858 P4267 BLD 27 -1 FP BE Pri
!#6 N11861 P4269 LD 14 -1 Int BE Pri
!#6 N11862 P4270 SWAP 13 0xffffffff 0x300001d Int BE Pri
!#6 N11863 P4269 LD 14 -1 Int BE Pri
!#6 N11864 P4270 SWAP 13 0xffffffff 0x300001e Int BE Pri
!#6 N11865 P4271 BLD 28 -1 FP BE Pri
!#6 N11866 P4271 BLD 29 -1 FP BE Pri
!#A N11865 N11866
!#6 N11867 P4271 BLD 30 -1 FP BE Pri
!#6 N11868 P4271 BLD 31 -1 FP BE Pri
!#6 N11870 P4273 BLD 24 -1 FP BE Pri
!#6 N11871 P4273 BLD 25 -1 FP BE Pri
!#A N11870 N11871
!#6 N11872 P4273 BLD 26 -1 FP BE Pri
!#6 N11873 P4273 BLD 27 -1 FP BE Pri
!#6 N11874 P4274 ST 18 0x300001f Int BE Pri
!#6 N11875 P4275 LD 14 -1 Int BE Pri
!#6 N11876 P4276 LD 29 -1 Int BE Pri
!#6 N11877 P4277 BLD 20 -1 FP BE Pri
!#6 N11878 P4277 BLD 21 -1 FP BE Pri
!#A N11877 N11878
!#6 N11879 P4277 BLD 22 -1 FP BE Pri
!#6 N11880 P4277 BLD 23 -1 FP BE Pri
!#6 N11881 P4277 BLD 20 -1 FP BE Pri
!#6 N11882 P4277 BLD 21 -1 FP BE Pri
!#A N11881 N11882
!#6 N11883 P4277 BLD 22 -1 FP BE Pri
!#6 N11884 P4277 BLD 23 -1 FP BE Pri
!#6 N11885 P4278 DWLD 27 -1 Int BE Pri
!#6 N11886 P4279 LD 15 -1 Int BE Pri
!#6 N11887 P4280 BLD 24 -1 FP BE Pri
!#6 N11888 P4280 BLD 25 -1 FP BE Pri
!#A N11887 N11888
!#6 N11889 P4280 BLD 26 -1 FP BE Pri
!#6 N11890 P4280 BLD 27 -1 FP BE Pri
!#6 N11891 P4281 BLD 4 -1 FP BE Pri
!#6 N11892 P4281 BLD 5 -1 FP BE Pri
!#A N11891 N11892
!#6 N11893 P4281 BLD 6 -1 FP BE Pri
!#6 N11894 P4281 BLD 7 -1 FP BE Pri
!#6 N11895 P4280 BLD 24 -1 FP BE Pri
!#6 N11896 P4280 BLD 25 -1 FP BE Pri
!#A N11895 N11896
!#6 N11897 P4280 BLD 26 -1 FP BE Pri
!#6 N11898 P4280 BLD 27 -1 FP BE Pri
!#6 N11899 P4281 BLD 4 -1 FP BE Pri
!#6 N11900 P4281 BLD 5 -1 FP BE Pri
!#A N11899 N11900
!#6 N11901 P4281 BLD 6 -1 FP BE Pri
!#6 N11902 P4281 BLD 7 -1 FP BE Pri
!#6 N11903 P4282 LD 28 -1 Int BE Pri
!#6 N11904 P4283 LD 5 -1 Int BE Pri
!#6 N11905 P4282 LD 28 -1 Int BE Pri
!#6 N11906 P4283 LD 5 -1 Int BE Pri
!#6 N11907 P4284 LD 18 -1 Int BE Pri
!#6 N11908 P4285 LD 24 -1 Int BE Pri
!#6 N11909 P4286 BLD 16 -1 FP BE Pri
!#6 N11910 P4286 BLD 17 -1 FP BE Pri
!#A N11909 N11910
!#6 N11911 P4286 BLD 18 -1 FP BE Pri
!#6 N11912 P4286 BLD 19 -1 FP BE Pri
!#6 N11913 P4287 LD 23 -1 Int BE Pri
!#6 N11914 P4288 DWLD 10 -1 Int BE Pri
!#6 N11915 P4287 LD 23 -1 Int BE Pri
!#6 N11916 P4288 DWLD 10 -1 Int BE Pri
!#6 N11917 P4289 LD 25 -1 Int BE Pri
!#6 N11918 P4290 LD 24 -1 Int BE Pri
!#6 N11919 P4291 DWLD 19 -1 Int BE Pri
!#6 N11920 P4292 LD 19 -1 Int BE Pri
!#6 N11921 P4293 DWLD 24 -1 Int BE Pri
!#6 N11922 P4293 DWLD 25 -1 Int BE Pri
!#A N11921 N11922
!#6 N11923 P4294 DWLD 2 -1 Int BE Pri
!#6 N11924 P4295 LD 12 -1 Int BE Pri
!#6 N11925 P4296 LD 21 -1 Int BE Pri
!#6 N11926 P4297 LD 28 -1 Int BE Pri
!#6 N11927 P4298 BLD 4 -1 FP BE Pri
!#6 N11928 P4298 BLD 5 -1 FP BE Pri
!#A N11927 N11928
!#6 N11929 P4298 BLD 6 -1 FP BE Pri
!#6 N11930 P4298 BLD 7 -1 FP BE Pri
!#6 N11931 P4298 BLD 4 -1 FP BE Pri
!#6 N11932 P4298 BLD 5 -1 FP BE Pri
!#A N11931 N11932
!#6 N11933 P4298 BLD 6 -1 FP BE Pri
!#6 N11934 P4298 BLD 7 -1 FP BE Pri
!#6 N11935 P4299 BLD 28 -1 FP BE Pri
!#6 N11936 P4299 BLD 29 -1 FP BE Pri
!#A N11935 N11936
!#6 N11937 P4299 BLD 30 -1 FP BE Pri
!#6 N11938 P4299 BLD 31 -1 FP BE Pri
!#6 N11939 P4300 LD 1 -1 Int BE Pri
!#6 N11940 P4301 LD 12 -1 Int BE Pri
!#6 N11941 P4299 BLD 28 -1 FP BE Pri
!#6 N11942 P4299 BLD 29 -1 FP BE Pri
!#A N11941 N11942
!#6 N11943 P4299 BLD 30 -1 FP BE Pri
!#6 N11944 P4299 BLD 31 -1 FP BE Pri
!#6 N11945 P4300 LD 1 -1 Int BE Pri
!#6 N11946 P4301 LD 12 -1 Int BE Pri
!#6 N11947 P4302 DWST 27 0x3000020 Int BE Pri
!#6 N11948 P4303 DWLD 8 -1 Int LE Pri
!#6 N11949 P4303 DWLD 9 -1 Int LE Pri
!#A N11948 N11949
!#6 N11950 P4304 LD 15 -1 Int BE Pri
!#6 N11951 P4305 LD 20 -1 Int BE Pri
!#6 N11952 P4306 BLD 0 -1 FP BE Pri
!#6 N11953 P4306 BLD 1 -1 FP BE Pri
!#A N11952 N11953
!#6 N11954 P4306 BLD 2 -1 FP BE Pri
!#6 N11955 P4306 BLD 3 -1 FP BE Pri
!#6 N11956 P4307 LD 24 -1 Int BE Pri
!#6 N11957 P4308 DWLD 16 -1 Int BE Pri
!#6 N11958 P4308 DWLD 17 -1 Int BE Pri
!#A N11957 N11958
!#6 N11959 P4309 LD 18 -1 Int BE Pri
!#6 N11960 P4310 LD 0 -1 Int BE Pri
!#6 N11961 P4311 BLD 8 -1 FP BE Pri
!#6 N11962 P4311 BLD 9 -1 FP BE Pri
!#A N11961 N11962
!#6 N11963 P4311 BLD 10 -1 FP BE Pri
!#6 N11964 P4311 BLD 11 -1 FP BE Pri
!#6 N11965 P4312 LD 13 -1 Int BE Pri
!#6 N11966 P4310 LD 0 -1 Int BE Pri
!#6 N11967 P4311 BLD 8 -1 FP BE Pri
!#6 N11968 P4311 BLD 9 -1 FP BE Pri
!#A N11967 N11968
!#6 N11969 P4311 BLD 10 -1 FP BE Pri
!#6 N11970 P4311 BLD 11 -1 FP BE Pri
!#6 N11971 P4312 LD 13 -1 Int BE Pri
!#6 N11972 P4313 BLD 8 -1 FP BE Pri
!#6 N11973 P4313 BLD 9 -1 FP BE Pri
!#A N11972 N11973
!#6 N11974 P4313 BLD 10 -1 FP BE Pri
!#6 N11975 P4313 BLD 11 -1 FP BE Pri
!#6 N11976 P4314 LD 29 -1 Int LE Pri
!#6 N11977 P4315 LD 31 -1 Int BE Pri
!#6 N11978 P4316 LD 29 -1 Int BE Pri
!#6 N11979 P4317 LD 29 -1 Int BE Pri
!#6 N11980 P4318 DWLD 16 -1 Int BE Pri
!#6 N11981 P4318 DWLD 17 -1 Int BE Pri
!#A N11980 N11981
!#6 N11982 P4318 CASX 16 -1 N11980 0x3000021 Int BE Pri
!#6 N11983 P4318 CASX 17 -1 N11981 0x3000022 Int BE Pri
!#A N11982 N11983
!#6 N11984 P4319 BLD 24 -1 FP BE Pri
!#6 N11985 P4319 BLD 25 -1 FP BE Pri
!#A N11984 N11985
!#6 N11986 P4319 BLD 26 -1 FP BE Pri
!#6 N11987 P4319 BLD 27 -1 FP BE Pri
!#6 N11988 P4320 LD 22 -1 Int LE Pri
!#6 N11989 P4321 LD 7 -1 Int BE Pri
!#6 N11990 P4322 DWLD 3 -1 FP BE Pri
!#6 N11991 P4323 ST 17 0x3000023 Int BE Pri
!#6 N11992 P4322 DWLD 3 -1 FP BE Pri
!#6 N11993 P4323 ST 17 0x3000024 Int BE Pri
!#6 N11994 P4324 BLD 12 -1 FP BE Pri
!#6 N11995 P4324 BLD 13 -1 FP BE Pri
!#A N11994 N11995
!#6 N11996 P4324 BLD 14 -1 FP BE Pri
!#6 N11997 P4324 BLD 15 -1 FP BE Pri
!#6 N11998 P4324 BLD 12 -1 FP BE Pri
!#6 N11999 P4324 BLD 13 -1 FP BE Pri
!#A N11998 N11999
!#6 N12000 P4324 BLD 14 -1 FP BE Pri
!#6 N12001 P4324 BLD 15 -1 FP BE Pri
!#6 N12002 P4325 BLD 12 -1 FP BE Pri
!#6 N12003 P4325 BLD 13 -1 FP BE Pri
!#A N12002 N12003
!#6 N12004 P4325 BLD 14 -1 FP BE Pri
!#6 N12005 P4325 BLD 15 -1 FP BE Pri
!#6 N12006 P4326 LD 24 -1 Int BE Pri
!#6 N12007 P4327 LD 11 -1 Int BE Pri
!#6 N12008 P4328 BLD 0 -1 FP BE Pri
!#6 N12009 P4328 BLD 1 -1 FP BE Pri
!#A N12008 N12009
!#6 N12010 P4328 BLD 2 -1 FP BE Pri
!#6 N12011 P4328 BLD 3 -1 FP BE Pri
!#6 N12012 P4329 DWLD 24 -1 Int LE Pri
!#6 N12013 P4329 DWLD 25 -1 Int LE Pri
!#A N12012 N12013
!#6 N12014 P4330 BLD 12 -1 FP BE Pri
!#6 N12015 P4330 BLD 13 -1 FP BE Pri
!#A N12014 N12015
!#6 N12016 P4330 BLD 14 -1 FP BE Pri
!#6 N12017 P4330 BLD 15 -1 FP BE Pri
!#6 N12018 P4330 BLD 12 -1 FP BE Pri
!#6 N12019 P4330 BLD 13 -1 FP BE Pri
!#A N12018 N12019
!#6 N12020 P4330 BLD 14 -1 FP BE Pri
!#6 N12021 P4330 BLD 15 -1 FP BE Pri
!#6 N12022 P4331 LD 9 -1 Int BE Pri
!#6 N12023 P4332 LD 12 -1 Int BE Pri
!#6 N12024 P4333 LD 20 -1 FP BE Pri
!#6 N12025 P4334 BLD 28 -1 FP BE Pri
!#6 N12026 P4334 BLD 29 -1 FP BE Pri
!#A N12025 N12026
!#6 N12027 P4334 BLD 30 -1 FP BE Pri
!#6 N12028 P4334 BLD 31 -1 FP BE Pri
!#6 N12029 P4335 DWLD 10 -1 Int BE Pri
!#6 N12030 P4336 LD 12 -1 Int BE Pri
!#6 N12031 P4337 LD 25 -1 Int BE Pri
!#6 N12032 P4338 BLD 8 -1 FP BE Pri
!#6 N12033 P4338 BLD 9 -1 FP BE Pri
!#A N12032 N12033
!#6 N12034 P4338 BLD 10 -1 FP BE Pri
!#6 N12035 P4338 BLD 11 -1 FP BE Pri
!#6 N12036 P4339 LD 22 -1 Int BE Pri
!#6 N12037 P4337 LD 25 -1 Int BE Pri
!#6 N12038 P4338 BLD 8 -1 FP BE Pri
!#6 N12039 P4338 BLD 9 -1 FP BE Pri
!#A N12038 N12039
!#6 N12040 P4338 BLD 10 -1 FP BE Pri
!#6 N12041 P4338 BLD 11 -1 FP BE Pri
!#6 N12042 P4339 LD 22 -1 Int BE Pri
!#6 N12043 P4340 BLD 20 -1 FP BE Pri
!#6 N12044 P4340 BLD 21 -1 FP BE Pri
!#A N12043 N12044
!#6 N12045 P4340 BLD 22 -1 FP BE Pri
!#6 N12046 P4340 BLD 23 -1 FP BE Pri
!#6 N12047 P4340 BLD 20 -1 FP BE Pri
!#6 N12048 P4340 BLD 21 -1 FP BE Pri
!#A N12047 N12048
!#6 N12049 P4340 BLD 22 -1 FP BE Pri
!#6 N12050 P4340 BLD 23 -1 FP BE Pri
!#6 N12051 P4341 LD 24 -1 Int BE Pri
!#6 N12052 P4342 LD 28 -1 Int BE Pri
!#6 N12053 P4341 LD 24 -1 Int BE Pri
!#6 N12054 P4342 LD 28 -1 Int BE Pri
!#6 N12055 P4343 BLD 12 -1 FP BE Pri
!#6 N12056 P4343 BLD 13 -1 FP BE Pri
!#A N12055 N12056
!#6 N12057 P4343 BLD 14 -1 FP BE Pri
!#6 N12058 P4343 BLD 15 -1 FP BE Pri
!#6 N12059 P4344 BLD 12 -1 FP BE Pri
!#6 N12060 P4344 BLD 13 -1 FP BE Pri
!#A N12059 N12060
!#6 N12061 P4344 BLD 14 -1 FP BE Pri
!#6 N12062 P4344 BLD 15 -1 FP BE Pri
!#6 N12063 P4343 BLD 12 -1 FP BE Pri
!#6 N12064 P4343 BLD 13 -1 FP BE Pri
!#A N12063 N12064
!#6 N12065 P4343 BLD 14 -1 FP BE Pri
!#6 N12066 P4343 BLD 15 -1 FP BE Pri
!#6 N12067 P4344 BLD 12 -1 FP BE Pri
!#6 N12068 P4344 BLD 13 -1 FP BE Pri
!#A N12067 N12068
!#6 N12069 P4344 BLD 14 -1 FP BE Pri
!#6 N12070 P4344 BLD 15 -1 FP BE Pri
!#6 N12071 P4345 MEMBAR
!#6 N12072 P4346 LD 28 -1 Int BE Pri
!#6 N12073 P4347 LD 2 -1 Int BE Pri
!#6 N12074 P4348 DWLD 20 -1 Int BE Pri
!#6 N12075 P4348 DWLD 21 -1 Int BE Pri
!#A N12074 N12075
!#6 N12076 P4349 DWLD 31 -1 Int BE Pri
!#6 N12077 P4350 BLD 24 -1 FP BE Pri
!#6 N12078 P4350 BLD 25 -1 FP BE Pri
!#A N12077 N12078
!#6 N12079 P4350 BLD 26 -1 FP BE Pri
!#6 N12080 P4350 BLD 27 -1 FP BE Pri
!#6 N12081 P4351 LD 12 -1 Int BE Pri
!#6 N12082 P4349 DWLD 31 -1 Int BE Pri
!#6 N12083 P4350 BLD 24 -1 FP BE Pri
!#6 N12084 P4350 BLD 25 -1 FP BE Pri
!#A N12083 N12084
!#6 N12085 P4350 BLD 26 -1 FP BE Pri
!#6 N12086 P4350 BLD 27 -1 FP BE Pri
!#6 N12087 P4351 LD 12 -1 Int BE Pri
!#6 N12088 P4352 BLD 24 -1 FP BE Pri
!#6 N12089 P4352 BLD 25 -1 FP BE Pri
!#A N12088 N12089
!#6 N12090 P4352 BLD 26 -1 FP BE Pri
!#6 N12091 P4352 BLD 27 -1 FP BE Pri
!#6 N12092 P4352 BLD 24 -1 FP BE Pri
!#6 N12093 P4352 BLD 25 -1 FP BE Pri
!#A N12092 N12093
!#6 N12094 P4352 BLD 26 -1 FP BE Pri
!#6 N12095 P4352 BLD 27 -1 FP BE Pri
!#6 N12096 P4353 DWLD 10 -1 Int BE Pri
!#6 N12097 P4354 BLD 8 -1 FP BE Pri
!#6 N12098 P4354 BLD 9 -1 FP BE Pri
!#A N12097 N12098
!#6 N12099 P4354 BLD 10 -1 FP BE Pri
!#6 N12100 P4354 BLD 11 -1 FP BE Pri
!#6 N12101 P4355 LD 3 -1 Int BE Pri
!#6 N12102 P4353 DWLD 10 -1 Int BE Pri
!#6 N12103 P4354 BLD 8 -1 FP BE Pri
!#6 N12104 P4354 BLD 9 -1 FP BE Pri
!#A N12103 N12104
!#6 N12105 P4354 BLD 10 -1 FP BE Pri
!#6 N12106 P4354 BLD 11 -1 FP BE Pri
!#6 N12107 P4355 LD 3 -1 Int BE Pri
!#6 N12108 P4356 BSTC 28 0x4280002b FP BE Pri
!#6 N12109 P4356 BSTC 29 0x4280002c FP BE Pri
!#A N12108 N12109
!#6 N12110 P4356 BSTC 30 0x4280002d FP BE Pri
!#6 N12111 P4356 BSTC 31 0x4280002e FP BE Pri
!#6 N12112 P4357 LD 9 -1 Int BE Pri
!#6 N12113 P4358 LD 6 -1 Int BE Pri
!#6 N12114 P4356 BSTC 28 0x4280002f FP BE Pri
!#6 N12115 P4356 BSTC 29 0x42800030 FP BE Pri
!#A N12114 N12115
!#6 N12116 P4356 BSTC 30 0x42800031 FP BE Pri
!#6 N12117 P4356 BSTC 31 0x42800032 FP BE Pri
!#6 N12118 P4357 LD 9 -1 Int BE Pri
!#6 N12119 P4358 LD 6 -1 Int BE Pri
!#6 N12120 P4359 LD 2 -1 Int BE Pri
!#6 N12121 P4360 DWLD 10 -1 Int BE Pri
!#6 N12122 P4361 DWLD 14 -1 Int BE Pri
!#6 N12123 P4362 LD 18 -1 Int BE Pri
!#6 N12124 P4363 MEMBAR
!#6 N12125 P4364 LD 17 -1 Int BE Pri
!#6 N12126 P4365 LD 30 -1 Int BE Pri
!#6 N12127 P4366 BLD 4 -1 FP BE Pri
!#6 N12128 P4366 BLD 5 -1 FP BE Pri
!#A N12127 N12128
!#6 N12129 P4366 BLD 6 -1 FP BE Pri
!#6 N12130 P4366 BLD 7 -1 FP BE Pri
!#6 N12131 P4367 DWLD 24 -1 Int BE Pri
!#6 N12132 P4367 DWLD 25 -1 Int BE Pri
!#A N12131 N12132
!#6 N12133 P4368 DWLD 27 -1 Int BE Pri
!#6 N12134 P4369 LD 21 -1 Int BE Pri
!#6 N12135 P4370 DWLD 28 -1 Int BE Pri
!#6 N12136 P4370 DWLD 29 -1 Int BE Pri
!#A N12135 N12136
!#6 N12137 P4371 LD 17 -1 Int BE Pri
!#6 N12138 P4372 LD 10 -1 Int BE Pri
!#6 N12139 P4373 BLD 24 -1 FP BE Pri
!#6 N12140 P4373 BLD 25 -1 FP BE Pri
!#A N12139 N12140
!#6 N12141 P4373 BLD 26 -1 FP BE Pri
!#6 N12142 P4373 BLD 27 -1 FP BE Pri
!#6 N12143 P4374 LD 28 -1 Int BE Pri
!#6 N12144 P4375 BLD 8 -1 FP BE Pri
!#6 N12145 P4375 BLD 9 -1 FP BE Pri
!#A N12144 N12145
!#6 N12146 P4375 BLD 10 -1 FP BE Pri
!#6 N12147 P4375 BLD 11 -1 FP BE Pri
!#6 N12148 P4376 LD 22 -1 Int BE Pri
!#6 N12149 P4374 LD 28 -1 Int BE Pri
!#6 N12150 P4375 BLD 8 -1 FP BE Pri
!#6 N12151 P4375 BLD 9 -1 FP BE Pri
!#A N12150 N12151
!#6 N12152 P4375 BLD 10 -1 FP BE Pri
!#6 N12153 P4375 BLD 11 -1 FP BE Pri
!#6 N12154 P4376 LD 22 -1 Int BE Pri
!#6 N12156 P4378 BLD 16 -1 FP BE Pri
!#6 N12157 P4378 BLD 17 -1 FP BE Pri
!#A N12156 N12157
!#6 N12158 P4378 BLD 18 -1 FP BE Pri
!#6 N12159 P4378 BLD 19 -1 FP BE Pri
!#6 N12161 P4378 BLD 16 -1 FP BE Pri
!#6 N12162 P4378 BLD 17 -1 FP BE Pri
!#A N12161 N12162
!#6 N12163 P4378 BLD 18 -1 FP BE Pri
!#6 N12164 P4378 BLD 19 -1 FP BE Pri
!#6 N12165 P4379 DWLD 0 -1 Int BE Pri
!#6 N12166 P4379 DWLD 1 -1 Int BE Pri
!#A N12165 N12166
!#6 N12167 P4379 DWLD 0 -1 Int BE Pri
!#6 N12168 P4379 DWLD 1 -1 Int BE Pri
!#A N12167 N12168
!#6 N12169 P4380 BSTC 8 0x42800033 FP BE Pri
!#6 N12170 P4380 BSTC 9 0x42800034 FP BE Pri
!#A N12169 N12170
!#6 N12171 P4380 BSTC 10 0x42800035 FP BE Pri
!#6 N12172 P4380 BSTC 11 0x42800036 FP BE Pri
!#6 N12173 P4380 BSTC 8 0x42800037 FP BE Pri
!#6 N12174 P4380 BSTC 9 0x42800038 FP BE Pri
!#A N12173 N12174
!#6 N12175 P4380 BSTC 10 0x42800039 FP BE Pri
!#6 N12176 P4380 BSTC 11 0x4280003a FP BE Pri
!#6 N12177 P4381 LD 2 -1 Int BE Pri
!#6 N12179 P4383 LD 21 -1 Int BE Pri
!#6 N12180 P4384 DWLD 8 -1 Int BE Pri
!#6 N12181 P4384 DWLD 9 -1 Int BE Pri
!#A N12180 N12181
!#6 N12182 P4385 BLD 28 -1 FP BE Pri
!#6 N12183 P4385 BLD 29 -1 FP BE Pri
!#A N12182 N12183
!#6 N12184 P4385 BLD 30 -1 FP BE Pri
!#6 N12185 P4385 BLD 31 -1 FP BE Pri
!#6 N12186 P4386 LD 26 -1 Int BE Pri
!#6 N12187 P4387 LD 23 -1 Int BE Pri
!#6 N12188 P4385 BLD 28 -1 FP BE Pri
!#6 N12189 P4385 BLD 29 -1 FP BE Pri
!#A N12188 N12189
!#6 N12190 P4385 BLD 30 -1 FP BE Pri
!#6 N12191 P4385 BLD 31 -1 FP BE Pri
!#6 N12192 P4386 LD 26 -1 Int BE Pri
!#6 N12193 P4387 LD 23 -1 Int BE Pri
!#6 N12194 P4388 DWLD 12 -1 FP BE Pri
!#6 N12195 P4388 DWLD 13 -1 FP BE Pri
!#A N12194 N12195
!#6 N12196 P4388 DWLD 12 -1 FP BE Pri
!#6 N12197 P4388 DWLD 13 -1 FP BE Pri
!#A N12196 N12197
!#6 N12198 P4389 BLD 0 -1 FP BE Pri
!#6 N12199 P4389 BLD 1 -1 FP BE Pri
!#A N12198 N12199
!#6 N12200 P4389 BLD 2 -1 FP BE Pri
!#6 N12201 P4389 BLD 3 -1 FP BE Pri
!#6 N12202 P4390 LD 9 -1 Int BE Pri
!#6 N12203 P4391 LD 27 -1 Int BE Pri
!#6 N12204 P4392 LD 16 -1 Int BE Pri
!#6 N12205 P4393 DWST 4 0x3000025 Int BE Pri
!#6 N12206 P4393 DWST 5 0x3000026 Int BE Pri
!#A N12205 N12206
!#6 N12207 P4394 LD 6 -1 Int BE Pri
!#6 N12208 P4395 LD 18 -1 FP BE Pri
!#6 N12209 P4396 BLD 8 -1 FP BE Pri
!#6 N12210 P4396 BLD 9 -1 FP BE Pri
!#A N12209 N12210
!#6 N12211 P4396 BLD 10 -1 FP BE Pri
!#6 N12212 P4396 BLD 11 -1 FP BE Pri
!#6 N12213 P4397 DWLD 6 -1 Int BE Pri
!#6 N12214 P4398 LD 24 -1 Int BE Pri
!#6 N12215 P4396 BLD 8 -1 FP BE Pri
!#6 N12216 P4396 BLD 9 -1 FP BE Pri
!#A N12215 N12216
!#6 N12217 P4396 BLD 10 -1 FP BE Pri
!#6 N12218 P4396 BLD 11 -1 FP BE Pri
!#6 N12219 P4397 DWLD 6 -1 Int BE Pri
!#6 N12220 P4398 LD 24 -1 Int BE Pri
!#6 N12221 P4399 DWLD 26 -1 Int BE Pri
!#6 N12222 P4400 LD 2 -1 Int BE Pri
!#6 N12223 P4401 DWLD 8 -1 FP BE Pri
!#6 N12224 P4401 DWLD 9 -1 FP BE Pri
!#A N12223 N12224
!#6 N12225 P4402 MEMBAR
!#6 N12226 P4403 LD 27 -1 Int BE Pri
!#6 N12227 P4404 LD 3 -1 Int BE Pri
!#6 N12228 P4402 MEMBAR
!#6 N12229 P4403 LD 27 -1 Int BE Pri
!#6 N12230 P4404 LD 3 -1 Int BE Pri
!#6 N12231 P4405 DWLD 8 -1 Int BE Pri
!#6 N12232 P4405 DWLD 9 -1 Int BE Pri
!#A N12231 N12232
!#6 N12233 P4406 BLD 8 -1 FP BE Pri
!#6 N12234 P4406 BLD 9 -1 FP BE Pri
!#A N12233 N12234
!#6 N12235 P4406 BLD 10 -1 FP BE Pri
!#6 N12236 P4406 BLD 11 -1 FP BE Pri
!#6 N12237 P4407 LD 9 -1 Int BE Pri
!#6 N12238 P4408 LD 20 -1 Int BE Pri
!#6 N12239 P4406 BLD 8 -1 FP BE Pri
!#6 N12240 P4406 BLD 9 -1 FP BE Pri
!#A N12239 N12240
!#6 N12241 P4406 BLD 10 -1 FP BE Pri
!#6 N12242 P4406 BLD 11 -1 FP BE Pri
!#6 N12243 P4407 LD 9 -1 Int BE Pri
!#6 N12244 P4408 LD 20 -1 Int BE Pri
!#6 N12246 P4410 BLD 20 -1 FP BE Pri
!#6 N12247 P4410 BLD 21 -1 FP BE Pri
!#A N12246 N12247
!#6 N12248 P4410 BLD 22 -1 FP BE Pri
!#6 N12249 P4410 BLD 23 -1 FP BE Pri
!#6 N12250 P4411 LD 8 -1 Int LE Pri
!#6 N12251 P4412 LD 29 -1 Int BE Pri
!#6 N12252 P4413 DWLD 4 -1 FP BE Pri
!#6 N12253 P4413 DWLD 5 -1 FP BE Pri
!#A N12252 N12253
!#6 N12254 P4413 DWLD 4 -1 FP BE Pri
!#6 N12255 P4413 DWLD 5 -1 FP BE Pri
!#A N12254 N12255
!#6 N12256 P4414 LD 23 -1 Int BE Pri
!#6 N12257 P4415 LD 29 -1 Int BE Pri
!#6 N12258 P4416 DWLD 28 -1 Int BE Pri
!#6 N12259 P4416 DWLD 29 -1 Int BE Pri
!#A N12258 N12259
!#6 N12260 P4416 DWLD 28 -1 Int BE Pri
!#6 N12261 P4416 DWLD 29 -1 Int BE Pri
!#A N12260 N12261
!#6 N12262 P4417 LD 28 -1 Int LE Pri
!#6 N12263 P4418 DWLD 7 -1 Int BE Pri
!#6 N12264 P4417 LD 28 -1 Int LE Pri
!#6 N12265 P4418 DWLD 7 -1 Int BE Pri
!#6 N12266 P4419 LD 14 -1 Int BE Pri
!#6 N12267 P4420 LD 28 -1 Int LE Pri
!#6 N12268 P4419 LD 14 -1 Int BE Pri
!#6 N12269 P4420 LD 28 -1 Int LE Pri
!#6 N12270 P4421 BLD 28 -1 FP BE Pri
!#6 N12271 P4421 BLD 29 -1 FP BE Pri
!#A N12270 N12271
!#6 N12272 P4421 BLD 30 -1 FP BE Pri
!#6 N12273 P4421 BLD 31 -1 FP BE Pri
!#6 N12274 P4421 BLD 28 -1 FP BE Pri
!#6 N12275 P4421 BLD 29 -1 FP BE Pri
!#A N12274 N12275
!#6 N12276 P4421 BLD 30 -1 FP BE Pri
!#6 N12277 P4421 BLD 31 -1 FP BE Pri
!#6 N12278 P4422 DWLD 4 -1 Int BE Pri
!#6 N12279 P4422 DWLD 5 -1 Int BE Pri
!#A N12278 N12279
!#6 N12280 P4422 DWLD 4 -1 Int BE Pri
!#6 N12281 P4422 DWLD 5 -1 Int BE Pri
!#A N12280 N12281
!#6 N12282 P4423 DWLD 20 -1 Int BE Pri
!#6 N12283 P4423 DWLD 21 -1 Int BE Pri
!#A N12282 N12283
!#6 N12284 P4423 DWLD 20 -1 Int BE Pri
!#6 N12285 P4423 DWLD 21 -1 Int BE Pri
!#A N12284 N12285
!#6 N12286 P4424 BLD 28 -1 FP BE Pri
!#6 N12287 P4424 BLD 29 -1 FP BE Pri
!#A N12286 N12287
!#6 N12288 P4424 BLD 30 -1 FP BE Pri
!#6 N12289 P4424 BLD 31 -1 FP BE Pri
!#6 N12290 P4425 LD 11 -1 Int BE Pri
!#6 N12291 P4426 LD 4 -1 Int BE Pri
!#6 N12292 P4427 BLD 16 -1 FP BE Pri
!#6 N12293 P4427 BLD 17 -1 FP BE Pri
!#A N12292 N12293
!#6 N12294 P4427 BLD 18 -1 FP BE Pri
!#6 N12295 P4427 BLD 19 -1 FP BE Pri
!#6 N12296 P4428 LD 30 -1 Int BE Pri
!#6 N12297 P4428 CAS 30 -1 N12296 0x3000027 Int BE Pri
!#6 N12298 P4429 BLD 16 -1 FP BE Pri
!#6 N12299 P4429 BLD 17 -1 FP BE Pri
!#A N12298 N12299
!#6 N12300 P4429 BLD 18 -1 FP BE Pri
!#6 N12301 P4429 BLD 19 -1 FP BE Pri
!#6 N12302 P4428 LD 30 -1 Int BE Pri
!#6 N12303 P4428 CAS 30 -1 N12302 0x3000028 Int BE Pri
!#6 N12304 P4429 BLD 16 -1 FP BE Pri
!#6 N12305 P4429 BLD 17 -1 FP BE Pri
!#A N12304 N12305
!#6 N12306 P4429 BLD 18 -1 FP BE Pri
!#6 N12307 P4429 BLD 19 -1 FP BE Pri
!#6 N12308 P4430 DWLD 4 -1 Int BE Pri
!#6 N12309 P4430 DWLD 5 -1 Int BE Pri
!#A N12308 N12309
!#6 N12310 P4431 DWLD 14 -1 Int BE Pri
!#6 N12311 P4432 LD 17 -1 Int BE Pri
!#6 N12312 P4433 DWLD 24 -1 Int BE Pri
!#6 N12313 P4433 DWLD 25 -1 Int BE Pri
!#A N12312 N12313
!#6 N12314 P4434 DWLD 14 -1 Int BE Pri
!#6 N12315 P4435 LD 27 -1 Int BE Pri
!#6 N12316 P4434 DWLD 14 -1 Int BE Pri
!#6 N12317 P4435 LD 27 -1 Int BE Pri
!#6 N12318 P4436 BLD 16 -1 FP BE Pri
!#6 N12319 P4436 BLD 17 -1 FP BE Pri
!#A N12318 N12319
!#6 N12320 P4436 BLD 18 -1 FP BE Pri
!#6 N12321 P4436 BLD 19 -1 FP BE Pri
!#6 N12322 P4437 LD 23 -1 Int BE Pri
!#6 N12323 P4438 DWLD 4 -1 FP BE Pri
!#6 N12324 P4438 DWLD 5 -1 FP BE Pri
!#A N12323 N12324
!#6 N12325 P4439 LD 11 -1 Int BE Pri
!#6 N12326 P4440 DWLD 0 -1 Int BE Pri
!#6 N12327 P4440 DWLD 1 -1 Int BE Pri
!#A N12326 N12327
!#6 N12328 P4441 BLD 8 -1 FP BE Pri
!#6 N12329 P4441 BLD 9 -1 FP BE Pri
!#A N12328 N12329
!#6 N12330 P4441 BLD 10 -1 FP BE Pri
!#6 N12331 P4441 BLD 11 -1 FP BE Pri
!#6 N12332 P4442 DWLD 15 -1 Int BE Pri
!#6 N12333 P4443 DWST 8 0x3000029 Int BE Pri
!#6 N12334 P4443 DWST 9 0x300002a Int BE Pri
!#A N12333 N12334
!#6 N12335 P4444 LD 16 -1 Int BE Pri
!#6 N12336 P4445 DWLD 22 -1 FP BE Pri
!#6 N12337 P4445 DWLD 22 -1 FP BE Pri
!#6 N12338 P4446 BLD 28 -1 FP BE Pri
!#6 N12339 P4446 BLD 29 -1 FP BE Pri
!#A N12338 N12339
!#6 N12340 P4446 BLD 30 -1 FP BE Pri
!#6 N12341 P4446 BLD 31 -1 FP BE Pri
!#6 N12342 P4446 BLD 28 -1 FP BE Pri
!#6 N12343 P4446 BLD 29 -1 FP BE Pri
!#A N12342 N12343
!#6 N12344 P4446 BLD 30 -1 FP BE Pri
!#6 N12345 P4446 BLD 31 -1 FP BE Pri
!#6 N12346 P4447 DWLD 15 -1 Int BE Pri
!#6 N12347 P4448 BLD 24 -1 FP BE Pri
!#6 N12348 P4448 BLD 25 -1 FP BE Pri
!#A N12347 N12348
!#6 N12349 P4448 BLD 26 -1 FP BE Pri
!#6 N12350 P4448 BLD 27 -1 FP BE Pri
!#6 N12351 P4449 LD 5 -1 Int BE Pri
!#6 N12352 P4450 LD 31 -1 Int BE Pri
!#6 N12353 P4451 LD 14 -1 Int BE Pri
!#6 N12354 P4450 LD 31 -1 Int BE Pri
!#6 N12355 P4451 LD 14 -1 Int BE Pri
!#6 N12356 P4452 BLD 4 -1 FP BE Pri
!#6 N12357 P4452 BLD 5 -1 FP BE Pri
!#A N12356 N12357
!#6 N12358 P4452 BLD 6 -1 FP BE Pri
!#6 N12359 P4452 BLD 7 -1 FP BE Pri
!#6 N12360 P4452 BLD 4 -1 FP BE Pri
!#6 N12361 P4452 BLD 5 -1 FP BE Pri
!#A N12360 N12361
!#6 N12362 P4452 BLD 6 -1 FP BE Pri
!#6 N12363 P4452 BLD 7 -1 FP BE Pri
!#6 N12364 P4453 DWLD 26 -1 Int BE Pri
!#6 N12365 P4454 LD 12 -1 Int BE Pri
!#6 N12366 P4455 LD 24 -1 Int BE Pri
!#6 N12367 P4456 LD 24 -1 Int BE Pri
!#6 N12368 P4457 DWLD 12 -1 Int BE Pri
!#6 N12369 P4457 DWLD 13 -1 Int BE Pri
!#A N12368 N12369
!#6 N12370 P4457 CASX 12 -1 N12368 0x300002b Int BE Pri
!#6 N12371 P4457 CASX 13 -1 N12369 0x300002c Int BE Pri
!#A N12370 N12371
!#6 N12372 P4457 DWLD 12 -1 Int BE Pri
!#6 N12373 P4457 DWLD 13 -1 Int BE Pri
!#A N12372 N12373
!#6 N12374 P4457 CASX 12 -1 N12372 0x300002d Int BE Pri
!#6 N12375 P4457 CASX 13 -1 N12373 0x300002e Int BE Pri
!#A N12374 N12375
!#6 N12376 P4458 DWLD 0 -1 Int BE Pri
!#6 N12377 P4458 DWLD 1 -1 Int BE Pri
!#A N12376 N12377
!#6 N12378 P4459 LD 5 -1 Int BE Pri
!#6 N12379 P4460 LD 5 -1 Int BE Pri
!#6 N12380 P4461 BLD 16 -1 FP BE Pri
!#6 N12381 P4461 BLD 17 -1 FP BE Pri
!#A N12380 N12381
!#6 N12382 P4461 BLD 18 -1 FP BE Pri
!#6 N12383 P4461 BLD 19 -1 FP BE Pri
!#6 N12384 P4461 BLD 16 -1 FP BE Pri
!#6 N12385 P4461 BLD 17 -1 FP BE Pri
!#A N12384 N12385
!#6 N12386 P4461 BLD 18 -1 FP BE Pri
!#6 N12387 P4461 BLD 19 -1 FP BE Pri
!#6 N12388 P4462 BLD 24 -1 FP BE Pri
!#6 N12389 P4462 BLD 25 -1 FP BE Pri
!#A N12388 N12389
!#6 N12390 P4462 BLD 26 -1 FP BE Pri
!#6 N12391 P4462 BLD 27 -1 FP BE Pri
!#6 N12392 P4463 BLD 28 -1 FP BE Pri
!#6 N12393 P4463 BLD 29 -1 FP BE Pri
!#A N12392 N12393
!#6 N12394 P4463 BLD 30 -1 FP BE Pri
!#6 N12395 P4463 BLD 31 -1 FP BE Pri
!#6 N12396 P4464 LD 29 -1 Int BE Pri
!#6 N12397 P4465 LD 28 -1 Int BE Pri
!#6 N12398 P4463 BLD 28 -1 FP BE Pri
!#6 N12399 P4463 BLD 29 -1 FP BE Pri
!#A N12398 N12399
!#6 N12400 P4463 BLD 30 -1 FP BE Pri
!#6 N12401 P4463 BLD 31 -1 FP BE Pri
!#6 N12402 P4464 LD 29 -1 Int BE Pri
!#6 N12403 P4465 LD 28 -1 Int BE Pri
!#6 N12404 P4466 BLD 8 -1 FP BE Pri
!#6 N12405 P4466 BLD 9 -1 FP BE Pri
!#A N12404 N12405
!#6 N12406 P4466 BLD 10 -1 FP BE Pri
!#6 N12407 P4466 BLD 11 -1 FP BE Pri
!#6 N12408 P4467 DWLD 23 -1 Int BE Pri
!#6 N12409 P4468 LD 16 -1 Int BE Pri
!#6 N12410 P4466 BLD 8 -1 FP BE Pri
!#6 N12411 P4466 BLD 9 -1 FP BE Pri
!#A N12410 N12411
!#6 N12412 P4466 BLD 10 -1 FP BE Pri
!#6 N12413 P4466 BLD 11 -1 FP BE Pri
!#6 N12414 P4467 DWLD 23 -1 Int BE Pri
!#6 N12415 P4468 LD 16 -1 Int BE Pri
!#6 N12416 P4469 DWLD 0 -1 Int BE Pri
!#6 N12417 P4469 DWLD 1 -1 Int BE Pri
!#A N12416 N12417
!#6 N12418 P4470 BLD 16 -1 FP BE Pri
!#6 N12419 P4470 BLD 17 -1 FP BE Pri
!#A N12418 N12419
!#6 N12420 P4470 BLD 18 -1 FP BE Pri
!#6 N12421 P4470 BLD 19 -1 FP BE Pri
!#6 N12422 P4469 DWLD 0 -1 Int BE Pri
!#6 N12423 P4469 DWLD 1 -1 Int BE Pri
!#A N12422 N12423
!#6 N12424 P4470 BLD 16 -1 FP BE Pri
!#6 N12425 P4470 BLD 17 -1 FP BE Pri
!#A N12424 N12425
!#6 N12426 P4470 BLD 18 -1 FP BE Pri
!#6 N12427 P4470 BLD 19 -1 FP BE Pri
!#6 N12428 P4471 BLD 4 -1 FP BE Pri
!#6 N12429 P4471 BLD 5 -1 FP BE Pri
!#A N12428 N12429
!#6 N12430 P4471 BLD 6 -1 FP BE Pri
!#6 N12431 P4471 BLD 7 -1 FP BE Pri
!#6 N12432 P4471 BLD 4 -1 FP BE Pri
!#6 N12433 P4471 BLD 5 -1 FP BE Pri
!#A N12432 N12433
!#6 N12434 P4471 BLD 6 -1 FP BE Pri
!#6 N12435 P4471 BLD 7 -1 FP BE Pri
!#6 N12436 P4472 BLD 12 -1 FP BE Pri
!#6 N12437 P4472 BLD 13 -1 FP BE Pri
!#A N12436 N12437
!#6 N12438 P4472 BLD 14 -1 FP BE Pri
!#6 N12439 P4472 BLD 15 -1 FP BE Pri
!#6 N12440 P4473 BLD 20 -1 FP BE Pri
!#6 N12441 P4473 BLD 21 -1 FP BE Pri
!#A N12440 N12441
!#6 N12442 P4473 BLD 22 -1 FP BE Pri
!#6 N12443 P4473 BLD 23 -1 FP BE Pri
!#6 N12444 P4474 LD 16 -1 Int BE Pri
!#6 N12445 P4475 LD 4 -1 Int LE Pri
!#6 N12446 P4474 LD 16 -1 Int BE Pri
!#6 N12447 P4475 LD 4 -1 Int LE Pri
!#6 N12448 P4476 LD 8 -1 Int BE Pri
!#6 N12449 P4477 BLD 24 -1 FP BE Pri
!#6 N12450 P4477 BLD 25 -1 FP BE Pri
!#A N12449 N12450
!#6 N12451 P4477 BLD 26 -1 FP BE Pri
!#6 N12452 P4477 BLD 27 -1 FP BE Pri
!#6 N12453 P4478 LD 5 -1 Int BE Pri
!#6 N12454 P4476 LD 8 -1 Int BE Pri
!#6 N12455 P4477 BLD 24 -1 FP BE Pri
!#6 N12456 P4477 BLD 25 -1 FP BE Pri
!#A N12455 N12456
!#6 N12457 P4477 BLD 26 -1 FP BE Pri
!#6 N12458 P4477 BLD 27 -1 FP BE Pri
!#6 N12459 P4478 LD 5 -1 Int BE Pri
!#6 N12460 P4479 BLD 8 -1 FP BE Pri
!#6 N12461 P4479 BLD 9 -1 FP BE Pri
!#A N12460 N12461
!#6 N12462 P4479 BLD 10 -1 FP BE Pri
!#6 N12463 P4479 BLD 11 -1 FP BE Pri
!#6 N12464 P4479 BLD 8 -1 FP BE Pri
!#6 N12465 P4479 BLD 9 -1 FP BE Pri
!#A N12464 N12465
!#6 N12466 P4479 BLD 10 -1 FP BE Pri
!#6 N12467 P4479 BLD 11 -1 FP BE Pri
!#6 N12468 P4480 BLD 12 -1 FP BE Pri
!#6 N12469 P4480 BLD 13 -1 FP BE Pri
!#A N12468 N12469
!#6 N12470 P4480 BLD 14 -1 FP BE Pri
!#6 N12471 P4480 BLD 15 -1 FP BE Pri
!#6 N12472 P4481 LD 31 -1 Int BE Pri
!#6 N12473 P4482 LD 19 -1 Int BE Pri
!#6 N12474 P4481 LD 31 -1 Int BE Pri
!#6 N12475 P4482 LD 19 -1 Int BE Pri
!#6 N12476 P4483 DWLD 0 -1 Int BE Pri
!#6 N12477 P4483 DWLD 1 -1 Int BE Pri
!#A N12476 N12477
!#6 N12478 P4483 DWLD 0 -1 Int BE Pri
!#6 N12479 P4483 DWLD 1 -1 Int BE Pri
!#A N12478 N12479
!#6 N12480 P4484 BLD 20 -1 FP BE Pri
!#6 N12481 P4484 BLD 21 -1 FP BE Pri
!#A N12480 N12481
!#6 N12482 P4484 BLD 22 -1 FP BE Pri
!#6 N12483 P4484 BLD 23 -1 FP BE Pri
!#6 N12484 P4485 DWLD 10 -1 Int BE Pri
!#6 N12485 P4486 DWLD 0 -1 Int BE Pri
!#6 N12486 P4486 DWLD 1 -1 Int BE Pri
!#A N12485 N12486
!#6 N12487 P4487 LD 13 -1 Int BE Pri
!#6 N12488 P4488 BLD 28 -1 FP BE Pri
!#6 N12489 P4488 BLD 29 -1 FP BE Pri
!#A N12488 N12489
!#6 N12490 P4488 BLD 30 -1 FP BE Pri
!#6 N12491 P4488 BLD 31 -1 FP BE Pri
!#6 N12492 P4489 DWLD 0 -1 Int BE Pri
!#6 N12493 P4489 DWLD 1 -1 Int BE Pri
!#A N12492 N12493
!#6 N12494 P4488 BLD 28 -1 FP BE Pri
!#6 N12495 P4488 BLD 29 -1 FP BE Pri
!#A N12494 N12495
!#6 N12496 P4488 BLD 30 -1 FP BE Pri
!#6 N12497 P4488 BLD 31 -1 FP BE Pri
!#6 N12498 P4489 DWLD 0 -1 Int BE Pri
!#6 N12499 P4489 DWLD 1 -1 Int BE Pri
!#A N12498 N12499
!#6 N12500 P4490 BLD 24 -1 FP BE Pri
!#6 N12501 P4490 BLD 25 -1 FP BE Pri
!#A N12500 N12501
!#6 N12502 P4490 BLD 26 -1 FP BE Pri
!#6 N12503 P4490 BLD 27 -1 FP BE Pri
!#6 N12504 P4490 BLD 24 -1 FP BE Pri
!#6 N12505 P4490 BLD 25 -1 FP BE Pri
!#A N12504 N12505
!#6 N12506 P4490 BLD 26 -1 FP BE Pri
!#6 N12507 P4490 BLD 27 -1 FP BE Pri
!#6 N12508 P4491 DWLD 7 -1 Int LE Pri
!#6 N12509 P4492 LD 25 -1 Int BE Pri
!#6 N12510 P4491 DWLD 7 -1 Int LE Pri
!#6 N12511 P4492 LD 25 -1 Int BE Pri
!#6 N12512 P4493 DWLD 6 -1 Int BE Pri
!#6 N12513 P4494 LD 4 -1 Int BE Pri
!#6 N12514 P4493 DWLD 6 -1 Int BE Pri
!#6 N12515 P4494 LD 4 -1 Int BE Pri
!#6 N12516 P4495 DWLD 24 -1 Int BE Pri
!#6 N12517 P4495 DWLD 25 -1 Int BE Pri
!#A N12516 N12517
!#6 N12518 P4495 CASX 24 -1 N12516 0x300002f Int BE Pri
!#6 N12519 P4495 CASX 25 -1 N12517 0x3000030 Int BE Pri
!#A N12518 N12519
!#6 N12520 P4496 BSTC 16 0x4280003b FP BE Pri
!#6 N12521 P4496 BSTC 17 0x4280003c FP BE Pri
!#A N12520 N12521
!#6 N12522 P4496 BSTC 18 0x4280003d FP BE Pri
!#6 N12523 P4496 BSTC 19 0x4280003e FP BE Pri
!#6 N12524 P4496 BSTC 16 0x4280003f FP BE Pri
!#6 N12525 P4496 BSTC 17 0x42800040 FP BE Pri
!#A N12524 N12525
!#6 N12526 P4496 BSTC 18 0x42800041 FP BE Pri
!#6 N12527 P4496 BSTC 19 0x42800042 FP BE Pri
!#6 N12528 P4497 BLD 0 -1 FP BE Pri
!#6 N12529 P4497 BLD 1 -1 FP BE Pri
!#A N12528 N12529
!#6 N12530 P4497 BLD 2 -1 FP BE Pri
!#6 N12531 P4497 BLD 3 -1 FP BE Pri
!#6 N12532 P4497 BLD 0 -1 FP BE Pri
!#6 N12533 P4497 BLD 1 -1 FP BE Pri
!#A N12532 N12533
!#6 N12534 P4497 BLD 2 -1 FP BE Pri
!#6 N12535 P4497 BLD 3 -1 FP BE Pri
!#6 N12536 P4498 DWLD 3 -1 Int LE Pri
!#6 N12537 P4499 BLD 12 -1 FP BE Pri
!#6 N12538 P4499 BLD 13 -1 FP BE Pri
!#A N12537 N12538
!#6 N12539 P4499 BLD 14 -1 FP BE Pri
!#6 N12540 P4499 BLD 15 -1 FP BE Pri
!#6 N12541 P4500 LD 23 -1 Int BE Pri
!#6 N12542 P4498 DWLD 3 -1 Int LE Pri
!#6 N12543 P4499 BLD 12 -1 FP BE Pri
!#6 N12544 P4499 BLD 13 -1 FP BE Pri
!#A N12543 N12544
!#6 N12545 P4499 BLD 14 -1 FP BE Pri
!#6 N12546 P4499 BLD 15 -1 FP BE Pri
!#6 N12547 P4500 LD 23 -1 Int BE Pri
!#6 N12548 P4501 SWAP 10 0xffffffff 0x3000031 Int BE Pri
!#6 N12549 P4502 LD 12 -1 Int BE Pri
!#6 N12550 P4501 SWAP 10 0xffffffff 0x3000032 Int BE Pri
!#6 N12551 P4502 LD 12 -1 Int BE Pri
!#6 N12552 P4503 DWLD 4 -1 Int BE Pri
!#6 N12553 P4503 DWLD 5 -1 Int BE Pri
!#A N12552 N12553
!#6 N12554 P4503 DWLD 4 -1 Int BE Pri
!#6 N12555 P4503 DWLD 5 -1 Int BE Pri
!#A N12554 N12555
!#6 N12556 P4504 DWLD 0 -1 Int BE Pri
!#6 N12557 P4504 DWLD 1 -1 Int BE Pri
!#A N12556 N12557
!#6 N12558 P4505 DWLD 4 -1 Int BE Pri
!#6 N12559 P4505 DWLD 5 -1 Int BE Pri
!#A N12558 N12559
!#6 N12560 P4506 BLD 4 -1 FP BE Pri
!#6 N12561 P4506 BLD 5 -1 FP BE Pri
!#A N12560 N12561
!#6 N12562 P4506 BLD 6 -1 FP BE Pri
!#6 N12563 P4506 BLD 7 -1 FP BE Pri
!#6 N12565 P4508 BLD 4 -1 FP BE Pri
!#6 N12566 P4508 BLD 5 -1 FP BE Pri
!#A N12565 N12566
!#6 N12567 P4508 BLD 6 -1 FP BE Pri
!#6 N12568 P4508 BLD 7 -1 FP BE Pri
!#6 N12569 P4508 BLD 4 -1 FP BE Pri
!#6 N12570 P4508 BLD 5 -1 FP BE Pri
!#A N12569 N12570
!#6 N12571 P4508 BLD 6 -1 FP BE Pri
!#6 N12572 P4508 BLD 7 -1 FP BE Pri
!#6 N12573 P4509 DWLD 4 -1 Int BE Pri
!#6 N12574 P4509 DWLD 5 -1 Int BE Pri
!#A N12573 N12574
!#6 N12575 P4510 DWLD 20 -1 Int BE Pri
!#6 N12576 P4510 DWLD 21 -1 Int BE Pri
!#A N12575 N12576
!#6 N12577 P4511 LD 2 -1 Int BE Pri
!#6 N12578 P4512 LD 17 -1 Int BE Pri
!#6 N12579 P4513 LD 25 -1 Int BE Pri
!#6 N12580 P4514 LD 9 -1 Int BE Pri
!#6 N12581 P4515 BLD 28 -1 FP BE Pri
!#6 N12582 P4515 BLD 29 -1 FP BE Pri
!#A N12581 N12582
!#6 N12583 P4515 BLD 30 -1 FP BE Pri
!#6 N12584 P4515 BLD 31 -1 FP BE Pri
!#6 N12585 P4516 DWLD 7 -1 FP BE Pri
!#6 N12586 P4516 DWLD 7 -1 FP BE Pri
!#6 N12587 P4517 LD 6 -1 Int BE Pri
!#6 N12588 P4518 BLD 24 -1 FP BE Pri
!#6 N12589 P4518 BLD 25 -1 FP BE Pri
!#A N12588 N12589
!#6 N12590 P4518 BLD 26 -1 FP BE Pri
!#6 N12591 P4518 BLD 27 -1 FP BE Pri
!#6 N12592 P4519 LD 26 -1 Int BE Pri
!#6 N12593 P4517 LD 6 -1 Int BE Pri
!#6 N12594 P4518 BLD 24 -1 FP BE Pri
!#6 N12595 P4518 BLD 25 -1 FP BE Pri
!#A N12594 N12595
!#6 N12596 P4518 BLD 26 -1 FP BE Pri
!#6 N12597 P4518 BLD 27 -1 FP BE Pri
!#6 N12598 P4519 LD 26 -1 Int BE Pri
!#6 N12599 P4520 BLD 16 -1 FP BE Pri
!#6 N12600 P4520 BLD 17 -1 FP BE Pri
!#A N12599 N12600
!#6 N12601 P4520 BLD 18 -1 FP BE Pri
!#6 N12602 P4520 BLD 19 -1 FP BE Pri
!#6 N12603 P4521 DWLD 22 -1 Int BE Pri
!#6 N12604 P4522 LD 21 -1 Int BE Pri
!#6 N12605 P4520 BLD 16 -1 FP BE Pri
!#6 N12606 P4520 BLD 17 -1 FP BE Pri
!#A N12605 N12606
!#6 N12607 P4520 BLD 18 -1 FP BE Pri
!#6 N12608 P4520 BLD 19 -1 FP BE Pri
!#6 N12609 P4521 DWLD 22 -1 Int BE Pri
!#6 N12610 P4522 LD 21 -1 Int BE Pri
!#6 N12611 P4523 DWLD 8 -1 Int BE Pri
!#6 N12612 P4523 DWLD 9 -1 Int BE Pri
!#A N12611 N12612
!#6 N12613 P4523 DWLD 8 -1 Int BE Pri
!#6 N12614 P4523 DWLD 9 -1 Int BE Pri
!#A N12613 N12614
!#6 N12615 P4524 DWLD 16 -1 Int BE Pri
!#6 N12616 P4524 DWLD 17 -1 Int BE Pri
!#A N12615 N12616
!#6 N12617 P4525 DWLD 20 -1 Int BE Pri
!#6 N12618 P4525 DWLD 21 -1 Int BE Pri
!#A N12617 N12618
!#6 N12619 P4525 CASX 20 -1 N12617 0x3000033 Int BE Pri
!#6 N12620 P4525 CASX 21 -1 N12618 0x3000034 Int BE Pri
!#A N12619 N12620
!#6 N12621 P4524 DWLD 16 -1 Int BE Pri
!#6 N12622 P4524 DWLD 17 -1 Int BE Pri
!#A N12621 N12622
!#6 N12623 P4525 DWLD 20 -1 Int BE Pri
!#6 N12624 P4525 DWLD 21 -1 Int BE Pri
!#A N12623 N12624
!#6 N12625 P4525 CASX 20 -1 N12623 0x3000035 Int BE Pri
!#6 N12626 P4525 CASX 21 -1 N12624 0x3000036 Int BE Pri
!#A N12625 N12626
!#6 N12627 P4526 BLD 28 -1 FP BE Pri
!#6 N12628 P4526 BLD 29 -1 FP BE Pri
!#A N12627 N12628
!#6 N12629 P4526 BLD 30 -1 FP BE Pri
!#6 N12630 P4526 BLD 31 -1 FP BE Pri
!#6 N12631 P4527 LD 7 -1 FP BE Pri
!#6 N12632 P4528 SWAP 18 0xffffffff 0x3000037 Int BE Pri
!#6 N12633 P4529 LD 17 -1 Int BE Pri
!#6 N12634 P4527 LD 7 -1 FP BE Pri
!#6 N12635 P4528 SWAP 18 0xffffffff 0x3000038 Int BE Pri
!#6 N12636 P4529 LD 17 -1 Int BE Pri
!#6 N12637 P4530 DWLD 4 -1 Int BE Pri
!#6 N12638 P4530 DWLD 5 -1 Int BE Pri
!#A N12637 N12638
!#6 N12639 P4530 DWLD 4 -1 Int BE Pri
!#6 N12640 P4530 DWLD 5 -1 Int BE Pri
!#A N12639 N12640
!#6 N12641 P4531 LD 27 -1 Int BE Pri
!#6 N12642 P4532 LD 16 -1 Int BE Pri
!#6 N12643 P4531 LD 27 -1 Int BE Pri
!#6 N12644 P4532 LD 16 -1 Int BE Pri
!#6 N12645 P4533 LD 4 -1 FP BE Pri
!#6 N12646 P4534 LD 27 -1 Int BE Pri
!#6 N12647 P4535 LD 9 -1 Int BE Pri
!#6 N12649 P4537 LD 29 -1 Int BE Pri
!#6 N12650 P4538 LD 13 -1 Int BE Pri
!#6 N12651 P4537 LD 29 -1 Int BE Pri
!#6 N12652 P4538 LD 13 -1 Int BE Pri
!#6 N12653 P4539 BLD 16 -1 FP BE Pri
!#6 N12654 P4539 BLD 17 -1 FP BE Pri
!#A N12653 N12654
!#6 N12655 P4539 BLD 18 -1 FP BE Pri
!#6 N12656 P4539 BLD 19 -1 FP BE Pri
!#6 N12657 P4540 LD 0 -1 Int BE Pri
!#6 N12658 P4541 LD 5 -1 Int BE Pri
!#6 N12659 P4542 DWLD 20 -1 Int BE Pri
!#6 N12660 P4542 DWLD 21 -1 Int BE Pri
!#A N12659 N12660
!#6 N12661 P4543 LD 27 -1 FP BE Pri
!#6 N12662 P4543 LD 27 -1 FP BE Pri
!#6 N12663 P4544 DWLD 10 -1 Int BE Pri
!#6 N12664 P4545 DWLD 14 -1 Int BE Pri
!#6 N12665 P4544 DWLD 10 -1 Int BE Pri
!#6 N12666 P4545 DWLD 14 -1 Int BE Pri
!#6 N12667 P4546 DWLD 15 -1 Int BE Pri
!#6 N12668 P4547 BLD 12 -1 FP BE Pri
!#6 N12669 P4547 BLD 13 -1 FP BE Pri
!#A N12668 N12669
!#6 N12670 P4547 BLD 14 -1 FP BE Pri
!#6 N12671 P4547 BLD 15 -1 FP BE Pri
!#6 N12672 P4548 LD 11 -1 Int BE Pri
!#6 N12673 P4549 DWLD 31 -1 FP BE Pri
!#6 N12674 P4550 DWLD 12 -1 Int BE Pri
!#6 N12675 P4550 DWLD 13 -1 Int BE Pri
!#A N12674 N12675
!#6 N12676 P4551 DWLD 6 -1 Int BE Pri
!#6 N12677 P4552 BLD 28 -1 FP BE Pri
!#6 N12678 P4552 BLD 29 -1 FP BE Pri
!#A N12677 N12678
!#6 N12679 P4552 BLD 30 -1 FP BE Pri
!#6 N12680 P4552 BLD 31 -1 FP BE Pri
!#6 N12681 P4553 LD 8 -1 Int BE Pri
!#6 N12682 P4554 BLD 28 -1 FP BE Pri
!#6 N12683 P4554 BLD 29 -1 FP BE Pri
!#A N12682 N12683
!#6 N12684 P4554 BLD 30 -1 FP BE Pri
!#6 N12685 P4554 BLD 31 -1 FP BE Pri
!#6 N12686 P4554 BLD 28 -1 FP BE Pri
!#6 N12687 P4554 BLD 29 -1 FP BE Pri
!#A N12686 N12687
!#6 N12688 P4554 BLD 30 -1 FP BE Pri
!#6 N12689 P4554 BLD 31 -1 FP BE Pri
!#6 N12690 P4555 DWLD 4 -1 Int BE Pri
!#6 N12691 P4555 DWLD 5 -1 Int BE Pri
!#A N12690 N12691
!#6 N12692 P4556 DWLD 6 -1 FP BE Pri
!#6 N12693 P4555 DWLD 4 -1 Int BE Pri
!#6 N12694 P4555 DWLD 5 -1 Int BE Pri
!#A N12693 N12694
!#6 N12695 P4556 DWLD 6 -1 FP BE Pri
!#6 N12696 P4557 LD 29 -1 Int BE Pri
!#6 N12697 P4558 LD 26 -1 Int BE Pri
!#6 N12698 P4557 LD 29 -1 Int BE Pri
!#6 N12699 P4558 LD 26 -1 Int BE Pri
!#6 N12700 P4559 LD 7 -1 Int BE Pri
!#6 N12701 P4560 BLD 8 -1 FP BE Pri
!#6 N12702 P4560 BLD 9 -1 FP BE Pri
!#A N12701 N12702
!#6 N12703 P4560 BLD 10 -1 FP BE Pri
!#6 N12704 P4560 BLD 11 -1 FP BE Pri
!#6 N12705 P4561 LD 16 -1 Int BE Pri
!#6 N12706 P4562 LD 30 -1 Int BE Pri
!#6 N12707 P4563 LD 31 -1 Int BE Pri
!#6 N12708 P4562 LD 30 -1 Int BE Pri
!#6 N12709 P4563 LD 31 -1 Int BE Pri
!#6 N12710 P4564 LD 21 -1 Int BE Pri
!#6 N12711 P4565 SWAP 20 0xffffffff 0x3000039 Int BE Pri
!#6 N12712 P4566 LD 2 -1 Int BE Pri
!#6 N12713 P4567 LD 19 -1 Int BE Pri
!#6 N12714 P4566 LD 2 -1 Int BE Pri
!#6 N12715 P4567 LD 19 -1 Int BE Pri
!#6 N12716 P4568 LD 28 -1 Int BE Pri
!#6 N12717 P4569 LD 15 -1 Int BE Pri
!#6 N12718 P4569 CAS 15 -1 N12717 0x300003a Int BE Pri
!#6 N12719 P4570 LD 15 -1 Int BE Pri
!#6 N12720 P4568 LD 28 -1 Int BE Pri
!#6 N12721 P4569 LD 15 -1 Int BE Pri
!#6 N12722 P4569 CAS 15 -1 N12721 0x300003b Int BE Pri
!#6 N12723 P4570 LD 15 -1 Int BE Pri
!#6 N12724 P4571 DWLD 16 -1 Int BE Pri
!#6 N12725 P4571 DWLD 17 -1 Int BE Pri
!#A N12724 N12725
!#6 N12726 P4572 BLD 12 -1 FP BE Pri
!#6 N12727 P4572 BLD 13 -1 FP BE Pri
!#A N12726 N12727
!#6 N12728 P4572 BLD 14 -1 FP BE Pri
!#6 N12729 P4572 BLD 15 -1 FP BE Pri
!#6 N12730 P4573 BLD 0 -1 FP BE Pri
!#6 N12731 P4573 BLD 1 -1 FP BE Pri
!#A N12730 N12731
!#6 N12732 P4573 BLD 2 -1 FP BE Pri
!#6 N12733 P4573 BLD 3 -1 FP BE Pri
!#6 N12734 P4574 LD 27 -1 Int BE Pri
!#6 N12735 P4575 DWLD 2 -1 Int BE Pri
!#6 N12736 P4576 LD 30 -1 Int BE Pri
!#6 N12737 P4577 BLD 16 -1 FP BE Pri
!#6 N12738 P4577 BLD 17 -1 FP BE Pri
!#A N12737 N12738
!#6 N12739 P4577 BLD 18 -1 FP BE Pri
!#6 N12740 P4577 BLD 19 -1 FP BE Pri
!#6 N12741 P4578 LD 23 -1 Int BE Pri
!#6 N12742 P4579 BLD 28 -1 FP BE Pri
!#6 N12743 P4579 BLD 29 -1 FP BE Pri
!#A N12742 N12743
!#6 N12744 P4579 BLD 30 -1 FP BE Pri
!#6 N12745 P4579 BLD 31 -1 FP BE Pri
!#6 N12746 P4580 BLD 20 -1 FP BE Pri
!#6 N12747 P4580 BLD 21 -1 FP BE Pri
!#A N12746 N12747
!#6 N12748 P4580 BLD 22 -1 FP BE Pri
!#6 N12749 P4580 BLD 23 -1 FP BE Pri
!#6 N12750 P4579 BLD 28 -1 FP BE Pri
!#6 N12751 P4579 BLD 29 -1 FP BE Pri
!#A N12750 N12751
!#6 N12752 P4579 BLD 30 -1 FP BE Pri
!#6 N12753 P4579 BLD 31 -1 FP BE Pri
!#6 N12754 P4580 BLD 20 -1 FP BE Pri
!#6 N12755 P4580 BLD 21 -1 FP BE Pri
!#A N12754 N12755
!#6 N12756 P4580 BLD 22 -1 FP BE Pri
!#6 N12757 P4580 BLD 23 -1 FP BE Pri
!#6 N12758 P4581 DWLD 26 -1 Int BE Pri
!#6 N12759 P4582 DWLD 16 -1 Int BE Pri
!#6 N12760 P4582 DWLD 17 -1 Int BE Pri
!#A N12759 N12760
!#6 N12761 P4583 LD 23 -1 Int BE Pri
!#6 N12762 P4581 DWLD 26 -1 Int BE Pri
!#6 N12763 P4582 DWLD 16 -1 Int BE Pri
!#6 N12764 P4582 DWLD 17 -1 Int BE Pri
!#A N12763 N12764
!#6 N12765 P4583 LD 23 -1 Int BE Pri
!#6 N12766 P4584 LD 1 -1 Int LE Pri
!#6 N12767 P4585 DWLD 22 -1 Int BE Pri
!#6 N12768 P4584 LD 1 -1 Int LE Pri
!#6 N12769 P4585 DWLD 22 -1 Int BE Pri
!#6 N12770 P4586 LD 8 -1 Int BE Pri
!#6 N12771 P4587 SWAP 20 0xffffffff 0x300003c Int BE Pri
!#6 N12772 P4586 LD 8 -1 Int BE Pri
!#6 N12773 P4587 SWAP 20 0xffffffff 0x300003d Int BE Pri
!#6 N12774 P4588 DWLD 28 -1 Int BE Pri
!#6 N12775 P4588 DWLD 29 -1 Int BE Pri
!#A N12774 N12775
!#6 N12776 P4589 BLD 16 -1 FP BE Pri
!#6 N12777 P4589 BLD 17 -1 FP BE Pri
!#A N12776 N12777
!#6 N12778 P4589 BLD 18 -1 FP BE Pri
!#6 N12779 P4589 BLD 19 -1 FP BE Pri
!#6 N12780 P4590 LD 25 -1 Int BE Pri
!#6 N12781 P4591 LD 28 -1 Int BE Pri
!#6 N12782 P4589 BLD 16 -1 FP BE Pri
!#6 N12783 P4589 BLD 17 -1 FP BE Pri
!#A N12782 N12783
!#6 N12784 P4589 BLD 18 -1 FP BE Pri
!#6 N12785 P4589 BLD 19 -1 FP BE Pri
!#6 N12786 P4590 LD 25 -1 Int BE Pri
!#6 N12787 P4591 LD 28 -1 Int BE Pri
!#6 N12788 P4592 DWLD 15 -1 Int BE Pri
!#6 N12789 P4593 LD 30 -1 Int BE Pri
!#6 N12790 P4592 DWLD 15 -1 Int BE Pri
!#6 N12791 P4593 LD 30 -1 Int BE Pri
!#6 N12792 P4594 LD 18 -1 Int BE Pri
!#6 N12793 P4595 LD 30 -1 Int BE Pri
!#6 N12794 P4596 LD 13 -1 Int BE Pri
!#6 N12795 P4597 DWLD 12 -1 FP BE Pri
!#6 N12796 P4597 DWLD 13 -1 FP BE Pri
!#A N12795 N12796
!#6 N12797 P4598 LD 11 -1 Int BE Pri
!#6 N12798 P4596 LD 13 -1 Int BE Pri
!#6 N12799 P4597 DWLD 12 -1 FP BE Pri
!#6 N12800 P4597 DWLD 13 -1 FP BE Pri
!#A N12799 N12800
!#6 N12801 P4598 LD 11 -1 Int BE Pri
!#6 N12803 P4600 DWLD 4 -1 Int BE Pri
!#6 N12804 P4600 DWLD 5 -1 Int BE Pri
!#A N12803 N12804
!#6 N12805 P4600 DWLD 4 -1 Int BE Pri
!#6 N12806 P4600 DWLD 5 -1 Int BE Pri
!#A N12805 N12806
!#6 N12807 P4601 LD 26 -1 Int BE Pri
!#6 N12808 P4602 DWLD 18 -1 Int BE Pri
!#6 N12809 P4603 BLD 28 -1 FP BE Pri
!#6 N12810 P4603 BLD 29 -1 FP BE Pri
!#A N12809 N12810
!#6 N12811 P4603 BLD 30 -1 FP BE Pri
!#6 N12812 P4603 BLD 31 -1 FP BE Pri
!#6 N12813 P4604 DWLD 16 -1 Int BE Pri
!#6 N12814 P4604 DWLD 17 -1 Int BE Pri
!#A N12813 N12814
!#6 N12815 P4605 LD 31 -1 Int BE Pri
!#6 N12816 P4606 LD 14 -1 Int BE Pri
!#6 N12817 P4604 DWLD 16 -1 Int BE Pri
!#6 N12818 P4604 DWLD 17 -1 Int BE Pri
!#A N12817 N12818
!#6 N12819 P4605 LD 31 -1 Int BE Pri
!#6 N12820 P4606 LD 14 -1 Int BE Pri
!#6 N12821 P4607 LD 11 -1 Int BE Pri
!#6 N12822 P4608 LD 17 -1 Int BE Pri
!#6 N12823 P4607 LD 11 -1 Int BE Pri
!#6 N12824 P4608 LD 17 -1 Int BE Pri
!#6 N12825 P4609 LD 18 -1 Int BE Pri
!#6 N12826 P4610 LD 17 -1 Int BE Pri
!#6 N12827 P4611 BSTC 16 0x42800043 FP BE Pri
!#6 N12828 P4611 BSTC 17 0x42800044 FP BE Pri
!#A N12827 N12828
!#6 N12829 P4611 BSTC 18 0x42800045 FP BE Pri
!#6 N12830 P4611 BSTC 19 0x42800046 FP BE Pri
!#6 N12831 P4612 DWLD 0 -1 Int BE Pri
!#6 N12832 P4612 DWLD 1 -1 Int BE Pri
!#A N12831 N12832
!#6 N12833 P4611 BSTC 16 0x42800047 FP BE Pri
!#6 N12834 P4611 BSTC 17 0x42800048 FP BE Pri
!#A N12833 N12834
!#6 N12835 P4611 BSTC 18 0x42800049 FP BE Pri
!#6 N12836 P4611 BSTC 19 0x4280004a FP BE Pri
!#6 N12837 P4612 DWLD 0 -1 Int BE Pri
!#6 N12838 P4612 DWLD 1 -1 Int BE Pri
!#A N12837 N12838
!#6 N12839 P4613 LD 3 -1 Int BE Pri
!#6 N12840 P4614 LD 26 -1 Int BE Pri
!#6 N12841 P4615 LD 25 -1 Int BE Pri
!#6 N12842 P4616 LD 20 -1 Int BE Pri
!#6 N12843 P4615 LD 25 -1 Int BE Pri
!#6 N12844 P4616 LD 20 -1 Int BE Pri
!#6 N12845 P4617 BLD 20 -1 FP BE Pri
!#6 N12846 P4617 BLD 21 -1 FP BE Pri
!#A N12845 N12846
!#6 N12847 P4617 BLD 22 -1 FP BE Pri
!#6 N12848 P4617 BLD 23 -1 FP BE Pri
!#6 N12849 P4618 DWLD 15 -1 Int BE Pri
!#6 N12850 P4619 LD 11 -1 Int BE Pri
!#6 N12851 P4620 BLD 8 -1 FP BE Pri
!#6 N12852 P4620 BLD 9 -1 FP BE Pri
!#A N12851 N12852
!#6 N12853 P4620 BLD 10 -1 FP BE Pri
!#6 N12854 P4620 BLD 11 -1 FP BE Pri
!#6 N12855 P4621 DWLD 2 -1 Int BE Pri
!#6 N12856 P4622 BLD 4 -1 FP BE Pri
!#6 N12857 P4622 BLD 5 -1 FP BE Pri
!#A N12856 N12857
!#6 N12858 P4622 BLD 6 -1 FP BE Pri
!#6 N12859 P4622 BLD 7 -1 FP BE Pri
!#6 N12860 P4623 LD 24 -1 Int BE Pri
!#6 N12861 P4624 LD 18 -1 Int BE Pri
!#6 N12862 P4625 DWLD 24 -1 Int BE Pri
!#6 N12863 P4625 DWLD 25 -1 Int BE Pri
!#A N12862 N12863
!#6 N12864 P4626 LD 26 -1 Int BE Pri
!#6 N12865 P4624 LD 18 -1 Int BE Pri
!#6 N12866 P4625 DWLD 24 -1 Int BE Pri
!#6 N12867 P4625 DWLD 25 -1 Int BE Pri
!#A N12866 N12867
!#6 N12868 P4626 LD 26 -1 Int BE Pri
!#6 N12871 P4628 LD 27 -1 Int BE Pri
!#6 N12872 P4628 CAS 27 -1 N12871 0x300003e Int BE Pri
!#6 N12873 P4629 DWLD 4 -1 Int BE Pri
!#6 N12874 P4629 DWLD 5 -1 Int BE Pri
!#A N12873 N12874
!#6 N12875 P4630 LD 17 -1 Int BE Pri
!#6 N12876 P4630 CAS 17 -1 N12875 0x300003f Int BE Pri
!#6 N12877 P4631 BLD 16 -1 FP BE Pri
!#6 N12878 P4631 BLD 17 -1 FP BE Pri
!#A N12877 N12878
!#6 N12879 P4631 BLD 18 -1 FP BE Pri
!#6 N12880 P4631 BLD 19 -1 FP BE Pri
!#6 N12881 P4632 BLD 8 -1 FP BE Pri
!#6 N12882 P4632 BLD 9 -1 FP BE Pri
!#A N12881 N12882
!#6 N12883 P4632 BLD 10 -1 FP BE Pri
!#6 N12884 P4632 BLD 11 -1 FP BE Pri
!#6 N12885 P4633 BLD 24 -1 FP BE Pri
!#6 N12886 P4633 BLD 25 -1 FP BE Pri
!#A N12885 N12886
!#6 N12887 P4633 BLD 26 -1 FP BE Pri
!#6 N12888 P4633 BLD 27 -1 FP BE Pri
!#6 N12890 P4635 BLD 20 -1 FP BE Pri
!#6 N12891 P4635 BLD 21 -1 FP BE Pri
!#A N12890 N12891
!#6 N12892 P4635 BLD 22 -1 FP BE Pri
!#6 N12893 P4635 BLD 23 -1 FP BE Pri
!#6 N12894 P4636 LD 5 -1 Int BE Pri
!#6 N12895 P4637 LD 15 -1 Int BE Pri
!#6 N12896 P4636 LD 5 -1 Int BE Pri
!#6 N12897 P4637 LD 15 -1 Int BE Pri
!#6 N12898 P4638 BLD 16 -1 FP BE Pri
!#6 N12899 P4638 BLD 17 -1 FP BE Pri
!#A N12898 N12899
!#6 N12900 P4638 BLD 18 -1 FP BE Pri
!#6 N12901 P4638 BLD 19 -1 FP BE Pri
!#6 N12903 P4640 DWLD 8 -1 Int BE Pri
!#6 N12904 P4640 DWLD 9 -1 Int BE Pri
!#A N12903 N12904
!#6 N12905 P4641 BLD 12 -1 FP BE Pri
!#6 N12906 P4641 BLD 13 -1 FP BE Pri
!#A N12905 N12906
!#6 N12907 P4641 BLD 14 -1 FP BE Pri
!#6 N12908 P4641 BLD 15 -1 FP BE Pri
!#6 N12909 P4641 BLD 12 -1 FP BE Pri
!#6 N12910 P4641 BLD 13 -1 FP BE Pri
!#A N12909 N12910
!#6 N12911 P4641 BLD 14 -1 FP BE Pri
!#6 N12912 P4641 BLD 15 -1 FP BE Pri
!#6 N12913 P4642 LD 1 -1 Int BE Pri
!#6 N12914 P4643 DWLD 24 -1 Int BE Pri
!#6 N12915 P4643 DWLD 25 -1 Int BE Pri
!#A N12914 N12915
!#6 N12916 P4644 LD 26 -1 Int BE Pri
!#6 N12917 P4645 DWLD 2 -1 Int BE Pri
!#6 N12918 P4646 LD 2 -1 Int BE Pri
!#6 N12919 P4645 DWLD 2 -1 Int BE Pri
!#6 N12920 P4646 LD 2 -1 Int BE Pri
!#6 N12921 P4647 BLD 12 -1 FP BE Pri
!#6 N12922 P4647 BLD 13 -1 FP BE Pri
!#A N12921 N12922
!#6 N12923 P4647 BLD 14 -1 FP BE Pri
!#6 N12924 P4647 BLD 15 -1 FP BE Pri
!#6 N12925 P4648 LD 1 -1 Int BE Pri
!#6 N12926 P4649 LD 27 -1 Int BE Pri
!#6 N12927 P4650 DWLD 2 -1,0x0 Int LE Pri
!#6 N12928 P4650 CASX 2 -1,0x0 N12927 0x3000040 Int LE Pri
!#6 N12929 P4650 DWLD 2 -1,0x0 Int LE Pri
!#6 N12930 P4650 CASX 2 -1,0x0 N12929 0x3000041 Int LE Pri
!#6 N12931 P4651 DWLD 10 -1,0x0 Int BE Pri
!#6 N12932 P4651 CASX 10 -1,0x0 N12931 0x3000042 Int BE Pri
!#6 N12933 P4652 LD 7 -1 Int BE Pri
!#6 N12934 P4653 LD 22 -1 Int BE Pri
!#6 N12935 P4652 LD 7 -1 Int BE Pri
!#6 N12936 P4653 LD 22 -1 Int BE Pri
!#6 N12937 P4654 DWLD 10 -1 Int BE Pri
!#6 N12938 P4655 LD 5 -1 Int BE Pri
!#6 N12939 P4656 DWLD 16 -1 Int BE Pri
!#6 N12940 P4656 DWLD 17 -1 Int BE Pri
!#A N12939 N12940
!#6 N12941 P4656 DWLD 16 -1 Int BE Pri
!#6 N12942 P4656 DWLD 17 -1 Int BE Pri
!#A N12941 N12942
!#6 N12943 P4657 DWLD 4 -1 Int BE Pri
!#6 N12944 P4657 DWLD 5 -1 Int BE Pri
!#A N12943 N12944
!#6 N12945 P4658 DWLD 16 -1 Int BE Pri
!#6 N12946 P4658 DWLD 17 -1 Int BE Pri
!#A N12945 N12946
!#6 N12947 P4659 BLD 8 -1 FP BE Pri
!#6 N12948 P4659 BLD 9 -1 FP BE Pri
!#A N12947 N12948
!#6 N12949 P4659 BLD 10 -1 FP BE Pri
!#6 N12950 P4659 BLD 11 -1 FP BE Pri
!#6 N12951 P4658 DWLD 16 -1 Int BE Pri
!#6 N12952 P4658 DWLD 17 -1 Int BE Pri
!#A N12951 N12952
!#6 N12953 P4659 BLD 8 -1 FP BE Pri
!#6 N12954 P4659 BLD 9 -1 FP BE Pri
!#A N12953 N12954
!#6 N12955 P4659 BLD 10 -1 FP BE Pri
!#6 N12956 P4659 BLD 11 -1 FP BE Pri
!#6 N12957 P4660 BLD 4 -1 FP BE Pri
!#6 N12958 P4660 BLD 5 -1 FP BE Pri
!#A N12957 N12958
!#6 N12959 P4660 BLD 6 -1 FP BE Pri
!#6 N12960 P4660 BLD 7 -1 FP BE Pri
!#6 N12961 P4661 MEMBAR
!#7 N12962 P4662 BLD 8 -1 FP BE Pri
!#7 N12963 P4662 BLD 9 -1 FP BE Pri
!#A N12962 N12963
!#7 N12964 P4662 BLD 10 -1 FP BE Pri
!#7 N12965 P4662 BLD 11 -1 FP BE Pri
!#7 N12966 P4663 MEMBAR
!#7 N12967 P4664 LD 11 -1 FP BE Pri
!#7 N12969 P4666 DWLD 8 -1 Int LE Pri
!#7 N12970 P4666 DWLD 9 -1 Int LE Pri
!#A N12969 N12970
!#7 N12971 P4666 DWLD 8 -1 Int LE Pri
!#7 N12972 P4666 DWLD 9 -1 Int LE Pri
!#A N12971 N12972
!#7 N12973 P4667 LD 11 -1 Int LE Pri
!#7 N12974 P4668 BLD 24 -1 FP BE Pri
!#7 N12975 P4668 BLD 25 -1 FP BE Pri
!#A N12974 N12975
!#7 N12976 P4668 BLD 26 -1 FP BE Pri
!#7 N12977 P4668 BLD 27 -1 FP BE Pri
!#7 N12978 P4669 LD 4 -1 Int LE Pri
!#7 N12979 P4667 LD 11 -1 Int LE Pri
!#7 N12980 P4668 BLD 24 -1 FP BE Pri
!#7 N12981 P4668 BLD 25 -1 FP BE Pri
!#A N12980 N12981
!#7 N12982 P4668 BLD 26 -1 FP BE Pri
!#7 N12983 P4668 BLD 27 -1 FP BE Pri
!#7 N12984 P4669 LD 4 -1 Int LE Pri
!#7 N12985 P4670 BLD 28 -1 FP BE Pri
!#7 N12986 P4670 BLD 29 -1 FP BE Pri
!#A N12985 N12986
!#7 N12987 P4670 BLD 30 -1 FP BE Pri
!#7 N12988 P4670 BLD 31 -1 FP BE Pri
!#7 N12989 P4671 DWLD 26 -1 Int BE Pri
!#7 N12990 P4672 LD 29 -1 Int BE Pri
!#7 N12991 P4670 BLD 28 -1 FP BE Pri
!#7 N12992 P4670 BLD 29 -1 FP BE Pri
!#A N12991 N12992
!#7 N12993 P4670 BLD 30 -1 FP BE Pri
!#7 N12994 P4670 BLD 31 -1 FP BE Pri
!#7 N12995 P4671 DWLD 26 -1 Int BE Pri
!#7 N12996 P4672 LD 29 -1 Int BE Pri
!#7 N12998 P4674 LD 14 -1 Int BE Pri
!#7 N12999 P4675 LD 0 -1 Int BE Pri
!#7 N13000 P4676 BLD 16 -1 FP BE Pri
!#7 N13001 P4676 BLD 17 -1 FP BE Pri
!#A N13000 N13001
!#7 N13002 P4676 BLD 18 -1 FP BE Pri
!#7 N13003 P4676 BLD 19 -1 FP BE Pri
!#7 N13004 P4676 BLD 16 -1 FP BE Pri
!#7 N13005 P4676 BLD 17 -1 FP BE Pri
!#A N13004 N13005
!#7 N13006 P4676 BLD 18 -1 FP BE Pri
!#7 N13007 P4676 BLD 19 -1 FP BE Pri
!#7 N13008 P4677 LD 30 -1 Int BE Pri
!#7 N13009 P4678 MEMBAR
!#7 N13010 P4679 LD 2 -1 Int BE Pri
!#7 N13011 P4680 BLD 4 -1 FP BE Pri
!#7 N13012 P4680 BLD 5 -1 FP BE Pri
!#A N13011 N13012
!#7 N13013 P4680 BLD 6 -1 FP BE Pri
!#7 N13014 P4680 BLD 7 -1 FP BE Pri
!#7 N13015 P4681 BSTC 12 0x43000001 FP BE Pri
!#7 N13016 P4681 BSTC 13 0x43000002 FP BE Pri
!#A N13015 N13016
!#7 N13017 P4681 BSTC 14 0x43000003 FP BE Pri
!#7 N13018 P4681 BSTC 15 0x43000004 FP BE Pri
!#7 N13019 P4682 DWLD 11 -1 Int BE Pri
!#7 N13020 P4683 LD 14 -1 Int BE Pri
!#7 N13021 P4684 LD 27 -1 FP BE Pri
!#7 N13022 P4684 LD 27 -1 FP BE Pri
!#7 N13023 P4685 BLD 20 -1 FP BE Pri
!#7 N13024 P4685 BLD 21 -1 FP BE Pri
!#A N13023 N13024
!#7 N13025 P4685 BLD 22 -1 FP BE Pri
!#7 N13026 P4685 BLD 23 -1 FP BE Pri
!#7 N13027 P4686 DWLD 20 -1 Int BE Pri
!#7 N13028 P4686 DWLD 21 -1 Int BE Pri
!#A N13027 N13028
!#7 N13029 P4685 BLD 20 -1 FP BE Pri
!#7 N13030 P4685 BLD 21 -1 FP BE Pri
!#A N13029 N13030
!#7 N13031 P4685 BLD 22 -1 FP BE Pri
!#7 N13032 P4685 BLD 23 -1 FP BE Pri
!#7 N13033 P4686 DWLD 20 -1 Int BE Pri
!#7 N13034 P4686 DWLD 21 -1 Int BE Pri
!#A N13033 N13034
!#7 N13035 P4687 BLD 12 -1 FP BE Pri
!#7 N13036 P4687 BLD 13 -1 FP BE Pri
!#A N13035 N13036
!#7 N13037 P4687 BLD 14 -1 FP BE Pri
!#7 N13038 P4687 BLD 15 -1 FP BE Pri
!#7 N13039 P4688 DWLD 24 -1 Int BE Pri
!#7 N13040 P4688 DWLD 25 -1 Int BE Pri
!#A N13039 N13040
!#7 N13041 P4689 BLD 12 -1 FP BE Pri
!#7 N13042 P4689 BLD 13 -1 FP BE Pri
!#A N13041 N13042
!#7 N13043 P4689 BLD 14 -1 FP BE Pri
!#7 N13044 P4689 BLD 15 -1 FP BE Pri
!#7 N13045 P4690 BLD 28 -1 FP BE Pri
!#7 N13046 P4690 BLD 29 -1 FP BE Pri
!#A N13045 N13046
!#7 N13047 P4690 BLD 30 -1 FP BE Pri
!#7 N13048 P4690 BLD 31 -1 FP BE Pri
!#7 N13049 P4689 BLD 12 -1 FP BE Pri
!#7 N13050 P4689 BLD 13 -1 FP BE Pri
!#A N13049 N13050
!#7 N13051 P4689 BLD 14 -1 FP BE Pri
!#7 N13052 P4689 BLD 15 -1 FP BE Pri
!#7 N13053 P4690 BLD 28 -1 FP BE Pri
!#7 N13054 P4690 BLD 29 -1 FP BE Pri
!#A N13053 N13054
!#7 N13055 P4690 BLD 30 -1 FP BE Pri
!#7 N13056 P4690 BLD 31 -1 FP BE Pri
!#7 N13057 P4691 LD 27 -1 Int BE Pri
!#7 N13058 P4692 LD 28 -1 Int BE Pri
!#7 N13059 P4693 BLD 8 -1 FP BE Pri
!#7 N13060 P4693 BLD 9 -1 FP BE Pri
!#A N13059 N13060
!#7 N13061 P4693 BLD 10 -1 FP BE Pri
!#7 N13062 P4693 BLD 11 -1 FP BE Pri
!#7 N13063 P4694 MEMBAR
!#7 N13064 P4695 DWLD 23 -1 Int BE Pri
!#7 N13065 P4696 LD 15 -1 Int BE Pri
!#7 N13066 P4695 DWLD 23 -1 Int BE Pri
!#7 N13067 P4696 LD 15 -1 Int BE Pri
!#7 N13068 P4697 BLD 4 -1 FP BE Pri
!#7 N13069 P4697 BLD 5 -1 FP BE Pri
!#A N13068 N13069
!#7 N13070 P4697 BLD 6 -1 FP BE Pri
!#7 N13071 P4697 BLD 7 -1 FP BE Pri
!#7 N13072 P4697 BLD 4 -1 FP BE Pri
!#7 N13073 P4697 BLD 5 -1 FP BE Pri
!#A N13072 N13073
!#7 N13074 P4697 BLD 6 -1 FP BE Pri
!#7 N13075 P4697 BLD 7 -1 FP BE Pri
!#7 N13076 P4698 LD 30 -1 Int BE Pri
!#7 N13077 P4699 LD 14 -1 Int BE Pri
!#7 N13079 P4701 LD 30 -1 Int BE Pri
!#7 N13080 P4701 CAS 30 -1 N13079 0x3800001 Int BE Pri
!#7 N13081 P4702 MEMBAR
!#7 N13082 P4703 LD 12 -1 Int LE Pri
!#7 N13083 P4704 LD 25 -1 Int BE Pri
!#7 N13084 P4702 MEMBAR
!#7 N13085 P4703 LD 12 -1 Int LE Pri
!#7 N13086 P4704 LD 25 -1 Int BE Pri
!#7 N13087 P4705 LD 31 -1 Int BE Pri
!#7 N13088 P4706 LD 11 -1 Int BE Pri
!#7 N13089 P4707 DWLD 4 -1 FP BE Pri
!#7 N13090 P4707 DWLD 5 -1 FP BE Pri
!#A N13089 N13090
!#7 N13091 P4708 LD 6 -1 Int BE Pri
!#7 N13092 P4709 LD 13 -1 Int BE Pri
!#7 N13093 P4710 LD 8 -1 Int BE Pri
!#7 N13094 P4710 CAS 8 -1 N13093 0x3800002 Int BE Pri
!#7 N13095 P4710 LD 8 -1 Int BE Pri
!#7 N13096 P4710 CAS 8 -1 N13095 0x3800003 Int BE Pri
!#7 N13099 P4712 DWLD 16 -1 Int BE Pri
!#7 N13100 P4712 DWLD 17 -1 Int BE Pri
!#A N13099 N13100
!#7 N13101 P4713 LD 13 -1 Int BE Pri
!#7 N13102 P4714 LD 28 -1 Int BE Pri
!#7 N13103 P4715 DWLD 20 -1 Int BE Pri
!#7 N13104 P4715 DWLD 21 -1 Int BE Pri
!#A N13103 N13104
!#7 N13105 P4716 BLD 0 -1 FP BE Pri
!#7 N13106 P4716 BLD 1 -1 FP BE Pri
!#A N13105 N13106
!#7 N13107 P4716 BLD 2 -1 FP BE Pri
!#7 N13108 P4716 BLD 3 -1 FP BE Pri
!#7 N13109 P4717 DWLD 12 -1 Int BE Pri
!#7 N13110 P4717 DWLD 13 -1 Int BE Pri
!#A N13109 N13110
!#7 N13111 P4716 BLD 0 -1 FP BE Pri
!#7 N13112 P4716 BLD 1 -1 FP BE Pri
!#A N13111 N13112
!#7 N13113 P4716 BLD 2 -1 FP BE Pri
!#7 N13114 P4716 BLD 3 -1 FP BE Pri
!#7 N13115 P4717 DWLD 12 -1 Int BE Pri
!#7 N13116 P4717 DWLD 13 -1 Int BE Pri
!#A N13115 N13116
!#7 N13117 P4718 DWST 23 0x3800004 Int BE Pri
!#7 N13118 P4719 BLD 8 -1 FP BE Pri
!#7 N13119 P4719 BLD 9 -1 FP BE Pri
!#A N13118 N13119
!#7 N13120 P4719 BLD 10 -1 FP BE Pri
!#7 N13121 P4719 BLD 11 -1 FP BE Pri
!#7 N13122 P4718 DWST 23 0x3800005 Int BE Pri
!#7 N13123 P4719 BLD 8 -1 FP BE Pri
!#7 N13124 P4719 BLD 9 -1 FP BE Pri
!#A N13123 N13124
!#7 N13125 P4719 BLD 10 -1 FP BE Pri
!#7 N13126 P4719 BLD 11 -1 FP BE Pri
!#7 N13127 P4720 LD 25 -1 Int BE Pri
!#7 N13128 P4720 CAS 25 -1 N13127 0x3800006 Int BE Pri
!#7 N13129 P4720 LD 25 -1 Int BE Pri
!#7 N13130 P4720 CAS 25 -1 N13129 0x3800007 Int BE Pri
!#7 N13131 P4721 BLD 24 -1 FP BE Pri
!#7 N13132 P4721 BLD 25 -1 FP BE Pri
!#A N13131 N13132
!#7 N13133 P4721 BLD 26 -1 FP BE Pri
!#7 N13134 P4721 BLD 27 -1 FP BE Pri
!#7 N13135 P4722 DWLD 30 -1 Int BE Pri
!#7 N13136 P4723 LD 17 -1 Int LE Pri
!#7 N13137 P4721 BLD 24 -1 FP BE Pri
!#7 N13138 P4721 BLD 25 -1 FP BE Pri
!#A N13137 N13138
!#7 N13139 P4721 BLD 26 -1 FP BE Pri
!#7 N13140 P4721 BLD 27 -1 FP BE Pri
!#7 N13141 P4722 DWLD 30 -1 Int BE Pri
!#7 N13142 P4723 LD 17 -1 Int LE Pri
!#7 N13143 P4724 BLD 4 -1 FP BE Pri
!#7 N13144 P4724 BLD 5 -1 FP BE Pri
!#A N13143 N13144
!#7 N13145 P4724 BLD 6 -1 FP BE Pri
!#7 N13146 P4724 BLD 7 -1 FP BE Pri
!#7 N13147 P4725 LD 7 -1 Int BE Pri
!#7 N13148 P4726 LD 9 -1 Int BE Pri
!#7 N13149 P4727 LD 10 -1 Int BE Pri
!#7 N13150 P4728 BLD 24 -1 FP BE Pri
!#7 N13151 P4728 BLD 25 -1 FP BE Pri
!#A N13150 N13151
!#7 N13152 P4728 BLD 26 -1 FP BE Pri
!#7 N13153 P4728 BLD 27 -1 FP BE Pri
!#7 N13154 P4729 LD 19 -1 Int BE Pri
!#7 N13155 P4730 BLD 8 -1 FP BE Pri
!#7 N13156 P4730 BLD 9 -1 FP BE Pri
!#A N13155 N13156
!#7 N13157 P4730 BLD 10 -1 FP BE Pri
!#7 N13158 P4730 BLD 11 -1 FP BE Pri
!#7 N13159 P4731 BLD 20 -1 FP BE Pri
!#7 N13160 P4731 BLD 21 -1 FP BE Pri
!#A N13159 N13160
!#7 N13161 P4731 BLD 22 -1 FP BE Pri
!#7 N13162 P4731 BLD 23 -1 FP BE Pri
!#7 N13163 P4732 BLD 16 -1 FP BE Pri
!#7 N13164 P4732 BLD 17 -1 FP BE Pri
!#A N13163 N13164
!#7 N13165 P4732 BLD 18 -1 FP BE Pri
!#7 N13166 P4732 BLD 19 -1 FP BE Pri
!#7 N13167 P4733 SWAP 13 0xffffffff 0x3800008 Int BE Pri
!#7 N13168 P4734 DWLD 12 -1 Int BE Pri
!#7 N13169 P4734 DWLD 13 -1 Int BE Pri
!#A N13168 N13169
!#7 N13170 P4735 LD 15 -1 Int BE Pri
!#7 N13171 P4736 BLD 0 -1 FP BE Pri
!#7 N13172 P4736 BLD 1 -1 FP BE Pri
!#A N13171 N13172
!#7 N13173 P4736 BLD 2 -1 FP BE Pri
!#7 N13174 P4736 BLD 3 -1 FP BE Pri
!#7 N13175 P4737 DWLD 15 -1 FP BE Pri
!#7 N13176 P4738 BLD 20 -1 FP BE Pri
!#7 N13177 P4738 BLD 21 -1 FP BE Pri
!#A N13176 N13177
!#7 N13178 P4738 BLD 22 -1 FP BE Pri
!#7 N13179 P4738 BLD 23 -1 FP BE Pri
!#7 N13180 P4739 DWLD 26 -1 Int BE Pri
!#7 N13181 P4740 BLD 12 -1 FP BE Pri
!#7 N13182 P4740 BLD 13 -1 FP BE Pri
!#A N13181 N13182
!#7 N13183 P4740 BLD 14 -1 FP BE Pri
!#7 N13184 P4740 BLD 15 -1 FP BE Pri
!#7 N13185 P4741 LD 4 -1 Int BE Pri
!#7 N13186 P4739 DWLD 26 -1 Int BE Pri
!#7 N13187 P4740 BLD 12 -1 FP BE Pri
!#7 N13188 P4740 BLD 13 -1 FP BE Pri
!#A N13187 N13188
!#7 N13189 P4740 BLD 14 -1 FP BE Pri
!#7 N13190 P4740 BLD 15 -1 FP BE Pri
!#7 N13191 P4741 LD 4 -1 Int BE Pri
!#7 N13192 P4742 BLD 24 -1 FP BE Pri
!#7 N13193 P4742 BLD 25 -1 FP BE Pri
!#A N13192 N13193
!#7 N13194 P4742 BLD 26 -1 FP BE Pri
!#7 N13195 P4742 BLD 27 -1 FP BE Pri
!#7 N13196 P4743 BLD 28 -1 FP BE Pri
!#7 N13197 P4743 BLD 29 -1 FP BE Pri
!#A N13196 N13197
!#7 N13198 P4743 BLD 30 -1 FP BE Pri
!#7 N13199 P4743 BLD 31 -1 FP BE Pri
!#7 N13200 P4743 BLD 28 -1 FP BE Pri
!#7 N13201 P4743 BLD 29 -1 FP BE Pri
!#A N13200 N13201
!#7 N13202 P4743 BLD 30 -1 FP BE Pri
!#7 N13203 P4743 BLD 31 -1 FP BE Pri
!#7 N13204 P4744 DWLD 14 -1 Int BE Pri
!#7 N13205 P4745 DWLD 24 -1 Int BE Pri
!#7 N13206 P4745 DWLD 25 -1 Int BE Pri
!#A N13205 N13206
!#7 N13207 P4746 LD 24 -1 Int BE Pri
!#7 N13208 P4744 DWLD 14 -1 Int BE Pri
!#7 N13209 P4745 DWLD 24 -1 Int BE Pri
!#7 N13210 P4745 DWLD 25 -1 Int BE Pri
!#A N13209 N13210
!#7 N13211 P4746 LD 24 -1 Int BE Pri
!#7 N13212 P4747 LD 26 -1 Int BE Pri
!#7 N13213 P4748 LD 7 -1 Int BE Pri
!#7 N13214 P4749 BLD 8 -1 FP BE Pri
!#7 N13215 P4749 BLD 9 -1 FP BE Pri
!#A N13214 N13215
!#7 N13216 P4749 BLD 10 -1 FP BE Pri
!#7 N13217 P4749 BLD 11 -1 FP BE Pri
!#7 N13218 P4750 DWLD 0 -1 Int BE Pri
!#7 N13219 P4750 DWLD 1 -1 Int BE Pri
!#A N13218 N13219
!#7 N13220 P4749 BLD 8 -1 FP BE Pri
!#7 N13221 P4749 BLD 9 -1 FP BE Pri
!#A N13220 N13221
!#7 N13222 P4749 BLD 10 -1 FP BE Pri
!#7 N13223 P4749 BLD 11 -1 FP BE Pri
!#7 N13224 P4750 DWLD 0 -1 Int BE Pri
!#7 N13225 P4750 DWLD 1 -1 Int BE Pri
!#A N13224 N13225
!#7 N13226 P4751 DWLD 6 -1 Int BE Pri
!#7 N13227 P4752 LD 23 -1 Int BE Pri
!#7 N13228 P4751 DWLD 6 -1 Int BE Pri
!#7 N13229 P4752 LD 23 -1 Int BE Pri
!#7 N13231 P4754 BLD 0 -1 FP BE Pri
!#7 N13232 P4754 BLD 1 -1 FP BE Pri
!#A N13231 N13232
!#7 N13233 P4754 BLD 2 -1 FP BE Pri
!#7 N13234 P4754 BLD 3 -1 FP BE Pri
!#7 N13235 P4755 BLD 28 -1 FP BE Pri
!#7 N13236 P4755 BLD 29 -1 FP BE Pri
!#A N13235 N13236
!#7 N13237 P4755 BLD 30 -1 FP BE Pri
!#7 N13238 P4755 BLD 31 -1 FP BE Pri
!#7 N13239 P4756 BLD 0 -1 FP BE Pri
!#7 N13240 P4756 BLD 1 -1 FP BE Pri
!#A N13239 N13240
!#7 N13241 P4756 BLD 2 -1 FP BE Pri
!#7 N13242 P4756 BLD 3 -1 FP BE Pri
!#7 N13243 P4755 BLD 28 -1 FP BE Pri
!#7 N13244 P4755 BLD 29 -1 FP BE Pri
!#A N13243 N13244
!#7 N13245 P4755 BLD 30 -1 FP BE Pri
!#7 N13246 P4755 BLD 31 -1 FP BE Pri
!#7 N13247 P4756 BLD 0 -1 FP BE Pri
!#7 N13248 P4756 BLD 1 -1 FP BE Pri
!#A N13247 N13248
!#7 N13249 P4756 BLD 2 -1 FP BE Pri
!#7 N13250 P4756 BLD 3 -1 FP BE Pri
!#7 N13251 P4757 LD 13 -1 Int BE Pri
!#7 N13252 P4757 CAS 13 -1 N13251 0x3800009 Int BE Pri
!#7 N13253 P4758 BLD 28 -1 FP BE Pri
!#7 N13254 P4758 BLD 29 -1 FP BE Pri
!#A N13253 N13254
!#7 N13255 P4758 BLD 30 -1 FP BE Pri
!#7 N13256 P4758 BLD 31 -1 FP BE Pri
!#7 N13257 P4757 LD 13 -1 Int BE Pri
!#7 N13258 P4757 CAS 13 -1 N13257 0x380000a Int BE Pri
!#7 N13259 P4758 BLD 28 -1 FP BE Pri
!#7 N13260 P4758 BLD 29 -1 FP BE Pri
!#A N13259 N13260
!#7 N13261 P4758 BLD 30 -1 FP BE Pri
!#7 N13262 P4758 BLD 31 -1 FP BE Pri
!#7 N13263 P4759 DWLD 18 -1 Int BE Pri
!#7 N13264 P4760 LD 30 -1 FP BE Pri
!#7 N13265 P4761 LD 28 -1 Int BE Pri
!#7 N13266 P4762 LD 19 -1 Int BE Pri
!#7 N13267 P4763 LD 20 -1 Int LE Pri
!#7 N13268 P4762 LD 19 -1 Int BE Pri
!#7 N13269 P4763 LD 20 -1 Int LE Pri
!#7 N13270 P4764 LD 18 -1 Int BE Pri
!#7 N13271 P4765 LD 30 -1 Int BE Pri
!#7 N13272 P4764 LD 18 -1 Int BE Pri
!#7 N13273 P4765 LD 30 -1 Int BE Pri
!#7 N13274 P4766 DWLD 31 -1 Int BE Pri
!#7 N13275 P4767 LD 13 -1 Int BE Pri
!#7 N13276 P4768 BLD 0 -1 FP BE Pri
!#7 N13277 P4768 BLD 1 -1 FP BE Pri
!#A N13276 N13277
!#7 N13278 P4768 BLD 2 -1 FP BE Pri
!#7 N13279 P4768 BLD 3 -1 FP BE Pri
!#7 N13281 P4770 LD 30 -1 Int BE Pri
!#7 N13282 P4771 BLD 24 -1 FP BE Pri
!#7 N13283 P4771 BLD 25 -1 FP BE Pri
!#A N13282 N13283
!#7 N13284 P4771 BLD 26 -1 FP BE Pri
!#7 N13285 P4771 BLD 27 -1 FP BE Pri
!#7 N13286 P4772 LD 6 -1 Int BE Pri
!#7 N13287 P4770 LD 30 -1 Int BE Pri
!#7 N13288 P4771 BLD 24 -1 FP BE Pri
!#7 N13289 P4771 BLD 25 -1 FP BE Pri
!#A N13288 N13289
!#7 N13290 P4771 BLD 26 -1 FP BE Pri
!#7 N13291 P4771 BLD 27 -1 FP BE Pri
!#7 N13292 P4772 LD 6 -1 Int BE Pri
!#7 N13293 P4773 DWLD 26 -1 Int BE Pri
!#7 N13295 P4775 LD 28 -1 Int BE Pri
!#7 N13296 P4776 DWLD 0 -1 Int BE Pri
!#7 N13297 P4776 DWLD 1 -1 Int BE Pri
!#A N13296 N13297
!#7 N13298 P4777 DWLD 4 -1 Int BE Pri
!#7 N13299 P4777 DWLD 5 -1 Int BE Pri
!#A N13298 N13299
!#7 N13300 P4778 DWLD 3 -1 Int BE Pri
!#7 N13301 P4779 LD 6 -1 Int BE Pri
!#7 N13302 P4778 DWLD 3 -1 Int BE Pri
!#7 N13303 P4779 LD 6 -1 Int BE Pri
!#7 N13304 P4780 BLD 16 -1 FP BE Pri
!#7 N13305 P4780 BLD 17 -1 FP BE Pri
!#A N13304 N13305
!#7 N13306 P4780 BLD 18 -1 FP BE Pri
!#7 N13307 P4780 BLD 19 -1 FP BE Pri
!#7 N13308 P4781 DWLD 22 -1 Int BE Pri
!#7 N13309 P4782 LD 26 -1 Int BE Pri
!#7 N13310 P4780 BLD 16 -1 FP BE Pri
!#7 N13311 P4780 BLD 17 -1 FP BE Pri
!#A N13310 N13311
!#7 N13312 P4780 BLD 18 -1 FP BE Pri
!#7 N13313 P4780 BLD 19 -1 FP BE Pri
!#7 N13314 P4781 DWLD 22 -1 Int BE Pri
!#7 N13315 P4782 LD 26 -1 Int BE Pri
!#7 N13316 P4783 DWLD 31 -1 Int BE Pri
!#7 N13317 P4784 LD 14 -1 Int BE Pri
!#7 N13318 P4783 DWLD 31 -1 Int BE Pri
!#7 N13319 P4784 LD 14 -1 Int BE Pri
!#7 N13320 P4785 BLD 12 -1 FP BE Pri
!#7 N13321 P4785 BLD 13 -1 FP BE Pri
!#A N13320 N13321
!#7 N13322 P4785 BLD 14 -1 FP BE Pri
!#7 N13323 P4785 BLD 15 -1 FP BE Pri
!#7 N13324 P4786 DWLD 11 -1 FP BE Pri
!#7 N13325 P4787 DWLD 28 -1 Int LE Pri
!#7 N13326 P4787 DWLD 29 -1 Int LE Pri
!#A N13325 N13326
!#7 N13327 P4788 BLD 8 -1 FP BE Pri
!#7 N13328 P4788 BLD 9 -1 FP BE Pri
!#A N13327 N13328
!#7 N13329 P4788 BLD 10 -1 FP BE Pri
!#7 N13330 P4788 BLD 11 -1 FP BE Pri
!#7 N13331 P4787 DWLD 28 -1 Int LE Pri
!#7 N13332 P4787 DWLD 29 -1 Int LE Pri
!#A N13331 N13332
!#7 N13333 P4788 BLD 8 -1 FP BE Pri
!#7 N13334 P4788 BLD 9 -1 FP BE Pri
!#A N13333 N13334
!#7 N13335 P4788 BLD 10 -1 FP BE Pri
!#7 N13336 P4788 BLD 11 -1 FP BE Pri
!#7 N13337 P4789 DWLD 24 -1 Int BE Pri
!#7 N13338 P4789 DWLD 25 -1 Int BE Pri
!#A N13337 N13338
!#7 N13339 P4789 DWLD 24 -1 Int BE Pri
!#7 N13340 P4789 DWLD 25 -1 Int BE Pri
!#A N13339 N13340
!#7 N13342 P4791 BLD 20 -1 FP BE Pri
!#7 N13343 P4791 BLD 21 -1 FP BE Pri
!#A N13342 N13343
!#7 N13344 P4791 BLD 22 -1 FP BE Pri
!#7 N13345 P4791 BLD 23 -1 FP BE Pri
!#7 N13346 P4792 LD 27 -1 Int BE Pri
!#7 N13347 P4793 DWLD 10 -1 Int BE Pri
!#7 N13348 P4792 LD 27 -1 Int BE Pri
!#7 N13349 P4793 DWLD 10 -1 Int BE Pri
!#7 N13350 P4794 DWLD 12 -1 Int BE Pri
!#7 N13351 P4794 DWLD 13 -1 Int BE Pri
!#A N13350 N13351
!#7 N13352 P4794 CASX 12 -1 N13350 0x380000b Int BE Pri
!#7 N13353 P4794 CASX 13 -1 N13351 0x380000c Int BE Pri
!#A N13352 N13353
!#7 N13354 P4795 LD 17 -1 Int BE Pri
!#7 N13355 P4796 DWLD 3 -1 Int BE Pri
!#7 N13356 P4797 LD 19 -1 Int BE Pri
!#7 N13357 P4798 LD 20 -1 Int LE Pri
!#7 N13358 P4799 BLD 8 -1 FP BE Pri
!#7 N13359 P4799 BLD 9 -1 FP BE Pri
!#A N13358 N13359
!#7 N13360 P4799 BLD 10 -1 FP BE Pri
!#7 N13361 P4799 BLD 11 -1 FP BE Pri
!#7 N13363 P4801 BLD 16 -1 FP BE Pri
!#7 N13364 P4801 BLD 17 -1 FP BE Pri
!#A N13363 N13364
!#7 N13365 P4801 BLD 18 -1 FP BE Pri
!#7 N13366 P4801 BLD 19 -1 FP BE Pri
!#7 N13368 P4801 BLD 16 -1 FP BE Pri
!#7 N13369 P4801 BLD 17 -1 FP BE Pri
!#A N13368 N13369
!#7 N13370 P4801 BLD 18 -1 FP BE Pri
!#7 N13371 P4801 BLD 19 -1 FP BE Pri
!#7 N13372 P4802 BLD 4 -1 FP BE Pri
!#7 N13373 P4802 BLD 5 -1 FP BE Pri
!#A N13372 N13373
!#7 N13374 P4802 BLD 6 -1 FP BE Pri
!#7 N13375 P4802 BLD 7 -1 FP BE Pri
!#7 N13376 P4803 DWLD 11 -1 Int BE Pri
!#7 N13377 P4804 LD 19 -1 Int BE Pri
!#7 N13378 P4805 BLD 16 -1 FP BE Pri
!#7 N13379 P4805 BLD 17 -1 FP BE Pri
!#A N13378 N13379
!#7 N13380 P4805 BLD 18 -1 FP BE Pri
!#7 N13381 P4805 BLD 19 -1 FP BE Pri
!#7 N13382 P4806 DWLD 24 -1 FP BE Pri
!#7 N13383 P4806 DWLD 25 -1 FP BE Pri
!#A N13382 N13383
!#7 N13385 P4808 LD 29 -1 Int BE Pri
!#7 N13386 P4809 LD 0 -1 Int BE Pri
!#7 N13387 P4810 DWLD 20 -1 FP BE Pri
!#7 N13388 P4810 DWLD 21 -1 FP BE Pri
!#A N13387 N13388
!#7 N13390 P4812 BLD 28 -1 FP BE Pri
!#7 N13391 P4812 BLD 29 -1 FP BE Pri
!#A N13390 N13391
!#7 N13392 P4812 BLD 30 -1 FP BE Pri
!#7 N13393 P4812 BLD 31 -1 FP BE Pri
!#7 N13394 P4812 BLD 28 -1 FP BE Pri
!#7 N13395 P4812 BLD 29 -1 FP BE Pri
!#A N13394 N13395
!#7 N13396 P4812 BLD 30 -1 FP BE Pri
!#7 N13397 P4812 BLD 31 -1 FP BE Pri
!#7 N13398 P4813 DWLD 22 -1 Int BE Pri
!#7 N13399 P4814 LD 19 -1 Int BE Pri
!#7 N13400 P4815 DWLD 11 -1 FP BE Pri
!#7 N13401 P4816 LD 28 -1 Int BE Pri
!#7 N13402 P4817 DWLD 8 -1 Int BE Pri
!#7 N13403 P4817 DWLD 9 -1 Int BE Pri
!#A N13402 N13403
!#7 N13404 P4818 LD 7 -1 Int BE Pri
!#7 N13405 P4816 LD 28 -1 Int BE Pri
!#7 N13406 P4817 DWLD 8 -1 Int BE Pri
!#7 N13407 P4817 DWLD 9 -1 Int BE Pri
!#A N13406 N13407
!#7 N13408 P4818 LD 7 -1 Int BE Pri
!#7 N13409 P4819 BLD 20 -1 FP BE Pri
!#7 N13410 P4819 BLD 21 -1 FP BE Pri
!#A N13409 N13410
!#7 N13411 P4819 BLD 22 -1 FP BE Pri
!#7 N13412 P4819 BLD 23 -1 FP BE Pri
!#7 N13413 P4819 BLD 20 -1 FP BE Pri
!#7 N13414 P4819 BLD 21 -1 FP BE Pri
!#A N13413 N13414
!#7 N13415 P4819 BLD 22 -1 FP BE Pri
!#7 N13416 P4819 BLD 23 -1 FP BE Pri
!#7 N13417 P4820 BLD 8 -1 FP BE Pri
!#7 N13418 P4820 BLD 9 -1 FP BE Pri
!#A N13417 N13418
!#7 N13419 P4820 BLD 10 -1 FP BE Pri
!#7 N13420 P4820 BLD 11 -1 FP BE Pri
!#7 N13421 P4821 LD 30 -1 Int BE Pri
!#7 N13422 P4822 LD 21 -1 Int BE Pri
!#7 N13423 P4823 BLD 24 -1 FP BE Pri
!#7 N13424 P4823 BLD 25 -1 FP BE Pri
!#A N13423 N13424
!#7 N13425 P4823 BLD 26 -1 FP BE Pri
!#7 N13426 P4823 BLD 27 -1 FP BE Pri
!#7 N13427 P4824 BLD 4 -1 FP BE Pri
!#7 N13428 P4824 BLD 5 -1 FP BE Pri
!#A N13427 N13428
!#7 N13429 P4824 BLD 6 -1 FP BE Pri
!#7 N13430 P4824 BLD 7 -1 FP BE Pri
!#7 N13433 P4827 LD 31 -1 Int BE Pri
!#7 N13434 P4828 LD 8 -1 Int BE Pri
!#7 N13435 P4828 CAS 8 -1 N13434 0x380000d Int BE Pri
!#7 N13436 P4829 LD 1 -1 Int BE Pri
!#7 N13437 P4827 LD 31 -1 Int BE Pri
!#7 N13438 P4828 LD 8 -1 Int BE Pri
!#7 N13439 P4828 CAS 8 -1 N13438 0x380000e Int BE Pri
!#7 N13440 P4829 LD 1 -1 Int BE Pri
!#7 N13441 P4830 DWLD 22 -1 Int BE Pri
!#7 N13442 P4831 LD 14 -1 Int BE Pri
!#7 N13443 P4832 DWLD 20 -1 Int BE Pri
!#7 N13444 P4832 DWLD 21 -1 Int BE Pri
!#A N13443 N13444
!#7 N13445 P4832 DWLD 20 -1 Int BE Pri
!#7 N13446 P4832 DWLD 21 -1 Int BE Pri
!#A N13445 N13446
!#7 N13447 P4833 BSTC 8 0x43000005 FP BE Pri
!#7 N13448 P4833 BSTC 9 0x43000006 FP BE Pri
!#A N13447 N13448
!#7 N13449 P4833 BSTC 10 0x43000007 FP BE Pri
!#7 N13450 P4833 BSTC 11 0x43000008 FP BE Pri
!#7 N13451 P4834 DWLD 16 -1 Int BE Pri
!#7 N13452 P4834 DWLD 17 -1 Int BE Pri
!#A N13451 N13452
!#7 N13453 P4833 BSTC 8 0x43000009 FP BE Pri
!#7 N13454 P4833 BSTC 9 0x4300000a FP BE Pri
!#A N13453 N13454
!#7 N13455 P4833 BSTC 10 0x4300000b FP BE Pri
!#7 N13456 P4833 BSTC 11 0x4300000c FP BE Pri
!#7 N13457 P4834 DWLD 16 -1 Int BE Pri
!#7 N13458 P4834 DWLD 17 -1 Int BE Pri
!#A N13457 N13458
!#7 N13459 P4835 DWLD 18 -1 Int BE Pri
!#7 N13460 P4836 LD 22 -1 Int BE Pri
!#7 N13462 P4838 BSTC 16 0x4300000d FP BE Pri
!#7 N13463 P4838 BSTC 17 0x4300000e FP BE Pri
!#A N13462 N13463
!#7 N13464 P4838 BSTC 18 0x4300000f FP BE Pri
!#7 N13465 P4838 BSTC 19 0x43000010 FP BE Pri
!#7 N13466 P4838 BSTC 16 0x43000011 FP BE Pri
!#7 N13467 P4838 BSTC 17 0x43000012 FP BE Pri
!#A N13466 N13467
!#7 N13468 P4838 BSTC 18 0x43000013 FP BE Pri
!#7 N13469 P4838 BSTC 19 0x43000014 FP BE Pri
!#7 N13470 P4839 LD 22 -1 Int BE Pri
!#7 N13471 P4840 LD 22 -1 Int BE Pri
!#7 N13472 P4841 MEMBAR
!#7 N13474 P4843 LD 7 -1 Int LE Pri
!#7 N13475 P4844 LD 16 -1 Int BE Pri
!#7 N13476 P4845 DWLD 4 -1 Int BE Pri
!#7 N13477 P4845 DWLD 5 -1 Int BE Pri
!#A N13476 N13477
!#7 N13478 P4846 LD 28 -1 Int BE Pri
!#7 N13479 P4847 LD 7 -1 Int BE Pri
!#7 N13480 P4848 BLD 0 -1 FP BE Pri
!#7 N13481 P4848 BLD 1 -1 FP BE Pri
!#A N13480 N13481
!#7 N13482 P4848 BLD 2 -1 FP BE Pri
!#7 N13483 P4848 BLD 3 -1 FP BE Pri
!#7 N13484 P4849 LD 27 -1 Int BE Pri
!#7 N13485 P4850 LD 13 -1 Int BE Pri
!#7 N13486 P4849 LD 27 -1 Int BE Pri
!#7 N13487 P4850 LD 13 -1 Int BE Pri
!#7 N13488 P4851 DWLD 24 -1 Int BE Pri
!#7 N13489 P4851 DWLD 25 -1 Int BE Pri
!#A N13488 N13489
!#7 N13490 P4851 DWLD 24 -1 Int BE Pri
!#7 N13491 P4851 DWLD 25 -1 Int BE Pri
!#A N13490 N13491
!#7 N13492 P4852 LD 14 -1 Int BE Pri
!#7 N13493 P4853 LD 25 -1 Int BE Pri
!#7 N13494 P4854 BLD 16 -1 FP BE Pri
!#7 N13495 P4854 BLD 17 -1 FP BE Pri
!#A N13494 N13495
!#7 N13496 P4854 BLD 18 -1 FP BE Pri
!#7 N13497 P4854 BLD 19 -1 FP BE Pri
!#7 N13498 P4854 BLD 16 -1 FP BE Pri
!#7 N13499 P4854 BLD 17 -1 FP BE Pri
!#A N13498 N13499
!#7 N13500 P4854 BLD 18 -1 FP BE Pri
!#7 N13501 P4854 BLD 19 -1 FP BE Pri
!#7 N13503 P4856 BLD 12 -1 FP BE Pri
!#7 N13504 P4856 BLD 13 -1 FP BE Pri
!#A N13503 N13504
!#7 N13505 P4856 BLD 14 -1 FP BE Pri
!#7 N13506 P4856 BLD 15 -1 FP BE Pri
!#7 N13508 P4856 BLD 12 -1 FP BE Pri
!#7 N13509 P4856 BLD 13 -1 FP BE Pri
!#A N13508 N13509
!#7 N13510 P4856 BLD 14 -1 FP BE Pri
!#7 N13511 P4856 BLD 15 -1 FP BE Pri
!#7 N13512 P4857 LD 1 -1 Int BE Pri
!#7 N13513 P4857 CAS 1 -1 N13512 0x380000f Int BE Pri
!#7 N13514 P4858 DWLD 19 -1 Int BE Pri
!#7 N13515 P4859 LD 19 -1 Int BE Pri
!#7 N13516 P4860 BLD 20 -1 FP BE Pri
!#7 N13517 P4860 BLD 21 -1 FP BE Pri
!#A N13516 N13517
!#7 N13518 P4860 BLD 22 -1 FP BE Pri
!#7 N13519 P4860 BLD 23 -1 FP BE Pri
!#7 N13520 P4861 SWAP 3 0xffffffff 0x3800010 Int BE Pri
!#7 N13521 P4862 LD 5 -1 Int BE Pri
!#7 N13522 P4863 BLD 0 -1 FP BE Pri
!#7 N13523 P4863 BLD 1 -1 FP BE Pri
!#A N13522 N13523
!#7 N13524 P4863 BLD 2 -1 FP BE Pri
!#7 N13525 P4863 BLD 3 -1 FP BE Pri
!#7 N13526 P4863 BLD 0 -1 FP BE Pri
!#7 N13527 P4863 BLD 1 -1 FP BE Pri
!#A N13526 N13527
!#7 N13528 P4863 BLD 2 -1 FP BE Pri
!#7 N13529 P4863 BLD 3 -1 FP BE Pri
!#7 N13530 P4864 DWLD 4 -1 Int BE Pri
!#7 N13531 P4864 DWLD 5 -1 Int BE Pri
!#A N13530 N13531
!#7 N13532 P4865 BLD 4 -1 FP BE Pri
!#7 N13533 P4865 BLD 5 -1 FP BE Pri
!#A N13532 N13533
!#7 N13534 P4865 BLD 6 -1 FP BE Pri
!#7 N13535 P4865 BLD 7 -1 FP BE Pri
!#7 N13536 P4864 DWLD 4 -1 Int BE Pri
!#7 N13537 P4864 DWLD 5 -1 Int BE Pri
!#A N13536 N13537
!#7 N13538 P4865 BLD 4 -1 FP BE Pri
!#7 N13539 P4865 BLD 5 -1 FP BE Pri
!#A N13538 N13539
!#7 N13540 P4865 BLD 6 -1 FP BE Pri
!#7 N13541 P4865 BLD 7 -1 FP BE Pri
!#7 N13542 P4866 DWLD 23 -1 Int BE Pri
!#7 N13543 P4867 LD 22 -1 Int BE Pri
!#7 N13544 P4866 DWLD 23 -1 Int BE Pri
!#7 N13545 P4867 LD 22 -1 Int BE Pri
!#7 N13546 P4868 DWLD 4 -1 Int BE Pri
!#7 N13547 P4868 DWLD 5 -1 Int BE Pri
!#A N13546 N13547
!#7 N13548 P4869 DWLD 30 -1 Int BE Pri
!#7 N13549 P4870 LD 1 -1 Int BE Pri
!#7 N13550 P4868 DWLD 4 -1 Int BE Pri
!#7 N13551 P4868 DWLD 5 -1 Int BE Pri
!#A N13550 N13551
!#7 N13552 P4869 DWLD 30 -1 Int BE Pri
!#7 N13553 P4870 LD 1 -1 Int BE Pri
!#7 N13554 P4871 LD 28 -1 Int BE Pri
!#7 N13555 P4872 DWLD 23 -1 Int BE Pri
!#7 N13556 P4871 LD 28 -1 Int BE Pri
!#7 N13557 P4872 DWLD 23 -1 Int BE Pri
!#7 N13558 P4873 LD 28 -1 Int BE Pri
!#7 N13559 P4874 LD 13 -1 Int BE Pri
!#7 N13560 P4873 LD 28 -1 Int BE Pri
!#7 N13561 P4874 LD 13 -1 Int BE Pri
!#7 N13562 P4875 BLD 12 -1 FP BE Pri
!#7 N13563 P4875 BLD 13 -1 FP BE Pri
!#A N13562 N13563
!#7 N13564 P4875 BLD 14 -1 FP BE Pri
!#7 N13565 P4875 BLD 15 -1 FP BE Pri
!#7 N13566 P4875 BLD 12 -1 FP BE Pri
!#7 N13567 P4875 BLD 13 -1 FP BE Pri
!#A N13566 N13567
!#7 N13568 P4875 BLD 14 -1 FP BE Pri
!#7 N13569 P4875 BLD 15 -1 FP BE Pri
!#7 N13571 P4877 DWLD 11 -1 Int BE Pri
!#7 N13572 P4878 LD 15 -1 Int BE Pri
!#7 N13574 P4877 DWLD 11 -1 Int BE Pri
!#7 N13575 P4878 LD 15 -1 Int BE Pri
!#7 N13576 P4879 DWLD 12 -1 Int BE Pri
!#7 N13577 P4879 DWLD 13 -1 Int BE Pri
!#A N13576 N13577
!#7 N13578 P4880 LD 18 -1 Int BE Pri
!#7 N13579 P4881 LD 25 -1 Int BE Pri
!#7 N13580 P4880 LD 18 -1 Int BE Pri
!#7 N13581 P4881 LD 25 -1 Int BE Pri
!#7 N13582 P4882 BLD 20 -1 FP BE Pri
!#7 N13583 P4882 BLD 21 -1 FP BE Pri
!#A N13582 N13583
!#7 N13584 P4882 BLD 22 -1 FP BE Pri
!#7 N13585 P4882 BLD 23 -1 FP BE Pri
!#7 N13587 P4882 BLD 20 -1 FP BE Pri
!#7 N13588 P4882 BLD 21 -1 FP BE Pri
!#A N13587 N13588
!#7 N13589 P4882 BLD 22 -1 FP BE Pri
!#7 N13590 P4882 BLD 23 -1 FP BE Pri
!#7 N13592 P4884 LD 4 -1 Int BE Pri
!#7 N13593 P4885 LD 6 -1 Int BE Pri
!#7 N13594 P4886 DWLD 7 -1 Int BE Pri
!#7 N13595 P4887 LD 13 -1 FP BE Pri
!#7 N13596 P4888 LD 19 -1 Int BE Pri
!#7 N13597 P4889 LD 19 -1 Int BE Pri
!#7 N13598 P4890 LD 6 -1 Int BE Pri
!#7 N13599 P4891 DWLD 16 -1 Int BE Pri
!#7 N13600 P4891 DWLD 17 -1 Int BE Pri
!#A N13599 N13600
!#7 N13601 P4892 BLD 12 -1 FP BE Pri
!#7 N13602 P4892 BLD 13 -1 FP BE Pri
!#A N13601 N13602
!#7 N13603 P4892 BLD 14 -1 FP BE Pri
!#7 N13604 P4892 BLD 15 -1 FP BE Pri
!#7 N13605 P4893 DWLD 31 -1 FP BE Pri
!#7 N13606 P4894 BLD 28 -1 FP BE Pri
!#7 N13607 P4894 BLD 29 -1 FP BE Pri
!#A N13606 N13607
!#7 N13608 P4894 BLD 30 -1 FP BE Pri
!#7 N13609 P4894 BLD 31 -1 FP BE Pri
!#7 N13610 P4893 DWLD 31 -1 FP BE Pri
!#7 N13611 P4894 BLD 28 -1 FP BE Pri
!#7 N13612 P4894 BLD 29 -1 FP BE Pri
!#A N13611 N13612
!#7 N13613 P4894 BLD 30 -1 FP BE Pri
!#7 N13614 P4894 BLD 31 -1 FP BE Pri
!#7 N13615 P4895 DWLD 0 -1 Int BE Pri
!#7 N13616 P4895 DWLD 1 -1 Int BE Pri
!#A N13615 N13616
!#7 N13617 P4896 LD 12 -1 Int BE Pri
!#7 N13618 P4897 LD 11 -1 Int BE Pri
!#7 N13619 P4895 DWLD 0 -1 Int BE Pri
!#7 N13620 P4895 DWLD 1 -1 Int BE Pri
!#A N13619 N13620
!#7 N13621 P4896 LD 12 -1 Int BE Pri
!#7 N13622 P4897 LD 11 -1 Int BE Pri
!#7 N13623 P4898 DWLD 18 -1 Int BE Pri
!#7 N13624 P4899 LD 27 -1 Int BE Pri
!#7 N13625 P4900 LD 0 -1 Int BE Pri
!#7 N13626 P4901 BLD 12 -1 FP BE Pri
!#7 N13627 P4901 BLD 13 -1 FP BE Pri
!#A N13626 N13627
!#7 N13628 P4901 BLD 14 -1 FP BE Pri
!#7 N13629 P4901 BLD 15 -1 FP BE Pri
!#7 N13630 P4902 LD 21 -1 Int BE Pri
!#7 N13631 P4903 LD 6 -1 Int BE Pri
!#7 N13632 P4904 DWLD 31 -1 Int BE Pri
!#7 N13633 P4903 LD 6 -1 Int BE Pri
!#7 N13634 P4904 DWLD 31 -1 Int BE Pri
!#7 N13636 P4906 DWLD 15 -1 Int BE Pri
!#7 N13637 P4907 LD 18 -1 Int BE Pri
!#7 N13639 P4906 DWLD 15 -1 Int BE Pri
!#7 N13640 P4907 LD 18 -1 Int BE Pri
!#7 N13641 P4908 BSTC 4 0x43000015 FP BE Pri
!#7 N13642 P4908 BSTC 5 0x43000016 FP BE Pri
!#A N13641 N13642
!#7 N13643 P4908 BSTC 6 0x43000017 FP BE Pri
!#7 N13644 P4908 BSTC 7 0x43000018 FP BE Pri
!#7 N13645 P4909 BLD 12 -1 FP BE Pri
!#7 N13646 P4909 BLD 13 -1 FP BE Pri
!#A N13645 N13646
!#7 N13647 P4909 BLD 14 -1 FP BE Pri
!#7 N13648 P4909 BLD 15 -1 FP BE Pri
!#7 N13649 P4910 BLD 12 -1 FP BE Pri
!#7 N13650 P4910 BLD 13 -1 FP BE Pri
!#A N13649 N13650
!#7 N13651 P4910 BLD 14 -1 FP BE Pri
!#7 N13652 P4910 BLD 15 -1 FP BE Pri
!#7 N13653 P4911 LD 20 -1 Int BE Pri
!#7 N13654 P4912 LD 11 -1 Int BE Pri
!#7 N13655 P4910 BLD 12 -1 FP BE Pri
!#7 N13656 P4910 BLD 13 -1 FP BE Pri
!#A N13655 N13656
!#7 N13657 P4910 BLD 14 -1 FP BE Pri
!#7 N13658 P4910 BLD 15 -1 FP BE Pri
!#7 N13659 P4911 LD 20 -1 Int BE Pri
!#7 N13660 P4912 LD 11 -1 Int BE Pri
!#7 N13661 P4913 BLD 12 -1 FP BE Pri
!#7 N13662 P4913 BLD 13 -1 FP BE Pri
!#A N13661 N13662
!#7 N13663 P4913 BLD 14 -1 FP BE Pri
!#7 N13664 P4913 BLD 15 -1 FP BE Pri
!#7 N13665 P4914 LD 2 -1 Int BE Pri
!#7 N13666 P4915 LD 4 -1 Int BE Pri
!#7 N13667 P4913 BLD 12 -1 FP BE Pri
!#7 N13668 P4913 BLD 13 -1 FP BE Pri
!#A N13667 N13668
!#7 N13669 P4913 BLD 14 -1 FP BE Pri
!#7 N13670 P4913 BLD 15 -1 FP BE Pri
!#7 N13671 P4914 LD 2 -1 Int BE Pri
!#7 N13672 P4915 LD 4 -1 Int BE Pri
!#7 N13673 P4916 DWLD 23 -1 Int LE Pri
!#7 N13674 P4917 BST 4 0x43000019 FP BE Pri
!#7 N13675 P4917 BST 5 0x4300001a FP BE Pri
!#A N13674 N13675
!#7 N13676 P4917 BST 6 0x4300001b FP BE Pri
!#7 N13677 P4917 BST 7 0x4300001c FP BE Pri
!#7 N13678 P4918 LD 9 -1 Int BE Pri
!#7 N13679 P4916 DWLD 23 -1 Int LE Pri
!#7 N13680 P4917 BST 4 0x4300001d FP BE Pri
!#7 N13681 P4917 BST 5 0x4300001e FP BE Pri
!#A N13680 N13681
!#7 N13682 P4917 BST 6 0x4300001f FP BE Pri
!#7 N13683 P4917 BST 7 0x43000020 FP BE Pri
!#7 N13684 P4918 LD 9 -1 Int BE Pri
!#7 N13685 P4919 LD 25 -1 Int BE Pri
!#7 N13686 P4920 LD 11 -1 Int BE Pri
!#7 N13687 P4919 LD 25 -1 Int BE Pri
!#7 N13688 P4920 LD 11 -1 Int BE Pri
!#7 N13689 P4921 BLD 4 -1 FP BE Pri
!#7 N13690 P4921 BLD 5 -1 FP BE Pri
!#A N13689 N13690
!#7 N13691 P4921 BLD 6 -1 FP BE Pri
!#7 N13692 P4921 BLD 7 -1 FP BE Pri
!#7 N13693 P4921 BLD 4 -1 FP BE Pri
!#7 N13694 P4921 BLD 5 -1 FP BE Pri
!#A N13693 N13694
!#7 N13695 P4921 BLD 6 -1 FP BE Pri
!#7 N13696 P4921 BLD 7 -1 FP BE Pri
!#7 N13697 P4922 BLD 12 -1 FP BE Pri
!#7 N13698 P4922 BLD 13 -1 FP BE Pri
!#A N13697 N13698
!#7 N13699 P4922 BLD 14 -1 FP BE Pri
!#7 N13700 P4922 BLD 15 -1 FP BE Pri
!#7 N13701 P4922 BLD 12 -1 FP BE Pri
!#7 N13702 P4922 BLD 13 -1 FP BE Pri
!#A N13701 N13702
!#7 N13703 P4922 BLD 14 -1 FP BE Pri
!#7 N13704 P4922 BLD 15 -1 FP BE Pri
!#7 N13705 P4923 BLD 28 -1 FP BE Pri
!#7 N13706 P4923 BLD 29 -1 FP BE Pri
!#A N13705 N13706
!#7 N13707 P4923 BLD 30 -1 FP BE Pri
!#7 N13708 P4923 BLD 31 -1 FP BE Pri
!#7 N13709 P4924 LD 19 -1 Int BE Pri
!#7 N13710 P4925 LD 26 -1 Int BE Pri
!#7 N13711 P4924 LD 19 -1 Int BE Pri
!#7 N13712 P4925 LD 26 -1 Int BE Pri
!#7 N13713 P4926 LD 7 -1 FP BE Pri
!#7 N13714 P4927 BLD 8 -1 FP BE Pri
!#7 N13715 P4927 BLD 9 -1 FP BE Pri
!#A N13714 N13715
!#7 N13716 P4927 BLD 10 -1 FP BE Pri
!#7 N13717 P4927 BLD 11 -1 FP BE Pri
!#7 N13718 P4928 SWAP 22 0xffffffff 0x3800011 Int BE Pri
!#7 N13719 P4929 LD 23 -1 Int BE Pri
!#7 N13720 P4928 SWAP 22 0xffffffff 0x3800012 Int BE Pri
!#7 N13721 P4929 LD 23 -1 Int BE Pri
!#7 N13722 P4930 DWLD 12 -1 Int BE Pri
!#7 N13723 P4930 DWLD 13 -1 Int BE Pri
!#A N13722 N13723
!#7 N13724 P4931 MEMBAR
!#7 N13725 P4930 DWLD 12 -1 Int BE Pri
!#7 N13726 P4930 DWLD 13 -1 Int BE Pri
!#A N13725 N13726
!#7 N13727 P4931 MEMBAR
!#7 N13728 P4932 BLD 28 -1 FP BE Pri
!#7 N13729 P4932 BLD 29 -1 FP BE Pri
!#A N13728 N13729
!#7 N13730 P4932 BLD 30 -1 FP BE Pri
!#7 N13731 P4932 BLD 31 -1 FP BE Pri
!#7 N13732 P4933 LD 0 -1 Int BE Pri
!#7 N13733 P4934 LD 19 -1 Int BE Pri
!#7 N13734 P4935 LD 19 -1 Int BE Pri
!#7 N13735 P4936 LD 3 -1 Int BE Pri
!#7 N13736 P4935 LD 19 -1 Int BE Pri
!#7 N13737 P4936 LD 3 -1 Int BE Pri
!#7 N13738 P4937 LD 21 -1 Int BE Pri
!#7 N13739 P4937 CAS 21 -1 N13738 0x3800013 Int BE Pri
!#7 N13740 P4938 BLD 8 -1 FP BE Pri
!#7 N13741 P4938 BLD 9 -1 FP BE Pri
!#A N13740 N13741
!#7 N13742 P4938 BLD 10 -1 FP BE Pri
!#7 N13743 P4938 BLD 11 -1 FP BE Pri
!#7 N13744 P4938 BLD 8 -1 FP BE Pri
!#7 N13745 P4938 BLD 9 -1 FP BE Pri
!#A N13744 N13745
!#7 N13746 P4938 BLD 10 -1 FP BE Pri
!#7 N13747 P4938 BLD 11 -1 FP BE Pri
!#7 N13748 P4939 DWLD 16 -1 Int BE Pri
!#7 N13749 P4939 DWLD 17 -1 Int BE Pri
!#A N13748 N13749
!#7 N13750 P4939 DWLD 16 -1 Int BE Pri
!#7 N13751 P4939 DWLD 17 -1 Int BE Pri
!#A N13750 N13751
!#7 N13752 P4940 LD 14 -1 Int BE Pri
!#7 N13753 P4941 LD 31 -1 Int BE Pri
!#7 N13754 P4940 LD 14 -1 Int BE Pri
!#7 N13755 P4941 LD 31 -1 Int BE Pri
!#7 N13756 P4942 DWLD 12 -1 Int BE Pri
!#7 N13757 P4942 DWLD 13 -1 Int BE Pri
!#A N13756 N13757
!#7 N13758 P4943 DWLD 2 -1 Int BE Pri
!#7 N13759 P4944 LD 23 -1 Int BE Pri
!#7 N13760 P4942 DWLD 12 -1 Int BE Pri
!#7 N13761 P4942 DWLD 13 -1 Int BE Pri
!#A N13760 N13761
!#7 N13762 P4943 DWLD 2 -1 Int BE Pri
!#7 N13763 P4944 LD 23 -1 Int BE Pri
!#7 N13764 P4945 BLD 4 -1 FP BE Pri
!#7 N13765 P4945 BLD 5 -1 FP BE Pri
!#A N13764 N13765
!#7 N13766 P4945 BLD 6 -1 FP BE Pri
!#7 N13767 P4945 BLD 7 -1 FP BE Pri
!#7 N13768 P4946 LD 31 -1 Int BE Pri
!#7 N13769 P4947 LD 12 -1 Int BE Pri
!#7 N13770 P4945 BLD 4 -1 FP BE Pri
!#7 N13771 P4945 BLD 5 -1 FP BE Pri
!#A N13770 N13771
!#7 N13772 P4945 BLD 6 -1 FP BE Pri
!#7 N13773 P4945 BLD 7 -1 FP BE Pri
!#7 N13774 P4946 LD 31 -1 Int BE Pri
!#7 N13775 P4947 LD 12 -1 Int BE Pri
!#7 N13776 P4948 LD 27 -1 Int BE Pri
!#7 N13777 P4949 DWLD 11 -1 Int BE Pri
!#7 N13778 P4948 LD 27 -1 Int BE Pri
!#7 N13779 P4949 DWLD 11 -1 Int BE Pri
!#7 N13780 P4950 BLD 28 -1 FP BE Pri
!#7 N13781 P4950 BLD 29 -1 FP BE Pri
!#A N13780 N13781
!#7 N13782 P4950 BLD 30 -1 FP BE Pri
!#7 N13783 P4950 BLD 31 -1 FP BE Pri
!#7 N13784 P4951 BLD 8 -1 FP BE Pri
!#7 N13785 P4951 BLD 9 -1 FP BE Pri
!#A N13784 N13785
!#7 N13786 P4951 BLD 10 -1 FP BE Pri
!#7 N13787 P4951 BLD 11 -1 FP BE Pri
!#7 N13788 P4950 BLD 28 -1 FP BE Pri
!#7 N13789 P4950 BLD 29 -1 FP BE Pri
!#A N13788 N13789
!#7 N13790 P4950 BLD 30 -1 FP BE Pri
!#7 N13791 P4950 BLD 31 -1 FP BE Pri
!#7 N13792 P4951 BLD 8 -1 FP BE Pri
!#7 N13793 P4951 BLD 9 -1 FP BE Pri
!#A N13792 N13793
!#7 N13794 P4951 BLD 10 -1 FP BE Pri
!#7 N13795 P4951 BLD 11 -1 FP BE Pri
!#7 N13796 P4952 DWLD 10 -1 Int BE Pri
!#7 N13797 P4953 LD 23 -1 Int BE Pri
!#7 N13798 P4952 DWLD 10 -1 Int BE Pri
!#7 N13799 P4953 LD 23 -1 Int BE Pri
!#7 N13800 P4954 DWLD 20 -1 Int LE Pri
!#7 N13801 P4954 DWLD 21 -1 Int LE Pri
!#A N13800 N13801
!#7 N13802 P4955 BLD 20 -1 FP BE Pri
!#7 N13803 P4955 BLD 21 -1 FP BE Pri
!#A N13802 N13803
!#7 N13804 P4955 BLD 22 -1 FP BE Pri
!#7 N13805 P4955 BLD 23 -1 FP BE Pri
!#7 N13806 P4955 BLD 20 -1 FP BE Pri
!#7 N13807 P4955 BLD 21 -1 FP BE Pri
!#A N13806 N13807
!#7 N13808 P4955 BLD 22 -1 FP BE Pri
!#7 N13809 P4955 BLD 23 -1 FP BE Pri
!#7 N13810 P4956 LD 23 -1 Int BE Pri
!#7 N13811 P4957 LD 14 -1 Int BE Pri
!#7 N13812 P4958 DWLD 15 -1 FP BE Pri
!#7 N13813 P4959 BLD 16 -1 FP BE Pri
!#7 N13814 P4959 BLD 17 -1 FP BE Pri
!#A N13813 N13814
!#7 N13815 P4959 BLD 18 -1 FP BE Pri
!#7 N13816 P4959 BLD 19 -1 FP BE Pri
!#7 N13817 P4960 BLD 12 -1 FP BE Pri
!#7 N13818 P4960 BLD 13 -1 FP BE Pri
!#A N13817 N13818
!#7 N13819 P4960 BLD 14 -1 FP BE Pri
!#7 N13820 P4960 BLD 15 -1 FP BE Pri
!#7 N13821 P4960 BLD 12 -1 FP BE Pri
!#7 N13822 P4960 BLD 13 -1 FP BE Pri
!#A N13821 N13822
!#7 N13823 P4960 BLD 14 -1 FP BE Pri
!#7 N13824 P4960 BLD 15 -1 FP BE Pri
!#7 N13825 P4961 BLD 24 -1 FP BE Pri
!#7 N13826 P4961 BLD 25 -1 FP BE Pri
!#A N13825 N13826
!#7 N13827 P4961 BLD 26 -1 FP BE Pri
!#7 N13828 P4961 BLD 27 -1 FP BE Pri
!#7 N13829 P4962 DWLD 15 -1 Int LE Pri
!#7 N13830 P4963 LD 3 -1 Int BE Pri
!#7 N13831 P4964 DWLD 24 -1 Int BE Pri
!#7 N13832 P4964 DWLD 25 -1 Int BE Pri
!#A N13831 N13832
!#7 N13833 P4965 LD 0 -1 Int BE Pri
!#7 N13834 P4966 LD 27 -1 Int BE Pri
!#7 N13835 P4967 BST 12 0x43000021 FP BE Pri
!#7 N13836 P4967 BST 13 0x43000022 FP BE Pri
!#A N13835 N13836
!#7 N13837 P4967 BST 14 0x43000023 FP BE Pri
!#7 N13838 P4967 BST 15 0x43000024 FP BE Pri
!#7 N13839 P4967 BST 12 0x43000025 FP BE Pri
!#7 N13840 P4967 BST 13 0x43000026 FP BE Pri
!#A N13839 N13840
!#7 N13841 P4967 BST 14 0x43000027 FP BE Pri
!#7 N13842 P4967 BST 15 0x43000028 FP BE Pri
!#7 N13843 P4968 BLD 28 -1 FP BE Pri
!#7 N13844 P4968 BLD 29 -1 FP BE Pri
!#A N13843 N13844
!#7 N13845 P4968 BLD 30 -1 FP BE Pri
!#7 N13846 P4968 BLD 31 -1 FP BE Pri
!#7 N13847 P4969 DWLD 16 -1 Int BE Pri
!#7 N13848 P4969 DWLD 17 -1 Int BE Pri
!#A N13847 N13848
!#7 N13849 P4970 BLD 8 -1 FP BE Pri
!#7 N13850 P4970 BLD 9 -1 FP BE Pri
!#A N13849 N13850
!#7 N13851 P4970 BLD 10 -1 FP BE Pri
!#7 N13852 P4970 BLD 11 -1 FP BE Pri
!#7 N13853 P4971 BLD 8 -1 FP BE Pri
!#7 N13854 P4971 BLD 9 -1 FP BE Pri
!#A N13853 N13854
!#7 N13855 P4971 BLD 10 -1 FP BE Pri
!#7 N13856 P4971 BLD 11 -1 FP BE Pri
!#7 N13857 P4970 BLD 8 -1 FP BE Pri
!#7 N13858 P4970 BLD 9 -1 FP BE Pri
!#A N13857 N13858
!#7 N13859 P4970 BLD 10 -1 FP BE Pri
!#7 N13860 P4970 BLD 11 -1 FP BE Pri
!#7 N13861 P4971 BLD 8 -1 FP BE Pri
!#7 N13862 P4971 BLD 9 -1 FP BE Pri
!#A N13861 N13862
!#7 N13863 P4971 BLD 10 -1 FP BE Pri
!#7 N13864 P4971 BLD 11 -1 FP BE Pri
!#7 N13865 P4972 LD 22 -1 Int BE Pri
!#7 N13866 P4973 LD 25 -1 Int BE Pri
!#7 N13867 P4972 LD 22 -1 Int BE Pri
!#7 N13868 P4973 LD 25 -1 Int BE Pri
!#7 N13869 P4974 LD 9 -1 Int LE Pri
!#7 N13870 P4975 LD 17 -1 Int BE Pri
!#7 N13871 P4974 LD 9 -1 Int LE Pri
!#7 N13872 P4975 LD 17 -1 Int BE Pri
!#7 N13873 P4976 LD 28 -1 Int BE Pri
!#7 N13874 P4977 LD 10 -1 Int BE Pri
!#7 N13875 P4978 DWLD 31 -1 Int BE Pri
!#7 N13876 P4979 BLD 12 -1 FP BE Pri
!#7 N13877 P4979 BLD 13 -1 FP BE Pri
!#A N13876 N13877
!#7 N13878 P4979 BLD 14 -1 FP BE Pri
!#7 N13879 P4979 BLD 15 -1 FP BE Pri
!#7 N13880 P4980 LD 18 -1 Int BE Pri
!#7 N13881 P4978 DWLD 31 -1 Int BE Pri
!#7 N13882 P4979 BLD 12 -1 FP BE Pri
!#7 N13883 P4979 BLD 13 -1 FP BE Pri
!#A N13882 N13883
!#7 N13884 P4979 BLD 14 -1 FP BE Pri
!#7 N13885 P4979 BLD 15 -1 FP BE Pri
!#7 N13886 P4980 LD 18 -1 Int BE Pri
!#7 N13887 P4981 BLD 0 -1 FP BE Pri
!#7 N13888 P4981 BLD 1 -1 FP BE Pri
!#A N13887 N13888
!#7 N13889 P4981 BLD 2 -1 FP BE Pri
!#7 N13890 P4981 BLD 3 -1 FP BE Pri
!#7 N13891 P4982 BSTC 16 0x43000029 FP BE Pri
!#7 N13892 P4982 BSTC 17 0x4300002a FP BE Pri
!#A N13891 N13892
!#7 N13893 P4982 BSTC 18 0x4300002b FP BE Pri
!#7 N13894 P4982 BSTC 19 0x4300002c FP BE Pri
!#7 N13895 P4981 BLD 0 -1 FP BE Pri
!#7 N13896 P4981 BLD 1 -1 FP BE Pri
!#A N13895 N13896
!#7 N13897 P4981 BLD 2 -1 FP BE Pri
!#7 N13898 P4981 BLD 3 -1 FP BE Pri
!#7 N13899 P4982 BSTC 16 0x4300002d FP BE Pri
!#7 N13900 P4982 BSTC 17 0x4300002e FP BE Pri
!#A N13899 N13900
!#7 N13901 P4982 BSTC 18 0x4300002f FP BE Pri
!#7 N13902 P4982 BSTC 19 0x43000030 FP BE Pri
!#7 N13903 P4983 MEMBAR
!#7 N13904 P4984 DWLD 15 -1 Int BE Pri
!#7 N13905 P4985 LD 13 -1 Int BE Pri
!#7 N13906 P4986 LD 23 -1 Int BE Pri
!#7 N13907 P4987 BLD 20 -1 FP BE Pri
!#7 N13908 P4987 BLD 21 -1 FP BE Pri
!#A N13907 N13908
!#7 N13909 P4987 BLD 22 -1 FP BE Pri
!#7 N13910 P4987 BLD 23 -1 FP BE Pri
!#7 N13911 P4988 LD 1 -1 Int BE Pri
!#7 N13912 P4989 LD 11 -1 Int BE Pri
!#7 N13913 P4990 LD 5 -1 Int BE Pri
!#7 N13914 P4991 DWLD 11 -1 Int BE Pri
!#7 N13915 P4992 LD 4 -1 Int BE Pri
!#7 N13916 P4991 DWLD 11 -1 Int BE Pri
!#7 N13917 P4992 LD 4 -1 Int BE Pri
!#7 N13918 P4993 LD 18 -1 Int BE Pri
!#7 N13919 P4994 LD 31 -1 Int BE Pri
!#7 N13920 P4993 LD 18 -1 Int BE Pri
!#7 N13921 P4994 LD 31 -1 Int BE Pri
!#7 N13922 P4995 BLD 8 -1 FP BE Pri
!#7 N13923 P4995 BLD 9 -1 FP BE Pri
!#A N13922 N13923
!#7 N13924 P4995 BLD 10 -1 FP BE Pri
!#7 N13925 P4995 BLD 11 -1 FP BE Pri
!#7 N13926 P4996 DWLD 0 -1 Int BE Pri
!#7 N13927 P4996 DWLD 1 -1 Int BE Pri
!#A N13926 N13927
!#7 N13928 P4997 BLD 24 -1 FP BE Pri
!#7 N13929 P4997 BLD 25 -1 FP BE Pri
!#A N13928 N13929
!#7 N13930 P4997 BLD 26 -1 FP BE Pri
!#7 N13931 P4997 BLD 27 -1 FP BE Pri
!#7 N13932 P4996 DWLD 0 -1 Int BE Pri
!#7 N13933 P4996 DWLD 1 -1 Int BE Pri
!#A N13932 N13933
!#7 N13934 P4997 BLD 24 -1 FP BE Pri
!#7 N13935 P4997 BLD 25 -1 FP BE Pri
!#A N13934 N13935
!#7 N13936 P4997 BLD 26 -1 FP BE Pri
!#7 N13937 P4997 BLD 27 -1 FP BE Pri
!#7 N13938 P4998 DWLD 20 -1 Int BE Pri
!#7 N13939 P4998 DWLD 21 -1 Int BE Pri
!#A N13938 N13939
!#7 N13940 P4999 DWLD 30 -1 Int BE Pri
!#7 N13941 P5000 LD 16 -1 Int BE Pri
!#7 N13942 P5001 BLD 12 -1 FP BE Pri
!#7 N13943 P5001 BLD 13 -1 FP BE Pri
!#A N13942 N13943
!#7 N13944 P5001 BLD 14 -1 FP BE Pri
!#7 N13945 P5001 BLD 15 -1 FP BE Pri
!#7 N13946 P5002 BLD 8 -1 FP BE Pri
!#7 N13947 P5002 BLD 9 -1 FP BE Pri
!#A N13946 N13947
!#7 N13948 P5002 BLD 10 -1 FP BE Pri
!#7 N13949 P5002 BLD 11 -1 FP BE Pri
!#7 N13950 P5001 BLD 12 -1 FP BE Pri
!#7 N13951 P5001 BLD 13 -1 FP BE Pri
!#A N13950 N13951
!#7 N13952 P5001 BLD 14 -1 FP BE Pri
!#7 N13953 P5001 BLD 15 -1 FP BE Pri
!#7 N13954 P5002 BLD 8 -1 FP BE Pri
!#7 N13955 P5002 BLD 9 -1 FP BE Pri
!#A N13954 N13955
!#7 N13956 P5002 BLD 10 -1 FP BE Pri
!#7 N13957 P5002 BLD 11 -1 FP BE Pri
!#7 N13958 P5003 LD 4 -1 Int BE Pri
!#7 N13959 P5004 LD 30 -1 Int BE Pri
!#7 N13960 P5005 DWLD 24 -1 FP BE Pri
!#7 N13961 P5005 DWLD 25 -1 FP BE Pri
!#A N13960 N13961
!#7 N13962 P5006 LD 12 -1 Int BE Pri
!#7 N13963 P5007 LD 10 -1 Int BE Pri
!#7 N13964 P5006 LD 12 -1 Int BE Pri
!#7 N13965 P5007 LD 10 -1 Int BE Pri
!#7 N13966 P5008 LD 14 -1 Int BE Pri
!#7 N13967 P5009 LD 11 -1 Int BE Pri
!#7 N13968 P5008 LD 14 -1 Int BE Pri
!#7 N13969 P5009 LD 11 -1 Int BE Pri
!#7 N13970 P5010 DWLD 28 -1 Int LE Pri
!#7 N13971 P5010 DWLD 29 -1 Int LE Pri
!#A N13970 N13971
!#7 N13972 P5011 BLD 0 -1 FP BE Pri
!#7 N13973 P5011 BLD 1 -1 FP BE Pri
!#A N13972 N13973
!#7 N13974 P5011 BLD 2 -1 FP BE Pri
!#7 N13975 P5011 BLD 3 -1 FP BE Pri
!#7 N13976 P5012 DWLD 7 -1 Int BE Pri
!#7 N13977 P5013 LD 23 -1 Int BE Pri
!#7 N13978 P5012 DWLD 7 -1 Int BE Pri
!#7 N13979 P5013 LD 23 -1 Int BE Pri
!#7 N13980 P5014 LD 3 -1 Int BE Pri
!#7 N13981 P5015 LD 20 -1 Int BE Pri
!#7 N13982 P5014 LD 3 -1 Int BE Pri
!#7 N13983 P5015 LD 20 -1 Int BE Pri
!#7 N13984 P5016 DWLD 28 -1 Int BE Pri
!#7 N13985 P5016 DWLD 29 -1 Int BE Pri
!#A N13984 N13985
!#7 N13986 P5016 DWLD 28 -1 Int BE Pri
!#7 N13987 P5016 DWLD 29 -1 Int BE Pri
!#A N13986 N13987
!#7 N13988 P5017 BLD 24 -1 FP BE Pri
!#7 N13989 P5017 BLD 25 -1 FP BE Pri
!#A N13988 N13989
!#7 N13990 P5017 BLD 26 -1 FP BE Pri
!#7 N13991 P5017 BLD 27 -1 FP BE Pri
!#7 N13992 P5018 BLD 8 -1 FP BE Pri
!#7 N13993 P5018 BLD 9 -1 FP BE Pri
!#A N13992 N13993
!#7 N13994 P5018 BLD 10 -1 FP BE Pri
!#7 N13995 P5018 BLD 11 -1 FP BE Pri
!#7 N13996 P5019 DWLD 8 -1 Int LE Pri
!#7 N13997 P5019 DWLD 9 -1 Int LE Pri
!#A N13996 N13997
!#7 N13998 P5020 DWLD 8 -1 Int BE Pri
!#7 N13999 P5020 DWLD 9 -1 Int BE Pri
!#A N13998 N13999
!#7 N14000 P5019 DWLD 8 -1 Int LE Pri
!#7 N14001 P5019 DWLD 9 -1 Int LE Pri
!#A N14000 N14001
!#7 N14002 P5020 DWLD 8 -1 Int BE Pri
!#7 N14003 P5020 DWLD 9 -1 Int BE Pri
!#A N14002 N14003
!#7 N14004 P5021 BLD 8 -1 FP BE Pri
!#7 N14005 P5021 BLD 9 -1 FP BE Pri
!#A N14004 N14005
!#7 N14006 P5021 BLD 10 -1 FP BE Pri
!#7 N14007 P5021 BLD 11 -1 FP BE Pri
!#7 N14008 P5021 BLD 8 -1 FP BE Pri
!#7 N14009 P5021 BLD 9 -1 FP BE Pri
!#A N14008 N14009
!#7 N14010 P5021 BLD 10 -1 FP BE Pri
!#7 N14011 P5021 BLD 11 -1 FP BE Pri
!#7 N14012 P5022 MEMBAR
!#7 N14013 P5022 MEMBAR
!#7 N14014 P5023 LD 7 -1 FP BE Pri
!#7 N14015 P5024 LD 10 -1 Int BE Pri
!#7 N14016 P5025 LD 6 -1 Int BE Pri
!#7 N14017 P5026 LD 10 -1 Int BE Pri
!#7 N14018 P5027 LD 14 -1 Int BE Pri
!#7 N14019 P5028 DWLD 6 -1 Int BE Pri
!#7 N14020 P5029 DWLD 10 -1 Int BE Pri
!#7 N14021 P5030 DWLD 15 -1 Int BE Pri
!#7 N14022 P5031 BLD 28 -1 FP BE Pri
!#7 N14023 P5031 BLD 29 -1 FP BE Pri
!#A N14022 N14023
!#7 N14024 P5031 BLD 30 -1 FP BE Pri
!#7 N14025 P5031 BLD 31 -1 FP BE Pri
!#7 N14026 P5032 LD 31 -1 Int BE Pri
!#7 N14027 P5030 DWLD 15 -1 Int BE Pri
!#7 N14028 P5031 BLD 28 -1 FP BE Pri
!#7 N14029 P5031 BLD 29 -1 FP BE Pri
!#A N14028 N14029
!#7 N14030 P5031 BLD 30 -1 FP BE Pri
!#7 N14031 P5031 BLD 31 -1 FP BE Pri
!#7 N14032 P5032 LD 31 -1 Int BE Pri
!#7 N14033 P5033 DWST 31 0x3800014 Int BE Pri
!#7 N14034 P5033 DWST 31 0x3800015 Int BE Pri
!#7 N14035 P5034 LD 11 -1 Int BE Pri
!#7 N14036 P5035 LD 19 -1 Int BE Pri
!#7 N14037 P5036 DWLD 8 -1 Int BE Pri
!#7 N14038 P5036 DWLD 9 -1 Int BE Pri
!#A N14037 N14038
!#7 N14039 P5037 DWLD 23 -1 Int BE Pri
!#7 N14040 P5038 LD 14 -1 Int BE Pri
!#7 N14041 P5037 DWLD 23 -1 Int BE Pri
!#7 N14042 P5038 LD 14 -1 Int BE Pri
!#7 N14043 P5039 DWLD 4 -1 Int BE Pri
!#7 N14044 P5039 DWLD 5 -1 Int BE Pri
!#A N14043 N14044
!#7 N14045 P5040 LD 12 -1 Int BE Pri
!#7 N14046 P5041 LD 15 -1 Int BE Pri
!#7 N14047 P5039 DWLD 4 -1 Int BE Pri
!#7 N14048 P5039 DWLD 5 -1 Int BE Pri
!#A N14047 N14048
!#7 N14049 P5040 LD 12 -1 Int BE Pri
!#7 N14050 P5041 LD 15 -1 Int BE Pri
!#7 N14051 P5042 LD 18 -1 Int BE Pri
!#7 N14052 P5043 LD 9 -1 Int BE Pri
!#7 N14053 P5044 DWLD 30 -1 Int BE Pri
!#7 N14054 P5045 LD 7 -1 Int BE Pri
!#7 N14055 P5046 BLD 20 -1 FP BE Pri
!#7 N14056 P5046 BLD 21 -1 FP BE Pri
!#A N14055 N14056
!#7 N14057 P5046 BLD 22 -1 FP BE Pri
!#7 N14058 P5046 BLD 23 -1 FP BE Pri
!#7 N14059 P5046 BLD 20 -1 FP BE Pri
!#7 N14060 P5046 BLD 21 -1 FP BE Pri
!#A N14059 N14060
!#7 N14061 P5046 BLD 22 -1 FP BE Pri
!#7 N14062 P5046 BLD 23 -1 FP BE Pri
!#7 N14063 P5047 BLD 8 -1 FP BE Pri
!#7 N14064 P5047 BLD 9 -1 FP BE Pri
!#A N14063 N14064
!#7 N14065 P5047 BLD 10 -1 FP BE Pri
!#7 N14066 P5047 BLD 11 -1 FP BE Pri
!#7 N14067 P5048 BLD 16 -1 FP BE Pri
!#7 N14068 P5048 BLD 17 -1 FP BE Pri
!#A N14067 N14068
!#7 N14069 P5048 BLD 18 -1 FP BE Pri
!#7 N14070 P5048 BLD 19 -1 FP BE Pri
!#7 N14071 P5049 MEMBAR
!#7 N14072 P5048 BLD 16 -1 FP BE Pri
!#7 N14073 P5048 BLD 17 -1 FP BE Pri
!#A N14072 N14073
!#7 N14074 P5048 BLD 18 -1 FP BE Pri
!#7 N14075 P5048 BLD 19 -1 FP BE Pri
!#7 N14076 P5049 MEMBAR
!#7 N14077 P5050 LD 3 -1 Int BE Pri
!#7 N14078 P5051 LD 18 -1 Int BE Pri
!#7 N14079 P5050 LD 3 -1 Int BE Pri
!#7 N14080 P5051 LD 18 -1 Int BE Pri
!#7 N14082 P5053 BLD 8 -1 FP BE Pri
!#7 N14083 P5053 BLD 9 -1 FP BE Pri
!#A N14082 N14083
!#7 N14084 P5053 BLD 10 -1 FP BE Pri
!#7 N14085 P5053 BLD 11 -1 FP BE Pri
!#7 N14086 P5054 BLD 24 -1 FP BE Pri
!#7 N14087 P5054 BLD 25 -1 FP BE Pri
!#A N14086 N14087
!#7 N14088 P5054 BLD 26 -1 FP BE Pri
!#7 N14089 P5054 BLD 27 -1 FP BE Pri
!#7 N14090 P5054 BLD 24 -1 FP BE Pri
!#7 N14091 P5054 BLD 25 -1 FP BE Pri
!#A N14090 N14091
!#7 N14092 P5054 BLD 26 -1 FP BE Pri
!#7 N14093 P5054 BLD 27 -1 FP BE Pri
!#7 N14094 P5055 DWLD 4 -1 Int BE Pri
!#7 N14095 P5055 DWLD 5 -1 Int BE Pri
!#A N14094 N14095
!#7 N14096 P5056 DWLD 12 -1 FP BE Pri
!#7 N14097 P5056 DWLD 13 -1 FP BE Pri
!#A N14096 N14097
!#7 N14098 P5055 DWLD 4 -1 Int BE Pri
!#7 N14099 P5055 DWLD 5 -1 Int BE Pri
!#A N14098 N14099
!#7 N14100 P5056 DWLD 12 -1 FP BE Pri
!#7 N14101 P5056 DWLD 13 -1 FP BE Pri
!#A N14100 N14101
!#7 N14102 P5057 LD 8 -1 Int BE Pri
!#7 N14103 P5058 LD 24 -1 Int BE Pri
!#7 N14104 P5057 LD 8 -1 Int BE Pri
!#7 N14105 P5058 LD 24 -1 Int BE Pri
!#7 N14106 P5059 BLD 20 -1 FP BE Pri
!#7 N14107 P5059 BLD 21 -1 FP BE Pri
!#A N14106 N14107
!#7 N14108 P5059 BLD 22 -1 FP BE Pri
!#7 N14109 P5059 BLD 23 -1 FP BE Pri
!#7 N14110 P5059 BLD 20 -1 FP BE Pri
!#7 N14111 P5059 BLD 21 -1 FP BE Pri
!#A N14110 N14111
!#7 N14112 P5059 BLD 22 -1 FP BE Pri
!#7 N14113 P5059 BLD 23 -1 FP BE Pri
!#7 N14114 P5060 LD 8 -1 Int BE Pri
!#7 N14115 P5061 BLD 16 -1 FP BE Pri
!#7 N14116 P5061 BLD 17 -1 FP BE Pri
!#A N14115 N14116
!#7 N14117 P5061 BLD 18 -1 FP BE Pri
!#7 N14118 P5061 BLD 19 -1 FP BE Pri
!#7 N14119 P5062 LD 25 -1 Int BE Pri
!#7 N14120 P5060 LD 8 -1 Int BE Pri
!#7 N14121 P5061 BLD 16 -1 FP BE Pri
!#7 N14122 P5061 BLD 17 -1 FP BE Pri
!#A N14121 N14122
!#7 N14123 P5061 BLD 18 -1 FP BE Pri
!#7 N14124 P5061 BLD 19 -1 FP BE Pri
!#7 N14125 P5062 LD 25 -1 Int BE Pri
!#7 N14126 P5063 BLD 4 -1 FP BE Pri
!#7 N14127 P5063 BLD 5 -1 FP BE Pri
!#A N14126 N14127
!#7 N14128 P5063 BLD 6 -1 FP BE Pri
!#7 N14129 P5063 BLD 7 -1 FP BE Pri
!#7 N14130 P5064 LD 6 -1 Int BE Pri
!#7 N14131 P5065 DWLD 6 -1 FP BE Pri
!#7 N14132 P5066 LD 23 -1 Int BE Pri
!#7 N14133 P5064 LD 6 -1 Int BE Pri
!#7 N14134 P5065 DWLD 6 -1 FP BE Pri
!#7 N14135 P5066 LD 23 -1 Int BE Pri
!#7 N14136 P5067 LD 29 -1 Int BE Pri
!#7 N14137 P5068 LD 29 -1 Int BE Pri
!#7 N14138 P5067 LD 29 -1 Int BE Pri
!#7 N14139 P5068 LD 29 -1 Int BE Pri
!#7 N14140 P5069 LD 4 -1 Int BE Pri
!#7 N14141 P5070 BLD 16 -1 FP BE Pri
!#7 N14142 P5070 BLD 17 -1 FP BE Pri
!#A N14141 N14142
!#7 N14143 P5070 BLD 18 -1 FP BE Pri
!#7 N14144 P5070 BLD 19 -1 FP BE Pri
!#7 N14145 P5071 LD 12 -1 Int BE Pri
!#7 N14146 P5069 LD 4 -1 Int BE Pri
!#7 N14147 P5070 BLD 16 -1 FP BE Pri
!#7 N14148 P5070 BLD 17 -1 FP BE Pri
!#A N14147 N14148
!#7 N14149 P5070 BLD 18 -1 FP BE Pri
!#7 N14150 P5070 BLD 19 -1 FP BE Pri
!#7 N14151 P5071 LD 12 -1 Int BE Pri
!#7 N14152 P5072 LD 10 -1 Int BE Pri
!#7 N14153 P5073 DWLD 4 -1 Int BE Pri
!#7 N14154 P5073 DWLD 5 -1 Int BE Pri
!#A N14153 N14154
!#7 N14155 P5074 LD 21 -1 Int BE Pri
!#7 N14156 P5072 LD 10 -1 Int BE Pri
!#7 N14157 P5073 DWLD 4 -1 Int BE Pri
!#7 N14158 P5073 DWLD 5 -1 Int BE Pri
!#A N14157 N14158
!#7 N14159 P5074 LD 21 -1 Int BE Pri
!#7 N14160 P5075 DWLD 28 -1 Int BE Pri
!#7 N14161 P5075 DWLD 29 -1 Int BE Pri
!#A N14160 N14161
!#7 N14162 P5075 DWLD 28 -1 Int BE Pri
!#7 N14163 P5075 DWLD 29 -1 Int BE Pri
!#A N14162 N14163
!#7 N14164 P5076 DWLD 15 -1 Int BE Pri
!#7 N14165 P5077 LD 28 -1 Int BE Pri
!#7 N14166 P5078 SWAP 17 0xffffffff 0x3800016 Int BE Pri
!#7 N14167 P5079 LD 31 -1 FP BE Pri
!#7 N14168 P5080 LD 10 -1 Int BE Pri
!#7 N14169 P5078 SWAP 17 0xffffffff 0x3800017 Int BE Pri
!#7 N14170 P5079 LD 31 -1 FP BE Pri
!#7 N14171 P5080 LD 10 -1 Int BE Pri
!#7 N14172 P5081 DWLD 15 -1 Int BE Pri
!#7 N14173 P5082 BLD 24 -1 FP BE Pri
!#7 N14174 P5082 BLD 25 -1 FP BE Pri
!#A N14173 N14174
!#7 N14175 P5082 BLD 26 -1 FP BE Pri
!#7 N14176 P5082 BLD 27 -1 FP BE Pri
!#7 N14177 P5083 LD 31 -1 Int BE Pri
!#7 N14178 P5081 DWLD 15 -1 Int BE Pri
!#7 N14179 P5082 BLD 24 -1 FP BE Pri
!#7 N14180 P5082 BLD 25 -1 FP BE Pri
!#A N14179 N14180
!#7 N14181 P5082 BLD 26 -1 FP BE Pri
!#7 N14182 P5082 BLD 27 -1 FP BE Pri
!#7 N14183 P5083 LD 31 -1 Int BE Pri
!#7 N14184 P5084 DWLD 31 -1 Int BE Pri
!#7 N14185 P5085 LD 31 -1 Int BE Pri
!#7 N14186 P5086 BLD 4 -1 FP BE Pri
!#7 N14187 P5086 BLD 5 -1 FP BE Pri
!#A N14186 N14187
!#7 N14188 P5086 BLD 6 -1 FP BE Pri
!#7 N14189 P5086 BLD 7 -1 FP BE Pri
!#7 N14190 P5087 BLD 8 -1 FP BE Pri
!#7 N14191 P5087 BLD 9 -1 FP BE Pri
!#A N14190 N14191
!#7 N14192 P5087 BLD 10 -1 FP BE Pri
!#7 N14193 P5087 BLD 11 -1 FP BE Pri
!#7 N14194 P5088 BLD 24 -1 FP BE Pri
!#7 N14195 P5088 BLD 25 -1 FP BE Pri
!#A N14194 N14195
!#7 N14196 P5088 BLD 26 -1 FP BE Pri
!#7 N14197 P5088 BLD 27 -1 FP BE Pri
!#7 N14198 P5089 LD 27 -1 Int BE Pri
!#7 N14199 P5090 LD 20 -1 Int LE Pri
!#7 N14200 P5088 BLD 24 -1 FP BE Pri
!#7 N14201 P5088 BLD 25 -1 FP BE Pri
!#A N14200 N14201
!#7 N14202 P5088 BLD 26 -1 FP BE Pri
!#7 N14203 P5088 BLD 27 -1 FP BE Pri
!#7 N14204 P5089 LD 27 -1 Int BE Pri
!#7 N14205 P5090 LD 20 -1 Int LE Pri
!#7 N14206 P5091 BST 4 0x43000031 FP BE Pri
!#7 N14207 P5091 BST 5 0x43000032 FP BE Pri
!#A N14206 N14207
!#7 N14208 P5091 BST 6 0x43000033 FP BE Pri
!#7 N14209 P5091 BST 7 0x43000034 FP BE Pri
!#7 N14210 P5092 LD 28 -1 Int BE Pri
!#7 N14211 P5093 LD 13 -1 Int LE Pri
!#7 N14212 P5094 BLD 28 -1 FP BE Pri
!#7 N14213 P5094 BLD 29 -1 FP BE Pri
!#A N14212 N14213
!#7 N14214 P5094 BLD 30 -1 FP BE Pri
!#7 N14215 P5094 BLD 31 -1 FP BE Pri
!#7 N14216 P5095 BLD 8 -1 FP BE Pri
!#7 N14217 P5095 BLD 9 -1 FP BE Pri
!#A N14216 N14217
!#7 N14218 P5095 BLD 10 -1 FP BE Pri
!#7 N14219 P5095 BLD 11 -1 FP BE Pri
!#7 N14220 P5094 BLD 28 -1 FP BE Pri
!#7 N14221 P5094 BLD 29 -1 FP BE Pri
!#A N14220 N14221
!#7 N14222 P5094 BLD 30 -1 FP BE Pri
!#7 N14223 P5094 BLD 31 -1 FP BE Pri
!#7 N14224 P5095 BLD 8 -1 FP BE Pri
!#7 N14225 P5095 BLD 9 -1 FP BE Pri
!#A N14224 N14225
!#7 N14226 P5095 BLD 10 -1 FP BE Pri
!#7 N14227 P5095 BLD 11 -1 FP BE Pri
!#7 N14228 P5096 DWLD 16 -1 Int BE Pri
!#7 N14229 P5096 DWLD 17 -1 Int BE Pri
!#A N14228 N14229
!#7 N14230 P5097 DWLD 26 -1 Int BE Pri
!#7 N14231 P5098 LD 25 -1 Int BE Pri
!#7 N14232 P5097 DWLD 26 -1 Int BE Pri
!#7 N14233 P5098 LD 25 -1 Int BE Pri
!#7 N14234 P5099 DWLD 28 -1 Int BE Pri
!#7 N14235 P5099 DWLD 29 -1 Int BE Pri
!#A N14234 N14235
!#7 N14236 P5100 BLD 16 -1 FP BE Pri
!#7 N14237 P5100 BLD 17 -1 FP BE Pri
!#A N14236 N14237
!#7 N14238 P5100 BLD 18 -1 FP BE Pri
!#7 N14239 P5100 BLD 19 -1 FP BE Pri
!#7 N14240 P5099 DWLD 28 -1 Int BE Pri
!#7 N14241 P5099 DWLD 29 -1 Int BE Pri
!#A N14240 N14241
!#7 N14242 P5100 BLD 16 -1 FP BE Pri
!#7 N14243 P5100 BLD 17 -1 FP BE Pri
!#A N14242 N14243
!#7 N14244 P5100 BLD 18 -1 FP BE Pri
!#7 N14245 P5100 BLD 19 -1 FP BE Pri
!#7 N14246 P5101 DWLD 8 -1 Int BE Pri
!#7 N14247 P5101 DWLD 9 -1 Int BE Pri
!#A N14246 N14247
!#7 N14248 P5102 BLD 12 -1 FP BE Pri
!#7 N14249 P5102 BLD 13 -1 FP BE Pri
!#A N14248 N14249
!#7 N14250 P5102 BLD 14 -1 FP BE Pri
!#7 N14251 P5102 BLD 15 -1 FP BE Pri
!#7 N14252 P5103 LD 6 -1 Int BE Pri
!#7 N14253 P5104 LD 3 -1 Int BE Pri
!#7 N14254 P5105 LD 14 -1 Int BE Pri
!#7 N14255 P5106 LD 11 -1 Int BE Pri
!#7 N14256 P5105 LD 14 -1 Int BE Pri
!#7 N14257 P5106 LD 11 -1 Int BE Pri
!#7 N14258 P5107 BLD 4 -1 FP BE Pri
!#7 N14259 P5107 BLD 5 -1 FP BE Pri
!#A N14258 N14259
!#7 N14260 P5107 BLD 6 -1 FP BE Pri
!#7 N14261 P5107 BLD 7 -1 FP BE Pri
!#7 N14262 P5108 SWAP 29 0xffffffff 0x3800018 Int BE Pri
!#7 N14263 P5109 DWLD 23 -1 FP BE Pri
!#7 N14264 P5110 LD 12 -1 Int BE Pri
!#7 N14265 P5108 SWAP 29 0xffffffff 0x3800019 Int BE Pri
!#7 N14266 P5109 DWLD 23 -1 FP BE Pri
!#7 N14267 P5110 LD 12 -1 Int BE Pri
!#7 N14268 P5111 BLD 16 -1 FP BE Pri
!#7 N14269 P5111 BLD 17 -1 FP BE Pri
!#A N14268 N14269
!#7 N14270 P5111 BLD 18 -1 FP BE Pri
!#7 N14271 P5111 BLD 19 -1 FP BE Pri
!#7 N14272 P5112 LD 27 -1 Int BE Pri
!#7 N14273 P5113 LD 25 -1 Int BE Pri
!#7 N14274 P5112 LD 27 -1 Int BE Pri
!#7 N14275 P5113 LD 25 -1 Int BE Pri
!#7 N14276 P5114 LD 28 -1 Int BE Pri
!#7 N14277 P5115 BLD 16 -1 FP BE Pri
!#7 N14278 P5115 BLD 17 -1 FP BE Pri
!#A N14277 N14278
!#7 N14279 P5115 BLD 18 -1 FP BE Pri
!#7 N14280 P5115 BLD 19 -1 FP BE Pri
!#7 N14281 P5116 LD 15 -1 Int BE Pri
!#7 N14283 P5118 LD 12 -1 Int BE Pri
!#7 N14284 P5119 LD 25 -1 Int LE Pri
!#7 N14285 P5120 DWLD 16 -1 Int BE Pri
!#7 N14286 P5120 DWLD 17 -1 Int BE Pri
!#A N14285 N14286
!#7 N14287 P5121 DWLD 20 -1 Int BE Pri
!#7 N14288 P5121 DWLD 21 -1 Int BE Pri
!#A N14287 N14288
!#7 N14290 P5123 LD 24 -1 FP BE Pri
!#7 N14291 P5124 BLD 24 -1 FP BE Pri
!#7 N14292 P5124 BLD 25 -1 FP BE Pri
!#A N14291 N14292
!#7 N14293 P5124 BLD 26 -1 FP BE Pri
!#7 N14294 P5124 BLD 27 -1 FP BE Pri
!#7 N14295 P5125 DWLD 8 -1 Int BE Pri
!#7 N14296 P5125 DWLD 9 -1 Int BE Pri
!#A N14295 N14296
!#7 N14297 P5126 ST 25 0x380001a Int LE Pri
!#7 N14298 P5125 DWLD 8 -1 Int BE Pri
!#7 N14299 P5125 DWLD 9 -1 Int BE Pri
!#A N14298 N14299
!#7 N14300 P5126 ST 25 0x380001b Int LE Pri
!#7 N14301 P5127 LD 29 -1 Int BE Pri
!#7 N14302 P5128 LD 18 -1 Int BE Pri
!#7 N14303 P5127 LD 29 -1 Int BE Pri
!#7 N14304 P5128 LD 18 -1 Int BE Pri
!#7 N14305 P5129 LD 18 -1 Int BE Pri
!#7 N14306 P5130 LD 23 -1 Int BE Pri
!#7 N14307 P5129 LD 18 -1 Int BE Pri
!#7 N14308 P5130 LD 23 -1 Int BE Pri
!#7 N14309 P5131 BLD 12 -1 FP BE Pri
!#7 N14310 P5131 BLD 13 -1 FP BE Pri
!#A N14309 N14310
!#7 N14311 P5131 BLD 14 -1 FP BE Pri
!#7 N14312 P5131 BLD 15 -1 FP BE Pri
!#7 N14313 P5132 BSTC 8 0x43000035 FP BE Pri
!#7 N14314 P5132 BSTC 9 0x43000036 FP BE Pri
!#A N14313 N14314
!#7 N14315 P5132 BSTC 10 0x43000037 FP BE Pri
!#7 N14316 P5132 BSTC 11 0x43000038 FP BE Pri
!#7 N14317 P5131 BLD 12 -1 FP BE Pri
!#7 N14318 P5131 BLD 13 -1 FP BE Pri
!#A N14317 N14318
!#7 N14319 P5131 BLD 14 -1 FP BE Pri
!#7 N14320 P5131 BLD 15 -1 FP BE Pri
!#7 N14321 P5132 BSTC 8 0x43000039 FP BE Pri
!#7 N14322 P5132 BSTC 9 0x4300003a FP BE Pri
!#A N14321 N14322
!#7 N14323 P5132 BSTC 10 0x4300003b FP BE Pri
!#7 N14324 P5132 BSTC 11 0x4300003c FP BE Pri
!#7 N14325 P5133 DWLD 31 -1 Int BE Pri
!#7 N14326 P5134 LD 17 -1 Int LE Pri
!#7 N14327 P5135 LD 0 -1 Int BE Pri
!#7 N14329 P5137 LD 0 -1 Int BE Pri
!#7 N14330 P5138 LD 26 -1 Int BE Pri
!#7 N14331 P5139 SWAP 16 0xffffffff 0x380001c Int BE Pri
!#7 N14332 P5140 DWLD 3 -1 Int BE Pri
!#7 N14333 P5141 DWLD 20 -1 Int BE Pri
!#7 N14334 P5141 DWLD 21 -1 Int BE Pri
!#A N14333 N14334
!#7 N14335 P5142 LD 3 -1 Int BE Pri
!#7 N14336 P5140 DWLD 3 -1 Int BE Pri
!#7 N14337 P5141 DWLD 20 -1 Int BE Pri
!#7 N14338 P5141 DWLD 21 -1 Int BE Pri
!#A N14337 N14338
!#7 N14339 P5142 LD 3 -1 Int BE Pri
!#7 N14340 P5143 BLD 8 -1 FP BE Pri
!#7 N14341 P5143 BLD 9 -1 FP BE Pri
!#A N14340 N14341
!#7 N14342 P5143 BLD 10 -1 FP BE Pri
!#7 N14343 P5143 BLD 11 -1 FP BE Pri
!#7 N14344 P5144 BLD 16 -1 FP BE Pri
!#7 N14345 P5144 BLD 17 -1 FP BE Pri
!#A N14344 N14345
!#7 N14346 P5144 BLD 18 -1 FP BE Pri
!#7 N14347 P5144 BLD 19 -1 FP BE Pri
!#7 N14348 P5145 LD 23 -1 Int BE Pri
!#7 N14349 P5146 LD 7 -1 Int BE Pri
!#7 N14350 P5145 LD 23 -1 Int BE Pri
!#7 N14351 P5146 LD 7 -1 Int BE Pri
!#7 N14352 P5147 LD 7 -1 Int BE Pri
!#7 N14353 P5148 LD 29 -1 Int BE Pri
!#7 N14354 P5149 BLD 8 -1 FP BE Pri
!#7 N14355 P5149 BLD 9 -1 FP BE Pri
!#A N14354 N14355
!#7 N14356 P5149 BLD 10 -1 FP BE Pri
!#7 N14357 P5149 BLD 11 -1 FP BE Pri
!#7 N14358 P5150 BLD 24 -1 FP BE Pri
!#7 N14359 P5150 BLD 25 -1 FP BE Pri
!#A N14358 N14359
!#7 N14360 P5150 BLD 26 -1 FP BE Pri
!#7 N14361 P5150 BLD 27 -1 FP BE Pri
!#7 N14362 P5151 DWLD 18 -1 Int BE Pri
!#7 N14363 P5152 LD 24 -1 Int BE Pri
!#7 N14364 P5151 DWLD 18 -1 Int BE Pri
!#7 N14365 P5152 LD 24 -1 Int BE Pri
!#7 N14366 P5153 BLD 28 -1 FP BE Pri
!#7 N14367 P5153 BLD 29 -1 FP BE Pri
!#A N14366 N14367
!#7 N14368 P5153 BLD 30 -1 FP BE Pri
!#7 N14369 P5153 BLD 31 -1 FP BE Pri
!#7 N14370 P5154 BLD 12 -1 FP BE Pri
!#7 N14371 P5154 BLD 13 -1 FP BE Pri
!#A N14370 N14371
!#7 N14372 P5154 BLD 14 -1 FP BE Pri
!#7 N14373 P5154 BLD 15 -1 FP BE Pri
!#7 N14374 P5155 LD 5 -1 Int BE Pri
!#7 N14375 P5156 LD 10 -1 Int BE Pri
!#7 N14376 P5155 LD 5 -1 Int BE Pri
!#7 N14377 P5156 LD 10 -1 Int BE Pri
!#7 N14378 P5157 BLD 4 -1 FP BE Pri
!#7 N14379 P5157 BLD 5 -1 FP BE Pri
!#A N14378 N14379
!#7 N14380 P5157 BLD 6 -1 FP BE Pri
!#7 N14381 P5157 BLD 7 -1 FP BE Pri
!#7 N14382 P5157 BLD 4 -1 FP BE Pri
!#7 N14383 P5157 BLD 5 -1 FP BE Pri
!#A N14382 N14383
!#7 N14384 P5157 BLD 6 -1 FP BE Pri
!#7 N14385 P5157 BLD 7 -1 FP BE Pri
!#7 N14386 P5158 LD 5 -1 Int BE Pri
!#7 N14387 P5159 LD 29 -1 Int BE Pri
!#7 N14388 P5160 DWLD 8 -1 Int BE Pri
!#7 N14389 P5160 DWLD 9 -1 Int BE Pri
!#A N14388 N14389
!#7 N14390 P5160 DWLD 8 -1 Int BE Pri
!#7 N14391 P5160 DWLD 9 -1 Int BE Pri
!#A N14390 N14391
!#7 N14392 P5161 LD 14 -1 Int BE Pri
!#7 N14393 P5162 LD 15 -1 Int BE Pri
!#7 N14394 P5163 DWLD 8 -1 Int BE Pri
!#7 N14395 P5163 DWLD 9 -1 Int BE Pri
!#A N14394 N14395
!#7 N14396 P5164 BLD 24 -1 FP BE Pri
!#7 N14397 P5164 BLD 25 -1 FP BE Pri
!#A N14396 N14397
!#7 N14398 P5164 BLD 26 -1 FP BE Pri
!#7 N14399 P5164 BLD 27 -1 FP BE Pri
!#7 N14400 P5165 LD 22 -1 Int BE Pri
!#7 N14401 P5166 LD 31 -1 Int BE Pri
!#7 N14402 P5167 DWLD 2 -1 Int BE Pri
!#7 N14403 P5168 LD 29 -1 Int BE Pri
!#7 N14406 P5170 LD 15 -1 Int BE Pri
!#7 N14407 P5171 LD 18 -1 Int BE Pri
!#7 N14408 P5170 LD 15 -1 Int BE Pri
!#7 N14409 P5171 LD 18 -1 Int BE Pri
!#7 N14410 P5172 BLD 20 -1 FP BE Pri
!#7 N14411 P5172 BLD 21 -1 FP BE Pri
!#A N14410 N14411
!#7 N14412 P5172 BLD 22 -1 FP BE Pri
!#7 N14413 P5172 BLD 23 -1 FP BE Pri
!#7 N14414 P5173 LD 8 -1 Int BE Pri
!#7 N14415 P5174 LD 28 -1 Int BE Pri
!#7 N14416 P5172 BLD 20 -1 FP BE Pri
!#7 N14417 P5172 BLD 21 -1 FP BE Pri
!#A N14416 N14417
!#7 N14418 P5172 BLD 22 -1 FP BE Pri
!#7 N14419 P5172 BLD 23 -1 FP BE Pri
!#7 N14420 P5173 LD 8 -1 Int BE Pri
!#7 N14421 P5174 LD 28 -1 Int BE Pri
!#7 N14422 P5175 DWLD 28 -1 Int BE Pri
!#7 N14423 P5175 DWLD 29 -1 Int BE Pri
!#A N14422 N14423
!#7 N14424 P5176 DWLD 27 -1 Int BE Pri
!#7 N14425 P5177 LD 16 -1 Int BE Pri
!#7 N14426 P5178 LD 13 -1 Int BE Pri
!#7 N14427 P5179 BLD 24 -1 FP BE Pri
!#7 N14428 P5179 BLD 25 -1 FP BE Pri
!#A N14427 N14428
!#7 N14429 P5179 BLD 26 -1 FP BE Pri
!#7 N14430 P5179 BLD 27 -1 FP BE Pri
!#7 N14431 P5180 LD 9 -1 Int BE Pri
!#7 N14432 P5178 LD 13 -1 Int BE Pri
!#7 N14433 P5179 BLD 24 -1 FP BE Pri
!#7 N14434 P5179 BLD 25 -1 FP BE Pri
!#A N14433 N14434
!#7 N14435 P5179 BLD 26 -1 FP BE Pri
!#7 N14436 P5179 BLD 27 -1 FP BE Pri
!#7 N14437 P5180 LD 9 -1 Int BE Pri
!#7 N14438 P5181 BLD 12 -1 FP BE Pri
!#7 N14439 P5181 BLD 13 -1 FP BE Pri
!#A N14438 N14439
!#7 N14440 P5181 BLD 14 -1 FP BE Pri
!#7 N14441 P5181 BLD 15 -1 FP BE Pri
!#7 N14442 P5182 LD 24 -1 Int BE Pri
!#7 N14443 P5183 DWLD 11 -1 FP BE Pri
!#7 N14444 P5184 LD 16 -1 Int BE Pri
!#7 N14445 P5185 LD 8 -1 Int BE Pri
!#7 N14446 P5186 BLD 20 -1 FP BE Pri
!#7 N14447 P5186 BLD 21 -1 FP BE Pri
!#A N14446 N14447
!#7 N14448 P5186 BLD 22 -1 FP BE Pri
!#7 N14449 P5186 BLD 23 -1 FP BE Pri
!#7 N14450 P5187 LD 17 -1 Int BE Pri
!#7 N14451 P5188 DWLD 7 -1 Int LE Pri
!#7 N14452 P5189 LD 23 -1 FP BE Pri
!#7 N14453 P5190 LD 27 -1 Int BE Pri
!#7 N14454 P5191 DWLD 8 -1 Int BE Pri
!#7 N14455 P5191 DWLD 9 -1 Int BE Pri
!#A N14454 N14455
!#7 N14456 P5191 DWLD 8 -1 Int BE Pri
!#7 N14457 P5191 DWLD 9 -1 Int BE Pri
!#A N14456 N14457
!#7 N14458 P5192 DWLD 8 -1 Int LE Pri
!#7 N14459 P5192 DWLD 9 -1 Int LE Pri
!#A N14458 N14459
!#7 N14460 P5193 BLD 20 -1 FP BE Pri
!#7 N14461 P5193 BLD 21 -1 FP BE Pri
!#A N14460 N14461
!#7 N14462 P5193 BLD 22 -1 FP BE Pri
!#7 N14463 P5193 BLD 23 -1 FP BE Pri
!#7 N14464 P5192 DWLD 8 -1 Int LE Pri
!#7 N14465 P5192 DWLD 9 -1 Int LE Pri
!#A N14464 N14465
!#7 N14466 P5193 BLD 20 -1 FP BE Pri
!#7 N14467 P5193 BLD 21 -1 FP BE Pri
!#A N14466 N14467
!#7 N14468 P5193 BLD 22 -1 FP BE Pri
!#7 N14469 P5193 BLD 23 -1 FP BE Pri
!#7 N14470 P5194 LD 14 -1 Int BE Pri
!#7 N14471 P5195 LD 20 -1 Int BE Pri
!#7 N14472 P5194 LD 14 -1 Int BE Pri
!#7 N14473 P5195 LD 20 -1 Int BE Pri
!#7 N14476 P5197 LD 28 -1 FP BE Pri
!#7 N14477 P5197 LD 28 -1 FP BE Pri
!#7 N14478 P5198 DWLD 31 -1 Int BE Pri
!#7 N14479 P5199 LD 25 -1 Int BE Pri
!#7 N14480 P5200 DWLD 20 -1 Int BE Pri
!#7 N14481 P5200 DWLD 21 -1 Int BE Pri
!#A N14480 N14481
!#7 N14482 P5201 LD 18 -1 Int BE Pri
!#7 N14483 P5201 CAS 18 -1 N14482 0x380001d Int BE Pri
!#7 N14484 P5202 DWLD 19 -1 Int BE Pri
!#7 N14485 P5203 DWLD 24 -1 Int BE Pri
!#7 N14486 P5203 DWLD 25 -1 Int BE Pri
!#A N14485 N14486
!#7 N14487 P5204 LD 11 -1 Int BE Pri
!#7 N14488 P5202 DWLD 19 -1 Int BE Pri
!#7 N14489 P5203 DWLD 24 -1 Int BE Pri
!#7 N14490 P5203 DWLD 25 -1 Int BE Pri
!#A N14489 N14490
!#7 N14491 P5204 LD 11 -1 Int BE Pri
!#7 N14492 P5205 DWLD 8 -1 Int BE Pri
!#7 N14493 P5205 DWLD 9 -1 Int BE Pri
!#A N14492 N14493
!#7 N14494 P5206 DWLD 2 -1 Int BE Pri
!#7 N14495 P5207 BLD 8 -1 FP BE Pri
!#7 N14496 P5207 BLD 9 -1 FP BE Pri
!#A N14495 N14496
!#7 N14497 P5207 BLD 10 -1 FP BE Pri
!#7 N14498 P5207 BLD 11 -1 FP BE Pri
!#7 N14499 P5208 LD 30 -1 Int BE Pri
!#7 N14500 P5206 DWLD 2 -1 Int BE Pri
!#7 N14501 P5207 BLD 8 -1 FP BE Pri
!#7 N14502 P5207 BLD 9 -1 FP BE Pri
!#A N14501 N14502
!#7 N14503 P5207 BLD 10 -1 FP BE Pri
!#7 N14504 P5207 BLD 11 -1 FP BE Pri
!#7 N14505 P5208 LD 30 -1 Int BE Pri
!#7 N14506 P5209 LD 21 -1 Int BE Pri
!#7 N14507 P5209 CAS 21 -1 N14506 0x380001e Int BE Pri
!#7 N14508 P5210 LD 5 -1 Int BE Pri
!#7 N14509 P5210 CAS 5 -1 N14508 0x380001f Int BE Pri
!#7 N14510 P5209 LD 21 -1 Int BE Pri
!#7 N14511 P5209 CAS 21 -1 N14510 0x3800020 Int BE Pri
!#7 N14512 P5210 LD 5 -1 Int BE Pri
!#7 N14513 P5210 CAS 5 -1 N14512 0x3800021 Int BE Pri
!#7 N14514 P5211 BLD 0 -1 FP BE Pri
!#7 N14515 P5211 BLD 1 -1 FP BE Pri
!#A N14514 N14515
!#7 N14516 P5211 BLD 2 -1 FP BE Pri
!#7 N14517 P5211 BLD 3 -1 FP BE Pri
!#7 N14518 P5212 BLD 28 -1 FP BE Pri
!#7 N14519 P5212 BLD 29 -1 FP BE Pri
!#A N14518 N14519
!#7 N14520 P5212 BLD 30 -1 FP BE Pri
!#7 N14521 P5212 BLD 31 -1 FP BE Pri
!#7 N14522 P5211 BLD 0 -1 FP BE Pri
!#7 N14523 P5211 BLD 1 -1 FP BE Pri
!#A N14522 N14523
!#7 N14524 P5211 BLD 2 -1 FP BE Pri
!#7 N14525 P5211 BLD 3 -1 FP BE Pri
!#7 N14526 P5212 BLD 28 -1 FP BE Pri
!#7 N14527 P5212 BLD 29 -1 FP BE Pri
!#A N14526 N14527
!#7 N14528 P5212 BLD 30 -1 FP BE Pri
!#7 N14529 P5212 BLD 31 -1 FP BE Pri
!#7 N14530 P5213 DWLD 2 -1 Int BE Pri
!#7 N14531 P5214 LD 11 -1 Int BE Pri
!#7 N14532 P5213 DWLD 2 -1 Int BE Pri
!#7 N14533 P5214 LD 11 -1 Int BE Pri
!#7 N14534 P5215 LD 29 -1 Int BE Pri
!#7 N14536 P5217 LD 2 -1 Int BE Pri
!#7 N14537 P5215 LD 29 -1 Int BE Pri
!#7 N14539 P5217 LD 2 -1 Int BE Pri
!#7 N14540 P5218 MEMBAR
!#7 N14541 P5219 BLD 20 -1 FP BE Pri
!#7 N14542 P5219 BLD 21 -1 FP BE Pri
!#A N14541 N14542
!#7 N14543 P5219 BLD 22 -1 FP BE Pri
!#7 N14544 P5219 BLD 23 -1 FP BE Pri
!#7 N14545 P5220 DWLD 18 -1 Int BE Pri
!#7 N14546 P5221 LD 6 -1 Int BE Pri
!#7 N14547 P5220 DWLD 18 -1 Int BE Pri
!#7 N14548 P5221 LD 6 -1 Int BE Pri
!#7 N14549 P5222 ST 19 0x3800022 Int BE Pri
!#7 N14550 P5222 ST 19 0x3800023 Int BE Pri
!#7 N14551 P5223 DWLD 12 -1 Int BE Pri
!#7 N14552 P5223 DWLD 13 -1 Int BE Pri
!#A N14551 N14552
!#7 N14553 P5223 CASX 12 -1 N14551 0x3800024 Int BE Pri
!#7 N14554 P5223 CASX 13 -1 N14552 0x3800025 Int BE Pri
!#A N14553 N14554
!#7 N14555 P5223 DWLD 12 -1 Int BE Pri
!#7 N14556 P5223 DWLD 13 -1 Int BE Pri
!#A N14555 N14556
!#7 N14557 P5223 CASX 12 -1 N14555 0x3800026 Int BE Pri
!#7 N14558 P5223 CASX 13 -1 N14556 0x3800027 Int BE Pri
!#A N14557 N14558
!#7 N14559 P5224 DWLD 19 -1 Int BE Pri
!#7 N14560 P5225 LD 5 -1 Int LE Pri
!#7 N14561 P5226 LD 16 -1 Int BE Pri
!#7 N14562 P5227 LD 20 -1 Int BE Pri
!#7 N14563 P5228 DWLD 24 -1 FP BE Pri
!#7 N14564 P5228 DWLD 25 -1 FP BE Pri
!#A N14563 N14564
!#7 N14565 P5228 DWLD 24 -1 FP BE Pri
!#7 N14566 P5228 DWLD 25 -1 FP BE Pri
!#A N14565 N14566
!#7 N14568 P5230 LD 23 -1 Int BE Pri
!#7 N14569 P5231 LD 22 -1 Int BE Pri
!#7 N14570 P5232 DWLD 20 -1 Int BE Pri
!#7 N14571 P5232 DWLD 21 -1 Int BE Pri
!#A N14570 N14571
!#7 N14572 P5233 DWLD 0 -1 Int BE Pri
!#7 N14573 P5233 DWLD 1 -1 Int BE Pri
!#A N14572 N14573
!#7 N14574 P5234 LD 18 -1 FP BE Pri
!#7 N14575 P5235 DWLD 11 -1 Int BE Pri
!#7 N14576 P5236 LD 2 -1 Int BE Pri
!#7 N14577 P5234 LD 18 -1 FP BE Pri
!#7 N14578 P5235 DWLD 11 -1 Int BE Pri
!#7 N14579 P5236 LD 2 -1 Int BE Pri
!#7 N14580 P5237 LD 13 -1 Int BE Pri
!#7 N14581 P5238 LD 18 -1 Int BE Pri
!#7 N14582 P5239 DWLD 0 -1 Int BE Pri
!#7 N14583 P5239 DWLD 1 -1 Int BE Pri
!#A N14582 N14583
!#7 N14584 P5239 CASX 0 -1 N14582 0x3800028 Int BE Pri
!#7 N14585 P5239 CASX 1 -1 N14583 0x3800029 Int BE Pri
!#A N14584 N14585
!#7 N14586 P5240 DWLD 23 -1 Int BE Pri
!#7 N14587 P5241 DWST 12 0x380002a Int BE Pri
!#7 N14588 P5241 DWST 13 0x380002b Int BE Pri
!#A N14587 N14588
!#7 N14589 P5242 LD 25 -1 Int BE Pri
!#7 N14590 P5240 DWLD 23 -1 Int BE Pri
!#7 N14591 P5241 DWST 12 0x380002c Int BE Pri
!#7 N14592 P5241 DWST 13 0x380002d Int BE Pri
!#A N14591 N14592
!#7 N14593 P5242 LD 25 -1 Int BE Pri
!#7 N14594 P5243 DWLD 2 -1 Int BE Pri
!#7 N14595 P5244 BLD 20 -1 FP BE Pri
!#7 N14596 P5244 BLD 21 -1 FP BE Pri
!#A N14595 N14596
!#7 N14597 P5244 BLD 22 -1 FP BE Pri
!#7 N14598 P5244 BLD 23 -1 FP BE Pri
!#7 N14599 P5245 LD 29 -1 Int BE Pri
!#7 N14600 P5243 DWLD 2 -1 Int BE Pri
!#7 N14601 P5244 BLD 20 -1 FP BE Pri
!#7 N14602 P5244 BLD 21 -1 FP BE Pri
!#A N14601 N14602
!#7 N14603 P5244 BLD 22 -1 FP BE Pri
!#7 N14604 P5244 BLD 23 -1 FP BE Pri
!#7 N14605 P5245 LD 29 -1 Int BE Pri
!#7 N14606 P5246 BST 28 0x4300003d FP BE Pri
!#7 N14607 P5246 BST 29 0x4300003e FP BE Pri
!#A N14606 N14607
!#7 N14608 P5246 BST 30 0x4300003f FP BE Pri
!#7 N14609 P5246 BST 31 0x43000040 FP BE Pri
!#7 N14610 P5247 BLD 28 -1 FP BE Pri
!#7 N14611 P5247 BLD 29 -1 FP BE Pri
!#A N14610 N14611
!#7 N14612 P5247 BLD 30 -1 FP BE Pri
!#7 N14613 P5247 BLD 31 -1 FP BE Pri
!#7 N14614 P5248 LD 17 -1 Int BE Pri
!#7 N14615 P5248 CAS 17 -1 N14614 0x380002e Int BE Pri
!#7 N14617 P5250 DWLD 8 -1 Int BE Pri
!#7 N14618 P5250 DWLD 9 -1 Int BE Pri
!#A N14617 N14618
!#7 N14619 P5251 LD 29 -1 Int BE Pri
!#7 N14620 P5252 LD 10 -1 Int BE Pri
!#7 N14621 P5251 LD 29 -1 Int BE Pri
!#7 N14622 P5252 LD 10 -1 Int BE Pri
!#7 N14623 P5253 DWST 10 0x380002f Int BE Pri
!#7 N14624 P5253 DWST 10 0x3800030 Int BE Pri
!#7 N14625 P5254 DWST 28 0x3800031 Int BE Pri
!#7 N14626 P5254 DWST 29 0x3800032 Int BE Pri
!#A N14625 N14626
!#7 N14627 P5255 BLD 24 -1 FP BE Pri
!#7 N14628 P5255 BLD 25 -1 FP BE Pri
!#A N14627 N14628
!#7 N14629 P5255 BLD 26 -1 FP BE Pri
!#7 N14630 P5255 BLD 27 -1 FP BE Pri
!#7 N14631 P5255 BLD 24 -1 FP BE Pri
!#7 N14632 P5255 BLD 25 -1 FP BE Pri
!#A N14631 N14632
!#7 N14633 P5255 BLD 26 -1 FP BE Pri
!#7 N14634 P5255 BLD 27 -1 FP BE Pri
!#7 N14635 P5256 DWLD 8 -1 Int BE Pri
!#7 N14636 P5256 DWLD 9 -1 Int BE Pri
!#A N14635 N14636
!#7 N14637 P5257 LD 3 -1 Int BE Pri
!#7 N14638 P5258 LD 9 -1 Int BE Pri
!#7 N14639 P5256 DWLD 8 -1 Int BE Pri
!#7 N14640 P5256 DWLD 9 -1 Int BE Pri
!#A N14639 N14640
!#7 N14641 P5257 LD 3 -1 Int BE Pri
!#7 N14642 P5258 LD 9 -1 Int BE Pri
!#7 N14643 P5259 LD 21 -1 Int BE Pri
!#7 N14644 P5260 LD 11 -1 Int BE Pri
!#7 N14645 P5259 LD 21 -1 Int BE Pri
!#7 N14646 P5260 LD 11 -1 Int BE Pri
!#7 N14647 P5261 LD 7 -1 FP BE Pri
!#7 N14648 P5262 LD 23 -1 Int BE Pri
!#7 N14649 P5263 LD 15 -1 Int BE Pri
!#7 N14650 P5261 LD 7 -1 FP BE Pri
!#7 N14651 P5262 LD 23 -1 Int BE Pri
!#7 N14652 P5263 LD 15 -1 Int BE Pri
!#7 N14653 P5264 BLD 12 -1 FP BE Pri
!#7 N14654 P5264 BLD 13 -1 FP BE Pri
!#A N14653 N14654
!#7 N14655 P5264 BLD 14 -1 FP BE Pri
!#7 N14656 P5264 BLD 15 -1 FP BE Pri
!#7 N14657 P5265 DWLD 16 -1 Int BE Pri
!#7 N14658 P5265 DWLD 17 -1 Int BE Pri
!#A N14657 N14658
!#7 N14660 P5265 DWLD 16 -1 Int BE Pri
!#7 N14661 P5265 DWLD 17 -1 Int BE Pri
!#A N14660 N14661
!#7 N14663 P5267 DWLD 27 -1 Int BE Pri
!#7 N14664 P5268 LD 21 -1 Int BE Pri
!#7 N14665 P5269 DWLD 14 -1 Int BE Pri
!#7 N14666 P5270 DWST 6 0x43000041 FP BE Pri
!#7 N14667 P5271 LD 10 -1 Int BE Pri
!#7 N14668 P5272 BLD 0 -1 FP BE Pri
!#7 N14669 P5272 BLD 1 -1 FP BE Pri
!#A N14668 N14669
!#7 N14670 P5272 BLD 2 -1 FP BE Pri
!#7 N14671 P5272 BLD 3 -1 FP BE Pri
!#7 N14672 P5273 LD 28 -1 Int BE Pri
!#7 N14673 P5274 BLD 0 -1 FP BE Pri
!#7 N14674 P5274 BLD 1 -1 FP BE Pri
!#A N14673 N14674
!#7 N14675 P5274 BLD 2 -1 FP BE Pri
!#7 N14676 P5274 BLD 3 -1 FP BE Pri
!#7 N14677 P5275 LD 24 -1 Int BE Pri
!#7 N14678 P5276 LD 6 -1 Int BE Pri
!#7 N14679 P5277 LD 28 -1 Int BE Pri
!#7 N14680 P5278 LD 19 -1 Int BE Pri
!#7 N14681 P5279 LD 6 -1 Int BE Pri
!#7 N14682 P5280 DWLD 26 -1 Int BE Pri
!#7 N14683 P5281 DWLD 16 -1 Int BE Pri
!#7 N14684 P5281 DWLD 17 -1 Int BE Pri
!#A N14683 N14684
!#7 N14685 P5282 LD 21 -1 Int BE Pri
!#7 N14686 P5280 DWLD 26 -1 Int BE Pri
!#7 N14687 P5281 DWLD 16 -1 Int BE Pri
!#7 N14688 P5281 DWLD 17 -1 Int BE Pri
!#A N14687 N14688
!#7 N14689 P5282 LD 21 -1 Int BE Pri
!#7 N14690 P5283 BLD 8 -1 FP BE Pri
!#7 N14691 P5283 BLD 9 -1 FP BE Pri
!#A N14690 N14691
!#7 N14692 P5283 BLD 10 -1 FP BE Pri
!#7 N14693 P5283 BLD 11 -1 FP BE Pri
!#7 N14694 P5284 BLD 12 -1 FP BE Pri
!#7 N14695 P5284 BLD 13 -1 FP BE Pri
!#A N14694 N14695
!#7 N14696 P5284 BLD 14 -1 FP BE Pri
!#7 N14697 P5284 BLD 15 -1 FP BE Pri
!#7 N14698 P5285 DWLD 10 -1 Int LE Pri
!#7 N14699 P5286 LD 21 -1 Int BE Pri
!#7 N14700 P5287 LD 2 -1 Int BE Pri
!#7 N14701 P5288 LD 24 -1 Int BE Pri
!#7 N14702 P5289 BLD 20 -1 FP BE Pri
!#7 N14703 P5289 BLD 21 -1 FP BE Pri
!#A N14702 N14703
!#7 N14704 P5289 BLD 22 -1 FP BE Pri
!#7 N14705 P5289 BLD 23 -1 FP BE Pri
!#7 N14706 P5290 DWLD 4 -1 Int BE Pri
!#7 N14707 P5290 DWLD 5 -1 Int BE Pri
!#A N14706 N14707
!#7 N14708 P5291 LD 5 -1 Int BE Pri
!#7 N14709 P5292 LD 5 -1 Int BE Pri
!#7 N14710 P5293 DWLD 4 -1 Int BE Pri
!#7 N14711 P5293 DWLD 5 -1 Int BE Pri
!#A N14710 N14711
!#7 N14712 P5293 CASX 4 -1 N14710 0x3800033 Int BE Pri
!#7 N14713 P5293 CASX 5 -1 N14711 0x3800034 Int BE Pri
!#A N14712 N14713
!#7 N14714 P5293 DWLD 4 -1 Int BE Pri
!#7 N14715 P5293 DWLD 5 -1 Int BE Pri
!#A N14714 N14715
!#7 N14716 P5293 CASX 4 -1 N14714 0x3800035 Int BE Pri
!#7 N14717 P5293 CASX 5 -1 N14715 0x3800036 Int BE Pri
!#A N14716 N14717
!#7 N14718 P5294 LD 21 -1 Int BE Pri
!#7 N14719 P5295 LD 4 -1 Int BE Pri
!#7 N14720 P5294 LD 21 -1 Int BE Pri
!#7 N14721 P5295 LD 4 -1 Int BE Pri
!#7 N14722 P5296 LD 26 -1 Int BE Pri
!#7 N14723 P5297 LD 4 -1 Int BE Pri
!#7 N14724 P5298 DWLD 22 -1 Int BE Pri
!#7 N14725 P5299 LD 21 -1 Int BE Pri
!#7 N14726 P5298 DWLD 22 -1 Int BE Pri
!#7 N14727 P5299 LD 21 -1 Int BE Pri
!#7 N14728 P5300 BLD 20 -1 FP BE Pri
!#7 N14729 P5300 BLD 21 -1 FP BE Pri
!#A N14728 N14729
!#7 N14730 P5300 BLD 22 -1 FP BE Pri
!#7 N14731 P5300 BLD 23 -1 FP BE Pri
!#7 N14732 P5301 DWLD 26 -1 Int BE Pri
!#7 N14733 P5302 LD 3 -1 Int BE Pri
!#7 N14734 P5301 DWLD 26 -1 Int BE Pri
!#7 N14735 P5302 LD 3 -1 Int BE Pri
!#7 N14736 P5303 DWLD 8 -1 Int BE Pri
!#7 N14737 P5303 DWLD 9 -1 Int BE Pri
!#A N14736 N14737
!#7 N14738 P5304 DWLD 11 -1 Int BE Pri
!#7 N14739 P5305 LD 15 -1 Int BE Pri
!#7 N14740 P5303 DWLD 8 -1 Int BE Pri
!#7 N14741 P5303 DWLD 9 -1 Int BE Pri
!#A N14740 N14741
!#7 N14742 P5304 DWLD 11 -1 Int BE Pri
!#7 N14743 P5305 LD 15 -1 Int BE Pri
!#7 N14744 P5306 LD 25 -1 Int LE Pri
!#7 N14745 P5307 LD 23 -1 Int BE Pri
!#7 N14746 P5308 DWLD 27 -1 Int BE Pri
!#7 N14747 P5309 LD 7 -1 Int BE Pri
!#7 N14748 P5310 DWLD 23 -1 Int LE Pri
!#7 N14749 P5311 LD 19 -1 Int BE Pri
!#7 N14750 P5310 DWLD 23 -1 Int LE Pri
!#7 N14751 P5311 LD 19 -1 Int BE Pri
!#7 N14752 P5312 LD 20 -1 Int BE Pri
!#7 N14753 P5313 LD 19 -1 Int BE Pri
!#7 N14754 P5312 LD 20 -1 Int BE Pri
!#7 N14755 P5313 LD 19 -1 Int BE Pri
!#7 N14756 P5314 DWLD 12 -1 Int BE Pri
!#7 N14757 P5314 DWLD 13 -1 Int BE Pri
!#A N14756 N14757
!#7 N14758 P5314 DWLD 12 -1 Int BE Pri
!#7 N14759 P5314 DWLD 13 -1 Int BE Pri
!#A N14758 N14759
!#7 N14760 P5315 LD 22 -1 Int BE Pri
!#7 N14761 P5316 LD 27 -1 Int LE Pri
!#7 N14762 P5315 LD 22 -1 Int BE Pri
!#7 N14763 P5316 LD 27 -1 Int LE Pri
!#7 N14764 P5317 DWLD 24 -1 Int BE Pri
!#7 N14765 P5317 DWLD 25 -1 Int BE Pri
!#A N14764 N14765
!#7 N14766 P5317 DWLD 24 -1 Int BE Pri
!#7 N14767 P5317 DWLD 25 -1 Int BE Pri
!#A N14766 N14767
!#7 N14768 P5318 DWLD 8 -1 Int BE Pri
!#7 N14769 P5318 DWLD 9 -1 Int BE Pri
!#A N14768 N14769
!#7 N14770 P5319 DWLD 28 -1 Int BE Pri
!#7 N14771 P5319 DWLD 29 -1 Int BE Pri
!#A N14770 N14771
!#7 N14772 P5318 DWLD 8 -1 Int BE Pri
!#7 N14773 P5318 DWLD 9 -1 Int BE Pri
!#A N14772 N14773
!#7 N14774 P5319 DWLD 28 -1 Int BE Pri
!#7 N14775 P5319 DWLD 29 -1 Int BE Pri
!#A N14774 N14775
!#7 N14776 P5320 MEMBAR
Full OpenSPARC design & verification tarball including full HDL.