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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / diag / assembly / uarch / tlu / diag / newfcrand05 / fcrand05_rand_43.s
/*
* ========== Copyright Header Begin ==========================================
*
* OpenSPARC T2 Processor File: fcrand05_rand_43.s
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
*
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
* For the avoidance of doubt, and except that if any non-GPL license
* choice is available it will apply instead, Sun elects to use only
* the General Public License version 2 (GPLv2) at this time for any
* software where a choice of GPL license versions is made
* available with the language indicating that GPLv2 or any later version
* may be used, or where a choice of which version of the GPL is applied is
* otherwise unspecified.
*
* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
* CA 95054 USA or visit www.sun.com if you need additional information or
* have any questions.
*
*
* ========== Copyright Header End ============================================
*/
#define NO_INTERNAL_SPU
#define IMMU_SKIP_IF_NO_TTE
#define DMMU_SKIP_IF_NO_TTE
#define MAIN_PAGE_NUCLEUS_ALSO
#define MAIN_PAGE_HV_ALSO
#define MAIN_PAGE_VA_IS_RA_ALSO
#define DISABLE_PART_LIMIT_CHECK
#define MAIN_PAGE_USE_CONFIG 3
#define PART0_Z_TSB_SIZE_3 10
#define PART0_Z_PAGE_SIZE_3 1
#define PART0_NZ_TSB_SIZE_3 10
#define PART0_NZ_PAGE_SIZE_3 1
#define PART0_Z_TSB_SIZE_1 3
#define PART0_NZ_TSB_SIZE_1 3
#define PART_0_BASE 0x0
#define USER_PAGE_CUSTOM_MAP
#define MAIN_BASE_TEXT_VA 0x333000000
#define MAIN_BASE_TEXT_RA 0x033000000
#define MAIN_BASE_DATA_VA 0x379400000
#define MAIN_BASE_DATA_RA 0x079400000
#define HIGHVA_HIGHNUM 0x3
#d
#define NO_EOB_MARKER
#undef INC_ERR_TRAPS
#undef H_HT0_Instruction_Access_MMU_Error_0x71
#define H_HT0_Instruction_Access_MMU_Error_0x71
#define SUN_H_HT0_Instruction_Access_MMU_Error_0x71 \
mov 0x80, %l3;\
stxa %g0, [%l3]0x57;\
retry;
#undef H_HT0_Instruction_access_error_0x0a
#define H_HT0_Instruction_access_error_0x0a
#define SUN_H_HT0_Instruction_access_error_0x0a retry
#undef H_HT0_Internal_Processor_Error_0x29
#define H_HT0_Internal_Processor_Error_0x29
#define SUN_H_HT0_Internal_Processor_Error_0x29 retry
#undef H_HT0_Data_Access_MMU_Error_0x72
#define H_HT0_Data_Access_MMU_Error_0x72
#define SUN_H_HT0_Data_Access_MMU_Error_0x72 \
mov 0x80, %l3;\
stxa %g0, [%l3]0x5f;\
retry;
#undef H_HT0_Data_access_error_0x32
#define H_HT0_Data_access_error_0x32
#define SUN_H_HT0_Data_access_error_0x32 \
add %g0, 0x18, %i1;\
ldxa [%i1] 0x58, %i2;\
cmp %i2, 0x4;\
bne 1f;\
nop;\
done;\
1:retry
#undef H_HT0_Hw_Corrected_Error_0x63
#define H_HT0_Hw_Corrected_Error_0x63
#define SUN_H_HT0_Hw_Corrected_Error_0x63 ldxa [%g0]ASI_DESR, %i1; retry
#undef H_HT0_Sw_Recoverable_Error_0x40
#define H_HT0_Sw_Recoverable_Error_0x40
#define SUN_H_HT0_Sw_Recoverable_Error_0x40 ldxa [%g0]ASI_DESR, %i1; retry
#undef H_HT0_Store_Error_0x07
#define H_HT0_Store_Error_0x07
#define SUN_H_HT0_Store_Error_0x07 retry
#define DAE_SKIP_IF_SOCU_ERROR
#ifndef T_HANDLER_RAND4_1
#define T_HANDLER_RAND4_1 b .+16;\
sdiv %r1, %r0, %l4;nop;nop
#endif
#ifndef T_HANDLER_RAND7_1
#define T_HANDLER_RAND7_1 b .+28;\
pdist %f4, %f6, %f20; \
nop; nop ; nop; nop; illtrap
#endif
#ifndef T_HANDLER_RAND4_2
#define T_HANDLER_RAND4_2 save %i7, %g0, %i7; \
save %i7, %g0, %i7; \
restore %i7, %g0, %i7;\
restore %i7, %g0, %i7;
#endif
#ifndef T_HANDLER_RAND7_2
#define T_HANDLER_RAND7_2 b .+8 ;\
rdpr %pstate, %l2;\
b .+8 ;\
rdpr %tstate, %l3;\
b .+12 ;\
wrpr %l3, %r0, %tstate; nop
#endif
#ifndef T_HANDLER_RAND4_3
#define T_HANDLER_RAND4_3 save %i7, %g0, %i7;\
restore %i7, %g0, %i7;\
save %i7, %g0, %i7; \
restore %i7, %g0, %i7;
#endif
#ifndef T_HANDLER_RAND7_3
#define T_HANDLER_RAND7_3 b .+8 ;\
rdpr %tnpc, %l2;\
and %l2, 0xfc0, %l2;\
add %i7, %l2, %l2;\
stda %f16,[%i7]ASI_BLOCK_AS_IF_USER_PRIMARY ;\
b .+8 ;\
stda %f0,[%i7]ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE ;
#endif
#ifndef T_HANDLER_RAND4_4
#define T_HANDLER_RAND4_4 b .+4 ; b .+4; b .+4; b .+4
#endif
#ifndef T_HANDLER_RAND7_4
#define T_HANDLER_RAND7_4 b .+8;\
save %i7, %g0, %i7; \
b,a .+8;\
b .+12;\
stw %i7, [%i7];\
b .-8;;\
restore %i7, %g0, %i7;
#endif
#ifndef T_HANDLER_RAND4_5
#define T_HANDLER_RAND4_5 ldda [%r31]ASI_NUCLEUS_QUAD_LDD, %f16;\
sdiv %l4, %l5, %l7;\
add %r31, 128, %l5;\
stda %l4, [%i7]ASI_BLOCK_PRIMARY_LITTLE;
#endif
#ifndef T_HANDLER_RAND7_5
#define T_HANDLER_RAND7_5 save %i7, %g0, %i7;\
rdpr %tnpc, %l2;\
wrpr %l2, %tpc;\
add %l2, 4, %l2;\
wrpr %l2, %tnpc;\
restore %i7, %g0, %i7;\
retry;
#endif
#ifndef T_HANDLER_RAND4_6
#define T_HANDLER_RAND4_6 ldda [%r31]ASI_BLOCK_AS_IF_USER_PRIMARY, %f32;\
rd %fprs, %l2; \
wr %l2, 0x4, %fprs ;\
stda %f0,[%r31]ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE;
#endif
#ifndef T_HANDLER_RAND7_6
#define T_HANDLER_RAND7_6 umul %o4, 2, %o5;\
rdpr %tnpc, %l2;\
wrpr %l2, %tpc;\
add %l2, 4, %l2;\
wrpr %l2, %tnpc;\
stw %l2, [%i7];\
retry;
#endif
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
#ifndef HT_HANDLER_RAND4_1
#define HT_HANDLER_RAND4_1 mov 0x80, %l3;\
b .+12;\
stxa %l3, [%l3]0x57 ;\
nop
#endif
#ifndef HT_HANDLER_RAND7_1
#define HT_HANDLER_RAND7_1 b .+28;\
pdist %f4, %f4, %f20;\
nop; nop ; nop; nop; illtrap
#endif
#ifndef HT_HANDLER_RAND4_2
#define HT_HANDLER_RAND4_2 rdpr %tstate, %l2;\
b .+12;\
wrpr %l2, 0x800, %tstate;\
nop;
#endif
#ifndef HT_HANDLER_RAND7_2
#define HT_HANDLER_RAND7_2 b .+8 ;\
rdhpr %hpstate, %l2;\
b .+8 ;\
rdhpr %htstate, %l3;\
b .+12 ;\
wrhpr %l3, %r0, %htstate; nop
#endif
#ifndef HT_HANDLER_RAND4_3
#define HT_HANDLER_RAND4_3 stxa %l4, [%r31]ASI_AS_IF_USER_PRIMARY;\
mov 0x80, %l3;\
stxa %l3, [%l3]0x5f ;\
b .+8 ;\
ldxa [%r31]ASI_AS_IF_USER_PRIMARY, %l4;
#endif
#ifndef HT_HANDLER_RAND7_3
#define HT_HANDLER_RAND7_3 b .+8 ;\
rdpr %tnpc, %l2;\
and %l2, 0xfc0, %l2;\
add %i7, %l2, %l2;\
stda %f16,[%i7]ASI_BLOCK_AS_IF_USER_PRIMARY ;\
b .+8 ;\
stda %f0,[%i7]ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE ;
#endif
#ifndef HT_HANDLER_RAND4_4
#define HT_HANDLER_RAND4_4 ldda [%i7]ASI_BLOCK_PRIMARY_LITTLE, %f0;\
b .+12 ;\
stxa %l3, [%g0]ASI_LSU_CONTROL; nop
#endif
#ifndef HT_HANDLER_RAND7_4
#define HT_HANDLER_RAND7_4 rdpr %tnpc, %l3;\
and %l3, 0xff, %l3;\
sllx %l3, 26, %l3;\
ldxa [%g0]0x45, %l4;\
or %l3, %l4, %l3 ;\
stxa %l3, [%g0]0x45 ;\
nop;
#endif
#ifndef HT_HANDLER_RAND4_5
#define HT_HANDLER_RAND4_5 ldda [%r31]ASI_NUCLEUS_QUAD_LDD, %f48;\
sdiv %l4, %l5, %l6;\
sdiv %l3, %l6, %l7;\
stda %f32, [%r31]ASI_BLOCK_PRIMARY_LITTLE;
#endif
#ifndef HT_HANDLER_RAND7_5
#define HT_HANDLER_RAND7_5 save %i7, %g0, %i7;\
rdpr %tnpc, %l2;\
wrpr %l2, %tpc;\
add %l2, 4, %l2;\
wrpr %l2, %tnpc;\
restore %i7, %g0, %i7;\
retry;
#endif
#ifndef HT_HANDLER_RAND4_6
#define HT_HANDLER_RAND4_6 ld [%r31], %l2;\
rd %fprs, %l2; \
wr %l2, 0x4, %fprs ;\
stda %f0,[%i7]ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE;
#endif
#ifndef HT_HANDLER_RAND7_6
#define HT_HANDLER_RAND7_6 rdhpr %htstate, %o4;\
rdpr %tnpc, %l2;\
wrpr %l2, %tpc;\
add %l2, 4, %l2;\
wrpr %l2, %tnpc;\
wrhpr %o4, %r0, %htstate;\
retry;
#endif
!!!!!!!!!!!!!!!!!!!!!!!!!
!! Disable trap checking
#define NO_TRAPCHECK
! Enable Traps
#define ENABLE_T1_Privileged_Opcode_0x11
#define ENABLE_T1_Fp_Disabled_0x20
#define ENABLE_HT0_Watchdog_Reset_0x02
#define FILL_TRAP_RETRY
#define SPILL_TRAP_RETRY
#define CLEAN_WIN_RETRY
#define My_RED_Mode_Other_Reset
#define My_RED_Mode_Other_Reset \
ba red_other_ext;\
nop;retry;nop;nop;nop;nop;nop
#define H_HT0_Software_Initiated_Reset_0x04
#define SUN_H_HT0_Software_Initiated_Reset_0x04 \
setx Software_Reset_Handler, %g1, %g2 ;\
jmp %g2 ;\
nop
#define H_T1_Clean_Window_0x24
#define SUN_H_T1_Clean_Window_0x24 \
rdpr %cleanwin, %l1;\
add %l1,1,%l1;\
wrpr %l1, %g0, %cleanwin;\
retry; nop; nop; nop; nop
#define H_T1_Clean_Window_0x25
#define SUN_H_T1_Clean_Window_0x25 \
rdpr %cleanwin, %l1;\
add %l1,1,%l1;\
wrpr %l1, %g0, %cleanwin;\
retry; nop; nop; nop; nop
#define H_T1_Clean_Window_0x26
#define SUN_H_T1_Clean_Window_0x26 \
rdpr %cleanwin, %l1;\
add %l1,1,%l1;\
wrpr %l1, %g0, %cleanwin;\
retry; nop; nop; nop; nop
#define H_T1_Clean_Window_0x27
#define SUN_H_T1_Clean_Window_0x27 \
rdpr %cleanwin, %l1;\
add %l1,1,%l1;\
wrpr %l1, %g0, %cleanwin;\
retry; nop; nop; nop; nop
#define H_HT0_Tag_Overflow
#define My_HT0_Tag_Overflow \
HT_HANDLER_RAND7_1 ;\
done
#define H_T0_Tag_Overflow
#define My_T0_Tag_Overflow \
T_HANDLER_RAND7_2 ;\
done
#define H_T1_Tag_Overflow_0x23
#define SUN_H_T1_Tag_Overflow_0x23 \
T_HANDLER_RAND7_3 ;\
done
#define H_T0_Window_Spill_0_Normal_Trap
#define SUN_H_T0_Window_Spill_0_Normal_Trap saved; retry; nop;nop;nop;nop;nop;nop;
#define H_T0_Window_Spill_1_Normal_Trap
#define SUN_H_T0_Window_Spill_1_Normal_Trap saved; retry; nop;nop;nop;nop;nop;nop;
#define H_T0_Window_Spill_2_Normal_Trap
#define SUN_H_T0_Window_Spill_2_Normal_Trap saved; retry; nop;nop;nop;nop;nop;nop;
#define H_T0_Window_Spill_3_Normal_Trap
#define SUN_H_T0_Window_Spill_3_Normal_Trap saved; retry; nop;nop;nop;nop;nop;nop;
#define H_T0_Window_Spill_4_Normal_Trap
#define SUN_H_T0_Window_Spill_4_Normal_Trap saved; retry; nop;nop;nop;nop;nop;nop;
#define H_T0_Window_Spill_5_Normal_Trap
#define SUN_H_T0_Window_Spill_5_Normal_Trap saved; retry; nop;nop;nop;nop;nop;nop;
#define H_T0_Window_Spill_6_Normal_Trap
#define SUN_H_T0_Window_Spill_6_Normal_Trap saved; retry; nop;nop;nop;nop;nop;nop;
#define H_T0_Window_Spill_7_Normal_Trap
#define SUN_H_T0_Window_Spill_7_Normal_Trap saved; retry; nop;nop;nop;nop;nop;nop;
#define H_T0_Window_Spill_0_Other_Trap
#define SUN_H_T0_Window_Spill_0_Other_Trap saved; retry; nop;nop;nop;nop;nop;nop;
#define H_T0_Window_Spill_1_Other_Trap
#define SUN_H_T0_Window_Spill_1_Other_Trap saved; retry; nop;nop;nop;nop;nop;nop;
#define H_T0_Window_Spill_2_Other_Trap
#define SUN_H_T0_Window_Spill_2_Other_Trap saved; retry; nop;nop;nop;nop;nop;nop;
#define H_T0_Window_Spill_3_Other_Trap
#define SUN_H_T0_Window_Spill_3_Other_Trap saved; retry; nop;nop;nop;nop;nop;nop;
#define H_T0_Window_Spill_4_Other_Trap
#define SUN_H_T0_Window_Spill_4_Other_Trap saved; retry; nop;nop;nop;nop;nop;nop;
#define H_T0_Window_Spill_5_Other_Trap
#define SUN_H_T0_Window_Spill_5_Other_Trap saved; retry; nop;nop;nop;nop;nop;nop;
#define H_T0_Window_Spill_6_Other_Trap
#define SUN_H_T0_Window_Spill_6_Other_Trap saved; retry; nop;nop;nop;nop;nop;nop;
#define H_T0_Window_Spill_7_Other_Trap
#define SUN_H_T0_Window_Spill_7_Other_Trap saved; retry; nop;nop;nop;nop;nop;nop;
#define H_T0_Window_Fill_0_Normal_Trap
#define SUN_H_T0_Window_Fill_0_Normal_Trap restored; retry; nop;nop;nop;nop;nop;nop;
#define H_T0_Window_Fill_1_Normal_Trap
#define SUN_H_T0_Window_Fill_1_Normal_Trap restored; retry; nop;nop;nop;nop;nop;nop;
#define H_T0_Window_Fill_2_Normal_Trap
#define SUN_H_T0_Window_Fill_2_Normal_Trap restored; retry; nop;nop;nop;nop;nop;nop;
#define H_T0_Window_Fill_3_Normal_Trap
#define SUN_H_T0_Window_Fill_3_Normal_Trap restored; retry; nop;nop;nop;nop;nop;nop;
#define H_T0_Window_Fill_4_Normal_Trap
#define SUN_H_T0_Window_Fill_4_Normal_Trap restored; retry; nop;nop;nop;nop;nop;nop;
#define H_T0_Window_Fill_5_Normal_Trap
#define SUN_H_T0_Window_Fill_5_Normal_Trap restored; retry; nop;nop;nop;nop;nop;nop;
#define H_T0_Window_Fill_6_Normal_Trap
#define SUN_H_T0_Window_Fill_6_Normal_Trap restored; retry; nop;nop;nop;nop;nop;nop;
#define H_T0_Window_Fill_7_Normal_Trap
#define SUN_H_T0_Window_Fill_7_Normal_Trap restored; retry; nop;nop;nop;nop;nop;nop;
#define H_T0_Window_Fill_0_Other_Trap
#define SUN_H_T0_Window_Fill_0_Other_Trap restored; retry; nop;nop;nop;nop;nop;nop;
#define H_T0_Window_Fill_1_Other_Trap
#define SUN_H_T0_Window_Fill_1_Other_Trap restored; retry; nop;nop;nop;nop;nop;nop;
#define H_T0_Window_Fill_2_Other_Trap
#define SUN_H_T0_Window_Fill_2_Other_Trap restored; retry; nop;nop;nop;nop;nop;nop;
#define H_T0_Window_Fill_3_Other_Trap
#define SUN_H_T0_Window_Fill_3_Other_Trap restored; retry; nop;nop;nop;nop;nop;nop;
#define H_T0_Window_Fill_4_Other_Trap
#define SUN_H_T0_Window_Fill_4_Other_Trap restored; retry; nop;nop;nop;nop;nop;nop;
#define H_T0_Window_Fill_5_Other_Trap
#define SUN_H_T0_Window_Fill_5_Other_Trap restored; retry; nop;nop;nop;nop;nop;nop;
#define H_T0_Window_Fill_6_Other_Trap
#define SUN_H_T0_Window_Fill_6_Other_Trap restored; retry; nop;nop;nop;nop;nop;nop;
#define H_T0_Window_Fill_7_Other_Trap
#define SUN_H_T0_Window_Fill_7_Other_Trap restored; retry; nop;nop;nop;nop;nop;nop;
#define H_T1_Window_Spill_0_Normal_Trap
#define SUN_H_T1_Window_Spill_0_Normal_Trap saved; retry; nop;nop;nop;nop;nop;nop;
#define H_T1_Window_Spill_1_Normal_Trap
#define SUN_H_T1_Window_Spill_1_Normal_Trap saved; retry; nop;nop;nop;nop;nop;nop;
#define H_T1_Window_Spill_2_Normal_Trap
#define SUN_H_T1_Window_Spill_2_Normal_Trap saved; retry; nop;nop;nop;nop;nop;nop;
#define H_T1_Window_Spill_3_Normal_Trap
#define SUN_H_T1_Window_Spill_3_Normal_Trap saved; retry; nop;nop;nop;nop;nop;nop;
#define H_T1_Window_Spill_4_Normal_Trap
#define SUN_H_T1_Window_Spill_4_Normal_Trap saved; retry; nop;nop;nop;nop;nop;nop;
#define H_T1_Window_Spill_5_Normal_Trap
#define SUN_H_T1_Window_Spill_5_Normal_Trap saved; retry; nop;nop;nop;nop;nop;nop;
#define H_T1_Window_Spill_6_Normal_Trap
#define SUN_H_T1_Window_Spill_6_Normal_Trap saved; retry; nop;nop;nop;nop;nop;nop;
#define H_T1_Window_Spill_7_Normal_Trap
#define SUN_H_T1_Window_Spill_7_Normal_Trap saved; retry; nop;nop;nop;nop;nop;nop;
#define H_T1_Window_Spill_0_Other_Trap
#define SUN_H_T1_Window_Spill_0_Other_Trap saved; retry; nop;nop;nop;nop;nop;nop;
#define H_T1_Window_Spill_1_Other_Trap
#define SUN_H_T1_Window_Spill_1_Other_Trap saved; retry; nop;nop;nop;nop;nop;nop;
#define H_T1_Window_Spill_2_Other_Trap
#define SUN_H_T1_Window_Spill_2_Other_Trap saved; retry; nop;nop;nop;nop;nop;nop;
#define H_T1_Window_Spill_3_Other_Trap
#define SUN_H_T1_Window_Spill_3_Other_Trap saved; retry; nop;nop;nop;nop;nop;nop;
#define H_T1_Window_Spill_4_Other_Trap
#define SUN_H_T1_Window_Spill_4_Other_Trap saved; retry; nop;nop;nop;nop;nop;nop;
#define H_T1_Window_Spill_5_Other_Trap
#define SUN_H_T1_Window_Spill_5_Other_Trap saved; retry; nop;nop;nop;nop;nop;nop;
#define H_T1_Window_Spill_6_Other_Trap
#define SUN_H_T1_Window_Spill_6_Other_Trap saved; retry; nop;nop;nop;nop;nop;nop;
#define H_T1_Window_Spill_7_Other_Trap
#define SUN_H_T1_Window_Spill_7_Other_Trap saved; retry; nop;nop;nop;nop;nop;nop;
#define H_T1_Window_Fill_0_Normal_Trap
#define SUN_H_T1_Window_Fill_0_Normal_Trap restored; retry; nop;nop;nop;nop;nop;nop;
#define H_T1_Window_Fill_1_Normal_Trap
#define SUN_H_T1_Window_Fill_1_Normal_Trap restored; retry; nop;nop;nop;nop;nop;nop;
#define H_T1_Window_Fill_2_Normal_Trap
#define SUN_H_T1_Window_Fill_2_Normal_Trap restored; retry; nop;nop;nop;nop;nop;nop;
#define H_T1_Window_Fill_3_Normal_Trap
#define SUN_H_T1_Window_Fill_3_Normal_Trap restored; retry; nop;nop;nop;nop;nop;nop;
#define H_T1_Window_Fill_4_Normal_Trap
#define SUN_H_T1_Window_Fill_4_Normal_Trap restored; retry; nop;nop;nop;nop;nop;nop;
#define H_T1_Window_Fill_5_Normal_Trap
#define SUN_H_T1_Window_Fill_5_Normal_Trap restored; retry; nop;nop;nop;nop;nop;nop;
#define H_T1_Window_Fill_6_Normal_Trap
#define SUN_H_T1_Window_Fill_6_Normal_Trap restored; retry; nop;nop;nop;nop;nop;nop;
#define H_T1_Window_Fill_7_Normal_Trap
#define SUN_H_T1_Window_Fill_7_Normal_Trap restored; retry; nop;nop;nop;nop;nop;nop;
#define H_T1_Window_Fill_0_Other_Trap
#define SUN_H_T1_Window_Fill_0_Other_Trap restored; retry; nop;nop;nop;nop;nop;nop;
#define H_T1_Window_Fill_1_Other_Trap
#define SUN_H_T1_Window_Fill_1_Other_Trap restored; retry; nop;nop;nop;nop;nop;nop;
#define H_T1_Window_Fill_2_Other_Trap
#define SUN_H_T1_Window_Fill_2_Other_Trap restored; retry; nop;nop;nop;nop;nop;nop;
#define H_T1_Window_Fill_3_Other_Trap
#define SUN_H_T1_Window_Fill_3_Other_Trap restored; retry; nop;nop;nop;nop;nop;nop;
#define H_T1_Window_Fill_4_Other_Trap
#define SUN_H_T1_Window_Fill_4_Other_Trap restored; retry; nop;nop;nop;nop;nop;nop;
#define H_T1_Window_Fill_5_Other_Trap
#define SUN_H_T1_Window_Fill_5_Other_Trap restored; retry; nop;nop;nop;nop;nop;nop;
#define H_T1_Window_Fill_6_Other_Trap
#define SUN_H_T1_Window_Fill_6_Other_Trap restored; retry; nop;nop;nop;nop;nop;nop;
#define H_T1_Window_Fill_7_Other_Trap
#define SUN_H_T1_Window_Fill_7_Other_Trap restored; retry; nop;nop;nop;nop;nop;nop;
#define H_T0_Trap_Instruction_0
#define My_T0_Trap_Instruction_0 \
T_HANDLER_RAND7_5 ;\
done;
#define H_T0_Trap_Instruction_1
#define My_T0_Trap_Instruction_1 \
T_HANDLER_RAND7_6 ;\
done;
#define H_T0_Trap_Instruction_2
#define My_T0_Trap_Instruction_2 \
inc %o3;\
umul %o3, 2, %o4;\
ba 1f; \
save %i7, %g0, %i7; \
2: done; \
nop; \
1: ba 2b; \
restore %i7, %g0, %i7
#define H_T0_Trap_Instruction_3
#define My_T0_Trap_Instruction_3 \
save %i7, %g0, %i7 ;\
T_HANDLER_RAND4_5;\
stw %o4, [%i7];\
restore %i7, %g0, %i7 ;\
done
#define H_T0_Trap_Instruction_4
#define My_T0_Trap_Instruction_4 \
T_HANDLER_RAND7_6 ;\
done;
#define H_T0_Trap_Instruction_5
#define My_T0_Trap_Instruction_5 \
T_HANDLER_RAND4_5;\
done;
#define H_T1_Trap_Instruction_0
#define My_T1_Trap_Instruction_0 \
inc %o4;\
umul %o4, 2, %o5;\
ba 3f; \
save %i7, %g0, %i7; \
4: done; \
nop; \
3: ba 4b; \
restore %i7, %g0, %i7
#define H_T1_Trap_Instruction_1
#define My_T1_Trap_Instruction_1 \
T_HANDLER_RAND7_3;\
done
#define H_T1_Trap_Instruction_2
#define My_T1_Trap_Instruction_2 \
inc %o3;\
umul %o3, 2, %o4;\
ba 5f; \
save %i7, %g0, %i7; \
6: done; \
nop; \
5: ba 6b; \
restore %i7, %g0, %i7
#define H_T1_Trap_Instruction_3
#define My_T1_Trap_Instruction_3 \
T_HANDLER_RAND4_1;\
done;
#define H_T1_Trap_Instruction_4
#define My_T1_Trap_Instruction_4 \
T_HANDLER_RAND7_1;\
done;
#define H_T1_Trap_Instruction_5
#define My_T1_Trap_Instruction_5 \
T_HANDLER_RAND7_2;\
done
#define H_HT0_Trap_Instruction_0
#define My_HT0_Trap_Instruction_0 \
HT_HANDLER_RAND4_1 ;\
done;
#define H_HT0_Trap_Instruction_1
#define My_HT0_Trap_Instruction_1 \
HT_HANDLER_RAND4_3 ;\
done
#define H_HT0_Trap_Instruction_2
#define My_HT0_Trap_Instruction_2 \
HT_HANDLER_RAND7_5 ;\
done;
#define H_HT0_Trap_Instruction_3
#define My_HT0_Trap_Instruction_3 \
HT_HANDLER_RAND4_5 ;\
done
#define H_HT0_Trap_Instruction_4
#define My_HT0_Trap_Instruction_4 \
HT_HANDLER_RAND7_4 ;\
done
#define H_HT0_Trap_Instruction_5
#define My_HT0_Trap_Instruction_5 \
ba htrap_5_ext;\
nop; retry;\
nop; nop; nop; nop; nop
#define H_HT0_Mem_Address_Not_Aligned_0x34
#define My_HT0_Mem_Address_Not_Aligned_0x34 \
HT_HANDLER_RAND4_2 ;\
done ;
#define H_HT0_Illegal_instruction_0x10
#define My_HT0_Illegal_instruction_0x10 \
done;
#define H_HT0_DAE_so_page_0x30
#define My_HT0_DAE_so_page_0x30 \
done;
#define H_HT0_DAE_invalid_asi_0x14
#define SUN_H_HT0_DAE_invalid_asi_0x14 \
done
#define H_HT0_DAE_privilege_violation_0x15
#define SUN_H_HT0_DAE_privilege_violation_0x15 \
done;
#define H_HT0_Privileged_Action_0x37
#define My_HT0_Privileged_Action_0x37 \
done; \
nop; nop
#define H_HT0_Lddf_Mem_Address_Not_Aligned_0x35
#define My_HT0_Lddf_Mem_Address_Not_Aligned_0x35 \
HT_HANDLER_RAND4_3 ;\
done
#define H_HT0_Stdf_Mem_Address_Not_Aligned_0x36
#define My_HT0_Stdf_Mem_Address_Not_Aligned_0x36 \
HT_HANDLER_RAND7_1;\
done
#define H_HT0_Fp_exception_ieee_754_0x21
#define My_HT0_Fp_exception_ieee_754_0x21 \
HT_HANDLER_RAND4_2 ;\
done
#define H_HT0_Fp_exception_other_0x22
#define My_HT0_Fp_exception_other_0x22 \
HT_HANDLER_RAND7_2 ;\
done
#define H_HT0_Division_By_Zero
#define My_HT0_Division_By_Zero \
HT_HANDLER_RAND4_6;\
done
#define H_T0_Division_By_Zero
#define My_T0_Division_By_Zero \
T_HANDLER_RAND4_3;\
done
#define H_T1_Division_By_Zero_0x28
#define My_H_T1_Division_By_Zero_0x28 \
T_HANDLER_RAND4_3;\
done
#define H_T0_Division_By_Zero
#define My_T0_Division_By_Zero\
T_HANDLER_RAND4_4 ;\
done
#define H_T0_Fp_exception_ieee_754_0x21
#define My_T0_Fp_exception_ieee_754_0x21 \
T_HANDLER_RAND4_3 ;\
done
#define H_T1_Fp_Exception_Ieee_754_0x21
#define My_H_T1_Fp_Exception_Ieee_754_0x21 \
T_HANDLER_RAND4_4 ;\
done
#define H_T1_Fp_Exception_Other_0x22
#define My_H_T1_Fp_Exception_Other_0x22 \
T_HANDLER_RAND4_5 ;\
done
#define H_T1_Privileged_Opcode_0x11
#define SUN_H_T1_Privileged_Opcode_0x11 \
T_HANDLER_RAND4_6 ;\
done
#define H_HT0_Privileged_opcode_0x11
#define My_HT0_Privileged_opcode_0x11 \
HT_HANDLER_RAND4_1;\
done;
#define H_HT0_Fp_disabled_0x20
#define My_HT0_Fp_disabled_0x20 \
mov 0x4, %l2 ;\
wr %l2, 0x0, %fprs ;\
sllx %l2, 10, %l3; \
rdpr %tstate, %l2;\
or %l2, %l3, %l2 ;\
stw %l2, [%i7];\
wrpr %l2, 0x0, %tstate;\
retry;
#define H_T0_Fp_disabled_0x20
#define My_T0_Fp_disabled_0x20 \
mov 0x4, %l2 ;\
wr %l2, 0x0, %fprs ;\
sllx %l2, 10, %l3; \
rdpr %tstate, %l2;\
or %l2, %l3, %l2 ;\
wrpr %l2, 0x0, %tstate;\
retry; nop
#define H_T1_Fp_Disabled_0x20
#define My_H_T1_Fp_Disabled_0x20 \
mov 0x4, %l2 ;\
wr %l2, 0x0, %fprs ;\
sllx %l2, 10, %l3; \
rdpr %tstate, %l2;\
or %l2, %l3, %l2 ;\
wrpr %l2, 0x0, %tstate;\
stw %l2, [%i7];\
retry
#define H_HT0_Watchdog_Reset_0x02
#define My_HT0_Watchdog_Reset_0x02 \
ba wdog_2_ext;\
nop;retry;nop;nop;nop;nop;nop
#define H_T0_Privileged_opcode_0x11
#define My_T0_Privileged_opcode_0x11 \
T_HANDLER_RAND4_4;\
done
#define H_T1_Fp_exception_other_0x22
#define My_T1_Fp_exception_other_0x22 \
T_HANDLER_RAND7_3 ;\
done;
#define H_T0_Fp_exception_other_0x22
#define My_T0_Fp_exception_other_0x22 \
T_HANDLER_RAND7_4;\
done
#define H_HT0_Trap_Level_Zero_0x5f
#define My_HT0_Trap_Level_Zero_0x5f \
not %g0, %r13; \
rdhpr %hpstate, %l3;\
jmp %r13;\
rdhpr %htstate, %l3;\
and %l3, 0xfe, %l3;\
wrhpr %l3, 0, %htstate;\
stw %r13, [%i7];\
retry
#define My_Watchdog_Reset
#define My_Watchdog_Reset \
ba wdog_red_ext;\
nop;retry;nop;nop;nop;nop;nop
#define H_HT0_Control_Transfer_Instr_0x74
#define My_H_HT0_Control_Transfer_Instr_0x74 \
rdpr %tstate, %l3;\
mov 1, %l4;\
sllx %l4, 20, %l4;\
wrpr %l3, %l4, %tstate ;\
retry;nop;
#define H_T0_Control_Transfer_Instr_0x74
#define My_H_T0_Control_Transfer_Instr_0x74 \
rdpr %tstate, %l3;\
mov 1, %l4;\
sllx %l4, 20, %l4;\
wrpr %l3, %l4, %tstate ;\
retry;nop;
#define H_T1_Control_Transfer_Instr_0x74
#define My_H_T1_Control_Transfer_Instr_0x74 \
rdpr %tstate, %l3;\
mov 1, %l4;\
sllx %l4, 20, %l4;\
wrpr %l3, %l4, %tstate ;\
retry;nop;
#define H_HT0_data_access_protection_0x6c
#define SUN_H_HT0_data_access_protection_0x6c ba daccess_prot_handler; nop
#define H_HT0_PA_Watchpoint_0x61
#define My_H_HT0_PA_Watchpoint_0x61 \
HT_HANDLER_RAND7_4;\
done
#ifndef H_HT0_Data_access_error_0x32
#define H_HT0_Data_access_error_0x32
#define SUN_H_HT0_Data_access_error_0x32 \
done;nop
#endif
#define H_T0_VA_Watchpoint_0x62
#define My_T0_VA_Watchpoint_0x62 \
T_HANDLER_RAND7_5;\
done
#define H_T1_VA_Watchpoint_0x62
#define SUN_H_T1_VA_Watchpoint_0x62 \
T_HANDLER_RAND7_3;\
done
#define H_HT0_VA_Watchpoint_0x62
#define My_H_HT0_VA_Watchpoint_0x62 \
HT_HANDLER_RAND7_5;\
done
#define H_HT0_Instruction_VA_Watchpoint_0x75
#define SUN_H_HT0_Instruction_VA_Watchpoint_0x75 \
done;
#define H_HT0_Instruction_Breakpoint_0x76
#define SUN_H_HT0_Instruction_Breakpoint_0x76 \
rdhpr %htstate, %g1;\
wrhpr %g1, 0x400, %htstate;\
retry;nop
#define H_HT0_Instruction_address_range_0x0d
#define SUN_H_HT0_Instruction_address_range_0x0d \
HT_HANDLER_RAND4_1;\
done;
#define H_HT0_Instruction_real_range_0x0e
#define SUN_H_HT0_Instruction_real_range_0x0e \
HT_HANDLER_RAND4_1;\
done;
#define H_HT0_mem_real_range_0x2d
#define SUN_H_HT0_mem_real_range_0x2d \
HT_HANDLER_RAND4_2;\
done;
#define H_HT0_mem_address_range_0x2e
#define SUN_H_HT0_mem_address_range_0x2e \
HT_HANDLER_RAND4_3;\
done;
#define H_HT0_DAE_nc_page_0x16
#define SUN_H_HT0_DAE_nc_page_0x16 \
done;
#define H_HT0_DAE_nfo_page_0x17
#define SUN_H_HT0_DAE_nfo_page_0x17 \
done;
#define H_HT0_IAE_unauth_access_0x0b
#define SUN_H_HT0_IAE_unauth_access_0x0b \
HT_HANDLER_RAND7_3;\
done;
#define H_HT0_IAE_nfo_page_0x0c
#define SUN_H_HT0_IAE_nfo_page_0x0c \
HT_HANDLER_RAND7_6;\
done;
#define H_HT0_Reserved_0x3b
#define SUN_H_HT0_Reserved_0x3b \
mov 0x80, %l3;\
stxa %l3, [%l3]0x5f ;\
stxa %l3, [%l3]0x57 ;\
done;
#define H_HT0_IAE_privilege_violation_0x08
#define My_HT0_IAE_privilege_violation_0x08 \
HT_HANDLER_RAND7_2;\
done;
#ifndef H_HT0_Instruction_Access_MMU_Error_0x71
#define H_HT0_Instruction_Access_MMU_Error_0x71
#define SUN_H_HT0_Instruction_Access_MMU_Error_0x71 \
mov 0x80, %l3;\
stxa %l3, [%l3]0x5f ;\
stxa %l3, [%l3]0x57 ;\
retry;
#endif
#ifndef H_HT0_Data_Access_MMU_Error_0x72
#define H_HT0_Data_Access_MMU_Error_0x72
#define SUN_H_HT0_Data_Access_MMU_Error_0x72 \
mov 0x80, %l3;\
stxa %l3, [%l3]0x5f ;\
stxa %l3, [%l3]0x57 ;\
retry;
#endif
!!!!!!!!!!!!!!!!!!!!!! END of all handlers !!!!!!!!!!!!!!!!!!!
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
!!!!!!!!!!!!!!!! START of Interrupt Handlers !!!!!!!!!!!!!!!!!
#ifndef INT_HANDLER_RAND4_1
#define INT_HANDLER_RAND4_1 retry; nop; nop; nop
#endif
#ifndef INT_HANDLER_RAND7_1
#define INT_HANDLER_RAND7_1 retry; nop; nop; nop ; nop; nop; nop
#endif
#ifndef INT_HANDLER_RAND4_2
#define INT_HANDLER_RAND4_2 retry; nop; nop; nop
#endif
#ifndef INT_HANDLER_RAND7_2
#define INT_HANDLER_RAND7_2 retry; nop; nop; nop ; nop; nop; nop
#endif
#ifndef INT_HANDLER_RAND4_3
#define INT_HANDLER_RAND4_3 retry; nop; nop; nop
#endif
#ifndef INT_HANDLER_RAND7_3
#define INT_HANDLER_RAND7_3 retry; nop; nop; nop ; nop; nop; nop
#endif
#define H_HT0_Externally_Initiated_Reset_0x03
#define SUN_H_HT0_Externally_Initiated_Reset_0x03 \
ldxa [%g0] ASI_LSU_CTL_REG, %g1; \
set cregs_lsu_ctl_reg_r64, %g1; \
stxa %g1, [%g0] ASI_LSU_CTL_REG; \
retry;nop
#define My_External_Reset \
ldxa [%g0] ASI_LSU_CTL_REG, %l5; \
set cregs_lsu_ctl_reg_r64, %l5; \
stxa %l5, [%g0] ASI_LSU_CTL_REG; \
retry;nop
!!!!! SPU Interrupt Handlers
#define H_HT0_Control_Word_Queue_Interrupt_0x3c
#define My_HT0_Control_Word_Queue_Interrupt_0x3c \
INT_HANDLER_RAND7_1 ;\
retry ;
#define H_HT0_Modular_Arithmetic_Interrupt_0x3d
#define My_H_HT0_Modular_Arithmetic_Interrupt_0x3d \
INT_HANDLER_RAND7_2 ;\
retry ;
!!!!! HW interrupt handlers
#define H_HT0_Interrupt_0x60
#define My_HT0_Interrupt_0x60 \
ldxa [%g0] ASI_SWVR_INTR_RECEIVE, %g5 ;\
ldxa [%g0] ASI_SWVR_INTR_R, %g4 ;\
ldxa [%g0] ASI_SWVR_INTR_RECEIVE, %g3 ;\
INT_HANDLER_RAND4_1 ;\
retry;
!!!!! Queue interrupt handler
#define H_T0_Cpu_Mondo_Trap_0x7c
#define My_T0_Cpu_Mondo_Trap_0x7c \
mov 0x3c8, %g3; \
ldxa [%g3] 0x25, %g5; \
mov 0x3c0, %g3; \
stxa %g5, [%g3] 0x25; \
retry; \
nop; \
nop; \
nop
#define H_T0_Dev_Mondo_Trap_0x7d
#define My_T0_Dev_Mondo_Trap_0x7d \
mov 0x3d8, %g3; \
ldxa [%g3] 0x25, %g5; \
mov 0x3d0, %g3; \
stxa %g5, [%g3] 0x25; \
retry; \
nop; \
nop; \
nop
#define H_T0_Resumable_Error_0x7e
#define My_T0_Resumable_Error_0x7e \
mov 0x3e8, %g3; \
ldxa [%g3] 0x25, %g5; \
mov 0x3e0, %g3; \
stxa %g5, [%g3] 0x25; \
retry; \
nop; \
nop; \
nop
#define H_T1_Cpu_Mondo_Trap_0x7c
#define My_T1_Cpu_Mondo_Trap_0x7c \
mov 0x3c8, %g3; \
ldxa [%g3] 0x25, %g5; \
mov 0x3c0, %g3; \
stxa %g5, [%g3] 0x25; \
retry; \
nop; \
nop; \
nop
#define H_T1_Dev_Mondo_Trap_0x7d
#define My_T1_Dev_Mondo_Trap_0x7d \
mov 0x3d8, %g3; \
ldxa [%g3] 0x25, %g5; \
mov 0x3d0, %g3; \
stxa %g5, [%g3] 0x25; \
retry; \
nop; \
nop; \
nop
#define H_T1_Resumable_Error_0x7e
#define My_T1_Resumable_Error_0x7e \
mov 0x3e8, %g3; \
ldxa [%g3] 0x25, %g5; \
mov 0x3e0, %g3; \
stxa %g5, [%g3] 0x25; \
retry; \
nop; \
nop; \
nop
#define H_HT0_Reserved_0x7c
#define SUN_H_HT0_Reserved_0x7c \
mov 0x3c8, %g3; \
ldxa [%g3] 0x25, %g5; \
mov 0x3c0, %g3; \
stxa %g5, [%g3] 0x25; \
retry; \
nop; \
nop; \
nop
#define H_HT0_Reserved_0x7d
#define SUN_H_HT0_Reserved_0x7d \
mov 0x3d8, %g3; \
ldxa [%g3] 0x25, %g5; \
mov 0x3d0, %g3; \
stxa %g5, [%g3] 0x25; \
retry; \
nop; \
nop; \
nop
#define H_HT0_Reserved_0x7e
#define SUN_H_HT0_Reserved_0x7e \
mov 0x3e8, %g3; \
ldxa [%g3] 0x25, %g5; \
mov 0x3e0, %g3; \
stxa %g5, [%g3] 0x25; \
retry; \
nop; \
nop; \
nop
!!!!! Hstick-match trap handler
#define H_T0_Reserved_0x5e
#define My_T0_Reserved_0x5e \
rdhpr %hintp, %g3; \
wrhpr %g3, %g3, %hintp; \
retry; \
nop; \
nop; \
nop; \
nop; \
nop
#define H_HT0_Hstick_Match_0x5e
#define My_HT0_Hstick_Match_0x5e \
rdhpr %hintp, %g3; \
wrhpr %g3, %g3, %hintp; \
retry; \
nop; \
nop; \
nop; \
nop; \
nop
#define H_T0_Reserved_0x5e
#define My_T0_Reserved_0x5e \
rdhpr %hintp, %g3; \
wrhpr %g3, %g3, %hintp; \
retry; \
nop; \
nop; \
nop; \
nop; \
nop
#define H_T1_Reserved_0x5e
#define My_T1_Reserved_0x5e \
rdhpr %hintp, %g3; \
wrhpr %g3, %g3, %hintp; \
retry; \
nop; \
nop; \
nop; \
nop; \
nop
!!!!! SW interuupt handlers
#define H_T0_Interrupt_Level_14_0x4e
#define My_T0_Interrupt_Level_14_0x4e \
rd %softint, %g3; \
sethi %hi(0x14000), %g3; \
or %g3, 0x1, %g3; \
wr %g3, %g0, %clear_softint; \
rd %tick, %g3 ;\
retry; \
#define H_T0_Interrupt_Level_1_0x41
#define My_T0_Interrupt_Level_1_0x41 \
rd %softint, %g3; \
or %g0, 0x2, %g3; \
wr %g3, %g0, %clear_softint; \
retry; \
nop; \
nop; \
nop; \
nop
#define H_T0_Interrupt_Level_2_0x42
#define My_T0_Interrupt_Level_2_0x42 \
rd %softint, %g3; \
or %g0, 0x4, %g3; \
wr %g3, %g0, %clear_softint; \
retry; \
nop; \
nop; \
nop; \
nop
#define H_T0_Interrupt_Level_3_0x43
#define My_T0_Interrupt_Level_3_0x43 \
rd %softint, %g3; \
or %g0, 0x8, %g3; \
wr %g3, %g0, %clear_softint; \
retry; \
nop; \
nop; \
nop; \
nop
#define H_T0_Interrupt_Level_4_0x44
#define My_T0_Interrupt_Level_4_0x44 \
rd %softint, %g3; \
or %g0, 0x10, %g3; \
wr %g3, %g0, %clear_softint; \
retry; \
nop; \
nop; \
nop; \
nop
#define H_T0_Interrupt_Level_5_0x45
#define My_T0_Interrupt_Level_5_0x45 \
rd %softint, %g3; \
or %g0, 0x20, %g3; \
wr %g3, %g0, %clear_softint; \
retry; \
nop; \
nop; \
nop; \
nop
#define H_T0_Interrupt_Level_6_0x46
#define My_T0_Interrupt_Level_6_0x46 \
rd %softint, %g3; \
or %g0, 0x40, %g3; \
wr %g3, %g0, %clear_softint; \
retry; \
nop; \
nop; \
nop; \
nop
#define H_T0_Interrupt_Level_7_0x47
#define My_T0_Interrupt_Level_7_0x47 \
rd %softint, %g3; \
or %g0, 0x80, %g3; \
wr %g3, %g0, %clear_softint; \
retry; \
nop; \
nop; \
nop; \
nop
#define H_T0_Interrupt_Level_8_0x48
#define My_T0_Interrupt_Level_8_0x48 \
rd %softint, %g3; \
or %g0, 0x100, %g3; \
wr %g3, %g0, %clear_softint; \
retry; \
nop; \
nop; \
nop; \
nop
#define H_T0_Interrupt_Level_9_0x49
#define My_T0_Interrupt_Level_9_0x49 \
rd %softint, %g3; \
or %g0, 0x200, %g3; \
wr %g3, %g0, %clear_softint; \
retry; \
nop; \
nop; \
nop; \
nop
#define H_T0_Interrupt_Level_10_0x4a
#define My_T0_Interrupt_Level_10_0x4a \
rd %softint, %g3; \
or %g0, 0x400, %g3; \
wr %g3, %g0, %clear_softint; \
retry; \
nop; \
nop; \
nop; \
nop
#define H_T0_Interrupt_Level_11_0x4b
#define My_T0_Interrupt_Level_11_0x4b \
rd %softint, %g3; \
or %g0, 0x800, %g3; \
wr %g3, %g0, %clear_softint; \
retry; \
nop; \
nop; \
nop; \
nop
#define H_T0_Interrupt_Level_12_0x4c
#define My_T0_Interrupt_Level_12_0x4c \
rd %softint, %g3; \
sethi %hi(0x1000), %g3; \
wr %g3, %g0, %clear_softint; \
retry; \
nop; \
nop; \
nop; \
nop
#define H_T0_Interrupt_Level_13_0x4d
#define My_T0_Interrupt_Level_13_0x4d \
rd %softint, %g3; \
sethi %hi(0x2000), %g3; \
wr %g3, %g0, %clear_softint; \
retry; \
nop; \
nop; \
nop; \
nop
#define H_T0_Interrupt_Level_15_0x4f
#define My_T0_Interrupt_Level_15_0x4f \
sethi %hi(0x8000), %g3; \
wr %g3, %g0, %clear_softint; \
wr %g0, %g0, %pic;\
sethi %hi(0x80040000), %g2;\
rd %pcr, %g3;\
andn %g3, %g2, %g3;\
wr %g3, %g0, %pcr;\
retry;
#define H_T1_Interrupt_Level_14_0x4e
#define My_T1_Interrupt_Level_14_0x4e \
rd %softint, %g3; \
sethi %hi(0x14000), %g3; \
or %g3, 0x1, %g3; \
wr %g3, %g0, %clear_softint; \
rd %tick, %g3 ;\
retry; \
#define H_T1_Interrupt_Level_1_0x41
#define My_T1_Interrupt_Level_1_0x41 \
rd %softint, %g3; \
or %g0, 0x2, %g3; \
wr %g3, %g0, %clear_softint; \
retry; \
nop; \
nop; \
nop; \
nop
#define H_T1_Interrupt_Level_2_0x42
#define My_T1_Interrupt_Level_2_0x42 \
rd %softint, %g3; \
or %g0, 0x4, %g3; \
wr %g3, %g0, %clear_softint; \
retry; \
nop; \
nop; \
nop; \
nop
#define H_T1_Interrupt_Level_3_0x43
#define My_T1_Interrupt_Level_3_0x43 \
rd %softint, %g3; \
or %g0, 0x8, %g3; \
wr %g3, %g0, %clear_softint; \
retry; \
nop; \
nop; \
nop; \
nop
#define H_T1_Interrupt_Level_4_0x44
#define My_T1_Interrupt_Level_4_0x44 \
rd %softint, %g3; \
or %g0, 0x10, %g3; \
wr %g3, %g0, %clear_softint; \
retry; \
nop; \
nop; \
nop; \
nop
#define H_T1_Interrupt_Level_5_0x45
#define My_T1_Interrupt_Level_5_0x45 \
rd %softint, %g3; \
or %g0, 0x20, %g3; \
wr %g3, %g0, %clear_softint; \
retry; \
nop; \
nop; \
nop; \
nop
#define H_T1_Interrupt_Level_6_0x46
#define My_T1_Interrupt_Level_6_0x46 \
rd %softint, %g3; \
or %g0, 0x40, %g3; \
wr %g3, %g0, %clear_softint; \
retry; \
nop; \
nop; \
nop; \
nop
#define H_T1_Interrupt_Level_7_0x47
#define My_T1_Interrupt_Level_7_0x47 \
rd %softint, %g3; \
or %g0, 0x80, %g3; \
wr %g3, %g0, %clear_softint; \
retry; \
nop; \
nop; \
nop; \
nop
#define H_T1_Interrupt_Level_8_0x48
#define My_T1_Interrupt_Level_8_0x48 \
rd %softint, %g3; \
or %g0, 0x100, %g3; \
wr %g3, %g0, %clear_softint; \
retry; \
nop; \
nop; \
nop; \
nop
#define H_T1_Interrupt_Level_9_0x49
#define My_T1_Interrupt_Level_9_0x49 \
rd %softint, %g3; \
or %g0, 0x200, %g3; \
wr %g3, %g0, %clear_softint; \
retry; \
nop; \
nop; \
nop; \
nop
#define H_T1_Interrupt_Level_10_0x4a
#define My_T1_Interrupt_Level_10_0x4a \
rd %softint, %g3; \
or %g0, 0x400, %g3; \
wr %g3, %g0, %clear_softint; \
retry; \
nop; \
nop; \
nop; \
nop
#define H_T1_Interrupt_Level_11_0x4b
#define My_T1_Interrupt_Level_11_0x4b \
rd %softint, %g3; \
or %g0, 0x800, %g3; \
wr %g3, %g0, %clear_softint; \
retry; \
nop; \
nop; \
nop; \
nop
#define H_T1_Interrupt_Level_12_0x4c
#define My_T1_Interrupt_Level_12_0x4c \
rd %softint, %g3; \
sethi %hi(0x1000), %g3; \
wr %g3, %g0, %clear_softint; \
retry; \
nop; \
nop; \
nop; \
nop
#define H_T1_Interrupt_Level_13_0x4d
#define My_T1_Interrupt_Level_13_0x4d \
rd %softint, %g3; \
sethi %hi(0x2000), %g3; \
wr %g3, %g0, %clear_softint; \
retry; \
nop; \
nop; \
nop; \
nop
#define H_T1_Interrupt_Level_15_0x4f
#define My_T1_Interrupt_Level_15_0x4f \
sethi %hi(0x8000), %g3; \
wr %g3, %g0, %clear_softint; \
wr %g0, %g0, %pic;\
sethi %hi(0x80040000), %g2;\
rd %pcr, %g3;\
andn %g3, %g2, %g3;\
wr %g3, %g0, %pcr;\
retry;
#define H_HT0_Interrupt_Level_14_0x4e
#define My_HT0_Interrupt_Level_14_0x4e \
rd %softint, %g3; \
sethi %hi(0x14000), %g3; \
or %g3, 0x1, %g3; \
wr %g3, %g0, %clear_softint; \
rd %tick, %g3 ;\
sub %g3, 0x80, %g3;\
wrpr %g3, %g0, %tick;\
retry; \
#define H_HT0_Interrupt_Level_1_0x41
#define My_HT0_Interrupt_Level_1_0x41 \
rd %softint, %g3; \
or %g0, 0x2, %g3; \
wr %g3, %g0, %clear_softint; \
retry; \
nop; \
nop; \
nop; \
nop
#define H_HT0_Interrupt_Level_2_0x42
#define My_HT0_Interrupt_Level_2_0x42 \
rd %softint, %g3; \
or %g0, 0x4, %g3; \
wr %g3, %g0, %clear_softint; \
retry; \
nop; \
nop; \
nop; \
nop
#define H_HT0_Interrupt_Level_3_0x43
#define My_HT0_Interrupt_Level_3_0x43 \
rd %softint, %g3; \
or %g0, 0x8, %g3; \
wr %g3, %g0, %clear_softint; \
retry; \
nop; \
nop; \
nop; \
nop
#define H_HT0_Interrupt_Level_4_0x44
#define My_HT0_Interrupt_Level_4_0x44 \
rd %softint, %g3; \
or %g0, 0x10, %g3; \
wr %g3, %g0, %clear_softint; \
retry; \
nop; \
nop; \
nop; \
nop
#define H_HT0_Interrupt_Level_5_0x45
#define My_HT0_Interrupt_Level_5_0x45 \
rd %softint, %g3; \
or %g0, 0x20, %g3; \
wr %g3, %g0, %clear_softint; \
retry; \
nop; \
nop; \
nop; \
nop
#define H_HT0_Interrupt_Level_6_0x46
#define My_HT0_Interrupt_Level_6_0x46 \
rd %softint, %g3; \
or %g0, 0x40, %g3; \
wr %g3, %g0, %clear_softint; \
retry; \
nop; \
nop; \
nop; \
nop
#define H_HT0_Interrupt_Level_7_0x47
#define My_HT0_Interrupt_Level_7_0x47 \
rd %softint, %g3; \
or %g0, 0x80, %g3; \
wr %g3, %g0, %clear_softint; \
retry; \
nop; \
nop; \
nop; \
nop
#define H_HT0_Interrupt_Level_8_0x48
#define My_HT0_Interrupt_Level_8_0x48 \
rd %softint, %g3; \
or %g0, 0x100, %g3; \
wr %g3, %g0, %clear_softint; \
retry; \
nop; \
nop; \
nop; \
nop
#define H_HT0_Interrupt_Level_9_0x49
#define My_HT0_Interrupt_Level_9_0x49 \
rd %softint, %g3; \
or %g0, 0x200, %g3; \
wr %g3, %g0, %clear_softint; \
retry; \
nop; \
nop; \
nop; \
nop
#define H_HT0_Interrupt_Level_10_0x4a
#define My_HT0_Interrupt_Level_10_0x4a \
rd %softint, %g3; \
or %g0, 0x400, %g3; \
wr %g3, %g0, %clear_softint; \
retry; \
nop; \
nop; \
nop; \
nop
#define H_HT0_Interrupt_Level_11_0x4b
#define My_HT0_Interrupt_Level_11_0x4b \
rd %softint, %g3; \
or %g0, 0x800, %g3; \
wr %g3, %g0, %clear_softint; \
retry; \
nop; \
nop; \
nop; \
nop
#define H_HT0_Interrupt_Level_12_0x4c
#define My_HT0_Interrupt_Level_12_0x4c \
rd %softint, %g3; \
sethi %hi(0x1000), %g3; \
wr %g3, %g0, %clear_softint; \
retry; \
nop; \
nop; \
nop; \
nop
#define H_HT0_Interrupt_Level_13_0x4d
#define My_HT0_Interrupt_Level_13_0x4d \
rd %softint, %g3; \
sethi %hi(0x2000), %g3; \
wr %g3, %g0, %clear_softint; \
retry; \
nop; \
nop; \
nop; \
nop
#define H_HT0_Interrupt_Level_15_0x4f
#define My_HT0_Interrupt_Level_15_0x4f \
sethi %hi(0x8000), %g3; \
wr %g3, %g0, %clear_softint; \
wr %g0, %g0, %pic;\
sethi %hi(0x80040000), %g2;\
rd %pcr, %g3;\
andn %g3, %g2, %g3;\
wr %g3, %g0, %pcr;\
retry;
!!!!!!!!!!!!!!!!!!!!!! END of all handlers !!!!!!!!!!!!!!!!!!!
!# Steer towards main TBA on these errors ..
!# These are redefines ...
#undef My_RED_Mode_Other_Reset
#define My_RED_Mode_Other_Reset
#define My_RED_Mode_Other_Reset \
mov ZRED_Mode_Other_Reset ,%r1;\
jmp %g1; nop;retry;nop;nop;nop;nop
#undef SUN_H_HT0_IAE_unauth_access_0x0b
#define SUN_H_HT0_IAE_unauth_access_0x0b \
set resolve_bad_tte, %g3;\
jmp %g3;\
nop
#undef My_HT0_IAE_privilege_violation_0x08
#define My_HT0_IAE_privilege_violation_0x08 \
set resolve_bad_tte, %g3;\
jmp %g3;\
nop
#define H_HT0_Instruction_address_range_0x0d
#define SUN_H_HT0_Instruction_address_range_0x0d \
rdpr %tpc, %g1;\
rdpr %tnpc, %g2;\
stw %g1, [%i7];\
stw %g2, [%i7+4];\
jmpl %r27+8, %r27;\
fdivd %f0, %f4, %f4;\
nop;
#define H_HT0_Instruction_real_range_0x0e
#define SUN_H_HT0_Instruction_real_range_0x0e \
rdpr %tpc, %g1;\
rdpr %tnpc, %g2;\
stw %g1, [%i7];\
stw %g2, [%i7+4];\
jmpl %r27+8, %r27;\
fdivd %f0, %f4, %f4;\
nop;
#undef SUN_H_HT0_IAE_nfo_page_0x0c
#define SUN_H_HT0_IAE_nfo_page_0x0c \
set resolve_bad_tte, %g3;\
jmp %g3;\
nop
#define H_HT0_Instruction_Invalid_TSB_Entry_0x2a
#define SUN_H_HT0_Instruction_Invalid_TSB_Entry_0x2a \
set restore_range_regs, %g3;\
jmp %g3;\
nop
#define H_HT0_Data_Invalid_TSB_Entry_0x2b
#define SUN_H_HT0_Data_Invalid_TSB_Entry_0x2b \
set restore_range_regs, %g3;\
jmp %g3;\
nop
#define H_T1_Reserved_0x00
#define SUN_H_T1_Reserved_0x00 \
nop;\
jmpl %r27+8, %r0;\
nop;
#undef FAST_BOOT
#include "hboot.s"
#ifndef MULTIPASS
#define MULTIPASS 0
#endif
#define LOMEIN_TEXT_VA [0x]mpeval(MAIN_BASE_TEXT_VA&0xffffffff,16)
#define LOMEIN_DATA_VA [0x]mpeval(MAIN_BASE_DATA_VA&0xffffffff,16)
changequote([, ])dnl
SECTION .LOMEIN TEXT_VA=LOMEIN_TEXT_VA, DATA_VA=LOMEIN_DATA_VA
attr_text {
Name = .LOMEIN,
VA= LOMEIN_TEXT_VA,
RA= MAIN_BASE_TEXT_RA,
PA= ra2pa2(MAIN_BASE_TEXT_RA, 0),
part_0_ctx_nonzero_tsb_config_1,
part_0_ctx_zero_tsb_config_1,
TTE_G=1, TTE_Context=0x44, TTE_V=1,
TTE_Size=0, TTE_NFO=0, TTE_IE=0, TTE_Soft2=0, TTE_Diag=0, TTE_Soft=0,
TTE_L=0, TTE_CP=1, TTE_CV=0, TTE_E=0, TTE_P=0, TTE_W=1, TTE_X=1,
tsbonly
}
attr_data {
Name = .LOMEIN,
VA= LOMEIN_DATA_VA,
RA= MAIN_BASE_DATA_RA,
PA= ra2pa2(MAIN_BASE_DATA_RA, 0),
part_0_ctx_nonzero_tsb_config_2,
part_0_ctx_zero_tsb_config_2
TTE_G=1, TTE_Context=0x44, TTE_V=1, TTE_Size=0, TTE_NFO=0,
TTE_IE=0, TTE_Soft2=0, TTE_Diag=0, TTE_Soft=0,
TTE_L=0, TTE_CP=1, TTE_CV=0, TTE_E=0, TTE_P=0, TTE_W=1, TTE_X=0,
tsbonly
}
attr_data {
Name = .LOMEIN,
VA= LOMEIN_DATA_VA,
RA= MAIN_BASE_DATA_RA,
PA= ra2pa2(MAIN_BASE_DATA_RA, 0),
part_0_ctx_nonzero_tsb_config_3,
part_0_ctx_zero_tsb_config_3
TTE_G=1, TTE_Context=0x55, TTE_V=1, TTE_Size=0, TTE_NFO=0,
TTE_IE=0, TTE_Soft2=0, TTE_Diag=0, TTE_Soft=0,
TTE_L=0, TTE_CP=1, TTE_CV=0, TTE_E=0, TTE_P=0, TTE_W=1, TTE_X=0,
tsbonly
}
.text
.align 0x100000
nop
.data
.word 0x0
SECTION .MAIN TEXT_VA=MAIN_BASE_TEXT_VA, DATA_VA=MAIN_BASE_DATA_VA
attr_text {
Name = .MAIN,
VA=MAIN_BASE_TEXT_VA,
RA= LOMEIN_TEXT_VA,
PA= LOMEIN_TEXT_VA,
part_0_ctx_nonzero_tsb_config_2,
part_0_ctx_zero_tsb_config_2,
TTE_G=1, TTE_Context=0x44, TTE_V=1,
TTE_Size=0, TTE_NFO=0, TTE_IE=0, TTE_Soft2=0, TTE_Diag=0, TTE_Soft=0,
TTE_L=0, TTE_CP=1, TTE_CV=0, TTE_E=0, TTE_P=0, TTE_W=1, TTE_X=1,
}
attr_data {
Name = .MAIN,
VA=MAIN_BASE_DATA_VA
RA= LOMEIN_DATA_VA,
PA= LOMEIN_DATA_VA,
part_0_ctx_nonzero_tsb_config_1,
part_0_ctx_zero_tsb_config_1
TTE_G=1, TTE_Context=0x44, TTE_V=1, TTE_Size=0, TTE_NFO=0,
TTE_IE=0, TTE_Soft2=0, TTE_Diag=0, TTE_Soft=0,
TTE_L=0, TTE_CP=1, TTE_CV=0, TTE_E=0, TTE_P=0, TTE_W=1, TTE_X=0,
}
attr_data {
Name = .MAIN,
VA=MAIN_BASE_DATA_VA
RA= LOMEIN_DATA_VA,
PA= LOMEIN_DATA_VA,
part_0_ctx_nonzero_tsb_config_3,
part_0_ctx_zero_tsb_config_3
TTE_G=1, TTE_Context=0x55, TTE_V=1, TTE_Size=0, TTE_NFO=0,
TTE_IE=0, TTE_Soft2=0, TTE_Diag=0, TTE_Soft=0,
TTE_L=0, TTE_CP=1, TTE_CV=0, TTE_E=0, TTE_P=0, TTE_W=1, TTE_X=0,
tsbonly
}
attr_text {
Name = .MAIN,
VA=MAIN_BASE_TEXT_VA,
hypervisor
}
attr_data {
Name = .MAIN,
VA=MAIN_BASE_DATA_VA
hypervisor
}
changequote(`,')dnl'
.text
.global main
main:
! Set up ld/st area per thread
ta T_CHANGE_HPRIV
ldxa [%g0]0x63, %o2
and %o2, 0x7, %o1
brnz %o1, init_start
mov 0xff, %r11
lock_sync_thds:
set sync_thr_counter4, %r23
#if(!defined SPC && !defined PORTABLE_CORE)
and %o2, 0x38, %o2
add %o2,%r23,%r23 !Core's sync counter
#endif
st %r11, [%r23] !lock sync_thr_counter4
add %r23, 64, %r23
st %r11, [%r23] !lock sync_thr_counter5
add %r23, 64, %r23
st %r11, [%r23] !lock sync_thr_counter6
init_start:
wrhpr %g0, 0x0, %hpstate ! ta T_CHANGE_NONHPRIV
umul %r9, 256, %r31
setx user_data_start, %r1, %r3
add %r31, %r3, %r31
wr %r0, 0x4, %asi
!Initializing integer registers
ldx [%r31+0], %r0
ldx [%r31+8], %r1
ldx [%r31+16], %r2
ldx [%r31+24], %r3
ldx [%r31+32], %r4
ldx [%r31+40], %r5
ldx [%r31+48], %r6
ldx [%r31+56], %r7
ldx [%r31+64], %r8
ldx [%r31+72], %r9
ldx [%r31+80], %r10
ldx [%r31+88], %r11
ldx [%r31+96], %r12
ldx [%r31+104], %r13
ldx [%r31+112], %r14
mov %r31, %r15
ldx [%r31+128], %r16
ldx [%r31+136], %r17
ldx [%r31+144], %r18
ldx [%r31+152], %r19
ldx [%r31+160], %r20
ldx [%r31+168], %r21
ldx [%r31+176], %r22
ldx [%r31+184], %r23
ldx [%r31+192], %r24
ldx [%r31+200], %r25
ldx [%r31+208], %r26
ldx [%r31+216], %r27
ldx [%r31+224], %r28
ldx [%r31+232], %r29
mov 0x30, %r14
mov 0x35, %r30
save %r31, %r0, %r31
ldx [%r31+0], %r0
ldx [%r31+8], %r1
ldx [%r31+16], %r2
ldx [%r31+24], %r3
ldx [%r31+32], %r4
ldx [%r31+40], %r5
ldx [%r31+48], %r6
ldx [%r31+56], %r7
ldx [%r31+64], %r8
ldx [%r31+72], %r9
ldx [%r31+80], %r10
ldx [%r31+88], %r11
ldx [%r31+96], %r12
ldx [%r31+104], %r13
ldx [%r31+112], %r14
mov %r31, %r15
ldx [%r31+128], %r16
ldx [%r31+136], %r17
ldx [%r31+144], %r18
ldx [%r31+152], %r19
ldx [%r31+160], %r20
ldx [%r31+168], %r21
ldx [%r31+176], %r22
ldx [%r31+184], %r23
ldx [%r31+192], %r24
ldx [%r31+200], %r25
ldx [%r31+208], %r26
ldx [%r31+216], %r27
ldx [%r31+224], %r28
ldx [%r31+232], %r29
mov 0x34, %r14
mov 0x33, %r30
save %r31, %r0, %r31
ldx [%r31+0], %r0
ldx [%r31+8], %r1
ldx [%r31+16], %r2
ldx [%r31+24], %r3
ldx [%r31+32], %r4
ldx [%r31+40], %r5
ldx [%r31+48], %r6
ldx [%r31+56], %r7
ldx [%r31+64], %r8
ldx [%r31+72], %r9
ldx [%r31+80], %r10
ldx [%r31+88], %r11
ldx [%r31+96], %r12
ldx [%r31+104], %r13
ldx [%r31+112], %r14
mov %r31, %r15
ldx [%r31+128], %r16
ldx [%r31+136], %r17
ldx [%r31+144], %r18
ldx [%r31+152], %r19
ldx [%r31+160], %r20
ldx [%r31+168], %r21
ldx [%r31+176], %r22
ldx [%r31+184], %r23
ldx [%r31+192], %r24
ldx [%r31+200], %r25
ldx [%r31+208], %r26
ldx [%r31+216], %r27
ldx [%r31+224], %r28
ldx [%r31+232], %r29
mov 0xb5, %r14
mov 0x32, %r30
save %r31, %r0, %r31
ldx [%r31+0], %r0
ldx [%r31+8], %r1
ldx [%r31+16], %r2
ldx [%r31+24], %r3
ldx [%r31+32], %r4
ldx [%r31+40], %r5
ldx [%r31+48], %r6
ldx [%r31+56], %r7
ldx [%r31+64], %r8
ldx [%r31+72], %r9
ldx [%r31+80], %r10
ldx [%r31+88], %r11
ldx [%r31+96], %r12
ldx [%r31+104], %r13
ldx [%r31+112], %r14
mov %r31, %r15
ldx [%r31+128], %r16
ldx [%r31+136], %r17
ldx [%r31+144], %r18
ldx [%r31+152], %r19
ldx [%r31+160], %r20
ldx [%r31+168], %r21
ldx [%r31+176], %r22
ldx [%r31+184], %r23
ldx [%r31+192], %r24
ldx [%r31+200], %r25
ldx [%r31+208], %r26
ldx [%r31+216], %r27
ldx [%r31+224], %r28
ldx [%r31+232], %r29
mov 0xb3, %r14
mov 0xb3, %r30
save %r31, %r0, %r31
ldx [%r31+0], %r0
ldx [%r31+8], %r1
ldx [%r31+16], %r2
ldx [%r31+24], %r3
ldx [%r31+32], %r4
ldx [%r31+40], %r5
ldx [%r31+48], %r6
ldx [%r31+56], %r7
ldx [%r31+64], %r8
ldx [%r31+72], %r9
ldx [%r31+80], %r10
ldx [%r31+88], %r11
ldx [%r31+96], %r12
ldx [%r31+104], %r13
ldx [%r31+112], %r14
mov %r31, %r15
ldx [%r31+128], %r16
ldx [%r31+136], %r17
ldx [%r31+144], %r18
ldx [%r31+152], %r19
ldx [%r31+160], %r20
ldx [%r31+168], %r21
ldx [%r31+176], %r22
ldx [%r31+184], %r23
ldx [%r31+192], %r24
ldx [%r31+200], %r25
ldx [%r31+208], %r26
ldx [%r31+216], %r27
ldx [%r31+224], %r28
ldx [%r31+232], %r29
mov 0xb2, %r14
mov 0x31, %r30
save %r31, %r0, %r31
ldx [%r31+0], %r0
ldx [%r31+8], %r1
ldx [%r31+16], %r2
ldx [%r31+24], %r3
ldx [%r31+32], %r4
ldx [%r31+40], %r5
ldx [%r31+48], %r6
ldx [%r31+56], %r7
ldx [%r31+64], %r8
ldx [%r31+72], %r9
ldx [%r31+80], %r10
ldx [%r31+88], %r11
ldx [%r31+96], %r12
ldx [%r31+104], %r13
ldx [%r31+112], %r14
mov %r31, %r15
ldx [%r31+128], %r16
ldx [%r31+136], %r17
ldx [%r31+144], %r18
ldx [%r31+152], %r19
ldx [%r31+160], %r20
ldx [%r31+168], %r21
ldx [%r31+176], %r22
ldx [%r31+184], %r23
ldx [%r31+192], %r24
ldx [%r31+200], %r25
ldx [%r31+208], %r26
ldx [%r31+216], %r27
ldx [%r31+224], %r28
ldx [%r31+232], %r29
mov 0xb2, %r14
mov 0x33, %r30
save %r31, %r0, %r31
ldx [%r31+0], %r0
ldx [%r31+8], %r1
ldx [%r31+16], %r2
ldx [%r31+24], %r3
ldx [%r31+32], %r4
ldx [%r31+40], %r5
ldx [%r31+48], %r6
ldx [%r31+56], %r7
ldx [%r31+64], %r8
ldx [%r31+72], %r9
ldx [%r31+80], %r10
ldx [%r31+88], %r11
ldx [%r31+96], %r12
ldx [%r31+104], %r13
ldx [%r31+112], %r14
mov %r31, %r15
ldx [%r31+128], %r16
ldx [%r31+136], %r17
ldx [%r31+144], %r18
ldx [%r31+152], %r19
ldx [%r31+160], %r20
ldx [%r31+168], %r21
ldx [%r31+176], %r22
ldx [%r31+184], %r23
ldx [%r31+192], %r24
ldx [%r31+200], %r25
ldx [%r31+208], %r26
ldx [%r31+216], %r27
ldx [%r31+224], %r28
ldx [%r31+232], %r29
mov 0xb5, %r14
mov 0x33, %r30
save %r31, %r0, %r31
restore
restore
restore
!Initializing float registers
ldd [%r31+0], %f0
ldd [%r31+16], %f2
ldd [%r31+32], %f4
ldd [%r31+48], %f6
ldd [%r31+64], %f8
ldd [%r31+80], %f10
ldd [%r31+96], %f12
ldd [%r31+112], %f14
ldd [%r31+128], %f16
ldd [%r31+144], %f18
ldd [%r31+160], %f20
ldd [%r31+176], %f22
ldd [%r31+192], %f24
ldd [%r31+208], %f26
ldd [%r31+224], %f28
ldd [%r31+240], %f30
!! Set TPC/TNPC to diag-finish in case we get to a strange TL ..
ta T_CHANGE_HPRIV
setx diag_finish, %r29, %r28
add %r28, 4, %r29
wrpr %g0, 1, %tl
wrpr %r28, %tpc
wrpr %r29, %tnpc
wrpr %g0, 2, %tl
wrpr %r28, %tpc
wrpr %r29, %tnpc
wrpr %g0, 3, %tl
wrpr %r28, %tpc
wrpr %r29, %tnpc
wrpr %g0, 4, %tl
wrpr %r28, %tpc
wrpr %r29, %tnpc
wrpr %g0, 5, %tl
wrpr %r28, %tpc
wrpr %r29, %tnpc
wrpr %g0, 6, %tl
wrpr %r28, %tpc
wrpr %r29, %tnpc
wrpr %g0, 0, %tl
!Initializing Tick Cmprs
mov 1, %g2
sllx %g2, 63, %g2
or %g1, %g2, %g1
wrhpr %g1, %g0, %hsys_tick_cmpr
wr %g1, %g0, %tick_cmpr
wr %g1, %g0, %sys_tick_cmpr
#if (MULTIPASS > 0)
mov 0x38, %g1
stxa %r0, [%g1]ASI_SCRATCHPAD
#endif
! Set up fpr PMU traps
set 0x58f08838, %g2
b fork_threads
wr %g2, %g0, %pcr
.align 1024
common_target:
nop
sub %r27, 8, %r27
and %r27, 8, %r12
mov HIGHVA_HIGHNUM, %r11
sllx %r11, 32, %r11
or %r27, %r11, %r27
brz,a %r12, .+8
lduw [%r27], %r12 ! load jmp dest into dcache - xinval
return %r27
.word 0x9bb344d4 ! 1: FCMPNE32 fcmpne32 %d44, %d20, %r13
nop
jmp %r27
nop
!$EV trig_pc_d(1,@VA(.MAIN.fork_threads)) -> marker(bootEnd, *, 1)
fork_threads:
rd %tick, %r17
mov 0x40, %g1
setup_hwtw_config:
stxa %r17, [%g1]0x58
ta %icc, T_RD_THID
! fork: source strm = 0xffffffffffffffff; target strm = 0x1
cmp %o1, 0
setx fork_lbl_0_1, %g2, %g3
be,a .+8
jmp %g3
nop
! fork: source strm = 0xffffffffffffffff; target strm = 0x2
cmp %o1, 1
setx fork_lbl_0_2, %g2, %g3
be,a .+8
jmp %g3
nop
! fork: source strm = 0xffffffffffffffff; target strm = 0x4
cmp %o1, 2
setx fork_lbl_0_3, %g2, %g3
be,a .+8
jmp %g3
nop
! fork: source strm = 0xffffffffffffffff; target strm = 0x8
cmp %o1, 3
setx fork_lbl_0_4, %g2, %g3
be,a .+8
jmp %g3
nop
! fork: source strm = 0xffffffffffffffff; target strm = 0x10
cmp %o1, 4
setx fork_lbl_0_5, %g2, %g3
be,a .+8
jmp %g3
nop
! fork: source strm = 0xffffffffffffffff; target strm = 0x20
cmp %o1, 5
setx fork_lbl_0_6, %g2, %g3
be,a .+8
jmp %g3
nop
! fork: source strm = 0xffffffffffffffff; target strm = 0x40
cmp %o1, 6
setx fork_lbl_0_7, %g2, %g3
be,a .+8
jmp %g3
nop
! fork: source strm = 0xffffffffffffffff; target strm = 0x80
cmp %o1, 7
setx fork_lbl_0_8, %g2, %g3
be,a .+8
jmp %g3
nop
.text
setx join_lbl_0_0, %g1, %g2
jmp %g2
nop
.text
setx join_lbl_0_0, %g1, %g2
jmp %g2
nop
fork_lbl_0_8:
wrhpr %g0, 0x948, %hpstate ! ta T_CHANGE_NONHPRIV
.word 0x0a800001 ! 1: BCS bcs <label_0x1>
.word 0x8d903475 ! 1: WRPR_PSTATE_I wrpr %r0, 0x1475, %pstate
frzptr_80_3:
nop
nop
best_set_reg(0x3cb40000+0x1ffc, %r20, %r27)
ldx [%r27+0xc], %r20
jmpl %r27, %r27
.word 0x20800001 ! 5: BN bn,a <label_0x1>
jmptr_80_5:
nop
nop
best_set_reg(0xe0a00000, %r20, %r27)
.word 0xb7c6c000 ! 9: JMPL_R jmpl %r27 + %r0, %r27
.word 0xc32fc000 ! 13: STXFSR_R st-sfr %f1, [%r0, %r31]
.word 0xda97d160 ! 17: LDUHA_R lduha [%r31, %r0] 0x8b, %r13
jmptr_80_9:
nop
nop
best_set_reg(0xe1a00000, %r20, %r27)
.word 0xb7c6c000 ! 21: JMPL_R jmpl %r27 + %r0, %r27
.word 0x8980000a ! 25: WRTICK_R wr %r0, %r10, %tick
.word 0xda800b20 ! 29: LDUWA_R lduwa [%r0, %r0] 0x59, %r13
.word 0x87ad0a53 ! 33: FCMPd fcmpd %fcc<n>, %f20, %f50
.word 0xe2800be0 ! 37: LDUWA_R lduwa [%r0, %r0] 0x5f, %r17
.word 0xe24fc000 ! 41: LDSB_R ldsb [%r31 + %r0], %r17
.word 0xa3b7c480 ! 1: FCMPLE32 fcmple32 %d62, %d0, %r17
.word 0xe3e7e000 ! 1: CASA_R casa [%r31] %asi, %r0, %r17
mov 0x33, %r30
.word 0x91d0001e ! 45: Tcc_R ta icc_or_xcc, %r0 + %r30
demap_80_21:
nop
mov 0x80, %g3
ta T_CHANGE_HPRIV
.word 0x30800002 ! 1: BA ba,a <label_0x2>
stxa %g3, [%g3] 0x5f
.word 0xe1bfc2c0 ! 1: STDFA_R stda %f16, [%r0, %r31]
wrhpr %g0, 0x29a, %hpstate ! ta T_CHANGE_NONHPRIV
.word 0xe21fe191 ! 49: LDD_I ldd [%r31 + 0x0191], %r17
.word 0xe247c000 ! 53: LDSW_R ldsw [%r31 + %r0], %r17
splash_lsu_80_22:
nop
nop
ta T_CHANGE_HPRIV
set 0xadc05f9b, %r2
mov 0x7, %r1
sllx %r1, 32, %r1
or %r1, %r2, %r2
.word 0x3e800001 ! 1: BVC bvc,a <label_0x1>
stxa %r2, [%r0] ASI_LSU_CONTROL
.word 0x3d400002 ! 57: FBPULE fbule,a,pn %fcc0, <label_0x2>
demap_80_25:
nop
mov 0x80, %g3
ta T_CHANGE_HPRIV
.word 0x25400001 ! 1: FBPLG fblg,a,pn %fcc0, <label_0x1>
stxa %g3, [%g3] 0x5f
.word 0xc1bfc2c0 ! 1: STDFA_R stda %f0, [%r0, %r31]
.word 0xe1bfde00 ! 1: STDFA_R stda %f16, [%r0, %r31]
.word 0xc0bfc3e0 ! 1: STDA_R stda %r0, [%r31 + %r0] 0x1f
stxa %g3, [%g3] 0x57
stxa %g3, [%g3] 0x5f
.word 0xc0bfde00 ! 1: STDA_R stda %r0, [%r31 + %r0] 0xf0
stxa %g3, [%g3] 0x5f
.word 0xc1bfde00 ! 1: STDFA_R stda %f0, [%r0, %r31]
.word 0xc1bfda60 ! 1: STDFA_R stda %f0, [%r0, %r31]
.word 0xe09fda60 ! 1: LDDA_R ldda [%r31, %r0] 0xd3, %r16
stxa %g3, [%g3] 0x5f
stxa %g3, [%g3] 0x57
.word 0xc19fda00 ! 1: LDDFA_R ldda [%r31, %r0], %f0
wrhpr %g0, 0x301, %hpstate ! ta T_CHANGE_NONHPRIV
.word 0xe21fe053 ! 61: LDD_I ldd [%r31 + 0x0053], %r17
nop
nop
mov 0x1, %r11
splash_cmpr_80_28:
sllx %r11, 63, %r11
not %r11, %r11
rd %tick, %r10
#if (defined SPC || defined CMP1)
add %r10, 0x150, %r10
#else
add %r10, 0x380, %r10
#endif
and %r10, %r11, %r10
ta T_CHANGE_PRIV
rd %tick, %r10
#if (defined SPC || defined CMP1)
add %r10, 0x200, %r10
#else
add %r10, 0xc00, %r10
#endif
and %r10, %r11, %r10
.word 0xb380000a ! 1: WR_STICK_CMPR_REG_R wr %r0, %r10, %-
#if (defined SPC || defined CMP1)
!$EV trig_pc_d(1, expr(@VA(.MAIN.splash_cmpr_80_28)+8 , 16, 16)) -> intp(4,0,27,*,960,*,f2,1)
!$EV trig_pc_d(1, expr((@VA(.MAIN.splash_cmpr_80_28)&0xffffffff)+8 , 16, 16)) -> intp(6,0,12,*,680,*,f2,1)
#endif
wrhpr %g0, 0x0, %halt ! HALT
.word 0x81b01021 ! 65: SIAM siam 1
.word 0xc19fe1e0 ! 69: LDDFA_I ldda [%r31, 0x01e0], %f0
.word 0xa1902009 ! 73: WRPR_GL_I wrpr %r0, 0x0009, %-
jmptr_80_34:
nop
nop
best_set_reg(0xe0a00000, %r20, %r27)
.word 0xb7c6c000 ! 77: JMPL_R jmpl %r27 + %r0, %r27
nop
nop
ta T_CHANGE_HPRIV ! macro
donret_80_35:
rd %pc, %r12
mov HIGHVA_HIGHNUM, %r10
sllx %r10, 32, %r10
or %r12, %r10, %r12
add %r12, (donretarg_80_35-donret_80_35+4), %r12
add %r12, 0x4, %r11 ! seq tnpc
andn %r11, %r10, %r11 ! low VA tnpc
wrpr %g0, 0x2, %tl
wrpr %g0, %r12, %tpc
wrpr %g0, %r11, %tnpc
set (0x00dbab00 | (0x4f << 24)), %r13
and %r12, 0xfff, %r14
sllx %r14, 32, %r14
or %r13, %r14, %r20
wrpr %r20, %g0, %tstate
wrhpr %g0, 0x174e, %htstate
best_set_reg(0x1940, %g1, %g2)
wrpr %g0, %g2, %pstate ! rand=0 (80)
done
donretarg_80_35:
.word 0x8d9024bb ! 81: WRPR_PSTATE_I wrpr %r0, 0x04bb, %pstate
#if (defined SPC || defined CMP1)
!$EV trig_pc_d(1, expr(@VA(.MAIN.intvec_80_36) , 16, 16)) -> intp(4,0,18,*,640,*,c4,1)
!$EV trig_pc_d(1, expr((@VA(.MAIN.intvec_80_36)&0xffffffff) , 16, 16)) -> intp(0,0,23,*,736,*,c4,1)
#else
nop
nop
set 0x9f900fae, %r28 !TTID : 7 (mask2tid(0x80))
#if (defined PORTABLE_CORE || MAX_THREADS == 8)
sethi %hi(0x3800), %r27
andn %r28, %r27, %r28
#ifdef PORTABLE_CORE
! Add CID to vector
ta T_CHANGE_HPRIV
ldxa [%g0]0x63, %r27
sllx %r27, 8, %r27
or %r27, %r28, %r28
#endif
#else
! Add CID IF tid matches
ifelse(7,mask2tid(0x80),`ta T_CHANGE_HPRIV;sethi %hi(0x3800), %r27;andn %r28, %r27, %r28;ldxa [%g0]0x63, %r27;sllx %r27, 8, %r27;or %r27, %r28, %r28 ')
#endif
ifelse(7,mask2tid(0x80),`.align 16')
stxa %r28, [%g0] 0x73
#endif
intvec_80_36:
#if (defined SPC || defined CMP1)
wrhpr %g0, 0x0, %halt ! HALT
#else
ifelse(7,mask2tid(0x80),`wrhpr %g0, 0x0, %halt ! HALT')
#endif
.word 0xa5a489c7 ! 85: FDIVd fdivd %f18, %f38, %f18
.word 0xa0810008 ! 89: ADDcc_R addcc %r4, %r8, %r16
nop
nop
set 0x6910732b, %r28 !TTID : 3 (mask2tid(0x80))
#if (defined PORTABLE_CORE || MAX_THREADS == 8)
sethi %hi(0x3800), %r27
andn %r28, %r27, %r28
#ifdef PORTABLE_CORE
! Add CID to vector
ta T_CHANGE_HPRIV
ldxa [%g0]0x63, %r27
sllx %r27, 8, %r27
or %r27, %r28, %r28
#endif
#else
! Add CID IF tid matches
ifelse(3,mask2tid(0x80),`ta T_CHANGE_HPRIV;sethi %hi(0x3800), %r27;andn %r28, %r27, %r28;ldxa [%g0]0x63, %r27;sllx %r27, 8, %r27;or %r27, %r28, %r28 ')
#endif
sethi %hi(0x30000), %r27
andn %r28, %r27, %r28
ta T_CHANGE_HPRIV
ifelse(3,mask2tid(0x80),`.align 16')
stxa %r28, [%g0] 0x73
intvec_80_39:
.word 0x39400001 ! 93: FBPUGE fbuge,a,pn %fcc0, <label_0x1>
.word 0x81460000 ! 97: RD_STICK_REG stbar
.word 0xe13fe030 ! 101: STDF_I std %f16, [0x0030, %r31]
.word 0x3c800001 ! 105: BPOS bpos,a <label_0x1>
nop
nop
set 0xa350ab65, %r28 !TTID : 3 (mask2tid(0x80))
#if (defined PORTABLE_CORE || MAX_THREADS == 8)
sethi %hi(0x3800), %r27
andn %r28, %r27, %r28
#ifdef PORTABLE_CORE
! Add CID to vector
ta T_CHANGE_HPRIV
ldxa [%g0]0x63, %r27
sllx %r27, 8, %r27
or %r27, %r28, %r28
#endif
#else
! Add CID IF tid matches
ifelse(3,mask2tid(0x80),`ta T_CHANGE_HPRIV;sethi %hi(0x3800), %r27;andn %r28, %r27, %r28;ldxa [%g0]0x63, %r27;sllx %r27, 8, %r27;or %r27, %r28, %r28 ')
#endif
sethi %hi(0x30000), %r27
andn %r28, %r27, %r28
ta T_CHANGE_HPRIV
ifelse(3,mask2tid(0x80),`.align 16')
stxa %r28, [%g0] 0x73
intvec_80_47:
.word 0xa1a409d0 ! 109: FDIVd fdivd %f16, %f16, %f16
.word 0xd88008a0 ! 113: LDUWA_R lduwa [%r0, %r0] 0x45, %r12
nop
nop
mov 0x0, %r11
splash_cmpr_80_52:
sllx %r11, 63, %r11
not %r11, %r11
rd %tick, %r10
#if (defined SPC || defined CMP1)
add %r10, 0x200, %r10
#else
add %r10, 0x380, %r10
#endif
and %r10, %r11, %r10
rd %tick, %r10
#if (defined SPC || defined CMP1)
add %r10, 0x300, %r10
#else
add %r10, 0x380, %r10
#endif
and %r10, %r11, %r10
.word 0xb380000a ! 1: WR_STICK_CMPR_REG_R wr %r0, %r10, %-
.word 0x81b01021 ! 117: SIAM siam 1
.word 0x8d802000 ! 121: WRFPRS_I wr %r0, 0x0000, %fprs
.word 0x9adcc00a ! 125: SMULcc_R smulcc %r19, %r10, %r13
brcommon2_80_54:
nop
nop
setx common_target, %r12, %r27
ba,a .+12
.word 0x97a489d0 ! 1: FDIVd fdivd %f18, %f16, %f42
ba,a .+8
jmpl %r27-4, %r27
.word 0xc1bfc3e0 ! 129: STDFA_R stda %f0, [%r0, %r31]
memptr_80_56:
set 0x60340000, %r31
.word 0x85833aaf ! 133: WRCCR_I wr %r12, 0x1aaf, %ccr
splash_lsu_80_58:
nop
nop
ta T_CHANGE_HPRIV
set 0x2f1372bb, %r2
mov 0x4, %r1
sllx %r1, 32, %r1
or %r1, %r2, %r2
stxa %r2, [%r0] ASI_LSU_CONTROL
ta T_CHANGE_NONHPRIV
.word 0x1d400001 ! 137: FBPULE fbule
.word 0xda77e1a2 ! 141: STX_I stx %r13, [%r31 + 0x01a2]
jmptr_80_65:
nop
nop
best_set_reg(0xe1a00000, %r20, %r27)
.word 0xb7c6c000 ! 145: JMPL_R jmpl %r27 + %r0, %r27
.word 0x91d020b3 ! 149: Tcc_I ta icc_or_xcc, %r0 + 179
.word 0xda8008a0 ! 153: LDUWA_R lduwa [%r0, %r0] 0x45, %r13
fpinit_80_70:
nop
setx fp_data_quads, %r19, %r20
ldd [%r20], %f0
ldd [%r20+8], %f4
ld [%r20+16], %fsr
ld [%r20+24], %r19
wr %r19, %g0, %gsr
.word 0x91a009c4 ! 157: FDIVd fdivd %f0, %f4, %f8
.word 0xc1bfdf00 ! 161: STDFA_R stda %f0, [%r0, %r31]
.word 0xda1fe150 ! 165: LDD_I ldd [%r31 + 0x0150], %r13
br_badelay3_80_78:
.word 0x91a489d0 ! 1: FDIVd fdivd %f18, %f16, %f8
.word 0xb9431b89 ! Random illegal ?
.word 0xe1144014 ! 1: LDQF_R - [%r17, %r20], %f16
.word 0xa5a4c833 ! 169: FADDs fadds %f19, %f19, %f18
.word 0xd2c7d040 ! 173: LDSWA_R ldswa [%r31, %r0] 0x82, %r9
nop
nop
ta T_CHANGE_HPRIV ! macro
donret_80_82:
rd %pc, %r12
mov HIGHVA_HIGHNUM, %r10
sllx %r10, 32, %r10
or %r12, %r10, %r12
add %r12, (donretarg_80_82-donret_80_82+4), %r12
add %r12, 0x4, %r11 ! seq tnpc
wrpr %g0, 0x1, %tl
wrpr %g0, %r12, %tpc
wrpr %g0, %r11, %tnpc
set (0x002a6600 | (0x89 << 24)), %r13
and %r12, 0xfff, %r14
sllx %r14, 32, %r14
or %r13, %r14, %r20
wrpr %r20, %g0, %tstate
wrhpr %g0, 0x917, %htstate
wrhpr %g0, 0x43, %hpstate ! rand=1 (80)
ldx [%r12+%r0], %g1
retry
donretarg_80_82:
.word 0x99a4c9d1 ! 177: FDIVd fdivd %f50, %f48, %f12
nop
nop
set 0x47e005ff, %r28 !TTID : 5 (mask2tid(0x80))
#if (defined PORTABLE_CORE || MAX_THREADS == 8)
sethi %hi(0x3800), %r27
andn %r28, %r27, %r28
#ifdef PORTABLE_CORE
! Add CID to vector
ta T_CHANGE_HPRIV
ldxa [%g0]0x63, %r27
sllx %r27, 8, %r27
or %r27, %r28, %r28
#endif
#else
! Add CID IF tid matches
ifelse(5,mask2tid(0x80),`ta T_CHANGE_HPRIV;sethi %hi(0x3800), %r27;andn %r28, %r27, %r28;ldxa [%g0]0x63, %r27;sllx %r27, 8, %r27;or %r27, %r28, %r28 ')
#endif
sethi %hi(0x30000), %r27
andn %r28, %r27, %r28
ta T_CHANGE_HPRIV
ifelse(5,mask2tid(0x80),`.align 16')
stxa %r28, [%g0] 0x73
intvec_80_83:
.word 0x39400001 ! 181: FBPUGE fbuge,a,pn %fcc0, <label_0x1>
brcommon3_80_86:
nop
nop
setx common_target, %r12, %r27
lduw [%r27], %r12 ! Load common dest into dcache ..
stuw %r12, [%r27] ! Load common dest into dcache ..
ba,a .+12
.word 0xd86fe080 ! 1: LDSTUB_I ldstub %r12, [%r31 + 0x0080]
ba,a .+8
jmpl %r27+0, %r27
stxa %r15, [%r0] ASI_LSU_CONTROL
.word 0xa1aac827 ! 185: FMOVGE fmovs %fcc1, %f7, %f16
cancelint_80_89:
rdhpr %halt, %r19
.word 0x85880000 ! 189: ALLCLEAN <illegal instruction>
.word 0xe927e1d8 ! 193: STF_I st %f20, [0x01d8, %r31]
splash_lsu_80_94:
nop
nop
ta T_CHANGE_HPRIV
set 0xce2fc737, %r2
mov 0x4, %r1
sllx %r1, 32, %r1
or %r1, %r2, %r2
.word 0x34800002 ! 1: BG bg,a <label_0x2>
stxa %r2, [%r0] ASI_LSU_CONTROL
ta T_CHANGE_NONHPRIV
.word 0x3d400001 ! 197: FBPULE fbule,a,pn %fcc0, <label_0x1>
.word 0xa1902003 ! 201: WRPR_GL_I wrpr %r0, 0x0003, %-
br_badelay3_80_98:
.word 0x34800001 ! 1: BG bg,a <label_0x1>
.word 0xfb781e6b ! Random illegal ?
.word 0xa9a0054b ! 1: FSQRTd fsqrt
.word 0xa5a20828 ! 205: FADDs fadds %f8, %f8, %f18
.word 0x8f902001 ! 1: WRPR_TL_I wrpr %r0, 0x0001, %tl
reduce_priv_lvl_80_99:
ta T_CHANGE_NONPRIV ! macro
splash_lsu_80_102:
nop
nop
ta T_CHANGE_HPRIV
set 0x3ee70486, %r2
mov 0x1, %r1
sllx %r1, 32, %r1
or %r1, %r2, %r2
stxa %r2, [%r0] ASI_LSU_CONTROL
ta T_CHANGE_NONHPRIV
.word 0x1d400001 ! 213: FBPULE fbule
.word 0x8d9032b9 ! 217: WRPR_PSTATE_I wrpr %r0, 0x12b9, %pstate
.word 0xe53fe010 ! 221: STDF_I std %f18, [0x0010, %r31]
.word 0xc19fde20 ! 225: LDDFA_R ldda [%r31, %r0], %f0
#if (defined SPC || defined CMP1)
!$EV trig_pc_d(1, expr(@VA(.MAIN.intvec_80_112) , 16, 16)) -> intp(3,0,27,*,912,*,83,1)
!$EV trig_pc_d(1, expr((@VA(.MAIN.intvec_80_112)&0xffffffff) , 16, 16)) -> intp(5,0,24,*,960,*,83,1)
#else
nop
nop
set 0x49f09305, %r28 !TTID : 3 (mask2tid(0x80))
#if (defined PORTABLE_CORE || MAX_THREADS == 8)
sethi %hi(0x3800), %r27
andn %r28, %r27, %r28
#ifdef PORTABLE_CORE
! Add CID to vector
ta T_CHANGE_HPRIV
ldxa [%g0]0x63, %r27
sllx %r27, 8, %r27
or %r27, %r28, %r28
#endif
#else
! Add CID IF tid matches
ifelse(3,mask2tid(0x80),`ta T_CHANGE_HPRIV;sethi %hi(0x3800), %r27;andn %r28, %r27, %r28;ldxa [%g0]0x63, %r27;sllx %r27, 8, %r27;or %r27, %r28, %r28 ')
#endif
ifelse(3,mask2tid(0x80),`.align 16')
stxa %r28, [%g0] 0x73
#endif
intvec_80_112:
.word 0xa7b404d4 ! 229: FCMPNE32 fcmpne32 %d16, %d20, %r19
jmptr_80_115:
nop
nop
best_set_reg(0xe0a00000, %r20, %r27)
.word 0xb7c6c000 ! 233: JMPL_R jmpl %r27 + %r0, %r27
.word 0xd097d160 ! 237: LDUHA_R lduha [%r31, %r0] 0x8b, %r8
intveclr_80_120:
nop
nop
ta T_CHANGE_HPRIV
setx 0x4293d3c6e72919d3, %r1, %r28
stxa %r28, [%g0] 0x72
wrhpr %g0, 0xc80, %hpstate ! ta T_CHANGE_NONHPRIV
.word 0x25400002 ! 241: FBPLG fblg,a,pn %fcc0, <label_0x2>
splash_lsu_80_122:
nop
nop
ta T_CHANGE_HPRIV
set 0x4c8e2dab, %r2
mov 0x6, %r1
sllx %r1, 32, %r1
or %r1, %r2, %r2
.word 0x1b400001 ! 1: FBPLE fble
stxa %r2, [%r0] ASI_LSU_CONTROL
ta T_CHANGE_NONHPRIV
.word 0x3d400001 ! 245: FBPULE fbule,a,pn %fcc0, <label_0x1>
.word 0xd137c000 ! 249: STQF_R - %f8, [%r0, %r31]
splash_lsu_80_125:
nop
nop
ta T_CHANGE_HPRIV
set 0x60748c5d, %r2
mov 0x6, %r1
sllx %r1, 32, %r1
or %r1, %r2, %r2
stxa %r2, [%r0] ASI_LSU_CONTROL
.word 0x3d400001 ! 253: FBPULE fbule,a,pn %fcc0, <label_0x1>
.word 0x8980000a ! 257: WRTICK_R wr %r0, %r10, %tick
.word 0xa1902003 ! 261: WRPR_GL_I wrpr %r0, 0x0003, %-
jmptr_80_133:
nop
nop
best_set_reg(0xe1a00000, %r20, %r27)
.word 0xb7c6c000 ! 265: JMPL_R jmpl %r27 + %r0, %r27
nop
nop
mov 0x1, %r11
splash_cmpr_80_134:
sllx %r11, 63, %r11
not %r11, %r11
rd %tick, %r10
#if (defined SPC || defined CMP1)
add %r10, 0x200, %r10
#else
add %r10, 0x900, %r10
#endif
and %r10, %r11, %r10
rd %tick, %r10
#if (defined SPC || defined CMP1)
add %r10, 0x200, %r10
#else
add %r10, 0x700, %r10
#endif
and %r10, %r11, %r10
.word 0xaf80000a ! 1: WR_TICK_CMPR_REG_R wr %r0, %r10, %-
#if (defined SPC || defined CMP1)
!$EV trig_pc_d(1, expr(@VA(.MAIN.splash_cmpr_80_134)+8 , 16, 16)) -> intp(4,0,2,*,928,*,82,1)
!$EV trig_pc_d(1, expr((@VA(.MAIN.splash_cmpr_80_134)&0xffffffff)+8 , 16, 16)) -> intp(7,0,30,*,752,*,82,1)
#endif
wrhpr %g0, 0x0, %halt ! HALT
.word 0x81b01021 ! 269: SIAM siam 1
jmptr_80_135:
nop
nop
best_set_reg(0xe0a00000, %r20, %r27)
.word 0xb7c6c000 ! 273: JMPL_R jmpl %r27 + %r0, %r27
intveclr_80_136:
nop
nop
ta T_CHANGE_HPRIV
setx 0x12b123726358c6c8, %r1, %r28
stxa %r28, [%g0] 0x72
.word 0x05400001 ! 277: FBPLG fblg
.word 0xd137e192 ! 281: STQF_I - %f8, [0x0192, %r31]
splash_hpstate_80_141:
.word 0x21400001 ! 1: FBPN fbn,a,pn %fcc0, <label_0x1>
.word 0x81982e36 ! 285: WRHPR_HPSTATE_I wrhpr %r0, 0x0e36, %hpstate
intveclr_80_145:
nop
nop
ta T_CHANGE_HPRIV
setx 0x72e595794bd2b1ef, %r1, %r28
stxa %r28, [%g0] 0x72
wrhpr %g0, 0x693, %hpstate ! ta T_CHANGE_NONHPRIV
.word 0x25400001 ! 289: FBPLG fblg,a,pn %fcc0, <label_0x1>
brcommon1_80_148:
nop
nop
setx common_target, %r12, %r27
lduw [%r27-4], %r12 ! Load common dest into dcache ..
stuw %r12, [%r27-0] ! Load common dest into dcache ..
ba,a .+12
.word 0x91a7c9c0 ! 1: FDIVd fdivd %f62, %f0, %f8
ba,a .+8
jmpl %r27-4, %r27
.word 0xa5a449d0 ! 293: FDIVd fdivd %f48, %f16, %f18
.word 0xd8dfc720 ! 297: LDXA_R ldxa [%r31, %r0] 0x39, %r12
.word 0x9191c004 ! 301: WRPR_PIL_R wrpr %r7, %r4, %pil
demap_80_156:
nop
mov 0x80, %g3
ta T_CHANGE_HPRIV
.word 0x26cc0001 ! 1: BRLZ brlz,a,pt %r16,<label_0xc0001>
stxa %g3, [%g3] 0x57
.word 0xe09fdf20 ! 1: LDDA_R ldda [%r31, %r0] 0xf9, %r16
stxa %g3, [%g3] 0x57
.word 0xc09fde20 ! 1: LDDA_R ldda [%r31, %r0] 0xf1, %r0
stxa %g3, [%g3] 0x57
.word 0xe19fdf20 ! 1: LDDFA_R ldda [%r31, %r0], %f16
stxa %g3, [%g3] 0x57
.word 0xc09fde00 ! 1: LDDA_R ldda [%r31, %r0] 0xf0, %r0
stxa %g3, [%g3] 0x57
.word 0xe09fdc40 ! 1: LDDA_R ldda [%r31, %r0] 0xe2, %r16
.word 0xc1bfdc00 ! 1: STDFA_R stda %f0, [%r0, %r31]
.word 0xc0bfdf20 ! 1: STDA_R stda %r0, [%r31 + %r0] 0xf9
wrhpr %g0, 0xa01, %hpstate ! ta T_CHANGE_NONHPRIV
.word 0xd81fe1b0 ! 305: LDD_I ldd [%r31 + 0x01b0], %r12
.word 0x91910001 ! 309: WRPR_PIL_R wrpr %r4, %r1, %pil
.word 0xa9b504d0 ! 313: FCMPNE32 fcmpne32 %d20, %d16, %r20
splash_lsu_80_163:
nop
nop
ta T_CHANGE_HPRIV
set 0x320c5a5b, %r2
mov 0x3, %r1
sllx %r1, 32, %r1
or %r1, %r2, %r2
.word 0x2f400001 ! 1: FBPU fbu,a,pn %fcc0, <label_0x1>
stxa %r2, [%r0] ASI_LSU_CONTROL
ta T_CHANGE_NONHPRIV
.word 0x3d400002 ! 317: FBPULE fbule,a,pn %fcc0, <label_0x2>
splash_hpstate_80_166:
.word 0x8198277b ! 321: WRHPR_HPSTATE_I wrhpr %r0, 0x077b, %hpstate
nop
nop
ta T_CHANGE_HPRIV
mov 0x1, %r11
splash_cmpr_80_169:
sllx %r11, 63, %r11
not %r11, %r11
rd %tick, %r10
#if (defined SPC || defined CMP1)
add %r10, 0x250, %r10
#else
add %r10, 0xc00, %r10
#endif
and %r10, %r11, %r10
wrhpr %r10, %g0, %hsys_tick_cmpr
wrhpr %g0, 0x0, %halt ! HALT
rd %tick, %r10
#if (defined SPC || defined CMP1)
add %r10, 0x200, %r10
#else
add %r10, 0x700, %r10
#endif
and %r10, %r11, %r10
.word 0xb380000a ! 1: WR_STICK_CMPR_REG_R wr %r0, %r10, %-
#if (defined SPC || defined CMP1)
!$EV trig_pc_d(1, expr(@VA(.MAIN.splash_cmpr_80_169)+8 , 16, 16)) -> intp(5,0,6,*,896,*,e3,1)
!$EV trig_pc_d(1, expr((@VA(.MAIN.splash_cmpr_80_169)&0xffffffff)+8 , 16, 16)) -> intp(6,0,2,*,656,*,e3,1)
#endif
wrhpr %g0, 0x0, %halt ! HALT
.word 0x81982dc7 ! 1: WRHPR_HPSTATE_I wrhpr %r0, 0x0dc7, %hpstate
.word 0x81b01021 ! 325: SIAM siam 1
intveclr_80_171:
nop
nop
ta T_CHANGE_HPRIV
setx 0x7bc5695b311f1c52, %r1, %r28
stxa %r28, [%g0] 0x72
wrhpr %g0, 0x6c2, %hpstate ! ta T_CHANGE_NONHPRIV
.word 0x25400001 ! 329: FBPLG fblg,a,pn %fcc0, <label_0x1>
.word 0x9191c001 ! 333: WRPR_PIL_R wrpr %r7, %r1, %pil
.word 0xd23fe08e ! 337: STD_I std %r9, [%r31 + 0x008e]
demap_80_179:
nop
mov 0x80, %g3
ta T_CHANGE_HPRIV
.word 0x13400001 ! 1: FBPE fbe
stxa %g3, [%g3] 0x57
.word 0xe1bfdf20 ! 1: STDFA_R stda %f16, [%r0, %r31]
.word 0xe19fdd40 ! 1: LDDFA_R ldda [%r31, %r0], %f16
.word 0xe1bfde00 ! 1: STDFA_R stda %f16, [%r0, %r31]
stxa %g3, [%g3] 0x5f
.word 0xc09fdc00 ! 1: LDDA_R ldda [%r31, %r0] 0xe0, %r0
.word 0xc1bfdc00 ! 1: STDFA_R stda %f0, [%r0, %r31]
stxa %g3, [%g3] 0x57
.word 0xe1bfdf20 ! 1: STDFA_R stda %f16, [%r0, %r31]
.word 0xc0bfdd40 ! 1: STDA_R stda %r0, [%r31 + %r0] 0xea
stxa %g3, [%g3] 0x5f
stxa %g3, [%g3] 0x5f
wrhpr %g0, 0xddb, %hpstate ! ta T_CHANGE_NONHPRIV
.word 0xd21fe198 ! 341: LDD_I ldd [%r31 + 0x0198], %r9
.word 0xa1902005 ! 345: WRPR_GL_I wrpr %r0, 0x0005, %-
nop
nop
mov 0x1, %r11
splash_cmpr_80_181:
sllx %r11, 63, %r11
not %r11, %r11
rd %tick, %r10
#if (defined SPC || defined CMP1)
add %r10, 0x200, %r10
#else
add %r10, 0x380, %r10
#endif
and %r10, %r11, %r10
rd %tick, %r10
#if (defined SPC || defined CMP1)
add %r10, 0x150, %r10
#else
add %r10, 0x380, %r10
#endif
and %r10, %r11, %r10
.word 0xaf80000a ! 1: WR_TICK_CMPR_REG_R wr %r0, %r10, %-
#if (defined SPC || defined CMP1)
!$EV trig_pc_d(1, expr(@VA(.MAIN.splash_cmpr_80_181)+8 , 16, 16)) -> intp(7,0,15,*,744,*,f2,1)
!$EV trig_pc_d(1, expr((@VA(.MAIN.splash_cmpr_80_181)&0xffffffff)+8 , 16, 16)) -> intp(7,0,9,*,944,*,f2,1)
#endif
wrhpr %g0, 0x0, %halt ! HALT
.word 0x81b01021 ! 349: SIAM siam 1
nop
nop
set 0x9570d56c, %r28 !TTID : 5 (mask2tid(0x80))
#if (defined PORTABLE_CORE || MAX_THREADS == 8)
sethi %hi(0x3800), %r27
andn %r28, %r27, %r28
#ifdef PORTABLE_CORE
! Add CID to vector
ta T_CHANGE_HPRIV
ldxa [%g0]0x63, %r27
sllx %r27, 8, %r27
or %r27, %r28, %r28
#endif
#else
! Add CID IF tid matches
ifelse(5,mask2tid(0x80),`ta T_CHANGE_HPRIV;sethi %hi(0x3800), %r27;andn %r28, %r27, %r28;ldxa [%g0]0x63, %r27;sllx %r27, 8, %r27;or %r27, %r28, %r28 ')
#endif
sethi %hi(0x30000), %r27
andn %r28, %r27, %r28
ta T_CHANGE_HPRIV
ifelse(5,mask2tid(0x80),`.align 16')
stxa %r28, [%g0] 0x73
intvec_80_183:
.word 0x97b284d4 ! 353: FCMPNE32 fcmpne32 %d10, %d20, %r11
splash_tba_80_187:
nop
ta T_CHANGE_PRIV
setx 0x00000000003a0000, %r11, %r12
.word 0x8b90000c ! 357: WRPR_TBA_R wrpr %r0, %r12, %tba
.word 0x2a780001 ! 361: BPCS <illegal instruction>
splash_lsu_80_191:
nop
nop
ta T_CHANGE_HPRIV
set 0x33137e24, %r2
mov 0x5, %r1
sllx %r1, 32, %r1
or %r1, %r2, %r2
stxa %r2, [%r0] ASI_LSU_CONTROL
ta T_CHANGE_NONHPRIV
.word 0x3d400001 ! 365: FBPULE fbule,a,pn %fcc0, <label_0x1>
#if (defined SPC || defined CMP1)
!$EV trig_pc_d(1, expr(@VA(.MAIN.intvec_80_194) , 16, 16)) -> intp(5,0,31,*,728,*,f1,1)
!$EV trig_pc_d(1, expr((@VA(.MAIN.intvec_80_194)&0xffffffff) , 16, 16)) -> intp(1,0,3,*,744,*,f1,1)
#else
nop
nop
set 0x5e30f0fe, %r28 !TTID : 0 (mask2tid(0x80))
#if (defined PORTABLE_CORE || MAX_THREADS == 8)
sethi %hi(0x3800), %r27
andn %r28, %r27, %r28
#ifdef PORTABLE_CORE
! Add CID to vector
ta T_CHANGE_HPRIV
ldxa [%g0]0x63, %r27
sllx %r27, 8, %r27
or %r27, %r28, %r28
#endif
#else
! Add CID IF tid matches
ifelse(0,mask2tid(0x80),`ta T_CHANGE_HPRIV;sethi %hi(0x3800), %r27;andn %r28, %r27, %r28;ldxa [%g0]0x63, %r27;sllx %r27, 8, %r27;or %r27, %r28, %r28 ')
#endif
ifelse(0,mask2tid(0x80),`.align 16')
stxa %r28, [%g0] 0x73
#endif
intvec_80_194:
#if (defined SPC || defined CMP1)
wrhpr %g0, 0x0, %halt ! HALT
#else
ifelse(0,mask2tid(0x80),`wrhpr %g0, 0x0, %halt ! HALT')
#endif
.word 0x93a449cb ! 369: FDIVd fdivd %f48, %f42, %f40
#if (defined SPC || defined CMP1)
!$EV trig_pc_d(1, expr(@VA(.MAIN.intvec_80_196) , 16, 16)) -> intp(0,0,17,*,664,*,c7,1)
!$EV trig_pc_d(1, expr((@VA(.MAIN.intvec_80_196)&0xffffffff) , 16, 16)) -> intp(5,0,18,*,896,*,c7,1)
#else
nop
nop
set 0x5ed04619, %r28 !TTID : 6 (mask2tid(0x80))
#if (defined PORTABLE_CORE || MAX_THREADS == 8)
sethi %hi(0x3800), %r27
andn %r28, %r27, %r28
#ifdef PORTABLE_CORE
! Add CID to vector
ta T_CHANGE_HPRIV
ldxa [%g0]0x63, %r27
sllx %r27, 8, %r27
or %r27, %r28, %r28
#endif
#else
! Add CID IF tid matches
ifelse(6,mask2tid(0x80),`ta T_CHANGE_HPRIV;sethi %hi(0x3800), %r27;andn %r28, %r27, %r28;ldxa [%g0]0x63, %r27;sllx %r27, 8, %r27;or %r27, %r28, %r28 ')
#endif
ifelse(6,mask2tid(0x80),`.align 16')
stxa %r28, [%g0] 0x73
#endif
intvec_80_196:
.word 0x39400001 ! 373: FBPUGE fbuge,a,pn %fcc0, <label_0x1>
frzptr_80_199:
nop
nop
best_set_reg(0x3cb80000+0x1ffc, %r20, %r27)
jmpl %r27, %r27
.word 0x20800002 ! 377: BN bn,a <label_0x2>
.word 0x32800001 ! 381: BNE bne,a <label_0x1>
#if (defined SPC || defined CMP1)
!$EV trig_pc_d(1, expr(@VA(.MAIN.intvec_80_204) , 16, 16)) -> intp(4,0,13,*,664,*,bf,1)
!$EV trig_pc_d(1, expr((@VA(.MAIN.intvec_80_204)&0xffffffff) , 16, 16)) -> intp(3,0,22,*,744,*,bf,1)
#else
nop
nop
set 0x2eb01398, %r28 !TTID : 3 (mask2tid(0x80))
#if (defined PORTABLE_CORE || MAX_THREADS == 8)
sethi %hi(0x3800), %r27
andn %r28, %r27, %r28
#ifdef PORTABLE_CORE
! Add CID to vector
ta T_CHANGE_HPRIV
ldxa [%g0]0x63, %r27
sllx %r27, 8, %r27
or %r27, %r28, %r28
#endif
#else
! Add CID IF tid matches
ifelse(3,mask2tid(0x80),`ta T_CHANGE_HPRIV;sethi %hi(0x3800), %r27;andn %r28, %r27, %r28;ldxa [%g0]0x63, %r27;sllx %r27, 8, %r27;or %r27, %r28, %r28 ')
#endif
ifelse(3,mask2tid(0x80),`.align 16')
stxa %r28, [%g0] 0x73
#endif
intvec_80_204:
.word 0x99b444c4 ! 385: FCMPNE32 fcmpne32 %d48, %d4, %r12
.word 0x87ac0a52 ! 389: FCMPd fcmpd %fcc<n>, %f16, %f18
.word 0xd917c000 ! 393: LDQF_R - [%r31, %r0], %f12
demap_80_211:
nop
mov 0x80, %g3
ta T_CHANGE_HPRIV
stxa %g3, [%g3] 0x5f
stxa %g3, [%g3] 0x57
wrhpr %g0, 0xa1b, %hpstate ! ta T_CHANGE_NONHPRIV
.word 0xd81fe0f8 ! 397: LDD_I ldd [%r31 + 0x00f8], %r12
brcommon1_80_213:
nop
nop
setx common_target, %r12, %r27
lduw [%r27-0], %r12 ! Load common dest into dcache ..
stuw %r12, [%r27-4] ! Load common dest into dcache ..
ba,a .+12
.word 0x99a7c9c0 ! 1: FDIVd fdivd %f62, %f0, %f12
ba,a .+8
jmpl %r27-4, %r27
.word 0xa9b447d0 ! 401: PDIST pdistn %d48, %d16, %d20
nop
nop
set 0x742025c9, %r28 !TTID : 5 (mask2tid(0x80))
#if (defined PORTABLE_CORE || MAX_THREADS == 8)
sethi %hi(0x3800), %r27
andn %r28, %r27, %r28
#ifdef PORTABLE_CORE
! Add CID to vector
ta T_CHANGE_HPRIV
ldxa [%g0]0x63, %r27
sllx %r27, 8, %r27
or %r27, %r28, %r28
#endif
#else
! Add CID IF tid matches
ifelse(5,mask2tid(0x80),`ta T_CHANGE_HPRIV;sethi %hi(0x3800), %r27;andn %r28, %r27, %r28;ldxa [%g0]0x63, %r27;sllx %r27, 8, %r27;or %r27, %r28, %r28 ')
#endif
sethi %hi(0x30000), %r27
andn %r28, %r27, %r28
ta T_CHANGE_HPRIV
ifelse(5,mask2tid(0x80),`.align 16')
stxa %r28, [%g0] 0x73
intvec_80_215:
.word 0x95b284d3 ! 405: FCMPNE32 fcmpne32 %d10, %d50, %r10
.word 0xe81fe1e0 ! 409: LDD_I ldd [%r31 + 0x01e0], %r20
.word 0x91944001 ! 413: WRPR_PIL_R wrpr %r17, %r1, %pil
.word 0xc19fe020 ! 417: LDDFA_I ldda [%r31, 0x0020], %f0
.word 0xe937c000 ! 421: STQF_R - %f20, [%r0, %r31]
.word 0x22cd0001 ! 1: BRZ brz,a,pt %r20,<label_0xd0001>
br_longdelay5_80_224:
#if (defined SPC || defined CMP1)
!$EV trig_pc_d(1, expr((@VA(.MAIN.br_longdelay5_80_224)&0xffffffff) , 16, 16)) -> intp(mask2tid(0x80),0,0,*,736,*,ffffffffffffffff,1)
!$EV trig_pc_d(1, expr((@VA(.MAIN.br_longdelay5_80_224)) , 16, 16)) -> intp(mask2tid(0x80),0,0,*,960,*,ffffffffffffffff,1)
wrhpr %g0, 0x0, %halt ! HALT
#endif
.word 0xe83fe170 ! 425: STD_I std %r20, [%r31 + 0x0170]
#if (defined SPC || defined CMP1)
!$EV trig_pc_d(1, expr(@VA(.MAIN.intvec_80_226) , 16, 16)) -> intp(0,0,20,*,952,*,a8,1)
!$EV trig_pc_d(1, expr((@VA(.MAIN.intvec_80_226)&0xffffffff) , 16, 16)) -> intp(0,0,2,*,760,*,a8,1)
#else
nop
nop
set 0x61f0f3f5, %r28 !TTID : 3 (mask2tid(0x80))
#if (defined PORTABLE_CORE || MAX_THREADS == 8)
sethi %hi(0x3800), %r27
andn %r28, %r27, %r28
#ifdef PORTABLE_CORE
! Add CID to vector
ta T_CHANGE_HPRIV
ldxa [%g0]0x63, %r27
sllx %r27, 8, %r27
or %r27, %r28, %r28
#endif
#else
! Add CID IF tid matches
ifelse(3,mask2tid(0x80),`ta T_CHANGE_HPRIV;sethi %hi(0x3800), %r27;andn %r28, %r27, %r28;ldxa [%g0]0x63, %r27;sllx %r27, 8, %r27;or %r27, %r28, %r28 ')
#endif
ifelse(3,mask2tid(0x80),`.align 16')
stxa %r28, [%g0] 0x73
#endif
intvec_80_226:
.word 0xa1a0c9cc ! 429: FDIVd fdivd %f34, %f12, %f16
jmptr_80_228:
nop
nop
best_set_reg(0xe1a00000, %r20, %r27)
.word 0xb7c6c000 ! 433: JMPL_R jmpl %r27 + %r0, %r27
demap_80_232:
nop
mov 0x80, %g3
ta T_CHANGE_HPRIV
stxa %g3, [%g3] 0x5f
.word 0xe09fda00 ! 1: LDDA_R ldda [%r31, %r0] 0xd0, %r16
.word 0xe1bfdc40 ! 1: STDFA_R stda %f16, [%r0, %r31]
stxa %g3, [%g3] 0x5f
.word 0xc0bfde00 ! 1: STDA_R stda %r0, [%r31 + %r0] 0xf0
.word 0xe09fdf20 ! 1: LDDA_R ldda [%r31, %r0] 0xf9, %r16
stxa %g3, [%g3] 0x5f
wrhpr %g0, 0xd80, %hpstate ! ta T_CHANGE_NONHPRIV
.word 0xda1fe118 ! 437: LDD_I ldd [%r31 + 0x0118], %r13
trapasi_80_235:
nop
mov 0x3d8, %r1 ! (VA for ASI 0x25)
.word 0xdad844a0 ! 441: LDXA_R ldxa [%r1, %r0] 0x25, %r13
.word 0xda57c000 ! 445: LDSH_R ldsh [%r31 + %r0], %r13
.word 0xda27e091 ! 449: STW_I stw %r13, [%r31 + 0x0091]
demap_80_240:
nop
mov 0x80, %g3
ta T_CHANGE_HPRIV
.word 0x28800001 ! 1: BLEU bleu,a <label_0x1>
stxa %g3, [%g3] 0x57
.word 0xe19fdc00 ! 1: LDDFA_R ldda [%r31, %r0], %f16
.word 0xc1bfc2c0 ! 1: STDFA_R stda %f0, [%r0, %r31]
.word 0xc0bfdf00 ! 1: STDA_R stda %r0, [%r31 + %r0] 0xf8
stxa %g3, [%g3] 0x5f
.word 0xc0bfde20 ! 1: STDA_R stda %r0, [%r31 + %r0] 0xf1
wrhpr %g0, 0x589, %hpstate ! ta T_CHANGE_NONHPRIV
.word 0xda1fe148 ! 453: LDD_I ldd [%r31 + 0x0148], %r13
.word 0xdadfc080 ! 457: LDXA_R ldxa [%r31, %r0] 0x04, %r13
.word 0xc30fc000 ! 461: LDXFSR_R ld-fsr [%r31, %r0], %f1
.word 0x91950010 ! 465: WRPR_PIL_R wrpr %r20, %r16, %pil
jmptr_80_253:
nop
nop
best_set_reg(0xe0a00000, %r20, %r27)
.word 0xb7c6c000 ! 469: JMPL_R jmpl %r27 + %r0, %r27
.word 0xda77c000 ! 473: STX_R stx %r13, [%r31 + %r0]
splash_tba_80_259:
nop
ta T_CHANGE_PRIV
setx 0x00000004003a0000, %r11, %r12
.word 0x8b90000c ! 477: WRPR_TBA_R wrpr %r0, %r12, %tba
#if (defined SPC || defined CMP1)
!$EV trig_pc_d(1, expr(@VA(.MAIN.intvec_80_262) , 16, 16)) -> intp(1,0,16,*,720,*,ee,1)
!$EV trig_pc_d(1, expr((@VA(.MAIN.intvec_80_262)&0xffffffff) , 16, 16)) -> intp(4,0,22,*,960,*,ee,1)
#else
nop
nop
set 0x714074be, %r28 !TTID : 4 (mask2tid(0x80))
#if (defined PORTABLE_CORE || MAX_THREADS == 8)
sethi %hi(0x3800), %r27
andn %r28, %r27, %r28
#ifdef PORTABLE_CORE
! Add CID to vector
ta T_CHANGE_HPRIV
ldxa [%g0]0x63, %r27
sllx %r27, 8, %r27
or %r27, %r28, %r28
#endif
#else
! Add CID IF tid matches
ifelse(4,mask2tid(0x80),`ta T_CHANGE_HPRIV;sethi %hi(0x3800), %r27;andn %r28, %r27, %r28;ldxa [%g0]0x63, %r27;sllx %r27, 8, %r27;or %r27, %r28, %r28 ')
#endif
ifelse(4,mask2tid(0x80),`.align 16')
stxa %r28, [%g0] 0x73
#endif
intvec_80_262:
.word 0x39400001 ! 481: FBPUGE fbuge,a,pn %fcc0, <label_0x1>
.word 0xe037e052 ! 485: STH_I sth %r16, [%r31 + 0x0052]
splash_lsu_80_263:
nop
nop
ta T_CHANGE_HPRIV
set 0x9f17df73, %r2
mov 0x7, %r1
sllx %r1, 32, %r1
or %r1, %r2, %r2
.word 0x19400002 ! 1: FBPUGE fbuge
stxa %r2, [%r0] ASI_LSU_CONTROL
.word 0x3d400001 ! 489: FBPULE fbule,a,pn %fcc0, <label_0x1>
.word 0x8d902860 ! 493: WRPR_PSTATE_I wrpr %r0, 0x0860, %pstate
.word 0xc19fe040 ! 497: LDDFA_I ldda [%r31, 0x0040], %f0
splash_tba_80_270:
nop
ta T_CHANGE_PRIV
set 0x120000, %r12
.word 0x8b90000c ! 501: WRPR_TBA_R wrpr %r0, %r12, %tba
.word 0xe11fe0f0 ! 505: LDDF_I ldd [%r31, 0x00f0], %f16
.word 0x8d802000 ! 509: WRFPRS_I wr %r0, 0x0000, %fprs
dvapa_80_277:
nop
nop
ta T_CHANGE_HPRIV
mov 0xce1, %r20
mov 0x1, %r19
sllx %r20, 23, %r20
or %r19, %r20, %r19
stxa %r19, [%g0] ASI_LSU_CONTROL
mov 0x38, %r18
stxa %r31, [%r18]0x58
wrhpr %g0, 0xa98, %hpstate ! ta T_CHANGE_NONHPRIV
.word 0xe03fe0b0 ! 513: STD_I std %r16, [%r31 + 0x00b0]
jmptr_80_279:
nop
nop
best_set_reg(0xe1a00000, %r20, %r27)
.word 0xb7c6c000 ! 517: JMPL_R jmpl %r27 + %r0, %r27
mondo_80_280:
nop
nop
.word 0x87802025 ! 1: WRASI_I wr %r0, 0x0025, %asi
stxa %r12, [%r0+0x3e0] %asi
.word 0x87802016 ! 1: WRASI_I wr %r0, 0x0016, %asi
.word 0x9d940010 ! 521: WRPR_WSTATE_R wrpr %r16, %r16, %wstate
.word 0xe08fc3c0 ! 525: LDUBA_R lduba [%r31, %r0] 0x1e, %r16
iaw_80_284:
nop
nop
ta T_CHANGE_HPRIV
mov 8, %r18
rd %asi, %r12
wr %r0, 0x41, %asi
set sync_thr_counter4, %r23
#ifndef SPC
ldxa [%g0]0x63, %r8
and %r8, 0x38, %r8 ! Core ID
#ifndef PORTABLE_CORE
add %r8, %r23, %r23
#endif
#else
mov 0, %r8
#endif
mov 0x80, %r16
iaw_startwait80_284:
cas [%r23],%g0,%r16 !lock
brz,a %r16, continue_iaw_80_284
mov (~0x80&0xf0), %r16
ld [%r23], %r16
iaw_wait80_284:
brnz %r16, iaw_wait80_284
ld [%r23], %r16
ba iaw_startwait80_284
mov 0x80, %r16
continue_iaw_80_284:
sllx %r16, %r8, %r16 !Mask for my core only
ldxa [0x58]%asi, %r17 !Running_status
wait_for_stat_80_284:
ldxa [0x50]%asi, %r13 !Running_rw
cmp %r13, %r17
bne,a %xcc, wait_for_stat_80_284
ldxa [0x58]%asi, %r17 !Running_status
stxa %r16, [0x68]%asi !Park (W1C)
ldxa [0x50]%asi, %r14 !Running_rw
wait_for_iaw_80_284:
ldxa [0x58]%asi, %r17 !Running_status
cmp %r14, %r17
bne,a %xcc, wait_for_iaw_80_284
ldxa [0x50]%asi, %r14 !Running_rw
iaw_doit80_284:
mov 0x38, %r18
iaw2_80_284:
rdpr %tba, %r19
mov 0x102, %r20
sllx %r20, 5, %r20
add %r20, %r19, %r19
stxa %r19, [%r18]0x50
stxa %r16, [0x60] %asi ! Unpark (W1S)
st %g0, [%r23] !clear lock
wr %r0, %r12, %asi ! restore %asi
wrhpr %g0, 0x7d9, %hpstate ! ta T_CHANGE_NONHPRIV
.word 0xe0bfd100 ! 529: STDA_R stda %r16, [%r31 + %r0] 0x88
.word 0x8d802000 ! 533: WRFPRS_I wr %r0, 0x0000, %fprs
mondo_80_286:
nop
nop
.word 0x87802025 ! 1: WRASI_I wr %r0, 0x0025, %asi
stxa %r19, [%r0+0x3e0] %asi
.word 0x87802020 ! 1: WRASI_I wr %r0, 0x0020, %asi
.word 0x9d94800c ! 537: WRPR_WSTATE_R wrpr %r18, %r12, %wstate
splash_tba_80_288:
nop
ta T_CHANGE_PRIV
setx 0x00000000003a0000, %r11, %r12
.word 0x8b90000c ! 541: WRPR_TBA_R wrpr %r0, %r12, %tba
.word 0x08800001 ! 545: BLEU bleu <label_0x1>
nop
nop
ta T_CHANGE_HPRIV ! macro
donret_80_292:
rd %pc, %r12
mov HIGHVA_HIGHNUM, %r10
sllx %r10, 32, %r10
or %r12, %r10, %r12
add %r12, (donretarg_80_292-donret_80_292), %r12
add %r12, 0x8, %r11 ! nonseq tnpc
wrpr %g0, 0x2, %tl
wrpr %g0, %r12, %tpc
wrpr %g0, %r11, %tnpc
set (0x00e43000 | (32 << 24)), %r13
and %r12, 0xfff, %r14
sllx %r14, 32, %r14
or %r13, %r14, %r20
wrpr %r20, %g0, %tstate
wrhpr %g0, 0x16c9, %htstate
best_set_reg(0x710, %g1, %g2)
wrpr %g0, %g2, %pstate ! rand=0 (80)
ldx [%r12+%r0], %g1
retry
donretarg_80_292:
.word 0x19400001 ! 549: FBPUGE fbuge
brcommon1_80_295:
nop
nop
setx common_target, %r12, %r27
lduw [%r27-0], %r12 ! Load common dest into dcache ..
stuw %r12, [%r27-0] ! Load common dest into dcache ..
ba,a .+12
.word 0xe1e7d920 ! 1: CASA_I casa [%r31] 0xc9, %r0, %r16
ba,a .+8
jmpl %r27-4, %r27
.word 0xa3a449a8 ! 553: FDIVs fdivs %f17, %f8, %f17
nop
nop
ta T_CHANGE_HPRIV
mov 0x0, %r11
splash_cmpr_80_298:
sllx %r11, 63, %r11
not %r11, %r11
rd %tick, %r10
#if (defined SPC || defined CMP1)
add %r10, 0x100, %r10
#else
add %r10, 0xc00, %r10
#endif
and %r10, %r11, %r10
wrhpr %r10, %g0, %hsys_tick_cmpr
rd %tick, %r10
#if (defined SPC || defined CMP1)
add %r10, 0x200, %r10
#else
add %r10, 0xc00, %r10
#endif
and %r10, %r11, %r10
.word 0xb380000a ! 1: WR_STICK_CMPR_REG_R wr %r0, %r10, %-
.word 0x81982d4f ! 1: WRHPR_HPSTATE_I wrhpr %r0, 0x0d4f, %hpstate
.word 0x81b01021 ! 557: SIAM siam 1
.word 0x8980000a ! 561: WRTICK_R wr %r0, %r10, %tick
cancelint_80_302:
rdhpr %halt, %r12
.word 0x85880000 ! 565: ALLCLEAN <illegal instruction>
nop
nop
set 0x7c500453, %r28 !TTID : 4 (mask2tid(0x80))
#if (defined PORTABLE_CORE || MAX_THREADS == 8)
sethi %hi(0x3800), %r27
andn %r28, %r27, %r28
#ifdef PORTABLE_CORE
! Add CID to vector
ta T_CHANGE_HPRIV
ldxa [%g0]0x63, %r27
sllx %r27, 8, %r27
or %r27, %r28, %r28
#endif
#else
! Add CID IF tid matches
ifelse(4,mask2tid(0x80),`ta T_CHANGE_HPRIV;sethi %hi(0x3800), %r27;andn %r28, %r27, %r28;ldxa [%g0]0x63, %r27;sllx %r27, 8, %r27;or %r27, %r28, %r28 ')
#endif
sethi %hi(0x30000), %r27
andn %r28, %r27, %r28
ta T_CHANGE_HPRIV
ifelse(4,mask2tid(0x80),`.align 16')
stxa %r28, [%g0] 0x73
intvec_80_305:
.word 0x95b244c7 ! 569: FCMPNE32 fcmpne32 %d40, %d38, %r10
.word 0xe2cfc380 ! 573: LDSBA_R ldsba [%r31, %r0] 0x1c, %r17
.word 0xa1902005 ! 577: WRPR_GL_I wrpr %r0, 0x0005, %-
nop
nop
set 0x14e0aa95, %r28 !TTID : 2 (mask2tid(0x80))
#if (defined PORTABLE_CORE || MAX_THREADS == 8)
sethi %hi(0x3800), %r27
andn %r28, %r27, %r28
#ifdef PORTABLE_CORE
! Add CID to vector
ta T_CHANGE_HPRIV
ldxa [%g0]0x63, %r27
sllx %r27, 8, %r27
or %r27, %r28, %r28
#endif
#else
! Add CID IF tid matches
ifelse(2,mask2tid(0x80),`ta T_CHANGE_HPRIV;sethi %hi(0x3800), %r27;andn %r28, %r27, %r28;ldxa [%g0]0x63, %r27;sllx %r27, 8, %r27;or %r27, %r28, %r28 ')
#endif
sethi %hi(0x30000), %r27
andn %r28, %r27, %r28
ta T_CHANGE_HPRIV
ifelse(2,mask2tid(0x80),`.align 16')
stxa %r28, [%g0] 0x73
intvec_80_309:
.word 0x39400001 ! 581: FBPUGE fbuge,a,pn %fcc0, <label_0x1>
trapasi_80_313:
nop
mov 0x30, %r1 ! (VA for ASI 0x5b)
.word 0xe2d84b60 ! 585: LDXA_R ldxa [%r1, %r0] 0x5b, %r17
.word 0xe277e1b8 ! 589: STX_I stx %r17, [%r31 + 0x01b8]
iaw_80_317:
nop
nop
ta T_CHANGE_HPRIV
mov 8, %r18
rd %asi, %r12
wr %r0, 0x41, %asi
set sync_thr_counter4, %r23
#ifndef SPC
ldxa [%g0]0x63, %r8
and %r8, 0x38, %r8 ! Core ID
#ifndef PORTABLE_CORE
add %r8, %r23, %r23
#endif
#else
mov 0, %r8
#endif
mov 0x80, %r16
iaw_startwait80_317:
cas [%r23],%g0,%r16 !lock
brz,a %r16, continue_iaw_80_317
mov (~0x80&0xf0), %r16
ld [%r23], %r16
iaw_wait80_317:
brnz %r16, iaw_wait80_317
ld [%r23], %r16
ba iaw_startwait80_317
mov 0x80, %r16
continue_iaw_80_317:
sllx %r16, %r8, %r16 !Mask for my core only
ldxa [0x58]%asi, %r17 !Running_status
wait_for_stat_80_317:
ldxa [0x50]%asi, %r13 !Running_rw
cmp %r13, %r17
bne,a %xcc, wait_for_stat_80_317
ldxa [0x58]%asi, %r17 !Running_status
stxa %r16, [0x68]%asi !Park (W1C)
ldxa [0x50]%asi, %r14 !Running_rw
wait_for_iaw_80_317:
ldxa [0x58]%asi, %r17 !Running_status
cmp %r14, %r17
bne,a %xcc, wait_for_iaw_80_317
ldxa [0x50]%asi, %r14 !Running_rw
iaw_doit80_317:
mov 0x38, %r18
iaw3_80_317:
setx vahole_target1, %r20, %r19
or %r19, 0x1, %r19
stxa %r19, [%r18]0x50
stxa %r16, [0x60] %asi ! Unpark (W1S)
st %g0, [%r23] !clear lock
wr %r0, %r12, %asi ! restore %asi
wrhpr %g0, 0x159, %hpstate ! ta T_CHANGE_NONHPRIV
.word 0xe19fdd40 ! 593: LDDFA_R ldda [%r31, %r0], %f16
.word 0x8d9033db ! 597: WRPR_PSTATE_I wrpr %r0, 0x13db, %pstate
splash_lsu_80_322:
nop
nop
ta T_CHANGE_HPRIV
set 0xf123aa70, %r2
mov 0x6, %r1
sllx %r1, 32, %r1
or %r1, %r2, %r2
.word 0x03400001 ! 1: FBPNE fbne
stxa %r2, [%r0] ASI_LSU_CONTROL
.word 0x3d400001 ! 601: FBPULE fbule,a,pn %fcc0, <label_0x1>
.word 0x8980000a ! 605: WRTICK_R wr %r0, %r10, %tick
.word 0xe3e7d060 ! 609: CASA_I casa [%r31] 0x83, %r0, %r17
jmptr_80_328:
nop
nop
best_set_reg(0xe0a00000, %r20, %r27)
.word 0xb7c6c000 ! 613: JMPL_R jmpl %r27 + %r0, %r27
intveclr_80_330:
nop
nop
ta T_CHANGE_HPRIV
setx 0x4725f331fd10524f, %r1, %r28
stxa %r28, [%g0] 0x72
wrhpr %g0, 0xa52, %hpstate ! ta T_CHANGE_NONHPRIV
.word 0x05400001 ! 617: FBPLG fblg
pmu_80_332:
nop
nop
setx 0xffffffb4ffffffae, %g1, %g7
.word 0xa3800007 ! 621: WR_PERF_COUNTER_R wr %r0, %r7, %-
.word 0x87802055 ! 625: WRASI_I wr %r0, 0x0055, %asi
splash_tba_80_337:
nop
ta T_CHANGE_PRIV
setx 0x00000004003a0000, %r11, %r12
.word 0x8b90000c ! 629: WRPR_TBA_R wrpr %r0, %r12, %tba
#if (defined SPC || defined CMP1)
!$EV trig_pc_d(1, expr(@VA(.MAIN.intvec_80_338) , 16, 16)) -> intp(1,0,27,*,744,*,90,1)
!$EV trig_pc_d(1, expr((@VA(.MAIN.intvec_80_338)&0xffffffff) , 16, 16)) -> intp(7,0,1,*,640,*,90,1)
#else
nop
nop
set 0xe40650e, %r28 !TTID : 5 (mask2tid(0x80))
#if (defined PORTABLE_CORE || MAX_THREADS == 8)
sethi %hi(0x3800), %r27
andn %r28, %r27, %r28
#ifdef PORTABLE_CORE
! Add CID to vector
ta T_CHANGE_HPRIV
ldxa [%g0]0x63, %r27
sllx %r27, 8, %r27
or %r27, %r28, %r28
#endif
#else
! Add CID IF tid matches
ifelse(5,mask2tid(0x80),`ta T_CHANGE_HPRIV;sethi %hi(0x3800), %r27;andn %r28, %r27, %r28;ldxa [%g0]0x63, %r27;sllx %r27, 8, %r27;or %r27, %r28, %r28 ')
#endif
ifelse(5,mask2tid(0x80),`.align 16')
stxa %r28, [%g0] 0x73
#endif
intvec_80_338:
.word 0x91a4c9d4 ! 633: FDIVd fdivd %f50, %f20, %f8
br_longdelay3_80_340:
nop
not %g0, %r27
jmpl %r27+0, %r27
.word 0x819829df ! 637: WRHPR_HPSTATE_I wrhpr %r0, 0x09df, %hpstate
intveclr_80_343:
nop
nop
ta T_CHANGE_HPRIV
setx 0x1ad79b37074e8571, %r1, %r28
stxa %r28, [%g0] 0x72
wrhpr %g0, 0xfc0, %hpstate ! ta T_CHANGE_NONHPRIV
.word 0x05400001 ! 641: FBPLG fblg
ibp_80_344:
nop
nop
.word 0x20800001 ! 645: BN bn,a <label_0x1>
.word 0xc32fc000 ! 649: STXFSR_R st-sfr %f1, [%r0, %r31]
.word 0xd497df00 ! 653: LDUHA_R lduha [%r31, %r0] 0xf8, %r10
jmptr_80_353:
nop
nop
best_set_reg(0xe1a00000, %r20, %r27)
.word 0xb7c6c000 ! 657: JMPL_R jmpl %r27 + %r0, %r27
.word 0xd497d160 ! 661: LDUHA_R lduha [%r31, %r0] 0x8b, %r10
.word 0xc19fe000 ! 665: LDDFA_I ldda [%r31, 0x0000], %f0
.word 0xd49fc280 ! 1: LDDA_R ldda [%r31, %r0] 0x14, %r10
.word 0xd43fe140 ! 1: STD_I std %r10, [%r31 + 0x0140]
mov 0xb2, %r30
.word 0x91d0001e ! 669: Tcc_R ta icc_or_xcc, %r0 + %r30
demap_80_359:
nop
mov 0x80, %g3
ta T_CHANGE_HPRIV
stxa %g3, [%g3] 0x5f
.word 0xc19fdb40 ! 1: LDDFA_R ldda [%r31, %r0], %f0
.word 0xc19fdc40 ! 1: LDDFA_R ldda [%r31, %r0], %f0
.word 0xe0bfde20 ! 1: STDA_R stda %r16, [%r31 + %r0] 0xf1
stxa %g3, [%g3] 0x5f
.word 0xc1bfdb40 ! 1: STDFA_R stda %f0, [%r0, %r31]
.word 0xc0bfdc40 ! 1: STDA_R stda %r0, [%r31 + %r0] 0xe2
.word 0xe19fdb40 ! 1: LDDFA_R ldda [%r31, %r0], %f16
stxa %g3, [%g3] 0x5f
.word 0xc09fdd40 ! 1: LDDA_R ldda [%r31, %r0] 0xea, %r0
stxa %g3, [%g3] 0x5f
wrhpr %g0, 0x7c1, %hpstate ! ta T_CHANGE_NONHPRIV
.word 0xd41fe043 ! 673: LDD_I ldd [%r31 + 0x0043], %r10
memptr_80_362:
set 0x60540000, %r31
.word 0x8584a315 ! 677: WRCCR_I wr %r18, 0x0315, %ccr
jmptr_80_363:
nop
nop
best_set_reg(0xe0a00000, %r20, %r27)
.word 0xb7c6c000 ! 681: JMPL_R jmpl %r27 + %r0, %r27
jmptr_80_366:
nop
nop
best_set_reg(0xe1a00000, %r20, %r27)
.word 0xb7c6c000 ! 685: JMPL_R jmpl %r27 + %r0, %r27
memptr_80_369:
set user_data_start, %r31
.word 0x8582b23b ! 689: WRCCR_I wr %r10, 0x123b, %ccr
nop
nop
ta T_CHANGE_HPRIV ! macro
donret_80_370:
rd %pc, %r12
mov HIGHVA_HIGHNUM, %r10
sllx %r10, 32, %r10
or %r12, %r10, %r12
add %r12, (donretarg_80_370-donret_80_370+4), %r12
add %r12, 0x4, %r11 ! seq tnpc
wrpr %g0, 0x1, %tl
wrpr %g0, %r12, %tpc
wrpr %g0, %r11, %tnpc
set (0x005e0300 | (22 << 24)), %r13
and %r12, 0xfff, %r14
sllx %r14, 32, %r14
or %r13, %r14, %r20
wrpr %r20, %g0, %tstate
wrhpr %g0, 0x18b, %htstate
wrhpr %g0, 0x542, %hpstate ! rand=1 (80)
ldx [%r12+%r0], %g1
retry
donretarg_80_370:
.word 0xd46fe1df ! 693: LDSTUB_I ldstub %r10, [%r31 + 0x01df]
brcommon3_80_371:
nop
nop
setx common_target, %r12, %r27
lduw [%r27-0], %r12 ! Load common dest into dcache ..
stuw %r12, [%r27-0] ! Load common dest into dcache ..
ba,a .+12
.word 0xd537e170 ! 1: STQF_I - %f10, [0x0170, %r31]
ba,a .+8
jmpl %r27-0, %r27
.word 0xc32fe020 ! 697: STXFSR_I st-sfr %f1, [0x0020, %r31]
.word 0xd477c000 ! 701: STX_R stx %r10, [%r31 + %r0]
.word 0xd537c000 ! 705: STQF_R - %f10, [%r0, %r31]
.word 0xc32fc000 ! 709: STXFSR_R st-sfr %f1, [%r0, %r31]
.word 0x9194800a ! 713: WRPR_PIL_R wrpr %r18, %r10, %pil
.word 0xd48008a0 ! 717: LDUWA_R lduwa [%r0, %r0] 0x45, %r10
.word 0xd527e13c ! 721: STF_I st %f10, [0x013c, %r31]
intveclr_80_383:
nop
nop
ta T_CHANGE_HPRIV
setx 0xde8d62170024e1af, %r1, %r28
stxa %r28, [%g0] 0x72
.word 0x05400001 ! 725: FBPLG fblg
demap_80_386:
nop
mov 0x80, %g3
ta T_CHANGE_HPRIV
stxa %g3, [%g3] 0x5f
stxa %g3, [%g3] 0x57
.word 0xc19fc2c0 ! 1: LDDFA_R ldda [%r31, %r0], %f0
.word 0xc0bfda00 ! 1: STDA_R stda %r0, [%r31 + %r0] 0xd0
.word 0xc19fdb20 ! 1: LDDFA_R ldda [%r31, %r0], %f0
stxa %g3, [%g3] 0x57
wrhpr %g0, 0xa42, %hpstate ! ta T_CHANGE_NONHPRIV
.word 0xd41fe0f3 ! 729: LDD_I ldd [%r31 + 0x00f3], %r10
.word 0xd4bfe1a2 ! 733: STDA_I stda %r10, [%r31 + 0x01a2] %asi
memptr_80_389:
set 0x60140000, %r31
.word 0x8582b020 ! 737: WRCCR_I wr %r10, 0x1020, %ccr
.word 0x8980000a ! 741: WRTICK_R wr %r0, %r10, %tick
.word 0xc32fc000 ! 745: STXFSR_R st-sfr %f1, [%r0, %r31]
splash_lsu_80_393:
nop
nop
ta T_CHANGE_HPRIV
set 0x6e538027, %r2
mov 0x2, %r1
sllx %r1, 32, %r1
or %r1, %r2, %r2
stxa %r2, [%r0] ASI_LSU_CONTROL
.word 0x3d400001 ! 749: FBPULE fbule,a,pn %fcc0, <label_0x1>
br_longdelay4_80_395:
nop
not %g0, %r27
jmpl %r27+0, %r27
.word 0x9d902000 ! 753: WRPR_WSTATE_I wrpr %r0, 0x0000, %wstate
brcommon3_80_399:
nop
nop
setx common_target, %r12, %r27
lduw [%r27-4], %r12 ! Load common dest into dcache ..
stuw %r12, [%r27-0] ! Load common dest into dcache ..
ba,a .+12
.word 0xd46fe110 ! 1: LDSTUB_I ldstub %r10, [%r31 + 0x0110]
ba,a .+8
jmpl %r27-0, %r27
.word 0xd5e7c080 ! 757: CASA_I casa [%r31] 0x 4, %r0, %r10
.word 0xc30fc000 ! 761: LDXFSR_R ld-fsr [%r31, %r0], %f1
nop
nop
ta T_CHANGE_HPRIV
mov 0x1, %r11
splash_cmpr_80_403:
sllx %r11, 63, %r11
not %r11, %r11
rd %tick, %r10
#if (defined SPC || defined CMP1)
add %r10, 0x200, %r10
#else
add %r10, 0x550, %r10
#endif
and %r10, %r11, %r10
wrhpr %r10, %g0, %hsys_tick_cmpr
wrhpr %g0, 0x0, %halt ! HALT
rd %tick, %r10
#if (defined SPC || defined CMP1)
add %r10, 0x200, %r10
#else
add %r10, 0xc00, %r10
#endif
and %r10, %r11, %r10
.word 0xb380000a ! 1: WR_STICK_CMPR_REG_R wr %r0, %r10, %-
#if (defined SPC || defined CMP1)
!$EV trig_pc_d(1, expr(@VA(.MAIN.splash_cmpr_80_403)+8 , 16, 16)) -> intp(5,0,20,*,984,*,c9,1)
!$EV trig_pc_d(1, expr((@VA(.MAIN.splash_cmpr_80_403)&0xffffffff)+8 , 16, 16)) -> intp(3,0,10,*,960,*,c9,1)
#endif
wrhpr %g0, 0x0, %halt ! HALT
.word 0x81982755 ! 1: WRHPR_HPSTATE_I wrhpr %r0, 0x0755, %hpstate
.word 0x81b01021 ! 765: SIAM siam 1
memptr_80_407:
set 0x60140000, %r31
.word 0x8582353d ! 769: WRCCR_I wr %r8, 0x153d, %ccr
br_badelay3_80_410:
.word 0x20800001 ! 1: BN bn,a <label_0x1>
.word 0xdb64d6bd ! Random illegal ?
.word 0xe9148013 ! 1: LDQF_R - [%r18, %r19], %f20
.word 0x97a50830 ! 773: FADDs fadds %f20, %f16, %f11
splash_lsu_80_411:
nop
nop
ta T_CHANGE_HPRIV
set 0x7199ff8c, %r2
mov 0x7, %r1
sllx %r1, 32, %r1
or %r1, %r2, %r2
stxa %r2, [%r0] ASI_LSU_CONTROL
ta T_CHANGE_NONHPRIV
.word 0x3d400001 ! 777: FBPULE fbule,a,pn %fcc0, <label_0x1>
.word 0x26800001 ! 781: BL bl,a <label_0x1>
pmu_80_417:
nop
nop
ta T_CHANGE_PRIV
setx 0xffffffb2ffffffa1, %g1, %g7
.word 0xa3800007 ! 785: WR_PERF_COUNTER_R wr %r0, %r7, %-
.word 0x81460000 ! 789: RD_STICK_REG stbar
demap_80_421:
nop
mov 0x80, %g3
ta T_CHANGE_HPRIV
.word 0x32800001 ! 1: BNE bne,a <label_0x1>
stxa %g3, [%g3] 0x57
.word 0xe0bfdc00 ! 1: STDA_R stda %r16, [%r31 + %r0] 0xe0
.word 0xc1bfdd40 ! 1: STDFA_R stda %f0, [%r0, %r31]
stxa %g3, [%g3] 0x5f
.word 0xc19fdc40 ! 1: LDDFA_R ldda [%r31, %r0], %f0
stxa %g3, [%g3] 0x57
.word 0xc09fdd40 ! 1: LDDA_R ldda [%r31, %r0] 0xea, %r0
stxa %g3, [%g3] 0x5f
.word 0xe0bfdb40 ! 1: STDA_R stda %r16, [%r31 + %r0] 0xda
wrhpr %g0, 0x542, %hpstate ! ta T_CHANGE_NONHPRIV
.word 0xd21fe178 ! 793: LDD_I ldd [%r31 + 0x0178], %r9
memptr_80_424:
set 0x60540000, %r31
.word 0x8584a135 ! 797: WRCCR_I wr %r18, 0x0135, %ccr
nop
nop
ta T_CHANGE_PRIV
wrpr %g0, %g0, %gl
nop
nop
.text
setx join_lbl_0_0, %g1, %g2
jmp %g2
nop
fork_lbl_0_7:
#ifndef PORTABLE_CORE
#define SPU_8
#endif
#define MAX_TIMEOUT 0x002
#define WAIT_LOOP 0x100
.text
.global _t2_main
_t2_main:
setx 0x0000deadbeefbad0, %l5, %l4
!# Switch to hpriv mode
ta T_CHANGE_HPRIV
set 0xb65, %g3
stxa %g3, [%g0] ASI_SPARC_PWR_MGMT
! Set up for PMU
set 0x29f95cf6, %g2
wr %g2, %g0, %pcr
setx 0xffffffbdffffffaa, %g2, %g7
wr %g7, %g0, %pic
! Get core ID & offset
#ifndef PORTABLE_CORE
ldxa [%g0]0x63, %o1
srlx %o1, 3, %o1
sllx %o1, 20, %o1 !! %o1 has core ID offset
#else
mov %g0, %o1
#endif
or %g0, 0x0, %g2 !# Operation Step
or %g0, 0x0, %g4 !# Operand Step
!# Execute Main Diag ..
!# Write address of data region to load from in MA_PA reg, and check
setx _t2_ma_operands, %g6, %l7
#ifdef SPU_8
#if (MAX_THREADS > 8)
! Add core ID offset
or %l7, %o1, %l7
#endif
#endif
add %l7, 14, %l7 !# _t2_WARNING : Misaligned _t2_address
add %l7, %g4, %l7
wr %g0, 0x40, %asi
stxa %l7, [%g0 + 0x88] %asi
_t2_ma_load:
!# Write MAMEM address, start at 0
or %g0, 0x0, %l2
stxa %l2, [%g0 + 0x90] %asi
!# write MA_CTL
set 0x0002002d, %l1
mov 6, %g7
sllx %g7, 18, %g7
or %l1, %g7, %l1
stxa %l1, [%g0 + 0x80] %asi !# LOAD
!# setup mask to check for INVOP
or %g0, 0x1, %l2
sllx %l2, 21, %l2
#! Try MA_SYNC operation...
_t2_wait:
ldxa [%g0 + 0xA0] %asi, %l1
ldxa [%g0 + 0x80] %asi, %l1
andcc %l1, %l2, %l1
bne,pn %xcc, _t2_fail
nop
_t2_loop_0:
wrpr %g0, 51, %pstate
!# write NPRIME
setx 0x827d8c38d332d95b, %g7, %l2
stxa %l2, [%g0 + 0x98] %asi
setx _t2_ma_operations, %g6, %l7
#ifdef SPU_8
#if (MAX_THREADS > 8)
! Add core ID offset
or %l7, %o1, %l7
#endif
#endif
or %g0, 11, %i0 !# OPSELECT
umul %i0, 16, %i0
add %i0, %g2, %i0
!# write MA_ADDR
ldx [%l7 + %i0], %l1
stxa %l1, [%g0 + 0x90] %asi
!# write MA_CTL
add %i0, 8, %i0
ldx [%l7 + %i0], %l1
stxa %l1, [%g0 + 0x80] %asi !# OPERATION
!# setup mask to check for INVOP
or %g0, 0x1, %l2
sllx %l2, 21, %l2
#! Try MA_SYNC operation...
_t2_wait2_0:
ldxa [%g0 + 0xA0] %asi, %l1
ldxa [%g0 + 0x98] %asi, %l1 !# MA PA
ldxa [%g0 + 0x90] %asi, %l1 !# MA Addr
ldxa [%g0 + 0x88] %asi, %l1 !# MA PA
ldxa [%g0 + 0x80] %asi, %l1 !# MA CTL
andcc %l1, %l2, %l1
bne,pn %xcc, _t2_fail
nop
rdhpr %halt, %g7
wrpr %g0, 0x55, %pstate
add %g2, 288, %g2 !# Operation Step (16 * # _t2_of _t2_operations _t2_in _t2_queue)
add %g4, 164, %g4 !# Operand Step (_t2_always 164)
_t2_loop_1:
wrpr %g0, 0x65, %pstate
!# write NPRIME
setx 0x7be327a252185a3a, %g7, %l2
stxa %l2, [%g0 + 0x98] %asi
setx _t2_ma_operations, %g6, %l7
#ifdef SPU_8
#if (MAX_THREADS > 8)
! Add core ID offset
or %l7, %o1, %l7
#endif
#endif
or %g0, 11, %i0 !# OPSELECT
umul %i0, 16, %i0
add %i0, %g2, %i0
!# write MA_ADDR
ldx [%l7 + %i0], %l1
stxa %l1, [%g0 + 0x90] %asi
!# write MA_CTL
add %i0, 8, %i0
ldx [%l7 + %i0], %l1
stxa %l1, [%g0 + 0x80] %asi !# OPERATION
!# setup mask to check for INVOP
or %g0, 0x1, %l2
sllx %l2, 21, %l2
#! Try MA_SYNC operation...
_t2_wait2_1:
ldxa [%g0 + 0xA0] %asi, %l1
ldxa [%g0 + 0x98] %asi, %l1 !# MA PA
ldxa [%g0 + 0x90] %asi, %l1 !# MA Addr
ldxa [%g0 + 0x88] %asi, %l1 !# MA PA
ldxa [%g0 + 0x80] %asi, %l1 !# MA CTL
andcc %l1, %l2, %l1
bne,pn %xcc, _t2_fail
nop
rdhpr %halt, %g7
wrpr %g0, 0x85, %pstate
add %g2, 288, %g2 !# Operation Step (16 * # _t2_of _t2_operations _t2_in _t2_queue)
add %g4, 164, %g4 !# Operand Step (_t2_always 164)
_t2_loop_2:
wrpr %g0, 0xa2, %pstate
!# write NPRIME
setx 0xca7ef8e4cfe59401, %g7, %l2
stxa %l2, [%g0 + 0x98] %asi
setx _t2_ma_operations, %g6, %l7
#ifdef SPU_8
#if (MAX_THREADS > 8)
! Add core ID offset
or %l7, %o1, %l7
#endif
#endif
or %g0, 11, %i0 !# OPSELECT
umul %i0, 16, %i0
add %i0, %g2, %i0
!# write MA_ADDR
ldx [%l7 + %i0], %l1
stxa %l1, [%g0 + 0x90] %asi
!# write MA_CTL
add %i0, 8, %i0
ldx [%l7 + %i0], %l1
stxa %l1, [%g0 + 0x80] %asi !# OPERATION
!# setup mask to check for INVOP
or %g0, 0x1, %l2
sllx %l2, 21, %l2
#! Try MA_SYNC operation...
_t2_wait2_2:
ldxa [%g0 + 0xA0] %asi, %l1
ldxa [%g0 + 0x98] %asi, %l1 !# MA PA
ldxa [%g0 + 0x90] %asi, %l1 !# MA Addr
ldxa [%g0 + 0x88] %asi, %l1 !# MA PA
ldxa [%g0 + 0x80] %asi, %l1 !# MA CTL
andcc %l1, %l2, %l1
bne,pn %xcc, _t2_fail
nop
rdhpr %halt, %g7
wrpr %g0, 0xe4, %pstate
add %g2, 288, %g2 !# Operation Step (16 * # _t2_of _t2_operations _t2_in _t2_queue)
add %g4, 164, %g4 !# Operand Step (_t2_always 164)
_t2_loop_3:
wrpr %g0, 0x90, %pstate
!# write NPRIME
setx 0xbffc62bac3431abc, %g7, %l2
stxa %l2, [%g0 + 0x98] %asi
setx _t2_ma_operations, %g6, %l7
#ifdef SPU_8
#if (MAX_THREADS > 8)
! Add core ID offset
or %l7, %o1, %l7
#endif
#endif
or %g0, 10, %i0 !# OPSELECT
umul %i0, 16, %i0
add %i0, %g2, %i0
!# write MA_ADDR
ldx [%l7 + %i0], %l1
stxa %l1, [%g0 + 0x90] %asi
!# write MA_CTL
add %i0, 8, %i0
ldx [%l7 + %i0], %l1
stxa %l1, [%g0 + 0x80] %asi !# OPERATION
!# setup mask to check for INVOP
or %g0, 0x1, %l2
sllx %l2, 21, %l2
#! Try MA_SYNC operation...
_t2_wait2_3:
ldxa [%g0 + 0xA0] %asi, %l1
ldxa [%g0 + 0x98] %asi, %l1 !# MA PA
ldxa [%g0 + 0x90] %asi, %l1 !# MA Addr
ldxa [%g0 + 0x88] %asi, %l1 !# MA PA
ldxa [%g0 + 0x80] %asi, %l1 !# MA CTL
andcc %l1, %l2, %l1
bne,pn %xcc, _t2_fail
nop
rdhpr %halt, %g7
wrpr %g0, 0xd3, %pstate
add %g2, 288, %g2 !# Operation Step (16 * # _t2_of _t2_operations _t2_in _t2_queue)
add %g4, 164, %g4 !# Operand Step (_t2_always 164)
_t2_loop_4:
wrpr %g0, 22, %pstate
!# write NPRIME
setx 0x6d10317535eb7c63, %g7, %l2
stxa %l2, [%g0 + 0x98] %asi
setx _t2_ma_operations, %g6, %l7
#ifdef SPU_8
#if (MAX_THREADS > 8)
! Add core ID offset
or %l7, %o1, %l7
#endif
#endif
or %g0, 3, %i0 !# OPSELECT
umul %i0, 16, %i0
add %i0, %g2, %i0
!# write MA_ADDR
ldx [%l7 + %i0], %l1
stxa %l1, [%g0 + 0x90] %asi
!# write MA_CTL
add %i0, 8, %i0
ldx [%l7 + %i0], %l1
stxa %l1, [%g0 + 0x80] %asi !# OPERATION
!# setup mask to check for INVOP
or %g0, 0x1, %l2
sllx %l2, 21, %l2
#! Try MA_SYNC operation...
_t2_wait2_4:
ldxa [%g0 + 0xA0] %asi, %l1
ldxa [%g0 + 0x98] %asi, %l1 !# MA PA
ldxa [%g0 + 0x90] %asi, %l1 !# MA Addr
ldxa [%g0 + 0x88] %asi, %l1 !# MA PA
ldxa [%g0 + 0x80] %asi, %l1 !# MA CTL
andcc %l1, %l2, %l1
bne,pn %xcc, _t2_fail
nop
rdhpr %halt, %g7
wrpr %g0, 33, %pstate
add %g2, 288, %g2 !# Operation Step (16 * # _t2_of _t2_operations _t2_in _t2_queue)
add %g4, 164, %g4 !# Operand Step (_t2_always 164)
_t2_loop_5:
wrpr %g0, 0x74, %pstate
!# write NPRIME
setx 0x01b275ac9a8c8995, %g7, %l2
stxa %l2, [%g0 + 0x98] %asi
setx _t2_ma_operations, %g6, %l7
#ifdef SPU_8
#if (MAX_THREADS > 8)
! Add core ID offset
or %l7, %o1, %l7
#endif
#endif
or %g0, 8, %i0 !# OPSELECT
umul %i0, 16, %i0
add %i0, %g2, %i0
!# write MA_ADDR
ldx [%l7 + %i0], %l1
stxa %l1, [%g0 + 0x90] %asi
!# write MA_CTL
add %i0, 8, %i0
ldx [%l7 + %i0], %l1
stxa %l1, [%g0 + 0x80] %asi !# OPERATION
!# setup mask to check for INVOP
or %g0, 0x1, %l2
sllx %l2, 21, %l2
#! Try MA_SYNC operation...
_t2_wait2_5:
ldxa [%g0 + 0xA0] %asi, %l1
ldxa [%g0 + 0x98] %asi, %l1 !# MA PA
ldxa [%g0 + 0x90] %asi, %l1 !# MA Addr
ldxa [%g0 + 0x88] %asi, %l1 !# MA PA
ldxa [%g0 + 0x80] %asi, %l1 !# MA CTL
andcc %l1, %l2, %l1
bne,pn %xcc, _t2_fail
nop
rdhpr %halt, %g7
wrpr %g0, 0xb4, %pstate
add %g2, 288, %g2 !# Operation Step (16 * # _t2_of _t2_operations _t2_in _t2_queue)
add %g4, 164, %g4 !# Operand Step (_t2_always 164)
_t2_loop_6:
wrpr %g0, 0xe6, %pstate
!# write NPRIME
setx 0x5f0e832d944b2da6, %g7, %l2
stxa %l2, [%g0 + 0x98] %asi
setx _t2_ma_operations, %g6, %l7
#ifdef SPU_8
#if (MAX_THREADS > 8)
! Add core ID offset
or %l7, %o1, %l7
#endif
#endif
or %g0, 2, %i0 !# OPSELECT
umul %i0, 16, %i0
add %i0, %g2, %i0
!# write MA_ADDR
ldx [%l7 + %i0], %l1
stxa %l1, [%g0 + 0x90] %asi
!# write MA_CTL
add %i0, 8, %i0
ldx [%l7 + %i0], %l1
stxa %l1, [%g0 + 0x80] %asi !# OPERATION
!# setup mask to check for INVOP
or %g0, 0x1, %l2
sllx %l2, 21, %l2
#! Try MA_SYNC operation...
_t2_wait2_6:
ldxa [%g0 + 0xA0] %asi, %l1
ldxa [%g0 + 0x98] %asi, %l1 !# MA PA
ldxa [%g0 + 0x90] %asi, %l1 !# MA Addr
ldxa [%g0 + 0x88] %asi, %l1 !# MA PA
ldxa [%g0 + 0x80] %asi, %l1 !# MA CTL
andcc %l1, %l2, %l1
bne,pn %xcc, _t2_fail
nop
rdhpr %halt, %g7
wrpr %g0, 0xe0, %pstate
add %g2, 288, %g2 !# Operation Step (16 * # _t2_of _t2_operations _t2_in _t2_queue)
add %g4, 164, %g4 !# Operand Step (_t2_always 164)
_t2_loop_7:
wrpr %g0, 0x84, %pstate
!# write NPRIME
setx 0x3b8592276c6f9848, %g7, %l2
stxa %l2, [%g0 + 0x98] %asi
setx _t2_ma_operations, %g6, %l7
#ifdef SPU_8
#if (MAX_THREADS > 8)
! Add core ID offset
or %l7, %o1, %l7
#endif
#endif
or %g0, 8, %i0 !# OPSELECT
umul %i0, 16, %i0
add %i0, %g2, %i0
!# write MA_ADDR
ldx [%l7 + %i0], %l1
stxa %l1, [%g0 + 0x90] %asi
!# write MA_CTL
add %i0, 8, %i0
ldx [%l7 + %i0], %l1
stxa %l1, [%g0 + 0x80] %asi !# OPERATION
!# setup mask to check for INVOP
or %g0, 0x1, %l2
sllx %l2, 21, %l2
#! Try MA_SYNC operation...
_t2_wait2_7:
ldxa [%g0 + 0xA0] %asi, %l1
ldxa [%g0 + 0x98] %asi, %l1 !# MA PA
ldxa [%g0 + 0x90] %asi, %l1 !# MA Addr
ldxa [%g0 + 0x88] %asi, %l1 !# MA PA
ldxa [%g0 + 0x80] %asi, %l1 !# MA CTL
andcc %l1, %l2, %l1
bne,pn %xcc, _t2_fail
nop
rdhpr %halt, %g7
wrpr %g0, 0x90, %pstate
add %g2, 288, %g2 !# Operation Step (16 * # _t2_of _t2_operations _t2_in _t2_queue)
add %g4, 164, %g4 !# Operand Step (_t2_always 164)
_t2_loop_8:
wrpr %g0, 0x57, %pstate
!# write NPRIME
setx 0x14439953d1d9a405, %g7, %l2
stxa %l2, [%g0 + 0x98] %asi
setx _t2_ma_operations, %g6, %l7
#ifdef SPU_8
#if (MAX_THREADS > 8)
! Add core ID offset
or %l7, %o1, %l7
#endif
#endif
or %g0, 7, %i0 !# OPSELECT
umul %i0, 16, %i0
add %i0, %g2, %i0
!# write MA_ADDR
ldx [%l7 + %i0], %l1
stxa %l1, [%g0 + 0x90] %asi
!# write MA_CTL
add %i0, 8, %i0
ldx [%l7 + %i0], %l1
stxa %l1, [%g0 + 0x80] %asi !# OPERATION
!# setup mask to check for INVOP
or %g0, 0x1, %l2
sllx %l2, 21, %l2
#! Try MA_SYNC operation...
_t2_wait2_8:
ldxa [%g0 + 0xA0] %asi, %l1
ldxa [%g0 + 0x98] %asi, %l1 !# MA PA
ldxa [%g0 + 0x90] %asi, %l1 !# MA Addr
ldxa [%g0 + 0x88] %asi, %l1 !# MA PA
ldxa [%g0 + 0x80] %asi, %l1 !# MA CTL
andcc %l1, %l2, %l1
bne,pn %xcc, _t2_fail
nop
rdhpr %halt, %g7
wrpr %g0, 0x95, %pstate
add %g2, 288, %g2 !# Operation Step (16 * # _t2_of _t2_operations _t2_in _t2_queue)
add %g4, 164, %g4 !# Operand Step (_t2_always 164)
_t2_loop_9:
wrpr %g0, 38, %pstate
!# write NPRIME
setx 0x80f9cd42642a7ba1, %g7, %l2
stxa %l2, [%g0 + 0x98] %asi
setx _t2_ma_operations, %g6, %l7
#ifdef SPU_8
#if (MAX_THREADS > 8)
! Add core ID offset
or %l7, %o1, %l7
#endif
#endif
or %g0, 10, %i0 !# OPSELECT
umul %i0, 16, %i0
add %i0, %g2, %i0
!# write MA_ADDR
ldx [%l7 + %i0], %l1
stxa %l1, [%g0 + 0x90] %asi
!# write MA_CTL
add %i0, 8, %i0
ldx [%l7 + %i0], %l1
stxa %l1, [%g0 + 0x80] %asi !# OPERATION
!# setup mask to check for INVOP
or %g0, 0x1, %l2
sllx %l2, 21, %l2
#! Try MA_SYNC operation...
_t2_wait2_9:
ldxa [%g0 + 0xA0] %asi, %l1
ldxa [%g0 + 0x98] %asi, %l1 !# MA PA
ldxa [%g0 + 0x90] %asi, %l1 !# MA Addr
ldxa [%g0 + 0x88] %asi, %l1 !# MA PA
ldxa [%g0 + 0x80] %asi, %l1 !# MA CTL
andcc %l1, %l2, %l1
bne,pn %xcc, _t2_fail
nop
rdhpr %halt, %g7
wrpr %g0, 0x73, %pstate
add %g2, 288, %g2 !# Operation Step (16 * # _t2_of _t2_operations _t2_in _t2_queue)
add %g4, 164, %g4 !# Operand Step (_t2_always 164)
_t2_loop_10:
wrpr %g0, 0x93, %pstate
!# write NPRIME
setx 0x391f3533345d821d, %g7, %l2
stxa %l2, [%g0 + 0x98] %asi
setx _t2_ma_operations, %g6, %l7
#ifdef SPU_8
#if (MAX_THREADS > 8)
! Add core ID offset
or %l7, %o1, %l7
#endif
#endif
or %g0, 7, %i0 !# OPSELECT
umul %i0, 16, %i0
add %i0, %g2, %i0
!# write MA_ADDR
ldx [%l7 + %i0], %l1
stxa %l1, [%g0 + 0x90] %asi
!# write MA_CTL
add %i0, 8, %i0
ldx [%l7 + %i0], %l1
stxa %l1, [%g0 + 0x80] %asi !# OPERATION
!# setup mask to check for INVOP
or %g0, 0x1, %l2
sllx %l2, 21, %l2
#! Try MA_SYNC operation...
_t2_wait2_10:
ldxa [%g0 + 0xA0] %asi, %l1
ldxa [%g0 + 0x98] %asi, %l1 !# MA PA
ldxa [%g0 + 0x90] %asi, %l1 !# MA Addr
ldxa [%g0 + 0x88] %asi, %l1 !# MA PA
ldxa [%g0 + 0x80] %asi, %l1 !# MA CTL
andcc %l1, %l2, %l1
bne,pn %xcc, _t2_fail
nop
rdhpr %halt, %g7
wrpr %g0, 0xf0, %pstate
add %g2, 288, %g2 !# Operation Step (16 * # _t2_of _t2_operations _t2_in _t2_queue)
add %g4, 164, %g4 !# Operand Step (_t2_always 164)
_t2_loop_11:
wrpr %g0, 0x45, %pstate
!# write NPRIME
setx 0xc3d1fe0708fcfd15, %g7, %l2
stxa %l2, [%g0 + 0x98] %asi
setx _t2_ma_operations, %g6, %l7
#ifdef SPU_8
#if (MAX_THREADS > 8)
! Add core ID offset
or %l7, %o1, %l7
#endif
#endif
or %g0, 11, %i0 !# OPSELECT
umul %i0, 16, %i0
add %i0, %g2, %i0
!# write MA_ADDR
ldx [%l7 + %i0], %l1
stxa %l1, [%g0 + 0x90] %asi
!# write MA_CTL
add %i0, 8, %i0
ldx [%l7 + %i0], %l1
stxa %l1, [%g0 + 0x80] %asi !# OPERATION
!# setup mask to check for INVOP
or %g0, 0x1, %l2
sllx %l2, 21, %l2
#! Try MA_SYNC operation...
_t2_wait2_11:
ldxa [%g0 + 0xA0] %asi, %l1
ldxa [%g0 + 0x98] %asi, %l1 !# MA PA
ldxa [%g0 + 0x90] %asi, %l1 !# MA Addr
ldxa [%g0 + 0x88] %asi, %l1 !# MA PA
ldxa [%g0 + 0x80] %asi, %l1 !# MA CTL
andcc %l1, %l2, %l1
bne,pn %xcc, _t2_fail
nop
rdhpr %halt, %g7
wrpr %g0, 0xf1, %pstate
add %g2, 288, %g2 !# Operation Step (16 * # _t2_of _t2_operations _t2_in _t2_queue)
add %g4, 164, %g4 !# Operand Step (_t2_always 164)
_t2_loop_12:
wrpr %g0, 0xa0, %pstate
!# write NPRIME
setx 0x9ec0f55503d715e7, %g7, %l2
stxa %l2, [%g0 + 0x98] %asi
setx _t2_ma_operations, %g6, %l7
#ifdef SPU_8
#if (MAX_THREADS > 8)
! Add core ID offset
or %l7, %o1, %l7
#endif
#endif
or %g0, 2, %i0 !# OPSELECT
umul %i0, 16, %i0
add %i0, %g2, %i0
!# write MA_ADDR
ldx [%l7 + %i0], %l1
stxa %l1, [%g0 + 0x90] %asi
!# write MA_CTL
add %i0, 8, %i0
ldx [%l7 + %i0], %l1
stxa %l1, [%g0 + 0x80] %asi !# OPERATION
!# setup mask to check for INVOP
or %g0, 0x1, %l2
sllx %l2, 21, %l2
#! Try MA_SYNC operation...
_t2_wait2_12:
ldxa [%g0 + 0xA0] %asi, %l1
ldxa [%g0 + 0x98] %asi, %l1 !# MA PA
ldxa [%g0 + 0x90] %asi, %l1 !# MA Addr
ldxa [%g0 + 0x88] %asi, %l1 !# MA PA
ldxa [%g0 + 0x80] %asi, %l1 !# MA CTL
andcc %l1, %l2, %l1
bne,pn %xcc, _t2_fail
nop
rdhpr %halt, %g7
wrpr %g0, 0xd2, %pstate
add %g2, 288, %g2 !# Operation Step (16 * # _t2_of _t2_operations _t2_in _t2_queue)
add %g4, 164, %g4 !# Operand Step (_t2_always 164)
_t2_loop_13:
wrpr %g0, 0x40, %pstate
!# write NPRIME
setx 0xa33e974e3b75f211, %g7, %l2
stxa %l2, [%g0 + 0x98] %asi
setx _t2_ma_operations, %g6, %l7
#ifdef SPU_8
#if (MAX_THREADS > 8)
! Add core ID offset
or %l7, %o1, %l7
#endif
#endif
or %g0, 14, %i0 !# OPSELECT
umul %i0, 16, %i0
add %i0, %g2, %i0
!# write MA_ADDR
ldx [%l7 + %i0], %l1
stxa %l1, [%g0 + 0x90] %asi
!# write MA_CTL
add %i0, 8, %i0
ldx [%l7 + %i0], %l1
stxa %l1, [%g0 + 0x80] %asi !# OPERATION
!# setup mask to check for INVOP
or %g0, 0x1, %l2
sllx %l2, 21, %l2
#! Try MA_SYNC operation...
_t2_wait2_13:
ldxa [%g0 + 0xA0] %asi, %l1
ldxa [%g0 + 0x98] %asi, %l1 !# MA PA
ldxa [%g0 + 0x90] %asi, %l1 !# MA Addr
ldxa [%g0 + 0x88] %asi, %l1 !# MA PA
ldxa [%g0 + 0x80] %asi, %l1 !# MA CTL
andcc %l1, %l2, %l1
bne,pn %xcc, _t2_fail
nop
rdhpr %halt, %g7
wrpr %g0, 0x63, %pstate
add %g2, 288, %g2 !# Operation Step (16 * # _t2_of _t2_operations _t2_in _t2_queue)
add %g4, 164, %g4 !# Operand Step (_t2_always 164)
_t2_loop_14:
wrpr %g0, 0x72, %pstate
!# write NPRIME
setx 0xa2d0fa03ee4a6de4, %g7, %l2
stxa %l2, [%g0 + 0x98] %asi
setx _t2_ma_operations, %g6, %l7
#ifdef SPU_8
#if (MAX_THREADS > 8)
! Add core ID offset
or %l7, %o1, %l7
#endif
#endif
or %g0, 12, %i0 !# OPSELECT
umul %i0, 16, %i0
add %i0, %g2, %i0
!# write MA_ADDR
ldx [%l7 + %i0], %l1
stxa %l1, [%g0 + 0x90] %asi
!# write MA_CTL
add %i0, 8, %i0
ldx [%l7 + %i0], %l1
stxa %l1, [%g0 + 0x80] %asi !# OPERATION
!# setup mask to check for INVOP
or %g0, 0x1, %l2
sllx %l2, 21, %l2
#! Try MA_SYNC operation...
_t2_wait2_14:
ldxa [%g0 + 0xA0] %asi, %l1
ldxa [%g0 + 0x98] %asi, %l1 !# MA PA
ldxa [%g0 + 0x90] %asi, %l1 !# MA Addr
ldxa [%g0 + 0x88] %asi, %l1 !# MA PA
ldxa [%g0 + 0x80] %asi, %l1 !# MA CTL
andcc %l1, %l2, %l1
bne,pn %xcc, _t2_fail
nop
rdhpr %halt, %g7
wrpr %g0, 0x87, %pstate
add %g2, 288, %g2 !# Operation Step (16 * # _t2_of _t2_operations _t2_in _t2_queue)
add %g4, 164, %g4 !# Operand Step (_t2_always 164)
_t2_loop_15:
wrpr %g0, 21, %pstate
!# write NPRIME
setx 0x35048505a17365e5, %g7, %l2
stxa %l2, [%g0 + 0x98] %asi
setx _t2_ma_operations, %g6, %l7
#ifdef SPU_8
#if (MAX_THREADS > 8)
! Add core ID offset
or %l7, %o1, %l7
#endif
#endif
or %g0, 7, %i0 !# OPSELECT
umul %i0, 16, %i0
add %i0, %g2, %i0
!# write MA_ADDR
ldx [%l7 + %i0], %l1
stxa %l1, [%g0 + 0x90] %asi
!# write MA_CTL
add %i0, 8, %i0
ldx [%l7 + %i0], %l1
stxa %l1, [%g0 + 0x80] %asi !# OPERATION
!# setup mask to check for INVOP
or %g0, 0x1, %l2
sllx %l2, 21, %l2
#! Try MA_SYNC operation...
_t2_wait2_15:
ldxa [%g0 + 0xA0] %asi, %l1
ldxa [%g0 + 0x98] %asi, %l1 !# MA PA
ldxa [%g0 + 0x90] %asi, %l1 !# MA Addr
ldxa [%g0 + 0x88] %asi, %l1 !# MA PA
ldxa [%g0 + 0x80] %asi, %l1 !# MA CTL
andcc %l1, %l2, %l1
bne,pn %xcc, _t2_fail
nop
rdhpr %halt, %g7
wrpr %g0, 0x56, %pstate
add %g2, 288, %g2 !# Operation Step (16 * # _t2_of _t2_operations _t2_in _t2_queue)
add %g4, 164, %g4 !# Operand Step (_t2_always 164)
_t2_loop_16:
wrpr %g0, 0x77, %pstate
!# write NPRIME
setx 0x301f7be6fc90d585, %g7, %l2
stxa %l2, [%g0 + 0x98] %asi
setx _t2_ma_operations, %g6, %l7
#ifdef SPU_8
#if (MAX_THREADS > 8)
! Add core ID offset
or %l7, %o1, %l7
#endif
#endif
or %g0, 6, %i0 !# OPSELECT
umul %i0, 16, %i0
add %i0, %g2, %i0
!# write MA_ADDR
ldx [%l7 + %i0], %l1
stxa %l1, [%g0 + 0x90] %asi
!# write MA_CTL
add %i0, 8, %i0
ldx [%l7 + %i0], %l1
stxa %l1, [%g0 + 0x80] %asi !# OPERATION
!# setup mask to check for INVOP
or %g0, 0x1, %l2
sllx %l2, 21, %l2
#! Try MA_SYNC operation...
_t2_wait2_16:
ldxa [%g0 + 0xA0] %asi, %l1
ldxa [%g0 + 0x98] %asi, %l1 !# MA PA
ldxa [%g0 + 0x90] %asi, %l1 !# MA Addr
ldxa [%g0 + 0x88] %asi, %l1 !# MA PA
ldxa [%g0 + 0x80] %asi, %l1 !# MA CTL
andcc %l1, %l2, %l1
bne,pn %xcc, _t2_fail
nop
rdhpr %halt, %g7
wrpr %g0, 16, %pstate
add %g2, 288, %g2 !# Operation Step (16 * # _t2_of _t2_operations _t2_in _t2_queue)
add %g4, 164, %g4 !# Operand Step (_t2_always 164)
_t2_loop_17:
wrpr %g0, 0xc1, %pstate
!# write NPRIME
setx 0x86cd2d16d7c4bee0, %g7, %l2
stxa %l2, [%g0 + 0x98] %asi
setx _t2_ma_operations, %g6, %l7
#ifdef SPU_8
#if (MAX_THREADS > 8)
! Add core ID offset
or %l7, %o1, %l7
#endif
#endif
or %g0, 15, %i0 !# OPSELECT
umul %i0, 16, %i0
add %i0, %g2, %i0
!# write MA_ADDR
ldx [%l7 + %i0], %l1
stxa %l1, [%g0 + 0x90] %asi
!# write MA_CTL
add %i0, 8, %i0
ldx [%l7 + %i0], %l1
stxa %l1, [%g0 + 0x80] %asi !# OPERATION
!# setup mask to check for INVOP
or %g0, 0x1, %l2
sllx %l2, 21, %l2
#! Try MA_SYNC operation...
_t2_wait2_17:
ldxa [%g0 + 0xA0] %asi, %l1
ldxa [%g0 + 0x98] %asi, %l1 !# MA PA
ldxa [%g0 + 0x90] %asi, %l1 !# MA Addr
ldxa [%g0 + 0x88] %asi, %l1 !# MA PA
ldxa [%g0 + 0x80] %asi, %l1 !# MA CTL
andcc %l1, %l2, %l1
bne,pn %xcc, _t2_fail
nop
rdhpr %halt, %g7
wrpr %g0, 0xb3, %pstate
add %g2, 288, %g2 !# Operation Step (16 * # _t2_of _t2_operations _t2_in _t2_queue)
add %g4, 164, %g4 !# Operand Step (_t2_always 164)
_t2_loop_18:
wrpr %g0, 0xb4, %pstate
!# write NPRIME
setx 0xccb6c3a3fb92547b, %g7, %l2
stxa %l2, [%g0 + 0x98] %asi
setx _t2_ma_operations, %g6, %l7
#ifdef SPU_8
#if (MAX_THREADS > 8)
! Add core ID offset
or %l7, %o1, %l7
#endif
#endif
or %g0, 9, %i0 !# OPSELECT
umul %i0, 16, %i0
add %i0, %g2, %i0
!# write MA_ADDR
ldx [%l7 + %i0], %l1
stxa %l1, [%g0 + 0x90] %asi
!# write MA_CTL
add %i0, 8, %i0
ldx [%l7 + %i0], %l1
stxa %l1, [%g0 + 0x80] %asi !# OPERATION
!# setup mask to check for INVOP
or %g0, 0x1, %l2
sllx %l2, 21, %l2
#! Try MA_SYNC operation...
_t2_wait2_18:
ldxa [%g0 + 0xA0] %asi, %l1
ldxa [%g0 + 0x98] %asi, %l1 !# MA PA
ldxa [%g0 + 0x90] %asi, %l1 !# MA Addr
ldxa [%g0 + 0x88] %asi, %l1 !# MA PA
ldxa [%g0 + 0x80] %asi, %l1 !# MA CTL
andcc %l1, %l2, %l1
bne,pn %xcc, _t2_fail
nop
rdhpr %halt, %g7
wrpr %g0, 33, %pstate
add %g2, 288, %g2 !# Operation Step (16 * # _t2_of _t2_operations _t2_in _t2_queue)
add %g4, 164, %g4 !# Operand Step (_t2_always 164)
_t2_loop_19:
wrpr %g0, 3, %pstate
!# write NPRIME
setx 0x6b1170bf3a7e3363, %g7, %l2
stxa %l2, [%g0 + 0x98] %asi
setx _t2_ma_operations, %g6, %l7
#ifdef SPU_8
#if (MAX_THREADS > 8)
! Add core ID offset
or %l7, %o1, %l7
#endif
#endif
or %g0, 6, %i0 !# OPSELECT
umul %i0, 16, %i0
add %i0, %g2, %i0
!# write MA_ADDR
ldx [%l7 + %i0], %l1
stxa %l1, [%g0 + 0x90] %asi
!# write MA_CTL
add %i0, 8, %i0
ldx [%l7 + %i0], %l1
stxa %l1, [%g0 + 0x80] %asi !# OPERATION
!# setup mask to check for INVOP
or %g0, 0x1, %l2
sllx %l2, 21, %l2
#! Try MA_SYNC operation...
_t2_wait2_19:
ldxa [%g0 + 0xA0] %asi, %l1
ldxa [%g0 + 0x98] %asi, %l1 !# MA PA
ldxa [%g0 + 0x90] %asi, %l1 !# MA Addr
ldxa [%g0 + 0x88] %asi, %l1 !# MA PA
ldxa [%g0 + 0x80] %asi, %l1 !# MA CTL
andcc %l1, %l2, %l1
bne,pn %xcc, _t2_fail
nop
rdhpr %halt, %g7
wrpr %g0, 0x85, %pstate
add %g2, 288, %g2 !# Operation Step (16 * # _t2_of _t2_operations _t2_in _t2_queue)
add %g4, 164, %g4 !# Operand Step (_t2_always 164)
_t2_loop_20:
wrpr %g0, 0xc2, %pstate
!# write NPRIME
setx 0x605d13cb8ca0e8c0, %g7, %l2
stxa %l2, [%g0 + 0x98] %asi
setx _t2_ma_operations, %g6, %l7
#ifdef SPU_8
#if (MAX_THREADS > 8)
! Add core ID offset
or %l7, %o1, %l7
#endif
#endif
or %g0, 12, %i0 !# OPSELECT
umul %i0, 16, %i0
add %i0, %g2, %i0
!# write MA_ADDR
ldx [%l7 + %i0], %l1
stxa %l1, [%g0 + 0x90] %asi
!# write MA_CTL
add %i0, 8, %i0
ldx [%l7 + %i0], %l1
stxa %l1, [%g0 + 0x80] %asi !# OPERATION
!# setup mask to check for INVOP
or %g0, 0x1, %l2
sllx %l2, 21, %l2
#! Try MA_SYNC operation...
_t2_wait2_20:
ldxa [%g0 + 0xA0] %asi, %l1
ldxa [%g0 + 0x98] %asi, %l1 !# MA PA
ldxa [%g0 + 0x90] %asi, %l1 !# MA Addr
ldxa [%g0 + 0x88] %asi, %l1 !# MA PA
ldxa [%g0 + 0x80] %asi, %l1 !# MA CTL
andcc %l1, %l2, %l1
bne,pn %xcc, _t2_fail
nop
rdhpr %halt, %g7
wrpr %g0, 33, %pstate
add %g2, 288, %g2 !# Operation Step (16 * # _t2_of _t2_operations _t2_in _t2_queue)
add %g4, 164, %g4 !# Operand Step (_t2_always 164)
_t2_loop_21:
wrpr %g0, 0x90, %pstate
!# write NPRIME
setx 0x88099b11162ef946, %g7, %l2
stxa %l2, [%g0 + 0x98] %asi
setx _t2_ma_operations, %g6, %l7
#ifdef SPU_8
#if (MAX_THREADS > 8)
! Add core ID offset
or %l7, %o1, %l7
#endif
#endif
or %g0, 16, %i0 !# OPSELECT
umul %i0, 16, %i0
add %i0, %g2, %i0
!# write MA_ADDR
ldx [%l7 + %i0], %l1
stxa %l1, [%g0 + 0x90] %asi
!# write MA_CTL
add %i0, 8, %i0
ldx [%l7 + %i0], %l1
stxa %l1, [%g0 + 0x80] %asi !# OPERATION
!# setup mask to check for INVOP
or %g0, 0x1, %l2
sllx %l2, 21, %l2
#! Try MA_SYNC operation...
_t2_wait2_21:
ldxa [%g0 + 0xA0] %asi, %l1
ldxa [%g0 + 0x98] %asi, %l1 !# MA PA
ldxa [%g0 + 0x90] %asi, %l1 !# MA Addr
ldxa [%g0 + 0x88] %asi, %l1 !# MA PA
ldxa [%g0 + 0x80] %asi, %l1 !# MA CTL
andcc %l1, %l2, %l1
bne,pn %xcc, _t2_fail
nop
rdhpr %halt, %g7
wrpr %g0, 0xf5, %pstate
add %g2, 288, %g2 !# Operation Step (16 * # _t2_of _t2_operations _t2_in _t2_queue)
add %g4, 164, %g4 !# Operand Step (_t2_always 164)
_t2_loop_22:
wrpr %g0, 0xb4, %pstate
!# write NPRIME
setx 0xf7bfebb33d0f3959, %g7, %l2
stxa %l2, [%g0 + 0x98] %asi
setx _t2_ma_operations, %g6, %l7
#ifdef SPU_8
#if (MAX_THREADS > 8)
! Add core ID offset
or %l7, %o1, %l7
#endif
#endif
or %g0, 0, %i0 !# OPSELECT
umul %i0, 16, %i0
add %i0, %g2, %i0
!# write MA_ADDR
ldx [%l7 + %i0], %l1
stxa %l1, [%g0 + 0x90] %asi
!# write MA_CTL
add %i0, 8, %i0
ldx [%l7 + %i0], %l1
stxa %l1, [%g0 + 0x80] %asi !# OPERATION
!# setup mask to check for INVOP
or %g0, 0x1, %l2
sllx %l2, 21, %l2
#! Try MA_SYNC operation...
_t2_wait2_22:
ldxa [%g0 + 0xA0] %asi, %l1
ldxa [%g0 + 0x98] %asi, %l1 !# MA PA
ldxa [%g0 + 0x90] %asi, %l1 !# MA Addr
ldxa [%g0 + 0x88] %asi, %l1 !# MA PA
ldxa [%g0 + 0x80] %asi, %l1 !# MA CTL
andcc %l1, %l2, %l1
bne,pn %xcc, _t2_fail
nop
rdhpr %halt, %g7
wrpr %g0, 0x47, %pstate
add %g2, 288, %g2 !# Operation Step (16 * # _t2_of _t2_operations _t2_in _t2_queue)
add %g4, 164, %g4 !# Operand Step (_t2_always 164)
_t2_loop_23:
wrpr %g0, 0xf7, %pstate
!# write NPRIME
setx 0x303e35803bd7d390, %g7, %l2
stxa %l2, [%g0 + 0x98] %asi
setx _t2_ma_operations, %g6, %l7
#ifdef SPU_8
#if (MAX_THREADS > 8)
! Add core ID offset
or %l7, %o1, %l7
#endif
#endif
or %g0, 16, %i0 !# OPSELECT
umul %i0, 16, %i0
add %i0, %g2, %i0
!# write MA_ADDR
ldx [%l7 + %i0], %l1
stxa %l1, [%g0 + 0x90] %asi
!# write MA_CTL
add %i0, 8, %i0
ldx [%l7 + %i0], %l1
stxa %l1, [%g0 + 0x80] %asi !# OPERATION
!# setup mask to check for INVOP
or %g0, 0x1, %l2
sllx %l2, 21, %l2
#! Try MA_SYNC operation...
_t2_wait2_23:
ldxa [%g0 + 0xA0] %asi, %l1
ldxa [%g0 + 0x98] %asi, %l1 !# MA PA
ldxa [%g0 + 0x90] %asi, %l1 !# MA Addr
ldxa [%g0 + 0x88] %asi, %l1 !# MA PA
ldxa [%g0 + 0x80] %asi, %l1 !# MA CTL
andcc %l1, %l2, %l1
bne,pn %xcc, _t2_fail
nop
rdhpr %halt, %g7
wrpr %g0, 0x40, %pstate
add %g2, 288, %g2 !# Operation Step (16 * # _t2_of _t2_operations _t2_in _t2_queue)
add %g4, 164, %g4 !# Operand Step (_t2_always 164)
_t2_loop_24:
wrpr %g0, 0x60, %pstate
!# write NPRIME
setx 0x3505df37505e4092, %g7, %l2
stxa %l2, [%g0 + 0x98] %asi
setx _t2_ma_operations, %g6, %l7
#ifdef SPU_8
#if (MAX_THREADS > 8)
! Add core ID offset
or %l7, %o1, %l7
#endif
#endif
or %g0, 13, %i0 !# OPSELECT
umul %i0, 16, %i0
add %i0, %g2, %i0
!# write MA_ADDR
ldx [%l7 + %i0], %l1
stxa %l1, [%g0 + 0x90] %asi
!# write MA_CTL
add %i0, 8, %i0
ldx [%l7 + %i0], %l1
stxa %l1, [%g0 + 0x80] %asi !# OPERATION
!# setup mask to check for INVOP
or %g0, 0x1, %l2
sllx %l2, 21, %l2
#! Try MA_SYNC operation...
_t2_wait2_24:
ldxa [%g0 + 0xA0] %asi, %l1
ldxa [%g0 + 0x98] %asi, %l1 !# MA PA
ldxa [%g0 + 0x90] %asi, %l1 !# MA Addr
ldxa [%g0 + 0x88] %asi, %l1 !# MA PA
ldxa [%g0 + 0x80] %asi, %l1 !# MA CTL
andcc %l1, %l2, %l1
bne,pn %xcc, _t2_fail
nop
rdhpr %halt, %g7
wrpr %g0, 37, %pstate
add %g2, 288, %g2 !# Operation Step (16 * # _t2_of _t2_operations _t2_in _t2_queue)
add %g4, 164, %g4 !# Operand Step (_t2_always 164)
_t2_loop_25:
wrpr %g0, 17, %pstate
!# write NPRIME
setx 0xa0f52fc894a18314, %g7, %l2
stxa %l2, [%g0 + 0x98] %asi
setx _t2_ma_operations, %g6, %l7
#ifdef SPU_8
#if (MAX_THREADS > 8)
! Add core ID offset
or %l7, %o1, %l7
#endif
#endif
or %g0, 8, %i0 !# OPSELECT
umul %i0, 16, %i0
add %i0, %g2, %i0
!# write MA_ADDR
ldx [%l7 + %i0], %l1
stxa %l1, [%g0 + 0x90] %asi
!# write MA_CTL
add %i0, 8, %i0
ldx [%l7 + %i0], %l1
stxa %l1, [%g0 + 0x80] %asi !# OPERATION
!# setup mask to check for INVOP
or %g0, 0x1, %l2
sllx %l2, 21, %l2
#! Try MA_SYNC operation...
_t2_wait2_25:
ldxa [%g0 + 0xA0] %asi, %l1
ldxa [%g0 + 0x98] %asi, %l1 !# MA PA
ldxa [%g0 + 0x90] %asi, %l1 !# MA Addr
ldxa [%g0 + 0x88] %asi, %l1 !# MA PA
ldxa [%g0 + 0x80] %asi, %l1 !# MA CTL
andcc %l1, %l2, %l1
bne,pn %xcc, _t2_fail
nop
rdhpr %halt, %g7
wrpr %g0, 0x92, %pstate
add %g2, 288, %g2 !# Operation Step (16 * # _t2_of _t2_operations _t2_in _t2_queue)
add %g4, 164, %g4 !# Operand Step (_t2_always 164)
_t2_loop_26:
wrpr %g0, 5, %pstate
!# write NPRIME
setx 0xd50514ac553a52d6, %g7, %l2
stxa %l2, [%g0 + 0x98] %asi
setx _t2_ma_operations, %g6, %l7
#ifdef SPU_8
#if (MAX_THREADS > 8)
! Add core ID offset
or %l7, %o1, %l7
#endif
#endif
or %g0, 12, %i0 !# OPSELECT
umul %i0, 16, %i0
add %i0, %g2, %i0
!# write MA_ADDR
ldx [%l7 + %i0], %l1
stxa %l1, [%g0 + 0x90] %asi
!# write MA_CTL
add %i0, 8, %i0
ldx [%l7 + %i0], %l1
stxa %l1, [%g0 + 0x80] %asi !# OPERATION
!# setup mask to check for INVOP
or %g0, 0x1, %l2
sllx %l2, 21, %l2
#! Try MA_SYNC operation...
_t2_wait2_26:
ldxa [%g0 + 0xA0] %asi, %l1
ldxa [%g0 + 0x98] %asi, %l1 !# MA PA
ldxa [%g0 + 0x90] %asi, %l1 !# MA Addr
ldxa [%g0 + 0x88] %asi, %l1 !# MA PA
ldxa [%g0 + 0x80] %asi, %l1 !# MA CTL
andcc %l1, %l2, %l1
bne,pn %xcc, _t2_fail
nop
rdhpr %halt, %g7
wrpr %g0, 21, %pstate
add %g2, 288, %g2 !# Operation Step (16 * # _t2_of _t2_operations _t2_in _t2_queue)
add %g4, 164, %g4 !# Operand Step (_t2_always 164)
_t2_loop_27:
wrpr %g0, 0x42, %pstate
!# write NPRIME
setx 0x0d1622de7eaf416c, %g7, %l2
stxa %l2, [%g0 + 0x98] %asi
setx _t2_ma_operations, %g6, %l7
#ifdef SPU_8
#if (MAX_THREADS > 8)
! Add core ID offset
or %l7, %o1, %l7
#endif
#endif
or %g0, 2, %i0 !# OPSELECT
umul %i0, 16, %i0
add %i0, %g2, %i0
!# write MA_ADDR
ldx [%l7 + %i0], %l1
stxa %l1, [%g0 + 0x90] %asi
!# write MA_CTL
add %i0, 8, %i0
ldx [%l7 + %i0], %l1
stxa %l1, [%g0 + 0x80] %asi !# OPERATION
!# setup mask to check for INVOP
or %g0, 0x1, %l2
sllx %l2, 21, %l2
#! Try MA_SYNC operation...
_t2_wait2_27:
ldxa [%g0 + 0xA0] %asi, %l1
ldxa [%g0 + 0x98] %asi, %l1 !# MA PA
ldxa [%g0 + 0x90] %asi, %l1 !# MA Addr
ldxa [%g0 + 0x88] %asi, %l1 !# MA PA
ldxa [%g0 + 0x80] %asi, %l1 !# MA CTL
andcc %l1, %l2, %l1
bne,pn %xcc, _t2_fail
nop
rdhpr %halt, %g7
wrpr %g0, 7, %pstate
add %g2, 288, %g2 !# Operation Step (16 * # _t2_of _t2_operations _t2_in _t2_queue)
add %g4, 164, %g4 !# Operand Step (_t2_always 164)
_t2_loop_28:
wrpr %g0, 16, %pstate
!# write NPRIME
setx 0x912a6e6f34e3d0d8, %g7, %l2
stxa %l2, [%g0 + 0x98] %asi
setx _t2_ma_operations, %g6, %l7
#ifdef SPU_8
#if (MAX_THREADS > 8)
! Add core ID offset
or %l7, %o1, %l7
#endif
#endif
or %g0, 1, %i0 !# OPSELECT
umul %i0, 16, %i0
add %i0, %g2, %i0
!# write MA_ADDR
ldx [%l7 + %i0], %l1
stxa %l1, [%g0 + 0x90] %asi
!# write MA_CTL
add %i0, 8, %i0
ldx [%l7 + %i0], %l1
stxa %l1, [%g0 + 0x80] %asi !# OPERATION
!# setup mask to check for INVOP
or %g0, 0x1, %l2
sllx %l2, 21, %l2
#! Try MA_SYNC operation...
_t2_wait2_28:
ldxa [%g0 + 0xA0] %asi, %l1
ldxa [%g0 + 0x98] %asi, %l1 !# MA PA
ldxa [%g0 + 0x90] %asi, %l1 !# MA Addr
ldxa [%g0 + 0x88] %asi, %l1 !# MA PA
ldxa [%g0 + 0x80] %asi, %l1 !# MA CTL
andcc %l1, %l2, %l1
bne,pn %xcc, _t2_fail
nop
rdhpr %halt, %g7
wrpr %g0, 0xa6, %pstate
add %g2, 288, %g2 !# Operation Step (16 * # _t2_of _t2_operations _t2_in _t2_queue)
add %g4, 164, %g4 !# Operand Step (_t2_always 164)
_t2_loop_29:
wrpr %g0, 35, %pstate
!# write NPRIME
setx 0xb839755ab7eb568f, %g7, %l2
stxa %l2, [%g0 + 0x98] %asi
setx _t2_ma_operations, %g6, %l7
#ifdef SPU_8
#if (MAX_THREADS > 8)
! Add core ID offset
or %l7, %o1, %l7
#endif
#endif
or %g0, 8, %i0 !# OPSELECT
umul %i0, 16, %i0
add %i0, %g2, %i0
!# write MA_ADDR
ldx [%l7 + %i0], %l1
stxa %l1, [%g0 + 0x90] %asi
!# write MA_CTL
add %i0, 8, %i0
ldx [%l7 + %i0], %l1
stxa %l1, [%g0 + 0x80] %asi !# OPERATION
!# setup mask to check for INVOP
or %g0, 0x1, %l2
sllx %l2, 21, %l2
#! Try MA_SYNC operation...
_t2_wait2_29:
ldxa [%g0 + 0xA0] %asi, %l1
ldxa [%g0 + 0x98] %asi, %l1 !# MA PA
ldxa [%g0 + 0x90] %asi, %l1 !# MA Addr
ldxa [%g0 + 0x88] %asi, %l1 !# MA PA
ldxa [%g0 + 0x80] %asi, %l1 !# MA CTL
andcc %l1, %l2, %l1
bne,pn %xcc, _t2_fail
nop
rdhpr %halt, %g7
wrpr %g0, 55, %pstate
add %g2, 288, %g2 !# Operation Step (16 * # _t2_of _t2_operations _t2_in _t2_queue)
add %g4, 164, %g4 !# Operand Step (_t2_always 164)
_t2_loop_30:
wrpr %g0, 0xb6, %pstate
!# write NPRIME
setx 0xba2fc2cb03b14b7c, %g7, %l2
stxa %l2, [%g0 + 0x98] %asi
setx _t2_ma_operations, %g6, %l7
#ifdef SPU_8
#if (MAX_THREADS > 8)
! Add core ID offset
or %l7, %o1, %l7
#endif
#endif
or %g0, 13, %i0 !# OPSELECT
umul %i0, 16, %i0
add %i0, %g2, %i0
!# write MA_ADDR
ldx [%l7 + %i0], %l1
stxa %l1, [%g0 + 0x90] %asi
!# write MA_CTL
add %i0, 8, %i0
ldx [%l7 + %i0], %l1
stxa %l1, [%g0 + 0x80] %asi !# OPERATION
!# setup mask to check for INVOP
or %g0, 0x1, %l2
sllx %l2, 21, %l2
#! Try MA_SYNC operation...
_t2_wait2_30:
ldxa [%g0 + 0xA0] %asi, %l1
ldxa [%g0 + 0x98] %asi, %l1 !# MA PA
ldxa [%g0 + 0x90] %asi, %l1 !# MA Addr
ldxa [%g0 + 0x88] %asi, %l1 !# MA PA
ldxa [%g0 + 0x80] %asi, %l1 !# MA CTL
andcc %l1, %l2, %l1
bne,pn %xcc, _t2_fail
nop
rdhpr %halt, %g7
wrpr %g0, 52, %pstate
add %g2, 288, %g2 !# Operation Step (16 * # _t2_of _t2_operations _t2_in _t2_queue)
add %g4, 164, %g4 !# Operand Step (_t2_always 164)
_t2_loop_31:
wrpr %g0, 0xe4, %pstate
!# write NPRIME
setx 0x95822fb1ce3c89d8, %g7, %l2
stxa %l2, [%g0 + 0x98] %asi
setx _t2_ma_operations, %g6, %l7
#ifdef SPU_8
#if (MAX_THREADS > 8)
! Add core ID offset
or %l7, %o1, %l7
#endif
#endif
or %g0, 16, %i0 !# OPSELECT
umul %i0, 16, %i0
add %i0, %g2, %i0
!# write MA_ADDR
ldx [%l7 + %i0], %l1
stxa %l1, [%g0 + 0x90] %asi
!# write MA_CTL
add %i0, 8, %i0
ldx [%l7 + %i0], %l1
stxa %l1, [%g0 + 0x80] %asi !# OPERATION
!# setup mask to check for INVOP
or %g0, 0x1, %l2
sllx %l2, 21, %l2
#! Try MA_SYNC operation...
_t2_wait2_31:
ldxa [%g0 + 0xA0] %asi, %l1
ldxa [%g0 + 0x98] %asi, %l1 !# MA PA
ldxa [%g0 + 0x90] %asi, %l1 !# MA Addr
ldxa [%g0 + 0x88] %asi, %l1 !# MA PA
ldxa [%g0 + 0x80] %asi, %l1 !# MA CTL
andcc %l1, %l2, %l1
bne,pn %xcc, _t2_fail
nop
rdhpr %halt, %g7
wrpr %g0, 0x63, %pstate
add %g2, 288, %g2 !# Operation Step (16 * # _t2_of _t2_operations _t2_in _t2_queue)
add %g4, 164, %g4 !# Operand Step (_t2_always 164)
_t2_loop_32:
wrpr %g0, 0x86, %pstate
!# write NPRIME
setx 0x5b6ec4933f0f26e8, %g7, %l2
stxa %l2, [%g0 + 0x98] %asi
setx _t2_ma_operations, %g6, %l7
#ifdef SPU_8
#if (MAX_THREADS > 8)
! Add core ID offset
or %l7, %o1, %l7
#endif
#endif
or %g0, 12, %i0 !# OPSELECT
umul %i0, 16, %i0
add %i0, %g2, %i0
!# write MA_ADDR
ldx [%l7 + %i0], %l1
stxa %l1, [%g0 + 0x90] %asi
!# write MA_CTL
add %i0, 8, %i0
ldx [%l7 + %i0], %l1
stxa %l1, [%g0 + 0x80] %asi !# OPERATION
!# setup mask to check for INVOP
or %g0, 0x1, %l2
sllx %l2, 21, %l2
#! Try MA_SYNC operation...
_t2_wait2_32:
ldxa [%g0 + 0xA0] %asi, %l1
ldxa [%g0 + 0x98] %asi, %l1 !# MA PA
ldxa [%g0 + 0x90] %asi, %l1 !# MA Addr
ldxa [%g0 + 0x88] %asi, %l1 !# MA PA
ldxa [%g0 + 0x80] %asi, %l1 !# MA CTL
andcc %l1, %l2, %l1
bne,pn %xcc, _t2_fail
nop
rdhpr %halt, %g7
wrpr %g0, 0x55, %pstate
add %g2, 288, %g2 !# Operation Step (16 * # _t2_of _t2_operations _t2_in _t2_queue)
add %g4, 164, %g4 !# Operand Step (_t2_always 164)
_t2_loop_33:
wrpr %g0, 0xa1, %pstate
!# write NPRIME
setx 0x60d2d9908aab073e, %g7, %l2
stxa %l2, [%g0 + 0x98] %asi
setx _t2_ma_operations, %g6, %l7
#ifdef SPU_8
#if (MAX_THREADS > 8)
! Add core ID offset
or %l7, %o1, %l7
#endif
#endif
or %g0, 14, %i0 !# OPSELECT
umul %i0, 16, %i0
add %i0, %g2, %i0
!# write MA_ADDR
ldx [%l7 + %i0], %l1
stxa %l1, [%g0 + 0x90] %asi
!# write MA_CTL
add %i0, 8, %i0
ldx [%l7 + %i0], %l1
stxa %l1, [%g0 + 0x80] %asi !# OPERATION
!# setup mask to check for INVOP
or %g0, 0x1, %l2
sllx %l2, 21, %l2
#! Try MA_SYNC operation...
_t2_wait2_33:
ldxa [%g0 + 0xA0] %asi, %l1
ldxa [%g0 + 0x98] %asi, %l1 !# MA PA
ldxa [%g0 + 0x90] %asi, %l1 !# MA Addr
ldxa [%g0 + 0x88] %asi, %l1 !# MA PA
ldxa [%g0 + 0x80] %asi, %l1 !# MA CTL
andcc %l1, %l2, %l1
bne,pn %xcc, _t2_fail
nop
rdhpr %halt, %g7
wrpr %g0, 0xd0, %pstate
add %g2, 288, %g2 !# Operation Step (16 * # _t2_of _t2_operations _t2_in _t2_queue)
add %g4, 164, %g4 !# Operand Step (_t2_always 164)
_t2_loop_34:
wrpr %g0, 34, %pstate
!# write NPRIME
setx 0x318e5090f6fd5c83, %g7, %l2
stxa %l2, [%g0 + 0x98] %asi
setx _t2_ma_operations, %g6, %l7
#ifdef SPU_8
#if (MAX_THREADS > 8)
! Add core ID offset
or %l7, %o1, %l7
#endif
#endif
or %g0, 15, %i0 !# OPSELECT
umul %i0, 16, %i0
add %i0, %g2, %i0
!# write MA_ADDR
ldx [%l7 + %i0], %l1
stxa %l1, [%g0 + 0x90] %asi
!# write MA_CTL
add %i0, 8, %i0
ldx [%l7 + %i0], %l1
stxa %l1, [%g0 + 0x80] %asi !# OPERATION
!# setup mask to check for INVOP
or %g0, 0x1, %l2
sllx %l2, 21, %l2
#! Try MA_SYNC operation...
_t2_wait2_34:
ldxa [%g0 + 0xA0] %asi, %l1
ldxa [%g0 + 0x98] %asi, %l1 !# MA PA
ldxa [%g0 + 0x90] %asi, %l1 !# MA Addr
ldxa [%g0 + 0x88] %asi, %l1 !# MA PA
ldxa [%g0 + 0x80] %asi, %l1 !# MA CTL
andcc %l1, %l2, %l1
bne,pn %xcc, _t2_fail
nop
rdhpr %halt, %g7
wrpr %g0, 0xd4, %pstate
add %g2, 288, %g2 !# Operation Step (16 * # _t2_of _t2_operations _t2_in _t2_queue)
add %g4, 164, %g4 !# Operand Step (_t2_always 164)
_t2_loop_35:
wrpr %g0, 20, %pstate
!# write NPRIME
setx 0x1e24c66026befcb1, %g7, %l2
stxa %l2, [%g0 + 0x98] %asi
setx _t2_ma_operations, %g6, %l7
#ifdef SPU_8
#if (MAX_THREADS > 8)
! Add core ID offset
or %l7, %o1, %l7
#endif
#endif
or %g0, 11, %i0 !# OPSELECT
umul %i0, 16, %i0
add %i0, %g2, %i0
!# write MA_ADDR
ldx [%l7 + %i0], %l1
stxa %l1, [%g0 + 0x90] %asi
!# write MA_CTL
add %i0, 8, %i0
ldx [%l7 + %i0], %l1
stxa %l1, [%g0 + 0x80] %asi !# OPERATION
!# setup mask to check for INVOP
or %g0, 0x1, %l2
sllx %l2, 21, %l2
#! Try MA_SYNC operation...
_t2_wait2_35:
ldxa [%g0 + 0xA0] %asi, %l1
ldxa [%g0 + 0x98] %asi, %l1 !# MA PA
ldxa [%g0 + 0x90] %asi, %l1 !# MA Addr
ldxa [%g0 + 0x88] %asi, %l1 !# MA PA
ldxa [%g0 + 0x80] %asi, %l1 !# MA CTL
andcc %l1, %l2, %l1
bne,pn %xcc, _t2_fail
nop
rdhpr %halt, %g7
wrpr %g0, 0xa5, %pstate
add %g2, 288, %g2 !# Operation Step (16 * # _t2_of _t2_operations _t2_in _t2_queue)
add %g4, 164, %g4 !# Operand Step (_t2_always 164)
_t2_loop_36:
wrpr %g0, 0xe0, %pstate
!# write NPRIME
setx 0x1908f8c26db61e08, %g7, %l2
stxa %l2, [%g0 + 0x98] %asi
setx _t2_ma_operations, %g6, %l7
#ifdef SPU_8
#if (MAX_THREADS > 8)
! Add core ID offset
or %l7, %o1, %l7
#endif
#endif
or %g0, 1, %i0 !# OPSELECT
umul %i0, 16, %i0
add %i0, %g2, %i0
!# write MA_ADDR
ldx [%l7 + %i0], %l1
stxa %l1, [%g0 + 0x90] %asi
!# write MA_CTL
add %i0, 8, %i0
ldx [%l7 + %i0], %l1
stxa %l1, [%g0 + 0x80] %asi !# OPERATION
!# setup mask to check for INVOP
or %g0, 0x1, %l2
sllx %l2, 21, %l2
#! Try MA_SYNC operation...
_t2_wait2_36:
ldxa [%g0 + 0xA0] %asi, %l1
ldxa [%g0 + 0x98] %asi, %l1 !# MA PA
ldxa [%g0 + 0x90] %asi, %l1 !# MA Addr
ldxa [%g0 + 0x88] %asi, %l1 !# MA PA
ldxa [%g0 + 0x80] %asi, %l1 !# MA CTL
andcc %l1, %l2, %l1
bne,pn %xcc, _t2_fail
nop
rdhpr %halt, %g7
wrpr %g0, 0xe6, %pstate
add %g2, 288, %g2 !# Operation Step (16 * # _t2_of _t2_operations _t2_in _t2_queue)
add %g4, 164, %g4 !# Operand Step (_t2_always 164)
_t2_loop_37:
wrpr %g0, 32, %pstate
!# write NPRIME
setx 0x32387393b229b086, %g7, %l2
stxa %l2, [%g0 + 0x98] %asi
setx _t2_ma_operations, %g6, %l7
#ifdef SPU_8
#if (MAX_THREADS > 8)
! Add core ID offset
or %l7, %o1, %l7
#endif
#endif
or %g0, 15, %i0 !# OPSELECT
umul %i0, 16, %i0
add %i0, %g2, %i0
!# write MA_ADDR
ldx [%l7 + %i0], %l1
stxa %l1, [%g0 + 0x90] %asi
!# write MA_CTL
add %i0, 8, %i0
ldx [%l7 + %i0], %l1
stxa %l1, [%g0 + 0x80] %asi !# OPERATION
!# setup mask to check for INVOP
or %g0, 0x1, %l2
sllx %l2, 21, %l2
#! Try MA_SYNC operation...
_t2_wait2_37:
ldxa [%g0 + 0xA0] %asi, %l1
ldxa [%g0 + 0x98] %asi, %l1 !# MA PA
ldxa [%g0 + 0x90] %asi, %l1 !# MA Addr
ldxa [%g0 + 0x88] %asi, %l1 !# MA PA
ldxa [%g0 + 0x80] %asi, %l1 !# MA CTL
andcc %l1, %l2, %l1
bne,pn %xcc, _t2_fail
nop
rdhpr %halt, %g7
wrpr %g0, 0x95, %pstate
add %g2, 288, %g2 !# Operation Step (16 * # _t2_of _t2_operations _t2_in _t2_queue)
add %g4, 164, %g4 !# Operand Step (_t2_always 164)
_t2_loop_38:
wrpr %g0, 0xd0, %pstate
!# write NPRIME
setx 0xa8d04c4d6095b29b, %g7, %l2
stxa %l2, [%g0 + 0x98] %asi
setx _t2_ma_operations, %g6, %l7
#ifdef SPU_8
#if (MAX_THREADS > 8)
! Add core ID offset
or %l7, %o1, %l7
#endif
#endif
or %g0, 17, %i0 !# OPSELECT
umul %i0, 16, %i0
add %i0, %g2, %i0
!# write MA_ADDR
ldx [%l7 + %i0], %l1
stxa %l1, [%g0 + 0x90] %asi
!# write MA_CTL
add %i0, 8, %i0
ldx [%l7 + %i0], %l1
stxa %l1, [%g0 + 0x80] %asi !# OPERATION
!# setup mask to check for INVOP
or %g0, 0x1, %l2
sllx %l2, 21, %l2
#! Try MA_SYNC operation...
_t2_wait2_38:
ldxa [%g0 + 0xA0] %asi, %l1
ldxa [%g0 + 0x98] %asi, %l1 !# MA PA
ldxa [%g0 + 0x90] %asi, %l1 !# MA Addr
ldxa [%g0 + 0x88] %asi, %l1 !# MA PA
ldxa [%g0 + 0x80] %asi, %l1 !# MA CTL
andcc %l1, %l2, %l1
bne,pn %xcc, _t2_fail
nop
rdhpr %halt, %g7
wrpr %g0, 0xa5, %pstate
add %g2, 288, %g2 !# Operation Step (16 * # _t2_of _t2_operations _t2_in _t2_queue)
add %g4, 164, %g4 !# Operand Step (_t2_always 164)
_t2_loop_39:
wrpr %g0, 0xf6, %pstate
!# write NPRIME
setx 0x1803e10027b79fb9, %g7, %l2
stxa %l2, [%g0 + 0x98] %asi
setx _t2_ma_operations, %g6, %l7
#ifdef SPU_8
#if (MAX_THREADS > 8)
! Add core ID offset
or %l7, %o1, %l7
#endif
#endif
or %g0, 15, %i0 !# OPSELECT
umul %i0, 16, %i0
add %i0, %g2, %i0
!# write MA_ADDR
ldx [%l7 + %i0], %l1
stxa %l1, [%g0 + 0x90] %asi
!# write MA_CTL
add %i0, 8, %i0
ldx [%l7 + %i0], %l1
stxa %l1, [%g0 + 0x80] %asi !# OPERATION
!# setup mask to check for INVOP
or %g0, 0x1, %l2
sllx %l2, 21, %l2
#! Try MA_SYNC operation...
_t2_wait2_39:
ldxa [%g0 + 0xA0] %asi, %l1
ldxa [%g0 + 0x98] %asi, %l1 !# MA PA
ldxa [%g0 + 0x90] %asi, %l1 !# MA Addr
ldxa [%g0 + 0x88] %asi, %l1 !# MA PA
ldxa [%g0 + 0x80] %asi, %l1 !# MA CTL
andcc %l1, %l2, %l1
bne,pn %xcc, _t2_fail
nop
rdhpr %halt, %g7
wrpr %g0, 0, %pstate
add %g2, 288, %g2 !# Operation Step (16 * # _t2_of _t2_operations _t2_in _t2_queue)
add %g4, 164, %g4 !# Operand Step (_t2_always 164)
_t2_loop_40:
wrpr %g0, 0xb2, %pstate
!# write NPRIME
setx 0xdc407d6d448420dc, %g7, %l2
stxa %l2, [%g0 + 0x98] %asi
setx _t2_ma_operations, %g6, %l7
#ifdef SPU_8
#if (MAX_THREADS > 8)
! Add core ID offset
or %l7, %o1, %l7
#endif
#endif
or %g0, 1, %i0 !# OPSELECT
umul %i0, 16, %i0
add %i0, %g2, %i0
!# write MA_ADDR
ldx [%l7 + %i0], %l1
stxa %l1, [%g0 + 0x90] %asi
!# write MA_CTL
add %i0, 8, %i0
ldx [%l7 + %i0], %l1
stxa %l1, [%g0 + 0x80] %asi !# OPERATION
!# setup mask to check for INVOP
or %g0, 0x1, %l2
sllx %l2, 21, %l2
#! Try MA_SYNC operation...
_t2_wait2_40:
ldxa [%g0 + 0xA0] %asi, %l1
ldxa [%g0 + 0x98] %asi, %l1 !# MA PA
ldxa [%g0 + 0x90] %asi, %l1 !# MA Addr
ldxa [%g0 + 0x88] %asi, %l1 !# MA PA
ldxa [%g0 + 0x80] %asi, %l1 !# MA CTL
andcc %l1, %l2, %l1
bne,pn %xcc, _t2_fail
nop
rdhpr %halt, %g7
wrpr %g0, 0xf2, %pstate
add %g2, 288, %g2 !# Operation Step (16 * # _t2_of _t2_operations _t2_in _t2_queue)
add %g4, 164, %g4 !# Operand Step (_t2_always 164)
_t2_loop_41:
wrpr %g0, 0xe1, %pstate
!# write NPRIME
setx 0xbf454a9c5cb5458d, %g7, %l2
stxa %l2, [%g0 + 0x98] %asi
setx _t2_ma_operations, %g6, %l7
#ifdef SPU_8
#if (MAX_THREADS > 8)
! Add core ID offset
or %l7, %o1, %l7
#endif
#endif
or %g0, 17, %i0 !# OPSELECT
umul %i0, 16, %i0
add %i0, %g2, %i0
!# write MA_ADDR
ldx [%l7 + %i0], %l1
stxa %l1, [%g0 + 0x90] %asi
!# write MA_CTL
add %i0, 8, %i0
ldx [%l7 + %i0], %l1
stxa %l1, [%g0 + 0x80] %asi !# OPERATION
!# setup mask to check for INVOP
or %g0, 0x1, %l2
sllx %l2, 21, %l2
#! Try MA_SYNC operation...
_t2_wait2_41:
ldxa [%g0 + 0xA0] %asi, %l1
ldxa [%g0 + 0x98] %asi, %l1 !# MA PA
ldxa [%g0 + 0x90] %asi, %l1 !# MA Addr
ldxa [%g0 + 0x88] %asi, %l1 !# MA PA
ldxa [%g0 + 0x80] %asi, %l1 !# MA CTL
andcc %l1, %l2, %l1
bne,pn %xcc, _t2_fail
nop
rdhpr %halt, %g7
wrpr %g0, 0x82, %pstate
add %g2, 288, %g2 !# Operation Step (16 * # _t2_of _t2_operations _t2_in _t2_queue)
add %g4, 164, %g4 !# Operand Step (_t2_always 164)
_t2_loop_42:
wrpr %g0, 0x86, %pstate
!# write NPRIME
setx 0x84f80bceda156076, %g7, %l2
stxa %l2, [%g0 + 0x98] %asi
setx _t2_ma_operations, %g6, %l7
#ifdef SPU_8
#if (MAX_THREADS > 8)
! Add core ID offset
or %l7, %o1, %l7
#endif
#endif
or %g0, 2, %i0 !# OPSELECT
umul %i0, 16, %i0
add %i0, %g2, %i0
!# write MA_ADDR
ldx [%l7 + %i0], %l1
stxa %l1, [%g0 + 0x90] %asi
!# write MA_CTL
add %i0, 8, %i0
ldx [%l7 + %i0], %l1
stxa %l1, [%g0 + 0x80] %asi !# OPERATION
!# setup mask to check for INVOP
or %g0, 0x1, %l2
sllx %l2, 21, %l2
#! Try MA_SYNC operation...
_t2_wait2_42:
ldxa [%g0 + 0xA0] %asi, %l1
ldxa [%g0 + 0x98] %asi, %l1 !# MA PA
ldxa [%g0 + 0x90] %asi, %l1 !# MA Addr
ldxa [%g0 + 0x88] %asi, %l1 !# MA PA
ldxa [%g0 + 0x80] %asi, %l1 !# MA CTL
andcc %l1, %l2, %l1
bne,pn %xcc, _t2_fail
nop
rdhpr %halt, %g7
wrpr %g0, 38, %pstate
add %g2, 288, %g2 !# Operation Step (16 * # _t2_of _t2_operations _t2_in _t2_queue)
add %g4, 164, %g4 !# Operand Step (_t2_always 164)
_t2_loop_43:
wrpr %g0, 19, %pstate
!# write NPRIME
setx 0xa6aed1edd620e7ef, %g7, %l2
stxa %l2, [%g0 + 0x98] %asi
setx _t2_ma_operations, %g6, %l7
#ifdef SPU_8
#if (MAX_THREADS > 8)
! Add core ID offset
or %l7, %o1, %l7
#endif
#endif
or %g0, 9, %i0 !# OPSELECT
umul %i0, 16, %i0
add %i0, %g2, %i0
!# write MA_ADDR
ldx [%l7 + %i0], %l1
stxa %l1, [%g0 + 0x90] %asi
!# write MA_CTL
add %i0, 8, %i0
ldx [%l7 + %i0], %l1
stxa %l1, [%g0 + 0x80] %asi !# OPERATION
!# setup mask to check for INVOP
or %g0, 0x1, %l2
sllx %l2, 21, %l2
#! Try MA_SYNC operation...
_t2_wait2_43:
ldxa [%g0 + 0xA0] %asi, %l1
ldxa [%g0 + 0x98] %asi, %l1 !# MA PA
ldxa [%g0 + 0x90] %asi, %l1 !# MA Addr
ldxa [%g0 + 0x88] %asi, %l1 !# MA PA
ldxa [%g0 + 0x80] %asi, %l1 !# MA CTL
andcc %l1, %l2, %l1
bne,pn %xcc, _t2_fail
nop
rdhpr %halt, %g7
wrpr %g0, 0xb6, %pstate
add %g2, 288, %g2 !# Operation Step (16 * # _t2_of _t2_operations _t2_in _t2_queue)
add %g4, 164, %g4 !# Operand Step (_t2_always 164)
_t2_loop_44:
wrpr %g0, 0x41, %pstate
!# write NPRIME
setx 0xdd08e751bf79819b, %g7, %l2
stxa %l2, [%g0 + 0x98] %asi
setx _t2_ma_operations, %g6, %l7
#ifdef SPU_8
#if (MAX_THREADS > 8)
! Add core ID offset
or %l7, %o1, %l7
#endif
#endif
or %g0, 6, %i0 !# OPSELECT
umul %i0, 16, %i0
add %i0, %g2, %i0
!# write MA_ADDR
ldx [%l7 + %i0], %l1
stxa %l1, [%g0 + 0x90] %asi
!# write MA_CTL
add %i0, 8, %i0
ldx [%l7 + %i0], %l1
stxa %l1, [%g0 + 0x80] %asi !# OPERATION
!# setup mask to check for INVOP
or %g0, 0x1, %l2
sllx %l2, 21, %l2
#! Try MA_SYNC operation...
_t2_wait2_44:
ldxa [%g0 + 0xA0] %asi, %l1
ldxa [%g0 + 0x98] %asi, %l1 !# MA PA
ldxa [%g0 + 0x90] %asi, %l1 !# MA Addr
ldxa [%g0 + 0x88] %asi, %l1 !# MA PA
ldxa [%g0 + 0x80] %asi, %l1 !# MA CTL
andcc %l1, %l2, %l1
bne,pn %xcc, _t2_fail
nop
rdhpr %halt, %g7
wrpr %g0, 37, %pstate
add %g2, 288, %g2 !# Operation Step (16 * # _t2_of _t2_operations _t2_in _t2_queue)
add %g4, 164, %g4 !# Operand Step (_t2_always 164)
_t2_loop_45:
wrpr %g0, 0x94, %pstate
!# write NPRIME
setx 0x16a44aadbcffbea7, %g7, %l2
stxa %l2, [%g0 + 0x98] %asi
setx _t2_ma_operations, %g6, %l7
#ifdef SPU_8
#if (MAX_THREADS > 8)
! Add core ID offset
or %l7, %o1, %l7
#endif
#endif
or %g0, 9, %i0 !# OPSELECT
umul %i0, 16, %i0
add %i0, %g2, %i0
!# write MA_ADDR
ldx [%l7 + %i0], %l1
stxa %l1, [%g0 + 0x90] %asi
!# write MA_CTL
add %i0, 8, %i0
ldx [%l7 + %i0], %l1
stxa %l1, [%g0 + 0x80] %asi !# OPERATION
!# setup mask to check for INVOP
or %g0, 0x1, %l2
sllx %l2, 21, %l2
#! Try MA_SYNC operation...
_t2_wait2_45:
ldxa [%g0 + 0xA0] %asi, %l1
ldxa [%g0 + 0x98] %asi, %l1 !# MA PA
ldxa [%g0 + 0x90] %asi, %l1 !# MA Addr
ldxa [%g0 + 0x88] %asi, %l1 !# MA PA
ldxa [%g0 + 0x80] %asi, %l1 !# MA CTL
andcc %l1, %l2, %l1
bne,pn %xcc, _t2_fail
nop
rdhpr %halt, %g7
wrpr %g0, 0xb2, %pstate
add %g2, 288, %g2 !# Operation Step (16 * # _t2_of _t2_operations _t2_in _t2_queue)
add %g4, 164, %g4 !# Operand Step (_t2_always 164)
_t2_loop_46:
wrpr %g0, 0xb4, %pstate
!# write NPRIME
setx 0x7c632804a3c3eeb6, %g7, %l2
stxa %l2, [%g0 + 0x98] %asi
setx _t2_ma_operations, %g6, %l7
#ifdef SPU_8
#if (MAX_THREADS > 8)
! Add core ID offset
or %l7, %o1, %l7
#endif
#endif
or %g0, 15, %i0 !# OPSELECT
umul %i0, 16, %i0
add %i0, %g2, %i0
!# write MA_ADDR
ldx [%l7 + %i0], %l1
stxa %l1, [%g0 + 0x90] %asi
!# write MA_CTL
add %i0, 8, %i0
ldx [%l7 + %i0], %l1
stxa %l1, [%g0 + 0x80] %asi !# OPERATION
!# setup mask to check for INVOP
or %g0, 0x1, %l2
sllx %l2, 21, %l2
#! Try MA_SYNC operation...
_t2_wait2_46:
ldxa [%g0 + 0xA0] %asi, %l1
ldxa [%g0 + 0x98] %asi, %l1 !# MA PA
ldxa [%g0 + 0x90] %asi, %l1 !# MA Addr
ldxa [%g0 + 0x88] %asi, %l1 !# MA PA
ldxa [%g0 + 0x80] %asi, %l1 !# MA CTL
andcc %l1, %l2, %l1
bne,pn %xcc, _t2_fail
nop
rdhpr %halt, %g7
wrpr %g0, 0xb7, %pstate
add %g2, 288, %g2 !# Operation Step (16 * # _t2_of _t2_operations _t2_in _t2_queue)
add %g4, 164, %g4 !# Operand Step (_t2_always 164)
_t2_loop_47:
wrpr %g0, 0x53, %pstate
!# write NPRIME
setx 0xa6842b696fea17ff, %g7, %l2
stxa %l2, [%g0 + 0x98] %asi
setx _t2_ma_operations, %g6, %l7
#ifdef SPU_8
#if (MAX_THREADS > 8)
! Add core ID offset
or %l7, %o1, %l7
#endif
#endif
or %g0, 1, %i0 !# OPSELECT
umul %i0, 16, %i0
add %i0, %g2, %i0
!# write MA_ADDR
ldx [%l7 + %i0], %l1
stxa %l1, [%g0 + 0x90] %asi
!# write MA_CTL
add %i0, 8, %i0
ldx [%l7 + %i0], %l1
stxa %l1, [%g0 + 0x80] %asi !# OPERATION
!# setup mask to check for INVOP
or %g0, 0x1, %l2
sllx %l2, 21, %l2
#! Try MA_SYNC operation...
_t2_wait2_47:
ldxa [%g0 + 0xA0] %asi, %l1
ldxa [%g0 + 0x98] %asi, %l1 !# MA PA
ldxa [%g0 + 0x90] %asi, %l1 !# MA Addr
ldxa [%g0 + 0x88] %asi, %l1 !# MA PA
ldxa [%g0 + 0x80] %asi, %l1 !# MA CTL
andcc %l1, %l2, %l1
bne,pn %xcc, _t2_fail
nop
rdhpr %halt, %g7
wrpr %g0, 0xb4, %pstate
add %g2, 288, %g2 !# Operation Step (16 * # _t2_of _t2_operations _t2_in _t2_queue)
add %g4, 164, %g4 !# Operand Step (_t2_always 164)
_t2_loop_48:
wrpr %g0, 0xf6, %pstate
!# write NPRIME
setx 0x3c74f2728acbc372, %g7, %l2
stxa %l2, [%g0 + 0x98] %asi
setx _t2_ma_operations, %g6, %l7
#ifdef SPU_8
#if (MAX_THREADS > 8)
! Add core ID offset
or %l7, %o1, %l7
#endif
#endif
or %g0, 12, %i0 !# OPSELECT
umul %i0, 16, %i0
add %i0, %g2, %i0
!# write MA_ADDR
ldx [%l7 + %i0], %l1
stxa %l1, [%g0 + 0x90] %asi
!# write MA_CTL
add %i0, 8, %i0
ldx [%l7 + %i0], %l1
stxa %l1, [%g0 + 0x80] %asi !# OPERATION
!# setup mask to check for INVOP
or %g0, 0x1, %l2
sllx %l2, 21, %l2
#! Try MA_SYNC operation...
_t2_wait2_48:
ldxa [%g0 + 0xA0] %asi, %l1
ldxa [%g0 + 0x98] %asi, %l1 !# MA PA
ldxa [%g0 + 0x90] %asi, %l1 !# MA Addr
ldxa [%g0 + 0x88] %asi, %l1 !# MA PA
ldxa [%g0 + 0x80] %asi, %l1 !# MA CTL
andcc %l1, %l2, %l1
bne,pn %xcc, _t2_fail
nop
rdhpr %halt, %g7
wrpr %g0, 0xa4, %pstate
add %g2, 288, %g2 !# Operation Step (16 * # _t2_of _t2_operations _t2_in _t2_queue)
add %g4, 164, %g4 !# Operand Step (_t2_always 164)
_t2_loop_49:
wrpr %g0, 49, %pstate
!# write NPRIME
setx 0x971b01ccf49a06ca, %g7, %l2
stxa %l2, [%g0 + 0x98] %asi
setx _t2_ma_operations, %g6, %l7
#ifdef SPU_8
#if (MAX_THREADS > 8)
! Add core ID offset
or %l7, %o1, %l7
#endif
#endif
or %g0, 1, %i0 !# OPSELECT
umul %i0, 16, %i0
add %i0, %g2, %i0
!# write MA_ADDR
ldx [%l7 + %i0], %l1
stxa %l1, [%g0 + 0x90] %asi
!# write MA_CTL
add %i0, 8, %i0
ldx [%l7 + %i0], %l1
stxa %l1, [%g0 + 0x80] %asi !# OPERATION
!# setup mask to check for INVOP
or %g0, 0x1, %l2
sllx %l2, 21, %l2
#! Try MA_SYNC operation...
_t2_wait2_49:
ldxa [%g0 + 0xA0] %asi, %l1
ldxa [%g0 + 0x98] %asi, %l1 !# MA PA
ldxa [%g0 + 0x90] %asi, %l1 !# MA Addr
ldxa [%g0 + 0x88] %asi, %l1 !# MA PA
ldxa [%g0 + 0x80] %asi, %l1 !# MA CTL
andcc %l1, %l2, %l1
bne,pn %xcc, _t2_fail
nop
rdhpr %halt, %g7
wrpr %g0, 0xc4, %pstate
add %g2, 288, %g2 !# Operation Step (16 * # _t2_of _t2_operations _t2_in _t2_queue)
add %g4, 164, %g4 !# Operand Step (_t2_always 164)
_t2_loop_50:
wrpr %g0, 0x42, %pstate
!# write NPRIME
setx 0x61fae0309d336697, %g7, %l2
stxa %l2, [%g0 + 0x98] %asi
setx _t2_ma_operations, %g6, %l7
#ifdef SPU_8
#if (MAX_THREADS > 8)
! Add core ID offset
or %l7, %o1, %l7
#endif
#endif
or %g0, 15, %i0 !# OPSELECT
umul %i0, 16, %i0
add %i0, %g2, %i0
!# write MA_ADDR
ldx [%l7 + %i0], %l1
stxa %l1, [%g0 + 0x90] %asi
!# write MA_CTL
add %i0, 8, %i0
ldx [%l7 + %i0], %l1
stxa %l1, [%g0 + 0x80] %asi !# OPERATION
!# setup mask to check for INVOP
or %g0, 0x1, %l2
sllx %l2, 21, %l2
#! Try MA_SYNC operation...
_t2_wait2_50:
ldxa [%g0 + 0xA0] %asi, %l1
ldxa [%g0 + 0x98] %asi, %l1 !# MA PA
ldxa [%g0 + 0x90] %asi, %l1 !# MA Addr
ldxa [%g0 + 0x88] %asi, %l1 !# MA PA
ldxa [%g0 + 0x80] %asi, %l1 !# MA CTL
andcc %l1, %l2, %l1
bne,pn %xcc, _t2_fail
nop
rdhpr %halt, %g7
wrpr %g0, 0xc7, %pstate
add %g2, 288, %g2 !# Operation Step (16 * # _t2_of _t2_operations _t2_in _t2_queue)
add %g4, 164, %g4 !# Operand Step (_t2_always 164)
_t2_loop_51:
wrpr %g0, 0x63, %pstate
!# write NPRIME
setx 0x573f34f58aa2acf4, %g7, %l2
stxa %l2, [%g0 + 0x98] %asi
setx _t2_ma_operations, %g6, %l7
#ifdef SPU_8
#if (MAX_THREADS > 8)
! Add core ID offset
or %l7, %o1, %l7
#endif
#endif
or %g0, 10, %i0 !# OPSELECT
umul %i0, 16, %i0
add %i0, %g2, %i0
!# write MA_ADDR
ldx [%l7 + %i0], %l1
stxa %l1, [%g0 + 0x90] %asi
!# write MA_CTL
add %i0, 8, %i0
ldx [%l7 + %i0], %l1
stxa %l1, [%g0 + 0x80] %asi !# OPERATION
!# setup mask to check for INVOP
or %g0, 0x1, %l2
sllx %l2, 21, %l2
#! Try MA_SYNC operation...
_t2_wait2_51:
ldxa [%g0 + 0xA0] %asi, %l1
ldxa [%g0 + 0x98] %asi, %l1 !# MA PA
ldxa [%g0 + 0x90] %asi, %l1 !# MA Addr
ldxa [%g0 + 0x88] %asi, %l1 !# MA PA
ldxa [%g0 + 0x80] %asi, %l1 !# MA CTL
andcc %l1, %l2, %l1
bne,pn %xcc, _t2_fail
nop
rdhpr %halt, %g7
wrpr %g0, 0x65, %pstate
add %g2, 288, %g2 !# Operation Step (16 * # _t2_of _t2_operations _t2_in _t2_queue)
add %g4, 164, %g4 !# Operand Step (_t2_always 164)
_t2_loop_52:
wrpr %g0, 0x77, %pstate
!# write NPRIME
setx 0xd6abe7e9e96e2381, %g7, %l2
stxa %l2, [%g0 + 0x98] %asi
setx _t2_ma_operations, %g6, %l7
#ifdef SPU_8
#if (MAX_THREADS > 8)
! Add core ID offset
or %l7, %o1, %l7
#endif
#endif
or %g0, 15, %i0 !# OPSELECT
umul %i0, 16, %i0
add %i0, %g2, %i0
!# write MA_ADDR
ldx [%l7 + %i0], %l1
stxa %l1, [%g0 + 0x90] %asi
!# write MA_CTL
add %i0, 8, %i0
ldx [%l7 + %i0], %l1
stxa %l1, [%g0 + 0x80] %asi !# OPERATION
!# setup mask to check for INVOP
or %g0, 0x1, %l2
sllx %l2, 21, %l2
#! Try MA_SYNC operation...
_t2_wait2_52:
ldxa [%g0 + 0xA0] %asi, %l1
ldxa [%g0 + 0x98] %asi, %l1 !# MA PA
ldxa [%g0 + 0x90] %asi, %l1 !# MA Addr
ldxa [%g0 + 0x88] %asi, %l1 !# MA PA
ldxa [%g0 + 0x80] %asi, %l1 !# MA CTL
andcc %l1, %l2, %l1
bne,pn %xcc, _t2_fail
nop
rdhpr %halt, %g7
wrpr %g0, 0xd6, %pstate
add %g2, 288, %g2 !# Operation Step (16 * # _t2_of _t2_operations _t2_in _t2_queue)
add %g4, 164, %g4 !# Operand Step (_t2_always 164)
_t2_loop_53:
wrpr %g0, 0xc1, %pstate
!# write NPRIME
setx 0x6fc1808c35375b10, %g7, %l2
stxa %l2, [%g0 + 0x98] %asi
setx _t2_ma_operations, %g6, %l7
#ifdef SPU_8
#if (MAX_THREADS > 8)
! Add core ID offset
or %l7, %o1, %l7
#endif
#endif
or %g0, 12, %i0 !# OPSELECT
umul %i0, 16, %i0
add %i0, %g2, %i0
!# write MA_ADDR
ldx [%l7 + %i0], %l1
stxa %l1, [%g0 + 0x90] %asi
!# write MA_CTL
add %i0, 8, %i0
ldx [%l7 + %i0], %l1
stxa %l1, [%g0 + 0x80] %asi !# OPERATION
!# setup mask to check for INVOP
or %g0, 0x1, %l2
sllx %l2, 21, %l2
#! Try MA_SYNC operation...
_t2_wait2_53:
ldxa [%g0 + 0xA0] %asi, %l1
ldxa [%g0 + 0x98] %asi, %l1 !# MA PA
ldxa [%g0 + 0x90] %asi, %l1 !# MA Addr
ldxa [%g0 + 0x88] %asi, %l1 !# MA PA
ldxa [%g0 + 0x80] %asi, %l1 !# MA CTL
andcc %l1, %l2, %l1
bne,pn %xcc, _t2_fail
nop
rdhpr %halt, %g7
wrpr %g0, 32, %pstate
add %g2, 288, %g2 !# Operation Step (16 * # _t2_of _t2_operations _t2_in _t2_queue)
add %g4, 164, %g4 !# Operand Step (_t2_always 164)
_t2_loop_54:
wrpr %g0, 19, %pstate
!# write NPRIME
setx 0x5660e5e555467663, %g7, %l2
stxa %l2, [%g0 + 0x98] %asi
setx _t2_ma_operations, %g6, %l7
#ifdef SPU_8
#if (MAX_THREADS > 8)
! Add core ID offset
or %l7, %o1, %l7
#endif
#endif
or %g0, 17, %i0 !# OPSELECT
umul %i0, 16, %i0
add %i0, %g2, %i0
!# write MA_ADDR
ldx [%l7 + %i0], %l1
stxa %l1, [%g0 + 0x90] %asi
!# write MA_CTL
add %i0, 8, %i0
ldx [%l7 + %i0], %l1
stxa %l1, [%g0 + 0x80] %asi !# OPERATION
!# setup mask to check for INVOP
or %g0, 0x1, %l2
sllx %l2, 21, %l2
#! Try MA_SYNC operation...
_t2_wait2_54:
ldxa [%g0 + 0xA0] %asi, %l1
ldxa [%g0 + 0x98] %asi, %l1 !# MA PA
ldxa [%g0 + 0x90] %asi, %l1 !# MA Addr
ldxa [%g0 + 0x88] %asi, %l1 !# MA PA
ldxa [%g0 + 0x80] %asi, %l1 !# MA CTL
andcc %l1, %l2, %l1
bne,pn %xcc, _t2_fail
nop
rdhpr %halt, %g7
wrpr %g0, 4, %pstate
add %g2, 288, %g2 !# Operation Step (16 * # _t2_of _t2_operations _t2_in _t2_queue)
add %g4, 164, %g4 !# Operand Step (_t2_always 164)
_t2_loop_55:
wrpr %g0, 0xc0, %pstate
!# write NPRIME
setx 0xca6d521b5c2b6f63, %g7, %l2
stxa %l2, [%g0 + 0x98] %asi
setx _t2_ma_operations, %g6, %l7
#ifdef SPU_8
#if (MAX_THREADS > 8)
! Add core ID offset
or %l7, %o1, %l7
#endif
#endif
or %g0, 2, %i0 !# OPSELECT
umul %i0, 16, %i0
add %i0, %g2, %i0
!# write MA_ADDR
ldx [%l7 + %i0], %l1
stxa %l1, [%g0 + 0x90] %asi
!# write MA_CTL
add %i0, 8, %i0
ldx [%l7 + %i0], %l1
stxa %l1, [%g0 + 0x80] %asi !# OPERATION
!# setup mask to check for INVOP
or %g0, 0x1, %l2
sllx %l2, 21, %l2
#! Try MA_SYNC operation...
_t2_wait2_55:
ldxa [%g0 + 0xA0] %asi, %l1
ldxa [%g0 + 0x98] %asi, %l1 !# MA PA
ldxa [%g0 + 0x90] %asi, %l1 !# MA Addr
ldxa [%g0 + 0x88] %asi, %l1 !# MA PA
ldxa [%g0 + 0x80] %asi, %l1 !# MA CTL
andcc %l1, %l2, %l1
bne,pn %xcc, _t2_fail
nop
rdhpr %halt, %g7
wrpr %g0, 0xd0, %pstate
add %g2, 288, %g2 !# Operation Step (16 * # _t2_of _t2_operations _t2_in _t2_queue)
add %g4, 164, %g4 !# Operand Step (_t2_always 164)
_t2_loop_56:
wrpr %g0, 0x82, %pstate
!# write NPRIME
setx 0x07c141a71eab82ae, %g7, %l2
stxa %l2, [%g0 + 0x98] %asi
setx _t2_ma_operations, %g6, %l7
#ifdef SPU_8
#if (MAX_THREADS > 8)
! Add core ID offset
or %l7, %o1, %l7
#endif
#endif
or %g0, 10, %i0 !# OPSELECT
umul %i0, 16, %i0
add %i0, %g2, %i0
!# write MA_ADDR
ldx [%l7 + %i0], %l1
stxa %l1, [%g0 + 0x90] %asi
!# write MA_CTL
add %i0, 8, %i0
ldx [%l7 + %i0], %l1
stxa %l1, [%g0 + 0x80] %asi !# OPERATION
!# setup mask to check for INVOP
or %g0, 0x1, %l2
sllx %l2, 21, %l2
#! Try MA_SYNC operation...
_t2_wait2_56:
ldxa [%g0 + 0xA0] %asi, %l1
ldxa [%g0 + 0x98] %asi, %l1 !# MA PA
ldxa [%g0 + 0x90] %asi, %l1 !# MA Addr
ldxa [%g0 + 0x88] %asi, %l1 !# MA PA
ldxa [%g0 + 0x80] %asi, %l1 !# MA CTL
andcc %l1, %l2, %l1
bne,pn %xcc, _t2_fail
nop
rdhpr %halt, %g7
wrpr %g0, 0x44, %pstate
add %g2, 288, %g2 !# Operation Step (16 * # _t2_of _t2_operations _t2_in _t2_queue)
add %g4, 164, %g4 !# Operand Step (_t2_always 164)
_t2_loop_57:
wrpr %g0, 2, %pstate
!# write NPRIME
setx 0xc241e36beec45f78, %g7, %l2
stxa %l2, [%g0 + 0x98] %asi
setx _t2_ma_operations, %g6, %l7
#ifdef SPU_8
#if (MAX_THREADS > 8)
! Add core ID offset
or %l7, %o1, %l7
#endif
#endif
or %g0, 7, %i0 !# OPSELECT
umul %i0, 16, %i0
add %i0, %g2, %i0
!# write MA_ADDR
ldx [%l7 + %i0], %l1
stxa %l1, [%g0 + 0x90] %asi
!# write MA_CTL
add %i0, 8, %i0
ldx [%l7 + %i0], %l1
stxa %l1, [%g0 + 0x80] %asi !# OPERATION
!# setup mask to check for INVOP
or %g0, 0x1, %l2
sllx %l2, 21, %l2
#! Try MA_SYNC operation...
_t2_wait2_57:
ldxa [%g0 + 0xA0] %asi, %l1
ldxa [%g0 + 0x98] %asi, %l1 !# MA PA
ldxa [%g0 + 0x90] %asi, %l1 !# MA Addr
ldxa [%g0 + 0x88] %asi, %l1 !# MA PA
ldxa [%g0 + 0x80] %asi, %l1 !# MA CTL
andcc %l1, %l2, %l1
bne,pn %xcc, _t2_fail
nop
rdhpr %halt, %g7
wrpr %g0, 0xf1, %pstate
add %g2, 288, %g2 !# Operation Step (16 * # _t2_of _t2_operations _t2_in _t2_queue)
add %g4, 164, %g4 !# Operand Step (_t2_always 164)
_t2_loop_58:
wrpr %g0, 0x83, %pstate
!# write NPRIME
setx 0x28921f166c8ea730, %g7, %l2
stxa %l2, [%g0 + 0x98] %asi
setx _t2_ma_operations, %g6, %l7
#ifdef SPU_8
#if (MAX_THREADS > 8)
! Add core ID offset
or %l7, %o1, %l7
#endif
#endif
or %g0, 0, %i0 !# OPSELECT
umul %i0, 16, %i0
add %i0, %g2, %i0
!# write MA_ADDR
ldx [%l7 + %i0], %l1
stxa %l1, [%g0 + 0x90] %asi
!# write MA_CTL
add %i0, 8, %i0
ldx [%l7 + %i0], %l1
stxa %l1, [%g0 + 0x80] %asi !# OPERATION
!# setup mask to check for INVOP
or %g0, 0x1, %l2
sllx %l2, 21, %l2
#! Try MA_SYNC operation...
_t2_wait2_58:
ldxa [%g0 + 0xA0] %asi, %l1
ldxa [%g0 + 0x98] %asi, %l1 !# MA PA
ldxa [%g0 + 0x90] %asi, %l1 !# MA Addr
ldxa [%g0 + 0x88] %asi, %l1 !# MA PA
ldxa [%g0 + 0x80] %asi, %l1 !# MA CTL
andcc %l1, %l2, %l1
bne,pn %xcc, _t2_fail
nop
rdhpr %halt, %g7
wrpr %g0, 0x70, %pstate
add %g2, 288, %g2 !# Operation Step (16 * # _t2_of _t2_operations _t2_in _t2_queue)
add %g4, 164, %g4 !# Operand Step (_t2_always 164)
_t2_ma_store:
!# write MA_ADDR
or %g0, 0x00, %l2
stxa %l2, [%g0 + 0x90] %asi
!# Write result address into MA_PA reg
setx _t2_ma_results, %g7, %l6
#ifdef SPU_8
#if (MAX_THREADS > 8)
! Add core ID offset
or %l6, %o1, %l6
#endif
#endif
add %l6, 4, %l6 !# _t2_WARNING : Misaligned _t2_address
stxa %l6, [%g0 + 0x88] %asi
!# write MA_CTL
set 0x00020171, %l1
mov 6, %g7
sllx %g7, 18, %g7
or %l1, %g7, %l1
stxa %l1, [%g0 + 0x80] %asi !# STORE
!# setup mask to check for INVOP
or %g0, 0x1, %l2
sllx %l2, 21, %l2
#! Try MA_SYNC operation...
_t2_wait3:
ldxa [%g0 + 0xA0] %asi, %l1
ldxa [%g0 + 0x80] %asi, %l1
andcc %l1, %l2, %l1
bne,pn %xcc, _t2_fail
nop
_t2_idle3:
#ifndef NO_MA_CHECK
!# do dummy loads into %g1
setx _t2_ma_results, %g7, %l7
#ifdef SPU_8
#if (MAX_THREADS > 8)
! Add core ID offset
or %l7, %o1, %l7
#endif
#endif
or %g0, %g0, %l3
!# setup loop count
or %g0, 164, %i0
_t2_more:
ldx [%l7+%l3], %l0 !# a[_t2_i]
addcc %i0, -1, %i0
bgt _t2_more
add %l3, 0x8, %l3 !# i++
#endif
b _t2_done_spu_ma_rand5
_t2_fail:
EXIT_BAD
nop
nop
_t2_done_spu_ma_rand5:
.word 0x9f802050 ! 1: SIR sir 0x0050
nop
nop
ta T_CHANGE_PRIV
wrpr %g0, %g0, %gl
nop
nop
.text
setx join_lbl_0_0, %g1, %g2
jmp %g2
nop
fork_lbl_0_6:
wrhpr %g0, 0x48a, %hpstate ! ta T_CHANGE_NONHPRIV
.word 0x28800001 ! 1: BLEU bleu,a <label_0x1>
.word 0x8d903b23 ! 1: WRPR_PSTATE_I wrpr %r0, 0x1b23, %pstate
frzptr_20_3:
nop
nop
best_set_reg(0x3cb80000+0x1ffc, %r20, %r27)
ldx [%r27+0xc], %r20
jmpl %r27, %r27
.word 0x20800001 ! 5: BN bn,a <label_0x1>
jmptr_20_5:
nop
nop
best_set_reg(0xe1200000, %r20, %r27)
.word 0xb7c6c000 ! 9: JMPL_R jmpl %r27 + %r0, %r27
.word 0xc32fc000 ! 13: STXFSR_R st-sfr %f1, [%r0, %r31]
.word 0xda97c400 ! 17: LDUHA_R lduha [%r31, %r0] 0x20, %r13
jmptr_20_9:
nop
nop
best_set_reg(0xe0200000, %r20, %r27)
.word 0xb7c6c000 ! 21: JMPL_R jmpl %r27 + %r0, %r27
.word 0x8980000a ! 25: WRTICK_R wr %r0, %r10, %tick
.word 0xda800c80 ! 29: LDUWA_R lduwa [%r0, %r0] 0x64, %r13
.word 0x24cd0001 ! 33: BRLEZ brlez,a,pt %r20,<label_0xd0001>
.word 0xe28008a0 ! 37: LDUWA_R lduwa [%r0, %r0] 0x45, %r17
.word 0xe24fc000 ! 41: LDSB_R ldsb [%r31 + %r0], %r17
.word 0xa3b7c480 ! 1: FCMPLE32 fcmple32 %d62, %d0, %r17
.word 0xe3e7d140 ! 1: CASA_I casa [%r31] 0x8a, %r0, %r17
mov 0x31, %r30
.word 0x83d0001e ! 45: Tcc_R te icc_or_xcc, %r0 + %r30
demap_20_21:
nop
mov 0x80, %g3
ta T_CHANGE_HPRIV
.word 0x12800001 ! 1: BNE bne <label_0x1>
stxa %g3, [%g3] 0x57
.word 0x9d97c000 ! 1: WRPR_WSTATE_R wrpr %r31, %r0, %wstate
wrhpr %g0, 0x20b, %hpstate ! ta T_CHANGE_NONHPRIV
.word 0xe21fe0d8 ! 49: LDD_I ldd [%r31 + 0x00d8], %r17
.word 0xe247c000 ! 53: LDSW_R ldsw [%r31 + %r0], %r17
splash_lsu_20_22:
nop
nop
ta T_CHANGE_HPRIV
set 0x1066ff4f, %r2
mov 0x5, %r1
sllx %r1, 32, %r1
or %r1, %r2, %r2
.word 0x34800001 ! 1: BG bg,a <label_0x1>
stxa %r2, [%r0] ASI_LSU_CONTROL
.word 0x1d400001 ! 57: FBPULE fbule
demap_20_25:
nop
mov 0x80, %g3
ta T_CHANGE_HPRIV
.word 0x22c98001 ! 1: BRZ brz,a,pt %r6,<label_0x98001>
stxa %g3, [%g3] 0x57
.word 0xbfefc000 ! 1: RESTORE_R restore %r31, %r0, %r31
.word 0xbfe7c000 ! 1: SAVE_R save %r31, %r0, %r31
.word 0xbfefc000 ! 1: RESTORE_R restore %r31, %r0, %r31
stxa %g3, [%g3] 0x5f
stxa %g3, [%g3] 0x57
.word 0xbfefc000 ! 1: RESTORE_R restore %r31, %r0, %r31
stxa %g3, [%g3] 0x5f
.word 0xbfefc000 ! 1: RESTORE_R restore %r31, %r0, %r31
.word 0xbfe7c000 ! 1: SAVE_R save %r31, %r0, %r31
.word 0xbfe7c000 ! 1: SAVE_R save %r31, %r0, %r31
stxa %g3, [%g3] 0x5f
stxa %g3, [%g3] 0x57
.word 0x9d97c000 ! 1: WRPR_WSTATE_R wrpr %r31, %r0, %wstate
wrhpr %g0, 0xe9b, %hpstate ! ta T_CHANGE_NONHPRIV
.word 0xe21fe1f0 ! 61: LDD_I ldd [%r31 + 0x01f0], %r17
nop
nop
mov 0x0, %r11
splash_cmpr_20_28:
sllx %r11, 63, %r11
not %r11, %r11
rd %tick, %r10
#if (defined SPC || defined CMP1)
add %r10, 0x300, %r10
#else
add %r10, 0x380, %r10
#endif
and %r10, %r11, %r10
ta T_CHANGE_PRIV
rd %tick, %r10
#if (defined SPC || defined CMP1)
add %r10, 0x300, %r10
#else
add %r10, 0x700, %r10
#endif
and %r10, %r11, %r10
.word 0xaf80000a ! 1: WR_TICK_CMPR_REG_R wr %r0, %r10, %-
.word 0x81b01021 ! 65: SIAM siam 1
.word 0xe19fe100 ! 69: LDDFA_I ldda [%r31, 0x0100], %f16
.word 0xa1902001 ! 73: WRPR_GL_I wrpr %r0, 0x0001, %-
jmptr_20_34:
nop
nop
best_set_reg(0xe1200000, %r20, %r27)
.word 0xb7c6c000 ! 77: JMPL_R jmpl %r27 + %r0, %r27
nop
nop
ta T_CHANGE_HPRIV ! macro
donret_20_35:
rd %pc, %r12
mov HIGHVA_HIGHNUM, %r10
sllx %r10, 32, %r10
or %r12, %r10, %r12
add %r12, (donretarg_20_35-donret_20_35+4), %r12
add %r12, 0x4, %r11 ! seq tnpc
andn %r11, %r10, %r11 ! low VA tnpc
wrpr %g0, 0x2, %tl
wrpr %g0, %r12, %tpc
wrpr %g0, %r11, %tnpc
set (0x009ca600 | (32 << 24)), %r13
and %r12, 0xfff, %r14
sllx %r14, 32, %r14
or %r13, %r14, %r20
wrpr %r20, %g0, %tstate
wrhpr %g0, 0x149d, %htstate
best_set_reg(0xe38, %g1, %g2)
wrpr %g0, %g2, %pstate ! rand=0 (20)
done
donretarg_20_35:
.word 0x81983945 ! 81: WRHPR_HPSTATE_I wrhpr %r0, 0x1945, %hpstate
#if (defined SPC || defined CMP1)
!$EV trig_pc_d(1, expr(@VA(.MAIN.intvec_20_36) , 16, 16)) -> intp(6,0,4,*,936,*,39,1)
!$EV trig_pc_d(1, expr((@VA(.MAIN.intvec_20_36)&0xffffffff) , 16, 16)) -> intp(2,0,10,*,928,*,39,1)
#else
nop
nop
set 0xe9c083fd, %r28 !TTID : 3 (mask2tid(0x20))
#if (defined PORTABLE_CORE || MAX_THREADS == 8)
sethi %hi(0x3800), %r27
andn %r28, %r27, %r28
#ifdef PORTABLE_CORE
! Add CID to vector
ta T_CHANGE_HPRIV
ldxa [%g0]0x63, %r27
sllx %r27, 8, %r27
or %r27, %r28, %r28
#endif
#else
! Add CID IF tid matches
ifelse(3,mask2tid(0x20),`ta T_CHANGE_HPRIV;sethi %hi(0x3800), %r27;andn %r28, %r27, %r28;ldxa [%g0]0x63, %r27;sllx %r27, 8, %r27;or %r27, %r28, %r28 ')
#endif
ifelse(3,mask2tid(0x20),`.align 16')
stxa %r28, [%g0] 0x73
#endif
intvec_20_36:
.word 0x91b484c4 ! 85: FCMPNE32 fcmpne32 %d18, %d4, %r8
.word 0x9884400b ! 89: ADDcc_R addcc %r17, %r11, %r12
nop
nop
set 0x7108e0c, %r28 !TTID : 6 (mask2tid(0x20))
#if (defined PORTABLE_CORE || MAX_THREADS == 8)
sethi %hi(0x3800), %r27
andn %r28, %r27, %r28
#ifdef PORTABLE_CORE
! Add CID to vector
ta T_CHANGE_HPRIV
ldxa [%g0]0x63, %r27
sllx %r27, 8, %r27
or %r27, %r28, %r28
#endif
#else
! Add CID IF tid matches
ifelse(6,mask2tid(0x20),`ta T_CHANGE_HPRIV;sethi %hi(0x3800), %r27;andn %r28, %r27, %r28;ldxa [%g0]0x63, %r27;sllx %r27, 8, %r27;or %r27, %r28, %r28 ')
#endif
sethi %hi(0x30000), %r27
andn %r28, %r27, %r28
ta T_CHANGE_HPRIV
ifelse(6,mask2tid(0x20),`.align 16')
stxa %r28, [%g0] 0x73
intvec_20_39:
.word 0xa5b444d4 ! 93: FCMPNE32 fcmpne32 %d48, %d20, %r18
.word 0x81460000 ! 97: RD_STICK_REG stbar
.word 0xc32fe1b0 ! 101: STXFSR_I st-sfr %f1, [0x01b0, %r31]
.word 0x1c800001 ! 105: BPOS bpos <label_0x1>
nop
nop
set 0x88700b84, %r28 !TTID : 3 (mask2tid(0x20))
#if (defined PORTABLE_CORE || MAX_THREADS == 8)
sethi %hi(0x3800), %r27
andn %r28, %r27, %r28
#ifdef PORTABLE_CORE
! Add CID to vector
ta T_CHANGE_HPRIV
ldxa [%g0]0x63, %r27
sllx %r27, 8, %r27
or %r27, %r28, %r28
#endif
#else
! Add CID IF tid matches
ifelse(3,mask2tid(0x20),`ta T_CHANGE_HPRIV;sethi %hi(0x3800), %r27;andn %r28, %r27, %r28;ldxa [%g0]0x63, %r27;sllx %r27, 8, %r27;or %r27, %r28, %r28 ')
#endif
sethi %hi(0x30000), %r27
andn %r28, %r27, %r28
ta T_CHANGE_HPRIV
ifelse(3,mask2tid(0x20),`.align 16')
stxa %r28, [%g0] 0x73
intvec_20_47:
.word 0xa7a489d0 ! 109: FDIVd fdivd %f18, %f16, %f50
.word 0xd88008a0 ! 113: LDUWA_R lduwa [%r0, %r0] 0x45, %r12
nop
nop
mov 0x1, %r11
splash_cmpr_20_52:
sllx %r11, 63, %r11
not %r11, %r11
rd %tick, %r10
#if (defined SPC || defined CMP1)
add %r10, 0x100, %r10
#else
add %r10, 0xc00, %r10
#endif
and %r10, %r11, %r10
rd %tick, %r10
#if (defined SPC || defined CMP1)
add %r10, 0x150, %r10
#else
add %r10, 0x380, %r10
#endif
and %r10, %r11, %r10
.word 0xb380000a ! 1: WR_STICK_CMPR_REG_R wr %r0, %r10, %-
#if (defined SPC || defined CMP1)
!$EV trig_pc_d(1, expr(@VA(.MAIN.splash_cmpr_20_52)+8 , 16, 16)) -> intp(5,0,8,*,672,*,a3,1)
!$EV trig_pc_d(1, expr((@VA(.MAIN.splash_cmpr_20_52)&0xffffffff)+8 , 16, 16)) -> intp(7,0,2,*,928,*,a3,1)
#endif
wrhpr %g0, 0x0, %halt ! HALT
.word 0x81b01021 ! 117: SIAM siam 1
.word 0x8d802000 ! 121: WRFPRS_I wr %r0, 0x0000, %fprs
.word 0xa0d9c00b ! 125: SMULcc_R smulcc %r7, %r11, %r16
brcommon2_20_54:
nop
nop
setx common_target, %r12, %r27
ba,a .+12
.word 0x9ba449d1 ! 1: FDIVd fdivd %f48, %f48, %f44
ba,a .+8
jmpl %r27-0, %r27
.word 0xc19fdf00 ! 129: LDDFA_R ldda [%r31, %r0], %f0
memptr_20_56:
set 0x60740000, %r31
.word 0x858229ad ! 133: WRCCR_I wr %r8, 0x09ad, %ccr
splash_lsu_20_58:
nop
nop
ta T_CHANGE_HPRIV
set 0x9155b10f, %r2
mov 0x2, %r1
sllx %r1, 32, %r1
or %r1, %r2, %r2
stxa %r2, [%r0] ASI_LSU_CONTROL
ta T_CHANGE_NONHPRIV
.word 0x3d400001 ! 137: FBPULE fbule,a,pn %fcc0, <label_0x1>
.word 0xda77e168 ! 141: STX_I stx %r13, [%r31 + 0x0168]
jmptr_20_65:
nop
nop
best_set_reg(0xe0200000, %r20, %r27)
.word 0xb7c6c000 ! 145: JMPL_R jmpl %r27 + %r0, %r27
.word 0x91d02032 ! 149: Tcc_I ta icc_or_xcc, %r0 + 50
.word 0xda800c60 ! 153: LDUWA_R lduwa [%r0, %r0] 0x63, %r13
fpinit_20_70:
nop
setx fp_data_quads, %r19, %r20
ldd [%r20], %f0
ldd [%r20+8], %f4
ld [%r20+16], %fsr
ld [%r20+24], %r19
wr %r19, %g0, %gsr
.word 0x87a80a44 ! 157: FCMPd fcmpd %fcc<n>, %f0, %f4
.word 0xc1bfdf00 ! 161: STDFA_R stda %f0, [%r0, %r31]
.word 0xdbe7c400 ! 165: CASA_I casa [%r31] 0x20, %r0, %r13
br_badelay3_20_78:
.word 0xa9a209d2 ! 1: FDIVd fdivd %f8, %f18, %f20
.word 0xc570c510 ! Random illegal ?
.word 0xd910c011 ! 1: LDQF_R - [%r3, %r17], %f12
.word 0xa5a3082b ! 169: FADDs fadds %f12, %f11, %f18
.word 0xd2c7c3c0 ! 173: LDSWA_R ldswa [%r31, %r0] 0x1e, %r9
nop
nop
ta T_CHANGE_HPRIV ! macro
donret_20_82:
rd %pc, %r12
mov HIGHVA_HIGHNUM, %r10
sllx %r10, 32, %r10
or %r12, %r10, %r12
add %r12, (donretarg_20_82-donret_20_82+4), %r12
add %r12, 0x4, %r11 ! seq tnpc
wrpr %g0, 0x2, %tl
wrpr %g0, %r12, %tpc
wrpr %g0, %r11, %tnpc
set (0x00d1d400 | (0x55 << 24)), %r13
and %r12, 0xfff, %r14
sllx %r14, 32, %r14
or %r13, %r14, %r20
wrpr %r20, %g0, %tstate
wrhpr %g0, 0x761, %htstate
wrhpr %g0, 0xf88, %hpstate ! rand=1 (20)
ldx [%r12+%r0], %g1
retry
donretarg_20_82:
.word 0xa5a4c9ca ! 177: FDIVd fdivd %f50, %f10, %f18
nop
nop
set 0xa6501021, %r28 !TTID : 0 (mask2tid(0x20))
#if (defined PORTABLE_CORE || MAX_THREADS == 8)
sethi %hi(0x3800), %r27
andn %r28, %r27, %r28
#ifdef PORTABLE_CORE
! Add CID to vector
ta T_CHANGE_HPRIV
ldxa [%g0]0x63, %r27
sllx %r27, 8, %r27
or %r27, %r28, %r28
#endif
#else
! Add CID IF tid matches
ifelse(0,mask2tid(0x20),`ta T_CHANGE_HPRIV;sethi %hi(0x3800), %r27;andn %r28, %r27, %r28;ldxa [%g0]0x63, %r27;sllx %r27, 8, %r27;or %r27, %r28, %r28 ')
#endif
sethi %hi(0x30000), %r27
andn %r28, %r27, %r28
ta T_CHANGE_HPRIV
ifelse(0,mask2tid(0x20),`.align 16')
stxa %r28, [%g0] 0x73
intvec_20_83:
.word 0x39400001 ! 181: FBPUGE fbuge,a,pn %fcc0, <label_0x1>
brcommon3_20_86:
nop
nop
setx common_target, %r12, %r27
lduw [%r27], %r12 ! Load common dest into dcache ..
stuw %r12, [%r27] ! Load common dest into dcache ..
ba,a .+12
.word 0xd86fe1c0 ! 1: LDSTUB_I ldstub %r12, [%r31 + 0x01c0]
ba,a .+8
jmpl %r27+0, %r27
stxa %r16, [%r0] ASI_LSU_CONTROL
.word 0xa3aac82d ! 185: FMOVGE fmovs %fcc1, %f13, %f17
cancelint_20_89:
rdhpr %halt, %r12
.word 0x85880000 ! 189: ALLCLEAN <illegal instruction>
.word 0xe927e100 ! 193: STF_I st %f20, [0x0100, %r31]
splash_lsu_20_94:
nop
nop
ta T_CHANGE_HPRIV
set 0x052aaa54, %r2
mov 0x2, %r1
sllx %r1, 32, %r1
or %r1, %r2, %r2
.word 0x39400001 ! 1: FBPUGE fbuge,a,pn %fcc0, <label_0x1>
stxa %r2, [%r0] ASI_LSU_CONTROL
ta T_CHANGE_NONHPRIV
.word 0x3d400001 ! 197: FBPULE fbule,a,pn %fcc0, <label_0x1>
.word 0xa190200b ! 201: WRPR_GL_I wrpr %r0, 0x000b, %-
br_badelay3_20_98:
.word 0x14800001 ! 1: BG bg <label_0x1>
.word 0xe753aa99 ! Random illegal ?
.word 0xa9a00553 ! 1: FSQRTd fsqrt
.word 0x99a40826 ! 205: FADDs fadds %f16, %f6, %f12
.word 0x8f902000 ! 1: WRPR_TL_I wrpr %r0, 0x0000, %tl
reduce_priv_lvl_20_99:
ta T_CHANGE_NONPRIV ! macro
splash_lsu_20_102:
nop
nop
ta T_CHANGE_HPRIV
set 0x61407687, %r2
mov 0x2, %r1
sllx %r1, 32, %r1
or %r1, %r2, %r2
stxa %r2, [%r0] ASI_LSU_CONTROL
ta T_CHANGE_NONHPRIV
.word 0x3d400002 ! 213: FBPULE fbule,a,pn %fcc0, <label_0x2>
.word 0x8d902675 ! 217: WRPR_PSTATE_I wrpr %r0, 0x0675, %pstate
.word 0xe49fc2e0 ! 221: LDDA_R ldda [%r31, %r0] 0x17, %r18
.word 0xc19fdd40 ! 225: LDDFA_R ldda [%r31, %r0], %f0
#if (defined SPC || defined CMP1)
!$EV trig_pc_d(1, expr(@VA(.MAIN.intvec_20_112) , 16, 16)) -> intp(6,0,25,*,728,*,3a,1)
!$EV trig_pc_d(1, expr((@VA(.MAIN.intvec_20_112)&0xffffffff) , 16, 16)) -> intp(5,0,29,*,944,*,3a,1)
#else
nop
nop
set 0xdbf08276, %r28 !TTID : 2 (mask2tid(0x20))
#if (defined PORTABLE_CORE || MAX_THREADS == 8)
sethi %hi(0x3800), %r27
andn %r28, %r27, %r28
#ifdef PORTABLE_CORE
! Add CID to vector
ta T_CHANGE_HPRIV
ldxa [%g0]0x63, %r27
sllx %r27, 8, %r27
or %r27, %r28, %r28
#endif
#else
! Add CID IF tid matches
ifelse(2,mask2tid(0x20),`ta T_CHANGE_HPRIV;sethi %hi(0x3800), %r27;andn %r28, %r27, %r28;ldxa [%g0]0x63, %r27;sllx %r27, 8, %r27;or %r27, %r28, %r28 ')
#endif
ifelse(2,mask2tid(0x20),`.align 16')
stxa %r28, [%g0] 0x73
#endif
intvec_20_112:
#if (defined SPC || defined CMP1)
wrhpr %g0, 0x0, %halt ! HALT
#else
ifelse(2,mask2tid(0x20),`wrhpr %g0, 0x0, %halt ! HALT')
#endif
.word 0x9ba0c9d3 ! 229: FDIVd fdivd %f34, %f50, %f44
jmptr_20_115:
nop
nop
best_set_reg(0xe1200000, %r20, %r27)
.word 0xb7c6c000 ! 233: JMPL_R jmpl %r27 + %r0, %r27
.word 0xd097c2c0 ! 237: LDUHA_R lduha [%r31, %r0] 0x16, %r8
intveclr_20_120:
nop
nop
ta T_CHANGE_HPRIV
setx 0x0dc0ca0badfbc54f, %r1, %r28
stxa %r28, [%g0] 0x72
wrhpr %g0, 0xe92, %hpstate ! ta T_CHANGE_NONHPRIV
.word 0x25400001 ! 241: FBPLG fblg,a,pn %fcc0, <label_0x1>
splash_lsu_20_122:
nop
nop
ta T_CHANGE_HPRIV
set 0xd2214611, %r2
mov 0x5, %r1
sllx %r1, 32, %r1
or %r1, %r2, %r2
.word 0x26800001 ! 1: BL bl,a <label_0x1>
stxa %r2, [%r0] ASI_LSU_CONTROL
ta T_CHANGE_NONHPRIV
.word 0x1d400001 ! 245: FBPULE fbule
.word 0xd137c000 ! 249: STQF_R - %f8, [%r0, %r31]
splash_lsu_20_125:
nop
nop
ta T_CHANGE_HPRIV
set 0x6c06bc0d, %r2
mov 0x6, %r1
sllx %r1, 32, %r1
or %r1, %r2, %r2
stxa %r2, [%r0] ASI_LSU_CONTROL
.word 0x1d400001 ! 253: FBPULE fbule
.word 0x8980000a ! 257: WRTICK_R wr %r0, %r10, %tick
.word 0xa1902009 ! 261: WRPR_GL_I wrpr %r0, 0x0009, %-
jmptr_20_133:
nop
nop
best_set_reg(0xe0200000, %r20, %r27)
.word 0xb7c6c000 ! 265: JMPL_R jmpl %r27 + %r0, %r27
nop
nop
mov 0x1, %r11
splash_cmpr_20_134:
sllx %r11, 63, %r11
not %r11, %r11
rd %tick, %r10
#if (defined SPC || defined CMP1)
add %r10, 0x200, %r10
#else
add %r10, 0x700, %r10
#endif
and %r10, %r11, %r10
rd %tick, %r10
#if (defined SPC || defined CMP1)
add %r10, 0x150, %r10
#else
add %r10, 0x900, %r10
#endif
and %r10, %r11, %r10
.word 0xb380000a ! 1: WR_STICK_CMPR_REG_R wr %r0, %r10, %-
#if (defined SPC || defined CMP1)
!$EV trig_pc_d(1, expr(@VA(.MAIN.splash_cmpr_20_134)+8 , 16, 16)) -> intp(5,0,17,*,704,*,6e,1)
!$EV trig_pc_d(1, expr((@VA(.MAIN.splash_cmpr_20_134)&0xffffffff)+8 , 16, 16)) -> intp(7,0,2,*,680,*,6e,1)
#endif
wrhpr %g0, 0x0, %halt ! HALT
.word 0x81b01021 ! 269: SIAM siam 1
jmptr_20_135:
nop
nop
best_set_reg(0xe1200000, %r20, %r27)
.word 0xb7c6c000 ! 273: JMPL_R jmpl %r27 + %r0, %r27
intveclr_20_136:
nop
nop
ta T_CHANGE_HPRIV
setx 0xa290dbd88fd74199, %r1, %r28
stxa %r28, [%g0] 0x72
.word 0x25400001 ! 277: FBPLG fblg,a,pn %fcc0, <label_0x1>
.word 0xd137e032 ! 281: STQF_I - %f8, [0x0032, %r31]
splash_hpstate_20_141:
.word 0x37400001 ! 1: FBPGE fbge,a,pn %fcc0, <label_0x1>
.word 0x81983657 ! 285: WRHPR_HPSTATE_I wrhpr %r0, 0x1657, %hpstate
intveclr_20_145:
nop
nop
ta T_CHANGE_HPRIV
setx 0xaf46a2408977bf58, %r1, %r28
stxa %r28, [%g0] 0x72
wrhpr %g0, 0xcb, %hpstate ! ta T_CHANGE_NONHPRIV
.word 0x05400001 ! 289: FBPLG fblg
brcommon1_20_148:
nop
nop
setx common_target, %r12, %r27
lduw [%r27-0], %r12 ! Load common dest into dcache ..
stuw %r12, [%r27-4] ! Load common dest into dcache ..
ba,a .+12
.word 0x91a7c9c0 ! 1: FDIVd fdivd %f62, %f0, %f8
ba,a .+8
jmpl %r27-0, %r27
.word 0x87aa8a50 ! 293: FCMPd fcmpd %fcc<n>, %f10, %f16
.word 0xd8dfc400 ! 297: LDXA_R ldxa [%r31, %r0] 0x20, %r12
.word 0x9194000c ! 301: WRPR_PIL_R wrpr %r16, %r12, %pil
demap_20_156:
nop
mov 0x80, %g3
ta T_CHANGE_HPRIV
.word 0x0cca8002 ! 1: BRGZ brgz,pt %r10,<label_0xa8002>
stxa %g3, [%g3] 0x57
.word 0x9d97c000 ! 1: WRPR_WSTATE_R wrpr %r31, %r0, %wstate
stxa %g3, [%g3] 0x5f
.word 0xbfefc000 ! 1: RESTORE_R restore %r31, %r0, %r31
stxa %g3, [%g3] 0x57
.word 0xbfefc000 ! 1: RESTORE_R restore %r31, %r0, %r31
stxa %g3, [%g3] 0x57
.word 0xbfefc000 ! 1: RESTORE_R restore %r31, %r0, %r31
stxa %g3, [%g3] 0x57
.word 0xbfe7c000 ! 1: SAVE_R save %r31, %r0, %r31
.word 0xbfe7c000 ! 1: SAVE_R save %r31, %r0, %r31
.word 0xbfefc000 ! 1: RESTORE_R restore %r31, %r0, %r31
wrhpr %g0, 0xb18, %hpstate ! ta T_CHANGE_NONHPRIV
.word 0xd81fe068 ! 305: LDD_I ldd [%r31 + 0x0068], %r12
.word 0x91914014 ! 309: WRPR_PIL_R wrpr %r5, %r20, %pil
.word 0xa7b204cc ! 313: FCMPNE32 fcmpne32 %d8, %d12, %r19
splash_lsu_20_163:
nop
nop
ta T_CHANGE_HPRIV
set 0x376761c1, %r2
mov 0x5, %r1
sllx %r1, 32, %r1
or %r1, %r2, %r2
.word 0x04cac001 ! 1: BRLEZ brlez,pt %r11,<label_0xac001>
stxa %r2, [%r0] ASI_LSU_CONTROL
ta T_CHANGE_NONHPRIV
.word 0x3d400001 ! 317: FBPULE fbule,a,pn %fcc0, <label_0x1>
splash_hpstate_20_166:
.word 0x8198205c ! 321: WRHPR_HPSTATE_I wrhpr %r0, 0x005c, %hpstate
nop
nop
ta T_CHANGE_HPRIV
mov 0x1, %r11
splash_cmpr_20_169:
sllx %r11, 63, %r11
not %r11, %r11
rd %tick, %r10
#if (defined SPC || defined CMP1)
add %r10, 0x250, %r10
#else
add %r10, 0x380, %r10
#endif
and %r10, %r11, %r10
wrhpr %r10, %g0, %hsys_tick_cmpr
wrhpr %g0, 0x0, %halt ! HALT
rd %tick, %r10
#if (defined SPC || defined CMP1)
add %r10, 0x300, %r10
#else
add %r10, 0x900, %r10
#endif
and %r10, %r11, %r10
.word 0xaf80000a ! 1: WR_TICK_CMPR_REG_R wr %r0, %r10, %-
#if (defined SPC || defined CMP1)
!$EV trig_pc_d(1, expr(@VA(.MAIN.splash_cmpr_20_169)+8 , 16, 16)) -> intp(5,0,9,*,920,*,a6,1)
!$EV trig_pc_d(1, expr((@VA(.MAIN.splash_cmpr_20_169)&0xffffffff)+8 , 16, 16)) -> intp(4,0,18,*,688,*,a6,1)
#endif
wrhpr %g0, 0x0, %halt ! HALT
.word 0x8198275f ! 1: WRHPR_HPSTATE_I wrhpr %r0, 0x075f, %hpstate
.word 0x81b01021 ! 325: SIAM siam 1
intveclr_20_171:
nop
nop
ta T_CHANGE_HPRIV
setx 0x679b56e52181359e, %r1, %r28
stxa %r28, [%g0] 0x72
wrhpr %g0, 0x74b, %hpstate ! ta T_CHANGE_NONHPRIV
.word 0x25400002 ! 329: FBPLG fblg,a,pn %fcc0, <label_0x2>
.word 0x91928012 ! 333: WRPR_PIL_R wrpr %r10, %r18, %pil
.word 0xc30fc000 ! 337: LDXFSR_R ld-fsr [%r31, %r0], %f1
demap_20_179:
nop
mov 0x80, %g3
ta T_CHANGE_HPRIV
.word 0x25400001 ! 1: FBPLG fblg,a,pn %fcc0, <label_0x1>
stxa %g3, [%g3] 0x57
.word 0x9d97c000 ! 1: WRPR_WSTATE_R wrpr %r31, %r0, %wstate
.word 0xbfe7c000 ! 1: SAVE_R save %r31, %r0, %r31
.word 0x9d97c000 ! 1: WRPR_WSTATE_R wrpr %r31, %r0, %wstate
stxa %g3, [%g3] 0x57
.word 0xbfefc000 ! 1: RESTORE_R restore %r31, %r0, %r31
.word 0x9d97c000 ! 1: WRPR_WSTATE_R wrpr %r31, %r0, %wstate
stxa %g3, [%g3] 0x5f
.word 0xbfefc000 ! 1: RESTORE_R restore %r31, %r0, %r31
.word 0xbfe7c000 ! 1: SAVE_R save %r31, %r0, %r31
stxa %g3, [%g3] 0x57
stxa %g3, [%g3] 0x57
wrhpr %g0, 0xe0b, %hpstate ! ta T_CHANGE_NONHPRIV
.word 0xd21fe1a0 ! 341: LDD_I ldd [%r31 + 0x01a0], %r9
.word 0xa190200c ! 345: WRPR_GL_I wrpr %r0, 0x000c, %-
nop
nop
mov 0x1, %r11
splash_cmpr_20_181:
sllx %r11, 63, %r11
not %r11, %r11
rd %tick, %r10
#if (defined SPC || defined CMP1)
add %r10, 0x250, %r10
#else
add %r10, 0x700, %r10
#endif
and %r10, %r11, %r10
rd %tick, %r10
#if (defined SPC || defined CMP1)
add %r10, 0x250, %r10
#else
add %r10, 0x900, %r10
#endif
and %r10, %r11, %r10
.word 0xaf80000a ! 1: WR_TICK_CMPR_REG_R wr %r0, %r10, %-
#if (defined SPC || defined CMP1)
!$EV trig_pc_d(1, expr(@VA(.MAIN.splash_cmpr_20_181)+8 , 16, 16)) -> intp(7,0,14,*,984,*,bd,1)
!$EV trig_pc_d(1, expr((@VA(.MAIN.splash_cmpr_20_181)&0xffffffff)+8 , 16, 16)) -> intp(2,0,29,*,680,*,bd,1)
#endif
wrhpr %g0, 0x0, %halt ! HALT
.word 0x81b01021 ! 349: SIAM siam 1
nop
nop
set 0x940062d9, %r28 !TTID : 2 (mask2tid(0x20))
#if (defined PORTABLE_CORE || MAX_THREADS == 8)
sethi %hi(0x3800), %r27
andn %r28, %r27, %r28
#ifdef PORTABLE_CORE
! Add CID to vector
ta T_CHANGE_HPRIV
ldxa [%g0]0x63, %r27
sllx %r27, 8, %r27
or %r27, %r28, %r28
#endif
#else
! Add CID IF tid matches
ifelse(2,mask2tid(0x20),`ta T_CHANGE_HPRIV;sethi %hi(0x3800), %r27;andn %r28, %r27, %r28;ldxa [%g0]0x63, %r27;sllx %r27, 8, %r27;or %r27, %r28, %r28 ')
#endif
sethi %hi(0x30000), %r27
andn %r28, %r27, %r28
ta T_CHANGE_HPRIV
ifelse(2,mask2tid(0x20),`.align 16')
stxa %r28, [%g0] 0x73
intvec_20_183:
.word 0x39400002 ! 353: FBPUGE fbuge,a,pn %fcc0, <label_0x2>
splash_tba_20_187:
nop
ta T_CHANGE_PRIV
setx 0x0000000400380000, %r11, %r12
.word 0x8b90000c ! 357: WRPR_TBA_R wrpr %r0, %r12, %tba
.word 0x0a780002 ! 361: BPCS <illegal instruction>
splash_lsu_20_191:
nop
nop
ta T_CHANGE_HPRIV
set 0x66c37b2e, %r2
mov 0x1, %r1
sllx %r1, 32, %r1
or %r1, %r2, %r2
stxa %r2, [%r0] ASI_LSU_CONTROL
ta T_CHANGE_NONHPRIV
.word 0x3d400001 ! 365: FBPULE fbule,a,pn %fcc0, <label_0x1>
#if (defined SPC || defined CMP1)
!$EV trig_pc_d(1, expr(@VA(.MAIN.intvec_20_194) , 16, 16)) -> intp(5,0,0,*,704,*,3f,1)
!$EV trig_pc_d(1, expr((@VA(.MAIN.intvec_20_194)&0xffffffff) , 16, 16)) -> intp(6,0,13,*,640,*,3f,1)
#else
nop
nop
set 0x6a203697, %r28 !TTID : 6 (mask2tid(0x20))
#if (defined PORTABLE_CORE || MAX_THREADS == 8)
sethi %hi(0x3800), %r27
andn %r28, %r27, %r28
#ifdef PORTABLE_CORE
! Add CID to vector
ta T_CHANGE_HPRIV
ldxa [%g0]0x63, %r27
sllx %r27, 8, %r27
or %r27, %r28, %r28
#endif
#else
! Add CID IF tid matches
ifelse(6,mask2tid(0x20),`ta T_CHANGE_HPRIV;sethi %hi(0x3800), %r27;andn %r28, %r27, %r28;ldxa [%g0]0x63, %r27;sllx %r27, 8, %r27;or %r27, %r28, %r28 ')
#endif
ifelse(6,mask2tid(0x20),`.align 16')
stxa %r28, [%g0] 0x73
#endif
intvec_20_194:
.word 0x9bb504cc ! 369: FCMPNE32 fcmpne32 %d20, %d12, %r13
#if (defined SPC || defined CMP1)
!$EV trig_pc_d(1, expr(@VA(.MAIN.intvec_20_196) , 16, 16)) -> intp(5,0,10,*,744,*,e4,1)
!$EV trig_pc_d(1, expr((@VA(.MAIN.intvec_20_196)&0xffffffff) , 16, 16)) -> intp(4,0,9,*,1016,*,e4,1)
#else
nop
nop
set 0x870a5f2, %r28 !TTID : 5 (mask2tid(0x20))
#if (defined PORTABLE_CORE || MAX_THREADS == 8)
sethi %hi(0x3800), %r27
andn %r28, %r27, %r28
#ifdef PORTABLE_CORE
! Add CID to vector
ta T_CHANGE_HPRIV
ldxa [%g0]0x63, %r27
sllx %r27, 8, %r27
or %r27, %r28, %r28
#endif
#else
! Add CID IF tid matches
ifelse(5,mask2tid(0x20),`ta T_CHANGE_HPRIV;sethi %hi(0x3800), %r27;andn %r28, %r27, %r28;ldxa [%g0]0x63, %r27;sllx %r27, 8, %r27;or %r27, %r28, %r28 ')
#endif
ifelse(5,mask2tid(0x20),`.align 16')
stxa %r28, [%g0] 0x73
#endif
intvec_20_196:
.word 0xa1b4c4d2 ! 373: FCMPNE32 fcmpne32 %d50, %d18, %r16
frzptr_20_199:
nop
nop
best_set_reg(0x3cb00000+0x1ffc, %r20, %r27)
jmpl %r27, %r27
.word 0x20800001 ! 377: BN bn,a <label_0x1>
.word 0x12800002 ! 381: BNE bne <label_0x2>
#if (defined SPC || defined CMP1)
!$EV trig_pc_d(1, expr(@VA(.MAIN.intvec_20_204) , 16, 16)) -> intp(2,0,14,*,712,*,27,1)
!$EV trig_pc_d(1, expr((@VA(.MAIN.intvec_20_204)&0xffffffff) , 16, 16)) -> intp(0,0,11,*,744,*,27,1)
#else
nop
nop
set 0x8b101e19, %r28 !TTID : 6 (mask2tid(0x20))
#if (defined PORTABLE_CORE || MAX_THREADS == 8)
sethi %hi(0x3800), %r27
andn %r28, %r27, %r28
#ifdef PORTABLE_CORE
! Add CID to vector
ta T_CHANGE_HPRIV
ldxa [%g0]0x63, %r27
sllx %r27, 8, %r27
or %r27, %r28, %r28
#endif
#else
! Add CID IF tid matches
ifelse(6,mask2tid(0x20),`ta T_CHANGE_HPRIV;sethi %hi(0x3800), %r27;andn %r28, %r27, %r28;ldxa [%g0]0x63, %r27;sllx %r27, 8, %r27;or %r27, %r28, %r28 ')
#endif
ifelse(6,mask2tid(0x20),`.align 16')
stxa %r28, [%g0] 0x73
#endif
intvec_20_204:
#if (defined SPC || defined CMP1)
wrhpr %g0, 0x0, %halt ! HALT
#else
ifelse(6,mask2tid(0x20),`wrhpr %g0, 0x0, %halt ! HALT')
#endif
.word 0x99b2c4c4 ! 385: FCMPNE32 fcmpne32 %d42, %d4, %r12
.word 0xa1b184c5 ! 389: FCMPNE32 fcmpne32 %d6, %d36, %r16
.word 0xd917c000 ! 393: LDQF_R - [%r31, %r0], %f12
demap_20_211:
nop
mov 0x80, %g3
ta T_CHANGE_HPRIV
stxa %g3, [%g3] 0x5f
stxa %g3, [%g3] 0x5f
wrhpr %g0, 0xc5a, %hpstate ! ta T_CHANGE_NONHPRIV
.word 0xd81fe173 ! 397: LDD_I ldd [%r31 + 0x0173], %r12
brcommon1_20_213:
nop
nop
setx common_target, %r12, %r27
lduw [%r27-4], %r12 ! Load common dest into dcache ..
stuw %r12, [%r27-0] ! Load common dest into dcache ..
ba,a .+12
.word 0x99a7c9c0 ! 1: FDIVd fdivd %f62, %f0, %f12
ba,a .+8
jmpl %r27-4, %r27
.word 0x87acca46 ! 401: FCMPd fcmpd %fcc<n>, %f50, %f6
nop
nop
set 0xf440dd67, %r28 !TTID : 5 (mask2tid(0x20))
#if (defined PORTABLE_CORE || MAX_THREADS == 8)
sethi %hi(0x3800), %r27
andn %r28, %r27, %r28
#ifdef PORTABLE_CORE
! Add CID to vector
ta T_CHANGE_HPRIV
ldxa [%g0]0x63, %r27
sllx %r27, 8, %r27
or %r27, %r28, %r28
#endif
#else
! Add CID IF tid matches
ifelse(5,mask2tid(0x20),`ta T_CHANGE_HPRIV;sethi %hi(0x3800), %r27;andn %r28, %r27, %r28;ldxa [%g0]0x63, %r27;sllx %r27, 8, %r27;or %r27, %r28, %r28 ')
#endif
sethi %hi(0x30000), %r27
andn %r28, %r27, %r28
ta T_CHANGE_HPRIV
ifelse(5,mask2tid(0x20),`.align 16')
stxa %r28, [%g0] 0x73
intvec_20_215:
.word 0xa7a309ca ! 405: FDIVd fdivd %f12, %f10, %f50
.word 0xe81fe0c0 ! 409: LDD_I ldd [%r31 + 0x00c0], %r20
.word 0x91904014 ! 413: WRPR_PIL_R wrpr %r1, %r20, %pil
.word 0xe19fe0c0 ! 417: LDDFA_I ldda [%r31, 0x00c0], %f16
.word 0xe937c000 ! 421: STQF_R - %f20, [%r0, %r31]
.word 0x35400001 ! 1: FBPUE fbue,a,pn %fcc0, <label_0x1>
br_longdelay5_20_224:
#if (defined SPC || defined CMP1)
!$EV trig_pc_d(1, expr((@VA(.MAIN.br_longdelay5_20_224)&0xffffffff) , 16, 16)) -> intp(mask2tid(0x20),0,0,*,664,*,ffffffffffffffff,1)
!$EV trig_pc_d(1, expr((@VA(.MAIN.br_longdelay5_20_224)) , 16, 16)) -> intp(mask2tid(0x20),0,0,*,720,*,ffffffffffffffff,1)
wrhpr %g0, 0x0, %halt ! HALT
#endif
.word 0xf16fe190 ! 425: PREFETCH_I prefetch [%r31 + 0x0190], #24
#if (defined SPC || defined CMP1)
!$EV trig_pc_d(1, expr(@VA(.MAIN.intvec_20_226) , 16, 16)) -> intp(4,0,0,*,640,*,34,1)
!$EV trig_pc_d(1, expr((@VA(.MAIN.intvec_20_226)&0xffffffff) , 16, 16)) -> intp(1,0,5,*,672,*,34,1)
#else
nop
nop
set 0x1da08db8, %r28 !TTID : 5 (mask2tid(0x20))
#if (defined PORTABLE_CORE || MAX_THREADS == 8)
sethi %hi(0x3800), %r27
andn %r28, %r27, %r28
#ifdef PORTABLE_CORE
! Add CID to vector
ta T_CHANGE_HPRIV
ldxa [%g0]0x63, %r27
sllx %r27, 8, %r27
or %r27, %r28, %r28
#endif
#else
! Add CID IF tid matches
ifelse(5,mask2tid(0x20),`ta T_CHANGE_HPRIV;sethi %hi(0x3800), %r27;andn %r28, %r27, %r28;ldxa [%g0]0x63, %r27;sllx %r27, 8, %r27;or %r27, %r28, %r28 ')
#endif
ifelse(5,mask2tid(0x20),`.align 16')
stxa %r28, [%g0] 0x73
#endif
intvec_20_226:
.word 0x91a449d0 ! 429: FDIVd fdivd %f48, %f16, %f8
jmptr_20_228:
nop
nop
best_set_reg(0xe0200000, %r20, %r27)
.word 0xb7c6c000 ! 433: JMPL_R jmpl %r27 + %r0, %r27
demap_20_232:
nop
mov 0x80, %g3
ta T_CHANGE_HPRIV
stxa %g3, [%g3] 0x5f
.word 0xbfefc000 ! 1: RESTORE_R restore %r31, %r0, %r31
.word 0xbfefc000 ! 1: RESTORE_R restore %r31, %r0, %r31
stxa %g3, [%g3] 0x5f
.word 0xbfe7c000 ! 1: SAVE_R save %r31, %r0, %r31
.word 0xbfe7c000 ! 1: SAVE_R save %r31, %r0, %r31
stxa %g3, [%g3] 0x5f
wrhpr %g0, 0x79b, %hpstate ! ta T_CHANGE_NONHPRIV
.word 0xda1fe104 ! 437: LDD_I ldd [%r31 + 0x0104], %r13
trapasi_20_235:
nop
mov 0x3e8, %r1 ! (VA for ASI 0x25)
.word 0xdad844a0 ! 441: LDXA_R ldxa [%r1, %r0] 0x25, %r13
.word 0xda57c000 ! 445: LDSH_R ldsh [%r31 + %r0], %r13
.word 0xda27e098 ! 449: STW_I stw %r13, [%r31 + 0x0098]
demap_20_240:
nop
mov 0x80, %g3
ta T_CHANGE_HPRIV
.word 0x24800001 ! 1: BLE ble,a <label_0x1>
stxa %g3, [%g3] 0x5f
.word 0xbfefc000 ! 1: RESTORE_R restore %r31, %r0, %r31
.word 0xbfe7c000 ! 1: SAVE_R save %r31, %r0, %r31
.word 0x9d97c000 ! 1: WRPR_WSTATE_R wrpr %r31, %r0, %wstate
stxa %g3, [%g3] 0x5f
.word 0xbfefc000 ! 1: RESTORE_R restore %r31, %r0, %r31
wrhpr %g0, 0xe5b, %hpstate ! ta T_CHANGE_NONHPRIV
.word 0xda1fe1ff ! 453: LDD_I ldd [%r31 + 0x01ff], %r13
.word 0xdb1fe1a0 ! 457: LDDF_I ldd [%r31, 0x01a0], %f13
.word 0xdbe7c3c0 ! 461: CASA_I casa [%r31] 0x1e, %r0, %r13
.word 0x9194000b ! 465: WRPR_PIL_R wrpr %r16, %r11, %pil
jmptr_20_253:
nop
nop
best_set_reg(0xe1200000, %r20, %r27)
.word 0xb7c6c000 ! 469: JMPL_R jmpl %r27 + %r0, %r27
.word 0xda77c000 ! 473: STX_R stx %r13, [%r31 + %r0]
splash_tba_20_259:
nop
ta T_CHANGE_PRIV
setx 0x0000000000380000, %r11, %r12
.word 0x8b90000c ! 477: WRPR_TBA_R wrpr %r0, %r12, %tba
#if (defined SPC || defined CMP1)
!$EV trig_pc_d(1, expr(@VA(.MAIN.intvec_20_262) , 16, 16)) -> intp(7,0,3,*,656,*,7f,1)
!$EV trig_pc_d(1, expr((@VA(.MAIN.intvec_20_262)&0xffffffff) , 16, 16)) -> intp(3,0,25,*,664,*,7f,1)
#else
nop
nop
set 0x54c0546a, %r28 !TTID : 4 (mask2tid(0x20))
#if (defined PORTABLE_CORE || MAX_THREADS == 8)
sethi %hi(0x3800), %r27
andn %r28, %r27, %r28
#ifdef PORTABLE_CORE
! Add CID to vector
ta T_CHANGE_HPRIV
ldxa [%g0]0x63, %r27
sllx %r27, 8, %r27
or %r27, %r28, %r28
#endif
#else
! Add CID IF tid matches
ifelse(4,mask2tid(0x20),`ta T_CHANGE_HPRIV;sethi %hi(0x3800), %r27;andn %r28, %r27, %r28;ldxa [%g0]0x63, %r27;sllx %r27, 8, %r27;or %r27, %r28, %r28 ')
#endif
ifelse(4,mask2tid(0x20),`.align 16')
stxa %r28, [%g0] 0x73
#endif
intvec_20_262:
#if (defined SPC || defined CMP1)
wrhpr %g0, 0x0, %halt ! HALT
#else
ifelse(4,mask2tid(0x20),`wrhpr %g0, 0x0, %halt ! HALT')
#endif
.word 0xa3b444c4 ! 481: FCMPNE32 fcmpne32 %d48, %d4, %r17
.word 0xe037e097 ! 485: STH_I sth %r16, [%r31 + 0x0097]
splash_lsu_20_263:
nop
nop
ta T_CHANGE_HPRIV
set 0xfad28fd0, %r2
mov 0x6, %r1
sllx %r1, 32, %r1
or %r1, %r2, %r2
.word 0x02800001 ! 1: BE be <label_0x1>
stxa %r2, [%r0] ASI_LSU_CONTROL
.word 0x3d400001 ! 489: FBPULE fbule,a,pn %fcc0, <label_0x1>
.word 0x8d903d03 ! 493: WRPR_PSTATE_I wrpr %r0, 0x1d03, %pstate
.word 0xe19fe1c0 ! 497: LDDFA_I ldda [%r31, 0x01c0], %f16
splash_tba_20_270:
nop
ta T_CHANGE_PRIV
set 0x120000, %r12
.word 0x8b90000c ! 501: WRPR_TBA_R wrpr %r0, %r12, %tba
.word 0xe11fe1b0 ! 505: LDDF_I ldd [%r31, 0x01b0], %f16
.word 0x8d802004 ! 509: WRFPRS_I wr %r0, 0x0004, %fprs
dvapa_20_277:
nop
nop
ta T_CHANGE_HPRIV
mov 0xbc5, %r20
mov 0x1a, %r19
sllx %r20, 23, %r20
or %r19, %r20, %r19
stxa %r19, [%g0] ASI_LSU_CONTROL
mov 0x38, %r18
stxa %r31, [%r18]0x58
wrhpr %g0, 0x392, %hpstate ! ta T_CHANGE_NONHPRIV
.word 0xe097c6c0 ! 513: LDUHA_R lduha [%r31, %r0] 0x36, %r16
jmptr_20_279:
nop
nop
best_set_reg(0xe0200000, %r20, %r27)
.word 0xb7c6c000 ! 517: JMPL_R jmpl %r27 + %r0, %r27
mondo_20_280:
nop
nop
.word 0x87802025 ! 1: WRASI_I wr %r0, 0x0025, %asi
stxa %r7, [%r0+0x3d0] %asi
stxa %r11, [%r0+0x3e0] %asi
.word 0x87802036 ! 1: WRASI_I wr %r0, 0x0036, %asi
.word 0x9d92c006 ! 521: WRPR_WSTATE_R wrpr %r11, %r6, %wstate
.word 0xe08fc6c0 ! 525: LDUBA_R lduba [%r31, %r0] 0x36, %r16
.word 0xf1efe130 ! 529: PREFETCHA_I prefetcha [%r31, + 0x0130] %asi, #24
.word 0x8d802000 ! 533: WRFPRS_I wr %r0, 0x0000, %fprs
mondo_20_286:
nop
nop
.word 0x87802025 ! 1: WRASI_I wr %r0, 0x0025, %asi
stxa %r19, [%r0+0x3c0] %asi
stxa %r17, [%r0+0x3e0] %asi
.word 0x87802016 ! 1: WRASI_I wr %r0, 0x0016, %asi
.word 0x9d904013 ! 537: WRPR_WSTATE_R wrpr %r1, %r19, %wstate
splash_tba_20_288:
nop
ta T_CHANGE_PRIV
setx 0x0000000400380000, %r11, %r12
.word 0x8b90000c ! 541: WRPR_TBA_R wrpr %r0, %r12, %tba
.word 0x08800001 ! 545: BLEU bleu <label_0x1>
nop
nop
ta T_CHANGE_HPRIV ! macro
donret_20_292:
rd %pc, %r12
mov HIGHVA_HIGHNUM, %r10
sllx %r10, 32, %r10
or %r12, %r10, %r12
add %r12, (donretarg_20_292-donret_20_292), %r12
add %r12, 0x8, %r11 ! nonseq tnpc
wrpr %g0, 0x1, %tl
wrpr %g0, %r12, %tpc
wrpr %g0, %r11, %tnpc
set (0x0074db00 | (22 << 24)), %r13
and %r12, 0xfff, %r14
sllx %r14, 32, %r14
or %r13, %r14, %r20
wrpr %r20, %g0, %tstate
wrhpr %g0, 0x1206, %htstate
best_set_reg(0x11a8, %g1, %g2)
wrpr %g0, %g2, %pstate ! rand=0 (20)
ldx [%r12+%r0], %g1
retry
donretarg_20_292:
.word 0x2a800001 ! 549: BCS bcs,a <label_0x1>
brcommon1_20_295:
nop
nop
setx common_target, %r12, %r27
lduw [%r27-0], %r12 ! Load common dest into dcache ..
stuw %r12, [%r27-4] ! Load common dest into dcache ..
ba,a .+12
.word 0xe1e7d060 ! 1: CASA_I casa [%r31] 0x83, %r0, %r16
ba,a .+8
jmpl %r27-4, %r27
.word 0xa5a489d1 ! 553: FDIVd fdivd %f18, %f48, %f18
nop
nop
ta T_CHANGE_HPRIV
mov 0x1, %r11
splash_cmpr_20_298:
sllx %r11, 63, %r11
not %r11, %r11
rd %tick, %r10
#if (defined SPC || defined CMP1)
add %r10, 0x200, %r10
#else
add %r10, 0x550, %r10
#endif
and %r10, %r11, %r10
wrhpr %r10, %g0, %hsys_tick_cmpr
wrhpr %g0, 0x0, %halt ! HALT
rd %tick, %r10
#if (defined SPC || defined CMP1)
add %r10, 0x300, %r10
#else
add %r10, 0x550, %r10
#endif
and %r10, %r11, %r10
.word 0xb380000a ! 1: WR_STICK_CMPR_REG_R wr %r0, %r10, %-
#if (defined SPC || defined CMP1)
!$EV trig_pc_d(1, expr(@VA(.MAIN.splash_cmpr_20_298)+8 , 16, 16)) -> intp(7,0,21,*,720,*,22,1)
!$EV trig_pc_d(1, expr((@VA(.MAIN.splash_cmpr_20_298)&0xffffffff)+8 , 16, 16)) -> intp(1,0,21,*,656,*,22,1)
#endif
wrhpr %g0, 0x0, %halt ! HALT
.word 0x81982d46 ! 1: WRHPR_HPSTATE_I wrhpr %r0, 0x0d46, %hpstate
.word 0x81b01021 ! 557: SIAM siam 1
.word 0x8980000a ! 561: WRTICK_R wr %r0, %r10, %tick
cancelint_20_302:
rdhpr %halt, %r9
.word 0x85880000 ! 565: ALLCLEAN <illegal instruction>
nop
nop
set 0x21000a0d, %r28 !TTID : 2 (mask2tid(0x20))
#if (defined PORTABLE_CORE || MAX_THREADS == 8)
sethi %hi(0x3800), %r27
andn %r28, %r27, %r28
#ifdef PORTABLE_CORE
! Add CID to vector
ta T_CHANGE_HPRIV
ldxa [%g0]0x63, %r27
sllx %r27, 8, %r27
or %r27, %r28, %r28
#endif
#else
! Add CID IF tid matches
ifelse(2,mask2tid(0x20),`ta T_CHANGE_HPRIV;sethi %hi(0x3800), %r27;andn %r28, %r27, %r28;ldxa [%g0]0x63, %r27;sllx %r27, 8, %r27;or %r27, %r28, %r28 ')
#endif
sethi %hi(0x30000), %r27
andn %r28, %r27, %r28
ta T_CHANGE_HPRIV
ifelse(2,mask2tid(0x20),`.align 16')
stxa %r28, [%g0] 0x73
intvec_20_305:
.word 0x19400001 ! 569: FBPUGE fbuge
.word 0xe2cfd920 ! 573: LDSBA_R ldsba [%r31, %r0] 0xc9, %r17
.word 0xa1902006 ! 577: WRPR_GL_I wrpr %r0, 0x0006, %-
nop
nop
set 0xd5f06ddc, %r28 !TTID : 5 (mask2tid(0x20))
#if (defined PORTABLE_CORE || MAX_THREADS == 8)
sethi %hi(0x3800), %r27
andn %r28, %r27, %r28
#ifdef PORTABLE_CORE
! Add CID to vector
ta T_CHANGE_HPRIV
ldxa [%g0]0x63, %r27
sllx %r27, 8, %r27
or %r27, %r28, %r28
#endif
#else
! Add CID IF tid matches
ifelse(5,mask2tid(0x20),`ta T_CHANGE_HPRIV;sethi %hi(0x3800), %r27;andn %r28, %r27, %r28;ldxa [%g0]0x63, %r27;sllx %r27, 8, %r27;or %r27, %r28, %r28 ')
#endif
sethi %hi(0x30000), %r27
andn %r28, %r27, %r28
ta T_CHANGE_HPRIV
ifelse(5,mask2tid(0x20),`.align 16')
stxa %r28, [%g0] 0x73
intvec_20_309:
.word 0x19400001 ! 581: FBPUGE fbuge
trapasi_20_313:
nop
mov 0x10, %r1 ! (VA for ASI 0x5b)
.word 0xe2d84b60 ! 585: LDXA_R ldxa [%r1, %r0] 0x5b, %r17
.word 0xe277e0ca ! 589: STX_I stx %r17, [%r31 + 0x00ca]
.word 0xe1bfdb20 ! 593: STDFA_R stda %f16, [%r0, %r31]
.word 0x8d902a36 ! 597: WRPR_PSTATE_I wrpr %r0, 0x0a36, %pstate
splash_lsu_20_322:
nop
nop
ta T_CHANGE_HPRIV
set 0x993cf2e3, %r2
mov 0x3, %r1
sllx %r1, 32, %r1
or %r1, %r2, %r2
.word 0x0b400001 ! 1: FBPUG fbug
stxa %r2, [%r0] ASI_LSU_CONTROL
.word 0x3d400001 ! 601: FBPULE fbule,a,pn %fcc0, <label_0x1>
.word 0x8980000a ! 605: WRTICK_R wr %r0, %r10, %tick
.word 0xe2dfc6c0 ! 609: LDXA_R ldxa [%r31, %r0] 0x36, %r17
jmptr_20_328:
nop
nop
best_set_reg(0xe1200000, %r20, %r27)
.word 0xb7c6c000 ! 613: JMPL_R jmpl %r27 + %r0, %r27
intveclr_20_330:
nop
nop
ta T_CHANGE_HPRIV
setx 0x2aad03986c479e9d, %r1, %r28
stxa %r28, [%g0] 0x72
wrhpr %g0, 0xe53, %hpstate ! ta T_CHANGE_NONHPRIV
.word 0x25400001 ! 617: FBPLG fblg,a,pn %fcc0, <label_0x1>
pmu_20_332:
nop
nop
setx 0xffffffb0ffffffae, %g1, %g7
.word 0xa3800007 ! 621: WR_PERF_COUNTER_R wr %r0, %r7, %-
.word 0x87802082 ! 625: WRASI_I wr %r0, 0x0082, %asi
splash_tba_20_337:
nop
ta T_CHANGE_PRIV
setx 0x0000000000380000, %r11, %r12
.word 0x8b90000c ! 629: WRPR_TBA_R wrpr %r0, %r12, %tba
#if (defined SPC || defined CMP1)
!$EV trig_pc_d(1, expr(@VA(.MAIN.intvec_20_338) , 16, 16)) -> intp(6,0,6,*,760,*,66,1)
!$EV trig_pc_d(1, expr((@VA(.MAIN.intvec_20_338)&0xffffffff) , 16, 16)) -> intp(0,0,26,*,680,*,66,1)
#else
nop
nop
set 0x68a0d124, %r28 !TTID : 1 (mask2tid(0x20))
#if (defined PORTABLE_CORE || MAX_THREADS == 8)
sethi %hi(0x3800), %r27
andn %r28, %r27, %r28
#ifdef PORTABLE_CORE
! Add CID to vector
ta T_CHANGE_HPRIV
ldxa [%g0]0x63, %r27
sllx %r27, 8, %r27
or %r27, %r28, %r28
#endif
#else
! Add CID IF tid matches
ifelse(1,mask2tid(0x20),`ta T_CHANGE_HPRIV;sethi %hi(0x3800), %r27;andn %r28, %r27, %r28;ldxa [%g0]0x63, %r27;sllx %r27, 8, %r27;or %r27, %r28, %r28 ')
#endif
ifelse(1,mask2tid(0x20),`.align 16')
stxa %r28, [%g0] 0x73
#endif
intvec_20_338:
.word 0xa3a289d1 ! 633: FDIVd fdivd %f10, %f48, %f48
br_longdelay3_20_340:
nop
not %g0, %r27
jmpl %r27+0, %r27
.word 0x81982b8f ! 637: WRHPR_HPSTATE_I wrhpr %r0, 0x0b8f, %hpstate
intveclr_20_343:
nop
nop
ta T_CHANGE_HPRIV
setx 0x74894d801c0d5559, %r1, %r28
stxa %r28, [%g0] 0x72
wrhpr %g0, 0x14b, %hpstate ! ta T_CHANGE_NONHPRIV
.word 0x25400002 ! 641: FBPLG fblg,a,pn %fcc0, <label_0x2>
ibp_20_344:
nop
nop
ta T_CHANGE_HPRIV
mov 8, %r18
rd %asi, %r12
wr %r0, 0x41, %asi
set sync_thr_counter4, %r23
#ifndef SPC
ldxa [%g0]0x63, %r8
and %r8, 0x38, %r8 ! Core ID
#ifndef PORTABLE_CORE
add %r8, %r23, %r23
#endif
#else
mov 0, %r8
#endif
mov 0x20, %r16
ibp_startwait20_344:
cas [%r23],%g0,%r16 !lock
brz,a %r16, continue_ibp_20_344
mov (~0x20&0xf0), %r16
ld [%r23], %r16
ibp_wait20_344:
brnz %r16, ibp_wait20_344
ld [%r23], %r16
ba ibp_startwait20_344
mov 0x20, %r16
continue_ibp_20_344:
sllx %r16, %r8, %r16 !Mask for my core only
ldxa [0x58]%asi, %r17 !Running_status
wait_for_stat_20_344:
ldxa [0x50]%asi, %r13 !Running_rw
cmp %r13, %r17
bne,a %xcc, wait_for_stat_20_344
ldxa [0x58]%asi, %r17 !Running_status
stxa %r16, [0x68]%asi !Park (W1C)
ldxa [0x50]%asi, %r14 !Running_rw
wait_for_ibp_20_344:
ldxa [0x58]%asi, %r17 !Running_status
cmp %r14, %r17
bne,a %xcc, wait_for_ibp_20_344
ldxa [0x50]%asi, %r14 !Running_rw
ibp_doit20_344:
best_set_reg(0x00000026dcb43a4d,%r19, %r20)
stxa %r20, [%r18]0x42
stxa %r16, [0x60] %asi !Unpark (W1S)
st %g0, [%r23] !clear lock
wr %r0, %r12, %asi !restore %asi
.word 0xe1bfda00 ! 645: STDFA_R stda %f16, [%r0, %r31]
.word 0xd5e7c3c0 ! 649: CASA_I casa [%r31] 0x1e, %r0, %r10
.word 0xd497c6c0 ! 653: LDUHA_R lduha [%r31, %r0] 0x36, %r10
jmptr_20_353:
nop
nop
best_set_reg(0xe0200000, %r20, %r27)
.word 0xb7c6c000 ! 657: JMPL_R jmpl %r27 + %r0, %r27
.word 0xd497c6c0 ! 661: LDUHA_R lduha [%r31, %r0] 0x36, %r10
.word 0xc19fe160 ! 665: LDDFA_I ldda [%r31, 0x0160], %f0
.word 0xc32fc000 ! 1: STXFSR_R st-sfr %f1, [%r0, %r31]
.word 0xd43fe1b0 ! 1: STD_I std %r10, [%r31 + 0x01b0]
mov 0xb1, %r30
.word 0x91d0001e ! 669: Tcc_R ta icc_or_xcc, %r0 + %r30
demap_20_359:
nop
mov 0x80, %g3
ta T_CHANGE_HPRIV
stxa %g3, [%g3] 0x57
.word 0xbfefc000 ! 1: RESTORE_R restore %r31, %r0, %r31
.word 0x9d97c000 ! 1: WRPR_WSTATE_R wrpr %r31, %r0, %wstate
.word 0xbfe7c000 ! 1: SAVE_R save %r31, %r0, %r31
stxa %g3, [%g3] 0x57
.word 0x9d97c000 ! 1: WRPR_WSTATE_R wrpr %r31, %r0, %wstate
.word 0xbfefc000 ! 1: RESTORE_R restore %r31, %r0, %r31
.word 0xbfe7c000 ! 1: SAVE_R save %r31, %r0, %r31
stxa %g3, [%g3] 0x57
.word 0xbfe7c000 ! 1: SAVE_R save %r31, %r0, %r31
stxa %g3, [%g3] 0x57
wrhpr %g0, 0xe90, %hpstate ! ta T_CHANGE_NONHPRIV
.word 0xd41fe06c ! 673: LDD_I ldd [%r31 + 0x006c], %r10
memptr_20_362:
set 0x60540000, %r31
.word 0x8584365d ! 677: WRCCR_I wr %r16, 0x165d, %ccr
jmptr_20_363:
nop
nop
best_set_reg(0xe1200000, %r20, %r27)
.word 0xb7c6c000 ! 681: JMPL_R jmpl %r27 + %r0, %r27
jmptr_20_366:
nop
nop
best_set_reg(0xe0200000, %r20, %r27)
.word 0xb7c6c000 ! 685: JMPL_R jmpl %r27 + %r0, %r27
memptr_20_369:
set user_data_start, %r31
.word 0x85817db6 ! 689: WRCCR_I wr %r5, 0x1db6, %ccr
nop
nop
ta T_CHANGE_HPRIV ! macro
donret_20_370:
rd %pc, %r12
mov HIGHVA_HIGHNUM, %r10
sllx %r10, 32, %r10
or %r12, %r10, %r12
add %r12, (donretarg_20_370-donret_20_370+4), %r12
add %r12, 0x4, %r11 ! seq tnpc
wrpr %g0, 0x2, %tl
wrpr %g0, %r12, %tpc
wrpr %g0, %r11, %tnpc
set (0x0006ff00 | (22 << 24)), %r13
and %r12, 0xfff, %r14
sllx %r14, 32, %r14
or %r13, %r14, %r20
wrpr %r20, %g0, %tstate
wrhpr %g0, 0x1cc5, %htstate
wrhpr %g0, 0x803, %hpstate ! rand=1 (20)
ldx [%r12+%r0], %g1
retry
donretarg_20_370:
.word 0xd46fe1b4 ! 693: LDSTUB_I ldstub %r10, [%r31 + 0x01b4]
brcommon3_20_371:
nop
nop
setx common_target, %r12, %r27
lduw [%r27-0], %r12 ! Load common dest into dcache ..
stuw %r12, [%r27-0] ! Load common dest into dcache ..
ba,a .+12
.word 0xd537e160 ! 1: STQF_I - %f10, [0x0160, %r31]
ba,a .+8
jmpl %r27-0, %r27
.word 0xd49fdc40 ! 697: LDDA_R ldda [%r31, %r0] 0xe2, %r10
.word 0xd477c000 ! 701: STX_R stx %r10, [%r31 + %r0]
.word 0xd537c000 ! 705: STQF_R - %f10, [%r0, %r31]
.word 0xc30fc000 ! 709: LDXFSR_R ld-fsr [%r31, %r0], %f1
.word 0x91944010 ! 713: WRPR_PIL_R wrpr %r17, %r16, %pil
.word 0xd48008a0 ! 717: LDUWA_R lduwa [%r0, %r0] 0x45, %r10
.word 0xd527e17e ! 721: STF_I st %f10, [0x017e, %r31]
intveclr_20_383:
nop
nop
ta T_CHANGE_HPRIV
setx 0x75cbae03a9be932b, %r1, %r28
stxa %r28, [%g0] 0x72
.word 0x25400001 ! 725: FBPLG fblg,a,pn %fcc0, <label_0x1>
demap_20_386:
nop
mov 0x80, %g3
ta T_CHANGE_HPRIV
stxa %g3, [%g3] 0x57
stxa %g3, [%g3] 0x5f
.word 0x9d97c000 ! 1: WRPR_WSTATE_R wrpr %r31, %r0, %wstate
.word 0xbfefc000 ! 1: RESTORE_R restore %r31, %r0, %r31
.word 0x9d97c000 ! 1: WRPR_WSTATE_R wrpr %r31, %r0, %wstate
stxa %g3, [%g3] 0x57
wrhpr %g0, 0xdcb, %hpstate ! ta T_CHANGE_NONHPRIV
.word 0xd41fe0c8 ! 729: LDD_I ldd [%r31 + 0x00c8], %r10
.word 0xd4bfe0e6 ! 733: STDA_I stda %r10, [%r31 + 0x00e6] %asi
memptr_20_389:
set 0x60740000, %r31
.word 0x8580e3dd ! 737: WRCCR_I wr %r3, 0x03dd, %ccr
.word 0x8980000a ! 741: WRTICK_R wr %r0, %r10, %tick
.word 0xd43fe0dc ! 745: STD_I std %r10, [%r31 + 0x00dc]
splash_lsu_20_393:
nop
nop
ta T_CHANGE_HPRIV
set 0xb3f556d8, %r2
mov 0x6, %r1
sllx %r1, 32, %r1
or %r1, %r2, %r2
stxa %r2, [%r0] ASI_LSU_CONTROL
.word 0x3d400001 ! 749: FBPULE fbule,a,pn %fcc0, <label_0x1>
br_longdelay4_20_395:
nop
not %g0, %r27
jmpl %r27+0, %r27
.word 0x9d902001 ! 753: WRPR_WSTATE_I wrpr %r0, 0x0001, %wstate
brcommon3_20_399:
nop
nop
setx common_target, %r12, %r27
lduw [%r27-0], %r12 ! Load common dest into dcache ..
stuw %r12, [%r27-4] ! Load common dest into dcache ..
ba,a .+12
.word 0xd46fe0a0 ! 1: LDSTUB_I ldstub %r10, [%r31 + 0x00a0]
ba,a .+8
jmpl %r27-4, %r27
.word 0xd51fe1a0 ! 757: LDDF_I ldd [%r31, 0x01a0], %f10
.word 0xc32fc000 ! 761: STXFSR_R st-sfr %f1, [%r0, %r31]
nop
nop
ta T_CHANGE_HPRIV
mov 0x1, %r11
splash_cmpr_20_403:
sllx %r11, 63, %r11
not %r11, %r11
rd %tick, %r10
#if (defined SPC || defined CMP1)
add %r10, 0x200, %r10
#else
add %r10, 0x550, %r10
#endif
and %r10, %r11, %r10
wrhpr %r10, %g0, %hsys_tick_cmpr
wrhpr %g0, 0x0, %halt ! HALT
rd %tick, %r10
#if (defined SPC || defined CMP1)
add %r10, 0x200, %r10
#else
add %r10, 0xc00, %r10
#endif
and %r10, %r11, %r10
.word 0xb380000a ! 1: WR_STICK_CMPR_REG_R wr %r0, %r10, %-
#if (defined SPC || defined CMP1)
!$EV trig_pc_d(1, expr(@VA(.MAIN.splash_cmpr_20_403)+8 , 16, 16)) -> intp(5,0,2,*,736,*,ec,1)
!$EV trig_pc_d(1, expr((@VA(.MAIN.splash_cmpr_20_403)&0xffffffff)+8 , 16, 16)) -> intp(0,0,3,*,1008,*,ec,1)
#endif
wrhpr %g0, 0x0, %halt ! HALT
.word 0x81982c55 ! 1: WRHPR_HPSTATE_I wrhpr %r0, 0x0c55, %hpstate
.word 0x81b01021 ! 765: SIAM siam 1
memptr_20_407:
set 0x60340000, %r31
.word 0x85853ed7 ! 769: WRCCR_I wr %r20, 0x1ed7, %ccr
br_badelay3_20_410:
.word 0x20800001 ! 1: BN bn,a <label_0x1>
.word 0xa5734183 ! Random illegal ?
.word 0xe9148006 ! 1: LDQF_R - [%r18, %r6], %f20
.word 0xa1a18832 ! 773: FADDs fadds %f6, %f18, %f16
splash_lsu_20_411:
nop
nop
ta T_CHANGE_HPRIV
set 0x4a2c7ba0, %r2
mov 0x5, %r1
sllx %r1, 32, %r1
or %r1, %r2, %r2
stxa %r2, [%r0] ASI_LSU_CONTROL
ta T_CHANGE_NONHPRIV
.word 0x3d400001 ! 777: FBPULE fbule,a,pn %fcc0, <label_0x1>
.word 0x26800001 ! 781: BL bl,a <label_0x1>
pmu_20_417:
nop
nop
ta T_CHANGE_PRIV
setx 0xffffffbfffffffa4, %g1, %g7
.word 0xa3800007 ! 785: WR_PERF_COUNTER_R wr %r0, %r7, %-
.word 0x81460000 ! 789: RD_STICK_REG stbar
demap_20_421:
nop
mov 0x80, %g3
ta T_CHANGE_HPRIV
.word 0x00800001 ! 1: BN bn <label_0x1>
stxa %g3, [%g3] 0x57
.word 0xbfefc000 ! 1: RESTORE_R restore %r31, %r0, %r31
.word 0xbfe7c000 ! 1: SAVE_R save %r31, %r0, %r31
stxa %g3, [%g3] 0x5f
.word 0x9d97c000 ! 1: WRPR_WSTATE_R wrpr %r31, %r0, %wstate
stxa %g3, [%g3] 0x57
.word 0xbfefc000 ! 1: RESTORE_R restore %r31, %r0, %r31
stxa %g3, [%g3] 0x5f
.word 0xbfe7c000 ! 1: SAVE_R save %r31, %r0, %r31
wrhpr %g0, 0xb98, %hpstate ! ta T_CHANGE_NONHPRIV
.word 0xd21fe088 ! 793: LDD_I ldd [%r31 + 0x0088], %r9
memptr_20_424:
set 0x60340000, %r31
.word 0x85853b3a ! 797: WRCCR_I wr %r20, 0x1b3a, %ccr
nop
nop
ta T_CHANGE_PRIV
wrpr %g0, %g0, %gl
nop
nop
.text
setx join_lbl_0_0, %g1, %g2
jmp %g2
nop
fork_lbl_0_5:
wrhpr %g0, 0xd92, %hpstate ! ta T_CHANGE_NONHPRIV
.word 0x1e800001 ! 1: BVC bvc <label_0x1>
.word 0x8d903814 ! 1: WRPR_PSTATE_I wrpr %r0, 0x1814, %pstate
frzptr_10_3:
nop
nop
best_set_reg(0x3cbc0000+0x1ffc, %r20, %r27)
ldx [%r27+0xc], %r20
jmpl %r27, %r27
.word 0xc19fde00 ! 5: LDDFA_R ldda [%r31, %r0], %f0
jmptr_10_5:
nop
nop
best_set_reg(0xe1a00000, %r20, %r27)
.word 0xb7c6c000 ! 9: JMPL_R jmpl %r27 + %r0, %r27
.word 0xc32fc000 ! 13: STXFSR_R st-sfr %f1, [%r0, %r31]
.word 0xda97d040 ! 17: LDUHA_R lduha [%r31, %r0] 0x82, %r13
jmptr_10_9:
nop
nop
best_set_reg(0xe0a00000, %r20, %r27)
.word 0xb7c6c000 ! 21: JMPL_R jmpl %r27 + %r0, %r27
.word 0x8980000a ! 25: WRTICK_R wr %r0, %r10, %tick
.word 0xda8008a0 ! 29: LDUWA_R lduwa [%r0, %r0] 0x45, %r13
.word 0xa5a1c9d0 ! 33: FDIVd fdivd %f38, %f16, %f18
.word 0xe28008a0 ! 37: LDUWA_R lduwa [%r0, %r0] 0x45, %r17
.word 0xe24fc000 ! 41: LDSB_R ldsb [%r31 + %r0], %r17
.word 0xa3a7c9c0 ! 1: FDIVd fdivd %f62, %f0, %f48
.word 0xe3e7c540 ! 1: CASA_I casa [%r31] 0x2a, %r0, %r17
mov 0x32, %r30
.word 0x93d0001e ! 45: Tcc_R tne icc_or_xcc, %r0 + %r30
demap_10_21:
nop
mov 0x80, %g3
ta T_CHANGE_HPRIV
.word 0x25400001 ! 1: FBPLG fblg,a,pn %fcc0, <label_0x1>
stxa %g3, [%g3] 0x5f
.word 0xe09fdc40 ! 1: LDDA_R ldda [%r31, %r0] 0xe2, %r16
wrhpr %g0, 0xd8, %hpstate ! ta T_CHANGE_NONHPRIV
.word 0xe21fe063 ! 49: LDD_I ldd [%r31 + 0x0063], %r17
.word 0xe247c000 ! 53: LDSW_R ldsw [%r31 + %r0], %r17
splash_lsu_10_22:
nop
nop
ta T_CHANGE_HPRIV
set 0xda1e7adb, %r2
mov 0x4, %r1
sllx %r1, 32, %r1
or %r1, %r2, %r2
.word 0x24cac001 ! 1: BRLEZ brlez,a,pt %r11,<label_0xac001>
stxa %r2, [%r0] ASI_LSU_CONTROL
.word 0x1d400001 ! 57: FBPULE fbule
demap_10_25:
nop
mov 0x80, %g3
ta T_CHANGE_HPRIV
.word 0x0cca0001 ! 1: BRGZ brgz,pt %r8,<label_0xa0001>
stxa %g3, [%g3] 0x5f
.word 0xe0bfdd40 ! 1: STDA_R stda %r16, [%r31 + %r0] 0xea
.word 0xc09fda00 ! 1: LDDA_R ldda [%r31, %r0] 0xd0, %r0
.word 0xe1bfdb20 ! 1: STDFA_R stda %f16, [%r0, %r31]
stxa %g3, [%g3] 0x5f
stxa %g3, [%g3] 0x5f
.word 0xe19fdd40 ! 1: LDDFA_R ldda [%r31, %r0], %f16
stxa %g3, [%g3] 0x5f
.word 0xc0bfda00 ! 1: STDA_R stda %r0, [%r31 + %r0] 0xd0
.word 0xe0bfdc00 ! 1: STDA_R stda %r16, [%r31 + %r0] 0xe0
.word 0xe19fc2c0 ! 1: LDDFA_R ldda [%r31, %r0], %f16
stxa %g3, [%g3] 0x5f
stxa %g3, [%g3] 0x5f
.word 0xe09fda60 ! 1: LDDA_R ldda [%r31, %r0] 0xd3, %r16
wrhpr %g0, 0x4ca, %hpstate ! ta T_CHANGE_NONHPRIV
.word 0xe21fe05a ! 61: LDD_I ldd [%r31 + 0x005a], %r17
nop
nop
mov 0x1, %r11
splash_cmpr_10_28:
sllx %r11, 63, %r11
not %r11, %r11
rd %tick, %r10
#if (defined SPC || defined CMP1)
add %r10, 0x150, %r10
#else
add %r10, 0x700, %r10
#endif
and %r10, %r11, %r10
rd %tick, %r10
#if (defined SPC || defined CMP1)
add %r10, 0x300, %r10
#else
add %r10, 0x700, %r10
#endif
and %r10, %r11, %r10
.word 0xb380000a ! 1: WR_STICK_CMPR_REG_R wr %r0, %r10, %-
#if (defined SPC || defined CMP1)
!$EV trig_pc_d(1, expr(@VA(.MAIN.splash_cmpr_10_28)+8 , 16, 16)) -> intp(2,0,22,*,744,*,1b,1)
!$EV trig_pc_d(1, expr((@VA(.MAIN.splash_cmpr_10_28)&0xffffffff)+8 , 16, 16)) -> intp(7,0,25,*,760,*,1b,1)
#endif
wrhpr %g0, 0x0, %halt ! HALT
.word 0x81b01021 ! 65: SIAM siam 1
.word 0xe19fe160 ! 69: LDDFA_I ldda [%r31, 0x0160], %f16
.word 0xa190200e ! 73: WRPR_GL_I wrpr %r0, 0x000e, %-
jmptr_10_34:
nop
nop
best_set_reg(0xe1a00000, %r20, %r27)
.word 0xb7c6c000 ! 77: JMPL_R jmpl %r27 + %r0, %r27
nop
nop
ta T_CHANGE_HPRIV ! macro
donret_10_35:
rd %pc, %r12
mov HIGHVA_HIGHNUM, %r10
sllx %r10, 32, %r10
or %r12, %r10, %r12
add %r12, (donretarg_10_35-donret_10_35+4), %r12
add %r12, 0x4, %r11 ! seq tnpc
andn %r11, %r10, %r11 ! low VA tnpc
wrpr %g0, 0x2, %tl
wrpr %g0, %r12, %tpc
wrpr %g0, %r11, %tnpc
set (0x00800700 | (0x88 << 24)), %r13
and %r12, 0xfff, %r14
sllx %r14, 32, %r14
or %r13, %r14, %r20
wrpr %r20, %g0, %tstate
wrhpr %g0, 0x1c4f, %htstate
best_set_reg(0x223, %g1, %g2)
wrpr %g0, %g2, %pstate ! rand=0 (10)
done
donretarg_10_35:
.word 0x8d9027e5 ! 81: WRPR_PSTATE_I wrpr %r0, 0x07e5, %pstate
#if (defined SPC || defined CMP1)
!$EV trig_pc_d(1, expr(@VA(.MAIN.intvec_10_36) , 16, 16)) -> intp(4,0,23,*,704,*,9a,1)
!$EV trig_pc_d(1, expr((@VA(.MAIN.intvec_10_36)&0xffffffff) , 16, 16)) -> intp(2,0,21,*,712,*,9a,1)
#else
nop
nop
set 0x89082dd, %r28 !TTID : 2 (mask2tid(0x10))
#if (defined PORTABLE_CORE || MAX_THREADS == 8)
sethi %hi(0x3800), %r27
andn %r28, %r27, %r28
#ifdef PORTABLE_CORE
! Add CID to vector
ta T_CHANGE_HPRIV
ldxa [%g0]0x63, %r27
sllx %r27, 8, %r27
or %r27, %r28, %r28
#endif
#else
! Add CID IF tid matches
ifelse(2,mask2tid(0x10),`ta T_CHANGE_HPRIV;sethi %hi(0x3800), %r27;andn %r28, %r27, %r28;ldxa [%g0]0x63, %r27;sllx %r27, 8, %r27;or %r27, %r28, %r28 ')
#endif
ifelse(2,mask2tid(0x10),`.align 16')
stxa %r28, [%g0] 0x73
#endif
intvec_10_36:
.word 0x39400001 ! 85: FBPUGE fbuge,a,pn %fcc0, <label_0x1>
.word 0x9684c003 ! 89: ADDcc_R addcc %r19, %r3, %r11
nop
nop
set 0xa0c0d673, %r28 !TTID : 6 (mask2tid(0x10))
#if (defined PORTABLE_CORE || MAX_THREADS == 8)
sethi %hi(0x3800), %r27
andn %r28, %r27, %r28
#ifdef PORTABLE_CORE
! Add CID to vector
ta T_CHANGE_HPRIV
ldxa [%g0]0x63, %r27
sllx %r27, 8, %r27
or %r27, %r28, %r28
#endif
#else
! Add CID IF tid matches
ifelse(6,mask2tid(0x10),`ta T_CHANGE_HPRIV;sethi %hi(0x3800), %r27;andn %r28, %r27, %r28;ldxa [%g0]0x63, %r27;sllx %r27, 8, %r27;or %r27, %r28, %r28 ')
#endif
sethi %hi(0x30000), %r27
andn %r28, %r27, %r28
ta T_CHANGE_HPRIV
ifelse(6,mask2tid(0x10),`.align 16')
stxa %r28, [%g0] 0x73
intvec_10_39:
.word 0xa1b504c4 ! 93: FCMPNE32 fcmpne32 %d20, %d4, %r16
.word 0x81460000 ! 97: RD_STICK_REG stbar
.word 0xe1e7c380 ! 101: CASA_I casa [%r31] 0x1c, %r0, %r16
.word 0x3c800001 ! 105: BPOS bpos,a <label_0x1>
nop
nop
set 0x89708502, %r28 !TTID : 5 (mask2tid(0x10))
#if (defined PORTABLE_CORE || MAX_THREADS == 8)
sethi %hi(0x3800), %r27
andn %r28, %r27, %r28
#ifdef PORTABLE_CORE
! Add CID to vector
ta T_CHANGE_HPRIV
ldxa [%g0]0x63, %r27
sllx %r27, 8, %r27
or %r27, %r28, %r28
#endif
#else
! Add CID IF tid matches
ifelse(5,mask2tid(0x10),`ta T_CHANGE_HPRIV;sethi %hi(0x3800), %r27;andn %r28, %r27, %r28;ldxa [%g0]0x63, %r27;sllx %r27, 8, %r27;or %r27, %r28, %r28 ')
#endif
sethi %hi(0x30000), %r27
andn %r28, %r27, %r28
ta T_CHANGE_HPRIV
ifelse(5,mask2tid(0x10),`.align 16')
stxa %r28, [%g0] 0x73
intvec_10_47:
.word 0xa7b404cd ! 109: FCMPNE32 fcmpne32 %d16, %d44, %r19
.word 0xd8800b60 ! 113: LDUWA_R lduwa [%r0, %r0] 0x5b, %r12
nop
nop
mov 0x1, %r11
splash_cmpr_10_52:
sllx %r11, 63, %r11
not %r11, %r11
rd %tick, %r10
#if (defined SPC || defined CMP1)
add %r10, 0x200, %r10
#else
add %r10, 0x700, %r10
#endif
and %r10, %r11, %r10
rd %tick, %r10
#if (defined SPC || defined CMP1)
add %r10, 0x200, %r10
#else
add %r10, 0x700, %r10
#endif
and %r10, %r11, %r10
.word 0xaf80000a ! 1: WR_TICK_CMPR_REG_R wr %r0, %r10, %-
#if (defined SPC || defined CMP1)
!$EV trig_pc_d(1, expr(@VA(.MAIN.splash_cmpr_10_52)+8 , 16, 16)) -> intp(6,0,13,*,1008,*,b2,1)
!$EV trig_pc_d(1, expr((@VA(.MAIN.splash_cmpr_10_52)&0xffffffff)+8 , 16, 16)) -> intp(1,0,5,*,944,*,b2,1)
#endif
wrhpr %g0, 0x0, %halt ! HALT
.word 0x81b01021 ! 117: SIAM siam 1
.word 0x8d802000 ! 121: WRFPRS_I wr %r0, 0x0000, %fprs
.word 0xa4da4004 ! 125: SMULcc_R smulcc %r9, %r4, %r18
brcommon2_10_54:
nop
nop
setx common_target, %r12, %r27
ba,a .+12
.word 0x9f8020d0 ! 1: SIR sir 0x00d0
ba,a .+8
jmpl %r27-0, %r27
.word 0xa1b7c7c0 ! 129: PDIST pdistn %d62, %d0, %d16
memptr_10_56:
set 0x60540000, %r31
.word 0x858420b7 ! 133: WRCCR_I wr %r16, 0x00b7, %ccr
splash_lsu_10_58:
nop
nop
ta T_CHANGE_HPRIV
set 0x1abd7c39, %r2
mov 0x3, %r1
sllx %r1, 32, %r1
or %r1, %r2, %r2
stxa %r2, [%r0] ASI_LSU_CONTROL
ta T_CHANGE_NONHPRIV
.word 0x3d400001 ! 137: FBPULE fbule,a,pn %fcc0, <label_0x1>
.word 0xda77e1a4 ! 141: STX_I stx %r13, [%r31 + 0x01a4]
jmptr_10_65:
nop
nop
best_set_reg(0xe0a00000, %r20, %r27)
.word 0xb7c6c000 ! 145: JMPL_R jmpl %r27 + %r0, %r27
.word 0x93d020b4 ! 149: Tcc_I tne icc_or_xcc, %r0 + 180
.word 0xda800aa0 ! 153: LDUWA_R lduwa [%r0, %r0] 0x55, %r13
fpinit_10_70:
nop
setx fp_data_quads, %r19, %r20
ldd [%r20], %f0
ldd [%r20+8], %f4
ld [%r20+16], %fsr
ld [%r20+24], %r19
wr %r19, %g0, %gsr
.word 0x87a80a44 ! 157: FCMPd fcmpd %fcc<n>, %f0, %f4
.word 0xe1bfda00 ! 161: STDFA_R stda %f16, [%r0, %r31]
.word 0xdabfdf00 ! 165: STDA_R stda %r13, [%r31 + %r0] 0xf8
br_badelay3_10_78:
.word 0x97a0c9c8 ! 1: FDIVd fdivd %f34, %f8, %f42
.word 0xd95efbb2 ! Random illegal ?
.word 0xe5114011 ! 1: LDQF_R - [%r5, %r17], %f18
.word 0x97a1c832 ! 169: FADDs fadds %f7, %f18, %f11
.word 0xd2c7c2e0 ! 173: LDSWA_R ldswa [%r31, %r0] 0x17, %r9
nop
nop
ta T_CHANGE_HPRIV ! macro
donret_10_82:
rd %pc, %r12
mov HIGHVA_HIGHNUM, %r10
sllx %r10, 32, %r10
or %r12, %r10, %r12
add %r12, (donretarg_10_82-donret_10_82+4), %r12
add %r12, 0x4, %r11 ! seq tnpc
wrpr %g0, 0x2, %tl
wrpr %g0, %r12, %tpc
wrpr %g0, %r11, %tnpc
set (0x00a25c00 | (0x58 << 24)), %r13
and %r12, 0xfff, %r14
sllx %r14, 32, %r14
or %r13, %r14, %r20
wrpr %r20, %g0, %tstate
wrhpr %g0, 0xdc5, %htstate
wrhpr %g0, 0x200, %hpstate ! rand=1 (10)
ldx [%r12+%r0], %g1
retry
donretarg_10_82:
.word 0x97a0c9d4 ! 177: FDIVd fdivd %f34, %f20, %f42
nop
nop
set 0x648020b0, %r28 !TTID : 0 (mask2tid(0x10))
#if (defined PORTABLE_CORE || MAX_THREADS == 8)
sethi %hi(0x3800), %r27
andn %r28, %r27, %r28
#ifdef PORTABLE_CORE
! Add CID to vector
ta T_CHANGE_HPRIV
ldxa [%g0]0x63, %r27
sllx %r27, 8, %r27
or %r27, %r28, %r28
#endif
#else
! Add CID IF tid matches
ifelse(0,mask2tid(0x10),`ta T_CHANGE_HPRIV;sethi %hi(0x3800), %r27;andn %r28, %r27, %r28;ldxa [%g0]0x63, %r27;sllx %r27, 8, %r27;or %r27, %r28, %r28 ')
#endif
sethi %hi(0x30000), %r27
andn %r28, %r27, %r28
ta T_CHANGE_HPRIV
ifelse(0,mask2tid(0x10),`.align 16')
stxa %r28, [%g0] 0x73
intvec_10_83:
.word 0xa9a409d2 ! 181: FDIVd fdivd %f16, %f18, %f20
brcommon3_10_86:
nop
nop
setx common_target, %r12, %r27
lduw [%r27], %r12 ! Load common dest into dcache ..
stuw %r12, [%r27] ! Load common dest into dcache ..
ba,a .+12
.word 0xd86fe150 ! 1: LDSTUB_I ldstub %r12, [%r31 + 0x0150]
ba,a .+8
jmpl %r27+0, %r27
stxa %r18, [%r0] ASI_LSU_CONTROL
.word 0xa1aac834 ! 185: FMOVGE fmovs %fcc1, %f20, %f16
cancelint_10_89:
rdhpr %halt, %r17
.word 0x85880000 ! 189: ALLCLEAN <illegal instruction>
.word 0xe927e170 ! 193: STF_I st %f20, [0x0170, %r31]
splash_lsu_10_94:
nop
nop
ta T_CHANGE_HPRIV
set 0x919e1d20, %r2
mov 0x7, %r1
sllx %r1, 32, %r1
or %r1, %r2, %r2
.word 0x30800001 ! 1: BA ba,a <label_0x1>
stxa %r2, [%r0] ASI_LSU_CONTROL
ta T_CHANGE_NONHPRIV
.word 0x1d400001 ! 197: FBPULE fbule
.word 0xa1902004 ! 201: WRPR_GL_I wrpr %r0, 0x0004, %-
br_badelay3_10_98:
.word 0x14800001 ! 1: BG bg <label_0x1>
.word 0xad4a8d15 ! Random illegal ?
.word 0xa5a00553 ! 1: FSQRTd fsqrt
.word 0xa1a34832 ! 205: FADDs fadds %f13, %f18, %f16
.word 0x8f902000 ! 1: WRPR_TL_I wrpr %r0, 0x0000, %tl
reduce_priv_lvl_10_99:
ta T_CHANGE_NONPRIV ! macro
splash_lsu_10_102:
nop
nop
ta T_CHANGE_HPRIV
set 0xa7188694, %r2
mov 0x6, %r1
sllx %r1, 32, %r1
or %r1, %r2, %r2
stxa %r2, [%r0] ASI_LSU_CONTROL
ta T_CHANGE_NONHPRIV
.word 0x3d400001 ! 213: FBPULE fbule,a,pn %fcc0, <label_0x1>
.word 0x8d903460 ! 217: WRPR_PSTATE_I wrpr %r0, 0x1460, %pstate
.word 0xe43fe1c0 ! 221: STD_I std %r18, [%r31 + 0x01c0]
.word 0xc19fdc00 ! 225: LDDFA_R ldda [%r31, %r0], %f0
#if (defined SPC || defined CMP1)
!$EV trig_pc_d(1, expr(@VA(.MAIN.intvec_10_112) , 16, 16)) -> intp(3,0,26,*,696,*,b7,1)
!$EV trig_pc_d(1, expr((@VA(.MAIN.intvec_10_112)&0xffffffff) , 16, 16)) -> intp(3,0,8,*,736,*,b7,1)
#else
nop
nop
set 0x9e80b418, %r28 !TTID : 4 (mask2tid(0x10))
#if (defined PORTABLE_CORE || MAX_THREADS == 8)
sethi %hi(0x3800), %r27
andn %r28, %r27, %r28
#ifdef PORTABLE_CORE
! Add CID to vector
ta T_CHANGE_HPRIV
ldxa [%g0]0x63, %r27
sllx %r27, 8, %r27
or %r27, %r28, %r28
#endif
#else
! Add CID IF tid matches
ifelse(4,mask2tid(0x10),`ta T_CHANGE_HPRIV;sethi %hi(0x3800), %r27;andn %r28, %r27, %r28;ldxa [%g0]0x63, %r27;sllx %r27, 8, %r27;or %r27, %r28, %r28 ')
#endif
ifelse(4,mask2tid(0x10),`.align 16')
stxa %r28, [%g0] 0x73
#endif
intvec_10_112:
#if (defined SPC || defined CMP1)
wrhpr %g0, 0x0, %halt ! HALT
#else
ifelse(4,mask2tid(0x10),`wrhpr %g0, 0x0, %halt ! HALT')
#endif
.word 0x95a489cc ! 229: FDIVd fdivd %f18, %f12, %f10
jmptr_10_115:
nop
nop
best_set_reg(0xe1a00000, %r20, %r27)
.word 0xb7c6c000 ! 233: JMPL_R jmpl %r27 + %r0, %r27
.word 0xd097d040 ! 237: LDUHA_R lduha [%r31, %r0] 0x82, %r8
intveclr_10_120:
nop
nop
ta T_CHANGE_HPRIV
setx 0xa4f87922fb7e8647, %r1, %r28
stxa %r28, [%g0] 0x72
wrhpr %g0, 0x590, %hpstate ! ta T_CHANGE_NONHPRIV
.word 0x25400001 ! 241: FBPLG fblg,a,pn %fcc0, <label_0x1>
splash_lsu_10_122:
nop
nop
ta T_CHANGE_HPRIV
set 0xe8acf802, %r2
mov 0x2, %r1
sllx %r1, 32, %r1
or %r1, %r2, %r2
.word 0x13400001 ! 1: FBPE fbe
stxa %r2, [%r0] ASI_LSU_CONTROL
ta T_CHANGE_NONHPRIV
.word 0x3d400001 ! 245: FBPULE fbule,a,pn %fcc0, <label_0x1>
.word 0xd137c000 ! 249: STQF_R - %f8, [%r0, %r31]
splash_lsu_10_125:
nop
nop
ta T_CHANGE_HPRIV
set 0x4f150317, %r2
mov 0x7, %r1
sllx %r1, 32, %r1
or %r1, %r2, %r2
stxa %r2, [%r0] ASI_LSU_CONTROL
.word 0x3d400001 ! 253: FBPULE fbule,a,pn %fcc0, <label_0x1>
.word 0x8980000a ! 257: WRTICK_R wr %r0, %r10, %tick
.word 0xa1902003 ! 261: WRPR_GL_I wrpr %r0, 0x0003, %-
jmptr_10_133:
nop
nop
best_set_reg(0xe0a00000, %r20, %r27)
.word 0xb7c6c000 ! 265: JMPL_R jmpl %r27 + %r0, %r27
nop
nop
mov 0x1, %r11
splash_cmpr_10_134:
sllx %r11, 63, %r11
not %r11, %r11
rd %tick, %r10
#if (defined SPC || defined CMP1)
add %r10, 0x250, %r10
#else
add %r10, 0xc00, %r10
#endif
and %r10, %r11, %r10
rd %tick, %r10
#if (defined SPC || defined CMP1)
add %r10, 0x200, %r10
#else
add %r10, 0x900, %r10
#endif
and %r10, %r11, %r10
.word 0xaf80000a ! 1: WR_TICK_CMPR_REG_R wr %r0, %r10, %-
#if (defined SPC || defined CMP1)
!$EV trig_pc_d(1, expr(@VA(.MAIN.splash_cmpr_10_134)+8 , 16, 16)) -> intp(1,0,31,*,952,*,b5,1)
!$EV trig_pc_d(1, expr((@VA(.MAIN.splash_cmpr_10_134)&0xffffffff)+8 , 16, 16)) -> intp(6,0,1,*,696,*,b5,1)
#endif
wrhpr %g0, 0x0, %halt ! HALT
.word 0x81b01021 ! 269: SIAM siam 1
jmptr_10_135:
nop
nop
best_set_reg(0xe1a00000, %r20, %r27)
.word 0xb7c6c000 ! 273: JMPL_R jmpl %r27 + %r0, %r27
intveclr_10_136:
nop
nop
ta T_CHANGE_HPRIV
setx 0x8453a5abe91ebcb6, %r1, %r28
stxa %r28, [%g0] 0x72
.word 0x25400001 ! 277: FBPLG fblg,a,pn %fcc0, <label_0x1>
.word 0xd137e004 ! 281: STQF_I - %f8, [0x0004, %r31]
splash_hpstate_10_141:
.word 0x26cc0001 ! 1: BRLZ brlz,a,pt %r16,<label_0xc0001>
.word 0x81983d15 ! 285: WRHPR_HPSTATE_I wrhpr %r0, 0x1d15, %hpstate
intveclr_10_145:
nop
nop
ta T_CHANGE_HPRIV
setx 0x46c388e96dd58f34, %r1, %r28
stxa %r28, [%g0] 0x72
wrhpr %g0, 0xec1, %hpstate ! ta T_CHANGE_NONHPRIV
.word 0x05400001 ! 289: FBPLG fblg
brcommon1_10_148:
nop
nop
setx common_target, %r12, %r27
lduw [%r27-4], %r12 ! Load common dest into dcache ..
stuw %r12, [%r27-0] ! Load common dest into dcache ..
ba,a .+12
.word 0x91a7c9c0 ! 1: FDIVd fdivd %f62, %f0, %f8
ba,a .+8
jmpl %r27-4, %r27
.word 0xa3a089a4 ! 293: FDIVs fdivs %f2, %f4, %f17
.word 0xd8dfd000 ! 297: LDXA_R ldxa [%r31, %r0] 0x80, %r12
.word 0x9192c005 ! 301: WRPR_PIL_R wrpr %r11, %r5, %pil
demap_10_156:
nop
mov 0x80, %g3
ta T_CHANGE_HPRIV
.word 0x38800001 ! 1: BGU bgu,a <label_0x1>
stxa %g3, [%g3] 0x57
.word 0xe1bfda60 ! 1: STDFA_R stda %f16, [%r0, %r31]
stxa %g3, [%g3] 0x5f
.word 0xc1bfda60 ! 1: STDFA_R stda %f0, [%r0, %r31]
stxa %g3, [%g3] 0x57
.word 0xe09fdf20 ! 1: LDDA_R ldda [%r31, %r0] 0xf9, %r16
stxa %g3, [%g3] 0x5f
.word 0xe09fde00 ! 1: LDDA_R ldda [%r31, %r0] 0xf0, %r16
stxa %g3, [%g3] 0x57
.word 0xc0bfdb20 ! 1: STDA_R stda %r0, [%r31 + %r0] 0xd9
.word 0xe09fdc40 ! 1: LDDA_R ldda [%r31, %r0] 0xe2, %r16
.word 0xe1bfc3e0 ! 1: STDFA_R stda %f16, [%r0, %r31]
wrhpr %g0, 0x9d0, %hpstate ! ta T_CHANGE_NONHPRIV
.word 0xd81fe1b8 ! 305: LDD_I ldd [%r31 + 0x01b8], %r12
.word 0x9194c00c ! 309: WRPR_PIL_R wrpr %r19, %r12, %pil
.word 0x87ad0a4b ! 313: FCMPd fcmpd %fcc<n>, %f20, %f42
splash_lsu_10_163:
nop
nop
ta T_CHANGE_HPRIV
set 0xfe93389f, %r2
mov 0x4, %r1
sllx %r1, 32, %r1
or %r1, %r2, %r2
.word 0x3d400001 ! 1: FBPULE fbule,a,pn %fcc0, <label_0x1>
stxa %r2, [%r0] ASI_LSU_CONTROL
ta T_CHANGE_NONHPRIV
.word 0x3d400001 ! 317: FBPULE fbule,a,pn %fcc0, <label_0x1>
splash_hpstate_10_166:
.word 0x81982fd3 ! 321: WRHPR_HPSTATE_I wrhpr %r0, 0x0fd3, %hpstate
nop
nop
ta T_CHANGE_HPRIV
mov 0x0, %r11
splash_cmpr_10_169:
sllx %r11, 63, %r11
not %r11, %r11
rd %tick, %r10
#if (defined SPC || defined CMP1)
add %r10, 0x150, %r10
#else
add %r10, 0xc00, %r10
#endif
and %r10, %r11, %r10
wrhpr %r10, %g0, %hsys_tick_cmpr
rd %tick, %r10
#if (defined SPC || defined CMP1)
add %r10, 0x100, %r10
#else
add %r10, 0x900, %r10
#endif
and %r10, %r11, %r10
.word 0xb380000a ! 1: WR_STICK_CMPR_REG_R wr %r0, %r10, %-
.word 0x819827d5 ! 1: WRHPR_HPSTATE_I wrhpr %r0, 0x07d5, %hpstate
.word 0x81b01021 ! 325: SIAM siam 1
intveclr_10_171:
nop
nop
ta T_CHANGE_HPRIV
setx 0xb426107e5afae688, %r1, %r28
stxa %r28, [%g0] 0x72
wrhpr %g0, 0x7d3, %hpstate ! ta T_CHANGE_NONHPRIV
.word 0x25400001 ! 329: FBPLG fblg,a,pn %fcc0, <label_0x1>
.word 0x91930003 ! 333: WRPR_PIL_R wrpr %r12, %r3, %pil
.word 0xc30fc000 ! 337: LDXFSR_R ld-fsr [%r31, %r0], %f1
demap_10_179:
nop
mov 0x80, %g3
ta T_CHANGE_HPRIV
.word 0x3e800001 ! 1: BVC bvc,a <label_0x1>
stxa %g3, [%g3] 0x57
.word 0xe1bfdb40 ! 1: STDFA_R stda %f16, [%r0, %r31]
.word 0xe09fc3e0 ! 1: LDDA_R ldda [%r31, %r0] 0x1f, %r16
.word 0xc0bfdc00 ! 1: STDA_R stda %r0, [%r31 + %r0] 0xe0
stxa %g3, [%g3] 0x57
.word 0xc1bfdf00 ! 1: STDFA_R stda %f0, [%r0, %r31]
.word 0xc0bfdf20 ! 1: STDA_R stda %r0, [%r31 + %r0] 0xf9
stxa %g3, [%g3] 0x57
.word 0xe09fdb20 ! 1: LDDA_R ldda [%r31, %r0] 0xd9, %r16
.word 0xc0bfdd40 ! 1: STDA_R stda %r0, [%r31 + %r0] 0xea
stxa %g3, [%g3] 0x5f
stxa %g3, [%g3] 0x57
wrhpr %g0, 0x2c0, %hpstate ! ta T_CHANGE_NONHPRIV
.word 0xd21fe180 ! 341: LDD_I ldd [%r31 + 0x0180], %r9
.word 0xa1902004 ! 345: WRPR_GL_I wrpr %r0, 0x0004, %-
nop
nop
mov 0x1, %r11
splash_cmpr_10_181:
sllx %r11, 63, %r11
not %r11, %r11
rd %tick, %r10
#if (defined SPC || defined CMP1)
add %r10, 0x150, %r10
#else
add %r10, 0x700, %r10
#endif
and %r10, %r11, %r10
rd %tick, %r10
#if (defined SPC || defined CMP1)
add %r10, 0x200, %r10
#else
add %r10, 0xc00, %r10
#endif
and %r10, %r11, %r10
.word 0xb380000a ! 1: WR_STICK_CMPR_REG_R wr %r0, %r10, %-
#if (defined SPC || defined CMP1)
!$EV trig_pc_d(1, expr(@VA(.MAIN.splash_cmpr_10_181)+8 , 16, 16)) -> intp(7,0,5,*,656,*,d1,1)
!$EV trig_pc_d(1, expr((@VA(.MAIN.splash_cmpr_10_181)&0xffffffff)+8 , 16, 16)) -> intp(7,0,22,*,1016,*,d1,1)
#endif
wrhpr %g0, 0x0, %halt ! HALT
.word 0x81b01021 ! 349: SIAM siam 1
nop
nop
set 0x35066c9, %r28 !TTID : 6 (mask2tid(0x10))
#if (defined PORTABLE_CORE || MAX_THREADS == 8)
sethi %hi(0x3800), %r27
andn %r28, %r27, %r28
#ifdef PORTABLE_CORE
! Add CID to vector
ta T_CHANGE_HPRIV
ldxa [%g0]0x63, %r27
sllx %r27, 8, %r27
or %r27, %r28, %r28
#endif
#else
! Add CID IF tid matches
ifelse(6,mask2tid(0x10),`ta T_CHANGE_HPRIV;sethi %hi(0x3800), %r27;andn %r28, %r27, %r28;ldxa [%g0]0x63, %r27;sllx %r27, 8, %r27;or %r27, %r28, %r28 ')
#endif
sethi %hi(0x30000), %r27
andn %r28, %r27, %r28
ta T_CHANGE_HPRIV
ifelse(6,mask2tid(0x10),`.align 16')
stxa %r28, [%g0] 0x73
intvec_10_183:
.word 0xa7a409c5 ! 353: FDIVd fdivd %f16, %f36, %f50
splash_tba_10_187:
nop
ta T_CHANGE_PRIV
setx 0x00000004003a0000, %r11, %r12
.word 0x8b90000c ! 357: WRPR_TBA_R wrpr %r0, %r12, %tba
.word 0x2a780001 ! 361: BPCS <illegal instruction>
splash_lsu_10_191:
nop
nop
ta T_CHANGE_HPRIV
set 0xa2aa04c4, %r2
mov 0x2, %r1
sllx %r1, 32, %r1
or %r1, %r2, %r2
stxa %r2, [%r0] ASI_LSU_CONTROL
ta T_CHANGE_NONHPRIV
.word 0x3d400001 ! 365: FBPULE fbule,a,pn %fcc0, <label_0x1>
#if (defined SPC || defined CMP1)
!$EV trig_pc_d(1, expr(@VA(.MAIN.intvec_10_194) , 16, 16)) -> intp(0,0,0,*,696,*,dc,1)
!$EV trig_pc_d(1, expr((@VA(.MAIN.intvec_10_194)&0xffffffff) , 16, 16)) -> intp(6,0,31,*,952,*,dc,1)
#else
nop
nop
set 0x43207c8d, %r28 !TTID : 4 (mask2tid(0x10))
#if (defined PORTABLE_CORE || MAX_THREADS == 8)
sethi %hi(0x3800), %r27
andn %r28, %r27, %r28
#ifdef PORTABLE_CORE
! Add CID to vector
ta T_CHANGE_HPRIV
ldxa [%g0]0x63, %r27
sllx %r27, 8, %r27
or %r27, %r28, %r28
#endif
#else
! Add CID IF tid matches
ifelse(4,mask2tid(0x10),`ta T_CHANGE_HPRIV;sethi %hi(0x3800), %r27;andn %r28, %r27, %r28;ldxa [%g0]0x63, %r27;sllx %r27, 8, %r27;or %r27, %r28, %r28 ')
#endif
ifelse(4,mask2tid(0x10),`.align 16')
stxa %r28, [%g0] 0x73
#endif
intvec_10_194:
.word 0xa3a449d3 ! 369: FDIVd fdivd %f48, %f50, %f48
#if (defined SPC || defined CMP1)
!$EV trig_pc_d(1, expr(@VA(.MAIN.intvec_10_196) , 16, 16)) -> intp(3,0,18,*,992,*,16,1)
!$EV trig_pc_d(1, expr((@VA(.MAIN.intvec_10_196)&0xffffffff) , 16, 16)) -> intp(3,0,12,*,640,*,16,1)
#else
nop
nop
set 0xf8c001f0, %r28 !TTID : 1 (mask2tid(0x10))
#if (defined PORTABLE_CORE || MAX_THREADS == 8)
sethi %hi(0x3800), %r27
andn %r28, %r27, %r28
#ifdef PORTABLE_CORE
! Add CID to vector
ta T_CHANGE_HPRIV
ldxa [%g0]0x63, %r27
sllx %r27, 8, %r27
or %r27, %r28, %r28
#endif
#else
! Add CID IF tid matches
ifelse(1,mask2tid(0x10),`ta T_CHANGE_HPRIV;sethi %hi(0x3800), %r27;andn %r28, %r27, %r28;ldxa [%g0]0x63, %r27;sllx %r27, 8, %r27;or %r27, %r28, %r28 ')
#endif
ifelse(1,mask2tid(0x10),`.align 16')
stxa %r28, [%g0] 0x73
#endif
intvec_10_196:
#if (defined SPC || defined CMP1)
wrhpr %g0, 0x0, %halt ! HALT
#else
ifelse(1,mask2tid(0x10),`wrhpr %g0, 0x0, %halt ! HALT')
#endif
.word 0xa3b504d0 ! 373: FCMPNE32 fcmpne32 %d20, %d16, %r17
frzptr_10_199:
nop
nop
best_set_reg(0x3cbc0000+0x1ffc, %r20, %r27)
jmpl %r27, %r27
.word 0x20800001 ! 377: BN bn,a <label_0x1>
.word 0x12800001 ! 381: BNE bne <label_0x1>
#if (defined SPC || defined CMP1)
!$EV trig_pc_d(1, expr(@VA(.MAIN.intvec_10_204) , 16, 16)) -> intp(2,0,6,*,752,*,52,1)
!$EV trig_pc_d(1, expr((@VA(.MAIN.intvec_10_204)&0xffffffff) , 16, 16)) -> intp(7,0,14,*,896,*,52,1)
#else
nop
nop
set 0x2320cbda, %r28 !TTID : 3 (mask2tid(0x10))
#if (defined PORTABLE_CORE || MAX_THREADS == 8)
sethi %hi(0x3800), %r27
andn %r28, %r27, %r28
#ifdef PORTABLE_CORE
! Add CID to vector
ta T_CHANGE_HPRIV
ldxa [%g0]0x63, %r27
sllx %r27, 8, %r27
or %r27, %r28, %r28
#endif
#else
! Add CID IF tid matches
ifelse(3,mask2tid(0x10),`ta T_CHANGE_HPRIV;sethi %hi(0x3800), %r27;andn %r28, %r27, %r28;ldxa [%g0]0x63, %r27;sllx %r27, 8, %r27;or %r27, %r28, %r28 ')
#endif
ifelse(3,mask2tid(0x10),`.align 16')
stxa %r28, [%g0] 0x73
#endif
intvec_10_204:
.word 0xa5a489cb ! 385: FDIVd fdivd %f18, %f42, %f18
.word 0x9bb504d0 ! 389: FCMPNE32 fcmpne32 %d20, %d16, %r13
.word 0xd917c000 ! 393: LDQF_R - [%r31, %r0], %f12
demap_10_211:
nop
mov 0x80, %g3
ta T_CHANGE_HPRIV
stxa %g3, [%g3] 0x5f
stxa %g3, [%g3] 0x57
wrhpr %g0, 0x2d3, %hpstate ! ta T_CHANGE_NONHPRIV
.word 0xd81fe0d0 ! 397: LDD_I ldd [%r31 + 0x00d0], %r12
brcommon1_10_213:
nop
nop
setx common_target, %r12, %r27
lduw [%r27-4], %r12 ! Load common dest into dcache ..
stuw %r12, [%r27-4] ! Load common dest into dcache ..
ba,a .+12
.word 0x99a7c9c0 ! 1: FDIVd fdivd %f62, %f0, %f12
ba,a .+8
jmpl %r27-4, %r27
.word 0x9170335c ! 401: POPC_I popc 0x135c, %r8
nop
nop
set 0x4650520e, %r28 !TTID : 2 (mask2tid(0x10))
#if (defined PORTABLE_CORE || MAX_THREADS == 8)
sethi %hi(0x3800), %r27
andn %r28, %r27, %r28
#ifdef PORTABLE_CORE
! Add CID to vector
ta T_CHANGE_HPRIV
ldxa [%g0]0x63, %r27
sllx %r27, 8, %r27
or %r27, %r28, %r28
#endif
#else
! Add CID IF tid matches
ifelse(2,mask2tid(0x10),`ta T_CHANGE_HPRIV;sethi %hi(0x3800), %r27;andn %r28, %r27, %r28;ldxa [%g0]0x63, %r27;sllx %r27, 8, %r27;or %r27, %r28, %r28 ')
#endif
sethi %hi(0x30000), %r27
andn %r28, %r27, %r28
ta T_CHANGE_HPRIV
ifelse(2,mask2tid(0x10),`.align 16')
stxa %r28, [%g0] 0x73
intvec_10_215:
.word 0x19400001 ! 405: FBPUGE fbuge
.word 0xe9e7c080 ! 409: CASA_I casa [%r31] 0x 4, %r0, %r20
.word 0x91924002 ! 413: WRPR_PIL_R wrpr %r9, %r2, %pil
.word 0xc19fe1c0 ! 417: LDDFA_I ldda [%r31, 0x01c0], %f0
.word 0xe937c000 ! 421: STQF_R - %f20, [%r0, %r31]
.word 0x34800001 ! 1: BG bg,a <label_0x1>
br_longdelay5_10_224:
#if (defined SPC || defined CMP1)
!$EV trig_pc_d(1, expr((@VA(.MAIN.br_longdelay5_10_224)&0xffffffff) , 16, 16)) -> intp(mask2tid(0x10),0,0,*,920,*,ffffffffffffffff,1)
!$EV trig_pc_d(1, expr((@VA(.MAIN.br_longdelay5_10_224)) , 16, 16)) -> intp(mask2tid(0x10),0,0,*,704,*,ffffffffffffffff,1)
wrhpr %g0, 0x0, %halt ! HALT
#endif
.word 0xf16fe060 ! 425: PREFETCH_I prefetch [%r31 + 0x0060], #24
#if (defined SPC || defined CMP1)
!$EV trig_pc_d(1, expr(@VA(.MAIN.intvec_10_226) , 16, 16)) -> intp(3,0,7,*,736,*,76,1)
!$EV trig_pc_d(1, expr((@VA(.MAIN.intvec_10_226)&0xffffffff) , 16, 16)) -> intp(6,0,27,*,752,*,76,1)
#else
nop
nop
set 0x58302a63, %r28 !TTID : 2 (mask2tid(0x10))
#if (defined PORTABLE_CORE || MAX_THREADS == 8)
sethi %hi(0x3800), %r27
andn %r28, %r27, %r28
#ifdef PORTABLE_CORE
! Add CID to vector
ta T_CHANGE_HPRIV
ldxa [%g0]0x63, %r27
sllx %r27, 8, %r27
or %r27, %r28, %r28
#endif
#else
! Add CID IF tid matches
ifelse(2,mask2tid(0x10),`ta T_CHANGE_HPRIV;sethi %hi(0x3800), %r27;andn %r28, %r27, %r28;ldxa [%g0]0x63, %r27;sllx %r27, 8, %r27;or %r27, %r28, %r28 ')
#endif
ifelse(2,mask2tid(0x10),`.align 16')
stxa %r28, [%g0] 0x73
#endif
intvec_10_226:
#if (defined SPC || defined CMP1)
wrhpr %g0, 0x0, %halt ! HALT
#else
ifelse(2,mask2tid(0x10),`wrhpr %g0, 0x0, %halt ! HALT')
#endif
.word 0xa5a2c9d1 ! 429: FDIVd fdivd %f42, %f48, %f18
jmptr_10_228:
nop
nop
best_set_reg(0xe0a00000, %r20, %r27)
.word 0xb7c6c000 ! 433: JMPL_R jmpl %r27 + %r0, %r27
demap_10_232:
nop
mov 0x80, %g3
ta T_CHANGE_HPRIV
stxa %g3, [%g3] 0x57
.word 0xe19fdd40 ! 1: LDDFA_R ldda [%r31, %r0], %f16
.word 0xc19fc2c0 ! 1: LDDFA_R ldda [%r31, %r0], %f0
stxa %g3, [%g3] 0x57
.word 0xc1bfc3e0 ! 1: STDFA_R stda %f0, [%r0, %r31]
.word 0xc19fde00 ! 1: LDDFA_R ldda [%r31, %r0], %f0
stxa %g3, [%g3] 0x5f
wrhpr %g0, 0x29b, %hpstate ! ta T_CHANGE_NONHPRIV
.word 0xda1fe1f8 ! 437: LDD_I ldd [%r31 + 0x01f8], %r13
trapasi_10_235:
nop
mov 0x3e0, %r1 ! (VA for ASI 0x25)
.word 0xdad844a0 ! 441: LDXA_R ldxa [%r1, %r0] 0x25, %r13
.word 0xda57c000 ! 445: LDSH_R ldsh [%r31 + %r0], %r13
.word 0xda27e082 ! 449: STW_I stw %r13, [%r31 + 0x0082]
demap_10_240:
nop
mov 0x80, %g3
ta T_CHANGE_HPRIV
.word 0x05400001 ! 1: FBPLG fblg
stxa %g3, [%g3] 0x5f
.word 0xe1bfdb20 ! 1: STDFA_R stda %f16, [%r0, %r31]
.word 0xc0bfdf20 ! 1: STDA_R stda %r0, [%r31 + %r0] 0xf9
.word 0xe1bfdc40 ! 1: STDFA_R stda %f16, [%r0, %r31]
stxa %g3, [%g3] 0x57
.word 0xc19fda00 ! 1: LDDFA_R ldda [%r31, %r0], %f0
wrhpr %g0, 0x50a, %hpstate ! ta T_CHANGE_NONHPRIV
.word 0xda1fe1b8 ! 453: LDD_I ldd [%r31 + 0x01b8], %r13
.word 0xdbe7c600 ! 457: CASA_I casa [%r31] 0x30, %r0, %r13
.word 0xc32fc000 ! 461: STXFSR_R st-sfr %f1, [%r0, %r31]
.word 0x91948011 ! 465: WRPR_PIL_R wrpr %r18, %r17, %pil
jmptr_10_253:
nop
nop
best_set_reg(0xe1a00000, %r20, %r27)
.word 0xb7c6c000 ! 469: JMPL_R jmpl %r27 + %r0, %r27
.word 0xda77c000 ! 473: STX_R stx %r13, [%r31 + %r0]
splash_tba_10_259:
nop
ta T_CHANGE_PRIV
setx 0x00000000003a0000, %r11, %r12
.word 0x8b90000c ! 477: WRPR_TBA_R wrpr %r0, %r12, %tba
#if (defined SPC || defined CMP1)
!$EV trig_pc_d(1, expr(@VA(.MAIN.intvec_10_262) , 16, 16)) -> intp(7,0,11,*,896,*,f8,1)
!$EV trig_pc_d(1, expr((@VA(.MAIN.intvec_10_262)&0xffffffff) , 16, 16)) -> intp(3,0,17,*,912,*,f8,1)
#else
nop
nop
set 0xfd607d12, %r28 !TTID : 5 (mask2tid(0x10))
#if (defined PORTABLE_CORE || MAX_THREADS == 8)
sethi %hi(0x3800), %r27
andn %r28, %r27, %r28
#ifdef PORTABLE_CORE
! Add CID to vector
ta T_CHANGE_HPRIV
ldxa [%g0]0x63, %r27
sllx %r27, 8, %r27
or %r27, %r28, %r28
#endif
#else
! Add CID IF tid matches
ifelse(5,mask2tid(0x10),`ta T_CHANGE_HPRIV;sethi %hi(0x3800), %r27;andn %r28, %r27, %r28;ldxa [%g0]0x63, %r27;sllx %r27, 8, %r27;or %r27, %r28, %r28 ')
#endif
ifelse(5,mask2tid(0x10),`.align 16')
stxa %r28, [%g0] 0x73
#endif
intvec_10_262:
#if (defined SPC || defined CMP1)
wrhpr %g0, 0x0, %halt ! HALT
#else
ifelse(5,mask2tid(0x10),`wrhpr %g0, 0x0, %halt ! HALT')
#endif
.word 0xa7b184d2 ! 481: FCMPNE32 fcmpne32 %d6, %d18, %r19
.word 0xe037e0a6 ! 485: STH_I sth %r16, [%r31 + 0x00a6]
splash_lsu_10_263:
nop
nop
ta T_CHANGE_HPRIV
set 0x92987b70, %r2
mov 0x1, %r1
sllx %r1, 32, %r1
or %r1, %r2, %r2
.word 0x07400001 ! 1: FBPUL fbul
stxa %r2, [%r0] ASI_LSU_CONTROL
.word 0x3d400001 ! 489: FBPULE fbule,a,pn %fcc0, <label_0x1>
.word 0x8d903ec3 ! 493: WRPR_PSTATE_I wrpr %r0, 0x1ec3, %pstate
.word 0xc19fe120 ! 497: LDDFA_I ldda [%r31, 0x0120], %f0
splash_tba_10_270:
nop
ta T_CHANGE_PRIV
set 0x120000, %r12
.word 0x8b90000c ! 501: WRPR_TBA_R wrpr %r0, %r12, %tba
.word 0xe11fe058 ! 505: LDDF_I ldd [%r31, 0x0058], %f16
.word 0x8d802000 ! 509: WRFPRS_I wr %r0, 0x0000, %fprs
dvapa_10_277:
nop
nop
ta T_CHANGE_HPRIV
mov 0xf50, %r20
mov 0x16, %r19
sllx %r20, 23, %r20
or %r19, %r20, %r19
stxa %r19, [%g0] ASI_LSU_CONTROL
mov 0x38, %r18
stxa %r31, [%r18]0x58
wrhpr %g0, 0x353, %hpstate ! ta T_CHANGE_NONHPRIV
.word 0xe13fe0a0 ! 513: STDF_I std %f16, [0x00a0, %r31]
jmptr_10_279:
nop
nop
best_set_reg(0xe0a00000, %r20, %r27)
.word 0xb7c6c000 ! 517: JMPL_R jmpl %r27 + %r0, %r27
mondo_10_280:
nop
nop
.word 0x87802025 ! 1: WRASI_I wr %r0, 0x0025, %asi
stxa %r8, [%r0+0x3e0] %asi
.word 0x8780201c ! 1: WRASI_I wr %r0, 0x001c, %asi
.word 0x9d95000a ! 521: WRPR_WSTATE_R wrpr %r20, %r10, %wstate
.word 0xe08fdd40 ! 525: LDUBA_R lduba [%r31, %r0] 0xea, %r16
.word 0xf1efe0f0 ! 529: PREFETCHA_I prefetcha [%r31, + 0x00f0] %asi, #24
.word 0x8d802004 ! 533: WRFPRS_I wr %r0, 0x0004, %fprs
mondo_10_286:
nop
nop
.word 0x87802025 ! 1: WRASI_I wr %r0, 0x0025, %asi
stxa %r9, [%r0+0x3e0] %asi
.word 0x8780201c ! 1: WRASI_I wr %r0, 0x001c, %asi
.word 0x9d940012 ! 537: WRPR_WSTATE_R wrpr %r16, %r18, %wstate
splash_tba_10_288:
nop
ta T_CHANGE_PRIV
setx 0x00000004003a0000, %r11, %r12
.word 0x8b90000c ! 541: WRPR_TBA_R wrpr %r0, %r12, %tba
.word 0x08800001 ! 545: BLEU bleu <label_0x1>
nop
nop
ta T_CHANGE_HPRIV ! macro
donret_10_292:
rd %pc, %r12
mov HIGHVA_HIGHNUM, %r10
sllx %r10, 32, %r10
or %r12, %r10, %r12
add %r12, (donretarg_10_292-donret_10_292), %r12
add %r12, 0x8, %r11 ! nonseq tnpc
wrpr %g0, 0x2, %tl
wrpr %g0, %r12, %tpc
wrpr %g0, %r11, %tnpc
set (0x00c5d300 | (16 << 24)), %r13
and %r12, 0xfff, %r14
sllx %r14, 32, %r14
or %r13, %r14, %r20
wrpr %r20, %g0, %tstate
wrhpr %g0, 0x7df, %htstate
best_set_reg(0x1421, %g1, %g2)
wrpr %g0, %g2, %pstate ! rand=0 (10)
ldx [%r12+%r0], %g1
retry
donretarg_10_292:
.word 0x2acc0001 ! 549: BRNZ brnz,a,pt %r16,<label_0xc0001>
brcommon1_10_295:
nop
nop
setx common_target, %r12, %r27
lduw [%r27-0], %r12 ! Load common dest into dcache ..
stuw %r12, [%r27-0] ! Load common dest into dcache ..
ba,a .+12
.word 0xe1e7d000 ! 1: CASA_I casa [%r31] 0x80, %r0, %r16
ba,a .+8
jmpl %r27-4, %r27
.word 0x87a8ca49 ! 553: FCMPd fcmpd %fcc<n>, %f34, %f40
nop
nop
ta T_CHANGE_HPRIV
mov 0x1, %r11
splash_cmpr_10_298:
sllx %r11, 63, %r11
not %r11, %r11
rd %tick, %r10
#if (defined SPC || defined CMP1)
add %r10, 0x250, %r10
#else
add %r10, 0x700, %r10
#endif
and %r10, %r11, %r10
wrhpr %r10, %g0, %hsys_tick_cmpr
wrhpr %g0, 0x0, %halt ! HALT
ta T_CHANGE_PRIV
rd %tick, %r10
#if (defined SPC || defined CMP1)
add %r10, 0x300, %r10
#else
add %r10, 0x900, %r10
#endif
and %r10, %r11, %r10
.word 0xb380000a ! 1: WR_STICK_CMPR_REG_R wr %r0, %r10, %-
#if (defined SPC || defined CMP1)
!$EV trig_pc_d(1, expr(@VA(.MAIN.splash_cmpr_10_298)+8 , 16, 16)) -> intp(3,0,2,*,728,*,d1,1)
!$EV trig_pc_d(1, expr((@VA(.MAIN.splash_cmpr_10_298)&0xffffffff)+8 , 16, 16)) -> intp(5,0,25,*,952,*,d1,1)
#endif
wrhpr %g0, 0x0, %halt ! HALT
.word 0x819834c4 ! 1: WRHPR_HPSTATE_I wrhpr %r0, 0x14c4, %hpstate
.word 0x81b01021 ! 557: SIAM siam 1
.word 0x8980000a ! 561: WRTICK_R wr %r0, %r10, %tick
cancelint_10_302:
rdhpr %halt, %r17
.word 0x85880000 ! 565: ALLCLEAN <illegal instruction>
nop
nop
set 0x78d0752a, %r28 !TTID : 5 (mask2tid(0x10))
#if (defined PORTABLE_CORE || MAX_THREADS == 8)
sethi %hi(0x3800), %r27
andn %r28, %r27, %r28
#ifdef PORTABLE_CORE
! Add CID to vector
ta T_CHANGE_HPRIV
ldxa [%g0]0x63, %r27
sllx %r27, 8, %r27
or %r27, %r28, %r28
#endif
#else
! Add CID IF tid matches
ifelse(5,mask2tid(0x10),`ta T_CHANGE_HPRIV;sethi %hi(0x3800), %r27;andn %r28, %r27, %r28;ldxa [%g0]0x63, %r27;sllx %r27, 8, %r27;or %r27, %r28, %r28 ')
#endif
sethi %hi(0x30000), %r27
andn %r28, %r27, %r28
ta T_CHANGE_HPRIV
ifelse(5,mask2tid(0x10),`.align 16')
stxa %r28, [%g0] 0x73
intvec_10_305:
.word 0xa5b344c3 ! 569: FCMPNE32 fcmpne32 %d44, %d34, %r18
.word 0xe2cfc380 ! 573: LDSBA_R ldsba [%r31, %r0] 0x1c, %r17
.word 0xa190200b ! 577: WRPR_GL_I wrpr %r0, 0x000b, %-
nop
nop
set 0x1420edef, %r28 !TTID : 5 (mask2tid(0x10))
#if (defined PORTABLE_CORE || MAX_THREADS == 8)
sethi %hi(0x3800), %r27
andn %r28, %r27, %r28
#ifdef PORTABLE_CORE
! Add CID to vector
ta T_CHANGE_HPRIV
ldxa [%g0]0x63, %r27
sllx %r27, 8, %r27
or %r27, %r28, %r28
#endif
#else
! Add CID IF tid matches
ifelse(5,mask2tid(0x10),`ta T_CHANGE_HPRIV;sethi %hi(0x3800), %r27;andn %r28, %r27, %r28;ldxa [%g0]0x63, %r27;sllx %r27, 8, %r27;or %r27, %r28, %r28 ')
#endif
sethi %hi(0x30000), %r27
andn %r28, %r27, %r28
ta T_CHANGE_HPRIV
ifelse(5,mask2tid(0x10),`.align 16')
stxa %r28, [%g0] 0x73
intvec_10_309:
.word 0x19400001 ! 581: FBPUGE fbuge
trapasi_10_313:
nop
mov 0x0, %r1 ! (VA for ASI 0x5b)
.word 0xe2d84b60 ! 585: LDXA_R ldxa [%r1, %r0] 0x5b, %r17
.word 0xe277e18c ! 589: STX_I stx %r17, [%r31 + 0x018c]
.word 0xc0bfde20 ! 593: STDA_R stda %r0, [%r31 + %r0] 0xf1
.word 0x8d90356d ! 597: WRPR_PSTATE_I wrpr %r0, 0x156d, %pstate
splash_lsu_10_322:
nop
nop
ta T_CHANGE_HPRIV
set 0x7b77f156, %r2
mov 0x6, %r1
sllx %r1, 32, %r1
or %r1, %r2, %r2
.word 0x28800001 ! 1: BLEU bleu,a <label_0x1>
stxa %r2, [%r0] ASI_LSU_CONTROL
.word 0x3d400001 ! 601: FBPULE fbule,a,pn %fcc0, <label_0x1>
.word 0x8980000a ! 605: WRTICK_R wr %r0, %r10, %tick
.word 0xe23fe040 ! 609: STD_I std %r17, [%r31 + 0x0040]
jmptr_10_328:
nop
nop
best_set_reg(0xe1a00000, %r20, %r27)
.word 0xb7c6c000 ! 613: JMPL_R jmpl %r27 + %r0, %r27
intveclr_10_330:
nop
nop
ta T_CHANGE_HPRIV
setx 0xabadc0bf8085a0ce, %r1, %r28
stxa %r28, [%g0] 0x72
wrhpr %g0, 0x3db, %hpstate ! ta T_CHANGE_NONHPRIV
.word 0x05400001 ! 617: FBPLG fblg
pmu_10_332:
nop
nop
setx 0xffffffb9ffffffa1, %g1, %g7
.word 0xa3800007 ! 621: WR_PERF_COUNTER_R wr %r0, %r7, %-
.word 0x87802080 ! 625: WRASI_I wr %r0, 0x0080, %asi
splash_tba_10_337:
nop
ta T_CHANGE_PRIV
setx 0x00000000003a0000, %r11, %r12
.word 0x8b90000c ! 629: WRPR_TBA_R wrpr %r0, %r12, %tba
#if (defined SPC || defined CMP1)
!$EV trig_pc_d(1, expr(@VA(.MAIN.intvec_10_338) , 16, 16)) -> intp(6,0,4,*,656,*,b8,1)
!$EV trig_pc_d(1, expr((@VA(.MAIN.intvec_10_338)&0xffffffff) , 16, 16)) -> intp(2,0,3,*,760,*,b8,1)
#else
nop
nop
set 0x23f010c5, %r28 !TTID : 0 (mask2tid(0x10))
#if (defined PORTABLE_CORE || MAX_THREADS == 8)
sethi %hi(0x3800), %r27
andn %r28, %r27, %r28
#ifdef PORTABLE_CORE
! Add CID to vector
ta T_CHANGE_HPRIV
ldxa [%g0]0x63, %r27
sllx %r27, 8, %r27
or %r27, %r28, %r28
#endif
#else
! Add CID IF tid matches
ifelse(0,mask2tid(0x10),`ta T_CHANGE_HPRIV;sethi %hi(0x3800), %r27;andn %r28, %r27, %r28;ldxa [%g0]0x63, %r27;sllx %r27, 8, %r27;or %r27, %r28, %r28 ')
#endif
ifelse(0,mask2tid(0x10),`.align 16')
stxa %r28, [%g0] 0x73
#endif
intvec_10_338:
.word 0x93a2c9cb ! 633: FDIVd fdivd %f42, %f42, %f40
br_longdelay3_10_340:
nop
not %g0, %r27
jmpl %r27+0, %r27
.word 0x81983597 ! 637: WRHPR_HPSTATE_I wrhpr %r0, 0x1597, %hpstate
intveclr_10_343:
nop
nop
ta T_CHANGE_HPRIV
setx 0x137d22ef6ad0b7a2, %r1, %r28
stxa %r28, [%g0] 0x72
wrhpr %g0, 0x5b, %hpstate ! ta T_CHANGE_NONHPRIV
.word 0x25400001 ! 641: FBPLG fblg,a,pn %fcc0, <label_0x1>
ibp_10_344:
nop
nop
.word 0xc1bfdd40 ! 645: STDFA_R stda %f0, [%r0, %r31]
.word 0xc32fc000 ! 649: STXFSR_R st-sfr %f1, [%r0, %r31]
.word 0xd497d160 ! 653: LDUHA_R lduha [%r31, %r0] 0x8b, %r10
jmptr_10_353:
nop
nop
best_set_reg(0xe0a00000, %r20, %r27)
.word 0xb7c6c000 ! 657: JMPL_R jmpl %r27 + %r0, %r27
.word 0xd497c540 ! 661: LDUHA_R lduha [%r31, %r0] 0x2a, %r10
.word 0xc19fe100 ! 665: LDDFA_I ldda [%r31, 0x0100], %f0
.word 0xd5e7e000 ! 1: CASA_R casa [%r31] %asi, %r0, %r10
.word 0xd5e7c400 ! 1: CASA_I casa [%r31] 0x20, %r0, %r10
mov 0x34, %r30
.word 0x93d0001e ! 669: Tcc_R tne icc_or_xcc, %r0 + %r30
demap_10_359:
nop
mov 0x80, %g3
ta T_CHANGE_HPRIV
stxa %g3, [%g3] 0x57
.word 0xe1bfde00 ! 1: STDFA_R stda %f16, [%r0, %r31]
.word 0xe0bfdb40 ! 1: STDA_R stda %r16, [%r31 + %r0] 0xda
.word 0xe09fde00 ! 1: LDDA_R ldda [%r31, %r0] 0xf0, %r16
stxa %g3, [%g3] 0x5f
.word 0xe1bfc2c0 ! 1: STDFA_R stda %f16, [%r0, %r31]
.word 0xe19fc3e0 ! 1: LDDFA_R ldda [%r31, %r0], %f16
.word 0xc19fdc00 ! 1: LDDFA_R ldda [%r31, %r0], %f0
stxa %g3, [%g3] 0x57
.word 0xc09fdc00 ! 1: LDDA_R ldda [%r31, %r0] 0xe0, %r0
stxa %g3, [%g3] 0x5f
wrhpr %g0, 0x3d0, %hpstate ! ta T_CHANGE_NONHPRIV
.word 0xd41fe058 ! 673: LDD_I ldd [%r31 + 0x0058], %r10
memptr_10_362:
set 0x60140000, %r31
.word 0x858532cb ! 677: WRCCR_I wr %r20, 0x12cb, %ccr
jmptr_10_363:
nop
nop
best_set_reg(0xe1a00000, %r20, %r27)
.word 0xb7c6c000 ! 681: JMPL_R jmpl %r27 + %r0, %r27
jmptr_10_366:
nop
nop
best_set_reg(0xe0a00000, %r20, %r27)
.word 0xb7c6c000 ! 685: JMPL_R jmpl %r27 + %r0, %r27
memptr_10_369:
set user_data_start, %r31
.word 0x8580a799 ! 689: WRCCR_I wr %r2, 0x0799, %ccr
nop
nop
ta T_CHANGE_HPRIV ! macro
donret_10_370:
rd %pc, %r12
mov HIGHVA_HIGHNUM, %r10
sllx %r10, 32, %r10
or %r12, %r10, %r12
add %r12, (donretarg_10_370-donret_10_370+4), %r12
add %r12, 0x4, %r11 ! seq tnpc
wrpr %g0, 0x1, %tl
wrpr %g0, %r12, %tpc
wrpr %g0, %r11, %tnpc
set (0x0052e100 | (48 << 24)), %r13
and %r12, 0xfff, %r14
sllx %r14, 32, %r14
or %r13, %r14, %r20
wrpr %r20, %g0, %tstate
wrhpr %g0, 0x68d, %htstate
wrhpr %g0, 0x39b, %hpstate ! rand=1 (10)
ldx [%r12+%r0], %g1
retry
donretarg_10_370:
.word 0xd46fe078 ! 693: LDSTUB_I ldstub %r10, [%r31 + 0x0078]
brcommon3_10_371:
nop
nop
setx common_target, %r12, %r27
lduw [%r27-4], %r12 ! Load common dest into dcache ..
stuw %r12, [%r27-0] ! Load common dest into dcache ..
ba,a .+12
.word 0xd537e1b0 ! 1: STQF_I - %f10, [0x01b0, %r31]
ba,a .+8
jmpl %r27-0, %r27
.word 0xd4bfc240 ! 697: STDA_R stda %r10, [%r31 + %r0] 0x12
.word 0xd477c000 ! 701: STX_R stx %r10, [%r31 + %r0]
.word 0xd537c000 ! 705: STQF_R - %f10, [%r0, %r31]
.word 0xf16fe0f6 ! 709: PREFETCH_I prefetch [%r31 + 0x00f6], #24
.word 0x91928013 ! 713: WRPR_PIL_R wrpr %r10, %r19, %pil
.word 0xd4800a60 ! 717: LDUWA_R lduwa [%r0, %r0] 0x53, %r10
.word 0xd527e122 ! 721: STF_I st %f10, [0x0122, %r31]
intveclr_10_383:
nop
nop
ta T_CHANGE_HPRIV
setx 0xa672847e07c60c63, %r1, %r28
stxa %r28, [%g0] 0x72
.word 0x05400001 ! 725: FBPLG fblg
demap_10_386:
nop
mov 0x80, %g3
ta T_CHANGE_HPRIV
stxa %g3, [%g3] 0x57
stxa %g3, [%g3] 0x5f
.word 0xe1bfde00 ! 1: STDFA_R stda %f16, [%r0, %r31]
.word 0xe19fde20 ! 1: LDDFA_R ldda [%r31, %r0], %f16
.word 0xc19fdd40 ! 1: LDDFA_R ldda [%r31, %r0], %f0
stxa %g3, [%g3] 0x5f
wrhpr %g0, 0x801, %hpstate ! ta T_CHANGE_NONHPRIV
.word 0xd41fe11a ! 729: LDD_I ldd [%r31 + 0x011a], %r10
.word 0xd4bfe1a4 ! 733: STDA_I stda %r10, [%r31 + 0x01a4] %asi
memptr_10_389:
set 0x60340000, %r31
.word 0x8581b879 ! 737: WRCCR_I wr %r6, 0x1879, %ccr
.word 0x8980000a ! 741: WRTICK_R wr %r0, %r10, %tick
.word 0xd43fe1f4 ! 745: STD_I std %r10, [%r31 + 0x01f4]
splash_lsu_10_393:
nop
nop
ta T_CHANGE_HPRIV
set 0x7f427f06, %r2
mov 0x3, %r1
sllx %r1, 32, %r1
or %r1, %r2, %r2
stxa %r2, [%r0] ASI_LSU_CONTROL
.word 0x3d400001 ! 749: FBPULE fbule,a,pn %fcc0, <label_0x1>
br_longdelay4_10_395:
nop
not %g0, %r27
jmpl %r27+0, %r27
.word 0x9d902001 ! 753: WRPR_WSTATE_I wrpr %r0, 0x0001, %wstate
brcommon3_10_399:
nop
nop
setx common_target, %r12, %r27
lduw [%r27-4], %r12 ! Load common dest into dcache ..
stuw %r12, [%r27-0] ! Load common dest into dcache ..
ba,a .+12
.word 0xd46fe0f0 ! 1: LDSTUB_I ldstub %r10, [%r31 + 0x00f0]
ba,a .+8
jmpl %r27-4, %r27
.word 0xd51fe090 ! 757: LDDF_I ldd [%r31, 0x0090], %f10
.word 0xd43fe095 ! 761: STD_I std %r10, [%r31 + 0x0095]
nop
nop
ta T_CHANGE_HPRIV
mov 0x1, %r11
splash_cmpr_10_403:
sllx %r11, 63, %r11
not %r11, %r11
rd %tick, %r10
#if (defined SPC || defined CMP1)
add %r10, 0x200, %r10
#else
add %r10, 0x900, %r10
#endif
and %r10, %r11, %r10
wrhpr %r10, %g0, %hsys_tick_cmpr
wrhpr %g0, 0x0, %halt ! HALT
rd %tick, %r10
#if (defined SPC || defined CMP1)
add %r10, 0x250, %r10
#else
add %r10, 0x700, %r10
#endif
and %r10, %r11, %r10
.word 0xb380000a ! 1: WR_STICK_CMPR_REG_R wr %r0, %r10, %-
#if (defined SPC || defined CMP1)
!$EV trig_pc_d(1, expr(@VA(.MAIN.splash_cmpr_10_403)+8 , 16, 16)) -> intp(4,0,5,*,1000,*,9b,1)
!$EV trig_pc_d(1, expr((@VA(.MAIN.splash_cmpr_10_403)&0xffffffff)+8 , 16, 16)) -> intp(2,0,13,*,760,*,9b,1)
#endif
wrhpr %g0, 0x0, %halt ! HALT
.word 0x819821e5 ! 1: WRHPR_HPSTATE_I wrhpr %r0, 0x01e5, %hpstate
.word 0x81b01021 ! 765: SIAM siam 1
memptr_10_407:
set 0x60140000, %r31
.word 0x8582e4a2 ! 769: WRCCR_I wr %r11, 0x04a2, %ccr
br_badelay3_10_410:
.word 0x20800001 ! 1: BN bn,a <label_0x1>
.word 0x816b0008 ! Random illegal ?
.word 0xe5150014 ! 1: LDQF_R - [%r20, %r20], %f18
.word 0x99a4c831 ! 773: FADDs fadds %f19, %f17, %f12
splash_lsu_10_411:
nop
nop
ta T_CHANGE_HPRIV
set 0x28149b83, %r2
mov 0x2, %r1
sllx %r1, 32, %r1
or %r1, %r2, %r2
stxa %r2, [%r0] ASI_LSU_CONTROL
ta T_CHANGE_NONHPRIV
.word 0x1d400001 ! 777: FBPULE fbule
.word 0x26800001 ! 781: BL bl,a <label_0x1>
pmu_10_417:
nop
nop
ta T_CHANGE_PRIV
setx 0xffffffbfffffffa6, %g1, %g7
.word 0xa3800007 ! 785: WR_PERF_COUNTER_R wr %r0, %r7, %-
.word 0x81460000 ! 789: RD_STICK_REG stbar
demap_10_421:
nop
mov 0x80, %g3
ta T_CHANGE_HPRIV
.word 0x3b400001 ! 1: FBPLE fble,a,pn %fcc0, <label_0x1>
stxa %g3, [%g3] 0x57
.word 0xc1bfc3e0 ! 1: STDFA_R stda %f0, [%r0, %r31]
.word 0xc09fdf00 ! 1: LDDA_R ldda [%r31, %r0] 0xf8, %r0
stxa %g3, [%g3] 0x5f
.word 0xc1bfde20 ! 1: STDFA_R stda %f0, [%r0, %r31]
stxa %g3, [%g3] 0x57
.word 0xc09fc3e0 ! 1: LDDA_R ldda [%r31, %r0] 0x1f, %r0
stxa %g3, [%g3] 0x57
.word 0xe09fdc40 ! 1: LDDA_R ldda [%r31, %r0] 0xe2, %r16
wrhpr %g0, 0x192, %hpstate ! ta T_CHANGE_NONHPRIV
.word 0xd21fe044 ! 793: LDD_I ldd [%r31 + 0x0044], %r9
memptr_10_424:
set 0x60740000, %r31
.word 0x8584334c ! 797: WRCCR_I wr %r16, 0x134c, %ccr
nop
nop
ta T_CHANGE_PRIV
wrpr %g0, %g0, %gl
nop
nop
.text
setx join_lbl_0_0, %g1, %g2
jmp %g2
nop
fork_lbl_0_4:
wrhpr %g0, 0x603, %hpstate ! ta T_CHANGE_NONHPRIV
.word 0x0e800001 ! 1: BVS bvs <label_0x1>
.word 0x8d902157 ! 1: WRPR_PSTATE_I wrpr %r0, 0x0157, %pstate
frzptr_8_3:
nop
nop
best_set_reg(0x3cbc0000+0x1ffc, %r20, %r27)
ldx [%r27+0xc], %r20
jmpl %r27, %r27
.word 0x20800001 ! 5: BN bn,a <label_0x1>
jmptr_8_5:
nop
nop
best_set_reg(0xe0200000, %r20, %r27)
.word 0xb7c6c000 ! 9: JMPL_R jmpl %r27 + %r0, %r27
.word 0xc32fc000 ! 13: STXFSR_R st-sfr %f1, [%r0, %r31]
.word 0xda97c2c0 ! 17: LDUHA_R lduha [%r31, %r0] 0x16, %r13
jmptr_8_9:
nop
nop
best_set_reg(0xe1200000, %r20, %r27)
.word 0xb7c6c000 ! 21: JMPL_R jmpl %r27 + %r0, %r27
.word 0x8980000a ! 25: WRTICK_R wr %r0, %r10, %tick
.word 0xda800ba0 ! 29: LDUWA_R lduwa [%r0, %r0] 0x5d, %r13
.word 0x87ac0a50 ! 33: FCMPd fcmpd %fcc<n>, %f16, %f16
.word 0xe28008a0 ! 37: LDUWA_R lduwa [%r0, %r0] 0x45, %r17
.word 0xe24fc000 ! 41: LDSB_R ldsb [%r31 + %r0], %r17
.word 0xa3a7c9a0 ! 1: FDIVs fdivs %f31, %f0, %f17
.word 0xc32fc000 ! 1: STXFSR_R st-sfr %f1, [%r0, %r31]
mov 0xb0, %r30
.word 0x91d0001e ! 45: Tcc_R ta icc_or_xcc, %r0 + %r30
demap_8_21:
nop
mov 0x80, %g3
ta T_CHANGE_HPRIV
.word 0x26cc4001 ! 1: BRLZ brlz,a,pt %r17,<label_0xc4001>
stxa %g3, [%g3] 0x5f
.word 0xc1bfde20 ! 1: STDFA_R stda %f0, [%r0, %r31]
wrhpr %g0, 0x30b, %hpstate ! ta T_CHANGE_NONHPRIV
.word 0xe21fe188 ! 49: LDD_I ldd [%r31 + 0x0188], %r17
.word 0xe247c000 ! 53: LDSW_R ldsw [%r31 + %r0], %r17
splash_lsu_8_22:
nop
nop
ta T_CHANGE_HPRIV
set 0x13cde1dd, %r2
mov 0x3, %r1
sllx %r1, 32, %r1
or %r1, %r2, %r2
.word 0x37400001 ! 1: FBPGE fbge,a,pn %fcc0, <label_0x1>
stxa %r2, [%r0] ASI_LSU_CONTROL
.word 0x3d400001 ! 57: FBPULE fbule,a,pn %fcc0, <label_0x1>
demap_8_25:
nop
mov 0x80, %g3
ta T_CHANGE_HPRIV
.word 0x2d400002 ! 1: FBPG fbg,a,pn %fcc0, <label_0x2>
stxa %g3, [%g3] 0x57
.word 0xc1bfc3e0 ! 1: STDFA_R stda %f0, [%r0, %r31]
.word 0xc1bfdd40 ! 1: STDFA_R stda %f0, [%r0, %r31]
.word 0xc09fdb20 ! 1: LDDA_R ldda [%r31, %r0] 0xd9, %r0
stxa %g3, [%g3] 0x57
stxa %g3, [%g3] 0x5f
.word 0xc09fde00 ! 1: LDDA_R ldda [%r31, %r0] 0xf0, %r0
stxa %g3, [%g3] 0x57
.word 0xe0bfdb40 ! 1: STDA_R stda %r16, [%r31 + %r0] 0xda
.word 0xc19fc2c0 ! 1: LDDFA_R ldda [%r31, %r0], %f0
.word 0xc19fda00 ! 1: LDDFA_R ldda [%r31, %r0], %f0
stxa %g3, [%g3] 0x5f
stxa %g3, [%g3] 0x5f
.word 0xe1bfdd40 ! 1: STDFA_R stda %f16, [%r0, %r31]
wrhpr %g0, 0xb50, %hpstate ! ta T_CHANGE_NONHPRIV
.word 0xe21fe030 ! 61: LDD_I ldd [%r31 + 0x0030], %r17
nop
nop
mov 0x1, %r11
splash_cmpr_8_28:
sllx %r11, 63, %r11
not %r11, %r11
rd %tick, %r10
#if (defined SPC || defined CMP1)
add %r10, 0x200, %r10
#else
add %r10, 0x380, %r10
#endif
and %r10, %r11, %r10
rd %tick, %r10
#if (defined SPC || defined CMP1)
add %r10, 0x300, %r10
#else
add %r10, 0x900, %r10
#endif
and %r10, %r11, %r10
.word 0xb380000a ! 1: WR_STICK_CMPR_REG_R wr %r0, %r10, %-
#if (defined SPC || defined CMP1)
!$EV trig_pc_d(1, expr(@VA(.MAIN.splash_cmpr_8_28)+8 , 16, 16)) -> intp(3,0,14,*,664,*,7e,1)
!$EV trig_pc_d(1, expr((@VA(.MAIN.splash_cmpr_8_28)&0xffffffff)+8 , 16, 16)) -> intp(5,0,24,*,744,*,7e,1)
#endif
wrhpr %g0, 0x0, %halt ! HALT
.word 0x81b01021 ! 65: SIAM siam 1
.word 0xc19fe160 ! 69: LDDFA_I ldda [%r31, 0x0160], %f0
.word 0xa1902000 ! 73: WRPR_GL_I wrpr %r0, 0x0000, %-
jmptr_8_34:
nop
nop
best_set_reg(0xe0200000, %r20, %r27)
.word 0xb7c6c000 ! 77: JMPL_R jmpl %r27 + %r0, %r27
nop
nop
ta T_CHANGE_HPRIV ! macro
donret_8_35:
rd %pc, %r12
mov HIGHVA_HIGHNUM, %r10
sllx %r10, 32, %r10
or %r12, %r10, %r12
add %r12, (donretarg_8_35-donret_8_35+4), %r12
add %r12, 0x4, %r11 ! seq tnpc
andn %r11, %r10, %r11 ! low VA tnpc
wrpr %g0, 0x2, %tl
wrpr %g0, %r12, %tpc
wrpr %g0, %r11, %tnpc
set (0x005dbd00 | (0x8b << 24)), %r13
and %r12, 0xfff, %r14
sllx %r14, 32, %r14
or %r13, %r14, %r20
wrpr %r20, %g0, %tstate
wrhpr %g0, 0x1e45, %htstate
best_set_reg(0x1932, %g1, %g2)
wrpr %g0, %g2, %pstate ! rand=0 (8)
done
donretarg_8_35:
.word 0x8d903b0d ! 81: WRPR_PSTATE_I wrpr %r0, 0x1b0d, %pstate
#if (defined SPC || defined CMP1)
!$EV trig_pc_d(1, expr(@VA(.MAIN.intvec_8_36) , 16, 16)) -> intp(4,0,4,*,896,*,ea,1)
!$EV trig_pc_d(1, expr((@VA(.MAIN.intvec_8_36)&0xffffffff) , 16, 16)) -> intp(1,0,27,*,648,*,ea,1)
#else
nop
nop
set 0x5880f254, %r28 !TTID : 2 (mask2tid(0x8))
#if (defined PORTABLE_CORE || MAX_THREADS == 8)
sethi %hi(0x3800), %r27
andn %r28, %r27, %r28
#ifdef PORTABLE_CORE
! Add CID to vector
ta T_CHANGE_HPRIV
ldxa [%g0]0x63, %r27
sllx %r27, 8, %r27
or %r27, %r28, %r28
#endif
#else
! Add CID IF tid matches
ifelse(2,mask2tid(0x8),`ta T_CHANGE_HPRIV;sethi %hi(0x3800), %r27;andn %r28, %r27, %r28;ldxa [%g0]0x63, %r27;sllx %r27, 8, %r27;or %r27, %r28, %r28 ')
#endif
ifelse(2,mask2tid(0x8),`.align 16')
stxa %r28, [%g0] 0x73
#endif
intvec_8_36:
#if (defined SPC || defined CMP1)
wrhpr %g0, 0x0, %halt ! HALT
#else
ifelse(2,mask2tid(0x8),`wrhpr %g0, 0x0, %halt ! HALT')
#endif
.word 0x99a509d2 ! 85: FDIVd fdivd %f20, %f18, %f12
.word 0xa6840012 ! 89: ADDcc_R addcc %r16, %r18, %r19
nop
nop
set 0x21a024c2, %r28 !TTID : 4 (mask2tid(0x8))
#if (defined PORTABLE_CORE || MAX_THREADS == 8)
sethi %hi(0x3800), %r27
andn %r28, %r27, %r28
#ifdef PORTABLE_CORE
! Add CID to vector
ta T_CHANGE_HPRIV
ldxa [%g0]0x63, %r27
sllx %r27, 8, %r27
or %r27, %r28, %r28
#endif
#else
! Add CID IF tid matches
ifelse(4,mask2tid(0x8),`ta T_CHANGE_HPRIV;sethi %hi(0x3800), %r27;andn %r28, %r27, %r28;ldxa [%g0]0x63, %r27;sllx %r27, 8, %r27;or %r27, %r28, %r28 ')
#endif
sethi %hi(0x30000), %r27
andn %r28, %r27, %r28
ta T_CHANGE_HPRIV
ifelse(4,mask2tid(0x8),`.align 16')
stxa %r28, [%g0] 0x73
intvec_8_39:
.word 0x19400001 ! 93: FBPUGE fbuge
.word 0x81460000 ! 97: RD_STICK_REG stbar
.word 0xe1e7c720 ! 101: CASA_I casa [%r31] 0x39, %r0, %r16
.word 0x1c800001 ! 105: BPOS bpos <label_0x1>
nop
nop
set 0xb5d06cee, %r28 !TTID : 4 (mask2tid(0x8))
#if (defined PORTABLE_CORE || MAX_THREADS == 8)
sethi %hi(0x3800), %r27
andn %r28, %r27, %r28
#ifdef PORTABLE_CORE
! Add CID to vector
ta T_CHANGE_HPRIV
ldxa [%g0]0x63, %r27
sllx %r27, 8, %r27
or %r27, %r28, %r28
#endif
#else
! Add CID IF tid matches
ifelse(4,mask2tid(0x8),`ta T_CHANGE_HPRIV;sethi %hi(0x3800), %r27;andn %r28, %r27, %r28;ldxa [%g0]0x63, %r27;sllx %r27, 8, %r27;or %r27, %r28, %r28 ')
#endif
sethi %hi(0x30000), %r27
andn %r28, %r27, %r28
ta T_CHANGE_HPRIV
ifelse(4,mask2tid(0x8),`.align 16')
stxa %r28, [%g0] 0x73
intvec_8_47:
.word 0x99a489d3 ! 109: FDIVd fdivd %f18, %f50, %f12
.word 0xd8800aa0 ! 113: LDUWA_R lduwa [%r0, %r0] 0x55, %r12
nop
nop
mov 0x1, %r11
splash_cmpr_8_52:
sllx %r11, 63, %r11
not %r11, %r11
rd %tick, %r10
#if (defined SPC || defined CMP1)
add %r10, 0x250, %r10
#else
add %r10, 0x380, %r10
#endif
and %r10, %r11, %r10
rd %tick, %r10
#if (defined SPC || defined CMP1)
add %r10, 0x200, %r10
#else
add %r10, 0x550, %r10
#endif
and %r10, %r11, %r10
.word 0xaf80000a ! 1: WR_TICK_CMPR_REG_R wr %r0, %r10, %-
#if (defined SPC || defined CMP1)
!$EV trig_pc_d(1, expr(@VA(.MAIN.splash_cmpr_8_52)+8 , 16, 16)) -> intp(0,0,31,*,936,*,4c,1)
!$EV trig_pc_d(1, expr((@VA(.MAIN.splash_cmpr_8_52)&0xffffffff)+8 , 16, 16)) -> intp(1,0,16,*,720,*,4c,1)
#endif
wrhpr %g0, 0x0, %halt ! HALT
.word 0x81b01021 ! 117: SIAM siam 1
.word 0x8d802004 ! 121: WRFPRS_I wr %r0, 0x0004, %fprs
.word 0xa2dc4001 ! 125: SMULcc_R smulcc %r17, %r1, %r17
brcommon2_8_54:
nop
nop
setx common_target, %r12, %r27
ba,a .+12
.word 0xa9a089d0 ! 1: FDIVd fdivd %f2, %f16, %f20
ba,a .+8
jmpl %r27-4, %r27
.word 0x81b7c7c0 ! 129: PDIST pdistn %d62, %d0, %d0
memptr_8_56:
set 0x60340000, %r31
.word 0x858268c5 ! 133: WRCCR_I wr %r9, 0x08c5, %ccr
splash_lsu_8_58:
nop
nop
ta T_CHANGE_HPRIV
set 0xec5a755b, %r2
mov 0x3, %r1
sllx %r1, 32, %r1
or %r1, %r2, %r2
stxa %r2, [%r0] ASI_LSU_CONTROL
ta T_CHANGE_NONHPRIV
.word 0x1d400001 ! 137: FBPULE fbule
.word 0xda77e04e ! 141: STX_I stx %r13, [%r31 + 0x004e]
jmptr_8_65:
nop
nop
best_set_reg(0xe1200000, %r20, %r27)
.word 0xb7c6c000 ! 145: JMPL_R jmpl %r27 + %r0, %r27
.word 0x91d02035 ! 149: Tcc_I ta icc_or_xcc, %r0 + 53
.word 0xda800c80 ! 153: LDUWA_R lduwa [%r0, %r0] 0x64, %r13
fpinit_8_70:
nop
setx fp_data_quads, %r19, %r20
ldd [%r20], %f0
ldd [%r20+8], %f4
ld [%r20+16], %fsr
ld [%r20+24], %r19
wr %r19, %g0, %gsr
.word 0x87a80a44 ! 157: FCMPd fcmpd %fcc<n>, %f0, %f4
.word 0xc1bfc3e0 ! 161: STDFA_R stda %f0, [%r0, %r31]
.word 0x9ba00160 ! 165: FABSq dis not found
br_badelay3_8_78:
.word 0xa1a409d2 ! 1: FDIVd fdivd %f16, %f18, %f16
.word 0xcb52ee49 ! Random illegal ?
.word 0xe9140002 ! 1: LDQF_R - [%r16, %r2], %f20
.word 0xa3a0c831 ! 169: FADDs fadds %f3, %f17, %f17
.word 0xd2c7c2c0 ! 173: LDSWA_R ldswa [%r31, %r0] 0x16, %r9
nop
nop
ta T_CHANGE_HPRIV ! macro
donret_8_82:
rd %pc, %r12
mov HIGHVA_HIGHNUM, %r10
sllx %r10, 32, %r10
or %r12, %r10, %r12
add %r12, (donretarg_8_82-donret_8_82+4), %r12
add %r12, 0x4, %r11 ! seq tnpc
wrpr %g0, 0x1, %tl
wrpr %g0, %r12, %tpc
wrpr %g0, %r11, %tnpc
set (0x00e58000 | (16 << 24)), %r13
and %r12, 0xfff, %r14
sllx %r14, 32, %r14
or %r13, %r14, %r20
wrpr %r20, %g0, %tstate
wrhpr %g0, 0x7cc, %htstate
wrhpr %g0, 0x7d1, %hpstate ! rand=1 (8)
ldx [%r12+%r0], %g1
retry
donretarg_8_82:
.word 0xa3a509cb ! 177: FDIVd fdivd %f20, %f42, %f48
nop
nop
set 0xce3027ca, %r28 !TTID : 7 (mask2tid(0x8))
#if (defined PORTABLE_CORE || MAX_THREADS == 8)
sethi %hi(0x3800), %r27
andn %r28, %r27, %r28
#ifdef PORTABLE_CORE
! Add CID to vector
ta T_CHANGE_HPRIV
ldxa [%g0]0x63, %r27
sllx %r27, 8, %r27
or %r27, %r28, %r28
#endif
#else
! Add CID IF tid matches
ifelse(7,mask2tid(0x8),`ta T_CHANGE_HPRIV;sethi %hi(0x3800), %r27;andn %r28, %r27, %r28;ldxa [%g0]0x63, %r27;sllx %r27, 8, %r27;or %r27, %r28, %r28 ')
#endif
sethi %hi(0x30000), %r27
andn %r28, %r27, %r28
ta T_CHANGE_HPRIV
ifelse(7,mask2tid(0x8),`.align 16')
stxa %r28, [%g0] 0x73
intvec_8_83:
.word 0xa7b284d0 ! 181: FCMPNE32 fcmpne32 %d10, %d16, %r19
brcommon3_8_86:
nop
nop
setx common_target, %r12, %r27
lduw [%r27], %r12 ! Load common dest into dcache ..
stuw %r12, [%r27] ! Load common dest into dcache ..
ba,a .+12
.word 0xd86fe150 ! 1: LDSTUB_I ldstub %r12, [%r31 + 0x0150]
ba,a .+8
jmpl %r27+0, %r27
stxa %r19, [%r0] ASI_LSU_CONTROL
.word 0xa7aac832 ! 185: FMOVGE fmovs %fcc1, %f18, %f19
cancelint_8_89:
rdhpr %halt, %r13
.word 0x85880000 ! 189: ALLCLEAN <illegal instruction>
.word 0xe927e1e9 ! 193: STF_I st %f20, [0x01e9, %r31]
splash_lsu_8_94:
nop
nop
ta T_CHANGE_HPRIV
set 0x8e5ca79d, %r2
mov 0x1, %r1
sllx %r1, 32, %r1
or %r1, %r2, %r2
.word 0x33400001 ! 1: FBPE fbe,a,pn %fcc0, <label_0x1>
stxa %r2, [%r0] ASI_LSU_CONTROL
ta T_CHANGE_NONHPRIV
.word 0x3d400001 ! 197: FBPULE fbule,a,pn %fcc0, <label_0x1>
.word 0xa1902004 ! 201: WRPR_GL_I wrpr %r0, 0x0004, %-
br_badelay3_8_98:
.word 0x14800001 ! 1: BG bg <label_0x1>
.word 0x8158f7eb ! Random illegal ?
.word 0x91a00548 ! 1: FSQRTd fsqrt
.word 0xa5a40829 ! 205: FADDs fadds %f16, %f9, %f18
.word 0x8f902000 ! 1: WRPR_TL_I wrpr %r0, 0x0000, %tl
reduce_priv_lvl_8_99:
ta T_CHANGE_NONPRIV ! macro
splash_lsu_8_102:
nop
nop
ta T_CHANGE_HPRIV
set 0xe48264ca, %r2
mov 0x2, %r1
sllx %r1, 32, %r1
or %r1, %r2, %r2
stxa %r2, [%r0] ASI_LSU_CONTROL
ta T_CHANGE_NONHPRIV
.word 0x3d400001 ! 213: FBPULE fbule,a,pn %fcc0, <label_0x1>
.word 0x8d903df0 ! 217: WRPR_PSTATE_I wrpr %r0, 0x1df0, %pstate
.word 0xe4bfc3c0 ! 221: STDA_R stda %r18, [%r31 + %r0] 0x1e
.word 0xe19fdf20 ! 225: LDDFA_R ldda [%r31, %r0], %f16
#if (defined SPC || defined CMP1)
!$EV trig_pc_d(1, expr(@VA(.MAIN.intvec_8_112) , 16, 16)) -> intp(0,0,29,*,1016,*,ba,1)
!$EV trig_pc_d(1, expr((@VA(.MAIN.intvec_8_112)&0xffffffff) , 16, 16)) -> intp(0,0,1,*,960,*,ba,1)
#else
nop
nop
set 0x2ff0489f, %r28 !TTID : 0 (mask2tid(0x8))
#if (defined PORTABLE_CORE || MAX_THREADS == 8)
sethi %hi(0x3800), %r27
andn %r28, %r27, %r28
#ifdef PORTABLE_CORE
! Add CID to vector
ta T_CHANGE_HPRIV
ldxa [%g0]0x63, %r27
sllx %r27, 8, %r27
or %r27, %r28, %r28
#endif
#else
! Add CID IF tid matches
ifelse(0,mask2tid(0x8),`ta T_CHANGE_HPRIV;sethi %hi(0x3800), %r27;andn %r28, %r27, %r28;ldxa [%g0]0x63, %r27;sllx %r27, 8, %r27;or %r27, %r28, %r28 ')
#endif
ifelse(0,mask2tid(0x8),`.align 16')
stxa %r28, [%g0] 0x73
#endif
intvec_8_112:
#if (defined SPC || defined CMP1)
wrhpr %g0, 0x0, %halt ! HALT
#else
ifelse(0,mask2tid(0x8),`wrhpr %g0, 0x0, %halt ! HALT')
#endif
.word 0x97b104c5 ! 229: FCMPNE32 fcmpne32 %d4, %d36, %r11
jmptr_8_115:
nop
nop
best_set_reg(0xe0200000, %r20, %r27)
.word 0xb7c6c000 ! 233: JMPL_R jmpl %r27 + %r0, %r27
.word 0xd097c600 ! 237: LDUHA_R lduha [%r31, %r0] 0x30, %r8
intveclr_8_120:
nop
nop
ta T_CHANGE_HPRIV
setx 0x7eb0597138f4c102, %r1, %r28
stxa %r28, [%g0] 0x72
wrhpr %g0, 0xdc0, %hpstate ! ta T_CHANGE_NONHPRIV
.word 0x25400001 ! 241: FBPLG fblg,a,pn %fcc0, <label_0x1>
splash_lsu_8_122:
nop
nop
ta T_CHANGE_HPRIV
set 0x67b28be9, %r2
mov 0x1, %r1
sllx %r1, 32, %r1
or %r1, %r2, %r2
.word 0x0b400002 ! 1: FBPUG fbug
stxa %r2, [%r0] ASI_LSU_CONTROL
ta T_CHANGE_NONHPRIV
.word 0x3d400001 ! 245: FBPULE fbule,a,pn %fcc0, <label_0x1>
.word 0xd137c000 ! 249: STQF_R - %f8, [%r0, %r31]
splash_lsu_8_125:
nop
nop
ta T_CHANGE_HPRIV
set 0x23a10588, %r2
mov 0x2, %r1
sllx %r1, 32, %r1
or %r1, %r2, %r2
stxa %r2, [%r0] ASI_LSU_CONTROL
.word 0x3d400001 ! 253: FBPULE fbule,a,pn %fcc0, <label_0x1>
.word 0x8980000a ! 257: WRTICK_R wr %r0, %r10, %tick
.word 0xa190200e ! 261: WRPR_GL_I wrpr %r0, 0x000e, %-
jmptr_8_133:
nop
nop
best_set_reg(0xe1200000, %r20, %r27)
.word 0xb7c6c000 ! 265: JMPL_R jmpl %r27 + %r0, %r27
nop
nop
mov 0x1, %r11
splash_cmpr_8_134:
sllx %r11, 63, %r11
not %r11, %r11
rd %tick, %r10
#if (defined SPC || defined CMP1)
add %r10, 0x300, %r10
#else
add %r10, 0x900, %r10
#endif
and %r10, %r11, %r10
rd %tick, %r10
#if (defined SPC || defined CMP1)
add %r10, 0x250, %r10
#else
add %r10, 0x380, %r10
#endif
and %r10, %r11, %r10
.word 0xaf80000a ! 1: WR_TICK_CMPR_REG_R wr %r0, %r10, %-
#if (defined SPC || defined CMP1)
!$EV trig_pc_d(1, expr(@VA(.MAIN.splash_cmpr_8_134)+8 , 16, 16)) -> intp(0,0,4,*,992,*,a,1)
!$EV trig_pc_d(1, expr((@VA(.MAIN.splash_cmpr_8_134)&0xffffffff)+8 , 16, 16)) -> intp(4,0,22,*,664,*,a,1)
#endif
wrhpr %g0, 0x0, %halt ! HALT
.word 0x81b01021 ! 269: SIAM siam 1
jmptr_8_135:
nop
nop
best_set_reg(0xe0200000, %r20, %r27)
.word 0xb7c6c000 ! 273: JMPL_R jmpl %r27 + %r0, %r27
intveclr_8_136:
nop
nop
ta T_CHANGE_HPRIV
setx 0x5ca6c1a1d6af09d3, %r1, %r28
stxa %r28, [%g0] 0x72
.word 0x05400001 ! 277: FBPLG fblg
.word 0xd137e1aa ! 281: STQF_I - %f8, [0x01aa, %r31]
splash_hpstate_8_141:
.word 0x0a800001 ! 1: BCS bcs <label_0x1>
.word 0x81983ec2 ! 285: WRHPR_HPSTATE_I wrhpr %r0, 0x1ec2, %hpstate
intveclr_8_145:
nop
nop
ta T_CHANGE_HPRIV
setx 0x62b05507fd4ecaa2, %r1, %r28
stxa %r28, [%g0] 0x72
wrhpr %g0, 0xdda, %hpstate ! ta T_CHANGE_NONHPRIV
.word 0x25400001 ! 289: FBPLG fblg,a,pn %fcc0, <label_0x1>
brcommon1_8_148:
nop
nop
setx common_target, %r12, %r27
lduw [%r27-0], %r12 ! Load common dest into dcache ..
stuw %r12, [%r27-4] ! Load common dest into dcache ..
ba,a .+12
.word 0x91a7c9c0 ! 1: FDIVd fdivd %f62, %f0, %f8
ba,a .+8
jmpl %r27-0, %r27
.word 0xa7b447d3 ! 293: PDIST pdistn %d48, %d50, %d50
.word 0xd8dfdf00 ! 297: LDXA_R ldxa [%r31, %r0] 0xf8, %r12
.word 0x9193000c ! 301: WRPR_PIL_R wrpr %r12, %r12, %pil
demap_8_156:
nop
mov 0x80, %g3
ta T_CHANGE_HPRIV
.word 0x27400001 ! 1: FBPUL fbul,a,pn %fcc0, <label_0x1>
stxa %g3, [%g3] 0x5f
.word 0xe1bfdc00 ! 1: STDFA_R stda %f16, [%r0, %r31]
stxa %g3, [%g3] 0x5f
.word 0xe19fdc00 ! 1: LDDFA_R ldda [%r31, %r0], %f16
stxa %g3, [%g3] 0x57
.word 0xc1bfc2c0 ! 1: STDFA_R stda %f0, [%r0, %r31]
stxa %g3, [%g3] 0x5f
.word 0xe0bfda60 ! 1: STDA_R stda %r16, [%r31 + %r0] 0xd3
stxa %g3, [%g3] 0x57
.word 0xe0bfde00 ! 1: STDA_R stda %r16, [%r31 + %r0] 0xf0
.word 0xc0bfde20 ! 1: STDA_R stda %r0, [%r31 + %r0] 0xf1
.word 0xc09fdc00 ! 1: LDDA_R ldda [%r31, %r0] 0xe0, %r0
wrhpr %g0, 0xc0, %hpstate ! ta T_CHANGE_NONHPRIV
.word 0xd81fe061 ! 305: LDD_I ldd [%r31 + 0x0061], %r12
.word 0x91950003 ! 309: WRPR_PIL_R wrpr %r20, %r3, %pil
.word 0x19400002 ! 313: FBPUGE fbuge
splash_lsu_8_163:
nop
nop
ta T_CHANGE_HPRIV
set 0x809772f8, %r2
mov 0x4, %r1
sllx %r1, 32, %r1
or %r1, %r2, %r2
.word 0x2e800002 ! 1: BVS bvs,a <label_0x2>
stxa %r2, [%r0] ASI_LSU_CONTROL
ta T_CHANGE_NONHPRIV
.word 0x3d400001 ! 317: FBPULE fbule,a,pn %fcc0, <label_0x1>
splash_hpstate_8_166:
.word 0x819829d5 ! 321: WRHPR_HPSTATE_I wrhpr %r0, 0x09d5, %hpstate
nop
nop
ta T_CHANGE_HPRIV
mov 0x0, %r11
splash_cmpr_8_169:
sllx %r11, 63, %r11
not %r11, %r11
rd %tick, %r10
#if (defined SPC || defined CMP1)
add %r10, 0x150, %r10
#else
add %r10, 0x380, %r10
#endif
and %r10, %r11, %r10
wrhpr %r10, %g0, %hsys_tick_cmpr
ta T_CHANGE_PRIV
rd %tick, %r10
#if (defined SPC || defined CMP1)
add %r10, 0x200, %r10
#else
add %r10, 0x900, %r10
#endif
and %r10, %r11, %r10
.word 0xb380000a ! 1: WR_STICK_CMPR_REG_R wr %r0, %r10, %-
.word 0x81982f9f ! 1: WRHPR_HPSTATE_I wrhpr %r0, 0x0f9f, %hpstate
.word 0x81b01021 ! 325: SIAM siam 1
intveclr_8_171:
nop
nop
ta T_CHANGE_HPRIV
setx 0x219cfe8f5c2760da, %r1, %r28
stxa %r28, [%g0] 0x72
wrhpr %g0, 0xa91, %hpstate ! ta T_CHANGE_NONHPRIV
.word 0x05400001 ! 329: FBPLG fblg
.word 0x91940010 ! 333: WRPR_PIL_R wrpr %r16, %r16, %pil
.word 0xf16fe032 ! 337: PREFETCH_I prefetch [%r31 + 0x0032], #24
demap_8_179:
nop
mov 0x80, %g3
ta T_CHANGE_HPRIV
.word 0x2ecc4001 ! 1: BRGEZ brgez,a,pt %r17,<label_0xc4001>
stxa %g3, [%g3] 0x5f
.word 0xe0bfda60 ! 1: STDA_R stda %r16, [%r31 + %r0] 0xd3
.word 0xe1bfc3e0 ! 1: STDFA_R stda %f16, [%r0, %r31]
.word 0xe09fdc00 ! 1: LDDA_R ldda [%r31, %r0] 0xe0, %r16
stxa %g3, [%g3] 0x57
.word 0xe0bfdf00 ! 1: STDA_R stda %r16, [%r31 + %r0] 0xf8
.word 0xc19fdb20 ! 1: LDDFA_R ldda [%r31, %r0], %f0
stxa %g3, [%g3] 0x5f
.word 0xe09fc3e0 ! 1: LDDA_R ldda [%r31, %r0] 0x1f, %r16
.word 0xc19fdd40 ! 1: LDDFA_R ldda [%r31, %r0], %f0
stxa %g3, [%g3] 0x5f
stxa %g3, [%g3] 0x5f
wrhpr %g0, 0xbd2, %hpstate ! ta T_CHANGE_NONHPRIV
.word 0xd21fe120 ! 341: LDD_I ldd [%r31 + 0x0120], %r9
.word 0xa190200b ! 345: WRPR_GL_I wrpr %r0, 0x000b, %-
nop
nop
mov 0x0, %r11
splash_cmpr_8_181:
sllx %r11, 63, %r11
not %r11, %r11
rd %tick, %r10
#if (defined SPC || defined CMP1)
add %r10, 0x200, %r10
#else
add %r10, 0x380, %r10
#endif
and %r10, %r11, %r10
rd %tick, %r10
#if (defined SPC || defined CMP1)
add %r10, 0x200, %r10
#else
add %r10, 0x380, %r10
#endif
and %r10, %r11, %r10
.word 0xaf80000a ! 1: WR_TICK_CMPR_REG_R wr %r0, %r10, %-
.word 0x81b01021 ! 349: SIAM siam 1
nop
nop
set 0xabc05ef1, %r28 !TTID : 6 (mask2tid(0x8))
#if (defined PORTABLE_CORE || MAX_THREADS == 8)
sethi %hi(0x3800), %r27
andn %r28, %r27, %r28
#ifdef PORTABLE_CORE
! Add CID to vector
ta T_CHANGE_HPRIV
ldxa [%g0]0x63, %r27
sllx %r27, 8, %r27
or %r27, %r28, %r28
#endif
#else
! Add CID IF tid matches
ifelse(6,mask2tid(0x8),`ta T_CHANGE_HPRIV;sethi %hi(0x3800), %r27;andn %r28, %r27, %r28;ldxa [%g0]0x63, %r27;sllx %r27, 8, %r27;or %r27, %r28, %r28 ')
#endif
sethi %hi(0x30000), %r27
andn %r28, %r27, %r28
ta T_CHANGE_HPRIV
ifelse(6,mask2tid(0x8),`.align 16')
stxa %r28, [%g0] 0x73
intvec_8_183:
.word 0x97a0c9c7 ! 353: FDIVd fdivd %f34, %f38, %f42
splash_tba_8_187:
nop
ta T_CHANGE_PRIV
setx 0x0000000000380000, %r11, %r12
.word 0x8b90000c ! 357: WRPR_TBA_R wrpr %r0, %r12, %tba
.word 0x2a780001 ! 361: BPCS <illegal instruction>
splash_lsu_8_191:
nop
nop
ta T_CHANGE_HPRIV
set 0xe6045afa, %r2
mov 0x2, %r1
sllx %r1, 32, %r1
or %r1, %r2, %r2
stxa %r2, [%r0] ASI_LSU_CONTROL
ta T_CHANGE_NONHPRIV
.word 0x3d400001 ! 365: FBPULE fbule,a,pn %fcc0, <label_0x1>
#if (defined SPC || defined CMP1)
!$EV trig_pc_d(1, expr(@VA(.MAIN.intvec_8_194) , 16, 16)) -> intp(5,0,14,*,696,*,da,1)
!$EV trig_pc_d(1, expr((@VA(.MAIN.intvec_8_194)&0xffffffff) , 16, 16)) -> intp(5,0,16,*,760,*,da,1)
#else
nop
nop
set 0xc170912e, %r28 !TTID : 1 (mask2tid(0x8))
#if (defined PORTABLE_CORE || MAX_THREADS == 8)
sethi %hi(0x3800), %r27
andn %r28, %r27, %r28
#ifdef PORTABLE_CORE
! Add CID to vector
ta T_CHANGE_HPRIV
ldxa [%g0]0x63, %r27
sllx %r27, 8, %r27
or %r27, %r28, %r28
#endif
#else
! Add CID IF tid matches
ifelse(1,mask2tid(0x8),`ta T_CHANGE_HPRIV;sethi %hi(0x3800), %r27;andn %r28, %r27, %r28;ldxa [%g0]0x63, %r27;sllx %r27, 8, %r27;or %r27, %r28, %r28 ')
#endif
ifelse(1,mask2tid(0x8),`.align 16')
stxa %r28, [%g0] 0x73
#endif
intvec_8_194:
#if (defined SPC || defined CMP1)
wrhpr %g0, 0x0, %halt ! HALT
#else
ifelse(1,mask2tid(0x8),`wrhpr %g0, 0x0, %halt ! HALT')
#endif
.word 0xa1a449c5 ! 369: FDIVd fdivd %f48, %f36, %f16
#if (defined SPC || defined CMP1)
!$EV trig_pc_d(1, expr(@VA(.MAIN.intvec_8_196) , 16, 16)) -> intp(5,0,25,*,944,*,2c,1)
!$EV trig_pc_d(1, expr((@VA(.MAIN.intvec_8_196)&0xffffffff) , 16, 16)) -> intp(0,0,16,*,984,*,2c,1)
#else
nop
nop
set 0xbfe0f286, %r28 !TTID : 2 (mask2tid(0x8))
#if (defined PORTABLE_CORE || MAX_THREADS == 8)
sethi %hi(0x3800), %r27
andn %r28, %r27, %r28
#ifdef PORTABLE_CORE
! Add CID to vector
ta T_CHANGE_HPRIV
ldxa [%g0]0x63, %r27
sllx %r27, 8, %r27
or %r27, %r28, %r28
#endif
#else
! Add CID IF tid matches
ifelse(2,mask2tid(0x8),`ta T_CHANGE_HPRIV;sethi %hi(0x3800), %r27;andn %r28, %r27, %r28;ldxa [%g0]0x63, %r27;sllx %r27, 8, %r27;or %r27, %r28, %r28 ')
#endif
ifelse(2,mask2tid(0x8),`.align 16')
stxa %r28, [%g0] 0x73
#endif
intvec_8_196:
#if (defined SPC || defined CMP1)
wrhpr %g0, 0x0, %halt ! HALT
#else
ifelse(2,mask2tid(0x8),`wrhpr %g0, 0x0, %halt ! HALT')
#endif
.word 0xa9b244d3 ! 373: FCMPNE32 fcmpne32 %d40, %d50, %r20
frzptr_8_199:
nop
nop
best_set_reg(0x3cb00000+0x1ffc, %r20, %r27)
jmpl %r27, %r27
.word 0x20800002 ! 377: BN bn,a <label_0x2>
.word 0x12800002 ! 381: BNE bne <label_0x2>
#if (defined SPC || defined CMP1)
!$EV trig_pc_d(1, expr(@VA(.MAIN.intvec_8_204) , 16, 16)) -> intp(1,0,4,*,664,*,6a,1)
!$EV trig_pc_d(1, expr((@VA(.MAIN.intvec_8_204)&0xffffffff) , 16, 16)) -> intp(6,0,25,*,672,*,6a,1)
#else
nop
nop
set 0x10b00aee, %r28 !TTID : 2 (mask2tid(0x8))
#if (defined PORTABLE_CORE || MAX_THREADS == 8)
sethi %hi(0x3800), %r27
andn %r28, %r27, %r28
#ifdef PORTABLE_CORE
! Add CID to vector
ta T_CHANGE_HPRIV
ldxa [%g0]0x63, %r27
sllx %r27, 8, %r27
or %r27, %r28, %r28
#endif
#else
! Add CID IF tid matches
ifelse(2,mask2tid(0x8),`ta T_CHANGE_HPRIV;sethi %hi(0x3800), %r27;andn %r28, %r27, %r28;ldxa [%g0]0x63, %r27;sllx %r27, 8, %r27;or %r27, %r28, %r28 ')
#endif
ifelse(2,mask2tid(0x8),`.align 16')
stxa %r28, [%g0] 0x73
#endif
intvec_8_204:
#if (defined SPC || defined CMP1)
wrhpr %g0, 0x0, %halt ! HALT
#else
ifelse(2,mask2tid(0x8),`wrhpr %g0, 0x0, %halt ! HALT')
#endif
.word 0x39400001 ! 385: FBPUGE fbuge,a,pn %fcc0, <label_0x1>
.word 0x97a309cc ! 389: FDIVd fdivd %f12, %f12, %f42
.word 0xd917c000 ! 393: LDQF_R - [%r31, %r0], %f12
demap_8_211:
nop
mov 0x80, %g3
ta T_CHANGE_HPRIV
stxa %g3, [%g3] 0x57
stxa %g3, [%g3] 0x5f
wrhpr %g0, 0xd1a, %hpstate ! ta T_CHANGE_NONHPRIV
.word 0xd81fe108 ! 397: LDD_I ldd [%r31 + 0x0108], %r12
brcommon1_8_213:
nop
nop
setx common_target, %r12, %r27
lduw [%r27-0], %r12 ! Load common dest into dcache ..
stuw %r12, [%r27-0] ! Load common dest into dcache ..
ba,a .+12
.word 0x99a7c9c0 ! 1: FDIVd fdivd %f62, %f0, %f12
ba,a .+8
jmpl %r27-4, %r27
.word 0x97703a8b ! 401: POPC_I popc 0x1a8b, %r11
nop
nop
set 0x7a0257a, %r28 !TTID : 5 (mask2tid(0x8))
#if (defined PORTABLE_CORE || MAX_THREADS == 8)
sethi %hi(0x3800), %r27
andn %r28, %r27, %r28
#ifdef PORTABLE_CORE
! Add CID to vector
ta T_CHANGE_HPRIV
ldxa [%g0]0x63, %r27
sllx %r27, 8, %r27
or %r27, %r28, %r28
#endif
#else
! Add CID IF tid matches
ifelse(5,mask2tid(0x8),`ta T_CHANGE_HPRIV;sethi %hi(0x3800), %r27;andn %r28, %r27, %r28;ldxa [%g0]0x63, %r27;sllx %r27, 8, %r27;or %r27, %r28, %r28 ')
#endif
sethi %hi(0x30000), %r27
andn %r28, %r27, %r28
ta T_CHANGE_HPRIV
ifelse(5,mask2tid(0x8),`.align 16')
stxa %r28, [%g0] 0x73
intvec_8_215:
.word 0x39400001 ! 405: FBPUGE fbuge,a,pn %fcc0, <label_0x1>
.word 0xe8bfdd40 ! 409: STDA_R stda %r20, [%r31 + %r0] 0xea
.word 0x91930003 ! 413: WRPR_PIL_R wrpr %r12, %r3, %pil
.word 0xc19fe000 ! 417: LDDFA_I ldda [%r31, 0x0000], %f0
.word 0xe937c000 ! 421: STQF_R - %f20, [%r0, %r31]
.word 0x34800002 ! 1: BG bg,a <label_0x2>
br_longdelay5_8_224:
#if (defined SPC || defined CMP1)
!$EV trig_pc_d(1, expr((@VA(.MAIN.br_longdelay5_8_224)&0xffffffff) , 16, 16)) -> intp(mask2tid(0x8),0,0,*,1016,*,ffffffffffffffff,1)
!$EV trig_pc_d(1, expr((@VA(.MAIN.br_longdelay5_8_224)) , 16, 16)) -> intp(mask2tid(0x8),0,0,*,712,*,ffffffffffffffff,1)
wrhpr %g0, 0x0, %halt ! HALT
#endif
.word 0x24cfc001 ! 425: BRLEZ brlez,a,pt %r31,<label_0xfc001>
#if (defined SPC || defined CMP1)
!$EV trig_pc_d(1, expr(@VA(.MAIN.intvec_8_226) , 16, 16)) -> intp(6,0,24,*,664,*,da,1)
!$EV trig_pc_d(1, expr((@VA(.MAIN.intvec_8_226)&0xffffffff) , 16, 16)) -> intp(4,0,25,*,744,*,da,1)
#else
nop
nop
set 0x4a06994, %r28 !TTID : 1 (mask2tid(0x8))
#if (defined PORTABLE_CORE || MAX_THREADS == 8)
sethi %hi(0x3800), %r27
andn %r28, %r27, %r28
#ifdef PORTABLE_CORE
! Add CID to vector
ta T_CHANGE_HPRIV
ldxa [%g0]0x63, %r27
sllx %r27, 8, %r27
or %r27, %r28, %r28
#endif
#else
! Add CID IF tid matches
ifelse(1,mask2tid(0x8),`ta T_CHANGE_HPRIV;sethi %hi(0x3800), %r27;andn %r28, %r27, %r28;ldxa [%g0]0x63, %r27;sllx %r27, 8, %r27;or %r27, %r28, %r28 ')
#endif
ifelse(1,mask2tid(0x8),`.align 16')
stxa %r28, [%g0] 0x73
#endif
intvec_8_226:
#if (defined SPC || defined CMP1)
wrhpr %g0, 0x0, %halt ! HALT
#else
ifelse(1,mask2tid(0x8),`wrhpr %g0, 0x0, %halt ! HALT')
#endif
.word 0x93a4c9c4 ! 429: FDIVd fdivd %f50, %f4, %f40
jmptr_8_228:
nop
nop
best_set_reg(0xe1200000, %r20, %r27)
.word 0xb7c6c000 ! 433: JMPL_R jmpl %r27 + %r0, %r27
demap_8_232:
nop
mov 0x80, %g3
ta T_CHANGE_HPRIV
stxa %g3, [%g3] 0x5f
.word 0xe0bfdb40 ! 1: STDA_R stda %r16, [%r31 + %r0] 0xda
.word 0xc1bfde20 ! 1: STDFA_R stda %f0, [%r0, %r31]
stxa %g3, [%g3] 0x5f
.word 0xe1bfda00 ! 1: STDFA_R stda %f16, [%r0, %r31]
.word 0xe09fdb40 ! 1: LDDA_R ldda [%r31, %r0] 0xda, %r16
stxa %g3, [%g3] 0x57
wrhpr %g0, 0xcc8, %hpstate ! ta T_CHANGE_NONHPRIV
.word 0xda1fe120 ! 437: LDD_I ldd [%r31 + 0x0120], %r13
trapasi_8_235:
nop
mov 0x3e0, %r1 ! (VA for ASI 0x25)
.word 0xdad844a0 ! 441: LDXA_R ldxa [%r1, %r0] 0x25, %r13
.word 0xda57c000 ! 445: LDSH_R ldsh [%r31 + %r0], %r13
.word 0xda27e198 ! 449: STW_I stw %r13, [%r31 + 0x0198]
demap_8_240:
nop
mov 0x80, %g3
ta T_CHANGE_HPRIV
.word 0x2a800001 ! 1: BCS bcs,a <label_0x1>
stxa %g3, [%g3] 0x5f
.word 0xe1bfdc00 ! 1: STDFA_R stda %f16, [%r0, %r31]
.word 0xc09fdb20 ! 1: LDDA_R ldda [%r31, %r0] 0xd9, %r0
.word 0xe19fc2c0 ! 1: LDDFA_R ldda [%r31, %r0], %f16
stxa %g3, [%g3] 0x57
.word 0xc09fdf00 ! 1: LDDA_R ldda [%r31, %r0] 0xf8, %r0
wrhpr %g0, 0xa11, %hpstate ! ta T_CHANGE_NONHPRIV
.word 0xda1fe180 ! 453: LDD_I ldd [%r31 + 0x0180], %r13
.word 0xda1fe1c0 ! 457: LDD_I ldd [%r31 + 0x01c0], %r13
.word 0xdbe7c3c0 ! 461: CASA_I casa [%r31] 0x1e, %r0, %r13
.word 0x91950004 ! 465: WRPR_PIL_R wrpr %r20, %r4, %pil
jmptr_8_253:
nop
nop
best_set_reg(0xe0200000, %r20, %r27)
.word 0xb7c6c000 ! 469: JMPL_R jmpl %r27 + %r0, %r27
.word 0xda77c000 ! 473: STX_R stx %r13, [%r31 + %r0]
splash_tba_8_259:
nop
ta T_CHANGE_PRIV
setx 0x0000000400380000, %r11, %r12
.word 0x8b90000c ! 477: WRPR_TBA_R wrpr %r0, %r12, %tba
#if (defined SPC || defined CMP1)
!$EV trig_pc_d(1, expr(@VA(.MAIN.intvec_8_262) , 16, 16)) -> intp(0,0,30,*,936,*,eb,1)
!$EV trig_pc_d(1, expr((@VA(.MAIN.intvec_8_262)&0xffffffff) , 16, 16)) -> intp(1,0,7,*,904,*,eb,1)
#else
nop
nop
set 0x24400691, %r28 !TTID : 6 (mask2tid(0x8))
#if (defined PORTABLE_CORE || MAX_THREADS == 8)
sethi %hi(0x3800), %r27
andn %r28, %r27, %r28
#ifdef PORTABLE_CORE
! Add CID to vector
ta T_CHANGE_HPRIV
ldxa [%g0]0x63, %r27
sllx %r27, 8, %r27
or %r27, %r28, %r28
#endif
#else
! Add CID IF tid matches
ifelse(6,mask2tid(0x8),`ta T_CHANGE_HPRIV;sethi %hi(0x3800), %r27;andn %r28, %r27, %r28;ldxa [%g0]0x63, %r27;sllx %r27, 8, %r27;or %r27, %r28, %r28 ')
#endif
ifelse(6,mask2tid(0x8),`.align 16')
stxa %r28, [%g0] 0x73
#endif
intvec_8_262:
#if (defined SPC || defined CMP1)
wrhpr %g0, 0x0, %halt ! HALT
#else
ifelse(6,mask2tid(0x8),`wrhpr %g0, 0x0, %halt ! HALT')
#endif
.word 0xa3b404c3 ! 481: FCMPNE32 fcmpne32 %d16, %d34, %r17
.word 0xe037e0c2 ! 485: STH_I sth %r16, [%r31 + 0x00c2]
splash_lsu_8_263:
nop
nop
ta T_CHANGE_HPRIV
set 0xc42eb640, %r2
mov 0x3, %r1
sllx %r1, 32, %r1
or %r1, %r2, %r2
.word 0x01400002 ! 1: FBPN fbn
stxa %r2, [%r0] ASI_LSU_CONTROL
.word 0x3d400001 ! 489: FBPULE fbule,a,pn %fcc0, <label_0x1>
.word 0x8d9028f1 ! 493: WRPR_PSTATE_I wrpr %r0, 0x08f1, %pstate
.word 0xe19fe140 ! 497: LDDFA_I ldda [%r31, 0x0140], %f16
splash_tba_8_270:
nop
ta T_CHANGE_PRIV
set 0x120000, %r12
.word 0x8b90000c ! 501: WRPR_TBA_R wrpr %r0, %r12, %tba
.word 0xe11fe178 ! 505: LDDF_I ldd [%r31, 0x0178], %f16
.word 0x8d802004 ! 509: WRFPRS_I wr %r0, 0x0004, %fprs
dvapa_8_277:
nop
nop
ta T_CHANGE_HPRIV
mov 0xc4c, %r20
mov 0xf, %r19
sllx %r20, 23, %r20
or %r19, %r20, %r19
stxa %r19, [%g0] ASI_LSU_CONTROL
mov 0x38, %r18
stxa %r31, [%r18]0x58
wrhpr %g0, 0x3c8, %hpstate ! ta T_CHANGE_NONHPRIV
.word 0xe1e7e000 ! 513: CASA_R casa [%r31] %asi, %r0, %r16
jmptr_8_279:
nop
nop
best_set_reg(0xe1200000, %r20, %r27)
.word 0xb7c6c000 ! 517: JMPL_R jmpl %r27 + %r0, %r27
mondo_8_280:
nop
nop
.word 0x87802025 ! 1: WRASI_I wr %r0, 0x0025, %asi
stxa %r6, [%r0+0x3c8] %asi
.word 0x87802088 ! 1: WRASI_I wr %r0, 0x0088, %asi
.word 0x9d90800d ! 521: WRPR_WSTATE_R wrpr %r2, %r13, %wstate
.word 0xe08fc2c0 ! 525: LDUBA_R lduba [%r31, %r0] 0x16, %r16
.word 0xe13fe1f0 ! 529: STDF_I std %f16, [0x01f0, %r31]
.word 0x8d802000 ! 533: WRFPRS_I wr %r0, 0x0000, %fprs
mondo_8_286:
nop
nop
.word 0x87802025 ! 1: WRASI_I wr %r0, 0x0025, %asi
stxa %r5, [%r0+0x3c0] %asi
.word 0x87802010 ! 1: WRASI_I wr %r0, 0x0010, %asi
.word 0x9d94c00a ! 537: WRPR_WSTATE_R wrpr %r19, %r10, %wstate
splash_tba_8_288:
nop
ta T_CHANGE_PRIV
setx 0x0000000000380000, %r11, %r12
.word 0x8b90000c ! 541: WRPR_TBA_R wrpr %r0, %r12, %tba
.word 0x08800001 ! 545: BLEU bleu <label_0x1>
nop
nop
ta T_CHANGE_HPRIV ! macro
donret_8_292:
rd %pc, %r12
mov HIGHVA_HIGHNUM, %r10
sllx %r10, 32, %r10
or %r12, %r10, %r12
add %r12, (donretarg_8_292-donret_8_292), %r12
add %r12, 0x8, %r11 ! nonseq tnpc
wrpr %g0, 0x1, %tl
wrpr %g0, %r12, %tpc
wrpr %g0, %r11, %tnpc
set (0x009c4c00 | (32 << 24)), %r13
and %r12, 0xfff, %r14
sllx %r14, 32, %r14
or %r13, %r14, %r20
wrpr %r20, %g0, %tstate
wrhpr %g0, 0xdcb, %htstate
best_set_reg(0x3a0, %g1, %g2)
wrpr %g0, %g2, %pstate ! rand=0 (8)
ldx [%r12+%r0], %g1
retry
donretarg_8_292:
.word 0x37400001 ! 549: FBPGE fbge,a,pn %fcc0, <label_0x1>
brcommon1_8_295:
nop
nop
setx common_target, %r12, %r27
lduw [%r27-4], %r12 ! Load common dest into dcache ..
stuw %r12, [%r27-4] ! Load common dest into dcache ..
ba,a .+12
.word 0xe1e7c200 ! 1: CASA_I casa [%r31] 0x10, %r0, %r16
ba,a .+8
jmpl %r27-4, %r27
.word 0xa1a509cd ! 553: FDIVd fdivd %f20, %f44, %f16
nop
nop
ta T_CHANGE_HPRIV
mov 0x1, %r11
splash_cmpr_8_298:
sllx %r11, 63, %r11
not %r11, %r11
rd %tick, %r10
#if (defined SPC || defined CMP1)
add %r10, 0x150, %r10
#else
add %r10, 0x380, %r10
#endif
and %r10, %r11, %r10
wrhpr %r10, %g0, %hsys_tick_cmpr
wrhpr %g0, 0x0, %halt ! HALT
rd %tick, %r10
#if (defined SPC || defined CMP1)
add %r10, 0x200, %r10
#else
add %r10, 0x900, %r10
#endif
and %r10, %r11, %r10
.word 0xaf80000a ! 1: WR_TICK_CMPR_REG_R wr %r0, %r10, %-
#if (defined SPC || defined CMP1)
!$EV trig_pc_d(1, expr(@VA(.MAIN.splash_cmpr_8_298)+8 , 16, 16)) -> intp(7,0,6,*,720,*,9f,1)
!$EV trig_pc_d(1, expr((@VA(.MAIN.splash_cmpr_8_298)&0xffffffff)+8 , 16, 16)) -> intp(7,0,11,*,928,*,9f,1)
#endif
wrhpr %g0, 0x0, %halt ! HALT
.word 0x81982695 ! 1: WRHPR_HPSTATE_I wrhpr %r0, 0x0695, %hpstate
.word 0x81b01021 ! 557: SIAM siam 1
.word 0x8980000a ! 561: WRTICK_R wr %r0, %r10, %tick
cancelint_8_302:
rdhpr %halt, %r13
.word 0x85880000 ! 565: ALLCLEAN <illegal instruction>
nop
nop
set 0xb9606565, %r28 !TTID : 5 (mask2tid(0x8))
#if (defined PORTABLE_CORE || MAX_THREADS == 8)
sethi %hi(0x3800), %r27
andn %r28, %r27, %r28
#ifdef PORTABLE_CORE
! Add CID to vector
ta T_CHANGE_HPRIV
ldxa [%g0]0x63, %r27
sllx %r27, 8, %r27
or %r27, %r28, %r28
#endif
#else
! Add CID IF tid matches
ifelse(5,mask2tid(0x8),`ta T_CHANGE_HPRIV;sethi %hi(0x3800), %r27;andn %r28, %r27, %r28;ldxa [%g0]0x63, %r27;sllx %r27, 8, %r27;or %r27, %r28, %r28 ')
#endif
sethi %hi(0x30000), %r27
andn %r28, %r27, %r28
ta T_CHANGE_HPRIV
ifelse(5,mask2tid(0x8),`.align 16')
stxa %r28, [%g0] 0x73
intvec_8_305:
.word 0x39400001 ! 569: FBPUGE fbuge,a,pn %fcc0, <label_0x1>
.word 0xe2cfd060 ! 573: LDSBA_R ldsba [%r31, %r0] 0x83, %r17
.word 0xa190200a ! 577: WRPR_GL_I wrpr %r0, 0x000a, %-
nop
nop
set 0x65a0ce20, %r28 !TTID : 6 (mask2tid(0x8))
#if (defined PORTABLE_CORE || MAX_THREADS == 8)
sethi %hi(0x3800), %r27
andn %r28, %r27, %r28
#ifdef PORTABLE_CORE
! Add CID to vector
ta T_CHANGE_HPRIV
ldxa [%g0]0x63, %r27
sllx %r27, 8, %r27
or %r27, %r28, %r28
#endif
#else
! Add CID IF tid matches
ifelse(6,mask2tid(0x8),`ta T_CHANGE_HPRIV;sethi %hi(0x3800), %r27;andn %r28, %r27, %r28;ldxa [%g0]0x63, %r27;sllx %r27, 8, %r27;or %r27, %r28, %r28 ')
#endif
sethi %hi(0x30000), %r27
andn %r28, %r27, %r28
ta T_CHANGE_HPRIV
ifelse(6,mask2tid(0x8),`.align 16')
stxa %r28, [%g0] 0x73
intvec_8_309:
.word 0xa5a249d3 ! 581: FDIVd fdivd %f40, %f50, %f18
trapasi_8_313:
nop
mov 0x10, %r1 ! (VA for ASI 0x5b)
.word 0xe2d84b60 ! 585: LDXA_R ldxa [%r1, %r0] 0x5b, %r17
.word 0xe277e1b0 ! 589: STX_I stx %r17, [%r31 + 0x01b0]
.word 0xc09fde20 ! 593: LDDA_R ldda [%r31, %r0] 0xf1, %r0
.word 0x8d9031ab ! 597: WRPR_PSTATE_I wrpr %r0, 0x11ab, %pstate
splash_lsu_8_322:
nop
nop
ta T_CHANGE_HPRIV
set 0x1f4937d3, %r2
mov 0x6, %r1
sllx %r1, 32, %r1
or %r1, %r2, %r2
.word 0x08800002 ! 1: BLEU bleu <label_0x2>
stxa %r2, [%r0] ASI_LSU_CONTROL
.word 0x3d400001 ! 601: FBPULE fbule,a,pn %fcc0, <label_0x1>
.word 0x8980000a ! 605: WRTICK_R wr %r0, %r10, %tick
.word 0xe31fe1a0 ! 609: LDDF_I ldd [%r31, 0x01a0], %f17
jmptr_8_328:
nop
nop
best_set_reg(0xe0200000, %r20, %r27)
.word 0xb7c6c000 ! 613: JMPL_R jmpl %r27 + %r0, %r27
intveclr_8_330:
nop
nop
ta T_CHANGE_HPRIV
setx 0xb75cf856382436a3, %r1, %r28
stxa %r28, [%g0] 0x72
wrhpr %g0, 0x38a, %hpstate ! ta T_CHANGE_NONHPRIV
.word 0x25400001 ! 617: FBPLG fblg,a,pn %fcc0, <label_0x1>
pmu_8_332:
nop
nop
setx 0xffffffb7ffffffab, %g1, %g7
.word 0xa3800007 ! 621: WR_PERF_COUNTER_R wr %r0, %r7, %-
.word 0x8780204f ! 625: WRASI_I wr %r0, 0x004f, %asi
splash_tba_8_337:
nop
ta T_CHANGE_PRIV
setx 0x0000000400380000, %r11, %r12
.word 0x8b90000c ! 629: WRPR_TBA_R wrpr %r0, %r12, %tba
#if (defined SPC || defined CMP1)
!$EV trig_pc_d(1, expr(@VA(.MAIN.intvec_8_338) , 16, 16)) -> intp(0,0,0,*,1016,*,cf,1)
!$EV trig_pc_d(1, expr((@VA(.MAIN.intvec_8_338)&0xffffffff) , 16, 16)) -> intp(7,0,30,*,736,*,cf,1)
#else
nop
nop
set 0x6f905661, %r28 !TTID : 6 (mask2tid(0x8))
#if (defined PORTABLE_CORE || MAX_THREADS == 8)
sethi %hi(0x3800), %r27
andn %r28, %r27, %r28
#ifdef PORTABLE_CORE
! Add CID to vector
ta T_CHANGE_HPRIV
ldxa [%g0]0x63, %r27
sllx %r27, 8, %r27
or %r27, %r28, %r28
#endif
#else
! Add CID IF tid matches
ifelse(6,mask2tid(0x8),`ta T_CHANGE_HPRIV;sethi %hi(0x3800), %r27;andn %r28, %r27, %r28;ldxa [%g0]0x63, %r27;sllx %r27, 8, %r27;or %r27, %r28, %r28 ')
#endif
ifelse(6,mask2tid(0x8),`.align 16')
stxa %r28, [%g0] 0x73
#endif
intvec_8_338:
.word 0x39400002 ! 633: FBPUGE fbuge,a,pn %fcc0, <label_0x2>
br_longdelay3_8_340:
nop
not %g0, %r27
jmpl %r27+0, %r27
.word 0x81982ddd ! 637: WRHPR_HPSTATE_I wrhpr %r0, 0x0ddd, %hpstate
intveclr_8_343:
nop
nop
ta T_CHANGE_HPRIV
setx 0xa4afc297afdd1d59, %r1, %r28
stxa %r28, [%g0] 0x72
wrhpr %g0, 0xdd2, %hpstate ! ta T_CHANGE_NONHPRIV
.word 0x05400001 ! 641: FBPLG fblg
ibp_8_344:
nop
nop
ta T_CHANGE_HPRIV
mov 8, %r18
rd %asi, %r12
wr %r0, 0x41, %asi
set sync_thr_counter4, %r23
#ifndef SPC
ldxa [%g0]0x63, %r8
and %r8, 0x38, %r8 ! Core ID
#ifndef PORTABLE_CORE
add %r8, %r23, %r23
#endif
#else
mov 0, %r8
#endif
mov 0x8, %r16
ibp_startwait8_344:
cas [%r23],%g0,%r16 !lock
brz,a %r16, continue_ibp_8_344
mov (~0x8&0xf), %r16
ld [%r23], %r16
ibp_wait8_344:
brnz %r16, ibp_wait8_344
ld [%r23], %r16
ba ibp_startwait8_344
mov 0x8, %r16
continue_ibp_8_344:
sllx %r16, %r8, %r16 !Mask for my core only
ldxa [0x58]%asi, %r17 !Running_status
wait_for_stat_8_344:
ldxa [0x50]%asi, %r13 !Running_rw
cmp %r13, %r17
bne,a %xcc, wait_for_stat_8_344
ldxa [0x58]%asi, %r17 !Running_status
stxa %r16, [0x68]%asi !Park (W1C)
ldxa [0x50]%asi, %r14 !Running_rw
wait_for_ibp_8_344:
ldxa [0x58]%asi, %r17 !Running_status
cmp %r14, %r17
bne,a %xcc, wait_for_ibp_8_344
ldxa [0x50]%asi, %r14 !Running_rw
ibp_doit8_344:
best_set_reg(0x000000567c1e55d3,%r19, %r20)
stxa %r20, [%r18]0x42
stxa %r16, [0x60] %asi !Unpark (W1S)
st %g0, [%r23] !clear lock
wr %r0, %r12, %asi !restore %asi
.word 0x20800002 ! 645: BN bn,a <label_0x2>
.word 0xd5e7c3c0 ! 649: CASA_I casa [%r31] 0x1e, %r0, %r10
.word 0xd497d920 ! 653: LDUHA_R lduha [%r31, %r0] 0xc9, %r10
jmptr_8_353:
nop
nop
best_set_reg(0xe1200000, %r20, %r27)
.word 0xb7c6c000 ! 657: JMPL_R jmpl %r27 + %r0, %r27
.word 0xd497c600 ! 661: LDUHA_R lduha [%r31, %r0] 0x30, %r10
.word 0xc19fe1a0 ! 665: LDDFA_I ldda [%r31, 0x01a0], %f0
.word 0xd4bfd000 ! 1: STDA_R stda %r10, [%r31 + %r0] 0x80
.word 0xd5e7d160 ! 1: CASA_I casa [%r31] 0x8b, %r0, %r10
mov 0xb2, %r30
.word 0x93d0001e ! 669: Tcc_R tne icc_or_xcc, %r0 + %r30
demap_8_359:
nop
mov 0x80, %g3
ta T_CHANGE_HPRIV
stxa %g3, [%g3] 0x57
.word 0xc09fdc40 ! 1: LDDA_R ldda [%r31, %r0] 0xe2, %r0
.word 0xe0bfc2c0 ! 1: STDA_R stda %r16, [%r31 + %r0] 0x16
.word 0xe09fdb20 ! 1: LDDA_R ldda [%r31, %r0] 0xd9, %r16
stxa %g3, [%g3] 0x57
.word 0xe09fda00 ! 1: LDDA_R ldda [%r31, %r0] 0xd0, %r16
.word 0xe09fc3e0 ! 1: LDDA_R ldda [%r31, %r0] 0x1f, %r16
.word 0xe09fdf00 ! 1: LDDA_R ldda [%r31, %r0] 0xf8, %r16
stxa %g3, [%g3] 0x5f
.word 0xc09fdf00 ! 1: LDDA_R ldda [%r31, %r0] 0xf8, %r0
stxa %g3, [%g3] 0x57
wrhpr %g0, 0xbc3, %hpstate ! ta T_CHANGE_NONHPRIV
.word 0xd41fe13e ! 673: LDD_I ldd [%r31 + 0x013e], %r10
memptr_8_362:
set 0x60740000, %r31
.word 0x8584f186 ! 677: WRCCR_I wr %r19, 0x1186, %ccr
jmptr_8_363:
nop
nop
best_set_reg(0xe0200000, %r20, %r27)
.word 0xb7c6c000 ! 681: JMPL_R jmpl %r27 + %r0, %r27
jmptr_8_366:
nop
nop
best_set_reg(0xe1200000, %r20, %r27)
.word 0xb7c6c000 ! 685: JMPL_R jmpl %r27 + %r0, %r27
memptr_8_369:
set user_data_start, %r31
.word 0x85847bd5 ! 689: WRCCR_I wr %r17, 0x1bd5, %ccr
nop
nop
ta T_CHANGE_HPRIV ! macro
donret_8_370:
rd %pc, %r12
mov HIGHVA_HIGHNUM, %r10
sllx %r10, 32, %r10
or %r12, %r10, %r12
add %r12, (donretarg_8_370-donret_8_370+4), %r12
add %r12, 0x4, %r11 ! seq tnpc
wrpr %g0, 0x1, %tl
wrpr %g0, %r12, %tpc
wrpr %g0, %r11, %tnpc
set (0x004b8200 | (0x4f << 24)), %r13
and %r12, 0xfff, %r14
sllx %r14, 32, %r14
or %r13, %r14, %r20
wrpr %r20, %g0, %tstate
wrhpr %g0, 0x1e16, %htstate
wrhpr %g0, 0x31a, %hpstate ! rand=1 (8)
ldx [%r12+%r0], %g1
retry
donretarg_8_370:
.word 0xd46fe17b ! 693: LDSTUB_I ldstub %r10, [%r31 + 0x017b]
brcommon3_8_371:
nop
nop
setx common_target, %r12, %r27
lduw [%r27-0], %r12 ! Load common dest into dcache ..
stuw %r12, [%r27-0] ! Load common dest into dcache ..
ba,a .+12
.word 0xd537e0b0 ! 1: STQF_I - %f10, [0x00b0, %r31]
ba,a .+8
jmpl %r27-4, %r27
.word 0xd51fe070 ! 697: LDDF_I ldd [%r31, 0x0070], %f10
.word 0xd477c000 ! 701: STX_R stx %r10, [%r31 + %r0]
.word 0xd537c000 ! 705: STQF_R - %f10, [%r0, %r31]
.word 0xd43fe040 ! 709: STD_I std %r10, [%r31 + 0x0040]
.word 0x91940006 ! 713: WRPR_PIL_R wrpr %r16, %r6, %pil
.word 0xd4800c00 ! 717: LDUWA_R lduwa [%r0, %r0] 0x60, %r10
.word 0xd527e080 ! 721: STF_I st %f10, [0x0080, %r31]
intveclr_8_383:
nop
nop
ta T_CHANGE_HPRIV
setx 0x60a4c0c3617048c6, %r1, %r28
stxa %r28, [%g0] 0x72
.word 0x25400001 ! 725: FBPLG fblg,a,pn %fcc0, <label_0x1>
demap_8_386:
nop
mov 0x80, %g3
ta T_CHANGE_HPRIV
stxa %g3, [%g3] 0x5f
stxa %g3, [%g3] 0x5f
.word 0xc19fdd40 ! 1: LDDFA_R ldda [%r31, %r0], %f0
.word 0xe09fdb40 ! 1: LDDA_R ldda [%r31, %r0] 0xda, %r16
.word 0xc0bfde20 ! 1: STDA_R stda %r0, [%r31 + %r0] 0xf1
stxa %g3, [%g3] 0x5f
wrhpr %g0, 0x6cb, %hpstate ! ta T_CHANGE_NONHPRIV
.word 0xd41fe160 ! 729: LDD_I ldd [%r31 + 0x0160], %r10
.word 0xd4bfe124 ! 733: STDA_I stda %r10, [%r31 + 0x0124] %asi
memptr_8_389:
set 0x60540000, %r31
.word 0x858167bc ! 737: WRCCR_I wr %r5, 0x07bc, %ccr
.word 0x8980000a ! 741: WRTICK_R wr %r0, %r10, %tick
.word 0xd5e7c3c0 ! 745: CASA_I casa [%r31] 0x1e, %r0, %r10
splash_lsu_8_393:
nop
nop
ta T_CHANGE_HPRIV
set 0x176acb5c, %r2
mov 0x2, %r1
sllx %r1, 32, %r1
or %r1, %r2, %r2
stxa %r2, [%r0] ASI_LSU_CONTROL
.word 0x3d400001 ! 749: FBPULE fbule,a,pn %fcc0, <label_0x1>
br_longdelay4_8_395:
nop
not %g0, %r27
jmpl %r27+0, %r27
.word 0x9d902000 ! 753: WRPR_WSTATE_I wrpr %r0, 0x0000, %wstate
brcommon3_8_399:
nop
nop
setx common_target, %r12, %r27
lduw [%r27-0], %r12 ! Load common dest into dcache ..
stuw %r12, [%r27-4] ! Load common dest into dcache ..
ba,a .+12
.word 0xd46fe140 ! 1: LDSTUB_I ldstub %r10, [%r31 + 0x0140]
ba,a .+8
jmpl %r27-0, %r27
.word 0xd51fe0f0 ! 757: LDDF_I ldd [%r31, 0x00f0], %f10
.word 0xd43fe069 ! 761: STD_I std %r10, [%r31 + 0x0069]
nop
nop
ta T_CHANGE_HPRIV
mov 0x1, %r11
splash_cmpr_8_403:
sllx %r11, 63, %r11
not %r11, %r11
rd %tick, %r10
#if (defined SPC || defined CMP1)
add %r10, 0x250, %r10
#else
add %r10, 0x900, %r10
#endif
and %r10, %r11, %r10
wrhpr %r10, %g0, %hsys_tick_cmpr
wrhpr %g0, 0x0, %halt ! HALT
rd %tick, %r10
#if (defined SPC || defined CMP1)
add %r10, 0x250, %r10
#else
add %r10, 0x700, %r10
#endif
and %r10, %r11, %r10
.word 0xb380000a ! 1: WR_STICK_CMPR_REG_R wr %r0, %r10, %-
#if (defined SPC || defined CMP1)
!$EV trig_pc_d(1, expr(@VA(.MAIN.splash_cmpr_8_403)+8 , 16, 16)) -> intp(0,0,30,*,640,*,b,1)
!$EV trig_pc_d(1, expr((@VA(.MAIN.splash_cmpr_8_403)&0xffffffff)+8 , 16, 16)) -> intp(5,0,17,*,736,*,b,1)
#endif
wrhpr %g0, 0x0, %halt ! HALT
.word 0x819835c3 ! 1: WRHPR_HPSTATE_I wrhpr %r0, 0x15c3, %hpstate
.word 0x81b01021 ! 765: SIAM siam 1
memptr_8_407:
set 0x60740000, %r31
.word 0x85827a3c ! 769: WRCCR_I wr %r9, 0x1a3c, %ccr
br_badelay3_8_410:
.word 0x20800001 ! 1: BN bn,a <label_0x1>
.word 0xcf64184a ! Random illegal ?
.word 0xd514c011 ! 1: LDQF_R - [%r19, %r17], %f10
.word 0xa7a44831 ! 773: FADDs fadds %f17, %f17, %f19
splash_lsu_8_411:
nop
nop
ta T_CHANGE_HPRIV
set 0xd35eef71, %r2
mov 0x7, %r1
sllx %r1, 32, %r1
or %r1, %r2, %r2
stxa %r2, [%r0] ASI_LSU_CONTROL
ta T_CHANGE_NONHPRIV
.word 0x1d400001 ! 777: FBPULE fbule
.word 0x26800001 ! 781: BL bl,a <label_0x1>
pmu_8_417:
nop
nop
ta T_CHANGE_PRIV
setx 0xffffffb6ffffffa4, %g1, %g7
.word 0xa3800007 ! 785: WR_PERF_COUNTER_R wr %r0, %r7, %-
.word 0x81460000 ! 789: RD_STICK_REG stbar
demap_8_421:
nop
mov 0x80, %g3
ta T_CHANGE_HPRIV
.word 0x24800001 ! 1: BLE ble,a <label_0x1>
stxa %g3, [%g3] 0x57
.word 0xe0bfdb20 ! 1: STDA_R stda %r16, [%r31 + %r0] 0xd9
.word 0xe19fdb20 ! 1: LDDFA_R ldda [%r31, %r0], %f16
stxa %g3, [%g3] 0x57
.word 0xc1bfdf20 ! 1: STDFA_R stda %f0, [%r0, %r31]
stxa %g3, [%g3] 0x57
.word 0xc19fdf20 ! 1: LDDFA_R ldda [%r31, %r0], %f0
stxa %g3, [%g3] 0x5f
.word 0xc1bfdc40 ! 1: STDFA_R stda %f0, [%r0, %r31]
wrhpr %g0, 0x49a, %hpstate ! ta T_CHANGE_NONHPRIV
.word 0xd21fe1a8 ! 793: LDD_I ldd [%r31 + 0x01a8], %r9
memptr_8_424:
set 0x60540000, %r31
.word 0x8582e95c ! 797: WRCCR_I wr %r11, 0x095c, %ccr
nop
nop
ta T_CHANGE_PRIV
wrpr %g0, %g0, %gl
nop
nop
.text
setx join_lbl_0_0, %g1, %g2
jmp %g2
nop
fork_lbl_0_3:
! Code for Template instance: _t1_
#ifndef PORTABLE_CORE
#define SPU_8
#endif
.text
.global _t1_main
_t1_main:
!# Switch to hpriv mode
ta T_CHANGE_HPRIV
!# trap counter
mov 0, %i6
set 0xad5, %g3
stxa %g3, [%g0] ASI_SPARC_PWR_MGMT
! Get core ID & offset
#ifndef PORTABLE_CORE
ldxa [%g0]0x63, %o1
srlx %o1, 3, %o1
sllx %o1, 20, %o1 !! %o1 has core ID offset
#else
mov %g0, %o1
#endif
! Set up for PMU
set 0x2b308db3, %g2
wr %g2, %g0, %pcr
setx 0xffffffb5ffffffa3, %g2, %g7
wr %g7, %g0, %pic
!# setup ASI register to point to SPU
wr %g0, 0x40, %asi
!# Make sure CWQ is currently disabled, not busy, not terminated, no protocol error; else fail
ldxa [%g0 + ASI_SPU_CWQ_CSR] %asi, %l1
and %l1, 0xf, %l2
cmp %g0, %l2
bne,pn %xcc, _t1_fail
nop
!# allocate control word queue (e.g., setup head/tail/first/last registers)
setx _t1_cwq_base, %g1, %l6
#ifdef SPU_8
#if (MAX_THREADS > 8)
! Add core ID offset
or %l6, %o1, %l6
#endif
#endif
!# write base addr to first, head, and tail ptr
!# first store to first
stxa %l6, [%g0 + ASI_SPU_CWQ_FIRST] %asi
ldxa [%g0 + ASI_SPU_CWQ_FIRST] %asi, %l1
!# Mask off upper 16 bits
setx 0x0000ffffffffffff, %l5, %l0
and %l0, %l6, %l2
cmp %l1, %l2
bne,pn %xcc, _t1_fail
nop
!# then to head
stxa %l6, [%g0 + ASI_SPU_CWQ_HEAD] %asi
ldxa [%g0 + ASI_SPU_CWQ_HEAD] %asi, %l1
cmp %l1, %l2
bne,pn %xcc, _t1_fail
nop
!# then to tail
stxa %l6, [%g0 + ASI_SPU_CWQ_TAIL] %asi
ldxa [%g0 + ASI_SPU_CWQ_TAIL] %asi, %l1
cmp %l1, %l2
bne,pn %xcc, _t1_fail
nop
!# then end of CWQ region to LAST
setx _t1_cwq_last, %g1, %l5
#ifdef SPU_8
#if (MAX_THREADS > 8)
! Add core ID offset
or %l5, %o1, %l5
#endif
#endif
stxa %l5, [%g0 + ASI_SPU_CWQ_LAST] %asi
ldxa [%g0 + ASI_SPU_CWQ_LAST] %asi, %l1
!# Mask off upper 16 bits
and %l0, %l5, %l2
cmp %l1, %l2
bne,pn %xcc, _t1_fail
nop
or %g0, 0x0, %i4 !# _t1_counter : Increment _t1_by 1 _t1_to _t1_step _t1_over CWs
or %g0, 0x0, %i5 !# _t1_offset : Increment _t1_by 8 _t1_to _t1_step _t1_over CWs
_t1_main_loop:
setx _t1_spu_op_array, %l1, %l2
#ifdef SPU_8
#if (MAX_THREADS > 8)
! Add core ID offset
or %l2, %o1, %l2
#endif
#endif
ldx [%l2 + %i5], %i1
cmp %i1, 7
bne _t1_not_ssl
mov %i5, %g5 !# Save _t1_real _t1_offset - _t1_if _t1_sslkey _t1_it _t1_has _t1_to _t1_be 0x10 _t1_aligned
btst 8, %i5
bz _t1_not_ssl
nop
add %i5, 8, %i5
_t1_not_ssl:
cmp %i1, 8
bg _t1_fail
mulx %i1, 8, %i1 !# Calc _t1_index _t1_into _t1_toc
setx _t1_table_of_context, %l1, %l2
#ifdef SPU_8
#if (MAX_THREADS > 8)
! Add core ID offset
or %l2, %o1, %l2
#endif
#endif
ldx [%l2 + %i1], %l3 !# l3 = _t1_toc _t1_of _t1_current _t1_operation
ldx [%l3 + 0x40], %l4 !# l4 = alignment array
!# set CWQ data
ldx [%l3], %l2
ldx [%l2 + %i5], %l2 !# Get Control Word _t1_from _t1_array
mov %l2, %i7 !# Save _t1_it _t1_for _t1_later
srlx %i7, 48, %l1
and %l1, 1, %l1
cmp %l1, 1
bne,pn %xcc, _t1_write_cwq
nop
inc %i6 !# increase _t1_interrupt _t1_counter
_t1_write_cwq:
!# write CWQ entry (%l6 points to CWQ)
stx %l2, [%l6 + 0x0]
!# source address
ldx [%l3 + 0x8], %l2
ldx [%l4 + 0x8], %l1
add %l2, %i5, %l2
add %l2, %l1, %l2 !# _t1_WARNING : Misaligned _t1_address
stx %l2, [%l6 + 0x8]
!# Authentication Key Address (40-bit)
ldx [%l3 + 0x10], %l2
ldx [%l4 + 0x10], %l1
add %l2, %i5, %l2
add %l2, %l1, %l2 !# _t1_WARNING : Misaligned _t1_address
stx %l2, [%l6 + 0x10]
!# Authentication IV Address (40-bit)
ldx [%l3 + 0x18], %l2
ldx [%l4 + 0x18], %l1
add %l2, %i5, %l2
add %l2, %l1, %l2 !# _t1_WARNING : Misaligned _t1_address
stx %l2, [%l6 + 0x18]
!# Authentication FSAS Address (40-bit)
ldx [%l3 + 0x20], %l2
ldx [%l4 + 0x20], %l1
add %l2, %i5, %l2
add %l2, %l1, %l2 !# _t1_WARNING : Misaligned _t1_address
stx %l2, [%l6 + 0x20]
!# Encryption Key Address (40-bit)
ldx [%l3 + 0x28], %l2
ldx [%l4 + 0x28], %l1
add %l2, %i5, %l2
add %l2, %l1, %l2 !# _t1_WARNING : Misaligned _t1_address
stx %l2, [%l6 + 0x28]
!# Encryption Initialization Vector Address (40-bit)
ldx [%l3 + 0x30], %l2
ldx [%l4 + 0x30], %l1
add %l2, %i5, %l2
add %l2, %l1, %l2 !# _t1_WARNING : Misaligned _t1_address
stx %l2, [%l6 + 0x30]
!# Destination Address (40-bit)
ldx [%l3 + 0x38], %l2
ldx [%l4 + 0x38], %l1
add %l2, %i5, %l2
add %l2, %l1, %l2 !# _t1_WARNING : Misaligned _t1_address
stx %l2, [%l6 + 0x38]
!# Make sure all these stores get to memory before we start
membar #Sync
ldx [%l6 + 0x20], %l2
ldx [%l6 + 0x28], %l2
ldx [%l6 + 0x30], %l2
ldx [%l6 + 0x38], %l2
membar #Sync
wrpr %g0, 0x51, %pstate
!# Set the enabled bit and reset the other bits
or %g0, 0x1, %g1
stxa %g1, [%g0 + ASI_SPU_CWQ_CSR] %asi
!# Kick off the CWQ operation by writing to the CWQ_TAIL
!# Now add 1 (actually 8*8B) to tail pointer
ldxa [%g0 + ASI_SPU_CWQ_TAIL] %asi, %l2
add %l2, 0x40, %l2
stxa %l2, [%g0 + ASI_SPU_CWQ_TAIL] %asi
ldxa [%g0 + ASI_SPU_CWQ_TAIL] %asi, %l1
cmp %l1, %l2
bne,pn %xcc, _t1_fail
nop
!# CWQ_SYNC operation...
ldxa [%g0 + 0x30] %asi, %l1
rdhpr %halt, %g7
wrpr %g0, 0xb5, %pstate
andn %l1, 0x10, %l1 !# clear interrupt request bit
addcc %l1, -1, %i0
bne _t1_fail !# test for unexpected protocal error
nop
ldxa [%g0 + ASI_SPU_CWQ_HEAD] %asi, %l1
ldxa [%g0 + ASI_SPU_CWQ_TAIL] %asi, %l1
!# I want to check all the data
or %g0, 260, %i0
or %g0, %g0, %g3
_t1_check_msg:
ldx [%l3 + 0x8], %l5 !# Needed _t1_for Inplace
add %l5, %i5, %l5
ldx [%l5 + %g3], %l1
add %g3, 0x8, %g3 !# i++
addcc %i0, -1, %i0
bgt _t1_check_msg
nop
!# I want to check all the data
or %g0, 260, %i0
or %g0, %g0, %g3
_t1_check_results:
ldx [%l3 + 0x38], %l5 !# Needed _t1_for Copy
add %l5, %i5, %l5
ldx [%l5 + %g3], %l1
add %g3, 0x8, %g3 !# i++
addcc %i0, -1, %i0
bgt _t1_check_results
nop
or %g0, 0x8, %i0
or %g0, %g0, %g3
_t1_check_sfas:
ldx [%l3 + 0x20], %l5
ldx [%l5 + %g3], %l1
add %g3, 0x8, %g3 !# i++
addcc %i0, -1, %i0
bgt _t1_check_sfas
nop
!# I want to check all the State 32 words + 2 bytes XY
or %g0, 0x23, %i0
or %g0, %g0, %g3
_t1_check_state:
ldx [%l3 + 0x28], %l5 !# Needed _t1_for Streamout
ldx [%l5 + %g3], %l1
add %g3, 0x8, %g3 !# i++
addcc %i0, -1, %i0
bgt _t1_check_state
nop
mov %g5, %i5
add %l6, 0x40, %l6 !# next CWQ address
add %i5, 8, %i5 !# next _t1_offset
add %i4, 1, %i4 !# loop _t1_counter
cmp %i4, 9
bl _t1_main_loop
nop
!call check_int_cnt !# Check #ints (assuming all have happened at this time!)
nop
EXIT_GOOD
_t1_fail:
EXIT_BAD
_t1_check_int_cnt:
cmp %g0, %i6
bne,pn %xcc, _t1_fail
nop
retl
nop
! diag source
.word 0x9f802120 ! 1: SIR sir 0x0120
nop
nop
ta T_CHANGE_PRIV
wrpr %g0, %g0, %gl
nop
nop
.text
setx join_lbl_0_0, %g1, %g2
jmp %g2
nop
fork_lbl_0_2:
master_thread_stuff:
setup_tick:
setx 0x6188efd66d30b56a, %r1, %r17
wrpr %g0, %r17, %tick
rd %asi, %r12
#ifdef XIR_RND_CORES
setup_xir_2:
setx 0xaffde9dcd9d3515b, %r1, %r28
mov 0x30, %r17
stxa %r28, [%r17] 0x41
#endif
#ifdef SPLASH_HIDECR
mov 8, %r1
set SPLASH_HIDECR, %r2
sllx %r2, 32, %r2
stxa %r2, [%r1] 0x45
#endif
#if (MULTIPASS > 0)
mov 0x38, %g1
ldxa [%g1]ASI_SCRATCHPAD, %r10
brnz %g1, unlock_sync_thds_2
wrpr %g0, %g0, %pstate
#endif
#ifndef NO_INTERNAL_SPU
setup_spu_2:
wr %g0, 0x40, %asi
!# allocate control word queue (e.g., setup head/tail/first/last registers)
set CWQ_BASE, %l6
#ifndef SPC
ldxa [%g0]0x63, %o2
and %o2, 0x38, %o2
#ifndef PORTABLE_CORE
sllx %o2, 5, %o2 !(CID*256)
add %l6, %o2, %l6
#endif
#endif
!# write base addr to first, head, and tail ptr
!# first store to first
stxa %l6, [%g0 + ASI_SPU_CWQ_FIRST] %asi !# first store to first
stxa %l6, [%g0 + ASI_SPU_CWQ_HEAD] %asi !# then to head
stxa %l6, [%g0 + ASI_SPU_CWQ_TAIL] %asi !# then to tail
setx CWQ_LAST, %g1, %l5 !# then end of CWQ region to LAST
#ifndef SPC
add %l5, %o2, %l5
#endif
stxa %l5, [%g0 + ASI_SPU_CWQ_LAST] %asi
!# set CWQ control word ([39:37] is strand ID ..)
best_set_reg(0x206100f0, %l1, %l2) !# Control Word
sllx %l2, 32, %l2
!# write CWQ entry (%l6 points to CWQ)
stx %l2, [%l6 + 0x0]
setx msg, %g1, %l2
stx %l2, [%l6 + 0x8] !# source address
stx %g0, [%l6 + 0x10] !# Authentication Key Address (40-bit)
stx %g0, [%l6 + 0x18] !# Authentication IV Address (40-bit)
stx %g0, [%l6 + 0x20] !# Authentication FSAS Address (40-bit)
stx %g0, [%l6 + 0x28] !# Encryption Key Address (40-bit)
stx %g0, [%l6 + 0x30] !# Encryption Initialization Vector Address (40-bit)
setx results, %g1, %o3
stx %o3, [%l6 + 0x38] !# Destination Address (40-bit)
membar #Sync
ldxa [%g0 + ASI_SPU_CWQ_TAIL] %asi, %l2
add %l2, 0x40, %l2
stxa %l2, [%g0 + ASI_SPU_CWQ_TAIL] %asi
!# Kick off the CWQ operation by writing to the CWQ_CSR
!# Set the enabled bit and reset the other bits
or %g0, 0x1, %g1
stxa %g1, [%g0 + ASI_SPU_CWQ_CSR] %asi
#endif
unlock_sync_thds_2:
set sync_thr_counter6, %r23
#if (!defined SPC && ! defined PORTABLE_CORE)
ldxa [%g0]0x63, %o2
and %o2, 0x38, %o2
add %o2, %r23, %r23
#endif
st %r0, [%r23] !unlock sync_thr_counter6
sub %r23, 64, %r23
st %r0, [%r23] !unlock sync_thr_counter5
sub %r23, 64, %r23
st %r0, [%r23] !unlock sync_thr_counter4
wr %r0, %r12, %asi
wrhpr %g0, 0xa02, %hpstate ! ta T_CHANGE_NONHPRIV
cmp_2_0:
nop
nop
ta T_CHANGE_HPRIV
rd %asi, %r12
wr %r0, 0x41, %asi
set sync_thr_counter4, %r23
#ifndef SPC
ldxa [%g0]0x63, %r8
and %r8, 0x38, %r8 ! Core ID
#ifndef PORTABLE_CORE
add %r8, %r23, %r23
#endif
mov 0xff, %r9
#if (!defined PORTABLE_CORE || MAX_THREADS == 8)
xor %r9, 0x2, %r9 ! My core mask
#else
xor %r9, 0x2, %r9
#endif
sllx %r9, %r8, %r9 ! My core mask
#else
mov 0, %r8
mov 0xff, %r9
xor %r9, 0x2, %r9 ! My core mask
#endif
mov 0x2, %r10
cmp_startwait2_0:
cas [%r23],%g0,%r10 !lock
brz,a %r10, continue_cmp_2_0
ldxa [0x50]%asi, %r13 !Running_rw
ld [%r23], %r10
cmp_wait2_0:
brnz,a %r10, cmp_wait2_0
ld [%r23], %r10
ba cmp_startwait2_0
mov 0x2, %r10
continue_cmp_2_0:
ldxa [0x58]%asi, %r14 !Running_status
xnor %r14, %r13, %r14 !Bits equal
#ifndef PORTABLE_CORE
brz,a %r8, cmp_multi_core_2_0
#endif
mov 0x36, %r17
#ifndef PORTABLE_CORE
best_set_reg(0xf79661de7277b9dc, %r16, %r17)
#else
sllx %r17, %r8, %r17
#endif
cmp_multi_core_2_0:
and %r14, %r17, %r14 !Apply set/clear mask to bits equal
and %r14, %r9, %r14 !Apply core-mask
stxa %r14, [0x68]%asi
st %g0, [%r23] !clear lock
wr %g0, %r12, %asi
.word 0x1f400001 ! 1: FBPO fbo
.word 0x8d903acd ! 1: WRPR_PSTATE_I wrpr %r0, 0x1acd, %pstate
frzptr_2_3:
nop
nop
best_set_reg(0x3cb40000+0x1ffc, %r20, %r27)
ldx [%r27+0xc], %r20
jmpl %r27, %r27
.word 0x20800001 ! 5: BN bn,a <label_0x1>
jmptr_2_5:
nop
nop
best_set_reg(0xe0a00000, %r20, %r27)
.word 0xb7c6c000 ! 9: JMPL_R jmpl %r27 + %r0, %r27
.word 0xc32fc000 ! 13: STXFSR_R st-sfr %f1, [%r0, %r31]
.word 0xda97c720 ! 17: LDUHA_R lduha [%r31, %r0] 0x39, %r13
jmptr_2_9:
nop
nop
best_set_reg(0xe1a00000, %r20, %r27)
.word 0xb7c6c000 ! 21: JMPL_R jmpl %r27 + %r0, %r27
splash_tick_2_11:
nop
nop
ta T_CHANGE_HPRIV
best_set_reg(0x35679ea172b90d6a, %r16, %r17)
.word 0x8980000a ! 25: WRTICK_R wr %r0, %r10, %tick
.word 0xda8008a0 ! 29: LDUWA_R lduwa [%r0, %r0] 0x45, %r13
.word 0xa3b344c9 ! 33: FCMPNE32 fcmpne32 %d44, %d40, %r17
.word 0xe2800b00 ! 37: LDUWA_R lduwa [%r0, %r0] 0x58, %r17
.word 0xe24fc000 ! 41: LDSB_R ldsb [%r31 + %r0], %r17
.word 0x87afca40 ! 1: FCMPd fcmpd %fcc<n>, %f62, %f0
.word 0xe33fe0a0 ! 1: STDF_I std %f17, [0x00a0, %r31]
mov 0xb5, %r30
.word 0x91d0001e ! 45: Tcc_R ta icc_or_xcc, %r0 + %r30
demap_2_21:
nop
mov 0x80, %g3
ta T_CHANGE_HPRIV
.word 0x2f400001 ! 1: FBPU fbu,a,pn %fcc0, <label_0x1>
stxa %g3, [%g3] 0x57
.word 0xe19fdc40 ! 1: LDDFA_R ldda [%r31, %r0], %f16
wrhpr %g0, 0xa88, %hpstate ! ta T_CHANGE_NONHPRIV
.word 0xe21fe1b0 ! 49: LDD_I ldd [%r31 + 0x01b0], %r17
.word 0xe247c000 ! 53: LDSW_R ldsw [%r31 + %r0], %r17
splash_lsu_2_22:
nop
nop
ta T_CHANGE_HPRIV
set 0x0b900940, %r2
mov 0x5, %r1
sllx %r1, 32, %r1
or %r1, %r2, %r2
.word 0x25400001 ! 1: FBPLG fblg,a,pn %fcc0, <label_0x1>
stxa %r2, [%r0] ASI_LSU_CONTROL
.word 0x1d400001 ! 57: FBPULE fbule
demap_2_25:
nop
mov 0x80, %g3
ta T_CHANGE_HPRIV
.word 0x2b400001 ! 1: FBPUG fbug,a,pn %fcc0, <label_0x1>
stxa %g3, [%g3] 0x57
.word 0xe19fde20 ! 1: LDDFA_R ldda [%r31, %r0], %f16
.word 0xe09fdd40 ! 1: LDDA_R ldda [%r31, %r0] 0xea, %r16
.word 0xc0bfdb40 ! 1: STDA_R stda %r0, [%r31 + %r0] 0xda
stxa %g3, [%g3] 0x5f
stxa %g3, [%g3] 0x57
.word 0xe0bfdb40 ! 1: STDA_R stda %r16, [%r31 + %r0] 0xda
stxa %g3, [%g3] 0x5f
.word 0xe09fda00 ! 1: LDDA_R ldda [%r31, %r0] 0xd0, %r16
.word 0xe09fdf20 ! 1: LDDA_R ldda [%r31, %r0] 0xf9, %r16
.word 0xc1bfdb20 ! 1: STDFA_R stda %f0, [%r0, %r31]
stxa %g3, [%g3] 0x5f
stxa %g3, [%g3] 0x5f
.word 0xe09fda60 ! 1: LDDA_R ldda [%r31, %r0] 0xd3, %r16
wrhpr %g0, 0x5c0, %hpstate ! ta T_CHANGE_NONHPRIV
.word 0xe21fe160 ! 61: LDD_I ldd [%r31 + 0x0160], %r17
nop
nop
mov 0x1, %r11
splash_cmpr_2_28:
sllx %r11, 63, %r11
not %r11, %r11
rd %tick, %r10
#if (defined SPC || defined CMP1)
add %r10, 0x150, %r10
#else
add %r10, 0x550, %r10
#endif
and %r10, %r11, %r10
rd %tick, %r10
#if (defined SPC || defined CMP1)
add %r10, 0x150, %r10
#else
add %r10, 0x900, %r10
#endif
and %r10, %r11, %r10
.word 0xb380000a ! 1: WR_STICK_CMPR_REG_R wr %r0, %r10, %-
#if (defined SPC || defined CMP1)
!$EV trig_pc_d(1, expr(@VA(.MAIN.splash_cmpr_2_28)+8 , 16, 16)) -> intp(6,0,14,*,968,*,33,1)
!$EV trig_pc_d(1, expr((@VA(.MAIN.splash_cmpr_2_28)&0xffffffff)+8 , 16, 16)) -> intp(3,0,29,*,688,*,33,1)
#endif
wrhpr %g0, 0x0, %halt ! HALT
.word 0x81b01021 ! 65: SIAM siam 1
.word 0xc19fe080 ! 69: LDDFA_I ldda [%r31, 0x0080], %f0
.word 0xa1902002 ! 73: WRPR_GL_I wrpr %r0, 0x0002, %-
jmptr_2_34:
nop
nop
best_set_reg(0xe0a00000, %r20, %r27)
.word 0xb7c6c000 ! 77: JMPL_R jmpl %r27 + %r0, %r27
nop
nop
ta T_CHANGE_HPRIV ! macro
donret_2_35:
rd %pc, %r12
mov HIGHVA_HIGHNUM, %r10
sllx %r10, 32, %r10
or %r12, %r10, %r12
add %r12, (donretarg_2_35-donret_2_35+4), %r12
add %r12, 0x4, %r11 ! seq tnpc
andn %r11, %r10, %r11 ! low VA tnpc
wrpr %g0, 0x1, %tl
wrpr %g0, %r12, %tpc
wrpr %g0, %r11, %tnpc
set (0x00c4e900 | (28 << 24)), %r13
and %r12, 0xfff, %r14
sllx %r14, 32, %r14
or %r13, %r14, %r20
wrpr %r20, %g0, %tstate
wrhpr %g0, 0x916, %htstate
best_set_reg(0xdeb, %g1, %g2)
wrpr %g0, %g2, %pstate ! rand=0 (2)
done
donretarg_2_35:
.word 0x81983e05 ! 81: WRHPR_HPSTATE_I wrhpr %r0, 0x1e05, %hpstate
#if (defined SPC || defined CMP1)
!$EV trig_pc_d(1, expr(@VA(.MAIN.intvec_2_36) , 16, 16)) -> intp(6,0,14,*,992,*,7f,1)
!$EV trig_pc_d(1, expr((@VA(.MAIN.intvec_2_36)&0xffffffff) , 16, 16)) -> intp(1,0,26,*,1000,*,7f,1)
#else
nop
nop
set 0x505077bf, %r28 !TTID : 7 (mask2tid(0x2))
#if (defined PORTABLE_CORE || MAX_THREADS == 8)
sethi %hi(0x3800), %r27
andn %r28, %r27, %r28
#ifdef PORTABLE_CORE
! Add CID to vector
ta T_CHANGE_HPRIV
ldxa [%g0]0x63, %r27
sllx %r27, 8, %r27
or %r27, %r28, %r28
#endif
#else
! Add CID IF tid matches
ifelse(7,mask2tid(0x2),`ta T_CHANGE_HPRIV;sethi %hi(0x3800), %r27;andn %r28, %r27, %r28;ldxa [%g0]0x63, %r27;sllx %r27, 8, %r27;or %r27, %r28, %r28 ')
#endif
ifelse(7,mask2tid(0x2),`.align 16')
stxa %r28, [%g0] 0x73
#endif
intvec_2_36:
.word 0x99b484d4 ! 85: FCMPNE32 fcmpne32 %d18, %d20, %r12
.word 0x9484400b ! 89: ADDcc_R addcc %r17, %r11, %r10
nop
nop
set 0x2950f7b3, %r28 !TTID : 7 (mask2tid(0x2))
#if (defined PORTABLE_CORE || MAX_THREADS == 8)
sethi %hi(0x3800), %r27
andn %r28, %r27, %r28
#ifdef PORTABLE_CORE
! Add CID to vector
ta T_CHANGE_HPRIV
ldxa [%g0]0x63, %r27
sllx %r27, 8, %r27
or %r27, %r28, %r28
#endif
#else
! Add CID IF tid matches
ifelse(7,mask2tid(0x2),`ta T_CHANGE_HPRIV;sethi %hi(0x3800), %r27;andn %r28, %r27, %r28;ldxa [%g0]0x63, %r27;sllx %r27, 8, %r27;or %r27, %r28, %r28 ')
#endif
sethi %hi(0x30000), %r27
andn %r28, %r27, %r28
ta T_CHANGE_HPRIV
ifelse(7,mask2tid(0x2),`.align 16')
stxa %r28, [%g0] 0x73
intvec_2_39:
.word 0x39400001 ! 93: FBPUGE fbuge,a,pn %fcc0, <label_0x1>
.word 0x81460000 ! 97: RD_STICK_REG stbar
cmp_2_44:
nop
nop
ta T_CHANGE_HPRIV
rd %asi, %r12
wr %r0, 0x41, %asi
set sync_thr_counter4, %r23
#ifndef SPC
ldxa [%g0]0x63, %r8
and %r8, 0x38, %r8 ! Core ID
#ifndef PORTABLE_CORE
add %r8, %r23, %r23
#endif
mov 0xff, %r9
#if (!defined PORTABLE_CORE || MAX_THREADS == 8)
xor %r9, 0x2, %r9 ! My core mask
#else
xor %r9, 0x2, %r9
#endif
sllx %r9, %r8, %r9 ! My core mask
#else
mov 0, %r8
mov 0xff, %r9
xor %r9, 0x2, %r9 ! My core mask
#endif
mov 0x2, %r10
cmp_startwait2_44:
cas [%r23],%g0,%r10 !lock
brz,a %r10, continue_cmp_2_44
ldxa [0x50]%asi, %r13 !Running_rw
ld [%r23], %r10
cmp_wait2_44:
brnz,a %r10, cmp_wait2_44
ld [%r23], %r10
ba cmp_startwait2_44
mov 0x2, %r10
continue_cmp_2_44:
ldxa [0x58]%asi, %r14 !Running_status
xnor %r14, %r13, %r14 !Bits equal
#ifndef PORTABLE_CORE
brz,a %r8, cmp_multi_core_2_44
#endif
mov 0xe9, %r17
#ifndef PORTABLE_CORE
best_set_reg(0x72cb655a3242c570, %r16, %r17)
#else
sllx %r17, %r8, %r17
#endif
cmp_multi_core_2_44:
and %r14, %r17, %r14 !Apply set/clear mask to bits equal
and %r14, %r9, %r14 !Apply core-mask
stxa %r14, [0x68]%asi
st %g0, [%r23] !clear lock
wr %g0, %r12, %asi
.word 0xa1a00160 ! 101: FABSq dis not found
.word 0x3c800001 ! 105: BPOS bpos,a <label_0x1>
nop
nop
set 0x90b0f94a, %r28 !TTID : 1 (mask2tid(0x2))
#if (defined PORTABLE_CORE || MAX_THREADS == 8)
sethi %hi(0x3800), %r27
andn %r28, %r27, %r28
#ifdef PORTABLE_CORE
! Add CID to vector
ta T_CHANGE_HPRIV
ldxa [%g0]0x63, %r27
sllx %r27, 8, %r27
or %r27, %r28, %r28
#endif
#else
! Add CID IF tid matches
ifelse(1,mask2tid(0x2),`ta T_CHANGE_HPRIV;sethi %hi(0x3800), %r27;andn %r28, %r27, %r28;ldxa [%g0]0x63, %r27;sllx %r27, 8, %r27;or %r27, %r28, %r28 ')
#endif
sethi %hi(0x30000), %r27
andn %r28, %r27, %r28
ta T_CHANGE_HPRIV
ifelse(1,mask2tid(0x2),`.align 16')
stxa %r28, [%g0] 0x73
intvec_2_47:
.word 0x39400002 ! 109: FBPUGE fbuge,a,pn %fcc0, <label_0x2>
.word 0xd8800b00 ! 113: LDUWA_R lduwa [%r0, %r0] 0x58, %r12
nop
nop
mov 0x0, %r11
splash_cmpr_2_52:
sllx %r11, 63, %r11
not %r11, %r11
rd %tick, %r10
#if (defined SPC || defined CMP1)
add %r10, 0x150, %r10
#else
add %r10, 0xc00, %r10
#endif
and %r10, %r11, %r10
rd %tick, %r10
#if (defined SPC || defined CMP1)
add %r10, 0x250, %r10
#else
add %r10, 0x380, %r10
#endif
and %r10, %r11, %r10
.word 0xaf80000a ! 1: WR_TICK_CMPR_REG_R wr %r0, %r10, %-
.word 0x81b01021 ! 117: SIAM siam 1
.word 0x8d802000 ! 121: WRFPRS_I wr %r0, 0x0000, %fprs
.word 0x98dac014 ! 125: SMULcc_R smulcc %r11, %r20, %r12
brcommon2_2_54:
nop
nop
setx common_target, %r12, %r27
ba,a .+12
.word 0x9ba149d0 ! 1: FDIVd fdivd %f36, %f16, %f44
ba,a .+8
jmpl %r27-0, %r27
.word 0x20800002 ! 129: BN bn,a <label_0x2>
memptr_2_56:
set 0x60540000, %r31
.word 0x858170c4 ! 133: WRCCR_I wr %r5, 0x10c4, %ccr
splash_lsu_2_58:
nop
nop
ta T_CHANGE_HPRIV
set 0xd8b4f52f, %r2
mov 0x1, %r1
sllx %r1, 32, %r1
or %r1, %r2, %r2
stxa %r2, [%r0] ASI_LSU_CONTROL
ta T_CHANGE_NONHPRIV
.word 0x3d400001 ! 137: FBPULE fbule,a,pn %fcc0, <label_0x1>
.word 0xda77e0d1 ! 141: STX_I stx %r13, [%r31 + 0x00d1]
jmptr_2_65:
nop
nop
best_set_reg(0xe1a00000, %r20, %r27)
.word 0xb7c6c000 ! 145: JMPL_R jmpl %r27 + %r0, %r27
.word 0x91d020b5 ! 149: Tcc_I ta icc_or_xcc, %r0 + 181
.word 0xda800b40 ! 153: LDUWA_R lduwa [%r0, %r0] 0x5a, %r13
fpinit_2_70:
nop
setx fp_data_quads, %r19, %r20
ldd [%r20], %f0
ldd [%r20+8], %f4
ld [%r20+16], %fsr
ld [%r20+24], %r19
wr %r19, %g0, %gsr
.word 0x8db00484 ! 157: FCMPLE32 fcmple32 %d0, %d4, %r6
.word 0xe1bfdb20 ! 161: STDFA_R stda %f16, [%r0, %r31]
cmp_2_75:
nop
nop
ta T_CHANGE_HPRIV
rd %asi, %r12
wr %r0, 0x41, %asi
set sync_thr_counter4, %r23
#ifndef SPC
ldxa [%g0]0x63, %r8
and %r8, 0x38, %r8 ! Core ID
#ifndef PORTABLE_CORE
add %r8, %r23, %r23
#endif
mov 0xff, %r9
#if (!defined PORTABLE_CORE || MAX_THREADS == 8)
xor %r9, 0x2, %r9 ! My core mask
#else
xor %r9, 0x2, %r9
#endif
sllx %r9, %r8, %r9 ! My core mask
#else
mov 0, %r8
mov 0xff, %r9
xor %r9, 0x2, %r9 ! My core mask
#endif
mov 0x2, %r10
cmp_startwait2_75:
cas [%r23],%g0,%r10 !lock
brz,a %r10, continue_cmp_2_75
ldxa [0x50]%asi, %r13 !Running_rw
ld [%r23], %r10
cmp_wait2_75:
brnz,a %r10, cmp_wait2_75
ld [%r23], %r10
ba cmp_startwait2_75
mov 0x2, %r10
continue_cmp_2_75:
ldxa [0x58]%asi, %r14 !Running_status
xnor %r14, %r13, %r14 !Bits equal
#ifndef PORTABLE_CORE
brz,a %r8, cmp_multi_core_2_75
#endif
mov 0x8d, %r17
#ifndef PORTABLE_CORE
best_set_reg(0xc6e89c505b4bc078, %r16, %r17)
#else
sllx %r17, %r8, %r17
#endif
cmp_multi_core_2_75:
and %r14, %r17, %r14 !Apply set/clear mask to bits equal
and %r14, %r9, %r14 !Apply core-mask
stxa %r14, [0x60]%asi
st %g0, [%r23] !clear lock
wr %g0, %r12, %asi
wrhpr %g0, 0x2c2, %hpstate ! ta T_CHANGE_NONHPRIV
.word 0xda9fc2c0 ! 165: LDDA_R ldda [%r31, %r0] 0x16, %r13
br_badelay3_2_78:
.word 0xa3a289d0 ! 1: FDIVd fdivd %f10, %f16, %f48
.word 0xb94f65e2 ! Random illegal ?
.word 0xe514c013 ! 1: LDQF_R - [%r19, %r19], %f18
.word 0x91a4c830 ! 169: FADDs fadds %f19, %f16, %f8
.word 0xd2c7c380 ! 173: LDSWA_R ldswa [%r31, %r0] 0x1c, %r9
nop
nop
ta T_CHANGE_HPRIV ! macro
donret_2_82:
rd %pc, %r12
mov HIGHVA_HIGHNUM, %r10
sllx %r10, 32, %r10
or %r12, %r10, %r12
add %r12, (donretarg_2_82-donret_2_82+4), %r12
add %r12, 0x4, %r11 ! seq tnpc
wrpr %g0, 0x1, %tl
wrpr %g0, %r12, %tpc
wrpr %g0, %r11, %tnpc
set (0x00d4e600 | (0x82 << 24)), %r13
and %r12, 0xfff, %r14
sllx %r14, 32, %r14
or %r13, %r14, %r20
wrpr %r20, %g0, %tstate
wrhpr %g0, 0x158d, %htstate
wrhpr %g0, 0x983, %hpstate ! rand=1 (2)
ldx [%r12+%r0], %g1
retry
donretarg_2_82:
.word 0xa9a509d0 ! 177: FDIVd fdivd %f20, %f16, %f20
nop
nop
set 0xf3e0ce91, %r28 !TTID : 6 (mask2tid(0x2))
#if (defined PORTABLE_CORE || MAX_THREADS == 8)
sethi %hi(0x3800), %r27
andn %r28, %r27, %r28
#ifdef PORTABLE_CORE
! Add CID to vector
ta T_CHANGE_HPRIV
ldxa [%g0]0x63, %r27
sllx %r27, 8, %r27
or %r27, %r28, %r28
#endif
#else
! Add CID IF tid matches
ifelse(6,mask2tid(0x2),`ta T_CHANGE_HPRIV;sethi %hi(0x3800), %r27;andn %r28, %r27, %r28;ldxa [%g0]0x63, %r27;sllx %r27, 8, %r27;or %r27, %r28, %r28 ')
#endif
sethi %hi(0x30000), %r27
andn %r28, %r27, %r28
ta T_CHANGE_HPRIV
ifelse(6,mask2tid(0x2),`.align 16')
stxa %r28, [%g0] 0x73
intvec_2_83:
.word 0x19400001 ! 181: FBPUGE fbuge
brcommon3_2_86:
nop
nop
setx common_target, %r12, %r27
lduw [%r27], %r12 ! Load common dest into dcache ..
stuw %r12, [%r27] ! Load common dest into dcache ..
ba,a .+12
.word 0xd86fe040 ! 1: LDSTUB_I ldstub %r12, [%r31 + 0x0040]
ba,a .+8
jmpl %r27+0, %r27
stxa %r16, [%r0] ASI_LSU_CONTROL
.word 0x95aac824 ! 185: FMOVGE fmovs %fcc1, %f4, %f10
cancelint_2_89:
rdhpr %halt, %r12
.word 0x85880000 ! 189: ALLCLEAN <illegal instruction>
.word 0xe927e174 ! 193: STF_I st %f20, [0x0174, %r31]
splash_lsu_2_94:
nop
nop
ta T_CHANGE_HPRIV
set 0x78bcb2c1, %r2
mov 0x6, %r1
sllx %r1, 32, %r1
or %r1, %r2, %r2
.word 0x26800001 ! 1: BL bl,a <label_0x1>
stxa %r2, [%r0] ASI_LSU_CONTROL
ta T_CHANGE_NONHPRIV
.word 0x3d400001 ! 197: FBPULE fbule,a,pn %fcc0, <label_0x1>
.word 0xa1902005 ! 201: WRPR_GL_I wrpr %r0, 0x0005, %-
br_badelay3_2_98:
.word 0x34800002 ! 1: BG bg,a <label_0x2>
.word 0x8d4926bb ! Random illegal ?
.word 0x93a00551 ! 1: FSQRTd fsqrt
.word 0xa5a1482c ! 205: FADDs fadds %f5, %f12, %f18
.word 0x8f902001 ! 1: WRPR_TL_I wrpr %r0, 0x0001, %tl
reduce_priv_lvl_2_99:
ta T_CHANGE_NONPRIV ! macro
splash_lsu_2_102:
nop
nop
ta T_CHANGE_HPRIV
set 0x5d83f7e8, %r2
mov 0x3, %r1
sllx %r1, 32, %r1
or %r1, %r2, %r2
stxa %r2, [%r0] ASI_LSU_CONTROL
ta T_CHANGE_NONHPRIV
.word 0x3d400002 ! 213: FBPULE fbule,a,pn %fcc0, <label_0x2>
.word 0x8d903f07 ! 217: WRPR_PSTATE_I wrpr %r0, 0x1f07, %pstate
cmp_2_108:
nop
nop
ta T_CHANGE_HPRIV
rd %asi, %r12
wr %r0, 0x41, %asi
set sync_thr_counter4, %r23
#ifndef SPC
ldxa [%g0]0x63, %r8
and %r8, 0x38, %r8 ! Core ID
#ifndef PORTABLE_CORE
add %r8, %r23, %r23
#endif
mov 0xff, %r9
#if (!defined PORTABLE_CORE || MAX_THREADS == 8)
xor %r9, 0x2, %r9 ! My core mask
#else
xor %r9, 0x2, %r9
#endif
sllx %r9, %r8, %r9 ! My core mask
#else
mov 0, %r8
mov 0xff, %r9
xor %r9, 0x2, %r9 ! My core mask
#endif
mov 0x2, %r10
cmp_startwait2_108:
cas [%r23],%g0,%r10 !lock
brz,a %r10, continue_cmp_2_108
ldxa [0x50]%asi, %r13 !Running_rw
ld [%r23], %r10
cmp_wait2_108:
brnz,a %r10, cmp_wait2_108
ld [%r23], %r10
ba cmp_startwait2_108
mov 0x2, %r10
continue_cmp_2_108:
ldxa [0x58]%asi, %r14 !Running_status
xnor %r14, %r13, %r14 !Bits equal
#ifndef PORTABLE_CORE
brz,a %r8, cmp_multi_core_2_108
#endif
mov 0xf, %r17
#ifndef PORTABLE_CORE
best_set_reg(0xb6499ffb6ba34829, %r16, %r17)
#else
sllx %r17, %r8, %r17
#endif
cmp_multi_core_2_108:
and %r14, %r17, %r14 !Apply set/clear mask to bits equal
and %r14, %r9, %r14 !Apply core-mask
stxa %r14, [0x68]%asi
st %g0, [%r23] !clear lock
wr %g0, %r12, %asi
wrhpr %g0, 0x148, %hpstate ! ta T_CHANGE_NONHPRIV
.word 0xe4bfc2e0 ! 221: STDA_R stda %r18, [%r31 + %r0] 0x17
.word 0xc19fc3e0 ! 225: LDDFA_R ldda [%r31, %r0], %f0
#if (defined SPC || defined CMP1)
!$EV trig_pc_d(1, expr(@VA(.MAIN.intvec_2_112) , 16, 16)) -> intp(2,0,16,*,976,*,3e,1)
!$EV trig_pc_d(1, expr((@VA(.MAIN.intvec_2_112)&0xffffffff) , 16, 16)) -> intp(2,0,3,*,688,*,3e,1)
#else
nop
nop
set 0x300029fe, %r28 !TTID : 1 (mask2tid(0x2))
#if (defined PORTABLE_CORE || MAX_THREADS == 8)
sethi %hi(0x3800), %r27
andn %r28, %r27, %r28
#ifdef PORTABLE_CORE
! Add CID to vector
ta T_CHANGE_HPRIV
ldxa [%g0]0x63, %r27
sllx %r27, 8, %r27
or %r27, %r28, %r28
#endif
#else
! Add CID IF tid matches
ifelse(1,mask2tid(0x2),`ta T_CHANGE_HPRIV;sethi %hi(0x3800), %r27;andn %r28, %r27, %r28;ldxa [%g0]0x63, %r27;sllx %r27, 8, %r27;or %r27, %r28, %r28 ')
#endif
ifelse(1,mask2tid(0x2),`.align 16')
stxa %r28, [%g0] 0x73
#endif
intvec_2_112:
#if (defined SPC || defined CMP1)
wrhpr %g0, 0x0, %halt ! HALT
#else
ifelse(1,mask2tid(0x2),`wrhpr %g0, 0x0, %halt ! HALT')
#endif
.word 0xa5a489cb ! 229: FDIVd fdivd %f18, %f42, %f18
jmptr_2_115:
nop
nop
best_set_reg(0xe0a00000, %r20, %r27)
.word 0xb7c6c000 ! 233: JMPL_R jmpl %r27 + %r0, %r27
.word 0xd097c3c0 ! 237: LDUHA_R lduha [%r31, %r0] 0x1e, %r8
intveclr_2_120:
nop
nop
ta T_CHANGE_HPRIV
setx 0xbd5632dbae40a759, %r1, %r28
stxa %r28, [%g0] 0x72
wrhpr %g0, 0xe01, %hpstate ! ta T_CHANGE_NONHPRIV
.word 0x25400001 ! 241: FBPLG fblg,a,pn %fcc0, <label_0x1>
splash_lsu_2_122:
nop
nop
ta T_CHANGE_HPRIV
set 0xa4b21818, %r2
mov 0x4, %r1
sllx %r1, 32, %r1
or %r1, %r2, %r2
.word 0x38800001 ! 1: BGU bgu,a <label_0x1>
stxa %r2, [%r0] ASI_LSU_CONTROL
ta T_CHANGE_NONHPRIV
.word 0x1d400001 ! 245: FBPULE fbule
.word 0xd137c000 ! 249: STQF_R - %f8, [%r0, %r31]
splash_lsu_2_125:
nop
nop
ta T_CHANGE_HPRIV
set 0x8ceea0d2, %r2
mov 0x3, %r1
sllx %r1, 32, %r1
or %r1, %r2, %r2
stxa %r2, [%r0] ASI_LSU_CONTROL
.word 0x3d400001 ! 253: FBPULE fbule,a,pn %fcc0, <label_0x1>
splash_tick_2_129:
nop
nop
ta T_CHANGE_HPRIV
best_set_reg(0xc90495cacafa5618, %r16, %r17)
.word 0x8980000a ! 257: WRTICK_R wr %r0, %r10, %tick
.word 0xa1902004 ! 261: WRPR_GL_I wrpr %r0, 0x0004, %-
jmptr_2_133:
nop
nop
best_set_reg(0xe1a00000, %r20, %r27)
.word 0xb7c6c000 ! 265: JMPL_R jmpl %r27 + %r0, %r27
nop
nop
mov 0x1, %r11
splash_cmpr_2_134:
sllx %r11, 63, %r11
not %r11, %r11
rd %tick, %r10
#if (defined SPC || defined CMP1)
add %r10, 0x200, %r10
#else
add %r10, 0x900, %r10
#endif
and %r10, %r11, %r10
ta T_CHANGE_PRIV
rd %tick, %r10
#if (defined SPC || defined CMP1)
add %r10, 0x200, %r10
#else
add %r10, 0x550, %r10
#endif
and %r10, %r11, %r10
.word 0xb380000a ! 1: WR_STICK_CMPR_REG_R wr %r0, %r10, %-
#if (defined SPC || defined CMP1)
!$EV trig_pc_d(1, expr(@VA(.MAIN.splash_cmpr_2_134)+8 , 16, 16)) -> intp(3,0,9,*,984,*,1a,1)
!$EV trig_pc_d(1, expr((@VA(.MAIN.splash_cmpr_2_134)&0xffffffff)+8 , 16, 16)) -> intp(7,0,1,*,952,*,1a,1)
#endif
wrhpr %g0, 0x0, %halt ! HALT
.word 0x81b01021 ! 269: SIAM siam 1
jmptr_2_135:
nop
nop
best_set_reg(0xe0a00000, %r20, %r27)
.word 0xb7c6c000 ! 273: JMPL_R jmpl %r27 + %r0, %r27
intveclr_2_136:
nop
nop
ta T_CHANGE_HPRIV
setx 0x519213055230f4cd, %r1, %r28
stxa %r28, [%g0] 0x72
.word 0x25400001 ! 277: FBPLG fblg,a,pn %fcc0, <label_0x1>
.word 0xd137e156 ! 281: STQF_I - %f8, [0x0156, %r31]
splash_hpstate_2_141:
.word 0x3e800001 ! 1: BVC bvc,a <label_0x1>
.word 0x81982def ! 285: WRHPR_HPSTATE_I wrhpr %r0, 0x0def, %hpstate
intveclr_2_145:
nop
nop
ta T_CHANGE_HPRIV
setx 0x08a12dc80ffdc3cd, %r1, %r28
stxa %r28, [%g0] 0x72
wrhpr %g0, 0x2da, %hpstate ! ta T_CHANGE_NONHPRIV
.word 0x05400001 ! 289: FBPLG fblg
brcommon1_2_148:
nop
nop
setx common_target, %r12, %r27
lduw [%r27-0], %r12 ! Load common dest into dcache ..
stuw %r12, [%r27-4] ! Load common dest into dcache ..
ba,a .+12
.word 0x91a7c9c0 ! 1: FDIVd fdivd %f62, %f0, %f8
ba,a .+8
jmpl %r27-0, %r27
.word 0xa9b14491 ! 293: FCMPLE32 fcmple32 %d36, %d48, %r20
.word 0xd8dfdd40 ! 297: LDXA_R ldxa [%r31, %r0] 0xea, %r12
cmp_2_153:
nop
nop
ta T_CHANGE_HPRIV
rd %asi, %r12
wr %r0, 0x41, %asi
set sync_thr_counter4, %r23
#ifndef SPC
ldxa [%g0]0x63, %r8
and %r8, 0x38, %r8 ! Core ID
#ifndef PORTABLE_CORE
add %r8, %r23, %r23
#endif
mov 0xff, %r9
#if (!defined PORTABLE_CORE || MAX_THREADS == 8)
xor %r9, 0x2, %r9 ! My core mask
#else
xor %r9, 0x2, %r9
#endif
sllx %r9, %r8, %r9 ! My core mask
#else
mov 0, %r8
mov 0xff, %r9
xor %r9, 0x2, %r9 ! My core mask
#endif
mov 0x2, %r10
cmp_startwait2_153:
cas [%r23],%g0,%r10 !lock
brz,a %r10, continue_cmp_2_153
ldxa [0x50]%asi, %r13 !Running_rw
ld [%r23], %r10
cmp_wait2_153:
brnz,a %r10, cmp_wait2_153
ld [%r23], %r10
ba cmp_startwait2_153
mov 0x2, %r10
continue_cmp_2_153:
ldxa [0x58]%asi, %r14 !Running_status
xnor %r14, %r13, %r14 !Bits equal
#ifndef PORTABLE_CORE
brz,a %r8, cmp_multi_core_2_153
#endif
mov 0xae, %r17
#ifndef PORTABLE_CORE
best_set_reg(0x37fbd2a0e2cee19f, %r16, %r17)
#else
sllx %r17, %r8, %r17
#endif
cmp_multi_core_2_153:
and %r14, %r17, %r14 !Apply set/clear mask to bits equal
and %r14, %r9, %r14 !Apply core-mask
stxa %r14, [0x60]%asi
st %g0, [%r23] !clear lock
wr %g0, %r12, %asi
.word 0x9191c012 ! 301: WRPR_PIL_R wrpr %r7, %r18, %pil
demap_2_156:
nop
mov 0x80, %g3
ta T_CHANGE_HPRIV
.word 0x34800001 ! 1: BG bg,a <label_0x1>
stxa %g3, [%g3] 0x57
.word 0xc0bfc2c0 ! 1: STDA_R stda %r0, [%r31 + %r0] 0x16
stxa %g3, [%g3] 0x5f
.word 0xe09fdc00 ! 1: LDDA_R ldda [%r31, %r0] 0xe0, %r16
stxa %g3, [%g3] 0x5f
.word 0xe1bfde00 ! 1: STDFA_R stda %f16, [%r0, %r31]
stxa %g3, [%g3] 0x57
.word 0xc19fc2c0 ! 1: LDDFA_R ldda [%r31, %r0], %f0
stxa %g3, [%g3] 0x57
.word 0xe0bfde20 ! 1: STDA_R stda %r16, [%r31 + %r0] 0xf1
.word 0xc0bfdc00 ! 1: STDA_R stda %r0, [%r31 + %r0] 0xe0
.word 0xe19fda60 ! 1: LDDFA_R ldda [%r31, %r0], %f16
wrhpr %g0, 0xb11, %hpstate ! ta T_CHANGE_NONHPRIV
.word 0xd81fe1f5 ! 305: LDD_I ldd [%r31 + 0x01f5], %r12
cmp_2_159:
nop
nop
ta T_CHANGE_HPRIV
rd %asi, %r12
wr %r0, 0x41, %asi
set sync_thr_counter4, %r23
#ifndef SPC
ldxa [%g0]0x63, %r8
and %r8, 0x38, %r8 ! Core ID
#ifndef PORTABLE_CORE
add %r8, %r23, %r23
#endif
mov 0xff, %r9
#if (!defined PORTABLE_CORE || MAX_THREADS == 8)
xor %r9, 0x2, %r9 ! My core mask
#else
xor %r9, 0x2, %r9
#endif
sllx %r9, %r8, %r9 ! My core mask
#else
mov 0, %r8
mov 0xff, %r9
xor %r9, 0x2, %r9 ! My core mask
#endif
mov 0x2, %r10
cmp_startwait2_159:
cas [%r23],%g0,%r10 !lock
brz,a %r10, continue_cmp_2_159
ldxa [0x50]%asi, %r13 !Running_rw
ld [%r23], %r10
cmp_wait2_159:
brnz,a %r10, cmp_wait2_159
ld [%r23], %r10
ba cmp_startwait2_159
mov 0x2, %r10
continue_cmp_2_159:
ldxa [0x58]%asi, %r14 !Running_status
xnor %r14, %r13, %r14 !Bits equal
#ifndef PORTABLE_CORE
brz,a %r8, cmp_multi_core_2_159
#endif
mov 0xa9, %r17
#ifndef PORTABLE_CORE
best_set_reg(0x5c633e2ad06c2157, %r16, %r17)
#else
sllx %r17, %r8, %r17
#endif
cmp_multi_core_2_159:
and %r14, %r17, %r14 !Apply set/clear mask to bits equal
and %r14, %r9, %r14 !Apply core-mask
stxa %r14, [0x60]%asi
st %g0, [%r23] !clear lock
wr %g0, %r12, %asi
.word 0x91950003 ! 309: WRPR_PIL_R wrpr %r20, %r3, %pil
.word 0x93a4c9d4 ! 313: FDIVd fdivd %f50, %f20, %f40
splash_lsu_2_163:
nop
nop
ta T_CHANGE_HPRIV
set 0x36fb7026, %r2
mov 0x5, %r1
sllx %r1, 32, %r1
or %r1, %r2, %r2
.word 0x39400001 ! 1: FBPUGE fbuge,a,pn %fcc0, <label_0x1>
stxa %r2, [%r0] ASI_LSU_CONTROL
ta T_CHANGE_NONHPRIV
.word 0x1d400001 ! 317: FBPULE fbule
splash_hpstate_2_166:
.word 0x819836cf ! 321: WRHPR_HPSTATE_I wrhpr %r0, 0x16cf, %hpstate
nop
nop
ta T_CHANGE_HPRIV
mov 0x1, %r11
splash_cmpr_2_169:
sllx %r11, 63, %r11
not %r11, %r11
rd %tick, %r10
#if (defined SPC || defined CMP1)
add %r10, 0x100, %r10
#else
add %r10, 0xc00, %r10
#endif
and %r10, %r11, %r10
wrhpr %r10, %g0, %hsys_tick_cmpr
wrhpr %g0, 0x0, %halt ! HALT
ta T_CHANGE_PRIV
rd %tick, %r10
#if (defined SPC || defined CMP1)
add %r10, 0x150, %r10
#else
add %r10, 0xc00, %r10
#endif
and %r10, %r11, %r10
.word 0xaf80000a ! 1: WR_TICK_CMPR_REG_R wr %r0, %r10, %-
#if (defined SPC || defined CMP1)
!$EV trig_pc_d(1, expr(@VA(.MAIN.splash_cmpr_2_169)+8 , 16, 16)) -> intp(6,0,22,*,688,*,7a,1)
!$EV trig_pc_d(1, expr((@VA(.MAIN.splash_cmpr_2_169)&0xffffffff)+8 , 16, 16)) -> intp(3,0,3,*,928,*,7a,1)
#endif
wrhpr %g0, 0x0, %halt ! HALT
.word 0x819833c3 ! 1: WRHPR_HPSTATE_I wrhpr %r0, 0x13c3, %hpstate
.word 0x81b01021 ! 325: SIAM siam 1
intveclr_2_171:
nop
nop
ta T_CHANGE_HPRIV
setx 0x02c249d5b458e83b, %r1, %r28
stxa %r28, [%g0] 0x72
wrhpr %g0, 0x459, %hpstate ! ta T_CHANGE_NONHPRIV
.word 0x05400002 ! 329: FBPLG fblg
cmp_2_173:
nop
nop
ta T_CHANGE_HPRIV
rd %asi, %r12
wr %r0, 0x41, %asi
set sync_thr_counter4, %r23
#ifndef SPC
ldxa [%g0]0x63, %r8
and %r8, 0x38, %r8 ! Core ID
#ifndef PORTABLE_CORE
add %r8, %r23, %r23
#endif
mov 0xff, %r9
#if (!defined PORTABLE_CORE || MAX_THREADS == 8)
xor %r9, 0x2, %r9 ! My core mask
#else
xor %r9, 0x2, %r9
#endif
sllx %r9, %r8, %r9 ! My core mask
#else
mov 0, %r8
mov 0xff, %r9
xor %r9, 0x2, %r9 ! My core mask
#endif
mov 0x2, %r10
cmp_startwait2_173:
cas [%r23],%g0,%r10 !lock
brz,a %r10, continue_cmp_2_173
ldxa [0x50]%asi, %r13 !Running_rw
ld [%r23], %r10
cmp_wait2_173:
brnz,a %r10, cmp_wait2_173
ld [%r23], %r10
ba cmp_startwait2_173
mov 0x2, %r10
continue_cmp_2_173:
ldxa [0x58]%asi, %r14 !Running_status
xnor %r14, %r13, %r14 !Bits equal
#ifndef PORTABLE_CORE
brz,a %r8, cmp_multi_core_2_173
#endif
mov 0xe6, %r17
#ifndef PORTABLE_CORE
best_set_reg(0x1830d92292e7f52a, %r16, %r17)
#else
sllx %r17, %r8, %r17
#endif
cmp_multi_core_2_173:
and %r14, %r17, %r14 !Apply set/clear mask to bits equal
and %r14, %r9, %r14 !Apply core-mask
stxa %r14, [0x60]%asi
st %g0, [%r23] !clear lock
wr %g0, %r12, %asi
wrhpr %g0, 0xb10, %hpstate ! ta T_CHANGE_NONHPRIV
.word 0x91944003 ! 333: WRPR_PIL_R wrpr %r17, %r3, %pil
.word 0xd3e7c3c0 ! 337: CASA_I casa [%r31] 0x1e, %r0, %r9
demap_2_179:
nop
mov 0x80, %g3
ta T_CHANGE_HPRIV
.word 0x24800001 ! 1: BLE ble,a <label_0x1>
stxa %g3, [%g3] 0x5f
.word 0xc09fc2c0 ! 1: LDDA_R ldda [%r31, %r0] 0x16, %r0
.word 0xc09fc2c0 ! 1: LDDA_R ldda [%r31, %r0] 0x16, %r0
.word 0xe09fdc40 ! 1: LDDA_R ldda [%r31, %r0] 0xe2, %r16
stxa %g3, [%g3] 0x57
.word 0xc09fda60 ! 1: LDDA_R ldda [%r31, %r0] 0xd3, %r0
.word 0xc1bfdb20 ! 1: STDFA_R stda %f0, [%r0, %r31]
stxa %g3, [%g3] 0x5f
.word 0xc0bfdb40 ! 1: STDA_R stda %r0, [%r31 + %r0] 0xda
.word 0xc09fc2c0 ! 1: LDDA_R ldda [%r31, %r0] 0x16, %r0
stxa %g3, [%g3] 0x57
stxa %g3, [%g3] 0x57
wrhpr %g0, 0x29b, %hpstate ! ta T_CHANGE_NONHPRIV
.word 0xd21fe0d8 ! 341: LDD_I ldd [%r31 + 0x00d8], %r9
.word 0xa1902003 ! 345: WRPR_GL_I wrpr %r0, 0x0003, %-
nop
nop
mov 0x1, %r11
splash_cmpr_2_181:
sllx %r11, 63, %r11
not %r11, %r11
rd %tick, %r10
#if (defined SPC || defined CMP1)
add %r10, 0x300, %r10
#else
add %r10, 0x550, %r10
#endif
and %r10, %r11, %r10
rd %tick, %r10
#if (defined SPC || defined CMP1)
add %r10, 0x150, %r10
#else
add %r10, 0x380, %r10
#endif
and %r10, %r11, %r10
.word 0xb380000a ! 1: WR_STICK_CMPR_REG_R wr %r0, %r10, %-
#if (defined SPC || defined CMP1)
!$EV trig_pc_d(1, expr(@VA(.MAIN.splash_cmpr_2_181)+8 , 16, 16)) -> intp(6,0,10,*,648,*,43,1)
!$EV trig_pc_d(1, expr((@VA(.MAIN.splash_cmpr_2_181)&0xffffffff)+8 , 16, 16)) -> intp(7,0,21,*,672,*,43,1)
#endif
wrhpr %g0, 0x0, %halt ! HALT
.word 0x81b01021 ! 349: SIAM siam 1
nop
nop
set 0x12a0103b, %r28 !TTID : 0 (mask2tid(0x2))
#if (defined PORTABLE_CORE || MAX_THREADS == 8)
sethi %hi(0x3800), %r27
andn %r28, %r27, %r28
#ifdef PORTABLE_CORE
! Add CID to vector
ta T_CHANGE_HPRIV
ldxa [%g0]0x63, %r27
sllx %r27, 8, %r27
or %r27, %r28, %r28
#endif
#else
! Add CID IF tid matches
ifelse(0,mask2tid(0x2),`ta T_CHANGE_HPRIV;sethi %hi(0x3800), %r27;andn %r28, %r27, %r28;ldxa [%g0]0x63, %r27;sllx %r27, 8, %r27;or %r27, %r28, %r28 ')
#endif
sethi %hi(0x30000), %r27
andn %r28, %r27, %r28
ta T_CHANGE_HPRIV
ifelse(0,mask2tid(0x2),`.align 16')
stxa %r28, [%g0] 0x73
intvec_2_183:
.word 0xa3a349d3 ! 353: FDIVd fdivd %f44, %f50, %f48
splash_tba_2_187:
nop
ta T_CHANGE_PRIV
setx 0x00000000003a0000, %r11, %r12
.word 0x8b90000c ! 357: WRPR_TBA_R wrpr %r0, %r12, %tba
.word 0x2a780001 ! 361: BPCS <illegal instruction>
splash_lsu_2_191:
nop
nop
ta T_CHANGE_HPRIV
set 0x9c085912, %r2
mov 0x2, %r1
sllx %r1, 32, %r1
or %r1, %r2, %r2
stxa %r2, [%r0] ASI_LSU_CONTROL
ta T_CHANGE_NONHPRIV
.word 0x3d400001 ! 365: FBPULE fbule,a,pn %fcc0, <label_0x1>
#if (defined SPC || defined CMP1)
!$EV trig_pc_d(1, expr(@VA(.MAIN.intvec_2_194) , 16, 16)) -> intp(7,0,9,*,912,*,2e,1)
!$EV trig_pc_d(1, expr((@VA(.MAIN.intvec_2_194)&0xffffffff) , 16, 16)) -> intp(4,0,0,*,728,*,2e,1)
#else
nop
nop
set 0xc2b09e21, %r28 !TTID : 6 (mask2tid(0x2))
#if (defined PORTABLE_CORE || MAX_THREADS == 8)
sethi %hi(0x3800), %r27
andn %r28, %r27, %r28
#ifdef PORTABLE_CORE
! Add CID to vector
ta T_CHANGE_HPRIV
ldxa [%g0]0x63, %r27
sllx %r27, 8, %r27
or %r27, %r28, %r28
#endif
#else
! Add CID IF tid matches
ifelse(6,mask2tid(0x2),`ta T_CHANGE_HPRIV;sethi %hi(0x3800), %r27;andn %r28, %r27, %r28;ldxa [%g0]0x63, %r27;sllx %r27, 8, %r27;or %r27, %r28, %r28 ')
#endif
ifelse(6,mask2tid(0x2),`.align 16')
stxa %r28, [%g0] 0x73
#endif
intvec_2_194:
.word 0x99a189d4 ! 369: FDIVd fdivd %f6, %f20, %f12
#if (defined SPC || defined CMP1)
!$EV trig_pc_d(1, expr(@VA(.MAIN.intvec_2_196) , 16, 16)) -> intp(3,0,22,*,1016,*,e7,1)
!$EV trig_pc_d(1, expr((@VA(.MAIN.intvec_2_196)&0xffffffff) , 16, 16)) -> intp(2,0,15,*,1000,*,e7,1)
#else
nop
nop
set 0x3e807994, %r28 !TTID : 1 (mask2tid(0x2))
#if (defined PORTABLE_CORE || MAX_THREADS == 8)
sethi %hi(0x3800), %r27
andn %r28, %r27, %r28
#ifdef PORTABLE_CORE
! Add CID to vector
ta T_CHANGE_HPRIV
ldxa [%g0]0x63, %r27
sllx %r27, 8, %r27
or %r27, %r28, %r28
#endif
#else
! Add CID IF tid matches
ifelse(1,mask2tid(0x2),`ta T_CHANGE_HPRIV;sethi %hi(0x3800), %r27;andn %r28, %r27, %r28;ldxa [%g0]0x63, %r27;sllx %r27, 8, %r27;or %r27, %r28, %r28 ')
#endif
ifelse(1,mask2tid(0x2),`.align 16')
stxa %r28, [%g0] 0x73
#endif
intvec_2_196:
.word 0x97b484c2 ! 373: FCMPNE32 fcmpne32 %d18, %d2, %r11
frzptr_2_199:
nop
nop
best_set_reg(0x3cb40000+0x1ffc, %r20, %r27)
jmpl %r27, %r27
.word 0xe19fda00 ! 377: LDDFA_R ldda [%r31, %r0], %f16
.word 0x32800002 ! 381: BNE bne,a <label_0x2>
#if (defined SPC || defined CMP1)
!$EV trig_pc_d(1, expr(@VA(.MAIN.intvec_2_204) , 16, 16)) -> intp(2,0,30,*,688,*,ae,1)
!$EV trig_pc_d(1, expr((@VA(.MAIN.intvec_2_204)&0xffffffff) , 16, 16)) -> intp(6,0,24,*,976,*,ae,1)
#else
nop
nop
set 0xa4207b60, %r28 !TTID : 3 (mask2tid(0x2))
#if (defined PORTABLE_CORE || MAX_THREADS == 8)
sethi %hi(0x3800), %r27
andn %r28, %r27, %r28
#ifdef PORTABLE_CORE
! Add CID to vector
ta T_CHANGE_HPRIV
ldxa [%g0]0x63, %r27
sllx %r27, 8, %r27
or %r27, %r28, %r28
#endif
#else
! Add CID IF tid matches
ifelse(3,mask2tid(0x2),`ta T_CHANGE_HPRIV;sethi %hi(0x3800), %r27;andn %r28, %r27, %r28;ldxa [%g0]0x63, %r27;sllx %r27, 8, %r27;or %r27, %r28, %r28 ')
#endif
ifelse(3,mask2tid(0x2),`.align 16')
stxa %r28, [%g0] 0x73
#endif
intvec_2_204:
#if (defined SPC || defined CMP1)
wrhpr %g0, 0x0, %halt ! HALT
#else
ifelse(3,mask2tid(0x2),`wrhpr %g0, 0x0, %halt ! HALT')
#endif
.word 0x91a189d1 ! 385: FDIVd fdivd %f6, %f48, %f8
.word 0x93a489c7 ! 389: FDIVd fdivd %f18, %f38, %f40
.word 0xd917c000 ! 393: LDQF_R - [%r31, %r0], %f12
demap_2_211:
nop
mov 0x80, %g3
ta T_CHANGE_HPRIV
stxa %g3, [%g3] 0x57
stxa %g3, [%g3] 0x5f
wrhpr %g0, 0xe18, %hpstate ! ta T_CHANGE_NONHPRIV
.word 0xd81fe009 ! 397: LDD_I ldd [%r31 + 0x0009], %r12
brcommon1_2_213:
nop
nop
setx common_target, %r12, %r27
lduw [%r27-0], %r12 ! Load common dest into dcache ..
stuw %r12, [%r27-4] ! Load common dest into dcache ..
ba,a .+12
.word 0x99a7c9c0 ! 1: FDIVd fdivd %f62, %f0, %f12
ba,a .+8
jmpl %r27-4, %r27
.word 0x20800001 ! 401: BN bn,a <label_0x1>
nop
nop
set 0x34a0e77a, %r28 !TTID : 7 (mask2tid(0x2))
#if (defined PORTABLE_CORE || MAX_THREADS == 8)
sethi %hi(0x3800), %r27
andn %r28, %r27, %r28
#ifdef PORTABLE_CORE
! Add CID to vector
ta T_CHANGE_HPRIV
ldxa [%g0]0x63, %r27
sllx %r27, 8, %r27
or %r27, %r28, %r28
#endif
#else
! Add CID IF tid matches
ifelse(7,mask2tid(0x2),`ta T_CHANGE_HPRIV;sethi %hi(0x3800), %r27;andn %r28, %r27, %r28;ldxa [%g0]0x63, %r27;sllx %r27, 8, %r27;or %r27, %r28, %r28 ')
#endif
sethi %hi(0x30000), %r27
andn %r28, %r27, %r28
ta T_CHANGE_HPRIV
ifelse(7,mask2tid(0x2),`.align 16')
stxa %r28, [%g0] 0x73
intvec_2_215:
.word 0xa9a509d0 ! 405: FDIVd fdivd %f20, %f16, %f20
cmp_2_218:
nop
nop
ta T_CHANGE_HPRIV
rd %asi, %r12
wr %r0, 0x41, %asi
set sync_thr_counter4, %r23
#ifndef SPC
ldxa [%g0]0x63, %r8
and %r8, 0x38, %r8 ! Core ID
#ifndef PORTABLE_CORE
add %r8, %r23, %r23
#endif
mov 0xff, %r9
#if (!defined PORTABLE_CORE || MAX_THREADS == 8)
xor %r9, 0x2, %r9 ! My core mask
#else
xor %r9, 0x2, %r9
#endif
sllx %r9, %r8, %r9 ! My core mask
#else
mov 0, %r8
mov 0xff, %r9
xor %r9, 0x2, %r9 ! My core mask
#endif
mov 0x2, %r10
cmp_startwait2_218:
cas [%r23],%g0,%r10 !lock
brz,a %r10, continue_cmp_2_218
ldxa [0x50]%asi, %r13 !Running_rw
ld [%r23], %r10
cmp_wait2_218:
brnz,a %r10, cmp_wait2_218
ld [%r23], %r10
ba cmp_startwait2_218
mov 0x2, %r10
continue_cmp_2_218:
ldxa [0x58]%asi, %r14 !Running_status
xnor %r14, %r13, %r14 !Bits equal
#ifndef PORTABLE_CORE
brz,a %r8, cmp_multi_core_2_218
#endif
mov 0xf, %r17
#ifndef PORTABLE_CORE
best_set_reg(0x442d8561f67e4c9f, %r16, %r17)
#else
sllx %r17, %r8, %r17
#endif
cmp_multi_core_2_218:
and %r14, %r17, %r14 !Apply set/clear mask to bits equal
and %r14, %r9, %r14 !Apply core-mask
stxa %r14, [0x68]%asi
st %g0, [%r23] !clear lock
wr %g0, %r12, %asi
wrhpr %g0, 0xc03, %hpstate ! ta T_CHANGE_NONHPRIV
.word 0xe81fe0a0 ! 409: LDD_I ldd [%r31 + 0x00a0], %r20
cmp_2_219:
nop
nop
ta T_CHANGE_HPRIV
rd %asi, %r12
wr %r0, 0x41, %asi
set sync_thr_counter4, %r23
#ifndef SPC
ldxa [%g0]0x63, %r8
and %r8, 0x38, %r8 ! Core ID
#ifndef PORTABLE_CORE
add %r8, %r23, %r23
#endif
mov 0xff, %r9
#if (!defined PORTABLE_CORE || MAX_THREADS == 8)
xor %r9, 0x2, %r9 ! My core mask
#else
xor %r9, 0x2, %r9
#endif
sllx %r9, %r8, %r9 ! My core mask
#else
mov 0, %r8
mov 0xff, %r9
xor %r9, 0x2, %r9 ! My core mask
#endif
mov 0x2, %r10
cmp_startwait2_219:
cas [%r23],%g0,%r10 !lock
brz,a %r10, continue_cmp_2_219
ldxa [0x50]%asi, %r13 !Running_rw
ld [%r23], %r10
cmp_wait2_219:
brnz,a %r10, cmp_wait2_219
ld [%r23], %r10
ba cmp_startwait2_219
mov 0x2, %r10
continue_cmp_2_219:
ldxa [0x58]%asi, %r14 !Running_status
xnor %r14, %r13, %r14 !Bits equal
#ifndef PORTABLE_CORE
brz,a %r8, cmp_multi_core_2_219
#endif
mov 0x1a, %r17
#ifndef PORTABLE_CORE
best_set_reg(0xe21f1e6eac0e5303, %r16, %r17)
#else
sllx %r17, %r8, %r17
#endif
cmp_multi_core_2_219:
and %r14, %r17, %r14 !Apply set/clear mask to bits equal
and %r14, %r9, %r14 !Apply core-mask
stxa %r14, [0x60]%asi
st %g0, [%r23] !clear lock
wr %g0, %r12, %asi
wrhpr %g0, 0xf0b, %hpstate ! ta T_CHANGE_NONHPRIV
.word 0x91934012 ! 413: WRPR_PIL_R wrpr %r13, %r18, %pil
.word 0xe19fe080 ! 417: LDDFA_I ldda [%r31, 0x0080], %f16
.word 0xe937c000 ! 421: STQF_R - %f20, [%r0, %r31]
.word 0x01400001 ! 1: FBPN fbn
br_longdelay5_2_224:
#if (defined SPC || defined CMP1)
!$EV trig_pc_d(1, expr((@VA(.MAIN.br_longdelay5_2_224)&0xffffffff) , 16, 16)) -> intp(mask2tid(0x2),0,0,*,640,*,ffffffffffffffff,1)
!$EV trig_pc_d(1, expr((@VA(.MAIN.br_longdelay5_2_224)) , 16, 16)) -> intp(mask2tid(0x2),0,0,*,952,*,ffffffffffffffff,1)
wrhpr %g0, 0x0, %halt ! HALT
#endif
.word 0xf16fe130 ! 425: PREFETCH_I prefetch [%r31 + 0x0130], #24
#if (defined SPC || defined CMP1)
!$EV trig_pc_d(1, expr(@VA(.MAIN.intvec_2_226) , 16, 16)) -> intp(4,0,22,*,952,*,8f,1)
!$EV trig_pc_d(1, expr((@VA(.MAIN.intvec_2_226)&0xffffffff) , 16, 16)) -> intp(7,0,26,*,720,*,8f,1)
#else
nop
nop
set 0x8ad093e4, %r28 !TTID : 3 (mask2tid(0x2))
#if (defined PORTABLE_CORE || MAX_THREADS == 8)
sethi %hi(0x3800), %r27
andn %r28, %r27, %r28
#ifdef PORTABLE_CORE
! Add CID to vector
ta T_CHANGE_HPRIV
ldxa [%g0]0x63, %r27
sllx %r27, 8, %r27
or %r27, %r28, %r28
#endif
#else
! Add CID IF tid matches
ifelse(3,mask2tid(0x2),`ta T_CHANGE_HPRIV;sethi %hi(0x3800), %r27;andn %r28, %r27, %r28;ldxa [%g0]0x63, %r27;sllx %r27, 8, %r27;or %r27, %r28, %r28 ')
#endif
ifelse(3,mask2tid(0x2),`.align 16')
stxa %r28, [%g0] 0x73
#endif
intvec_2_226:
.word 0x9ba309c1 ! 429: FDIVd fdivd %f12, %f32, %f44
jmptr_2_228:
nop
nop
best_set_reg(0xe1a00000, %r20, %r27)
.word 0xb7c6c000 ! 433: JMPL_R jmpl %r27 + %r0, %r27
demap_2_232:
nop
mov 0x80, %g3
ta T_CHANGE_HPRIV
stxa %g3, [%g3] 0x5f
.word 0xc1bfc3e0 ! 1: STDFA_R stda %f0, [%r0, %r31]
.word 0xe19fc3e0 ! 1: LDDFA_R ldda [%r31, %r0], %f16
stxa %g3, [%g3] 0x5f
.word 0xe09fc3e0 ! 1: LDDA_R ldda [%r31, %r0] 0x1f, %r16
.word 0xe09fc3e0 ! 1: LDDA_R ldda [%r31, %r0] 0x1f, %r16
stxa %g3, [%g3] 0x57
wrhpr %g0, 0x8c1, %hpstate ! ta T_CHANGE_NONHPRIV
.word 0xda1fe1f0 ! 437: LDD_I ldd [%r31 + 0x01f0], %r13
trapasi_2_235:
nop
mov 0x3c8, %r1 ! (VA for ASI 0x25)
.word 0xdad844a0 ! 441: LDXA_R ldxa [%r1, %r0] 0x25, %r13
.word 0xda57c000 ! 445: LDSH_R ldsh [%r31 + %r0], %r13
.word 0xda27e0fc ! 449: STW_I stw %r13, [%r31 + 0x00fc]
demap_2_240:
nop
mov 0x80, %g3
ta T_CHANGE_HPRIV
.word 0x35400002 ! 1: FBPUE fbue,a,pn %fcc0, <label_0x2>
stxa %g3, [%g3] 0x5f
.word 0xc0bfda00 ! 1: STDA_R stda %r0, [%r31 + %r0] 0xd0
.word 0xe1bfc3e0 ! 1: STDFA_R stda %f16, [%r0, %r31]
.word 0xc1bfdf00 ! 1: STDFA_R stda %f0, [%r0, %r31]
stxa %g3, [%g3] 0x57
.word 0xc09fda60 ! 1: LDDA_R ldda [%r31, %r0] 0xd3, %r0
wrhpr %g0, 0x712, %hpstate ! ta T_CHANGE_NONHPRIV
.word 0xda1fe0e8 ! 453: LDD_I ldd [%r31 + 0x00e8], %r13
cmp_2_243:
nop
nop
ta T_CHANGE_HPRIV
rd %asi, %r12
wr %r0, 0x41, %asi
set sync_thr_counter4, %r23
#ifndef SPC
ldxa [%g0]0x63, %r8
and %r8, 0x38, %r8 ! Core ID
#ifndef PORTABLE_CORE
add %r8, %r23, %r23
#endif
mov 0xff, %r9
#if (!defined PORTABLE_CORE || MAX_THREADS == 8)
xor %r9, 0x2, %r9 ! My core mask
#else
xor %r9, 0x2, %r9
#endif
sllx %r9, %r8, %r9 ! My core mask
#else
mov 0, %r8
mov 0xff, %r9
xor %r9, 0x2, %r9 ! My core mask
#endif
mov 0x2, %r10
cmp_startwait2_243:
cas [%r23],%g0,%r10 !lock
brz,a %r10, continue_cmp_2_243
ldxa [0x50]%asi, %r13 !Running_rw
ld [%r23], %r10
cmp_wait2_243:
brnz,a %r10, cmp_wait2_243
ld [%r23], %r10
ba cmp_startwait2_243
mov 0x2, %r10
continue_cmp_2_243:
ldxa [0x58]%asi, %r14 !Running_status
xnor %r14, %r13, %r14 !Bits equal
#ifndef PORTABLE_CORE
brz,a %r8, cmp_multi_core_2_243
#endif
mov 0x5, %r17
#ifndef PORTABLE_CORE
best_set_reg(0x4d0deb409a19d8b7, %r16, %r17)
#else
sllx %r17, %r8, %r17
#endif
cmp_multi_core_2_243:
and %r14, %r17, %r14 !Apply set/clear mask to bits equal
and %r14, %r9, %r14 !Apply core-mask
stxa %r14, [0x60]%asi
st %g0, [%r23] !clear lock
wr %g0, %r12, %asi
wrhpr %g0, 0x1c9, %hpstate ! ta T_CHANGE_NONHPRIV
.word 0xdb1fe1a0 ! 457: LDDF_I ldd [%r31, 0x01a0], %f13
.word 0xda3fe10e ! 461: STD_I std %r13, [%r31 + 0x010e]
cmp_2_250:
nop
nop
ta T_CHANGE_HPRIV
rd %asi, %r12
wr %r0, 0x41, %asi
set sync_thr_counter4, %r23
#ifndef SPC
ldxa [%g0]0x63, %r8
and %r8, 0x38, %r8 ! Core ID
#ifndef PORTABLE_CORE
add %r8, %r23, %r23
#endif
mov 0xff, %r9
#if (!defined PORTABLE_CORE || MAX_THREADS == 8)
xor %r9, 0x2, %r9 ! My core mask
#else
xor %r9, 0x2, %r9
#endif
sllx %r9, %r8, %r9 ! My core mask
#else
mov 0, %r8
mov 0xff, %r9
xor %r9, 0x2, %r9 ! My core mask
#endif
mov 0x2, %r10
cmp_startwait2_250:
cas [%r23],%g0,%r10 !lock
brz,a %r10, continue_cmp_2_250
ldxa [0x50]%asi, %r13 !Running_rw
ld [%r23], %r10
cmp_wait2_250:
brnz,a %r10, cmp_wait2_250
ld [%r23], %r10
ba cmp_startwait2_250
mov 0x2, %r10
continue_cmp_2_250:
ldxa [0x58]%asi, %r14 !Running_status
xnor %r14, %r13, %r14 !Bits equal
#ifndef PORTABLE_CORE
brz,a %r8, cmp_multi_core_2_250
#endif
mov 0x88, %r17
#ifndef PORTABLE_CORE
best_set_reg(0x2a7d2bcaca99878b, %r16, %r17)
#else
sllx %r17, %r8, %r17
#endif
cmp_multi_core_2_250:
and %r14, %r17, %r14 !Apply set/clear mask to bits equal
and %r14, %r9, %r14 !Apply core-mask
stxa %r14, [0x68]%asi
st %g0, [%r23] !clear lock
wr %g0, %r12, %asi
wrhpr %g0, 0x750, %hpstate ! ta T_CHANGE_NONHPRIV
.word 0x9194c010 ! 465: WRPR_PIL_R wrpr %r19, %r16, %pil
jmptr_2_253:
nop
nop
best_set_reg(0xe0a00000, %r20, %r27)
.word 0xb7c6c000 ! 469: JMPL_R jmpl %r27 + %r0, %r27
.word 0xda77c000 ! 473: STX_R stx %r13, [%r31 + %r0]
splash_tba_2_259:
nop
ta T_CHANGE_PRIV
setx 0x00000004003a0000, %r11, %r12
.word 0x8b90000c ! 477: WRPR_TBA_R wrpr %r0, %r12, %tba
#if (defined SPC || defined CMP1)
!$EV trig_pc_d(1, expr(@VA(.MAIN.intvec_2_262) , 16, 16)) -> intp(6,0,17,*,960,*,6a,1)
!$EV trig_pc_d(1, expr((@VA(.MAIN.intvec_2_262)&0xffffffff) , 16, 16)) -> intp(6,0,26,*,672,*,6a,1)
#else
nop
nop
set 0x5f0b7f3, %r28 !TTID : 7 (mask2tid(0x2))
#if (defined PORTABLE_CORE || MAX_THREADS == 8)
sethi %hi(0x3800), %r27
andn %r28, %r27, %r28
#ifdef PORTABLE_CORE
! Add CID to vector
ta T_CHANGE_HPRIV
ldxa [%g0]0x63, %r27
sllx %r27, 8, %r27
or %r27, %r28, %r28
#endif
#else
! Add CID IF tid matches
ifelse(7,mask2tid(0x2),`ta T_CHANGE_HPRIV;sethi %hi(0x3800), %r27;andn %r28, %r27, %r28;ldxa [%g0]0x63, %r27;sllx %r27, 8, %r27;or %r27, %r28, %r28 ')
#endif
ifelse(7,mask2tid(0x2),`.align 16')
stxa %r28, [%g0] 0x73
#endif
intvec_2_262:
#if (defined SPC || defined CMP1)
wrhpr %g0, 0x0, %halt ! HALT
#else
ifelse(7,mask2tid(0x2),`wrhpr %g0, 0x0, %halt ! HALT')
#endif
.word 0x39400001 ! 481: FBPUGE fbuge,a,pn %fcc0, <label_0x1>
.word 0xe037e1f3 ! 485: STH_I sth %r16, [%r31 + 0x01f3]
splash_lsu_2_263:
nop
nop
ta T_CHANGE_HPRIV
set 0x225c8f1f, %r2
mov 0x6, %r1
sllx %r1, 32, %r1
or %r1, %r2, %r2
.word 0x3a800001 ! 1: BCC bcc,a <label_0x1>
stxa %r2, [%r0] ASI_LSU_CONTROL
.word 0x3d400002 ! 489: FBPULE fbule,a,pn %fcc0, <label_0x2>
.word 0x8d90264a ! 493: WRPR_PSTATE_I wrpr %r0, 0x064a, %pstate
.word 0xe19fe160 ! 497: LDDFA_I ldda [%r31, 0x0160], %f16
splash_tba_2_270:
nop
ta T_CHANGE_PRIV
set 0x120000, %r12
.word 0x8b90000c ! 501: WRPR_TBA_R wrpr %r0, %r12, %tba
.word 0xe11fe040 ! 505: LDDF_I ldd [%r31, 0x0040], %f16
.word 0x8d802000 ! 509: WRFPRS_I wr %r0, 0x0000, %fprs
dvapa_2_277:
nop
nop
ta T_CHANGE_HPRIV
mov 0xef2, %r20
mov 0x4, %r19
sllx %r20, 23, %r20
or %r19, %r20, %r19
stxa %r19, [%g0] ASI_LSU_CONTROL
mov 0x38, %r18
stxa %r31, [%r18]0x58
wrhpr %g0, 0x35a, %hpstate ! ta T_CHANGE_NONHPRIV
.word 0xe09fdd40 ! 513: LDDA_R ldda [%r31, %r0] 0xea, %r16
jmptr_2_279:
nop
nop
best_set_reg(0xe1a00000, %r20, %r27)
.word 0xb7c6c000 ! 517: JMPL_R jmpl %r27 + %r0, %r27
mondo_2_280:
nop
nop
.word 0x87802025 ! 1: WRASI_I wr %r0, 0x0025, %asi
stxa %r18, [%r0+0x3e0] %asi
.word 0x87802014 ! 1: WRASI_I wr %r0, 0x0014, %asi
.word 0x9d940008 ! 521: WRPR_WSTATE_R wrpr %r16, %r8, %wstate
.word 0xe08fc3c0 ! 525: LDUBA_R lduba [%r31, %r0] 0x1e, %r16
.word 0xe1e7c720 ! 529: CASA_I casa [%r31] 0x39, %r0, %r16
.word 0x8d802000 ! 533: WRFPRS_I wr %r0, 0x0000, %fprs
mondo_2_286:
nop
nop
.word 0x87802025 ! 1: WRASI_I wr %r0, 0x0025, %asi
stxa %r17, [%r0+0x3c8] %asi
.word 0x87802055 ! 1: WRASI_I wr %r0, 0x0055, %asi
.word 0x9d950014 ! 537: WRPR_WSTATE_R wrpr %r20, %r20, %wstate
splash_tba_2_288:
nop
ta T_CHANGE_PRIV
setx 0x00000000003a0000, %r11, %r12
.word 0x8b90000c ! 541: WRPR_TBA_R wrpr %r0, %r12, %tba
.word 0x08800001 ! 545: BLEU bleu <label_0x1>
nop
nop
ta T_CHANGE_HPRIV ! macro
donret_2_292:
rd %pc, %r12
mov HIGHVA_HIGHNUM, %r10
sllx %r10, 32, %r10
or %r12, %r10, %r12
add %r12, (donretarg_2_292-donret_2_292), %r12
add %r12, 0x8, %r11 ! nonseq tnpc
wrpr %g0, 0x1, %tl
wrpr %g0, %r12, %tpc
wrpr %g0, %r11, %tnpc
set (0x00514000 | (0x89 << 24)), %r13
and %r12, 0xfff, %r14
sllx %r14, 32, %r14
or %r13, %r14, %r20
wrpr %r20, %g0, %tstate
wrhpr %g0, 0x1b0c, %htstate
best_set_reg(0x1998, %g1, %g2)
wrpr %g0, %g2, %pstate ! rand=0 (2)
ldx [%r12+%r0], %g1
retry
donretarg_2_292:
.word 0x2b400001 ! 549: FBPUG fbug,a,pn %fcc0, <label_0x1>
brcommon1_2_295:
nop
nop
setx common_target, %r12, %r27
lduw [%r27-4], %r12 ! Load common dest into dcache ..
stuw %r12, [%r27-4] ! Load common dest into dcache ..
ba,a .+12
.word 0xe1e7d160 ! 1: CASA_I casa [%r31] 0x8b, %r0, %r16
ba,a .+8
jmpl %r27-4, %r27
.word 0x9bb20493 ! 553: FCMPLE32 fcmple32 %d8, %d50, %r13
nop
nop
ta T_CHANGE_HPRIV
mov 0x1, %r11
splash_cmpr_2_298:
sllx %r11, 63, %r11
not %r11, %r11
rd %tick, %r10
#if (defined SPC || defined CMP1)
add %r10, 0x100, %r10
#else
add %r10, 0xc00, %r10
#endif
and %r10, %r11, %r10
wrhpr %r10, %g0, %hsys_tick_cmpr
wrhpr %g0, 0x0, %halt ! HALT
rd %tick, %r10
#if (defined SPC || defined CMP1)
add %r10, 0x250, %r10
#else
add %r10, 0x700, %r10
#endif
and %r10, %r11, %r10
.word 0xb380000a ! 1: WR_STICK_CMPR_REG_R wr %r0, %r10, %-
#if (defined SPC || defined CMP1)
!$EV trig_pc_d(1, expr(@VA(.MAIN.splash_cmpr_2_298)+8 , 16, 16)) -> intp(1,0,16,*,736,*,8e,1)
!$EV trig_pc_d(1, expr((@VA(.MAIN.splash_cmpr_2_298)&0xffffffff)+8 , 16, 16)) -> intp(2,0,23,*,736,*,8e,1)
#endif
wrhpr %g0, 0x0, %halt ! HALT
.word 0x81982edf ! 1: WRHPR_HPSTATE_I wrhpr %r0, 0x0edf, %hpstate
.word 0x81b01021 ! 557: SIAM siam 1
splash_tick_2_300:
nop
nop
ta T_CHANGE_HPRIV
best_set_reg(0xf8568e283f2715c6, %r16, %r17)
.word 0x8980000a ! 561: WRTICK_R wr %r0, %r10, %tick
cancelint_2_302:
rdhpr %halt, %r12
.word 0x85880000 ! 565: ALLCLEAN <illegal instruction>
nop
nop
set 0xa4b0e95a, %r28 !TTID : 1 (mask2tid(0x2))
#if (defined PORTABLE_CORE || MAX_THREADS == 8)
sethi %hi(0x3800), %r27
andn %r28, %r27, %r28
#ifdef PORTABLE_CORE
! Add CID to vector
ta T_CHANGE_HPRIV
ldxa [%g0]0x63, %r27
sllx %r27, 8, %r27
or %r27, %r28, %r28
#endif
#else
! Add CID IF tid matches
ifelse(1,mask2tid(0x2),`ta T_CHANGE_HPRIV;sethi %hi(0x3800), %r27;andn %r28, %r27, %r28;ldxa [%g0]0x63, %r27;sllx %r27, 8, %r27;or %r27, %r28, %r28 ')
#endif
sethi %hi(0x30000), %r27
andn %r28, %r27, %r28
ta T_CHANGE_HPRIV
ifelse(1,mask2tid(0x2),`.align 16')
stxa %r28, [%g0] 0x73
intvec_2_305:
.word 0x97b444c3 ! 569: FCMPNE32 fcmpne32 %d48, %d34, %r11
.word 0xe2cfc3c0 ! 573: LDSBA_R ldsba [%r31, %r0] 0x1e, %r17
.word 0xa1902004 ! 577: WRPR_GL_I wrpr %r0, 0x0004, %-
nop
nop
set 0x547099c2, %r28 !TTID : 1 (mask2tid(0x2))
#if (defined PORTABLE_CORE || MAX_THREADS == 8)
sethi %hi(0x3800), %r27
andn %r28, %r27, %r28
#ifdef PORTABLE_CORE
! Add CID to vector
ta T_CHANGE_HPRIV
ldxa [%g0]0x63, %r27
sllx %r27, 8, %r27
or %r27, %r28, %r28
#endif
#else
! Add CID IF tid matches
ifelse(1,mask2tid(0x2),`ta T_CHANGE_HPRIV;sethi %hi(0x3800), %r27;andn %r28, %r27, %r28;ldxa [%g0]0x63, %r27;sllx %r27, 8, %r27;or %r27, %r28, %r28 ')
#endif
sethi %hi(0x30000), %r27
andn %r28, %r27, %r28
ta T_CHANGE_HPRIV
ifelse(1,mask2tid(0x2),`.align 16')
stxa %r28, [%g0] 0x73
intvec_2_309:
.word 0xa3a189c8 ! 581: FDIVd fdivd %f6, %f8, %f48
trapasi_2_313:
nop
mov 0x8, %r1 ! (VA for ASI 0x5b)
.word 0xe2d84b60 ! 585: LDXA_R ldxa [%r1, %r0] 0x5b, %r17
.word 0xe277e1e0 ! 589: STX_I stx %r17, [%r31 + 0x01e0]
.word 0xc0bfdc40 ! 593: STDA_R stda %r0, [%r31 + %r0] 0xe2
.word 0x8d9036ce ! 597: WRPR_PSTATE_I wrpr %r0, 0x16ce, %pstate
splash_lsu_2_322:
nop
nop
ta T_CHANGE_HPRIV
set 0x12127eb5, %r2
mov 0x4, %r1
sllx %r1, 32, %r1
or %r1, %r2, %r2
.word 0x07400001 ! 1: FBPUL fbul
stxa %r2, [%r0] ASI_LSU_CONTROL
.word 0x3d400001 ! 601: FBPULE fbule,a,pn %fcc0, <label_0x1>
splash_tick_2_324:
nop
nop
ta T_CHANGE_HPRIV
best_set_reg(0x87155266af2ca1e9, %r16, %r17)
.word 0x8980000a ! 605: WRTICK_R wr %r0, %r10, %tick
cmp_2_326:
nop
nop
ta T_CHANGE_HPRIV
rd %asi, %r12
wr %r0, 0x41, %asi
set sync_thr_counter4, %r23
#ifndef SPC
ldxa [%g0]0x63, %r8
and %r8, 0x38, %r8 ! Core ID
#ifndef PORTABLE_CORE
add %r8, %r23, %r23
#endif
mov 0xff, %r9
#if (!defined PORTABLE_CORE || MAX_THREADS == 8)
xor %r9, 0x2, %r9 ! My core mask
#else
xor %r9, 0x2, %r9
#endif
sllx %r9, %r8, %r9 ! My core mask
#else
mov 0, %r8
mov 0xff, %r9
xor %r9, 0x2, %r9 ! My core mask
#endif
mov 0x2, %r10
cmp_startwait2_326:
cas [%r23],%g0,%r10 !lock
brz,a %r10, continue_cmp_2_326
ldxa [0x50]%asi, %r13 !Running_rw
ld [%r23], %r10
cmp_wait2_326:
brnz,a %r10, cmp_wait2_326
ld [%r23], %r10
ba cmp_startwait2_326
mov 0x2, %r10
continue_cmp_2_326:
ldxa [0x58]%asi, %r14 !Running_status
xnor %r14, %r13, %r14 !Bits equal
#ifndef PORTABLE_CORE
brz,a %r8, cmp_multi_core_2_326
#endif
mov 0xb6, %r17
#ifndef PORTABLE_CORE
best_set_reg(0x8f0012297f0b0d3d, %r16, %r17)
#else
sllx %r17, %r8, %r17
#endif
cmp_multi_core_2_326:
and %r14, %r17, %r14 !Apply set/clear mask to bits equal
and %r14, %r9, %r14 !Apply core-mask
stxa %r14, [0x68]%asi
st %g0, [%r23] !clear lock
wr %g0, %r12, %asi
.word 0xe21fe1c0 ! 609: LDD_I ldd [%r31 + 0x01c0], %r17
jmptr_2_328:
nop
nop
best_set_reg(0xe0a00000, %r20, %r27)
.word 0xb7c6c000 ! 613: JMPL_R jmpl %r27 + %r0, %r27
intveclr_2_330:
nop
nop
ta T_CHANGE_HPRIV
setx 0x2d108a16571b5b4c, %r1, %r28
stxa %r28, [%g0] 0x72
wrhpr %g0, 0xf00, %hpstate ! ta T_CHANGE_NONHPRIV
.word 0x25400001 ! 617: FBPLG fblg,a,pn %fcc0, <label_0x1>
pmu_2_332:
nop
nop
setx 0xffffffb3ffffffaf, %g1, %g7
.word 0xa3800007 ! 621: WR_PERF_COUNTER_R wr %r0, %r7, %-
.word 0x8780208b ! 625: WRASI_I wr %r0, 0x008b, %asi
splash_tba_2_337:
nop
ta T_CHANGE_PRIV
setx 0x00000004003a0000, %r11, %r12
.word 0x8b90000c ! 629: WRPR_TBA_R wrpr %r0, %r12, %tba
#if (defined SPC || defined CMP1)
!$EV trig_pc_d(1, expr(@VA(.MAIN.intvec_2_338) , 16, 16)) -> intp(0,0,13,*,760,*,2b,1)
!$EV trig_pc_d(1, expr((@VA(.MAIN.intvec_2_338)&0xffffffff) , 16, 16)) -> intp(1,0,13,*,680,*,2b,1)
#else
nop
nop
set 0xd950cae1, %r28 !TTID : 2 (mask2tid(0x2))
#if (defined PORTABLE_CORE || MAX_THREADS == 8)
sethi %hi(0x3800), %r27
andn %r28, %r27, %r28
#ifdef PORTABLE_CORE
! Add CID to vector
ta T_CHANGE_HPRIV
ldxa [%g0]0x63, %r27
sllx %r27, 8, %r27
or %r27, %r28, %r28
#endif
#else
! Add CID IF tid matches
ifelse(2,mask2tid(0x2),`ta T_CHANGE_HPRIV;sethi %hi(0x3800), %r27;andn %r28, %r27, %r28;ldxa [%g0]0x63, %r27;sllx %r27, 8, %r27;or %r27, %r28, %r28 ')
#endif
ifelse(2,mask2tid(0x2),`.align 16')
stxa %r28, [%g0] 0x73
#endif
intvec_2_338:
#if (defined SPC || defined CMP1)
wrhpr %g0, 0x0, %halt ! HALT
#else
ifelse(2,mask2tid(0x2),`wrhpr %g0, 0x0, %halt ! HALT')
#endif
.word 0xa3a409cc ! 633: FDIVd fdivd %f16, %f12, %f48
br_longdelay3_2_340:
nop
not %g0, %r27
jmpl %r27+0, %r27
.word 0x8d902b9a ! 637: WRPR_PSTATE_I wrpr %r0, 0x0b9a, %pstate
intveclr_2_343:
nop
nop
ta T_CHANGE_HPRIV
setx 0x8c44d207c1b18811, %r1, %r28
stxa %r28, [%g0] 0x72
wrhpr %g0, 0xc99, %hpstate ! ta T_CHANGE_NONHPRIV
.word 0x05400002 ! 641: FBPLG fblg
ibp_2_344:
nop
nop
.word 0x20800002 ! 645: BN bn,a <label_0x2>
.word 0xd5e7c3c0 ! 649: CASA_I casa [%r31] 0x1e, %r0, %r10
.word 0xd497c380 ! 653: LDUHA_R lduha [%r31, %r0] 0x1c, %r10
jmptr_2_353:
nop
nop
best_set_reg(0xe1a00000, %r20, %r27)
.word 0xb7c6c000 ! 657: JMPL_R jmpl %r27 + %r0, %r27
.word 0xd497dd40 ! 661: LDUHA_R lduha [%r31, %r0] 0xea, %r10
.word 0xc19fe040 ! 665: LDDFA_I ldda [%r31, 0x0040], %f0
.word 0xd4dfc180 ! 1: LDXA_R ldxa [%r31, %r0] 0x0c, %r10
.word 0xd43fe140 ! 1: STD_I std %r10, [%r31 + 0x0140]
mov 0xb0, %r30
.word 0x91d0001e ! 669: Tcc_R ta icc_or_xcc, %r0 + %r30
demap_2_359:
nop
mov 0x80, %g3
ta T_CHANGE_HPRIV
stxa %g3, [%g3] 0x57
.word 0xe09fdf00 ! 1: LDDA_R ldda [%r31, %r0] 0xf8, %r16
.word 0xe19fdc00 ! 1: LDDFA_R ldda [%r31, %r0], %f16
.word 0xe0bfde20 ! 1: STDA_R stda %r16, [%r31 + %r0] 0xf1
stxa %g3, [%g3] 0x57
.word 0xc09fdb20 ! 1: LDDA_R ldda [%r31, %r0] 0xd9, %r0
.word 0xc1bfdb20 ! 1: STDFA_R stda %f0, [%r0, %r31]
.word 0xe09fdf00 ! 1: LDDA_R ldda [%r31, %r0] 0xf8, %r16
stxa %g3, [%g3] 0x57
.word 0xe09fdb40 ! 1: LDDA_R ldda [%r31, %r0] 0xda, %r16
stxa %g3, [%g3] 0x57
wrhpr %g0, 0x28a, %hpstate ! ta T_CHANGE_NONHPRIV
.word 0xd41fe0bb ! 673: LDD_I ldd [%r31 + 0x00bb], %r10
memptr_2_362:
set 0x60140000, %r31
.word 0x8584748a ! 677: WRCCR_I wr %r17, 0x148a, %ccr
jmptr_2_363:
nop
nop
best_set_reg(0xe0a00000, %r20, %r27)
.word 0xb7c6c000 ! 681: JMPL_R jmpl %r27 + %r0, %r27
jmptr_2_366:
nop
nop
best_set_reg(0xe1a00000, %r20, %r27)
.word 0xb7c6c000 ! 685: JMPL_R jmpl %r27 + %r0, %r27
memptr_2_369:
set user_data_start, %r31
.word 0x85837073 ! 689: WRCCR_I wr %r13, 0x1073, %ccr
nop
nop
ta T_CHANGE_HPRIV ! macro
donret_2_370:
rd %pc, %r12
mov HIGHVA_HIGHNUM, %r10
sllx %r10, 32, %r10
or %r12, %r10, %r12
add %r12, (donretarg_2_370-donret_2_370+4), %r12
add %r12, 0x4, %r11 ! seq tnpc
wrpr %g0, 0x2, %tl
wrpr %g0, %r12, %tpc
wrpr %g0, %r11, %tnpc
set (0x00d84b00 | (16 << 24)), %r13
and %r12, 0xfff, %r14
sllx %r14, 32, %r14
or %r13, %r14, %r20
wrpr %r20, %g0, %tstate
wrhpr %g0, 0x1507, %htstate
wrhpr %g0, 0xadb, %hpstate ! rand=1 (2)
ldx [%r12+%r0], %g1
retry
donretarg_2_370:
.word 0xd46fe1b5 ! 693: LDSTUB_I ldstub %r10, [%r31 + 0x01b5]
brcommon3_2_371:
nop
nop
setx common_target, %r12, %r27
lduw [%r27-0], %r12 ! Load common dest into dcache ..
stuw %r12, [%r27-4] ! Load common dest into dcache ..
ba,a .+12
.word 0xd537e090 ! 1: STQF_I - %f10, [0x0090, %r31]
ba,a .+8
jmpl %r27-0, %r27
.word 0x95b7c7c0 ! 697: PDIST pdistn %d62, %d0, %d10
.word 0xd477c000 ! 701: STX_R stx %r10, [%r31 + %r0]
.word 0xd537c000 ! 705: STQF_R - %f10, [%r0, %r31]
.word 0xd43fe0c0 ! 709: STD_I std %r10, [%r31 + 0x00c0]
cmp_2_379:
nop
nop
ta T_CHANGE_HPRIV
rd %asi, %r12
wr %r0, 0x41, %asi
set sync_thr_counter4, %r23
#ifndef SPC
ldxa [%g0]0x63, %r8
and %r8, 0x38, %r8 ! Core ID
#ifndef PORTABLE_CORE
add %r8, %r23, %r23
#endif
mov 0xff, %r9
#if (!defined PORTABLE_CORE || MAX_THREADS == 8)
xor %r9, 0x2, %r9 ! My core mask
#else
xor %r9, 0x2, %r9
#endif
sllx %r9, %r8, %r9 ! My core mask
#else
mov 0, %r8
mov 0xff, %r9
xor %r9, 0x2, %r9 ! My core mask
#endif
mov 0x2, %r10
cmp_startwait2_379:
cas [%r23],%g0,%r10 !lock
brz,a %r10, continue_cmp_2_379
ldxa [0x50]%asi, %r13 !Running_rw
ld [%r23], %r10
cmp_wait2_379:
brnz,a %r10, cmp_wait2_379
ld [%r23], %r10
ba cmp_startwait2_379
mov 0x2, %r10
continue_cmp_2_379:
ldxa [0x58]%asi, %r14 !Running_status
xnor %r14, %r13, %r14 !Bits equal
#ifndef PORTABLE_CORE
brz,a %r8, cmp_multi_core_2_379
#endif
mov 0x78, %r17
#ifndef PORTABLE_CORE
best_set_reg(0x0afd4f50e1542d1b, %r16, %r17)
#else
sllx %r17, %r8, %r17
#endif
cmp_multi_core_2_379:
and %r14, %r17, %r14 !Apply set/clear mask to bits equal
and %r14, %r9, %r14 !Apply core-mask
stxa %r14, [0x60]%asi
st %g0, [%r23] !clear lock
wr %g0, %r12, %asi
.word 0x9194c006 ! 713: WRPR_PIL_R wrpr %r19, %r6, %pil
.word 0xd48008a0 ! 717: LDUWA_R lduwa [%r0, %r0] 0x45, %r10
.word 0xd527e0b0 ! 721: STF_I st %f10, [0x00b0, %r31]
intveclr_2_383:
nop
nop
ta T_CHANGE_HPRIV
setx 0xecbd9d103d33fddf, %r1, %r28
stxa %r28, [%g0] 0x72
.word 0x05400001 ! 725: FBPLG fblg
demap_2_386:
nop
mov 0x80, %g3
ta T_CHANGE_HPRIV
stxa %g3, [%g3] 0x5f
stxa %g3, [%g3] 0x57
.word 0xc19fdd40 ! 1: LDDFA_R ldda [%r31, %r0], %f0
.word 0xc1bfde00 ! 1: STDFA_R stda %f0, [%r0, %r31]
.word 0xe1bfde20 ! 1: STDFA_R stda %f16, [%r0, %r31]
stxa %g3, [%g3] 0x5f
wrhpr %g0, 0x718, %hpstate ! ta T_CHANGE_NONHPRIV
.word 0xd41fe1b9 ! 729: LDD_I ldd [%r31 + 0x01b9], %r10
.word 0xd4bfe0fc ! 733: STDA_I stda %r10, [%r31 + 0x00fc] %asi
memptr_2_389:
set 0x60540000, %r31
.word 0x85826834 ! 737: WRCCR_I wr %r9, 0x0834, %ccr
splash_tick_2_390:
nop
nop
ta T_CHANGE_HPRIV
best_set_reg(0x3682c18f45de7be6, %r16, %r17)
.word 0x8980000a ! 741: WRTICK_R wr %r0, %r10, %tick
.word 0xd5e7c3c0 ! 745: CASA_I casa [%r31] 0x1e, %r0, %r10
splash_lsu_2_393:
nop
nop
ta T_CHANGE_HPRIV
set 0x90923aa7, %r2
mov 0x6, %r1
sllx %r1, 32, %r1
or %r1, %r2, %r2
stxa %r2, [%r0] ASI_LSU_CONTROL
.word 0x3d400001 ! 749: FBPULE fbule,a,pn %fcc0, <label_0x1>
br_longdelay4_2_395:
nop
not %g0, %r27
jmpl %r27+0, %r27
.word 0x9d902000 ! 753: WRPR_WSTATE_I wrpr %r0, 0x0000, %wstate
brcommon3_2_399:
nop
nop
setx common_target, %r12, %r27
lduw [%r27-0], %r12 ! Load common dest into dcache ..
stuw %r12, [%r27-0] ! Load common dest into dcache ..
ba,a .+12
.word 0xd46fe190 ! 1: LDSTUB_I ldstub %r10, [%r31 + 0x0190]
ba,a .+8
jmpl %r27-4, %r27
.word 0xd51fe120 ! 757: LDDF_I ldd [%r31, 0x0120], %f10
.word 0xf16fe0de ! 761: PREFETCH_I prefetch [%r31 + 0x00de], #24
nop
nop
ta T_CHANGE_HPRIV
mov 0x0, %r11
splash_cmpr_2_403:
sllx %r11, 63, %r11
not %r11, %r11
rd %tick, %r10
#if (defined SPC || defined CMP1)
add %r10, 0x200, %r10
#else
add %r10, 0x380, %r10
#endif
and %r10, %r11, %r10
wrhpr %r10, %g0, %hsys_tick_cmpr
rd %tick, %r10
#if (defined SPC || defined CMP1)
add %r10, 0x200, %r10
#else
add %r10, 0x700, %r10
#endif
and %r10, %r11, %r10
.word 0xaf80000a ! 1: WR_TICK_CMPR_REG_R wr %r0, %r10, %-
.word 0x81983d45 ! 1: WRHPR_HPSTATE_I wrhpr %r0, 0x1d45, %hpstate
.word 0x81b01021 ! 765: SIAM siam 1
memptr_2_407:
set 0x60540000, %r31
.word 0x85832013 ! 769: WRCCR_I wr %r12, 0x0013, %ccr
br_badelay3_2_410:
.word 0x20800001 ! 1: BN bn,a <label_0x1>
.word 0xf55ffc5e ! Random illegal ?
.word 0xe9140008 ! 1: LDQF_R - [%r16, %r8], %f20
.word 0x91a5082b ! 773: FADDs fadds %f20, %f11, %f8
splash_lsu_2_411:
nop
nop
ta T_CHANGE_HPRIV
set 0xdd4e7fb1, %r2
mov 0x1, %r1
sllx %r1, 32, %r1
or %r1, %r2, %r2
stxa %r2, [%r0] ASI_LSU_CONTROL
ta T_CHANGE_NONHPRIV
.word 0x1d400002 ! 777: FBPULE fbule
.word 0x26800001 ! 781: BL bl,a <label_0x1>
pmu_2_417:
nop
nop
ta T_CHANGE_PRIV
setx 0xffffffbfffffffab, %g1, %g7
.word 0xa3800007 ! 785: WR_PERF_COUNTER_R wr %r0, %r7, %-
.word 0x81460000 ! 789: RD_STICK_REG stbar
demap_2_421:
nop
mov 0x80, %g3
ta T_CHANGE_HPRIV
.word 0x3d400001 ! 1: FBPULE fbule,a,pn %fcc0, <label_0x1>
stxa %g3, [%g3] 0x5f
.word 0xe1bfde00 ! 1: STDFA_R stda %f16, [%r0, %r31]
.word 0xc1bfdd40 ! 1: STDFA_R stda %f0, [%r0, %r31]
stxa %g3, [%g3] 0x57
.word 0xe09fc3e0 ! 1: LDDA_R ldda [%r31, %r0] 0x1f, %r16
stxa %g3, [%g3] 0x5f
.word 0xe19fdf00 ! 1: LDDFA_R ldda [%r31, %r0], %f16
stxa %g3, [%g3] 0x57
.word 0xc1bfdc40 ! 1: STDFA_R stda %f0, [%r0, %r31]
wrhpr %g0, 0x80b, %hpstate ! ta T_CHANGE_NONHPRIV
.word 0xd21fe1c0 ! 793: LDD_I ldd [%r31 + 0x01c0], %r9
memptr_2_424:
set 0x60540000, %r31
.word 0x8580657b ! 797: WRCCR_I wr %r1, 0x057b, %ccr
cmpenall_2_425:
nop
nop
ta T_CHANGE_HPRIV
rd %asi, %r12
wr %r0, 0x41, %asi
set sync_thr_counter4, %r23
#ifndef SPC
ldxa [%g0]0x63, %r8
and %r8, 0x38, %r8 ! Core ID
#ifndef PORTABLE_CORE
add %r8, %r23, %r23
#endif
mov 0xff, %r9
sllx %r9, %r8, %r9 ! My core mask
#else
mov 0xff, %r9 ! My core mask
#endif
cmpenall_startwait2_425:
mov 0x2, %r10
cas [%r23],%g0,%r10 !lock
brz,a %r10, continue_cmpenall_2_425
nop
cmpenall_wait2_425:
ld [%r23], %r10
brnz %r10, cmpenall_wait2_425
nop
ba,a cmpenall_startwait2_425
continue_cmpenall_2_425:
ldxa [0x58]%asi, %r14 !Running_status
wait_for_cmpstat_2_425:
ldxa [0x50]%asi, %r13 !Running_rw
cmp %r13, %r14
bne,a %xcc, wait_for_cmpstat_2_425
ldxa [0x58]%asi, %r14 !Running_status
ldxa [0x10]%asi, %r14 !Get enabled threads
and %r14, %r9, %r14 !My core mask
stxa %r14, [0x60]%asi !W1S
ldxa [0x58]%asi, %r16 !Running_status
wait_for_cmpstat2_2_425:
and %r16, %r9, %r16 !My core mask
cmp %r14, %r16
bne,a %xcc, wait_for_cmpstat2_2_425
ldxa [0x58]%asi, %r16 !Running_status
st %g0, [%r23] !clear lock
!! Send interrupt to all threads in my core in case of halted threads.
intall_mast:
mov 7, %r14
#ifdef SPC
mov %g0, %r8
#endif
intall_loop_mast:
add %r8, %r14, %r16
sllx %r16, 8, %r16
stxa %r16, [%g0]0x73
brnz %r14, intall_loop_mast
dec %r14
#if (MULTIPASS > 0)
multipass_check_mt:
rd %asi, %r12
wr %g0, ASI_SCRATCHPAD, %asi
ldxa [0x38]%asi, %r10
cmp %r10, MULTIPASS
inc %r10
stxa %r10, [0x38]%asi
be finish_diag
wr %g0, %r12, %asi
lock_sync_thds_again:
mov 0xff, %r10
set sync_thr_counter4, %r23
#ifndef SPC
add %r23,%r8,%r23 !Core's sync counter
#endif
! st %r10, [%r23] !lock sync_thr_counter4 !! Still locked from cmpenall
add %r23, 64, %r23
st %r10, [%r23] !lock sync_thr_counter5
add %r23, 64, %r23
st %r10, [%r23] !lock sync_thr_counter6
ba fork_threads
wrpr %g0, %g0, %gl
#endif
nop
nop
ta T_CHANGE_PRIV
wrpr %g0, %g0, %gl
nop
nop
.text
setx join_lbl_0_0, %g1, %g2
jmp %g2
nop
fork_lbl_0_1:
wrhpr %g0, 0x4d9, %hpstate ! ta T_CHANGE_NONHPRIV
.word 0x28800001 ! 1: BLEU bleu,a <label_0x1>
.word 0x8d9034f4 ! 1: WRPR_PSTATE_I wrpr %r0, 0x14f4, %pstate
frzptr_1_3:
nop
nop
best_set_reg(0x3cb00000+0x1ffc, %r20, %r27)
ldx [%r27+0xc], %r20
jmpl %r27, %r27
.word 0xc1bfdf20 ! 5: STDFA_R stda %f0, [%r0, %r31]
jmptr_1_5:
nop
nop
best_set_reg(0xe1200000, %r20, %r27)
.word 0xb7c6c000 ! 9: JMPL_R jmpl %r27 + %r0, %r27
.word 0xc32fc000 ! 13: STXFSR_R st-sfr %f1, [%r0, %r31]
.word 0xda97c3c0 ! 17: LDUHA_R lduha [%r31, %r0] 0x1e, %r13
jmptr_1_9:
nop
nop
best_set_reg(0xe0200000, %r20, %r27)
.word 0xb7c6c000 ! 21: JMPL_R jmpl %r27 + %r0, %r27
.word 0x8980000a ! 25: WRTICK_R wr %r0, %r10, %tick
.word 0xda8008a0 ! 29: LDUWA_R lduwa [%r0, %r0] 0x45, %r13
.word 0x24ccc001 ! 33: BRLEZ brlez,a,pt %r19,<label_0xcc001>
.word 0xe28008a0 ! 37: LDUWA_R lduwa [%r0, %r0] 0x45, %r17
.word 0xe24fc000 ! 41: LDSB_R ldsb [%r31 + %r0], %r17
.word 0x87afca40 ! 1: FCMPd fcmpd %fcc<n>, %f62, %f0
.word 0xe33fe0e0 ! 1: STDF_I std %f17, [0x00e0, %r31]
mov 0xb2, %r30
.word 0x91d0001e ! 45: Tcc_R ta icc_or_xcc, %r0 + %r30
demap_1_21:
nop
mov 0x80, %g3
ta T_CHANGE_HPRIV
.word 0x04cc8001 ! 1: BRLEZ brlez,pt %r18,<label_0xc8001>
stxa %g3, [%g3] 0x57
.word 0xc0bfc3e0 ! 1: STDA_R stda %r0, [%r31 + %r0] 0x1f
wrhpr %g0, 0x61a, %hpstate ! ta T_CHANGE_NONHPRIV
.word 0xe21fe0e9 ! 49: LDD_I ldd [%r31 + 0x00e9], %r17
.word 0xe247c000 ! 53: LDSW_R ldsw [%r31 + %r0], %r17
splash_lsu_1_22:
nop
nop
ta T_CHANGE_HPRIV
set 0xefb049bc, %r2
mov 0x1, %r1
sllx %r1, 32, %r1
or %r1, %r2, %r2
.word 0x2f400001 ! 1: FBPU fbu,a,pn %fcc0, <label_0x1>
stxa %r2, [%r0] ASI_LSU_CONTROL
.word 0x3d400001 ! 57: FBPULE fbule,a,pn %fcc0, <label_0x1>
demap_1_25:
nop
mov 0x80, %g3
ta T_CHANGE_HPRIV
.word 0x0acc0001 ! 1: BRNZ brnz,pt %r16,<label_0xc0001>
stxa %g3, [%g3] 0x57
.word 0xc09fc2c0 ! 1: LDDA_R ldda [%r31, %r0] 0x16, %r0
.word 0xc1bfdc00 ! 1: STDFA_R stda %f0, [%r0, %r31]
.word 0xe1bfc2c0 ! 1: STDFA_R stda %f16, [%r0, %r31]
stxa %g3, [%g3] 0x57
stxa %g3, [%g3] 0x57
.word 0xe19fdf00 ! 1: LDDFA_R ldda [%r31, %r0], %f16
stxa %g3, [%g3] 0x57
.word 0xe0bfdc00 ! 1: STDA_R stda %r16, [%r31 + %r0] 0xe0
.word 0xc09fdc00 ! 1: LDDA_R ldda [%r31, %r0] 0xe0, %r0
.word 0xe0bfdc00 ! 1: STDA_R stda %r16, [%r31 + %r0] 0xe0
stxa %g3, [%g3] 0x57
stxa %g3, [%g3] 0x5f
.word 0xc0bfdf00 ! 1: STDA_R stda %r0, [%r31 + %r0] 0xf8
wrhpr %g0, 0xb08, %hpstate ! ta T_CHANGE_NONHPRIV
.word 0xe21fe19a ! 61: LDD_I ldd [%r31 + 0x019a], %r17
nop
nop
mov 0x0, %r11
splash_cmpr_1_28:
sllx %r11, 63, %r11
not %r11, %r11
rd %tick, %r10
#if (defined SPC || defined CMP1)
add %r10, 0x200, %r10
#else
add %r10, 0x700, %r10
#endif
and %r10, %r11, %r10
ta T_CHANGE_PRIV
rd %tick, %r10
#if (defined SPC || defined CMP1)
add %r10, 0x100, %r10
#else
add %r10, 0x380, %r10
#endif
and %r10, %r11, %r10
.word 0xaf80000a ! 1: WR_TICK_CMPR_REG_R wr %r0, %r10, %-
.word 0x81b01021 ! 65: SIAM siam 1
.word 0xe19fe1c0 ! 69: LDDFA_I ldda [%r31, 0x01c0], %f16
.word 0xa1902005 ! 73: WRPR_GL_I wrpr %r0, 0x0005, %-
jmptr_1_34:
nop
nop
best_set_reg(0xe1200000, %r20, %r27)
.word 0xb7c6c000 ! 77: JMPL_R jmpl %r27 + %r0, %r27
nop
nop
ta T_CHANGE_HPRIV ! macro
donret_1_35:
rd %pc, %r12
mov HIGHVA_HIGHNUM, %r10
sllx %r10, 32, %r10
or %r12, %r10, %r12
add %r12, (donretarg_1_35-donret_1_35+4), %r12
add %r12, 0x4, %r11 ! seq tnpc
andn %r11, %r10, %r11 ! low VA tnpc
wrpr %g0, 0x1, %tl
wrpr %g0, %r12, %tpc
wrpr %g0, %r11, %tnpc
set (0x0053ec00 | (0x8a << 24)), %r13
and %r12, 0xfff, %r14
sllx %r14, 32, %r14
or %r13, %r14, %r20
wrpr %r20, %g0, %tstate
wrhpr %g0, 0x847, %htstate
best_set_reg(0x1cc0, %g1, %g2)
wrpr %g0, %g2, %pstate ! rand=0 (1)
done
donretarg_1_35:
.word 0x81983e9d ! 81: WRHPR_HPSTATE_I wrhpr %r0, 0x1e9d, %hpstate
#if (defined SPC || defined CMP1)
!$EV trig_pc_d(1, expr(@VA(.MAIN.intvec_1_36) , 16, 16)) -> intp(5,0,29,*,912,*,cd,1)
!$EV trig_pc_d(1, expr((@VA(.MAIN.intvec_1_36)&0xffffffff) , 16, 16)) -> intp(4,0,23,*,1000,*,cd,1)
#else
nop
nop
set 0xc7806886, %r28 !TTID : 0 (mask2tid(0x1))
#if (defined PORTABLE_CORE || MAX_THREADS == 8)
sethi %hi(0x3800), %r27
andn %r28, %r27, %r28
#ifdef PORTABLE_CORE
! Add CID to vector
ta T_CHANGE_HPRIV
ldxa [%g0]0x63, %r27
sllx %r27, 8, %r27
or %r27, %r28, %r28
#endif
#else
! Add CID IF tid matches
ifelse(0,mask2tid(0x1),`ta T_CHANGE_HPRIV;sethi %hi(0x3800), %r27;andn %r28, %r27, %r28;ldxa [%g0]0x63, %r27;sllx %r27, 8, %r27;or %r27, %r28, %r28 ')
#endif
ifelse(0,mask2tid(0x1),`.align 16')
stxa %r28, [%g0] 0x73
#endif
intvec_1_36:
#if (defined SPC || defined CMP1)
wrhpr %g0, 0x0, %halt ! HALT
#else
ifelse(0,mask2tid(0x1),`wrhpr %g0, 0x0, %halt ! HALT')
#endif
.word 0x97a049d0 ! 85: FDIVd fdivd %f32, %f16, %f42
.word 0x9a844014 ! 89: ADDcc_R addcc %r17, %r20, %r13
nop
nop
set 0x25a036be, %r28 !TTID : 6 (mask2tid(0x1))
#if (defined PORTABLE_CORE || MAX_THREADS == 8)
sethi %hi(0x3800), %r27
andn %r28, %r27, %r28
#ifdef PORTABLE_CORE
! Add CID to vector
ta T_CHANGE_HPRIV
ldxa [%g0]0x63, %r27
sllx %r27, 8, %r27
or %r27, %r28, %r28
#endif
#else
! Add CID IF tid matches
ifelse(6,mask2tid(0x1),`ta T_CHANGE_HPRIV;sethi %hi(0x3800), %r27;andn %r28, %r27, %r28;ldxa [%g0]0x63, %r27;sllx %r27, 8, %r27;or %r27, %r28, %r28 ')
#endif
sethi %hi(0x30000), %r27
andn %r28, %r27, %r28
ta T_CHANGE_HPRIV
ifelse(6,mask2tid(0x1),`.align 16')
stxa %r28, [%g0] 0x73
intvec_1_39:
.word 0x39400001 ! 93: FBPUGE fbuge,a,pn %fcc0, <label_0x1>
.word 0x81460000 ! 97: RD_STICK_REG stbar
.word 0xe0dfdc40 ! 101: LDXA_R ldxa [%r31, %r0] 0xe2, %r16
.word 0x3c800001 ! 105: BPOS bpos,a <label_0x1>
nop
nop
set 0x7f60654a, %r28 !TTID : 5 (mask2tid(0x1))
#if (defined PORTABLE_CORE || MAX_THREADS == 8)
sethi %hi(0x3800), %r27
andn %r28, %r27, %r28
#ifdef PORTABLE_CORE
! Add CID to vector
ta T_CHANGE_HPRIV
ldxa [%g0]0x63, %r27
sllx %r27, 8, %r27
or %r27, %r28, %r28
#endif
#else
! Add CID IF tid matches
ifelse(5,mask2tid(0x1),`ta T_CHANGE_HPRIV;sethi %hi(0x3800), %r27;andn %r28, %r27, %r28;ldxa [%g0]0x63, %r27;sllx %r27, 8, %r27;or %r27, %r28, %r28 ')
#endif
sethi %hi(0x30000), %r27
andn %r28, %r27, %r28
ta T_CHANGE_HPRIV
ifelse(5,mask2tid(0x1),`.align 16')
stxa %r28, [%g0] 0x73
intvec_1_47:
.word 0x39400002 ! 109: FBPUGE fbuge,a,pn %fcc0, <label_0x2>
.word 0xd8800c00 ! 113: LDUWA_R lduwa [%r0, %r0] 0x60, %r12
nop
nop
mov 0x0, %r11
splash_cmpr_1_52:
sllx %r11, 63, %r11
not %r11, %r11
rd %tick, %r10
#if (defined SPC || defined CMP1)
add %r10, 0x150, %r10
#else
add %r10, 0x380, %r10
#endif
and %r10, %r11, %r10
rd %tick, %r10
#if (defined SPC || defined CMP1)
add %r10, 0x200, %r10
#else
add %r10, 0x380, %r10
#endif
and %r10, %r11, %r10
.word 0xb380000a ! 1: WR_STICK_CMPR_REG_R wr %r0, %r10, %-
.word 0x81b01021 ! 117: SIAM siam 1
.word 0x8d802000 ! 121: WRFPRS_I wr %r0, 0x0000, %fprs
.word 0xa0dd000a ! 125: SMULcc_R smulcc %r20, %r10, %r16
brcommon2_1_54:
nop
nop
setx common_target, %r12, %r27
ba,a .+12
.word 0x9f8020f0 ! 1: SIR sir 0x00f0
ba,a .+8
jmpl %r27-4, %r27
.word 0x81b7c7c0 ! 129: PDIST pdistn %d62, %d0, %d0
memptr_1_56:
set 0x60340000, %r31
.word 0x85842c32 ! 133: WRCCR_I wr %r16, 0x0c32, %ccr
splash_lsu_1_58:
nop
nop
ta T_CHANGE_HPRIV
set 0x75ab3af2, %r2
mov 0x4, %r1
sllx %r1, 32, %r1
or %r1, %r2, %r2
stxa %r2, [%r0] ASI_LSU_CONTROL
ta T_CHANGE_NONHPRIV
.word 0x3d400001 ! 137: FBPULE fbule,a,pn %fcc0, <label_0x1>
.word 0xda77e1f8 ! 141: STX_I stx %r13, [%r31 + 0x01f8]
jmptr_1_65:
nop
nop
best_set_reg(0xe0200000, %r20, %r27)
.word 0xb7c6c000 ! 145: JMPL_R jmpl %r27 + %r0, %r27
.word 0x93d020b3 ! 149: Tcc_I tne icc_or_xcc, %r0 + 179
.word 0xda8008a0 ! 153: LDUWA_R lduwa [%r0, %r0] 0x45, %r13
fpinit_1_70:
nop
setx fp_data_quads, %r19, %r20
ldd [%r20], %f0
ldd [%r20+8], %f4
ld [%r20+16], %fsr
ld [%r20+24], %r19
wr %r19, %g0, %gsr
.word 0x91a009a4 ! 157: FDIVs fdivs %f0, %f4, %f8
.word 0xc1bfc2c0 ! 161: STDFA_R stda %f0, [%r0, %r31]
.word 0xda97d920 ! 165: LDUHA_R lduha [%r31, %r0] 0xc9, %r13
br_badelay3_1_78:
.word 0xa7a049d0 ! 1: FDIVd fdivd %f32, %f16, %f50
.word 0xd35b45bd ! Random illegal ?
.word 0xe711c00a ! 1: LDQF_R - [%r7, %r10], %f19
.word 0x93a14823 ! 169: FADDs fadds %f5, %f3, %f9
.word 0xd2c7d920 ! 173: LDSWA_R ldswa [%r31, %r0] 0xc9, %r9
nop
nop
ta T_CHANGE_HPRIV ! macro
donret_1_82:
rd %pc, %r12
mov HIGHVA_HIGHNUM, %r10
sllx %r10, 32, %r10
or %r12, %r10, %r12
add %r12, (donretarg_1_82-donret_1_82+4), %r12
add %r12, 0x4, %r11 ! seq tnpc
wrpr %g0, 0x1, %tl
wrpr %g0, %r12, %tpc
wrpr %g0, %r11, %tnpc
set (0x00645c00 | (16 << 24)), %r13
and %r12, 0xfff, %r14
sllx %r14, 32, %r14
or %r13, %r14, %r20
wrpr %r20, %g0, %tstate
wrhpr %g0, 0xc5d, %htstate
wrhpr %g0, 0xb98, %hpstate ! rand=1 (1)
ldx [%r12+%r0], %g1
retry
donretarg_1_82:
.word 0x97a309d3 ! 177: FDIVd fdivd %f12, %f50, %f42
nop
nop
set 0x1750794a, %r28 !TTID : 1 (mask2tid(0x1))
#if (defined PORTABLE_CORE || MAX_THREADS == 8)
sethi %hi(0x3800), %r27
andn %r28, %r27, %r28
#ifdef PORTABLE_CORE
! Add CID to vector
ta T_CHANGE_HPRIV
ldxa [%g0]0x63, %r27
sllx %r27, 8, %r27
or %r27, %r28, %r28
#endif
#else
! Add CID IF tid matches
ifelse(1,mask2tid(0x1),`ta T_CHANGE_HPRIV;sethi %hi(0x3800), %r27;andn %r28, %r27, %r28;ldxa [%g0]0x63, %r27;sllx %r27, 8, %r27;or %r27, %r28, %r28 ')
#endif
sethi %hi(0x30000), %r27
andn %r28, %r27, %r28
ta T_CHANGE_HPRIV
ifelse(1,mask2tid(0x1),`.align 16')
stxa %r28, [%g0] 0x73
intvec_1_83:
.word 0x99b104d2 ! 181: FCMPNE32 fcmpne32 %d4, %d18, %r12
brcommon3_1_86:
nop
nop
setx common_target, %r12, %r27
lduw [%r27], %r12 ! Load common dest into dcache ..
stuw %r12, [%r27] ! Load common dest into dcache ..
ba,a .+12
.word 0xd86fe1f0 ! 1: LDSTUB_I ldstub %r12, [%r31 + 0x01f0]
ba,a .+8
jmpl %r27+0, %r27
stxa %r11, [%r0] ASI_LSU_CONTROL
.word 0x91aac832 ! 185: FMOVGE fmovs %fcc1, %f18, %f8
cancelint_1_89:
rdhpr %halt, %r20
.word 0x85880000 ! 189: ALLCLEAN <illegal instruction>
.word 0xe927e074 ! 193: STF_I st %f20, [0x0074, %r31]
splash_lsu_1_94:
nop
nop
ta T_CHANGE_HPRIV
set 0x352b6663, %r2
mov 0x6, %r1
sllx %r1, 32, %r1
or %r1, %r2, %r2
.word 0x25400001 ! 1: FBPLG fblg,a,pn %fcc0, <label_0x1>
stxa %r2, [%r0] ASI_LSU_CONTROL
ta T_CHANGE_NONHPRIV
.word 0x1d400001 ! 197: FBPULE fbule
.word 0xa1902002 ! 201: WRPR_GL_I wrpr %r0, 0x0002, %-
br_badelay3_1_98:
.word 0x14800001 ! 1: BG bg <label_0x1>
.word 0x99405d58 ! Random illegal ?
.word 0xa3a0054c ! 1: FSQRTd fsqrt
.word 0xa5a4c82d ! 205: FADDs fadds %f19, %f13, %f18
.word 0x8f902000 ! 1: WRPR_TL_I wrpr %r0, 0x0000, %tl
reduce_priv_lvl_1_99:
ta T_CHANGE_NONPRIV ! macro
splash_lsu_1_102:
nop
nop
ta T_CHANGE_HPRIV
set 0xd3c571ac, %r2
mov 0x7, %r1
sllx %r1, 32, %r1
or %r1, %r2, %r2
stxa %r2, [%r0] ASI_LSU_CONTROL
ta T_CHANGE_NONHPRIV
.word 0x3d400001 ! 213: FBPULE fbule,a,pn %fcc0, <label_0x1>
.word 0x8d903275 ! 217: WRPR_PSTATE_I wrpr %r0, 0x1275, %pstate
.word 0xe4dfd160 ! 221: LDXA_R ldxa [%r31, %r0] 0x8b, %r18
.word 0xe19fc3e0 ! 225: LDDFA_R ldda [%r31, %r0], %f16
#if (defined SPC || defined CMP1)
!$EV trig_pc_d(1, expr(@VA(.MAIN.intvec_1_112) , 16, 16)) -> intp(2,0,6,*,1008,*,f5,1)
!$EV trig_pc_d(1, expr((@VA(.MAIN.intvec_1_112)&0xffffffff) , 16, 16)) -> intp(2,0,16,*,688,*,f5,1)
#else
nop
nop
set 0xcd20396a, %r28 !TTID : 1 (mask2tid(0x1))
#if (defined PORTABLE_CORE || MAX_THREADS == 8)
sethi %hi(0x3800), %r27
andn %r28, %r27, %r28
#ifdef PORTABLE_CORE
! Add CID to vector
ta T_CHANGE_HPRIV
ldxa [%g0]0x63, %r27
sllx %r27, 8, %r27
or %r27, %r28, %r28
#endif
#else
! Add CID IF tid matches
ifelse(1,mask2tid(0x1),`ta T_CHANGE_HPRIV;sethi %hi(0x3800), %r27;andn %r28, %r27, %r28;ldxa [%g0]0x63, %r27;sllx %r27, 8, %r27;or %r27, %r28, %r28 ')
#endif
ifelse(1,mask2tid(0x1),`.align 16')
stxa %r28, [%g0] 0x73
#endif
intvec_1_112:
.word 0x91a189c9 ! 229: FDIVd fdivd %f6, %f40, %f8
jmptr_1_115:
nop
nop
best_set_reg(0xe1200000, %r20, %r27)
.word 0xb7c6c000 ! 233: JMPL_R jmpl %r27 + %r0, %r27
.word 0xd097c400 ! 237: LDUHA_R lduha [%r31, %r0] 0x20, %r8
intveclr_1_120:
nop
nop
ta T_CHANGE_HPRIV
setx 0x8444010e65326825, %r1, %r28
stxa %r28, [%g0] 0x72
wrhpr %g0, 0x3ca, %hpstate ! ta T_CHANGE_NONHPRIV
.word 0x25400001 ! 241: FBPLG fblg,a,pn %fcc0, <label_0x1>
splash_lsu_1_122:
nop
nop
ta T_CHANGE_HPRIV
set 0x2d4b42fe, %r2
mov 0x7, %r1
sllx %r1, 32, %r1
or %r1, %r2, %r2
.word 0x2d400001 ! 1: FBPG fbg,a,pn %fcc0, <label_0x1>
stxa %r2, [%r0] ASI_LSU_CONTROL
ta T_CHANGE_NONHPRIV
.word 0x3d400001 ! 245: FBPULE fbule,a,pn %fcc0, <label_0x1>
.word 0xd137c000 ! 249: STQF_R - %f8, [%r0, %r31]
splash_lsu_1_125:
nop
nop
ta T_CHANGE_HPRIV
set 0xf53f4d7d, %r2
mov 0x2, %r1
sllx %r1, 32, %r1
or %r1, %r2, %r2
stxa %r2, [%r0] ASI_LSU_CONTROL
.word 0x3d400001 ! 253: FBPULE fbule,a,pn %fcc0, <label_0x1>
.word 0x8980000a ! 257: WRTICK_R wr %r0, %r10, %tick
.word 0xa1902009 ! 261: WRPR_GL_I wrpr %r0, 0x0009, %-
jmptr_1_133:
nop
nop
best_set_reg(0xe0200000, %r20, %r27)
.word 0xb7c6c000 ! 265: JMPL_R jmpl %r27 + %r0, %r27
nop
nop
mov 0x1, %r11
splash_cmpr_1_134:
sllx %r11, 63, %r11
not %r11, %r11
rd %tick, %r10
#if (defined SPC || defined CMP1)
add %r10, 0x150, %r10
#else
add %r10, 0x700, %r10
#endif
and %r10, %r11, %r10
ta T_CHANGE_PRIV
rd %tick, %r10
#if (defined SPC || defined CMP1)
add %r10, 0x200, %r10
#else
add %r10, 0x900, %r10
#endif
and %r10, %r11, %r10
.word 0xb380000a ! 1: WR_STICK_CMPR_REG_R wr %r0, %r10, %-
#if (defined SPC || defined CMP1)
!$EV trig_pc_d(1, expr(@VA(.MAIN.splash_cmpr_1_134)+8 , 16, 16)) -> intp(3,0,25,*,992,*,b,1)
!$EV trig_pc_d(1, expr((@VA(.MAIN.splash_cmpr_1_134)&0xffffffff)+8 , 16, 16)) -> intp(4,0,4,*,760,*,b,1)
#endif
wrhpr %g0, 0x0, %halt ! HALT
.word 0x81b01021 ! 269: SIAM siam 1
jmptr_1_135:
nop
nop
best_set_reg(0xe1200000, %r20, %r27)
.word 0xb7c6c000 ! 273: JMPL_R jmpl %r27 + %r0, %r27
intveclr_1_136:
nop
nop
ta T_CHANGE_HPRIV
setx 0xcc634955a67cbe31, %r1, %r28
stxa %r28, [%g0] 0x72
.word 0x25400002 ! 277: FBPLG fblg,a,pn %fcc0, <label_0x2>
.word 0xd137e0ec ! 281: STQF_I - %f8, [0x00ec, %r31]
splash_hpstate_1_141:
.word 0x1d400001 ! 1: FBPULE fbule
.word 0x8198358d ! 285: WRHPR_HPSTATE_I wrhpr %r0, 0x158d, %hpstate
intveclr_1_145:
nop
nop
ta T_CHANGE_HPRIV
setx 0x96a8e08245ef1c4b, %r1, %r28
stxa %r28, [%g0] 0x72
wrhpr %g0, 0x950, %hpstate ! ta T_CHANGE_NONHPRIV
.word 0x05400001 ! 289: FBPLG fblg
brcommon1_1_148:
nop
nop
setx common_target, %r12, %r27
lduw [%r27-4], %r12 ! Load common dest into dcache ..
stuw %r12, [%r27-0] ! Load common dest into dcache ..
ba,a .+12
.word 0x91a7c9c0 ! 1: FDIVd fdivd %f62, %f0, %f8
ba,a .+8
jmpl %r27-0, %r27
.word 0x99b10490 ! 293: FCMPLE32 fcmple32 %d4, %d16, %r12
.word 0xd8dfc540 ! 297: LDXA_R ldxa [%r31, %r0] 0x2a, %r12
.word 0x91924005 ! 301: WRPR_PIL_R wrpr %r9, %r5, %pil
demap_1_156:
nop
mov 0x80, %g3
ta T_CHANGE_HPRIV
.word 0x32800001 ! 1: BNE bne,a <label_0x1>
stxa %g3, [%g3] 0x5f
.word 0xc19fde00 ! 1: LDDFA_R ldda [%r31, %r0], %f0
stxa %g3, [%g3] 0x5f
.word 0xe1bfdf00 ! 1: STDFA_R stda %f16, [%r0, %r31]
stxa %g3, [%g3] 0x5f
.word 0xe19fdf20 ! 1: LDDFA_R ldda [%r31, %r0], %f16
stxa %g3, [%g3] 0x5f
.word 0xc09fde00 ! 1: LDDA_R ldda [%r31, %r0] 0xf0, %r0
stxa %g3, [%g3] 0x5f
.word 0xe0bfdf00 ! 1: STDA_R stda %r16, [%r31 + %r0] 0xf8
.word 0xe09fdc40 ! 1: LDDA_R ldda [%r31, %r0] 0xe2, %r16
.word 0xe0bfc3e0 ! 1: STDA_R stda %r16, [%r31 + %r0] 0x1f
wrhpr %g0, 0x5ca, %hpstate ! ta T_CHANGE_NONHPRIV
.word 0xd81fe188 ! 305: LDD_I ldd [%r31 + 0x0188], %r12
.word 0x91944006 ! 309: WRPR_PIL_R wrpr %r17, %r6, %pil
.word 0x87a8ca50 ! 313: FCMPd fcmpd %fcc<n>, %f34, %f16
splash_lsu_1_163:
nop
nop
ta T_CHANGE_HPRIV
set 0xfdadb94c, %r2
mov 0x7, %r1
sllx %r1, 32, %r1
or %r1, %r2, %r2
.word 0x2e800002 ! 1: BVS bvs,a <label_0x2>
stxa %r2, [%r0] ASI_LSU_CONTROL
ta T_CHANGE_NONHPRIV
.word 0x3d400001 ! 317: FBPULE fbule,a,pn %fcc0, <label_0x1>
splash_hpstate_1_166:
.word 0x81982f08 ! 321: WRHPR_HPSTATE_I wrhpr %r0, 0x0f08, %hpstate
nop
nop
ta T_CHANGE_HPRIV
mov 0x1, %r11
splash_cmpr_1_169:
sllx %r11, 63, %r11
not %r11, %r11
rd %tick, %r10
#if (defined SPC || defined CMP1)
add %r10, 0x250, %r10
#else
add %r10, 0xc00, %r10
#endif
and %r10, %r11, %r10
wrhpr %r10, %g0, %hsys_tick_cmpr
wrhpr %g0, 0x0, %halt ! HALT
rd %tick, %r10
#if (defined SPC || defined CMP1)
add %r10, 0x200, %r10
#else
add %r10, 0x700, %r10
#endif
and %r10, %r11, %r10
.word 0xb380000a ! 1: WR_STICK_CMPR_REG_R wr %r0, %r10, %-
#if (defined SPC || defined CMP1)
!$EV trig_pc_d(1, expr(@VA(.MAIN.splash_cmpr_1_169)+8 , 16, 16)) -> intp(1,0,9,*,1016,*,a3,1)
!$EV trig_pc_d(1, expr((@VA(.MAIN.splash_cmpr_1_169)&0xffffffff)+8 , 16, 16)) -> intp(4,0,2,*,712,*,a3,1)
#endif
wrhpr %g0, 0x0, %halt ! HALT
.word 0x81983f81 ! 1: WRHPR_HPSTATE_I wrhpr %r0, 0x1f81, %hpstate
.word 0x81b01021 ! 325: SIAM siam 1
intveclr_1_171:
nop
nop
ta T_CHANGE_HPRIV
setx 0x84b543b93f077925, %r1, %r28
stxa %r28, [%g0] 0x72
wrhpr %g0, 0xac2, %hpstate ! ta T_CHANGE_NONHPRIV
.word 0x05400001 ! 329: FBPLG fblg
.word 0x91908012 ! 333: WRPR_PIL_R wrpr %r2, %r18, %pil
.word 0xd23fe090 ! 337: STD_I std %r9, [%r31 + 0x0090]
demap_1_179:
nop
mov 0x80, %g3
ta T_CHANGE_HPRIV
.word 0x24800001 ! 1: BLE ble,a <label_0x1>
stxa %g3, [%g3] 0x5f
.word 0xe09fdd40 ! 1: LDDA_R ldda [%r31, %r0] 0xea, %r16
.word 0xe09fda00 ! 1: LDDA_R ldda [%r31, %r0] 0xd0, %r16
.word 0xe0bfc2c0 ! 1: STDA_R stda %r16, [%r31 + %r0] 0x16
stxa %g3, [%g3] 0x57
.word 0xc0bfc3e0 ! 1: STDA_R stda %r0, [%r31 + %r0] 0x1f
.word 0xc0bfdc40 ! 1: STDA_R stda %r0, [%r31 + %r0] 0xe2
stxa %g3, [%g3] 0x5f
.word 0xc1bfdd40 ! 1: STDFA_R stda %f0, [%r0, %r31]
.word 0xe09fdc40 ! 1: LDDA_R ldda [%r31, %r0] 0xe2, %r16
stxa %g3, [%g3] 0x5f
stxa %g3, [%g3] 0x57
wrhpr %g0, 0x31a, %hpstate ! ta T_CHANGE_NONHPRIV
.word 0xd21fe0ca ! 341: LDD_I ldd [%r31 + 0x00ca], %r9
.word 0xa1902004 ! 345: WRPR_GL_I wrpr %r0, 0x0004, %-
nop
nop
mov 0x0, %r11
splash_cmpr_1_181:
sllx %r11, 63, %r11
not %r11, %r11
rd %tick, %r10
#if (defined SPC || defined CMP1)
add %r10, 0x200, %r10
#else
add %r10, 0x700, %r10
#endif
and %r10, %r11, %r10
ta T_CHANGE_PRIV
rd %tick, %r10
#if (defined SPC || defined CMP1)
add %r10, 0x100, %r10
#else
add %r10, 0x900, %r10
#endif
and %r10, %r11, %r10
.word 0xaf80000a ! 1: WR_TICK_CMPR_REG_R wr %r0, %r10, %-
.word 0x81b01021 ! 349: SIAM siam 1
nop
nop
set 0x51802212, %r28 !TTID : 2 (mask2tid(0x1))
#if (defined PORTABLE_CORE || MAX_THREADS == 8)
sethi %hi(0x3800), %r27
andn %r28, %r27, %r28
#ifdef PORTABLE_CORE
! Add CID to vector
ta T_CHANGE_HPRIV
ldxa [%g0]0x63, %r27
sllx %r27, 8, %r27
or %r27, %r28, %r28
#endif
#else
! Add CID IF tid matches
ifelse(2,mask2tid(0x1),`ta T_CHANGE_HPRIV;sethi %hi(0x3800), %r27;andn %r28, %r27, %r28;ldxa [%g0]0x63, %r27;sllx %r27, 8, %r27;or %r27, %r28, %r28 ')
#endif
sethi %hi(0x30000), %r27
andn %r28, %r27, %r28
ta T_CHANGE_HPRIV
ifelse(2,mask2tid(0x1),`.align 16')
stxa %r28, [%g0] 0x73
intvec_1_183:
.word 0x39400001 ! 353: FBPUGE fbuge,a,pn %fcc0, <label_0x1>
splash_tba_1_187:
nop
ta T_CHANGE_PRIV
setx 0x0000000400380000, %r11, %r12
.word 0x8b90000c ! 357: WRPR_TBA_R wrpr %r0, %r12, %tba
.word 0x2a780001 ! 361: BPCS <illegal instruction>
splash_lsu_1_191:
nop
nop
ta T_CHANGE_HPRIV
set 0x2a24519b, %r2
mov 0x4, %r1
sllx %r1, 32, %r1
or %r1, %r2, %r2
stxa %r2, [%r0] ASI_LSU_CONTROL
ta T_CHANGE_NONHPRIV
.word 0x3d400002 ! 365: FBPULE fbule,a,pn %fcc0, <label_0x2>
#if (defined SPC || defined CMP1)
!$EV trig_pc_d(1, expr(@VA(.MAIN.intvec_1_194) , 16, 16)) -> intp(6,0,28,*,640,*,71,1)
!$EV trig_pc_d(1, expr((@VA(.MAIN.intvec_1_194)&0xffffffff) , 16, 16)) -> intp(6,0,17,*,1016,*,71,1)
#else
nop
nop
set 0x4900ac46, %r28 !TTID : 4 (mask2tid(0x1))
#if (defined PORTABLE_CORE || MAX_THREADS == 8)
sethi %hi(0x3800), %r27
andn %r28, %r27, %r28
#ifdef PORTABLE_CORE
! Add CID to vector
ta T_CHANGE_HPRIV
ldxa [%g0]0x63, %r27
sllx %r27, 8, %r27
or %r27, %r28, %r28
#endif
#else
! Add CID IF tid matches
ifelse(4,mask2tid(0x1),`ta T_CHANGE_HPRIV;sethi %hi(0x3800), %r27;andn %r28, %r27, %r28;ldxa [%g0]0x63, %r27;sllx %r27, 8, %r27;or %r27, %r28, %r28 ')
#endif
ifelse(4,mask2tid(0x1),`.align 16')
stxa %r28, [%g0] 0x73
#endif
intvec_1_194:
#if (defined SPC || defined CMP1)
wrhpr %g0, 0x0, %halt ! HALT
#else
ifelse(4,mask2tid(0x1),`wrhpr %g0, 0x0, %halt ! HALT')
#endif
.word 0x93b204cc ! 369: FCMPNE32 fcmpne32 %d8, %d12, %r9
#if (defined SPC || defined CMP1)
!$EV trig_pc_d(1, expr(@VA(.MAIN.intvec_1_196) , 16, 16)) -> intp(1,0,30,*,992,*,8b,1)
!$EV trig_pc_d(1, expr((@VA(.MAIN.intvec_1_196)&0xffffffff) , 16, 16)) -> intp(6,0,13,*,920,*,8b,1)
#else
nop
nop
set 0x5c4013a6, %r28 !TTID : 3 (mask2tid(0x1))
#if (defined PORTABLE_CORE || MAX_THREADS == 8)
sethi %hi(0x3800), %r27
andn %r28, %r27, %r28
#ifdef PORTABLE_CORE
! Add CID to vector
ta T_CHANGE_HPRIV
ldxa [%g0]0x63, %r27
sllx %r27, 8, %r27
or %r27, %r28, %r28
#endif
#else
! Add CID IF tid matches
ifelse(3,mask2tid(0x1),`ta T_CHANGE_HPRIV;sethi %hi(0x3800), %r27;andn %r28, %r27, %r28;ldxa [%g0]0x63, %r27;sllx %r27, 8, %r27;or %r27, %r28, %r28 ')
#endif
ifelse(3,mask2tid(0x1),`.align 16')
stxa %r28, [%g0] 0x73
#endif
intvec_1_196:
.word 0x39400001 ! 373: FBPUGE fbuge,a,pn %fcc0, <label_0x1>
frzptr_1_199:
nop
nop
best_set_reg(0x3cb00000+0x1ffc, %r20, %r27)
jmpl %r27, %r27
.word 0x20800001 ! 377: BN bn,a <label_0x1>
.word 0x32800001 ! 381: BNE bne,a <label_0x1>
#if (defined SPC || defined CMP1)
!$EV trig_pc_d(1, expr(@VA(.MAIN.intvec_1_204) , 16, 16)) -> intp(7,0,10,*,744,*,31,1)
!$EV trig_pc_d(1, expr((@VA(.MAIN.intvec_1_204)&0xffffffff) , 16, 16)) -> intp(7,0,28,*,952,*,31,1)
#else
nop
nop
set 0xd5208cef, %r28 !TTID : 4 (mask2tid(0x1))
#if (defined PORTABLE_CORE || MAX_THREADS == 8)
sethi %hi(0x3800), %r27
andn %r28, %r27, %r28
#ifdef PORTABLE_CORE
! Add CID to vector
ta T_CHANGE_HPRIV
ldxa [%g0]0x63, %r27
sllx %r27, 8, %r27
or %r27, %r28, %r28
#endif
#else
! Add CID IF tid matches
ifelse(4,mask2tid(0x1),`ta T_CHANGE_HPRIV;sethi %hi(0x3800), %r27;andn %r28, %r27, %r28;ldxa [%g0]0x63, %r27;sllx %r27, 8, %r27;or %r27, %r28, %r28 ')
#endif
ifelse(4,mask2tid(0x1),`.align 16')
stxa %r28, [%g0] 0x73
#endif
intvec_1_204:
#if (defined SPC || defined CMP1)
wrhpr %g0, 0x0, %halt ! HALT
#else
ifelse(4,mask2tid(0x1),`wrhpr %g0, 0x0, %halt ! HALT')
#endif
.word 0x93b444d3 ! 385: FCMPNE32 fcmpne32 %d48, %d50, %r9
.word 0x99b284c2 ! 389: FCMPNE32 fcmpne32 %d10, %d2, %r12
.word 0xd917c000 ! 393: LDQF_R - [%r31, %r0], %f12
demap_1_211:
nop
mov 0x80, %g3
ta T_CHANGE_HPRIV
stxa %g3, [%g3] 0x5f
stxa %g3, [%g3] 0x57
wrhpr %g0, 0xd93, %hpstate ! ta T_CHANGE_NONHPRIV
.word 0xd81fe078 ! 397: LDD_I ldd [%r31 + 0x0078], %r12
brcommon1_1_213:
nop
nop
setx common_target, %r12, %r27
lduw [%r27-4], %r12 ! Load common dest into dcache ..
stuw %r12, [%r27-4] ! Load common dest into dcache ..
ba,a .+12
.word 0x99a7c9c0 ! 1: FDIVd fdivd %f62, %f0, %f12
ba,a .+8
jmpl %r27-0, %r27
.word 0xa9b447d4 ! 401: PDIST pdistn %d48, %d20, %d20
nop
nop
set 0x6ea00a6e, %r28 !TTID : 2 (mask2tid(0x1))
#if (defined PORTABLE_CORE || MAX_THREADS == 8)
sethi %hi(0x3800), %r27
andn %r28, %r27, %r28
#ifdef PORTABLE_CORE
! Add CID to vector
ta T_CHANGE_HPRIV
ldxa [%g0]0x63, %r27
sllx %r27, 8, %r27
or %r27, %r28, %r28
#endif
#else
! Add CID IF tid matches
ifelse(2,mask2tid(0x1),`ta T_CHANGE_HPRIV;sethi %hi(0x3800), %r27;andn %r28, %r27, %r28;ldxa [%g0]0x63, %r27;sllx %r27, 8, %r27;or %r27, %r28, %r28 ')
#endif
sethi %hi(0x30000), %r27
andn %r28, %r27, %r28
ta T_CHANGE_HPRIV
ifelse(2,mask2tid(0x1),`.align 16')
stxa %r28, [%g0] 0x73
intvec_1_215:
.word 0x19400001 ! 405: FBPUGE fbuge
.word 0xe9e7d140 ! 409: CASA_I casa [%r31] 0x8a, %r0, %r20
.word 0x91940014 ! 413: WRPR_PIL_R wrpr %r16, %r20, %pil
.word 0xc19fe000 ! 417: LDDFA_I ldda [%r31, 0x0000], %f0
.word 0xe937c000 ! 421: STQF_R - %f20, [%r0, %r31]
.word 0x3c800001 ! 1: BPOS bpos,a <label_0x1>
br_longdelay5_1_224:
#if (defined SPC || defined CMP1)
!$EV trig_pc_d(1, expr((@VA(.MAIN.br_longdelay5_1_224)&0xffffffff) , 16, 16)) -> intp(mask2tid(0x1),0,0,*,944,*,ffffffffffffffff,1)
!$EV trig_pc_d(1, expr((@VA(.MAIN.br_longdelay5_1_224)) , 16, 16)) -> intp(mask2tid(0x1),0,0,*,752,*,ffffffffffffffff,1)
wrhpr %g0, 0x0, %halt ! HALT
#endif
.word 0xe9e7d040 ! 425: CASA_I casa [%r31] 0x82, %r0, %r20
#if (defined SPC || defined CMP1)
!$EV trig_pc_d(1, expr(@VA(.MAIN.intvec_1_226) , 16, 16)) -> intp(0,0,31,*,664,*,d1,1)
!$EV trig_pc_d(1, expr((@VA(.MAIN.intvec_1_226)&0xffffffff) , 16, 16)) -> intp(1,0,5,*,752,*,d1,1)
#else
nop
nop
set 0xfa705f5e, %r28 !TTID : 7 (mask2tid(0x1))
#if (defined PORTABLE_CORE || MAX_THREADS == 8)
sethi %hi(0x3800), %r27
andn %r28, %r27, %r28
#ifdef PORTABLE_CORE
! Add CID to vector
ta T_CHANGE_HPRIV
ldxa [%g0]0x63, %r27
sllx %r27, 8, %r27
or %r27, %r28, %r28
#endif
#else
! Add CID IF tid matches
ifelse(7,mask2tid(0x1),`ta T_CHANGE_HPRIV;sethi %hi(0x3800), %r27;andn %r28, %r27, %r28;ldxa [%g0]0x63, %r27;sllx %r27, 8, %r27;or %r27, %r28, %r28 ')
#endif
ifelse(7,mask2tid(0x1),`.align 16')
stxa %r28, [%g0] 0x73
#endif
intvec_1_226:
.word 0x9ba509ca ! 429: FDIVd fdivd %f20, %f10, %f44
jmptr_1_228:
nop
nop
best_set_reg(0xe0200000, %r20, %r27)
.word 0xb7c6c000 ! 433: JMPL_R jmpl %r27 + %r0, %r27
demap_1_232:
nop
mov 0x80, %g3
ta T_CHANGE_HPRIV
stxa %g3, [%g3] 0x5f
.word 0xe0bfdf20 ! 1: STDA_R stda %r16, [%r31 + %r0] 0xf9
.word 0xc1bfdf00 ! 1: STDFA_R stda %f0, [%r0, %r31]
stxa %g3, [%g3] 0x5f
.word 0xe19fdc40 ! 1: LDDFA_R ldda [%r31, %r0], %f16
.word 0xe19fdc00 ! 1: LDDFA_R ldda [%r31, %r0], %f16
stxa %g3, [%g3] 0x5f
wrhpr %g0, 0x3cb, %hpstate ! ta T_CHANGE_NONHPRIV
.word 0xda1fe171 ! 437: LDD_I ldd [%r31 + 0x0171], %r13
trapasi_1_235:
nop
mov 0x3c8, %r1 ! (VA for ASI 0x25)
.word 0xdad844a0 ! 441: LDXA_R ldxa [%r1, %r0] 0x25, %r13
.word 0xda57c000 ! 445: LDSH_R ldsh [%r31 + %r0], %r13
.word 0xda27e198 ! 449: STW_I stw %r13, [%r31 + 0x0198]
demap_1_240:
nop
mov 0x80, %g3
ta T_CHANGE_HPRIV
.word 0x1f400001 ! 1: FBPO fbo
stxa %g3, [%g3] 0x57
.word 0xc0bfdd40 ! 1: STDA_R stda %r0, [%r31 + %r0] 0xea
.word 0xe09fda00 ! 1: LDDA_R ldda [%r31, %r0] 0xd0, %r16
.word 0xc1bfdc40 ! 1: STDFA_R stda %f0, [%r0, %r31]
stxa %g3, [%g3] 0x57
.word 0xe0bfdb40 ! 1: STDA_R stda %r16, [%r31 + %r0] 0xda
wrhpr %g0, 0x998, %hpstate ! ta T_CHANGE_NONHPRIV
.word 0xda1fe048 ! 453: LDD_I ldd [%r31 + 0x0048], %r13
.word 0xda1fe150 ! 457: LDD_I ldd [%r31 + 0x0150], %r13
.word 0xc32fc000 ! 461: STXFSR_R st-sfr %f1, [%r0, %r31]
.word 0x91904011 ! 465: WRPR_PIL_R wrpr %r1, %r17, %pil
jmptr_1_253:
nop
nop
best_set_reg(0xe1200000, %r20, %r27)
.word 0xb7c6c000 ! 469: JMPL_R jmpl %r27 + %r0, %r27
.word 0xda77c000 ! 473: STX_R stx %r13, [%r31 + %r0]
splash_tba_1_259:
nop
ta T_CHANGE_PRIV
setx 0x0000000000380000, %r11, %r12
.word 0x8b90000c ! 477: WRPR_TBA_R wrpr %r0, %r12, %tba
#if (defined SPC || defined CMP1)
!$EV trig_pc_d(1, expr(@VA(.MAIN.intvec_1_262) , 16, 16)) -> intp(5,0,2,*,920,*,3b,1)
!$EV trig_pc_d(1, expr((@VA(.MAIN.intvec_1_262)&0xffffffff) , 16, 16)) -> intp(0,0,9,*,672,*,3b,1)
#else
nop
nop
set 0x15d09df0, %r28 !TTID : 5 (mask2tid(0x1))
#if (defined PORTABLE_CORE || MAX_THREADS == 8)
sethi %hi(0x3800), %r27
andn %r28, %r27, %r28
#ifdef PORTABLE_CORE
! Add CID to vector
ta T_CHANGE_HPRIV
ldxa [%g0]0x63, %r27
sllx %r27, 8, %r27
or %r27, %r28, %r28
#endif
#else
! Add CID IF tid matches
ifelse(5,mask2tid(0x1),`ta T_CHANGE_HPRIV;sethi %hi(0x3800), %r27;andn %r28, %r27, %r28;ldxa [%g0]0x63, %r27;sllx %r27, 8, %r27;or %r27, %r28, %r28 ')
#endif
ifelse(5,mask2tid(0x1),`.align 16')
stxa %r28, [%g0] 0x73
#endif
intvec_1_262:
#if (defined SPC || defined CMP1)
wrhpr %g0, 0x0, %halt ! HALT
#else
ifelse(5,mask2tid(0x1),`wrhpr %g0, 0x0, %halt ! HALT')
#endif
.word 0xa1b504c3 ! 481: FCMPNE32 fcmpne32 %d20, %d34, %r16
.word 0xe037e0a6 ! 485: STH_I sth %r16, [%r31 + 0x00a6]
splash_lsu_1_263:
nop
nop
ta T_CHANGE_HPRIV
set 0xddea1e24, %r2
mov 0x4, %r1
sllx %r1, 32, %r1
or %r1, %r2, %r2
.word 0x18800001 ! 1: BGU bgu <label_0x1>
stxa %r2, [%r0] ASI_LSU_CONTROL
.word 0x3d400002 ! 489: FBPULE fbule,a,pn %fcc0, <label_0x2>
.word 0x8d902983 ! 493: WRPR_PSTATE_I wrpr %r0, 0x0983, %pstate
.word 0xe19fe020 ! 497: LDDFA_I ldda [%r31, 0x0020], %f16
splash_tba_1_270:
nop
ta T_CHANGE_PRIV
set 0x120000, %r12
.word 0x8b90000c ! 501: WRPR_TBA_R wrpr %r0, %r12, %tba
.word 0xe11fe170 ! 505: LDDF_I ldd [%r31, 0x0170], %f16
.word 0x8d802000 ! 509: WRFPRS_I wr %r0, 0x0000, %fprs
dvapa_1_277:
nop
nop
ta T_CHANGE_HPRIV
mov 0xd18, %r20
mov 0x18, %r19
sllx %r20, 23, %r20
or %r19, %r20, %r19
stxa %r19, [%g0] ASI_LSU_CONTROL
mov 0x38, %r18
stxa %r31, [%r18]0x58
wrhpr %g0, 0x3c1, %hpstate ! ta T_CHANGE_NONHPRIV
.word 0xc32fc000 ! 513: STXFSR_R st-sfr %f1, [%r0, %r31]
jmptr_1_279:
nop
nop
best_set_reg(0xe0200000, %r20, %r27)
.word 0xb7c6c000 ! 517: JMPL_R jmpl %r27 + %r0, %r27
mondo_1_280:
nop
nop
.word 0x87802025 ! 1: WRASI_I wr %r0, 0x0025, %asi
stxa %r18, [%r0+0x3c0] %asi
.word 0x87802089 ! 1: WRASI_I wr %r0, 0x0089, %asi
.word 0x9d924006 ! 521: WRPR_WSTATE_R wrpr %r9, %r6, %wstate
.word 0xe08fd160 ! 525: LDUBA_R lduba [%r31, %r0] 0x8b, %r16
iaw_1_284:
nop
nop
ta T_CHANGE_HPRIV
mov 8, %r18
rd %asi, %r12
wr %r0, 0x41, %asi
set sync_thr_counter4, %r23
#ifndef SPC
ldxa [%g0]0x63, %r8
and %r8, 0x38, %r8 ! Core ID
#ifndef PORTABLE_CORE
add %r8, %r23, %r23
#endif
#else
mov 0, %r8
#endif
mov 0x1, %r16
iaw_startwait1_284:
cas [%r23],%g0,%r16 !lock
brz,a %r16, continue_iaw_1_284
mov (~0x1&0xf), %r16
ld [%r23], %r16
iaw_wait1_284:
brnz %r16, iaw_wait1_284
ld [%r23], %r16
ba iaw_startwait1_284
mov 0x1, %r16
continue_iaw_1_284:
sllx %r16, %r8, %r16 !Mask for my core only
ldxa [0x58]%asi, %r17 !Running_status
wait_for_stat_1_284:
ldxa [0x50]%asi, %r13 !Running_rw
cmp %r13, %r17
bne,a %xcc, wait_for_stat_1_284
ldxa [0x58]%asi, %r17 !Running_status
stxa %r16, [0x68]%asi !Park (W1C)
ldxa [0x50]%asi, %r14 !Running_rw
wait_for_iaw_1_284:
ldxa [0x58]%asi, %r17 !Running_status
cmp %r14, %r17
bne,a %xcc, wait_for_iaw_1_284
ldxa [0x50]%asi, %r14 !Running_rw
iaw_doit1_284:
mov 0x38, %r18
iaw2_1_284:
rdpr %tba, %r19
mov 0x102, %r20
sllx %r20, 5, %r20
add %r20, %r19, %r19
stxa %r19, [%r18]0x50
stxa %r16, [0x60] %asi ! Unpark (W1S)
st %g0, [%r23] !clear lock
wr %r0, %r12, %asi ! restore %asi
wrhpr %g0, 0xf00, %hpstate ! ta T_CHANGE_NONHPRIV
.word 0xe01fe060 ! 529: LDD_I ldd [%r31 + 0x0060], %r16
.word 0x8d802004 ! 533: WRFPRS_I wr %r0, 0x0004, %fprs
mondo_1_286:
nop
nop
.word 0x87802025 ! 1: WRASI_I wr %r0, 0x0025, %asi
stxa %r20, [%r0+0x3e0] %asi
.word 0x87802020 ! 1: WRASI_I wr %r0, 0x0020, %asi
.word 0x9d944003 ! 537: WRPR_WSTATE_R wrpr %r17, %r3, %wstate
splash_tba_1_288:
nop
ta T_CHANGE_PRIV
setx 0x0000000400380000, %r11, %r12
.word 0x8b90000c ! 541: WRPR_TBA_R wrpr %r0, %r12, %tba
.word 0x08800001 ! 545: BLEU bleu <label_0x1>
nop
nop
ta T_CHANGE_HPRIV ! macro
donret_1_292:
rd %pc, %r12
mov HIGHVA_HIGHNUM, %r10
sllx %r10, 32, %r10
or %r12, %r10, %r12
add %r12, (donretarg_1_292-donret_1_292), %r12
add %r12, 0x8, %r11 ! nonseq tnpc
wrpr %g0, 0x1, %tl
wrpr %g0, %r12, %tpc
wrpr %g0, %r11, %tnpc
set (0x00f86800 | (0x4f << 24)), %r13
and %r12, 0xfff, %r14
sllx %r14, 32, %r14
or %r13, %r14, %r20
wrpr %r20, %g0, %tstate
wrhpr %g0, 0x1a5c, %htstate
best_set_reg(0x1e9, %g1, %g2)
wrpr %g0, %g2, %pstate ! rand=0 (1)
ldx [%r12+%r0], %g1
retry
donretarg_1_292:
.word 0x24800001 ! 549: BLE ble,a <label_0x1>
brcommon1_1_295:
nop
nop
setx common_target, %r12, %r27
lduw [%r27-4], %r12 ! Load common dest into dcache ..
stuw %r12, [%r27-0] ! Load common dest into dcache ..
ba,a .+12
.word 0xe1e7c540 ! 1: CASA_I casa [%r31] 0x2a, %r0, %r16
ba,a .+8
jmpl %r27-4, %r27
.word 0x95702dba ! 553: POPC_I popc 0x0dba, %r10
nop
nop
ta T_CHANGE_HPRIV
mov 0x1, %r11
splash_cmpr_1_298:
sllx %r11, 63, %r11
not %r11, %r11
rd %tick, %r10
#if (defined SPC || defined CMP1)
add %r10, 0x100, %r10
#else
add %r10, 0x550, %r10
#endif
and %r10, %r11, %r10
wrhpr %r10, %g0, %hsys_tick_cmpr
wrhpr %g0, 0x0, %halt ! HALT
ta T_CHANGE_PRIV
rd %tick, %r10
#if (defined SPC || defined CMP1)
add %r10, 0x250, %r10
#else
add %r10, 0x380, %r10
#endif
and %r10, %r11, %r10
.word 0xaf80000a ! 1: WR_TICK_CMPR_REG_R wr %r0, %r10, %-
#if (defined SPC || defined CMP1)
!$EV trig_pc_d(1, expr(@VA(.MAIN.splash_cmpr_1_298)+8 , 16, 16)) -> intp(4,0,15,*,936,*,4b,1)
!$EV trig_pc_d(1, expr((@VA(.MAIN.splash_cmpr_1_298)&0xffffffff)+8 , 16, 16)) -> intp(4,0,18,*,992,*,4b,1)
#endif
wrhpr %g0, 0x0, %halt ! HALT
.word 0x81983f1b ! 1: WRHPR_HPSTATE_I wrhpr %r0, 0x1f1b, %hpstate
.word 0x81b01021 ! 557: SIAM siam 1
.word 0x8980000a ! 561: WRTICK_R wr %r0, %r10, %tick
cancelint_1_302:
rdhpr %halt, %r9
.word 0x85880000 ! 565: ALLCLEAN <illegal instruction>
nop
nop
set 0x1910476e, %r28 !TTID : 7 (mask2tid(0x1))
#if (defined PORTABLE_CORE || MAX_THREADS == 8)
sethi %hi(0x3800), %r27
andn %r28, %r27, %r28
#ifdef PORTABLE_CORE
! Add CID to vector
ta T_CHANGE_HPRIV
ldxa [%g0]0x63, %r27
sllx %r27, 8, %r27
or %r27, %r28, %r28
#endif
#else
! Add CID IF tid matches
ifelse(7,mask2tid(0x1),`ta T_CHANGE_HPRIV;sethi %hi(0x3800), %r27;andn %r28, %r27, %r28;ldxa [%g0]0x63, %r27;sllx %r27, 8, %r27;or %r27, %r28, %r28 ')
#endif
sethi %hi(0x30000), %r27
andn %r28, %r27, %r28
ta T_CHANGE_HPRIV
ifelse(7,mask2tid(0x1),`.align 16')
stxa %r28, [%g0] 0x73
intvec_1_305:
.word 0xa3a489c6 ! 569: FDIVd fdivd %f18, %f6, %f48
.word 0xe2cfd140 ! 573: LDSBA_R ldsba [%r31, %r0] 0x8a, %r17
.word 0xa190200a ! 577: WRPR_GL_I wrpr %r0, 0x000a, %-
nop
nop
set 0x8950e46e, %r28 !TTID : 4 (mask2tid(0x1))
#if (defined PORTABLE_CORE || MAX_THREADS == 8)
sethi %hi(0x3800), %r27
andn %r28, %r27, %r28
#ifdef PORTABLE_CORE
! Add CID to vector
ta T_CHANGE_HPRIV
ldxa [%g0]0x63, %r27
sllx %r27, 8, %r27
or %r27, %r28, %r28
#endif
#else
! Add CID IF tid matches
ifelse(4,mask2tid(0x1),`ta T_CHANGE_HPRIV;sethi %hi(0x3800), %r27;andn %r28, %r27, %r28;ldxa [%g0]0x63, %r27;sllx %r27, 8, %r27;or %r27, %r28, %r28 ')
#endif
sethi %hi(0x30000), %r27
andn %r28, %r27, %r28
ta T_CHANGE_HPRIV
ifelse(4,mask2tid(0x1),`.align 16')
stxa %r28, [%g0] 0x73
intvec_1_309:
.word 0x39400002 ! 581: FBPUGE fbuge,a,pn %fcc0, <label_0x2>
trapasi_1_313:
nop
mov 0x10, %r1 ! (VA for ASI 0x5b)
.word 0xe2d84b60 ! 585: LDXA_R ldxa [%r1, %r0] 0x5b, %r17
.word 0xe277e040 ! 589: STX_I stx %r17, [%r31 + 0x0040]
iaw_1_317:
nop
nop
ta T_CHANGE_HPRIV
mov 8, %r18
rd %asi, %r12
wr %r0, 0x41, %asi
set sync_thr_counter4, %r23
#ifndef SPC
ldxa [%g0]0x63, %r8
and %r8, 0x38, %r8 ! Core ID
#ifndef PORTABLE_CORE
add %r8, %r23, %r23
#endif
#else
mov 0, %r8
#endif
mov 0x1, %r16
iaw_startwait1_317:
cas [%r23],%g0,%r16 !lock
brz,a %r16, continue_iaw_1_317
mov (~0x1&0xf), %r16
ld [%r23], %r16
iaw_wait1_317:
brnz %r16, iaw_wait1_317
ld [%r23], %r16
ba iaw_startwait1_317
mov 0x1, %r16
continue_iaw_1_317:
sllx %r16, %r8, %r16 !Mask for my core only
ldxa [0x58]%asi, %r17 !Running_status
wait_for_stat_1_317:
ldxa [0x50]%asi, %r13 !Running_rw
cmp %r13, %r17
bne,a %xcc, wait_for_stat_1_317
ldxa [0x58]%asi, %r17 !Running_status
stxa %r16, [0x68]%asi !Park (W1C)
ldxa [0x50]%asi, %r14 !Running_rw
wait_for_iaw_1_317:
ldxa [0x58]%asi, %r17 !Running_status
cmp %r14, %r17
bne,a %xcc, wait_for_iaw_1_317
ldxa [0x50]%asi, %r14 !Running_rw
iaw_doit1_317:
mov 0x38, %r18
iaw3_1_317:
setx vahole_target1, %r20, %r19
or %r19, 0x1, %r19
stxa %r19, [%r18]0x50
stxa %r16, [0x60] %asi ! Unpark (W1S)
st %g0, [%r23] !clear lock
wr %r0, %r12, %asi ! restore %asi
wrhpr %g0, 0xb9b, %hpstate ! ta T_CHANGE_NONHPRIV
.word 0xc1bfdf00 ! 593: STDFA_R stda %f0, [%r0, %r31]
.word 0x8d902afb ! 597: WRPR_PSTATE_I wrpr %r0, 0x0afb, %pstate
splash_lsu_1_322:
nop
nop
ta T_CHANGE_HPRIV
set 0x49a5d56a, %r2
mov 0x7, %r1
sllx %r1, 32, %r1
or %r1, %r2, %r2
.word 0x2b400002 ! 1: FBPUG fbug,a,pn %fcc0, <label_0x2>
stxa %r2, [%r0] ASI_LSU_CONTROL
.word 0x3d400001 ! 601: FBPULE fbule,a,pn %fcc0, <label_0x1>
.word 0x8980000a ! 605: WRTICK_R wr %r0, %r10, %tick
.word 0xe23fe1c0 ! 609: STD_I std %r17, [%r31 + 0x01c0]
jmptr_1_328:
nop
nop
best_set_reg(0xe1200000, %r20, %r27)
.word 0xb7c6c000 ! 613: JMPL_R jmpl %r27 + %r0, %r27
intveclr_1_330:
nop
nop
ta T_CHANGE_HPRIV
setx 0xa391b51b2fd83de7, %r1, %r28
stxa %r28, [%g0] 0x72
wrhpr %g0, 0x643, %hpstate ! ta T_CHANGE_NONHPRIV
.word 0x25400001 ! 617: FBPLG fblg,a,pn %fcc0, <label_0x1>
pmu_1_332:
nop
nop
setx 0xffffffbaffffffa9, %g1, %g7
.word 0xa3800007 ! 621: WR_PERF_COUNTER_R wr %r0, %r7, %-
.word 0x87802016 ! 625: WRASI_I wr %r0, 0x0016, %asi
splash_tba_1_337:
nop
ta T_CHANGE_PRIV
setx 0x0000000000380000, %r11, %r12
.word 0x8b90000c ! 629: WRPR_TBA_R wrpr %r0, %r12, %tba
#if (defined SPC || defined CMP1)
!$EV trig_pc_d(1, expr(@VA(.MAIN.intvec_1_338) , 16, 16)) -> intp(6,0,31,*,648,*,a3,1)
!$EV trig_pc_d(1, expr((@VA(.MAIN.intvec_1_338)&0xffffffff) , 16, 16)) -> intp(5,0,18,*,1016,*,a3,1)
#else
nop
nop
set 0x1c305c04, %r28 !TTID : 4 (mask2tid(0x1))
#if (defined PORTABLE_CORE || MAX_THREADS == 8)
sethi %hi(0x3800), %r27
andn %r28, %r27, %r28
#ifdef PORTABLE_CORE
! Add CID to vector
ta T_CHANGE_HPRIV
ldxa [%g0]0x63, %r27
sllx %r27, 8, %r27
or %r27, %r28, %r28
#endif
#else
! Add CID IF tid matches
ifelse(4,mask2tid(0x1),`ta T_CHANGE_HPRIV;sethi %hi(0x3800), %r27;andn %r28, %r27, %r28;ldxa [%g0]0x63, %r27;sllx %r27, 8, %r27;or %r27, %r28, %r28 ')
#endif
ifelse(4,mask2tid(0x1),`.align 16')
stxa %r28, [%g0] 0x73
#endif
intvec_1_338:
#if (defined SPC || defined CMP1)
wrhpr %g0, 0x0, %halt ! HALT
#else
ifelse(4,mask2tid(0x1),`wrhpr %g0, 0x0, %halt ! HALT')
#endif
.word 0x95b204cd ! 633: FCMPNE32 fcmpne32 %d8, %d44, %r10
br_longdelay3_1_340:
nop
not %g0, %r27
jmpl %r27+0, %r27
.word 0x8d902c56 ! 637: WRPR_PSTATE_I wrpr %r0, 0x0c56, %pstate
intveclr_1_343:
nop
nop
ta T_CHANGE_HPRIV
setx 0x8519b89ce6f6b702, %r1, %r28
stxa %r28, [%g0] 0x72
wrhpr %g0, 0x452, %hpstate ! ta T_CHANGE_NONHPRIV
.word 0x25400001 ! 641: FBPLG fblg,a,pn %fcc0, <label_0x1>
ibp_1_344:
nop
nop
.word 0x20800001 ! 645: BN bn,a <label_0x1>
.word 0xd43fe03c ! 649: STD_I std %r10, [%r31 + 0x003c]
.word 0xd497d060 ! 653: LDUHA_R lduha [%r31, %r0] 0x83, %r10
jmptr_1_353:
nop
nop
best_set_reg(0xe0200000, %r20, %r27)
.word 0xb7c6c000 ! 657: JMPL_R jmpl %r27 + %r0, %r27
.word 0xd497d040 ! 661: LDUHA_R lduha [%r31, %r0] 0x82, %r10
.word 0xc19fe120 ! 665: LDDFA_I ldda [%r31, 0x0120], %f0
.word 0xd4bfd000 ! 1: STDA_R stda %r10, [%r31 + %r0] 0x80
.word 0xc32fc000 ! 1: STXFSR_R st-sfr %f1, [%r0, %r31]
mov 0x35, %r30
.word 0x83d0001e ! 669: Tcc_R te icc_or_xcc, %r0 + %r30
demap_1_359:
nop
mov 0x80, %g3
ta T_CHANGE_HPRIV
stxa %g3, [%g3] 0x57
.word 0xe1bfdb20 ! 1: STDFA_R stda %f16, [%r0, %r31]
.word 0xc19fdc00 ! 1: LDDFA_R ldda [%r31, %r0], %f0
.word 0xe09fc3e0 ! 1: LDDA_R ldda [%r31, %r0] 0x1f, %r16
stxa %g3, [%g3] 0x57
.word 0xc19fc2c0 ! 1: LDDFA_R ldda [%r31, %r0], %f0
.word 0xe09fdc40 ! 1: LDDA_R ldda [%r31, %r0] 0xe2, %r16
.word 0xe1bfdb40 ! 1: STDFA_R stda %f16, [%r0, %r31]
stxa %g3, [%g3] 0x5f
.word 0xc0bfde20 ! 1: STDA_R stda %r0, [%r31 + %r0] 0xf1
stxa %g3, [%g3] 0x57
wrhpr %g0, 0x54a, %hpstate ! ta T_CHANGE_NONHPRIV
.word 0xd41fe15a ! 673: LDD_I ldd [%r31 + 0x015a], %r10
memptr_1_362:
set 0x60340000, %r31
.word 0x8584792c ! 677: WRCCR_I wr %r17, 0x192c, %ccr
jmptr_1_363:
nop
nop
best_set_reg(0xe1200000, %r20, %r27)
.word 0xb7c6c000 ! 681: JMPL_R jmpl %r27 + %r0, %r27
jmptr_1_366:
nop
nop
best_set_reg(0xe0200000, %r20, %r27)
.word 0xb7c6c000 ! 685: JMPL_R jmpl %r27 + %r0, %r27
memptr_1_369:
set user_data_start, %r31
.word 0x8580b6b1 ! 689: WRCCR_I wr %r2, 0x16b1, %ccr
nop
nop
ta T_CHANGE_HPRIV ! macro
donret_1_370:
rd %pc, %r12
mov HIGHVA_HIGHNUM, %r10
sllx %r10, 32, %r10
or %r12, %r10, %r12
add %r12, (donretarg_1_370-donret_1_370+4), %r12
add %r12, 0x4, %r11 ! seq tnpc
wrpr %g0, 0x1, %tl
wrpr %g0, %r12, %tpc
wrpr %g0, %r11, %tnpc
set (0x002f9c00 | (22 << 24)), %r13
and %r12, 0xfff, %r14
sllx %r14, 32, %r14
or %r13, %r14, %r20
wrpr %r20, %g0, %tstate
wrhpr %g0, 0x85, %htstate
wrhpr %g0, 0x7c0, %hpstate ! rand=1 (1)
ldx [%r12+%r0], %g1
retry
donretarg_1_370:
.word 0xd46fe17a ! 693: LDSTUB_I ldstub %r10, [%r31 + 0x017a]
brcommon3_1_371:
nop
nop
setx common_target, %r12, %r27
lduw [%r27-4], %r12 ! Load common dest into dcache ..
stuw %r12, [%r27-4] ! Load common dest into dcache ..
ba,a .+12
.word 0xd537e160 ! 1: STQF_I - %f10, [0x0160, %r31]
ba,a .+8
jmpl %r27-0, %r27
.word 0xd4dfc2c0 ! 697: LDXA_R ldxa [%r31, %r0] 0x16, %r10
.word 0xd477c000 ! 701: STX_R stx %r10, [%r31 + %r0]
.word 0xd537c000 ! 705: STQF_R - %f10, [%r0, %r31]
.word 0xc32fc000 ! 709: STXFSR_R st-sfr %f1, [%r0, %r31]
.word 0x91930001 ! 713: WRPR_PIL_R wrpr %r12, %r1, %pil
.word 0xd48008a0 ! 717: LDUWA_R lduwa [%r0, %r0] 0x45, %r10
.word 0xd527e0cc ! 721: STF_I st %f10, [0x00cc, %r31]
intveclr_1_383:
nop
nop
ta T_CHANGE_HPRIV
setx 0xdea5c2c376b07339, %r1, %r28
stxa %r28, [%g0] 0x72
.word 0x25400001 ! 725: FBPLG fblg,a,pn %fcc0, <label_0x1>
demap_1_386:
nop
mov 0x80, %g3
ta T_CHANGE_HPRIV
stxa %g3, [%g3] 0x5f
stxa %g3, [%g3] 0x5f
.word 0xe19fc2c0 ! 1: LDDFA_R ldda [%r31, %r0], %f16
.word 0xe1bfda60 ! 1: STDFA_R stda %f16, [%r0, %r31]
.word 0xc1bfdb40 ! 1: STDFA_R stda %f0, [%r0, %r31]
stxa %g3, [%g3] 0x57
wrhpr %g0, 0xf08, %hpstate ! ta T_CHANGE_NONHPRIV
.word 0xd41fe02c ! 729: LDD_I ldd [%r31 + 0x002c], %r10
.word 0xd4bfe192 ! 733: STDA_I stda %r10, [%r31 + 0x0192] %asi
memptr_1_389:
set 0x60540000, %r31
.word 0x8584ab10 ! 737: WRCCR_I wr %r18, 0x0b10, %ccr
.word 0x8980000a ! 741: WRTICK_R wr %r0, %r10, %tick
.word 0xd5e7c3c0 ! 745: CASA_I casa [%r31] 0x1e, %r0, %r10
splash_lsu_1_393:
nop
nop
ta T_CHANGE_HPRIV
set 0xb9ac7ca2, %r2
mov 0x2, %r1
sllx %r1, 32, %r1
or %r1, %r2, %r2
stxa %r2, [%r0] ASI_LSU_CONTROL
.word 0x3d400001 ! 749: FBPULE fbule,a,pn %fcc0, <label_0x1>
br_longdelay4_1_395:
nop
not %g0, %r27
jmpl %r27+0, %r27
.word 0x9d902004 ! 753: WRPR_WSTATE_I wrpr %r0, 0x0004, %wstate
brcommon3_1_399:
nop
nop
setx common_target, %r12, %r27
lduw [%r27-0], %r12 ! Load common dest into dcache ..
stuw %r12, [%r27-0] ! Load common dest into dcache ..
ba,a .+12
.word 0xd46fe000 ! 1: LDSTUB_I ldstub %r10, [%r31 + 0x0000]
ba,a .+8
jmpl %r27-4, %r27
.word 0x95b7c7c0 ! 757: PDIST pdistn %d62, %d0, %d10
.word 0xd5e7c3c0 ! 761: CASA_I casa [%r31] 0x1e, %r0, %r10
nop
nop
ta T_CHANGE_HPRIV
mov 0x1, %r11
splash_cmpr_1_403:
sllx %r11, 63, %r11
not %r11, %r11
rd %tick, %r10
#if (defined SPC || defined CMP1)
add %r10, 0x100, %r10
#else
add %r10, 0x550, %r10
#endif
and %r10, %r11, %r10
wrhpr %r10, %g0, %hsys_tick_cmpr
wrhpr %g0, 0x0, %halt ! HALT
ta T_CHANGE_PRIV
rd %tick, %r10
#if (defined SPC || defined CMP1)
add %r10, 0x200, %r10
#else
add %r10, 0x380, %r10
#endif
and %r10, %r11, %r10
.word 0xaf80000a ! 1: WR_TICK_CMPR_REG_R wr %r0, %r10, %-
#if (defined SPC || defined CMP1)
!$EV trig_pc_d(1, expr(@VA(.MAIN.splash_cmpr_1_403)+8 , 16, 16)) -> intp(1,0,21,*,744,*,eb,1)
!$EV trig_pc_d(1, expr((@VA(.MAIN.splash_cmpr_1_403)&0xffffffff)+8 , 16, 16)) -> intp(0,0,10,*,1000,*,eb,1)
#endif
wrhpr %g0, 0x0, %halt ! HALT
.word 0x81983c45 ! 1: WRHPR_HPSTATE_I wrhpr %r0, 0x1c45, %hpstate
.word 0x81b01021 ! 765: SIAM siam 1
memptr_1_407:
set 0x60540000, %r31
.word 0x8584a12a ! 769: WRCCR_I wr %r18, 0x012a, %ccr
br_badelay3_1_410:
.word 0x20800001 ! 1: BN bn,a <label_0x1>
.word 0xdf6065bb ! Random illegal ?
.word 0xe1130004 ! 1: LDQF_R - [%r12, %r4], %f16
.word 0x93a50834 ! 773: FADDs fadds %f20, %f20, %f9
splash_lsu_1_411:
nop
nop
ta T_CHANGE_HPRIV
set 0x8c5d7eef, %r2
mov 0x2, %r1
sllx %r1, 32, %r1
or %r1, %r2, %r2
stxa %r2, [%r0] ASI_LSU_CONTROL
ta T_CHANGE_NONHPRIV
.word 0x3d400002 ! 777: FBPULE fbule,a,pn %fcc0, <label_0x2>
.word 0x26800001 ! 781: BL bl,a <label_0x1>
pmu_1_417:
nop
nop
ta T_CHANGE_PRIV
setx 0xffffffb7ffffffa9, %g1, %g7
.word 0xa3800007 ! 785: WR_PERF_COUNTER_R wr %r0, %r7, %-
.word 0x81460000 ! 789: RD_STICK_REG stbar
demap_1_421:
nop
mov 0x80, %g3
ta T_CHANGE_HPRIV
.word 0x32800001 ! 1: BNE bne,a <label_0x1>
stxa %g3, [%g3] 0x5f
.word 0xe1bfde00 ! 1: STDFA_R stda %f16, [%r0, %r31]
.word 0xe1bfdb20 ! 1: STDFA_R stda %f16, [%r0, %r31]
stxa %g3, [%g3] 0x57
.word 0xc19fde00 ! 1: LDDFA_R ldda [%r31, %r0], %f0
stxa %g3, [%g3] 0x5f
.word 0xe19fdf00 ! 1: LDDFA_R ldda [%r31, %r0], %f16
stxa %g3, [%g3] 0x57
.word 0xc0bfde20 ! 1: STDA_R stda %r0, [%r31 + %r0] 0xf1
wrhpr %g0, 0xfd2, %hpstate ! ta T_CHANGE_NONHPRIV
.word 0xd21fe024 ! 793: LDD_I ldd [%r31 + 0x0024], %r9
memptr_1_424:
set 0x60540000, %r31
.word 0x8584eaf2 ! 797: WRCCR_I wr %r19, 0x0af2, %ccr
nop
nop
ta T_CHANGE_PRIV
wrpr %g0, %g0, %gl
nop
nop
join_lbl_0_0:
SECTION .MAIN
.text
diag_finish:
nop
nop
nop
ta T_CHANGE_HPRIV
#ifndef SPC
ldxa [%g0]0x63, %r8
and %r8, 0x38, %r8 ! Core ID
#else
mov %g0, %r8
#endif
!! Send interrupt to all threads in my core in case of halted threads.
intall_nomast:
mov 7, %r14
intall_loop_nomast:
add %r8, %r14, %r16
sllx %r16, 8, %r16
stxa %r16, [%g0]0x73
brnz %r14, intall_loop_nomast
dec %r14
#if (MULTIPASS > 0)
multipass_check:
rd %asi, %r12
wr %g0, ASI_SCRATCHPAD, %asi
ldxa [0x38]%asi, %r10
cmp %r10, MULTIPASS
inc %r10
stxa %r10, [0x38]%asi
wr %g0, %r12, %asi
bne fork_threads
wrpr %g0, %g0, %gl
#endif
finish_diag:
best_set_reg(HV_TRAP_BASE_PA, %r1, %r2)
wrhpr %g2, %g0, %htba
ta T_GOOD_TRAP
nop
nop
nop
.data
.xword 0x0
! fp data rs1, rs2, fsr, gsr quads ..
.global fp_data_quads
fp_data_quads:
.xword 0x0044000000000000
.xword 0x4028000000000000
.xword 0x0fc0400400000000
.xword 0x0000000000000000
.xword 0x0041000000000000
.xword 0x4022000000000000
.xword 0x0600800000000000
.xword 0x0000000000000000
.xword 0x0220000000000000
.xword 0x4140000000000000
.xword 0x4fc0400400000000
.xword 0x0000000000000000
.xword 0x4090000000000000
.xword 0x0090000000000000
.xword 0x0f80400800000000
.xword 0x0a00000000000000
.align 128
.global user_data_start
.data
user_data_start:
.xword 0x4f4f7050c20bcab9
.xword 0xdce207b00279a4a7
.xword 0x06763674b6b807cd
.xword 0xbc0723dbf8e2e0db
.xword 0x5afd8879e1e7a36b
.xword 0xca700606da1370af
.xword 0x15ee0139b41d3fb1
.xword 0xe49e127fc9b1f4e0
.xword 0xa97863c4c80df84d
.xword 0x269e20ac96787414
.xword 0x336e2d24c32aa370
.xword 0x435f89ea876e273a
.xword 0xaae515cebdd4bbe3
.xword 0x2fb569b735ada46b
.xword 0x53c3af4f2ff84eba
.xword 0x03ca34468a39639e
.xword 0xc8a302633c83780e
.xword 0x4d5a8e09654b0ce3
.xword 0xaf05bc3ec0843a23
.xword 0xafcff45c52daa4ef
.xword 0x11274eeb3b8e256a
.xword 0x1b5952e6aac255c5
.xword 0x2f864cdaf8442389
.xword 0x0dd8700a9631b831
.xword 0xf7e1388d121bc424
.xword 0xedffef985e73cf89
.xword 0xf2887a3f7862b75f
.xword 0x472801da5b6092b0
.xword 0xed079af22c21092e
.xword 0xe638d0ad2163e016
.xword 0xe9930db254dd495a
.xword 0x5f65efeedc3f6c6e
.xword 0xce36bad729961448
.xword 0xd5bae52403dc65f5
.xword 0x2847a08b645077e3
.xword 0x33b411d21f8c86d6
.xword 0x326f1fc03e519d96
.xword 0x6165d98621a8934f
.xword 0x6c46ec5e35216674
.xword 0x677c3264706f4f65
.xword 0x6ab94b67e433f8e4
.xword 0x27d5a1da3f88028e
.xword 0x4235dfaf8d70fc61
.xword 0xf05b7605a32fbc26
.xword 0xd834467c0242b95f
.xword 0x956332f331b05a21
.xword 0xa0ac06b21de68c13
.xword 0x8e866238b2210ed1
.xword 0x8a847c4eb2025a0b
.xword 0x9ddb0d60bdede9f7
.xword 0x17c6dc29fdc413cd
.xword 0x28c5418e8728b56d
.xword 0x127076b17f244227
.xword 0x0c33566bc39eb31a
.xword 0xf237ab361675a3aa
.xword 0x0cacffb1332673ca
.xword 0xbd63aa96712957f1
.xword 0x6ab466e0bde91b32
.xword 0x1fb58274e66cb730
.xword 0x18b08b0633d8381e
.xword 0xcdc642c258c3fc94
.xword 0x071e04805f65e5f9
.xword 0x66f5598714788121
.xword 0xbbaab3bf929a0c93
.xword 0x4740e0c6b4c9fa5c
.xword 0x759328f6ad4b1263
.xword 0x9abd483970e4d8fa
.xword 0xace73ae2a6ba3ab6
.xword 0xdf286ad9102253c5
.xword 0x3479aa9c208b3417
.xword 0x79980e488a265d22
.xword 0x720885b38cd89f71
.xword 0x48dc8b69fe035ecc
.xword 0x665fde5a786de752
.xword 0x4ac214259e024688
.xword 0xca223ea65ae01f80
.xword 0x65f8b4ebb99013d4
.xword 0x49afccf3c653a3f3
.xword 0x101c1b9255580f99
.xword 0xa93936b4b3389ecf
.xword 0xa83d6398a0e642d6
.xword 0xd940bf95e107a71d
.xword 0x89536ab36f80010e
.xword 0x061f7b7dad71fbed
.xword 0xaef1e978cfa4ec6c
.xword 0x46f2f1430a4d18e0
.xword 0x8a64d5ee8e25f426
.xword 0xd0bbec45baf730b4
.xword 0x1225d63401bdccef
.xword 0xca513ff67aa7b8df
.xword 0xdd27575c582c5318
.xword 0xd6debef679d7e536
.xword 0x35f31d1d65792aa8
.xword 0x03a5c55f7319d769
.xword 0x591c4b06b52401b2
.xword 0x6e1038edab7d5738
.xword 0x9edb5fe261cad2bf
.xword 0xd1ce9ac730af0620
.xword 0x98a56a8577a9bb21
.xword 0x1e491ddd40e1f61f
.xword 0x0a4c8d181cfef94e
.xword 0xc4e9aaba8cb36e98
.xword 0x2f087bb9feefa02b
.xword 0xac0f5912078c0e15
.xword 0x529e80b7a815f1e5
.xword 0xe1a3bd4874319101
.xword 0x9a024720350bd6d3
.xword 0x71cc1050bfa90749
.xword 0x439d598e243d8a1d
.xword 0x148a9b30545c0b54
.xword 0x58d29bb8c3e6881e
.xword 0xbcbe07350065aed4
.xword 0x8e9597c85d824cb8
.xword 0x63b31bca8dab3777
.xword 0x3d7fad70514705d7
.xword 0x1cfeace527add4e9
.xword 0x19906d9529a6d9b1
.xword 0x157075c24a44addb
.xword 0x717418e2c5d39990
.xword 0x812c62356a8f66cc
.xword 0x978b1670c4a8181d
.xword 0x132609b5a253b28e
.xword 0x50a60a2c9f100f8a
.xword 0x78ea45d32cb2e410
.xword 0xfd368b1003161ea2
.xword 0x0822b870a5dbddb8
.xword 0xe1b18e3cffac461d
.xword 0xe2bd9c682563a966
.xword 0x1b5e3c69ea867b91
.xword 0x8f8acfb7772c7d2a
.xword 0xef1695e22561ac59
.xword 0x7d4f257a2d684a18
.xword 0xcd966e4f5149acd0
.xword 0xdc6071334aa4a089
.xword 0x81be46b1b48e0319
.xword 0x2ae28bbee71026ca
.xword 0xd3200b54aa4668e7
.xword 0x0e2cc57aaadfb53a
.xword 0x79a72619def94b29
.xword 0xa6f6e71bd4596659
.xword 0xf9897980ca3e9990
.xword 0x792f7bb7e348c3e0
.xword 0xedf428f7e7259233
.xword 0x01ad056950359a27
.xword 0x70338846fe24ec13
.xword 0x60649a01bb3b113b
.xword 0x52c9ec200f03b6ef
.xword 0x91b811f7c19f20c5
.xword 0xe00d27827b792b1e
.xword 0x42130a266bfb08e4
.xword 0x42562dc8487bdee8
.xword 0x41829640178a17ea
.xword 0xb542d9589f3e478b
.xword 0x875739f29ef8c924
.xword 0xba8a7af0ac834b65
.xword 0x4f389fa69db8a599
.xword 0x0dedddebdbc7c8e8
.xword 0xc7743f36cee5b701
.xword 0xebee51c2b7d5e53c
.xword 0x9763ce58d44d785d
.xword 0x9f41752338142374
.xword 0xc108c8ced36b738d
.xword 0xcb22363fbcf14587
.xword 0xbab5a2ab64a8b06f
.xword 0x4eabeb69a57cd87b
.xword 0x100972935a8b6971
.xword 0x89011d873461f5d6
.xword 0x82d72a43cd6fcc12
.xword 0x24dde296d726c47c
.xword 0xf7b06368f1379816
.xword 0xc09b710d56e4e34d
.xword 0x4b76f50774b16350
.xword 0x32554d69cdd2bd2d
.xword 0x9ec8abe8c5912726
.xword 0x2d39005968aba717
.xword 0x0c1b312a29e27e76
.xword 0xfd90e1887e19d79a
.xword 0x9e7fd84983edbad8
.xword 0x4de7133281d6951f
.xword 0x12acc5b10bbfaace
.xword 0x264a2e8665cae473
.xword 0xfc2458e68167029c
.xword 0x2ad87f76bfce8a55
.xword 0x0372d382fb25fae2
.xword 0xaf612fac35e3e64f
.xword 0x00d1c7d915a8ca01
.xword 0x8529ab549918e239
.xword 0xc5b09f6debb28cd2
.xword 0xea5bc98934ecb3ac
.xword 0xb877dba3d2adc48c
.xword 0x206254e3612c55d4
.xword 0xd1fecaa4c43e1823
.xword 0xff2663ffe915da72
.xword 0xf96364023c40a47c
.xword 0xbf11bab908162a6b
.xword 0x49472d5a5cb1fccd
.xword 0x6a7e868e6c8410c6
.xword 0xac4422ba62f7891d
.xword 0xf26be4bf21e6aa21
.xword 0x373381850148e530
.xword 0x86649745858f2468
.xword 0xc25abacd98c2a842
.xword 0x47654b6f8b7bcf89
.xword 0x5356bc7279d619dc
.xword 0x51ba72e579df592a
.xword 0x8c5c4e471e44b22e
.xword 0xe55fb722c74b14c8
.xword 0x188a2794594edbdb
.xword 0x2263296f43dede86
.xword 0x10ac48575c0c5012
.xword 0x2a880969665bf9ab
.xword 0x86b34913d7e557b8
.xword 0x2a53c1eb0426f160
.xword 0xea89fbb395fdf218
.xword 0xef1536c03cdfceaf
.xword 0x0f1747853e0c6cde
.xword 0xcbdcb806b2b0acb5
.xword 0x1914b532d56a1287
.xword 0x49fb4990296ec340
.xword 0x20b5487ebf1cdc28
.xword 0xe5938535fe7da981
.xword 0x7158626a2d2d2c5f
.xword 0x087111d86f21f2b2
.xword 0x709fe80d516b2417
.xword 0xdce9f0ed15ea65d5
.xword 0x836d2110f20f0b92
.xword 0xd2e42887f21a56af
.xword 0x295374301ca83848
.xword 0x43ccf07aa862f36b
.xword 0x52816d893f061968
.xword 0x8f00fc00ec13aa71
.xword 0xde30e3ac18e78c5a
.xword 0x689df9a6768383c5
.xword 0x9eecbf00e1cef8de
.xword 0x008038c36cca53e6
.xword 0x584ad421eca4b722
.xword 0xec4d9ef18f1ef6fa
.xword 0xc729933a64d673e9
.xword 0x270b21462d916c23
.xword 0xf03d40ba13accaeb
.xword 0x3424da7bc02192b7
.xword 0xceaaeb316e730cf0
.xword 0x573ec7ba1cde0b13
.xword 0x1b0b0118659e0755
.xword 0xa0f1c541c26a70b3
.xword 0x06d0813dcd5a5289
.xword 0x0af4d99e34f5bc40
.xword 0xdec468bb19603097
.xword 0xaedce853c873ab06
.xword 0xccc9af8ff92502c7
.xword 0xb6a34702e09c0eed
.xword 0x62fcbf87704973fc
.xword 0x99fbe3457bf57b66
.xword 0x3ea35aa47f8c402a
.xword 0x34cfa56ca3f81107
.xword 0x2b2cd2cf7bb47452
SECTION .HTRAPS
.text
.global restore_range_regs
restore_range_regs:
wr %g0, ASI_MMU_REAL_RANGE, %asi
mov 1, %g1
sllx %g1, 63, %g1
ldxa [ASI_MMU_REAL_RANGE_0] %asi, %g2
or %g2 ,%g1, %g2
stxa %g2, [ASI_MMU_REAL_RANGE_0] %asi
ldxa [ASI_MMU_REAL_RANGE_1] %asi, %g2
or %g2 ,%g1, %g2
stxa %g2, [ASI_MMU_REAL_RANGE_1] %asi
ldxa [ASI_MMU_REAL_RANGE_2] %asi, %g2
or %g2 ,%g1, %g2
stxa %g2, [ASI_MMU_REAL_RANGE_2] %asi
ldxa [ASI_MMU_REAL_RANGE_3] %asi, %g2
or %g2 ,%g1, %g2
stxa %g2, [ASI_MMU_REAL_RANGE_3] %asi
retry
.global wdog_2_ext
SECTION .HTRAPS
.global wdog_2_ext
.global retry_with_base_tba
.global resolve_bad_tte
.text
resolve_bad_tte:
!if pc[63:15] matches tba, then relocated handler ..
rdpr %tpc, %r4
check_tba:
set 0x7fff, %r5
andn %r4, %r5, %r5 !clear 14:0
rdpr %tba, %r6 !compare pc[63:15] to tba
cmp %r5, %r6
bne,a not_a_reloc_handler
andn %r27, 0x1f, %r6
retry_with_base_tba:
best_set_reg(TRAP_BASE_VA, %r3, %r5)
cmp %r4, %r5
bz htrap_5_ext_done
set 0x7fff, %r3
and %r4, %r3, %r4
or %r5, %r4, %r4
wrpr %r4, %tpc
rdpr %tnpc, %r4
and %r4, %r3, %r4
or %r5, %r4, %r4
wrpr %r4, %tnpc
retry
!assume %r27 is where we came from ..
not_a_reloc_handler:
stxa %r27, [%r6] 0x57
add %r27, 8, %r27
wrpr %r27, %tnpc
done
htrap_5_ext:
rd %pc, %l2
inc %l3
add %l2, htrap_5_ext_done-htrap_5_ext, %l2
rdpr %tl, %l3
rdpr %tstate, %l4
rdhpr %htstate, %l5
or %l5, 0x4, %l5
inc %l3
wrpr %l3, %tl
wrpr %l2, %tpc
add %l2, 4, %l2
wrpr %l2, %tnpc
wrpr %l4, %tstate
wrhpr %l5, %htstate
retry
htrap_5_ext_done:
done
wdog_2_ext:
mov 0x1f, %l1
stxa %l1, [%g0] ASI_LSU_CTL_REG
! If TT != 2, then goto trap handler
rdpr %tt, %l1
cmp %l1, 0x2
bne wdog_2_goto_handler
nop
! else done
done
wdog_2_goto_handler:
rdhpr %htstate, %l3
and %l3, 0x4, %l3 ! If previously in hpriv mode, go to hpriv
brnz,a %l3, wdog_2_goto_handler_1
rdhpr %htba, %l3
srlx %l1, 7, %l3 ! Send priv sw traps to priv mode ..
cmp %l3, 0x2 ! 0x2 = priv sw trap, 0x3=hpriv sw trap ..
be,a wdog_2_goto_handler_1
rdpr %tba, %l3
rdhpr %htba, %l3
wdog_2_goto_handler_1:
sllx %l1, 5, %l1
add %l1, %l3, %l3
jmp %l3
nop
! Red mode other reset handler
! Get htba, and tt and make trap address
! Jump to trap handler ..
SECTION .RED_SEC
.global red_other_ext
.global wdog_red_ext
.text
red_other_ext:
! IF TL=6, shift stack by one ..
rdpr %tl, %l1
cmp %l1, 6
be start_tsa_shift
nop
continue_red_other:
mov 0x1f, %l1
stxa %l1, [%g0] ASI_LSU_CTL_REG
rdpr %tt, %l1
rdhpr %htstate, %l2
and %l2, 0x4, %l2 ! If previously in hpriv mode, go to hpriv
brnz,a %l2, red_goto_handler
rdhpr %htba, %l2
srlx %l1, 7, %l2 ! Send priv sw traps to priv mode ..
cmp %l2, 0x2 ! 0x2 = priv sw trap, 0x3=hpriv sw trap ..
be,a red_goto_handler
rdpr %tba, %l2
rdhpr %htba, %l2
red_goto_handler:
sllx %l1, 5, %l1
add %l1, %l2, %l2
rdhpr %htstate, %l1
andn %l1, 0x20, %l1
wrhpr %g0, %l1, %htstate
rdhpr %hpstate, %l1
jmp %l2
wrhpr %l1, 0x20, %hpstate
nop
wdog_red_ext:
! Shift stack down by 1 ...
rdpr %tl, %l1
cmp %l1, 6
bl wdog_end
start_tsa_shift:
mov 0x2, %l2
tsa_shift:
wrpr %l2, %tl
rdpr %tt, %l3
rdpr %tpc, %l4
rdpr %tnpc, %l5
rdpr %tstate, %l6
rdhpr %htstate, %l7
dec %l2
wrpr %l2, %tl
wrpr %l3, %tt
wrpr %l4, %tpc
wrpr %l5, %tnpc
wrpr %l6, %tstate
wrhpr %l7, %htstate
add %l2, 2, %l2
cmp %l2, %l1
ble tsa_shift
nop
tsa_shift_done:
dec %l1
wrpr %l1, %tl
wdog_end:
! If TT != 2, then goto trap handler
rdpr %tt, %l1
cmp %l1, 0x2
bne continue_red_other
nop
! else done
mov 0x1f, %l1
stxa %l1, [%g0] ASI_LSU_CTL_REG
done
SECTION .T_CWQ_DATA DATA_VA=0x11000000
attr_data {
Name = .T_CWQ_DATA
hypervisor
}
.data
.global _t1_user_data_start
_t1_user_data_start:
.global _t1_scratch_area
_t1_scratch_area:
.align 16
.global _t1_spu_op_array
_t1_spu_op_array:
.xword 6
.xword 7
.xword 6
.xword 3
.xword 4
.xword 6
.xword 7
.xword 2
.xword 0
.xword 2
.xword 3
.xword 5
.xword 7
.xword 1
.xword 1
.align 16
.global _t1_aes_cwd_array
_t1_aes_cwd_array:
.xword 0xc0e100601900002f
.xword 0xc0e000601800003f
.xword 0xc0e100e01300000f
.xword 0xc0e000601800001f
.xword 0xc0e000801000000f
.xword 0x40e000401400002f
.xword 0x406000c01100000f
.xword 0xc06000601300001f
.xword 0xc06100001700003f
.xword 0xc0e100401700000f
.xword 0xc06000601400003f
.xword 0xc0e100801500000f
.xword 0x406100801900002f
.xword 0x40e000001b00001f
.xword 0xc06000e01400003f
.align 16
.global _t1_des_cwd_array
_t1_des_cwd_array:
.xword 0x406000e00a000017
.xword 0xc06100400a000017
.xword 0x406000400c00000f
.xword 0x40e100e008000007
.xword 0x406000c00800000f
.xword 0xc0e000a00c00000f
.xword 0x406000200a000007
.xword 0x40e000000e000017
.xword 0x406100800a00001f
.xword 0xc0e000600a000007
.xword 0xc06000c00a00000f
.xword 0x406000200e000017
.xword 0xc06000e00e000017
.xword 0xc06000e00d000017
.xword 0x40e000a00a00001f
.align 16
.global _t1_copy_cwd_array
_t1_copy_cwd_array:
.xword 0xa06000c000000002
.xword 0x2061006000000000
.xword 0x206100600000000a
.xword 0xa06000a00000000d
.xword 0xa061000000000004
.xword 0xa06000a000000005
.xword 0x2060006000000009
.xword 0x2060006000000002
.xword 0x206000a00000000c
.xword 0xa061006000000006
.xword 0x2060000000000003
.xword 0xa061008000000009
.xword 0x206100800000000b
.xword 0xa06100c000000003
.xword 0x206100e00000000d
.align 16
.global _t1_crc_cwd_array
_t1_crc_cwd_array:
.xword 0x4162032400000007
.xword 0x416101e800000002
.xword 0xc16103c40000000d
.xword 0xc16101c800000004
.xword 0xc161034400000008
.xword 0x416301480000000a
.xword 0xc161038400000003
.xword 0x4160010800000001
.xword 0xc16303a400000009
.xword 0x416301280000000b
.xword 0x4162032400000001
.xword 0x416201880000000b
.xword 0x416003640000000d
.xword 0x4162010800000008
.align 16
.global _t1_hash_cwd_array
_t1_hash_cwd_array:
.xword 0xc1610f0100000019
.xword 0xc161058100000024
.xword 0xc163130200000035
.xword 0x416100020000002f
.xword 0x41620fc100000024
.xword 0x41630dc10000002c
.xword 0x4161036100000008
.xword 0xc16300e300000007
.xword 0xc16006c100000014
.xword 0xc16002610000001e
.xword 0xc16208a10000001b
.xword 0xc1630e610000001d
.xword 0x416101210000003b
.xword 0x416302e100000035
.xword 0xc16104620000003c
.align 16
.global _t1_hmac_cwd_array
_t1_hmac_cwd_array:
.xword 0x4163020b001f0021
.xword 0x41600469000f0026
.xword 0x416302060013001f
.xword 0x416002e9000f0015
.xword 0xc1630669000f0011
.xword 0x41610405000f0003
.xword 0x416107460013001f
.xword 0x41620e29000f0013
.xword 0x416300cb001f002b
.xword 0xc1610eaa00130035
.xword 0xc163158b001f0026
.xword 0x41620baa00130006
.xword 0x416108e5000f0025
.xword 0x41620749000f0009
.xword 0xc1611007001f001e
.align 16
.global _t1_rc4_cwd_array
_t1_rc4_cwd_array:
.xword 0x40e000400400000e
.xword 0x40e100200400000e
.xword 0x40e000e000000006
.xword 0x40e0002000000004
.xword 0xc0e0000004000005
.xword 0x40e000e000000005
.xword 0x40e000e00400000d
.xword 0xc0e1006004000006
.xword 0x40e0002004000003
.xword 0x40e1004000000004
.xword 0xc0e0008000000006
.xword 0xc0e000a004000009
.xword 0xc0e100200400000c
.xword 0x40e0006000000001
.xword 0xc0e100600400000b
.global _t1_sslkey_cwd_array
.align 16
_t1_sslkey_cwd_array:
.xword 0x90602a6000000000, 0
.xword 0x9060338000000000, 0
.xword 0x9060150000000000, 0
.xword 0x106031c000000000, 0
.xword 0x90603ba000000000, 0
.xword 0x90602dc000000000, 0
.xword 0x106025c000000000, 0
.xword 0x10602ae000000000, 0
.xword 0x1060038000000000, 0
.xword 0x10600f4000000000, 0
.xword 0x10600e4000000000, 0
.xword 0x1060262000000000, 0
.xword 0x1060020000000000, 0
.xword 0x9060372000000000, 0
.xword 0x90603c4000000000, 0
.align 16
_t1_aes_key_array:
.xword 0x6998589ae0c88530
.xword 0x9cf3260c4bd0b7b5
.xword 0x76a8ee80b60f715c
.xword 0xc4d9d2df54c6e60b
.xword 0x5b273e0e04fc6bb5
.xword 0xc5fd9d941337061c
.xword 0xe5f6ef7d69b35080
.xword 0x9921e181f371654a
.xword 0x830d079247470b15
.xword 0xa867901d8ed21798
.xword 0x4fe98bb9f25c5a11
.xword 0x33fcc4a0fa372804
.xword 0x7dcd7acdc21ceaed
.xword 0x2ab766e7fd4f35d3
.xword 0xd658e6f7d5616055
.xword 0xea0c0a087a6f2a96
.xword 0xbe9be244aec2ade5
.xword 0x9973affa08f5bace
.xword 0x39072ac1c54c5114
.xword 0x9513064351dd8925
.xword 0x6c25aa0b784e5bfd
.xword 0x4d08c530311f250a
.xword 0x2af979c6b57bd338
.xword 0x48210d626ee0ad1b
.xword 0x736a012c914fa382
.xword 0xcb19ee3028a6023e
.xword 0x54bec4af24510e80
.xword 0xc150f2321d9ee128
.xword 0x39f47776a9d24a71
.xword 0xc12831cf13fea646
.xword 0xcf61cd7da8bc7510
.xword 0x19365b02bb56afcd
.xword 0xf4876dda0f9f517d
.xword 0xa07379c269eab4d8
.xword 0x3feb9a4f02a5ea1c
.xword 0xd91ac908ad5ac7f9
.xword 0xa4f75e2073c05036
.xword 0x476681c05b0c0fed
.xword 0x84b090f7bac4dc69
.xword 0x316f3c23c0ea8129
.xword 0xd64cc2506f0c4607
.xword 0xf0b110035fd5b0b1
.xword 0x8443b7bee68fc521
.xword 0x3b14e8cdf358128c
.xword 0xc712cd9e5b832a1d
.xword 0xc804802299ea2867
.xword 0x0a4345c77f8ef709
.xword 0xfe4ffc29bbe6b6a2
.xword 0xe1f465e3752b6889
.xword 0x1c13098424196f38
.xword 0xb287761b3b8603fa
.align 16
_t1_aes_iv_array:
.xword 0xdb9874dc54074e43
.xword 0xf357435b91eb317d
.xword 0x73f6d3683f15cc9c
.xword 0xb606696bfcaca603
.xword 0x0d4b672de3c3aa4d
.xword 0xd3b8034efb30bc9e
.xword 0x60dc1ac225e4eefa
.xword 0x7fef70dffcbdd8c7
.xword 0xae17ccad9701a312
.xword 0x9f4f828b2c608724
.xword 0x340be71147921d7f
.xword 0xdcdfb6da0f3fbc2c
.xword 0x1a93e6d151e67624
.xword 0x209beb1df40fffc1
.xword 0x6a2c6b6b36e6e859
.xword 0x55c4841b4c6a928f
.xword 0x182221e9a61125b4
.xword 0x5f387e9ed15e44c8
.xword 0x3007b59e2b70e2a9
.xword 0xf510a8c061a6fab2
.xword 0x407456a338f477a4
.xword 0xec62cfcfb3ad45c7
.xword 0x68ad96c99dc96d45
.xword 0x78ae6a1ea9d60397
.xword 0xea708e72520e301a
.xword 0x9921416855df94a3
.xword 0x751ea5cac831f5b4
.xword 0xf534d6a8dca9c59c
.xword 0x4ddea232e8fdafa1
.xword 0x61408ec28001eef4
.xword 0xbdfd67dede2b0e72
.xword 0x1e163c02efbdef96
.xword 0xb27ac45da31e6f9b
.xword 0x55e25e50a95e2645
.xword 0xf14e983b19513869
.xword 0x50ccfc0b94713bae
.xword 0xb36e4c3cdbd6777a
.xword 0xc81200703f290cfa
.xword 0x88a5dd43b4420630
.xword 0x2ac47e26a2ffc8aa
.xword 0xbb04f7b2de185cf8
.xword 0xfbdfede438a81af1
.xword 0x2de79a789f759ff5
.xword 0x7312905180a86147
.xword 0xa92d0b3fda1830fc
.align 16
_t1_aes_alignment_array:
.xword 13
.xword 13
.xword 14
.xword 6
.xword 3
.xword 11
.xword 15
.xword 10
.xword 3
.xword 5
.xword 5
.xword 9
.xword 15
.xword 2
.xword 12
.xword 14
.xword 10
.xword 8
.xword 6
.xword 12
.xword 3
.xword 4
.xword 0
.xword 4
.xword 10
.xword 7
.xword 6
.xword 3
.xword 13
.xword 8
.xword 10
.xword 11
.xword 6
.xword 9
.xword 8
.xword 4
.xword 7
.xword 6
.xword 10
.xword 2
.xword 1
.xword 5
.xword 11
.xword 14
.xword 7
.xword 7
.xword 9
.xword 0
.xword 1
.xword 10
.xword 7
.xword 13
.xword 7
.xword 7
.xword 4
.xword 0
.xword 10
.xword 15
.xword 8
.xword 3
.xword 13
.xword 10
.xword 5
.xword 4
.xword 5
.xword 14
.xword 10
.xword 9
.xword 6
.xword 1
.xword 11
.xword 4
.xword 7
.xword 8
.xword 12
.xword 11
.xword 3
.xword 14
.xword 11
.xword 3
.xword 1
.xword 5
.xword 11
.xword 6
.xword 15
.xword 4
.xword 4
.xword 6
.xword 4
.xword 11
.xword 11
.xword 12
.xword 15
.xword 11
.xword 9
.xword 8
.xword 7
.xword 2
.xword 2
.xword 8
.xword 12
.xword 8
.xword 8
.xword 15
.xword 8
.align 16
_t1_aes_src:
.xword 0xb89ef50948d798a0
.xword 0x3f9254228339485c
.xword 0xd0d736c0d91c7c54
.xword 0x835ed22e9d5bf321
.xword 0x69ff32852f8ed7e5
.xword 0xc5fafb8730963aea
.xword 0x6f7df15b748d864b
.xword 0xe7bd5c8219c8077d
.xword 0xb56e7a91a2b7edc5
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.align 16
_t1_hash_iv_array:
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.align 16
_t1_hash_alignment_array:
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.xword 0
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.xword 7
.xword 8
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.align 16
_t1_hash_src:
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Full OpenSPARC design & verification tarball including full HDL.