verif/diag/diaglists/mss/mcu_dimm_cfg_1c1r.diaglist

// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T2 Processor File: mcu_dimm_cfg_1c1r.diaglist
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
//
// For the avoidance of doubt, and except that if any non-GPL license
// choice is available it will apply instead, Sun elects to use only
// the General Public License version 2 (GPLv2) at this time for any
// software where a choice of GPL license versions is made
// available with the language indicating that GPLv2 or any later version
// may be used, or where a choice of which version of the GPL is applied is
// otherwise unspecified.
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
// CA 95054 USA or visit www.sun.com if you need additional information or
// have any questions.
//
// ========== Copyright Header End ============================================
#ifndef SYSNAME
#  ifdef FC8
//   // FC8 parameters
#    define SYSNAME fc8
#    define sys(x) mss_fc8_ ## x
#  else
//   // FC1 parameters
#    define SYSNAME fc1
#    define sys(x) mss_fc1_ ## x
#  endif
#endif
//
#ifdef SETMODREL
#  define MODREL_1c1r -vcs_rel_name=fc1_dimm8_1rank_sng
#else
#  define MODREL_1c1r
#endif
//
//==============================================================================
//
<sys(dimmCfg_1c1r)  name=sys(dimmCfg_1c1r)>
//
//==============================================================================
<sys(build_dimmCfg_1c1r) sys=SYSNAME -sunv_run -vcs_build -zeroIn_build -config_rtl=ZIN_USE_CORE_CHECKERS -vcs_build_args=+define+DEBUG_PIPE -vcs_build_args=+define+FBDIMM_NUM_8 -vcs_build_args=+define+SNG_CHANNEL>
//
//==============================================================================
//
<runargs -vcs_run -sas -midas_args=-DCMP_THREAD_START=ALL -finish_mask=all -midas_args=-DPART_0_BASE=0x80000000 -vcs_run_args=+l2esr_mon_off -fast_boot -midas_args=-allow_tsb_conflicts -vcs_run_args=+noDebugChecks -max_cycle=+10000000 -vcs_run_args=+TIMEOUT=250000 -rtl_timeout=100000000 -vcs_run_args=+th_timeout=100000000 -vcs_run_args=+skt_timeout=100000000 -tg_seed=1 -midas_args=-DDISABLE_ALL_CACHES -vcs_run_args=+SNG_CHANNEL -drm_freeram=2000 -drm_freeswap=2000 -drm_type=rgrs -regress MODREL_1c1r -nosaslog -midas_args=-DHBOOT_HV_ONLY -vcs_run_args=+err_chkrs_off -vcs_run_args=+PEU_TEST>
//
//==============================================================================
//
indra_mcu_1c1r_Dma0Cac0Mcu1Tog0_rand_0 indra_mcu_1c1r_Dma0Cac0Mcu1Tog0_rand_0.s -vcs_run_args=+SNG_CHANNEL -vcs_run_args=+RANK_HIGH -vcs_run_args=+2_FBDIMMS -vcs_run_args=+DIMM_SIZE_512
indra_mcu_1c1r_Dma0Cac0Mcu1Tog1_rand_0 indra_mcu_1c1r_Dma0Cac0Mcu1Tog1_rand_0.s -vcs_run_args=+SNG_CHANNEL -vcs_run_args=+RANK_LOW -vcs_run_args=+4_FBDIMMS -vcs_run_args=+DIMM_SIZE_2G
indra_mcu_1c1r_Dma0Cac0Mcu1Tog2_rand_0 indra_mcu_1c1r_Dma0Cac0Mcu1Tog2_rand_0.s -vcs_run_args=+SNG_CHANNEL -vcs_run_args=+RANK_LOW -vcs_run_args=+2_FBDIMMS -vcs_run_args=+DIMM_SIZE_2G
indra_mcu_1c1r_Dma0Cac0Mcu1Tog3_rand_0 indra_mcu_1c1r_Dma0Cac0Mcu1Tog3_rand_0.s -vcs_run_args=+SNG_CHANNEL -vcs_run_args=+RANK_LOW -vcs_run_args=+4_FBDIMMS -vcs_run_args=+DIMM_SIZE_1G
indra_mcu_1c1r_Dma0Cac0Mcu2Tog0_rand_0 indra_mcu_1c1r_Dma0Cac0Mcu2Tog0_rand_0.s -vcs_run_args=+SNG_CHANNEL -vcs_run_args=+RANK_HIGH -vcs_run_args=+1_FBDIMM -vcs_run_args=+DIMM_SIZE_2G
indra_mcu_1c1r_Dma0Cac0Mcu2Tog1_rand_0 indra_mcu_1c1r_Dma0Cac0Mcu2Tog1_rand_0.s -vcs_run_args=+SNG_CHANNEL -vcs_run_args=+RANK_LOW -vcs_run_args=+1_FBDIMM -vcs_run_args=+DIMM_SIZE_1G
indra_mcu_1c1r_Dma0Cac0Mcu2Tog2_rand_0 indra_mcu_1c1r_Dma0Cac0Mcu2Tog2_rand_0.s -vcs_run_args=+SNG_CHANNEL -vcs_run_args=+RANK_HIGH -vcs_run_args=+1_FBDIMM -vcs_run_args=+DIMM_SIZE_2G
indra_mcu_1c1r_Dma0Cac0Mcu2Tog3_rand_0 indra_mcu_1c1r_Dma0Cac0Mcu2Tog3_rand_0.s -vcs_run_args=+SNG_CHANNEL -vcs_run_args=+RANK_LOW -vcs_run_args=+4_FBDIMMS -vcs_run_args=+DIMM_SIZE_1G
indra_mcu_1c1r_Dma0Cac0McurTog0_rand_0 indra_mcu_1c1r_Dma0Cac0McurTog0_rand_0.s -vcs_run_args=+SNG_CHANNEL -vcs_run_args=+RANK_LOW -vcs_run_args=+8_FBDIMMS -vcs_run_args=+DIMM_SIZE_1G
indra_mcu_1c1r_Dma0Cac0McurTog1_rand_0 indra_mcu_1c1r_Dma0Cac0McurTog1_rand_0.s -vcs_run_args=+SNG_CHANNEL -vcs_run_args=+RANK_HIGH -vcs_run_args=+1_FBDIMM -vcs_run_args=+DIMM_SIZE_512
indra_mcu_1c1r_Dma0Cac0McurTog2_rand_0 indra_mcu_1c1r_Dma0Cac0McurTog2_rand_0.s -vcs_run_args=+SNG_CHANNEL -vcs_run_args=+RANK_HIGH -vcs_run_args=+8_FBDIMMS -vcs_run_args=+DIMM_SIZE_512
indra_mcu_1c1r_Dma0Cac0McurTog3_rand_0 indra_mcu_1c1r_Dma0Cac0McurTog3_rand_0.s -vcs_run_args=+SNG_CHANNEL -vcs_run_args=+RANK_LOW -vcs_run_args=+4_FBDIMMS -vcs_run_args=+DIMM_SIZE_1G
//
// =========================================================================================
//
</runargs>
//
//==============================================================================
//
<runargs -vcs_run -sas -midas_args=-DCMP_THREAD_START=ALL -finish_mask=all -midas_args=-DPART_0_BASE=0x80000000 -vcs_run_args=+l2esr_mon_off -fast_boot -midas_args=-allow_tsb_conflicts -vcs_run_args=+noDebugChecks -max_cycle=+10000000 -vcs_run_args=+TIMEOUT=250000 -rtl_timeout=100000000 -vcs_run_args=+th_timeout=100000000 -vcs_run_args=+skt_timeout=100000000 -tg_seed=1 -midas_args=-DDISABLE_ALL_CACHES -vcs_run_args=+SNG_CHANNEL -drm_freeram=2000 -drm_freeswap=2000 -drm_type=rgrs -regress MODREL_1c1r>
//==============================================================================
//
// 18 diags generated from MPGen

mpgen_1ch_hi_2g_1r_4fb mpgen_1ch_hi_2g_1r_4fb.s  -vcs_run_args=+RANK_HIGH -vcs_run_args=+DIMM_SIZE_2G  -vcs_run_args=+4_FBDIMMS
mpgen_1ch_hi_2g_1r_2fb mpgen_1ch_hi_2g_1r_2fb.s  -vcs_run_args=+RANK_HIGH -vcs_run_args=+DIMM_SIZE_2G  -vcs_run_args=+2_FBDIMMS
mpgen_1ch_hi_2g_1r_1fb mpgen_1ch_hi_2g_1r_1fb.s  -vcs_run_args=+RANK_HIGH -vcs_run_args=+DIMM_SIZE_2G  -vcs_run_args=+1_FBDIMM
mpgen_1ch_hi_1g_1r_4fb mpgen_1ch_hi_1g_1r_4fb.s  -vcs_run_args=+RANK_HIGH -vcs_run_args=+DIMM_SIZE_1G  -vcs_run_args=+4_FBDIMMS
mpgen_1ch_hi_1g_1r_2fb mpgen_1ch_hi_1g_1r_2fb.s  -vcs_run_args=+RANK_HIGH -vcs_run_args=+DIMM_SIZE_1G  -vcs_run_args=+2_FBDIMMS
mpgen_1ch_hi_1g_1r_1fb mpgen_1ch_hi_1g_1r_1fb.s  -vcs_run_args=+RANK_HIGH -vcs_run_args=+DIMM_SIZE_1G  -vcs_run_args=+1_FBDIMM
mpgen_1ch_hi_0g_1r_4fb mpgen_1ch_hi_0g_1r_4fb.s  -vcs_run_args=+RANK_HIGH -vcs_run_args=+DIMM_SIZE_512 -vcs_run_args=+4_FBDIMMS
mpgen_1ch_hi_0g_1r_2fb mpgen_1ch_hi_0g_1r_2fb.s  -vcs_run_args=+RANK_HIGH -vcs_run_args=+DIMM_SIZE_512 -vcs_run_args=+2_FBDIMMS
mpgen_1ch_hi_0g_1r_1fb mpgen_1ch_hi_0g_1r_1fb.s  -vcs_run_args=+RANK_HIGH -vcs_run_args=+DIMM_SIZE_512 -vcs_run_args=+1_FBDIMM
mpgen_1ch_lo_2g_1r_4fb mpgen_1ch_lo_2g_1r_4fb.s  -vcs_run_args=+RANK_LOW  -vcs_run_args=+DIMM_SIZE_2G  -vcs_run_args=+4_FBDIMMS
mpgen_1ch_lo_2g_1r_2fb mpgen_1ch_lo_2g_1r_2fb.s  -vcs_run_args=+RANK_LOW  -vcs_run_args=+DIMM_SIZE_2G  -vcs_run_args=+2_FBDIMMS
mpgen_1ch_lo_2g_1r_1fb mpgen_1ch_lo_2g_1r_1fb.s  -vcs_run_args=+RANK_LOW  -vcs_run_args=+DIMM_SIZE_2G  -vcs_run_args=+1_FBDIMM
mpgen_1ch_lo_1g_1r_4fb mpgen_1ch_lo_1g_1r_4fb.s  -vcs_run_args=+RANK_LOW  -vcs_run_args=+DIMM_SIZE_1G  -vcs_run_args=+4_FBDIMMS
mpgen_1ch_lo_1g_1r_2fb mpgen_1ch_lo_1g_1r_2fb.s  -vcs_run_args=+RANK_LOW  -vcs_run_args=+DIMM_SIZE_1G  -vcs_run_args=+2_FBDIMMS
mpgen_1ch_lo_1g_1r_1fb mpgen_1ch_lo_1g_1r_1fb.s  -vcs_run_args=+RANK_LOW  -vcs_run_args=+DIMM_SIZE_1G  -vcs_run_args=+1_FBDIMM
mpgen_1ch_lo_0g_1r_4fb mpgen_1ch_lo_0g_1r_4fb.s  -vcs_run_args=+RANK_LOW  -vcs_run_args=+DIMM_SIZE_512 -vcs_run_args=+4_FBDIMMS
mpgen_1ch_lo_0g_1r_2fb mpgen_1ch_lo_0g_1r_2fb.s  -vcs_run_args=+RANK_LOW  -vcs_run_args=+DIMM_SIZE_512 -vcs_run_args=+2_FBDIMMS
mpgen_1ch_lo_0g_1r_1fb mpgen_1ch_lo_0g_1r_1fb.s  -vcs_run_args=+RANK_LOW  -vcs_run_args=+DIMM_SIZE_512 -vcs_run_args=+1_FBDIMM

</runargs>

</sys(build_dimmCfg_1c1r)>

</sys(dimmCfg_1c1r)>

//==============================================================================