verif/diag/diaglists/pm/pm_spu.diaglist

// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T2 Processor File: pm_spu.diaglist
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
//
// For the avoidance of doubt, and except that if any non-GPL license
// choice is available it will apply instead, Sun elects to use only
// the General Public License version 2 (GPLv2) at this time for any
// software where a choice of GPL license versions is made
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// ========== Copyright Header End ============================================
<sys(spu_pm) name=sys(spu_pm)>
<sys(pm_all)>

<sys(pm_spu)>

<runargs -vcs_run_args=+show_delta -vcs_run_args=+show_memop -vcs_run_args=+8_FBDIMMS -midas_args=-DPART_0_BASE=0x200000000 -sas -midas_args=-allow_tsb_conflicts -fast_boot>

//Core0_2bank
<runargs -vcs_run_args=+core_set_mask=01 -vcs_run_args=+bank_set_mask=1 -midas_args=-DCMP_THREAD_START=0x1 -finish_mask=1>
n2_pm_spu_Core0_Bank1     n2_sput0.s
<runargs -midas_args=-DL2_DIRECT_MAP>
n2_pm_spu_Core0_Bank1_DM  n2_sput0.s
</runargs>
</runargs>

<runargs -vcs_run_args=+core_set_mask=01 -vcs_run_args=+bank_set_mask=2 -midas_args=-DCMP_THREAD_START=0x1 -finish_mask=1>
n2_pm_spu_Core0_Bank2     n2_sput0.s
<runargs -midas_args=-DL2_DIRECT_MAP>
n2_pm_spu_Core0_Bank2_DM  n2_sput0.s
</runargs>
</runargs>

<runargs -vcs_run_args=+core_set_mask=01 -vcs_run_args=+bank_set_mask=4 -midas_args=-DCMP_THREAD_START=0x1 -finish_mask=1>
n2_pm_spu_Core0_Bank4     n2_sput0.s
<runargs -midas_args=-DL2_DIRECT_MAP>
n2_pm_spu_Core0_Bank4_DM  n2_sput0.s
</runargs>
</runargs>

<runargs -vcs_run_args=+core_set_mask=01 -vcs_run_args=+bank_set_mask=8 -midas_args=-DCMP_THREAD_START=0x1 -finish_mask=1>
n2_pm_spu_Core0_Bank8     n2_sput0.s
<runargs -midas_args=-DL2_DIRECT_MAP>
n2_pm_spu_Core0_Bank8_DM  n2_sput0.s
</runargs>
</runargs>

//Core0_4bank
<runargs -vcs_run_args=+core_set_mask=01 -vcs_run_args=+bank_set_mask=3 -midas_args=-DCMP_THREAD_START=0x1 -finish_mask=1>
n2_pm_spu_Core0_Bank3     n2_sput0.s
<runargs -midas_args=-DL2_DIRECT_MAP>
n2_pm_spu_Core0_Bank3_DM  n2_sput0.s
</runargs>
</runargs>

<runargs -vcs_run_args=+core_set_mask=01 -vcs_run_args=+bank_set_mask=c -midas_args=-DCMP_THREAD_START=0x1 -finish_mask=1>
n2_pm_spu_Core0_Bankc     n2_sput0.s
<runargs -midas_args=-DL2_DIRECT_MAP>
n2_pm_spu_Core0_Bankc_DM  n2_sput0.s
</runargs>
</runargs>

//Core1_2bank
<runargs -vcs_run_args=+core_set_mask=02 -vcs_run_args=+bank_set_mask=1 -midas_args=-DCMP_THREAD_START=0x100 -finish_mask=100>
n2_pm_spu_Core1_Bank1     sput8.s
<runargs -midas_args=-DL2_DIRECT_MAP>
n2_pm_spu_Core1_Bank1_DM  sput8.s
</runargs>
</runargs>

<runargs -vcs_run_args=+core_set_mask=02 -vcs_run_args=+bank_set_mask=2 -midas_args=-DCMP_THREAD_START=0x100 -finish_mask=100>
n2_pm_spu_Core1_Bank2     sput8.s
<runargs -midas_args=-DL2_DIRECT_MAP>
n2_pm_spu_Core1_Bank2_DM  sput8.s
</runargs>
</runargs>

<runargs -vcs_run_args=+core_set_mask=02 -vcs_run_args=+bank_set_mask=4 -midas_args=-DCMP_THREAD_START=0x100 -finish_mask=100>
n2_pm_spu_Core1_Bank4     sput8.s
<runargs -midas_args=-DL2_DIRECT_MAP>
n2_pm_spu_Core1_Bank4_DM  sput8.s
</runargs>
</runargs>

<runargs -vcs_run_args=+core_set_mask=02 -vcs_run_args=+bank_set_mask=8 -midas_args=-DCMP_THREAD_START=0x100 -finish_mask=100>
n2_pm_spu_Core1_Bank8     sput8.s
<runargs -midas_args=-DL2_DIRECT_MAP>
n2_pm_spu_Core1_Bank8_DM  sput8.s
</runargs>
</runargs>

//Core1_4bank
<runargs -vcs_run_args=+core_set_mask=02 -vcs_run_args=+bank_set_mask=3 -midas_args=-DCMP_THREAD_START=0x100 -finish_mask=100>
n2_pm_spu_Core1_Bank3     sput8.s
<runargs -midas_args=-DL2_DIRECT_MAP>
n2_pm_spu_Core1_Bank3_DM  sput8.s
</runargs>
</runargs>

<runargs -vcs_run_args=+core_set_mask=02 -vcs_run_args=+bank_set_mask=c -midas_args=-DCMP_THREAD_START=0x100 -finish_mask=100>
n2_pm_spu_Core1_Bankc     sput8.s
<runargs -midas_args=-DL2_DIRECT_MAP>
n2_pm_spu_Core1_Bankc_DM  sput8.s
</runargs>
</runargs>

//Core1_8bank
<runargs -vcs_run_args=+core_set_mask=02 -midas_args=-DCMP_THREAD_START=0x100 -finish_mask=100>
n2_pm_spu_Core1_Bank      sput8.s
<runargs -midas_args=-DL2_DIRECT_MAP>
n2_pm_spu_Core1_Bank_DM  sput8.s
</runargs>
</runargs>

</runargs>

</sys(pm_spu)>


</sys(pm_all)>
</sys(spu_pm)>