verif/env/common/coverage/dmu/dmu_clu_sample.vrh

// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T2 Processor File: dmu_clu_sample.vrh
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
//
// For the avoidance of doubt, and except that if any non-GPL license
// choice is available it will apply instead, Sun elects to use only
// the General Public License version 2 (GPLv2) at this time for any
// software where a choice of GPL license versions is made
// available with the language indicating that GPLv2 or any later version
// may be used, or where a choice of which version of the GPL is applied is
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// ========== Copyright Header End ============================================
sample dmu_clu_cl2ps (dmu_clu_coverage.cl2ps_e_trn)
{

state DMU_CLU_ADR_00  ( 5'b00000 );
state DMU_CLU_ADR_01  ( 5'b00001 );
state DMU_CLU_ADR_02  ( 5'b00010 );
state DMU_CLU_ADR_03  ( 5'b00011 );
state DMU_CLU_ADR_04  ( 5'b00100 );
state DMU_CLU_ADR_05  ( 5'b00101 );
state DMU_CLU_ADR_06  ( 5'b00110 );
state DMU_CLU_ADR_07  ( 5'b00111 );
state DMU_CLU_ADR_08  ( 5'b01000 );
state DMU_CLU_ADR_09  ( 5'b01001 );
state DMU_CLU_ADR_10  ( 5'b01010 );
state DMU_CLU_ADR_11  ( 5'b01011 );
state DMU_CLU_ADR_12  ( 5'b01100 );
state DMU_CLU_ADR_13  ( 5'b01101 );
state DMU_CLU_ADR_14  ( 5'b01110 );
state DMU_CLU_ADR_15  ( 5'b01111 );
state DMU_CLU_ADR_16  ( 5'b10000 );
state DMU_CLU_ADR_17  ( 5'b10001 );
state DMU_CLU_ADR_18  ( 5'b10010 );
state DMU_CLU_ADR_19  ( 5'b10011 );
state DMU_CLU_ADR_20  ( 5'b10100 );
state DMU_CLU_ADR_21  ( 5'b10101 );
state DMU_CLU_ADR_22  ( 5'b10110 );
state DMU_CLU_ADR_23  ( 5'b10111 );
state DMU_CLU_ADR_24  ( 5'b11000 );
state DMU_CLU_ADR_25  ( 5'b11001 );
state DMU_CLU_ADR_26  ( 5'b11010 );
state DMU_CLU_ADR_27  ( 5'b11011 );
state DMU_CLU_ADR_28  ( 5'b11100 );
state DMU_CLU_ADR_29  ( 5'b11101 );
state DMU_CLU_ADR_30  ( 5'b11110 );
state DMU_CLU_ADR_31  ( 5'b11111 );

}