// ========== Copyright Header Begin ==========================================
// OpenSPARC T2 Processor File: l2_error_offmode_sample.vrhpal
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
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// ========== Copyright Header End ============================================
wildcard state LOAD_ue( {1'b1, 2'b1x, 1'b1, 1'b1, 1'b0, LOAD_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
wildcard state LOAD_ce( {1'b1, 2'bx1, 1'b1, 1'b1, 1'b0, LOAD_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
// PREFETCH off ue,ce fbhit vld diag reqtype nc jbi cputh inv pf bis
wildcard state PREFETCH_ue( {1'b1, 2'b1x, 1'b1, 1'b1, 1'b0, LOAD_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b1, 1'b0} );
wildcard state PREFETCH_ce( {1'b1, 2'bx1, 1'b1, 1'b1, 1'b0, LOAD_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b1, 1'b0} );
// IMISS off ue,ce fbhit vld diag reqtype nc jbi cputh inv pf bis
wildcard state IMISS_ue( {1'b1, 2'b1x, 1'b1, 1'b1, 1'b0, IMISS_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
wildcard state IMISS_ce( {1'b1, 2'bx1, 1'b1, 1'b1, 1'b0, IMISS_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
// STORE off ue,ce fbhit vld diag reqtype nc jbi cputh inv pf bis
wildcard state STORE_ue( {1'b1, 2'b1x, 1'b1, 1'b1, 1'b0, STORE_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
wildcard state STORE_ce( {1'b1, 2'bx1, 1'b1, 1'b1, 1'b0, STORE_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
// BLKSTORE off ue,ce fbhit vld diag reqtype nc jbi cputh inv pf bis
wildcard state BLKSTORE_ue( {1'b1, 2'b1x, 1'b1, 1'b1, 1'b0, STORE_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b1, 1'b1} );
wildcard state BLKSTORE_ce( {1'b1, 2'bx1, 1'b1, 1'b1, 1'b0, STORE_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b1, 1'b1} );
// BLKINITST off ue,ce fbhit vld diag reqtype nc jbi cputh inv pf bis
wildcard state BLKINITST_ue( {1'b1, 2'b1x, 1'b1, 1'b1, 1'b0, STORE_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b1} );
wildcard state BLKINITST_ce( {1'b1, 2'bx1, 1'b1, 1'b1, 1'b0, STORE_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b1} );
// CAS1 off ue,ce fbhit vld diag reqtype nc jbi cputh inv pf bis
wildcard state CAS1_ue( {1'b1, 2'b1x, 1'b1, 1'b1, 1'b0, CAS1_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
wildcard state CAS1_ce( {1'b1, 2'bx1, 1'b1, 1'b1, 1'b0, CAS1_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
// SWAP off ue,ce fbhit vld diag reqtype nc jbi cputh inv pf bis
wildcard state SWAP_ue( {1'b1, 2'b1x, 1'b1, 1'b1, 1'b0, SWAP_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
wildcard state SWAP_ce( {1'b1, 2'bx1, 1'b1, 1'b1, 1'b0, SWAP_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
// STRLOAD off ue,ce fbhit vld diag reqtype nc jbi cputh inv pf bis
wildcard state STRLOAD_ue( {1'b1, 2'b1x, 1'b1, 1'b1, 1'b0, STRLOAD_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
wildcard state STRLOAD_ce( {1'b1, 2'bx1, 1'b1, 1'b1, 1'b0, STRLOAD_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
// STRST off ue,ce fbhit vld diag reqtype nc jbi cputh inv pf bis
wildcard state STRST_ue( {1'b1, 2'b1x, 1'b1, 1'b1, 1'b0, STRST_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
wildcard state STRST_ce( {1'b1, 2'bx1, 1'b1, 1'b1, 1'b0, STRST_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
// FWDRQ_LOAD off ue,ce fbhit vld diag reqtype nc jbi cputh inv pf bis
wildcard state FWDRQ_LOAD_ue( {1'b1, 2'b1x, 1'b1, 1'b1, 1'b0, FWD_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
wildcard state FWDRQ_LOAD_ce( {1'b1, 2'bx1, 1'b1, 1'b1, 1'b0, FWD_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
// FWDRQ_STORE off ue,ce fbhit vld diag reqtype nc jbi cputh inv pf bis
wildcard state FWDRQ_STORE_ue( {1'b1, 2'b1x, 1'b1, 1'b1, 1'b0, FWD_RQ, 1'b0, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
wildcard state FWDRQ_STORE_ce( {1'b1, 2'bx1, 1'b1, 1'b1, 1'b0, FWD_RQ, 1'b0, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
// PREFETCH_ICE off ue,ce fbhit vld diag reqtype nc jbi cputh inv pf bis
wildcard state PFICE_ue( {1'b1, 2'b1x, 1'b1, 1'b1, 1'b0, LOAD_RQ, 1'b1, 1'b0, 6'bx, 1'b1, 1'b1, 1'b0} );
wildcard state PFICE_ce( {1'b1, 2'bx1, 1'b1, 1'b1, 1'b0, LOAD_RQ, 1'b1, 1'b0, 6'bx, 1'b1, 1'b1, 1'b0} );
// RDD off ue,ce fbhit vld diag reqtype nc jbi
wildcard state RDD_ue( {1'b1, 2'b1x, 1'b1, 1'b1, 1'b0, 5'bxx001, 1'b0, 1'b1, 9'bx} );
wildcard state RDD_ce( {1'b1, 2'bx1, 1'b1, 1'b1, 1'b0, 5'bxx001, 1'b0, 1'b1, 9'bx} );
// WR8 off ue,ce fbhit vld diag reqtype nc jbi
wildcard state WR8_ue( {1'b1, 2'b1x, 1'b1, 1'b1, 1'b0, 5'bxx010, 1'b0, 1'b1, 9'bx} );
wildcard state WR8_ce( {1'b1, 2'bx1, 1'b1, 1'b1, 1'b0, 5'bxx010, 1'b0, 1'b1, 9'bx} );
// WRI does not make a DRAM read request and does not hit the FB
// WRI off ue,ce fbhit vld diag reqtype nc jbi
//wildcard state WRI_ue( {1'b1, 2'b1x, 1'b1, 1'b1, 1'b0, 5'bxx100, 1'b0, 1'b1, 9'bx} );
//wildcard state WRI_ce( {1'b1, 2'bx1, 1'b1, 1'b1, 1'b0, 5'bxx100, 1'b0, 1'b1, 9'bx} );
projects / OpenSPARC-T2-DV / blob