verif/env/common/coverage/l2sat/l2_error_status_reg_sample.vrhpal

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//
// OpenSPARC T2 Processor File: l2_error_status_reg_sample.vrhpal
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wildcard state LVU_new_esr_wr ({LVU_1,  LVU_1});
wildcard state LRU_new_esr_wr ({LRU_1,  LRU_1});
wildcard state LDAU_new_esr_wr({LDAU_1, LDAU_1});
wildcard state LDSU_new_esr_wr({LDSU_1, LDSU_1});
wildcard state LDRU_new_esr_wr({LDRU_1, LDRU_1});
wildcard state LDWU_new_esr_wr({LDWU_1, LDWU_1});
wildcard state DAU_new_esr_wr ({DAU_1,  DAU_1});
wildcard state DRU_new_esr_wr ({DRU_1,  DRU_1});
wildcard state DSU_new_esr_wr ({DSU_1,  DSU_1});
wildcard state LTC_new_esr_wr ({LTC_1,  LTC_1});
wildcard state LDAC_new_esr_wr({LDAC_1, LDAC_1});
wildcard state LDSC_new_esr_wr({LDSC_1, LDSC_1});
wildcard state LDRC_new_esr_wr({LDRC_1, LDRC_1});
wildcard state LDWC_new_esr_wr({LDWC_1, LDWC_1});
wildcard state DAC_new_esr_wr ({DAC_1,  DAC_1});
wildcard state DRC_new_esr_wr ({DRC_1,  DRC_1});
wildcard state DSC_new_esr_wr ({DSC_1,  DSC_1});
wildcard state LVC_new_esr_wr ({LVC_1,  LVC_1});

// error detected, corresponding ESR bit not set
//wildcard state LVU_new_no_esr_wr ({LVU_1,  LVU_0});
wildcard state LRU_new_no_esr_wr ({LRU_1,  LRU_0});
wildcard state LDAU_new_no_esr_wr({LDAU_1, LDAU_0});
wildcard state LDSU_new_no_esr_wr({LDSU_1, LDSU_0});
wildcard state LDRU_new_no_esr_wr({LDRU_1, LDRU_0});
wildcard state LDWU_new_no_esr_wr({LDWU_1, LDWU_0});
wildcard state DAU_new_no_esr_wr ({DAU_1,  DAU_0});
wildcard state DRU_new_no_esr_wr ({DRU_1,  DRU_0});
wildcard state LTC_new_no_esr_wr ({LTC_1,  LTC_0});
wildcard state LDAC_new_no_esr_wr({LDAC_1, LDAC_0});
wildcard state LDSC_new_no_esr_wr({LDSC_1, LDSC_0});
wildcard state LDRC_new_no_esr_wr({LDRC_1, LDRC_0});
wildcard state LDWC_new_no_esr_wr({LDWC_1, LDWC_0});
wildcard state DAC_new_no_esr_wr ({DAC_1,  DAC_0});
wildcard state DRC_new_no_esr_wr ({DRC_1,  DRC_0});
wildcard state LVC_new_no_esr_wr ({LVC_1,  LVC_0});