Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / env / common / coverage / l2sat / l2_error_tag_sample.vrhpal
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// OpenSPARC T2 Processor File: l2_error_tag_sample.vrhpal
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wildcard state LOAD_detect ( {4'bx0x1, 1'b1, 1'b0, 1'bx, LOAD_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
wildcard state LOAD_report ( {4'b00x1, 1'b1, 1'b0, 1'bx, LOAD_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
wildcard state LOAD_schedule( {4'b0001, 1'b1, 1'b0, 1'bx, LOAD_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
wildcard state LOAD_scrub ( {4'bx1xx, 1'b1, 1'b0, 1'bx, LOAD_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
// PREFETCH vld diag pst2 reqtype nc jbi cputh inv pf bis
wildcard state PREFETCH_detect ( {4'bx0x1, 1'b1, 1'b0, 1'bx, LOAD_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b1, 1'b0} );
wildcard state PREFETCH_report ( {4'b00x1, 1'b1, 1'b0, 1'bx, LOAD_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b1, 1'b0} );
wildcard state PREFETCH_schedule( {4'b0001, 1'b1, 1'b0, 1'bx, LOAD_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b1, 1'b0} );
wildcard state PREFETCH_scrub ( {4'bx1xx, 1'b1, 1'b0, 1'bx, LOAD_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b1, 1'b0} );
// IMISS vld diag pst2 reqtype nc jbi cputh inv pf bis
wildcard state IMISS_detect ( {4'bx0x1, 1'b1, 1'b0, 1'bx, IMISS_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
wildcard state IMISS_report ( {4'b00x1, 1'b1, 1'b0, 1'bx, IMISS_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
wildcard state IMISS_schedule( {4'b0001, 1'b1, 1'b0, 1'bx, IMISS_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
wildcard state IMISS_scrub ( {4'bx1xx, 1'b1, 1'b0, 1'bx, IMISS_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
// STORE vld diag pst2 reqtype nc jbi cputh inv pf bis
wildcard state STORE_detect ( {4'bx0x1, 1'b1, 1'b0, 1'b0, STORE_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
wildcard state STORE_report ( {4'b00x1, 1'b1, 1'b0, 1'b0, STORE_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
wildcard state STORE_schedule( {4'b0001, 1'b1, 1'b0, 1'b0, STORE_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
wildcard state STORE_scrub ( {4'bx1xx, 1'b1, 1'b0, 1'b0, STORE_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
// STORE (partial, 2nd pass) vld diag pst2 reqtype nc jbi cputh inv pf bis
wildcard state STOREpst2_detect ( {4'bx0x1, 1'b1, 1'b0, 1'b1, STORE_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
wildcard state STOREpst2_report ( {4'b00x1, 1'b1, 1'b0, 1'b1, STORE_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
wildcard state STOREpst2_schedule( {4'b0001, 1'b1, 1'b0, 1'b1, STORE_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
wildcard state STOREpst2_scrub ( {4'bx1xx, 1'b1, 1'b0, 1'b1, STORE_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
// BLKSTORE vld diag pst2 reqtype nc jbi cputh inv pf bis
wildcard state BLKSTORE_detect ( {4'bx0x1, 1'b1, 1'b0, 1'bx, STORE_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b1, 1'b1} );
wildcard state BLKSTORE_report ( {4'b00x1, 1'b1, 1'b0, 1'bx, STORE_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b1, 1'b1} );
wildcard state BLKSTORE_schedule( {4'b0001, 1'b1, 1'b0, 1'bx, STORE_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b1, 1'b1} );
wildcard state BLKSTORE_scrub ( {4'bx1xx, 1'b1, 1'b0, 1'bx, STORE_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b1, 1'b1} );
// BLKINITST vld diag pst2 reqtype nc jbi cputh inv pf bis
wildcard state BLKINITST_detect ( {4'bx0x1, 1'b1, 1'b0, 1'bx, STORE_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b1} );
wildcard state BLKINITST_report ( {4'b00x1, 1'b1, 1'b0, 1'bx, STORE_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b1} );
wildcard state BLKINITST_schedule( {4'b0001, 1'b1, 1'b0, 1'bx, STORE_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b1} );
wildcard state BLKINITST_scrub ( {4'bx1xx, 1'b1, 1'b0, 1'bx, STORE_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b1} );
// CAS1 vld diag pst2 reqtype nc jbi cputh inv pf bis
wildcard state CAS1_detect ( {4'bx0x1, 1'b1, 1'b0, 1'bx, CAS1_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
wildcard state CAS1_report ( {4'b00x1, 1'b1, 1'b0, 1'bx, CAS1_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
wildcard state CAS1_schedule( {4'b0001, 1'b1, 1'b0, 1'bx, CAS1_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
wildcard state CAS1_scrub ( {4'bx1xx, 1'b1, 1'b0, 1'bx, CAS1_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
// CAS2 vld diag pst2 reqtype nc jbi cputh inv pf bis
wildcard state CAS2_detect ( {4'bx0x1, 1'b1, 1'b0, 1'bx, CAS2_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
wildcard state CAS2_report ( {4'b00x1, 1'b1, 1'b0, 1'bx, CAS2_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
wildcard state CAS2_schedule( {4'b0001, 1'b1, 1'b0, 1'bx, CAS2_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
wildcard state CAS2_scrub ( {4'bx1xx, 1'b1, 1'b0, 1'bx, CAS2_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
// SWAP vld diag pst2 reqtype nc jbi cputh inv pf bis
wildcard state SWAP_detect ( {4'bx0x1, 1'b1, 1'b0, 1'b0, SWAP_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
wildcard state SWAP_report ( {4'b00x1, 1'b1, 1'b0, 1'b0, SWAP_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
wildcard state SWAP_schedule( {4'b0001, 1'b1, 1'b0, 1'b0, SWAP_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
wildcard state SWAP_scrub ( {4'bx1xx, 1'b1, 1'b0, 1'b0, SWAP_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
// SWAP (partial, 2nd pass) vld diag pst2 reqtype nc jbi cputh inv pf bis
wildcard state SWAPpst2_detect ( {4'bx0x1, 1'b1, 1'b0, 1'b1, SWAP_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
wildcard state SWAPpst2_report ( {4'b00x1, 1'b1, 1'b0, 1'b1, SWAP_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
wildcard state SWAPpst2_schedule( {4'b0001, 1'b1, 1'b0, 1'b1, SWAP_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
wildcard state SWAPpst2_scrub ( {4'bx1xx, 1'b1, 1'b0, 1'b1, SWAP_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
// STRLOAD vld diag pst2 reqtype nc jbi cputh inv pf bis
wildcard state STRLOAD_detect ( {4'bx0x1, 1'b1, 1'b0, 1'bx, STRLOAD_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
wildcard state STRLOAD_report ( {4'b00x1, 1'b1, 1'b0, 1'bx, STRLOAD_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
wildcard state STRLOAD_schedule( {4'b0001, 1'b1, 1'b0, 1'bx, STRLOAD_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
wildcard state STRLOAD_scrub ( {4'bx1xx, 1'b1, 1'b0, 1'bx, STRLOAD_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
// STRST vld diag pst2 reqtype nc jbi cputh inv pf bis
wildcard state STRST_detect ( {4'bx0x1, 1'b1, 1'b0, 1'b0, STRST_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
wildcard state STRST_report ( {4'b00x1, 1'b1, 1'b0, 1'b0, STRST_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
wildcard state STRST_schedule( {4'b0001, 1'b1, 1'b0, 1'b0, STRST_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
wildcard state STRST_scrub ( {4'bx1xx, 1'b1, 1'b0, 1'b0, STRST_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
// STRST (partial, 2nd pass) vld diag pst2 reqtype nc jbi cputh inv pf bis
wildcard state STRSTpst2_detect ( {4'bx0x1, 1'b1, 1'b0, 1'b1, STRST_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
wildcard state STRSTpst2_report ( {4'b00x1, 1'b1, 1'b0, 1'b1, STRST_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
wildcard state STRSTpst2_schedule( {4'b0001, 1'b1, 1'b0, 1'b1, STRST_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
wildcard state STRSTpst2_scrub ( {4'bx1xx, 1'b1, 1'b0, 1'b1, STRST_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
/*
// FWDRQ_LOAD vld diag pst2 reqtype nc jbi cputh inv pf bis
wildcard state FWDRQ_LOAD_detect ( {4'bx0x1, 1'b1, 1'b0, 1'bx, FWD_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
wildcard state FWDRQ_LOAD_report ( {4'b00x1, 1'b1, 1'b0, 1'bx, FWD_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
wildcard state FWDRQ_LOAD_schedule( {4'b0001, 1'b1, 1'b0, 1'bx, FWD_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
wildcard state FWDRQ_LOAD_scrub ( {4'bx1xx, 1'b1, 1'b0, 1'bx, FWD_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
// FWDRQ_STORE vld diag pst2 reqtype nc jbi cputh inv pf bis
wildcard state FWDRQ_STORE_detect ( {4'bx0x1, 1'b1, 1'b0, 1'bx, FWD_RQ, 1'b0, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
wildcard state FWDRQ_STORE_report ( {4'b00x1, 1'b1, 1'b0, 1'bx, FWD_RQ, 1'b0, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
wildcard state FWDRQ_STORE_schedule( {4'b0001, 1'b1, 1'b0, 1'bx, FWD_RQ, 1'b0, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
wildcard state FWDRQ_STORE_scrub ( {4'bx1xx, 1'b1, 1'b0, 1'bx, FWD_RQ, 1'b0, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
*/
// PREFETCH_ICE vld diag pst2 reqtype nc jbi cputh inv pf bis
wildcard state PFICE_detect ( {4'bx0x1, 1'b1, 1'b0, 1'bx, LOAD_RQ, 1'b1, 1'b0, 6'bx, 1'b1, 1'b1, 1'b0} );
wildcard state PFICE_report ( {4'b00x1, 1'b1, 1'b0, 1'bx, LOAD_RQ, 1'b1, 1'b0, 6'bx, 1'b1, 1'b1, 1'b0} );
wildcard state PFICE_schedule( {4'b0001, 1'b1, 1'b0, 1'bx, LOAD_RQ, 1'b1, 1'b0, 6'bx, 1'b1, 1'b1, 1'b0} );
wildcard state PFICE_scrub ( {4'bx1xx, 1'b1, 1'b0, 1'bx, LOAD_RQ, 1'b1, 1'b0, 6'bx, 1'b1, 1'b1, 1'b0} );
// RDD vld diag pst2 reqtype nc jbi
wildcard state RDD_detect ( {4'bx0x1, 1'b1, 1'b0, 1'bx, 5'bxx001, 1'b0, 1'b1, 9'bx} );
wildcard state RDD_report ( {4'b00x1, 1'b1, 1'b0, 1'bx, 5'bxx001, 1'b0, 1'b1, 9'bx} );
wildcard state RDD_schedule( {4'b0001, 1'b1, 1'b0, 1'bx, 5'bxx001, 1'b0, 1'b1, 9'bx} );
wildcard state RDD_scrub ( {4'bx1xx, 1'b1, 1'b0, 1'bx, 5'bxx001, 1'b0, 1'b1, 9'bx} );
// WR8 vld diag pst2 reqtype nc jbi
wildcard state WR8_detect ( {4'bx0x1, 1'b1, 1'b0, 1'b0, 5'bxx010, 1'b0, 1'b1, 9'bx} );
wildcard state WR8_report ( {4'b00x1, 1'b1, 1'b0, 1'b0, 5'bxx010, 1'b0, 1'b1, 9'bx} );
wildcard state WR8_schedule( {4'b0001, 1'b1, 1'b0, 1'b0, 5'bxx010, 1'b0, 1'b1, 9'bx} );
wildcard state WR8_scrub ( {4'bx1xx, 1'b1, 1'b0, 1'b0, 5'bxx010, 1'b0, 1'b1, 9'bx} );
// WR8 (partial, 2nd pass) vld diag pst2 reqtype nc jbi
wildcard state WR8pst2_detect ( {4'bx0x1, 1'b1, 1'b0, 1'b1, 5'bxx010, 1'b0, 1'b1, 9'bx} );
wildcard state WR8pst2_report ( {4'b00x1, 1'b1, 1'b0, 1'b1, 5'bxx010, 1'b0, 1'b1, 9'bx} );
wildcard state WR8pst2_schedule( {4'b0001, 1'b1, 1'b0, 1'b1, 5'bxx010, 1'b0, 1'b1, 9'bx} );
wildcard state WR8pst2_scrub ( {4'bx1xx, 1'b1, 1'b0, 1'b1, 5'bxx010, 1'b0, 1'b1, 9'bx} );
// WRI vld diag pst2 reqtype nc jbi
wildcard state WRI_detect ( {4'bx0x1, 1'b1, 1'b0, 1'bx, 5'bxx100, 1'b0, 1'b1, 9'bx} );
wildcard state WRI_report ( {4'b00x1, 1'b1, 1'b0, 1'bx, 5'bxx100, 1'b0, 1'b1, 9'bx} );
wildcard state WRI_schedule( {4'b0001, 1'b1, 1'b0, 1'bx, 5'bxx100, 1'b0, 1'b1, 9'bx} );
wildcard state WRI_scrub ( {4'bx1xx, 1'b1, 1'b0, 1'bx, 5'bxx100, 1'b0, 1'b1, 9'bx} );