verif/env/common/coverage/l2sat/l2_fill_complete_sample.vrhpal

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//
// OpenSPARC T2 Processor File: l2_fill_complete_sample.vrhpal
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wildcard state dec_fill_entry_0       ( {8'b00000001, 8'b0, 3'b0xx} );
wildcard state dec_fill_entry_1       ( {8'b00000010, 8'b0, 3'b0xx} );
wildcard state dec_fill_entry_2       ( {8'b00000100, 8'b0, 3'b0xx} );
wildcard state dec_fill_entry_3       ( {8'b00001000, 8'b0, 3'b0xx} );
wildcard state dec_fill_entry_4       ( {8'b00010000, 8'b0, 3'b0xx} );
wildcard state dec_fill_entry_5       ( {8'b00100000, 8'b0, 3'b0xx} );
wildcard state dec_fill_entry_6       ( {8'b01000000, 8'b0, 3'b0xx} );
wildcard state dec_fill_entry_7       ( {8'b10000000, 8'b0, 3'b0xx} );
wildcard state no_fill_entry_dequeue_0( {8'b0, 8'b00000001, 3'b0xx} );
wildcard state no_fill_entry_dequeue_1( {8'b0, 8'b00000010, 3'b0xx} );
wildcard state no_fill_entry_dequeue_2( {8'b0, 8'b00000100, 3'b0xx} );
wildcard state no_fill_entry_dequeue_3( {8'b0, 8'b00001000, 3'b0xx} );
wildcard state no_fill_entry_dequeue_4( {8'b0, 8'b00010000, 3'b0xx} );
wildcard state no_fill_entry_dequeue_5( {8'b0, 8'b00100000, 3'b0xx} );
wildcard state no_fill_entry_dequeue_6( {8'b0, 8'b01000000, 3'b0xx} );
wildcard state no_fill_entry_dequeue_7( {8'b0, 8'b10000000, 3'b0xx} );
wildcard state en_hit_dequeue_0       ( {8'b0, 8'b0, 3'b10x} );
wildcard state en_hit_dequeue_1       ( {8'b0, 8'b0, 3'b1x0} );