// ========== Copyright Header Begin ==========================================
// OpenSPARC T2 Processor File: l2sat_cov.if.vrhpal
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
// For the avoidance of doubt, and except that if any non-GPL license
// choice is available it will apply instead, Sun elects to use only
// the General Public License version 2 (GPLv2) at this time for any
// software where a choice of GPL license versions is made
// available with the language indicating that GPLv2 or any later version
// may be used, or where a choice of which version of the GPL is applied is
// otherwise unspecified.
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
// CA 95054 USA or visit www.sun.com if you need additional information or
// ========== Copyright Header End ============================================
#ifndef __L2SAT_COV_IF_VRH__
#define __L2SAT_COV_IF_VRH__
#include <vera_defines.vrh>
#define OUTPUT_EDGE PHOLD
#define INPUT_EDGE PSAMPLE
interface l2sat_coverage_ifc
// Common & Clock Signals
// This clock declaration allows referencing "l2sat_coverage_ifc.clock"
input clock CLOCK verilog_node "`TOP.cpu.l2t0.gclk";
input reset INPUT_EDGE INPUT_SKEW verilog_node "`TOP.reset";
input clock CLOCK verilog_node "l2sat_top.clock";
input reset INPUT_EDGE INPUT_SKEW verilog_node "l2sat_top.reset";
input cmp_diag_done PSAMPLE;
//for l2sat_ccx_cpx_req_samp
input [7:0] spc7_pcx_req PSAMPLE #-3 verilog_node "$CCX_PATH.spc7_pcx_req_pq";
input [7:0] spc6_pcx_req PSAMPLE #-3 verilog_node "$CCX_PATH.spc6_pcx_req_pq";
input [7:0] spc5_pcx_req PSAMPLE #-3 verilog_node "$CCX_PATH.spc5_pcx_req_pq";
input [7:0] spc4_pcx_req PSAMPLE #-3 verilog_node "$CCX_PATH.spc4_pcx_req_pq";
input [7:0] spc3_pcx_req PSAMPLE #-3 verilog_node "$CCX_PATH.spc3_pcx_req_pq";
input [7:0] spc2_pcx_req PSAMPLE #-3 verilog_node "$CCX_PATH.spc2_pcx_req_pq";
input [7:0] spc1_pcx_req PSAMPLE #-3 verilog_node "$CCX_PATH.spc1_pcx_req_pq";
input [7:0] spc0_pcx_req PSAMPLE #-3 verilog_node "$CCX_PATH.spc0_pcx_req_pq";
input [7:0] spc7_pcx_req_d1 PSAMPLE #-3 verilog_node "`TOP.spc7_pcx_req_d1";
input [7:0] spc7_pcx_req_d2 PSAMPLE #-3 verilog_node "`TOP.spc7_pcx_req_d2";
input [7:0] spc7_pcx_req_d3 PSAMPLE #-3 verilog_node "`TOP.spc7_pcx_req_d3";
input [7:0] spc7_pcx_req_d4 PSAMPLE #-3 verilog_node "`TOP.spc7_pcx_req_d4";
input [7:0] spc7_pcx_req_d5 PSAMPLE #-3 verilog_node "`TOP.spc7_pcx_req_d5";
input [7:0] spc7_pcx_req_d6 PSAMPLE #-3 verilog_node "`TOP.spc7_pcx_req_d6";
input [7:0] spc7_pcx_req_d7 PSAMPLE #-3 verilog_node "`TOP.spc7_pcx_req_d7";
input [7:0] spc7_pcx_req_d8 PSAMPLE #-3 verilog_node "`TOP.spc7_pcx_req_d8";
input [7:0] spc7_pcx_req_d9 PSAMPLE #-3 verilog_node "`TOP.spc7_pcx_req_d9";
input [7:0] spc7_pcx_req_d10 PSAMPLE #-3 verilog_node "`TOP.spc7_pcx_req_d10";
input [7:0] spc6_pcx_req_d1 PSAMPLE #-3 verilog_node "`TOP.spc6_pcx_req_d1";
input [7:0] spc6_pcx_req_d2 PSAMPLE #-3 verilog_node "`TOP.spc6_pcx_req_d2";
input [7:0] spc6_pcx_req_d3 PSAMPLE #-3 verilog_node "`TOP.spc6_pcx_req_d3";
input [7:0] spc6_pcx_req_d4 PSAMPLE #-3 verilog_node "`TOP.spc6_pcx_req_d4";
input [7:0] spc6_pcx_req_d5 PSAMPLE #-3 verilog_node "`TOP.spc6_pcx_req_d5";
input [7:0] spc6_pcx_req_d6 PSAMPLE #-3 verilog_node "`TOP.spc6_pcx_req_d6";
input [7:0] spc6_pcx_req_d7 PSAMPLE #-3 verilog_node "`TOP.spc6_pcx_req_d7";
input [7:0] spc6_pcx_req_d8 PSAMPLE #-3 verilog_node "`TOP.spc6_pcx_req_d8";
input [7:0] spc6_pcx_req_d9 PSAMPLE #-3 verilog_node "`TOP.spc6_pcx_req_d9";
input [7:0] spc6_pcx_req_d10 PSAMPLE #-3 verilog_node "`TOP.spc6_pcx_req_d10";
input [7:0] spc5_pcx_req_d1 PSAMPLE #-3 verilog_node "`TOP.spc5_pcx_req_d1";
input [7:0] spc5_pcx_req_d2 PSAMPLE #-3 verilog_node "`TOP.spc5_pcx_req_d2";
input [7:0] spc5_pcx_req_d3 PSAMPLE #-3 verilog_node "`TOP.spc5_pcx_req_d3";
input [7:0] spc5_pcx_req_d4 PSAMPLE #-3 verilog_node "`TOP.spc5_pcx_req_d4";
input [7:0] spc5_pcx_req_d5 PSAMPLE #-3 verilog_node "`TOP.spc5_pcx_req_d5";
input [7:0] spc5_pcx_req_d6 PSAMPLE #-3 verilog_node "`TOP.spc5_pcx_req_d6";
input [7:0] spc5_pcx_req_d7 PSAMPLE #-3 verilog_node "`TOP.spc5_pcx_req_d7";
input [7:0] spc5_pcx_req_d8 PSAMPLE #-3 verilog_node "`TOP.spc5_pcx_req_d8";
input [7:0] spc5_pcx_req_d9 PSAMPLE #-3 verilog_node "`TOP.spc5_pcx_req_d9";
input [7:0] spc5_pcx_req_d10 PSAMPLE #-3 verilog_node "`TOP.spc5_pcx_req_d10";
input [7:0] spc4_pcx_req_d1 PSAMPLE #-3 verilog_node "`TOP.spc4_pcx_req_d1";
input [7:0] spc4_pcx_req_d2 PSAMPLE #-3 verilog_node "`TOP.spc4_pcx_req_d2";
input [7:0] spc4_pcx_req_d3 PSAMPLE #-3 verilog_node "`TOP.spc4_pcx_req_d3";
input [7:0] spc4_pcx_req_d4 PSAMPLE #-3 verilog_node "`TOP.spc4_pcx_req_d4";
input [7:0] spc4_pcx_req_d5 PSAMPLE #-3 verilog_node "`TOP.spc4_pcx_req_d5";
input [7:0] spc4_pcx_req_d6 PSAMPLE #-3 verilog_node "`TOP.spc4_pcx_req_d6";
input [7:0] spc4_pcx_req_d7 PSAMPLE #-3 verilog_node "`TOP.spc4_pcx_req_d7";
input [7:0] spc4_pcx_req_d8 PSAMPLE #-3 verilog_node "`TOP.spc4_pcx_req_d8";
input [7:0] spc4_pcx_req_d9 PSAMPLE #-3 verilog_node "`TOP.spc4_pcx_req_d9";
input [7:0] spc4_pcx_req_d10 PSAMPLE #-3 verilog_node "`TOP.spc4_pcx_req_d10";
input [7:0] spc3_pcx_req_d1 PSAMPLE #-3 verilog_node "`TOP.spc3_pcx_req_d1";
input [7:0] spc3_pcx_req_d2 PSAMPLE #-3 verilog_node "`TOP.spc3_pcx_req_d2";
input [7:0] spc3_pcx_req_d3 PSAMPLE #-3 verilog_node "`TOP.spc3_pcx_req_d3";
input [7:0] spc3_pcx_req_d4 PSAMPLE #-3 verilog_node "`TOP.spc3_pcx_req_d4";
input [7:0] spc3_pcx_req_d5 PSAMPLE #-3 verilog_node "`TOP.spc3_pcx_req_d5";
input [7:0] spc3_pcx_req_d6 PSAMPLE #-3 verilog_node "`TOP.spc3_pcx_req_d6";
input [7:0] spc3_pcx_req_d7 PSAMPLE #-3 verilog_node "`TOP.spc3_pcx_req_d7";
input [7:0] spc3_pcx_req_d8 PSAMPLE #-3 verilog_node "`TOP.spc3_pcx_req_d8";
input [7:0] spc3_pcx_req_d9 PSAMPLE #-3 verilog_node "`TOP.spc3_pcx_req_d9";
input [7:0] spc3_pcx_req_d10 PSAMPLE #-3 verilog_node "`TOP.spc3_pcx_req_d10";
input [7:0] spc2_pcx_req_d1 PSAMPLE #-3 verilog_node "`TOP.spc2_pcx_req_d1";
input [7:0] spc2_pcx_req_d2 PSAMPLE #-3 verilog_node "`TOP.spc2_pcx_req_d2";
input [7:0] spc2_pcx_req_d3 PSAMPLE #-3 verilog_node "`TOP.spc2_pcx_req_d3";
input [7:0] spc2_pcx_req_d4 PSAMPLE #-3 verilog_node "`TOP.spc2_pcx_req_d4";
input [7:0] spc2_pcx_req_d5 PSAMPLE #-3 verilog_node "`TOP.spc2_pcx_req_d5";
input [7:0] spc2_pcx_req_d6 PSAMPLE #-3 verilog_node "`TOP.spc2_pcx_req_d6";
input [7:0] spc2_pcx_req_d7 PSAMPLE #-3 verilog_node "`TOP.spc2_pcx_req_d7";
input [7:0] spc2_pcx_req_d8 PSAMPLE #-3 verilog_node "`TOP.spc2_pcx_req_d8";
input [7:0] spc2_pcx_req_d9 PSAMPLE #-3 verilog_node "`TOP.spc2_pcx_req_d9";
input [7:0] spc2_pcx_req_d10 PSAMPLE #-3 verilog_node "`TOP.spc2_pcx_req_d10";
input [7:0] spc1_pcx_req_d1 PSAMPLE #-3 verilog_node "`TOP.spc1_pcx_req_d1";
input [7:0] spc1_pcx_req_d2 PSAMPLE #-3 verilog_node "`TOP.spc1_pcx_req_d2";
input [7:0] spc1_pcx_req_d3 PSAMPLE #-3 verilog_node "`TOP.spc1_pcx_req_d3";
input [7:0] spc1_pcx_req_d4 PSAMPLE #-3 verilog_node "`TOP.spc1_pcx_req_d4";
input [7:0] spc1_pcx_req_d5 PSAMPLE #-3 verilog_node "`TOP.spc1_pcx_req_d5";
input [7:0] spc1_pcx_req_d6 PSAMPLE #-3 verilog_node "`TOP.spc1_pcx_req_d6";
input [7:0] spc1_pcx_req_d7 PSAMPLE #-3 verilog_node "`TOP.spc1_pcx_req_d7";
input [7:0] spc1_pcx_req_d8 PSAMPLE #-3 verilog_node "`TOP.spc1_pcx_req_d8";
input [7:0] spc1_pcx_req_d9 PSAMPLE #-3 verilog_node "`TOP.spc1_pcx_req_d9";
input [7:0] spc1_pcx_req_d10 PSAMPLE #-3 verilog_node "`TOP.spc1_pcx_req_d10";
input [7:0] spc0_pcx_req_d1 PSAMPLE #-3 verilog_node "`TOP.spc0_pcx_req_d1";
input [7:0] spc0_pcx_req_d2 PSAMPLE #-3 verilog_node "`TOP.spc0_pcx_req_d2";
input [7:0] spc0_pcx_req_d3 PSAMPLE #-3 verilog_node "`TOP.spc0_pcx_req_d3";
input [7:0] spc0_pcx_req_d4 PSAMPLE #-3 verilog_node "`TOP.spc0_pcx_req_d4";
input [7:0] spc0_pcx_req_d5 PSAMPLE #-3 verilog_node "`TOP.spc0_pcx_req_d5";
input [7:0] spc0_pcx_req_d6 PSAMPLE #-3 verilog_node "`TOP.spc0_pcx_req_d6";
input [7:0] spc0_pcx_req_d7 PSAMPLE #-3 verilog_node "`TOP.spc0_pcx_req_d7";
input [7:0] spc0_pcx_req_d8 PSAMPLE #-3 verilog_node "`TOP.spc0_pcx_req_d8";
input [7:0] spc0_pcx_req_d9 PSAMPLE #-3 verilog_node "`TOP.spc0_pcx_req_d9";
input [7:0] spc0_pcx_req_d10 PSAMPLE #-3 verilog_node "`TOP.spc0_pcx_req_d10";
input [7:0] spc7_pcx_atm_d1 PSAMPLE #-3 verilog_node "`TOP.spc7_pcx_atm_d1";
input [7:0] spc7_pcx_atm_d2 PSAMPLE #-3 verilog_node "`TOP.spc7_pcx_atm_d2";
input [7:0] spc7_pcx_atm_d3 PSAMPLE #-3 verilog_node "`TOP.spc7_pcx_atm_d3";
input [7:0] spc7_pcx_atm_d4 PSAMPLE #-3 verilog_node "`TOP.spc7_pcx_atm_d4";
input [7:0] spc7_pcx_atm_d5 PSAMPLE #-3 verilog_node "`TOP.spc7_pcx_atm_d5";
input [7:0] spc7_pcx_atm_d6 PSAMPLE #-3 verilog_node "`TOP.spc7_pcx_atm_d6";
input [7:0] spc7_pcx_atm_d7 PSAMPLE #-3 verilog_node "`TOP.spc7_pcx_atm_d7";
input [7:0] spc7_pcx_atm_d8 PSAMPLE #-3 verilog_node "`TOP.spc7_pcx_atm_d8";
input [7:0] spc7_pcx_atm_d9 PSAMPLE #-3 verilog_node "`TOP.spc7_pcx_atm_d9";
input [7:0] spc7_pcx_atm_d10 PSAMPLE #-3 verilog_node "`TOP.spc7_pcx_atm_d10";
input [7:0] spc6_pcx_atm_d1 PSAMPLE #-3 verilog_node "`TOP.spc6_pcx_atm_d1";
input [7:0] spc6_pcx_atm_d2 PSAMPLE #-3 verilog_node "`TOP.spc6_pcx_atm_d2";
input [7:0] spc6_pcx_atm_d3 PSAMPLE #-3 verilog_node "`TOP.spc6_pcx_atm_d3";
input [7:0] spc6_pcx_atm_d4 PSAMPLE #-3 verilog_node "`TOP.spc6_pcx_atm_d4";
input [7:0] spc6_pcx_atm_d5 PSAMPLE #-3 verilog_node "`TOP.spc6_pcx_atm_d5";
input [7:0] spc6_pcx_atm_d6 PSAMPLE #-3 verilog_node "`TOP.spc6_pcx_atm_d6";
input [7:0] spc6_pcx_atm_d7 PSAMPLE #-3 verilog_node "`TOP.spc6_pcx_atm_d7";
input [7:0] spc6_pcx_atm_d8 PSAMPLE #-3 verilog_node "`TOP.spc6_pcx_atm_d8";
input [7:0] spc6_pcx_atm_d9 PSAMPLE #-3 verilog_node "`TOP.spc6_pcx_atm_d9";
input [7:0] spc6_pcx_atm_d10 PSAMPLE #-3 verilog_node "`TOP.spc6_pcx_atm_d10";
input [7:0] spc5_pcx_atm_d1 PSAMPLE #-3 verilog_node "`TOP.spc5_pcx_atm_d1";
input [7:0] spc5_pcx_atm_d2 PSAMPLE #-3 verilog_node "`TOP.spc5_pcx_atm_d2";
input [7:0] spc5_pcx_atm_d3 PSAMPLE #-3 verilog_node "`TOP.spc5_pcx_atm_d3";
input [7:0] spc5_pcx_atm_d4 PSAMPLE #-3 verilog_node "`TOP.spc5_pcx_atm_d4";
input [7:0] spc5_pcx_atm_d5 PSAMPLE #-3 verilog_node "`TOP.spc5_pcx_atm_d5";
input [7:0] spc5_pcx_atm_d6 PSAMPLE #-3 verilog_node "`TOP.spc5_pcx_atm_d6";
input [7:0] spc5_pcx_atm_d7 PSAMPLE #-3 verilog_node "`TOP.spc5_pcx_atm_d7";
input [7:0] spc5_pcx_atm_d8 PSAMPLE #-3 verilog_node "`TOP.spc5_pcx_atm_d8";
input [7:0] spc5_pcx_atm_d9 PSAMPLE #-3 verilog_node "`TOP.spc5_pcx_atm_d9";
input [7:0] spc5_pcx_atm_d10 PSAMPLE #-3 verilog_node "`TOP.spc5_pcx_atm_d10";
input [7:0] spc4_pcx_atm_d1 PSAMPLE #-3 verilog_node "`TOP.spc4_pcx_atm_d1";
input [7:0] spc4_pcx_atm_d2 PSAMPLE #-3 verilog_node "`TOP.spc4_pcx_atm_d2";
input [7:0] spc4_pcx_atm_d3 PSAMPLE #-3 verilog_node "`TOP.spc4_pcx_atm_d3";
input [7:0] spc4_pcx_atm_d4 PSAMPLE #-3 verilog_node "`TOP.spc4_pcx_atm_d4";
input [7:0] spc4_pcx_atm_d5 PSAMPLE #-3 verilog_node "`TOP.spc4_pcx_atm_d5";
input [7:0] spc4_pcx_atm_d6 PSAMPLE #-3 verilog_node "`TOP.spc4_pcx_atm_d6";
input [7:0] spc4_pcx_atm_d7 PSAMPLE #-3 verilog_node "`TOP.spc4_pcx_atm_d7";
input [7:0] spc4_pcx_atm_d8 PSAMPLE #-3 verilog_node "`TOP.spc4_pcx_atm_d8";
input [7:0] spc4_pcx_atm_d9 PSAMPLE #-3 verilog_node "`TOP.spc4_pcx_atm_d9";
input [7:0] spc4_pcx_atm_d10 PSAMPLE #-3 verilog_node "`TOP.spc4_pcx_atm_d10";
input [7:0] spc3_pcx_atm_d1 PSAMPLE #-3 verilog_node "`TOP.spc3_pcx_atm_d1";
input [7:0] spc3_pcx_atm_d2 PSAMPLE #-3 verilog_node "`TOP.spc3_pcx_atm_d2";
input [7:0] spc3_pcx_atm_d3 PSAMPLE #-3 verilog_node "`TOP.spc3_pcx_atm_d3";
input [7:0] spc3_pcx_atm_d4 PSAMPLE #-3 verilog_node "`TOP.spc3_pcx_atm_d4";
input [7:0] spc3_pcx_atm_d5 PSAMPLE #-3 verilog_node "`TOP.spc3_pcx_atm_d5";
input [7:0] spc3_pcx_atm_d6 PSAMPLE #-3 verilog_node "`TOP.spc3_pcx_atm_d6";
input [7:0] spc3_pcx_atm_d7 PSAMPLE #-3 verilog_node "`TOP.spc3_pcx_atm_d7";
input [7:0] spc3_pcx_atm_d8 PSAMPLE #-3 verilog_node "`TOP.spc3_pcx_atm_d8";
input [7:0] spc3_pcx_atm_d9 PSAMPLE #-3 verilog_node "`TOP.spc3_pcx_atm_d9";
input [7:0] spc3_pcx_atm_d10 PSAMPLE #-3 verilog_node "`TOP.spc3_pcx_atm_d10";
input [7:0] spc2_pcx_atm_d1 PSAMPLE #-3 verilog_node "`TOP.spc2_pcx_atm_d1";
input [7:0] spc2_pcx_atm_d2 PSAMPLE #-3 verilog_node "`TOP.spc2_pcx_atm_d2";
input [7:0] spc2_pcx_atm_d3 PSAMPLE #-3 verilog_node "`TOP.spc2_pcx_atm_d3";
input [7:0] spc2_pcx_atm_d4 PSAMPLE #-3 verilog_node "`TOP.spc2_pcx_atm_d4";
input [7:0] spc2_pcx_atm_d5 PSAMPLE #-3 verilog_node "`TOP.spc2_pcx_atm_d5";
input [7:0] spc2_pcx_atm_d6 PSAMPLE #-3 verilog_node "`TOP.spc2_pcx_atm_d6";
input [7:0] spc2_pcx_atm_d7 PSAMPLE #-3 verilog_node "`TOP.spc2_pcx_atm_d7";
input [7:0] spc2_pcx_atm_d8 PSAMPLE #-3 verilog_node "`TOP.spc2_pcx_atm_d8";
input [7:0] spc2_pcx_atm_d9 PSAMPLE #-3 verilog_node "`TOP.spc2_pcx_atm_d9";
input [7:0] spc2_pcx_atm_d10 PSAMPLE #-3 verilog_node "`TOP.spc2_pcx_atm_d10";
input [7:0] spc1_pcx_atm_d1 PSAMPLE #-3 verilog_node "`TOP.spc1_pcx_atm_d1";
input [7:0] spc1_pcx_atm_d2 PSAMPLE #-3 verilog_node "`TOP.spc1_pcx_atm_d2";
input [7:0] spc1_pcx_atm_d3 PSAMPLE #-3 verilog_node "`TOP.spc1_pcx_atm_d3";
input [7:0] spc1_pcx_atm_d4 PSAMPLE #-3 verilog_node "`TOP.spc1_pcx_atm_d4";
input [7:0] spc1_pcx_atm_d5 PSAMPLE #-3 verilog_node "`TOP.spc1_pcx_atm_d5";
input [7:0] spc1_pcx_atm_d6 PSAMPLE #-3 verilog_node "`TOP.spc1_pcx_atm_d6";
input [7:0] spc1_pcx_atm_d7 PSAMPLE #-3 verilog_node "`TOP.spc1_pcx_atm_d7";
input [7:0] spc1_pcx_atm_d8 PSAMPLE #-3 verilog_node "`TOP.spc1_pcx_atm_d8";
input [7:0] spc1_pcx_atm_d9 PSAMPLE #-3 verilog_node "`TOP.spc1_pcx_atm_d9";
input [7:0] spc1_pcx_atm_d10 PSAMPLE #-3 verilog_node "`TOP.spc1_pcx_atm_d10";
input [7:0] spc0_pcx_atm_d1 PSAMPLE #-3 verilog_node "`TOP.spc0_pcx_atm_d1";
input [7:0] spc0_pcx_atm_d2 PSAMPLE #-3 verilog_node "`TOP.spc0_pcx_atm_d2";
input [7:0] spc0_pcx_atm_d3 PSAMPLE #-3 verilog_node "`TOP.spc0_pcx_atm_d3";
input [7:0] spc0_pcx_atm_d4 PSAMPLE #-3 verilog_node "`TOP.spc0_pcx_atm_d4";
input [7:0] spc0_pcx_atm_d5 PSAMPLE #-3 verilog_node "`TOP.spc0_pcx_atm_d5";
input [7:0] spc0_pcx_atm_d6 PSAMPLE #-3 verilog_node "`TOP.spc0_pcx_atm_d6";
input [7:0] spc0_pcx_atm_d7 PSAMPLE #-3 verilog_node "`TOP.spc0_pcx_atm_d7";
input [7:0] spc0_pcx_atm_d8 PSAMPLE #-3 verilog_node "`TOP.spc0_pcx_atm_d8";
input [7:0] spc0_pcx_atm_d9 PSAMPLE #-3 verilog_node "`TOP.spc0_pcx_atm_d9";
input [7:0] spc0_pcx_atm_d10 PSAMPLE #-3 verilog_node "`TOP.spc0_pcx_atm_d10";
input [7:0] l2t7_cpx_req_d1 PSAMPLE #-3 verilog_node "`TOP.l2t7_cpx_req_d1";
input [7:0] l2t7_cpx_req_d2 PSAMPLE #-3 verilog_node "`TOP.l2t7_cpx_req_d2";
input [7:0] l2t7_cpx_req_d3 PSAMPLE #-3 verilog_node "`TOP.l2t7_cpx_req_d3";
input [7:0] l2t7_cpx_req_d4 PSAMPLE #-3 verilog_node "`TOP.l2t7_cpx_req_d4";
input [7:0] l2t6_cpx_req_d1 PSAMPLE #-3 verilog_node "`TOP.l2t6_cpx_req_d1";
input [7:0] l2t6_cpx_req_d2 PSAMPLE #-3 verilog_node "`TOP.l2t6_cpx_req_d2";
input [7:0] l2t6_cpx_req_d3 PSAMPLE #-3 verilog_node "`TOP.l2t6_cpx_req_d3";
input [7:0] l2t6_cpx_req_d4 PSAMPLE #-3 verilog_node "`TOP.l2t6_cpx_req_d4";
input [7:0] l2t5_cpx_req_d1 PSAMPLE #-3 verilog_node "`TOP.l2t5_cpx_req_d1";
input [7:0] l2t5_cpx_req_d2 PSAMPLE #-3 verilog_node "`TOP.l2t5_cpx_req_d2";
input [7:0] l2t5_cpx_req_d3 PSAMPLE #-3 verilog_node "`TOP.l2t5_cpx_req_d3";
input [7:0] l2t5_cpx_req_d4 PSAMPLE #-3 verilog_node "`TOP.l2t5_cpx_req_d4";
input [7:0] l2t4_cpx_req_d1 PSAMPLE #-3 verilog_node "`TOP.l2t4_cpx_req_d1";
input [7:0] l2t4_cpx_req_d2 PSAMPLE #-3 verilog_node "`TOP.l2t4_cpx_req_d2";
input [7:0] l2t4_cpx_req_d3 PSAMPLE #-3 verilog_node "`TOP.l2t4_cpx_req_d3";
input [7:0] l2t4_cpx_req_d4 PSAMPLE #-3 verilog_node "`TOP.l2t4_cpx_req_d4";
input [7:0] l2t3_cpx_req_d1 PSAMPLE #-3 verilog_node "`TOP.l2t3_cpx_req_d1";
input [7:0] l2t3_cpx_req_d2 PSAMPLE #-3 verilog_node "`TOP.l2t3_cpx_req_d2";
input [7:0] l2t3_cpx_req_d3 PSAMPLE #-3 verilog_node "`TOP.l2t3_cpx_req_d3";
input [7:0] l2t3_cpx_req_d4 PSAMPLE #-3 verilog_node "`TOP.l2t3_cpx_req_d4";
input [7:0] l2t2_cpx_req_d1 PSAMPLE #-3 verilog_node "`TOP.l2t2_cpx_req_d1";
input [7:0] l2t2_cpx_req_d2 PSAMPLE #-3 verilog_node "`TOP.l2t2_cpx_req_d2";
input [7:0] l2t2_cpx_req_d3 PSAMPLE #-3 verilog_node "`TOP.l2t2_cpx_req_d3";
input [7:0] l2t2_cpx_req_d4 PSAMPLE #-3 verilog_node "`TOP.l2t2_cpx_req_d4";
input [7:0] l2t1_cpx_req_d1 PSAMPLE #-3 verilog_node "`TOP.l2t1_cpx_req_d1";
input [7:0] l2t1_cpx_req_d2 PSAMPLE #-3 verilog_node "`TOP.l2t1_cpx_req_d2";
input [7:0] l2t1_cpx_req_d3 PSAMPLE #-3 verilog_node "`TOP.l2t1_cpx_req_d3";
input [7:0] l2t1_cpx_req_d4 PSAMPLE #-3 verilog_node "`TOP.l2t1_cpx_req_d4";
input [7:0] l2t0_cpx_req_d1 PSAMPLE #-3 verilog_node "`TOP.l2t0_cpx_req_d1";
input [7:0] l2t0_cpx_req_d2 PSAMPLE #-3 verilog_node "`TOP.l2t0_cpx_req_d2";
input [7:0] l2t0_cpx_req_d3 PSAMPLE #-3 verilog_node "`TOP.l2t0_cpx_req_d3";
input [7:0] l2t0_cpx_req_d4 PSAMPLE #-3 verilog_node "`TOP.l2t0_cpx_req_d4";
input [7:0] l2t7_cpx_atom_d1 PSAMPLE #-3 verilog_node "`TOP.l2t7_cpx_atom_d1";
input [7:0] l2t7_cpx_atom_d2 PSAMPLE #-3 verilog_node "`TOP.l2t7_cpx_atom_d2";
input [7:0] l2t7_cpx_atom_d3 PSAMPLE #-3 verilog_node "`TOP.l2t7_cpx_atom_d3";
input [7:0] l2t7_cpx_atom_d4 PSAMPLE #-3 verilog_node "`TOP.l2t7_cpx_atom_d4";
input [7:0] l2t6_cpx_atom_d1 PSAMPLE #-3 verilog_node "`TOP.l2t6_cpx_atom_d1";
input [7:0] l2t6_cpx_atom_d2 PSAMPLE #-3 verilog_node "`TOP.l2t6_cpx_atom_d2";
input [7:0] l2t6_cpx_atom_d3 PSAMPLE #-3 verilog_node "`TOP.l2t6_cpx_atom_d3";
input [7:0] l2t6_cpx_atom_d4 PSAMPLE #-3 verilog_node "`TOP.l2t6_cpx_atom_d4";
input [7:0] l2t5_cpx_atom_d1 PSAMPLE #-3 verilog_node "`TOP.l2t5_cpx_atom_d1";
input [7:0] l2t5_cpx_atom_d2 PSAMPLE #-3 verilog_node "`TOP.l2t5_cpx_atom_d2";
input [7:0] l2t5_cpx_atom_d3 PSAMPLE #-3 verilog_node "`TOP.l2t5_cpx_atom_d3";
input [7:0] l2t5_cpx_atom_d4 PSAMPLE #-3 verilog_node "`TOP.l2t5_cpx_atom_d4";
input [7:0] l2t4_cpx_atom_d1 PSAMPLE #-3 verilog_node "`TOP.l2t4_cpx_atom_d1";
input [7:0] l2t4_cpx_atom_d2 PSAMPLE #-3 verilog_node "`TOP.l2t4_cpx_atom_d2";
input [7:0] l2t4_cpx_atom_d3 PSAMPLE #-3 verilog_node "`TOP.l2t4_cpx_atom_d3";
input [7:0] l2t4_cpx_atom_d4 PSAMPLE #-3 verilog_node "`TOP.l2t4_cpx_atom_d4";
input [7:0] l2t3_cpx_atom_d1 PSAMPLE #-3 verilog_node "`TOP.l2t3_cpx_atom_d1";
input [7:0] l2t3_cpx_atom_d2 PSAMPLE #-3 verilog_node "`TOP.l2t3_cpx_atom_d2";
input [7:0] l2t3_cpx_atom_d3 PSAMPLE #-3 verilog_node "`TOP.l2t3_cpx_atom_d3";
input [7:0] l2t3_cpx_atom_d4 PSAMPLE #-3 verilog_node "`TOP.l2t3_cpx_atom_d4";
input [7:0] l2t2_cpx_atom_d1 PSAMPLE #-3 verilog_node "`TOP.l2t2_cpx_atom_d1";
input [7:0] l2t2_cpx_atom_d2 PSAMPLE #-3 verilog_node "`TOP.l2t2_cpx_atom_d2";
input [7:0] l2t2_cpx_atom_d3 PSAMPLE #-3 verilog_node "`TOP.l2t2_cpx_atom_d3";
input [7:0] l2t2_cpx_atom_d4 PSAMPLE #-3 verilog_node "`TOP.l2t2_cpx_atom_d4";
input [7:0] l2t1_cpx_atom_d1 PSAMPLE #-3 verilog_node "`TOP.l2t1_cpx_atom_d1";
input [7:0] l2t1_cpx_atom_d2 PSAMPLE #-3 verilog_node "`TOP.l2t1_cpx_atom_d2";
input [7:0] l2t1_cpx_atom_d3 PSAMPLE #-3 verilog_node "`TOP.l2t1_cpx_atom_d3";
input [7:0] l2t1_cpx_atom_d4 PSAMPLE #-3 verilog_node "`TOP.l2t1_cpx_atom_d4";
input [7:0] l2t0_cpx_atom_d1 PSAMPLE #-3 verilog_node "`TOP.l2t0_cpx_atom_d1";
input [7:0] l2t0_cpx_atom_d2 PSAMPLE #-3 verilog_node "`TOP.l2t0_cpx_atom_d2";
input [7:0] l2t0_cpx_atom_d3 PSAMPLE #-3 verilog_node "`TOP.l2t0_cpx_atom_d3";
input [7:0] l2t0_cpx_atom_d4 PSAMPLE #-3 verilog_node "`TOP.l2t0_cpx_atom_d4";
input [7:0] spc7_pcx_atm PSAMPLE #-3 verilog_node "$CCX_PATH.spc7_pcx_atm_pq";
input [7:0] spc6_pcx_atm PSAMPLE #-3 verilog_node "$CCX_PATH.spc6_pcx_atm_pq";
input [7:0] spc5_pcx_atm PSAMPLE #-3 verilog_node "$CCX_PATH.spc5_pcx_atm_pq";
input [7:0] spc4_pcx_atm PSAMPLE #-3 verilog_node "$CCX_PATH.spc4_pcx_atm_pq";
input [7:0] spc3_pcx_atm PSAMPLE #-3 verilog_node "$CCX_PATH.spc3_pcx_atm_pq";
input [7:0] spc2_pcx_atm PSAMPLE #-3 verilog_node "$CCX_PATH.spc2_pcx_atm_pq";
input [7:0] spc1_pcx_atm PSAMPLE #-3 verilog_node "$CCX_PATH.spc1_pcx_atm_pq";
input [7:0] spc0_pcx_atm PSAMPLE #-3 verilog_node "$CCX_PATH.spc0_pcx_atm_pq";
//for l2sat_ccx_cpx_req_samp
input [7:0] l2t7_cpx_req PSAMPLE #-3 verilog_node "$CCX_PATH.sctag7_cpx_req_cq";
input [7:0] l2t6_cpx_req PSAMPLE #-3 verilog_node "$CCX_PATH.sctag6_cpx_req_cq";
input [7:0] l2t5_cpx_req PSAMPLE #-3 verilog_node "$CCX_PATH.sctag5_cpx_req_cq";
input [7:0] l2t4_cpx_req PSAMPLE #-3 verilog_node "$CCX_PATH.sctag4_cpx_req_cq";
input [7:0] l2t3_cpx_req PSAMPLE #-3 verilog_node "$CCX_PATH.sctag3_cpx_req_cq";
input [7:0] l2t2_cpx_req PSAMPLE #-3 verilog_node "$CCX_PATH.sctag2_cpx_req_cq";
input [7:0] l2t1_cpx_req PSAMPLE #-3 verilog_node "$CCX_PATH.sctag1_cpx_req_cq";
input [7:0] l2t0_cpx_req PSAMPLE #-3 verilog_node "$CCX_PATH.sctag0_cpx_req_cq";
input l2t7_cpx_atom PSAMPLE #-3 verilog_node "$CCX_PATH.sctag7_cpx_atom_cq";
input l2t6_cpx_atom PSAMPLE #-3 verilog_node "$CCX_PATH.sctag6_cpx_atom_cq";
input l2t5_cpx_atom PSAMPLE #-3 verilog_node "$CCX_PATH.sctag5_cpx_atom_cq";
input l2t4_cpx_atom PSAMPLE #-3 verilog_node "$CCX_PATH.sctag4_cpx_atom_cq";
input l2t3_cpx_atom PSAMPLE #-3 verilog_node "$CCX_PATH.sctag3_cpx_atom_cq";
input l2t2_cpx_atom PSAMPLE #-3 verilog_node "$CCX_PATH.sctag2_cpx_atom_cq";
input l2t1_cpx_atom PSAMPLE #-3 verilog_node "$CCX_PATH.sctag1_cpx_atom_cq";
input l2t0_cpx_atom PSAMPLE #-3 verilog_node "$CCX_PATH.sctag0_cpx_atom_cq";
//for l2sat_ccx_pcx_sequence_samp
input [7:0] pcx_spc0_grant PSAMPLE #-3 verilog_node "$CCX_PATH.pcx_spc0_grant_px";
//for l2sat_ccx_pcx_qfull_samp
input [7:0] pcx_arb7_qfull PSAMPLE #-3 verilog_node "$CCX_PATH.pcx.pcx_arbl7.arc.qfull_a";
input [7:0] pcx_arb6_qfull PSAMPLE #-3 verilog_node "$CCX_PATH.pcx.pcx_arbl6.arc.qfull_a";
input [7:0] pcx_arb5_qfull PSAMPLE #-3 verilog_node "$CCX_PATH.pcx.pcx_arbl5.arc.qfull_a";
input [7:0] pcx_arb4_qfull PSAMPLE #-3 verilog_node "$CCX_PATH.pcx.pcx_arbl4.arc.qfull_a";
input [7:0] pcx_arb3_qfull PSAMPLE #-3 verilog_node "$CCX_PATH.pcx.pcx_arbl3.arc.qfull_a";
input [7:0] pcx_arb2_qfull PSAMPLE #-3 verilog_node "$CCX_PATH.pcx.pcx_arbl2.arc.qfull_a";
input [7:0] pcx_arb1_qfull PSAMPLE #-3 verilog_node "$CCX_PATH.pcx.pcx_arbl1.arc.qfull_a";
input [7:0] pcx_arb0_qfull PSAMPLE #-3 verilog_node "$CCX_PATH.pcx.pcx_arbl0.arc.qfull_a";
//for l2sat_ccx_cpx_qfull_samp
input [7:0] cpx_arb7_qfull PSAMPLE #-3 verilog_node "$CCX_PATH.cpx.cpx_arbl7.arc.qfull_a";
input [7:0] cpx_arb6_qfull PSAMPLE #-3 verilog_node "$CCX_PATH.cpx.cpx_arbl6.arc.qfull_a";
input [7:0] cpx_arb5_qfull PSAMPLE #-3 verilog_node "$CCX_PATH.cpx.cpx_arbl5.arc.qfull_a";
input [7:0] cpx_arb4_qfull PSAMPLE #-3 verilog_node "$CCX_PATH.cpx.cpx_arbl4.arc.qfull_a";
input [7:0] cpx_arb3_qfull PSAMPLE #-3 verilog_node "$CCX_PATH.cpx.cpx_arbl3.arc.qfull_a";
input [7:0] cpx_arb2_qfull PSAMPLE #-3 verilog_node "$CCX_PATH.cpx.cpx_arbl2.arc.qfull_a";
input [7:0] cpx_arb1_qfull PSAMPLE #-3 verilog_node "$CCX_PATH.cpx.cpx_arbl1.arc.qfull_a";
input [7:0] cpx_arb0_qfull PSAMPLE #-3 verilog_node "$CCX_PATH.cpx.cpx_arbl0.arc.qfull_a";
//for l2sat_ccx_pcx_stallatom_samp
input [7:0] pcx_arb0_atom PSAMPLE #-3 verilog_node "$CCX_PATH.pcx.pcx_arbl0.ard.atom";
input [7:0] pcx_arb0_grant_a PSAMPLE #-3 verilog_node "$CCX_PATH.pcx.pcx_arbl0.ard.grant_a";
input pcx_arb0_stall_a_ PSAMPLE #-3 verilog_node "$CCX_PATH.pcx.pcx_arbl0.ard.stall_a_";
//for l2sat_ccx_cpx_stallatom_samp
input [7:0] cpx_arb0_atom PSAMPLE #-3 verilog_node "$CCX_PATH.cpx.cpx_arbl0.ard.atom";
input [7:0] cpx_arb0_grant_a PSAMPLE #-3 verilog_node "$CCX_PATH.cpx.cpx_arbl0.ard.grant_a";
input cpx_arb0_stall_a_ PSAMPLE #-3 verilog_node "$CCX_PATH.cpx.cpx_arbl0.ard.stall_a_";
//////////////////////////////
//////////////////////////////
input pcx_l2t0_data_rdy PSAMPLE #-3 verilog_node "$L2T_PATH[0].iqu.pcx_l2t_data_rdy_px1_fnl";
input [129:0] pcx_l2t0_data PSAMPLE #-3 verilog_node "$L2T_PATH[0].pcx_l2t_data_px2";
input [145:0] l2t0_cpx_data PSAMPLE #-3 verilog_node "$L2T_PATH[0].l2t_cpx_data_ca";
// no new signals needed for l2_cpx_fields_samp (l2t0_cpx_data)
input sii_l2t0_req_vld PSAMPLE #-3 verilog_node "$L2T_PATH[0].sii_l2t_req_vld";
input sii_l2t1_req_vld PSAMPLE #-3 verilog_node "`TOP.cpu.l2t1.sii_l2t_req_vld";
input sii_l2t2_req_vld PSAMPLE #-3 verilog_node "`TOP.cpu.l2t2.sii_l2t_req_vld";
input sii_l2t3_req_vld PSAMPLE #-3 verilog_node "`TOP.cpu.l2t3.sii_l2t_req_vld";
input sii_l2t4_req_vld PSAMPLE #-3 verilog_node "`TOP.cpu.l2t4.sii_l2t_req_vld";
input sii_l2t5_req_vld PSAMPLE #-3 verilog_node "`TOP.cpu.l2t5.sii_l2t_req_vld";
input sii_l2t6_req_vld PSAMPLE #-3 verilog_node "`TOP.cpu.l2t6.sii_l2t_req_vld";
input sii_l2t7_req_vld PSAMPLE #-3 verilog_node "`TOP.cpu.l2t7.sii_l2t_req_vld";
input [31:0] sii_l2t0_req PSAMPLE #-3 verilog_node "$L2T_PATH[0].sii_l2t_req";
input [31:0] sii_l2t1_req PSAMPLE #-3 verilog_node "`TOP.cpu.l2t1.sii_l2t_req";
input [31:0] sii_l2t2_req PSAMPLE #-3 verilog_node "`TOP.cpu.l2t2.sii_l2t_req";
input [31:0] sii_l2t3_req PSAMPLE #-3 verilog_node "`TOP.cpu.l2t3.sii_l2t_req";
input [31:0] sii_l2t4_req PSAMPLE #-3 verilog_node "`TOP.cpu.l2t4.sii_l2t_req";
input [31:0] sii_l2t5_req PSAMPLE #-3 verilog_node "`TOP.cpu.l2t5.sii_l2t_req";
input [31:0] sii_l2t6_req PSAMPLE #-3 verilog_node "`TOP.cpu.l2t6.sii_l2t_req";
input [31:0] sii_l2t7_req PSAMPLE #-3 verilog_node "`TOP.cpu.l2t7.sii_l2t_req";
input [5:0] sii_l2b0_ecc PSAMPLE #-3 verilog_node "$L2B_PATH[0].sii_l2b_ecc";
// input [31:0] sii_l2t0_req_pkt PSAMPLE #-3 verilog_node "$L2T_PATH[0].sii_l2t_req";
// input [31:0] sii_l2t1_req_pkt PSAMPLE #-3 verilog_node "`TOP.cpu.l2t1.sii_l2t_req";
// input [31:0] sii_l2t2_req_pkt PSAMPLE #-3 verilog_node "`TOP.cpu.l2t2.sii_l2t_req";
// input [31:0] sii_l2t3_req_pkt PSAMPLE #-3 verilog_node "`TOP.cpu.l2t3.sii_l2t_req";
// input [31:0] sii_l2t4_req_pkt PSAMPLE #-3 verilog_node "`TOP.cpu.l2t4.sii_l2t_req";
// input [31:0] sii_l2t5_req_pkt PSAMPLE #-3 verilog_node "`TOP.cpu.l2t5.sii_l2t_req";
// input [31:0] sii_l2t6_req_pkt PSAMPLE #-3 verilog_node "`TOP.cpu.l2t6.sii_l2t_req";
// input [31:0] sii_l2t7_req_pkt PSAMPLE #-3 verilog_node "`TOP.cpu.l2t7.sii_l2t_req";
input arbctl_inst_vld_c2_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].arb.arb_inst_vld_c2";
input arbctl_inst_diag_c2_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].arb.arb_inst_diag_c2";
input arbctl_inval_inst_c2_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].arb.arb_inval_inst_c2";
input arb_decdp_inst_int_c2_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].arb.arb_decdp_inst_int_c2";
input [39:0] arbdp_addr_c2_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].arbadr.arbdp_addr_c2";
input [4:0] iq_count_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].iqu.que_cnt";
input [4:0] oq_count_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].oqu.oq_count_p";
input imiss1_to_xbarq_c6_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].oqu.imiss1_to_xbarq_c6";
input sel_old_req_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].oqu.sel_old_req";
input ic_wr_en_c4_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].dirrep_ic_wr_en_c4";
input [4:0] dir_panel_icd_c4_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].dirrep.dir_panel_icd_c4";
input [4:0] wr_ic_dir_entry_c4_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].dirrep.dirrep_wr_ic_dir_entry_c4";
input dc_wr_en_c4_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].dirrep_dc_wr_en_c4";
input [4:0] dir_panel_dcd_c4_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].dirrep.dir_panel_dcd_c4";
input [4:0] wr_dc_dir_entry_c4_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].dirrep_wr_dc_dir_entry_c4";
input [3:0] ic_lkup_row_dec_c4_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].dirrep_ic_lkup_row_dec_c4";
input [2:0] lkup_row_addr_icd_c4_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].dirrep.lkup_row_addr_icd_c4";
input [3:0] dc_lkup_row_dec_c4_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].dirrep_dc_lkup_row_dec_c4";
input [2:0] lkup_row_addr_dcd_c4_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].dirrep.lkup_row_addr_dcd_c4";
input [5:0] mb_count_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].misbuf.mb_count_c4";
//for l2_mb_sameindex_samp
input [5:0] mb_sameindex_count_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].misbuf.hit_count_c4";
//for l2_mb_hit_bypass_samp
input mbctl_hit_c2_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].misbuf.misbuf_hit_c2";
input tmp_hit_unqual_c2_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].misbuf.tmp_hit_unqual_c2";
input tmp_cam_hit_c2_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].misbuf.tmp_cam_hit_c2";
input mbf_insert_c3_tmp_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].misbuf.mbf_insert_c3_tmp";
input [15:0] cam_hit_vec_c1_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].misbuf.cam_hit_vec_c1";
input [3:0] fb_count_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].filbuf.fb_count";
//for l2_fbmb_miss_entries_samp
input fbf_ready_miss_r1_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].filbuf.filbuf_fbf_ready_miss_r1";
input [2:0] dram_rd_req_id_r0_d1_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].filbuf.mcu_rd_req_id_r0_d1";
input [4:0] fbf_enc_ld_mbid_r1_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].filbuf.filbuf_fbf_enc_ld_mbid_r1";
//for l2_fbmb_stdep_entries_samp
input fbf_st_or_dep_rdy_c4_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].filbuf.filbuf_fbf_st_or_dep_rdy_c4";
input [7:0] fill_complete_c4_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].filbuf.fill_complete_c4";
input [4:0] fbf_enc_dep_mbid_c4_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].filbuf.filbuf_fbf_enc_dep_mbid_c4";
//for l2_fb_bypass_entries_samp
input fbctl_hit_c2_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].filbuf.filbuf_hit_c2";
input [7:0] fb_hit_vec_c2_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].filbuf.fb_hit_vec_c2";
//for l2_fb_bypass_insts_samp
input [40:0] arbdp_inst_c2_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].arbdec.arbdp_inst_c2";
//for l2_fill_complete_samp
input [7:0] dec_fill_entry_c3_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].filbuf.dec_fill_entry_c3";
input [7:0] no_fill_entry_dequeue_c3_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].filbuf.no_fill_entry_dequeue_c3";
input en_hit_dequeue_c2_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].filbuf.en_hit_dequeue_c2";
input rdma_inst_c2_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].filbuf.rdma_inst_c2";
input mbctl_rdma_reg_vld_c2_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].filbuf.tag_misbuf_rdma_reg_vld_c2";
input [3:0] wb_count_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].wbuf.wb_count";
//for l2_wb_hit_bypass_samp
input wbctl_hit_qual_c2_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].wbuf.wbuf_hit_qual_c2";
input bypass_hit_en_c2_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].wbuf.bypass_hit_en_c2";
input [7:0] wb_cam_hit_vec_tmp_c2_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].wbuf.wb_cam_hit_vec_tmp_c2";
//for l2_snpiq_valid_samp
input [1:0] snpq_valid_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].snp.snpq_valid";
//for l2_rdmawb_valid_samp
input [3:0] rdma_valid_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].rdmat.rdma_valid";
//for l2_pipeline_full_samp
input arbctl_inst_vld_c1_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].arb.arb_inst_vld_c1";
//for l2_stalled_insts1_samp
input same_col_stall_c1_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].arb.same_col_stall_c1";
input imiss_stall_op_c1inc1_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].arb.imiss_stall_op_c1inc1";
input arbctl_evict_vld_c2_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].arb.arb_evict_vld_c2";
input arbctl_fill_vld_c2_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].arb.arb_fill_vld_c2";
input arbctl_fill_vld_c3_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].arb.arb_fill_vld_c3";
input rdma_64B_stall_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].arb.rdma_64B_stall";
//input arbctl_inval_inst_c2_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].
input inval_inst_vld_c3_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].arb.inval_inst_vld_c3";
input inval_inst_vld_c4_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].arb.inval_inst_vld_c4";
input ic_inval_vld_c5_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].arb.ic_inval_vld_c5";
input ic_inval_vld_c52_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].arb.ic_inval_vld_c52";
input ic_inval_vld_c6_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].arb.ic_inval_vld_c6";
input arb_ic_inval_vld_c7_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].arb.arb_ic_inval_vld_c7";
input inst_l2data_vld_c2_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].arb.inst_l2data_vld_c2";
input inst_l2tag_vld_c2_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].arb.inst_l2tag_vld_c2";
input inst_l2tag_vld_c3_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].arb.inst_l2tag_vld_c3";
input inst_l2vuad_vld_c2_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].arb.inst_l2vuad_vld_c2";
input inst_l2vuad_vld_c3_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].arb.inst_l2vuad_vld_c3";
input inst_l2vuad_vld_c4_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].arb.inst_l2vuad_vld_c4";
input inc_tag_ecc_cnt_c2_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].arb.inc_tag_ecc_cnt_c2";
input inc_tag_ecc_cnt_c3_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].arb.inc_tag_ecc_cnt_c3";
input data_ecc_active_c4_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].arb.data_ecc_active_c4";
input arbctl_inst_diag_c1_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].arb.arb_inst_diag_c1";
input [33:0] arbdp_inst_c1_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].arbdec.arbdp_inst_c1";
//for l2_stalled_insts2_samp
input arbdp_evict_c1_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].arb.arbdec_arbdp_evict_c1";
input arbdp_inst_fb_c1_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].arb.arbdec_arbdp_inst_fb_c1";
input decdp_imiss_inst_c1_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].arb.decdp_imiss_inst_c1";
input decdp_ic_inval_c1_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].arb.decdp_ic_inval_c1";
input decdp_dc_inval_c1_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].arb.decdp_dc_inval_c1";
input arbdp_tecc_c1_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].arb.arbdec_arbdp_tecc_c1";
input arbdp_inst_rsvd_c1_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].arb.arbdec_arbdp_inst_rsvd_c1";
input arbctl_stall_c2_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].arb.arb_stall_c2";
//for l2_vuad_bypass_samp
input vuad_sel_c2orc3_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].vuad.vuaddp_vuad_sel_c2orc3";
input vuad_sel_c2_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].vuad.vuaddp_vuad_sel_c2";
input vuad_sel_c4orc5_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].vuad.vuad_sel_c4orc5";
input vuad_sel_c4_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].vuad.vuaddp_vuad_sel_c4";
//for l2_offmode_directmap_insts_samp
input l2_bypass_mode_on_d1_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].tagctl.l2_bypass_mode_on_d1";
input l2_dir_map_on_d1_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].tagdp.l2_dir_map_on_d1";
input tagctl_hit_l2orfb_c2_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].tagctl.tag_hit_l2orfb_c2";
//input mbctl_hit_c2_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].misbuf.misbuf_hit_c2";
input arbdp_inst_mb_c2_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].arbdec.arbdec_arbdp_inst_mb_c2";
//input arbctl_evict_vld_c2_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].arb.arb_evict_vld_c2";
//for l2_buffer_hits_samp
input fbctl_mbctl_match_c2_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].filbuf.filbuf_misbuf_match_c2";
//input wbctl_hit_qual_c2_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].wbuf.wbuf_hit_qual_c2";
input rdmatctl_hit_qual_c2_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].rdmat.rdma_hit_qual_c2";
//for l2_error_status_reg_samp
input [63:0] err_state_new_c9_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].csreg.err_state_new_c9";
input [63:0] err_status_in_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].csreg.err_status_in";
//for l2_notdata_error_reg_samp
input [1:0] err_state_notdata_new_c9_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].csreg.err_state_notdata_new_c9";
input [1:0] err_status_notdata_in_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].csreg.err_status_notdata_in";
//for l2_two_successive_errors_samp
input [47:0] csr_l2_notdata_reg_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].csr.csr_l2_notdata_reg";
//for l2_dir/tag/data_scrub_cov
input [10:0] dir_addr_cnt_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].arb.dir_addr_cnt_c3";
input [7:0] tecc_st_cnt_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].arb.tecc_st_cnt";
input [3:0] arb_tecc_way_c2_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].arb.arb_tecc_way_c2";
input [8:0] arbadr_data_ecc_idx_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].arbadr.arbadr_data_ecc_idx";
//for l2_error_trans_samp
input [63:0] csr_l2_errstate_reg_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].csr.csr_l2_errstate_reg";
input tecc_c2_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].tagctl.arb_tecc_c2";
input par_err_c2_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].tagdp.par_err_c2";
input arbdp_pst_with_ctrue_c2_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].arb.arb_arbdp_pst_with_ctrue_c2";
//for l2_error_offmode_samp
input fbuerr0_d1_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].filbuf.fbuerr0_d1";
input fbcerr0_d1_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].filbuf.fbcerr0_d1";
//for l2_error_vuad_ce_samp
input vlddir_valid_c2_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].vlddir.valid_c2";
input vlddir_valid_corr_c2_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].vlddir.valid_corr_c2";
input l2t_l2d_way_sel_c2_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].l2t_l2d_way_sel_c2";
input tag_hit_unqual_c2_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].tag_hit_unqual_c2";
input arb_vuad_ce_err_c2_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].misbuf.arb_vuad_ce_err_c2_qual";
//for l2sat_partial_corebank_coverage_group
input ncu_l2t_pm_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].ncu_l2t_pm";
input ncu_l2t_ba01_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].ncu_l2t_ba01";
input ncu_l2t_ba23_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].ncu_l2t_ba23";
input ncu_l2t_ba45_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].ncu_l2t_ba45";
input ncu_l2t_ba67_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].ncu_l2t_ba67";
input ncu_spc0_core_enable_status_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].ncu_spc0_core_enable_status";
input ncu_spc1_core_enable_status_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].ncu_spc1_core_enable_status";
input ncu_spc2_core_enable_status_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].ncu_spc2_core_enable_status";
input ncu_spc3_core_enable_status_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].ncu_spc3_core_enable_status";
input ncu_spc4_core_enable_status_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].ncu_spc4_core_enable_status";
input ncu_spc5_core_enable_status_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].ncu_spc5_core_enable_status";
input ncu_spc6_core_enable_status_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].ncu_spc6_core_enable_status";
input ncu_spc7_core_enable_status_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].ncu_spc7_core_enable_status";
//for l2_pipeline_arbiter_cov
input mbf_valid_px2_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].arb.mbf_valid_px2";
input fbf_valid_px2_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].arb.fbf_valid_px2_1";
input snp_valid_px2_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].arb.snp_valid_px2";
//input atm_instr_c1_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].arb.atm_instr_c1";
input ique_iq_arb_atm_px2_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].arb.ique_iq_arb_atm_px2";
input arb_stall_c2_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].arb.arb_stall_c2";
//input iqsel_px2_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].arb.iqsel_px2";
input iqu_iq_arb_vld_px2_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].arb.iqu_iq_arb_vld_px2";
//for l2_fb_wb_iowb_cam_results_cov
input [7:0] fb_cam_match PSAMPLE #-3 verilog_node "$L2T_PATH[0].filbuf.fb_cam_match";
input [7:0] fb_valid PSAMPLE #-3 verilog_node "$L2T_PATH[0].filbuf.fb_valid";
input [7:0] wb_cam_match_c2 PSAMPLE #-3 verilog_node "$L2T_PATH[0].wbuf.wb_cam_match_c2";
input [7:0] wb_valid PSAMPLE #-3 verilog_node "$L2T_PATH[0].wbuf.wb_valid";
input [3:0] rdmat_cam_match_c2 PSAMPLE #-3 verilog_node "$L2T_PATH[0].rdmat.rdmat_cam_match_c2";
input [3:0] rdma_valid PSAMPLE #-3 verilog_node "$L2T_PATH[0].rdmat.rdma_valid";
//for l2_store_pipelining_cov
input arbctl_inst_vld_c3_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].arb.arb_inst_vld_c3";
input arb_decdp_st_inst_c3_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].arb.arb_decdp_st_inst_c3";
input misbuf_dep_inst_c3_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].misbuf.misbuf_dep_inst_c3";
input mbf_insert_c3_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].misbuf.mbf_insert_c3_tmp";
input tag_hit_c3_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].tagctl.tag_hit_c3";
input arb_vuad_ce_err_c3_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].misbuf.arb_vuad_ce_err_c3";
// ******************************************************************************************************
// Interface for l2 & SIU internal coverage obj for FC
// ******************************************************************************************************
interface l2_siu_ccx_intf {
input clk CLOCK verilog_node "`TOP.cpu.l2t0.gclk";
input clk CLOCK verilog_node "l2sat_top.clock";
input [7:0] sctag0_cpx_req_cq INPUT_EDGE INPUT_SKEW verilog_node "`TOP.cpu.sctag0_cpx_req_cq";
input [7:0] sctag1_cpx_req_cq INPUT_EDGE INPUT_SKEW verilog_node "`TOP.cpu.sctag1_cpx_req_cq";
input [7:0] sctag2_cpx_req_cq INPUT_EDGE INPUT_SKEW verilog_node "`TOP.cpu.sctag2_cpx_req_cq";
input [7:0] sctag3_cpx_req_cq INPUT_EDGE INPUT_SKEW verilog_node "`TOP.cpu.sctag3_cpx_req_cq";
input [7:0] sctag4_cpx_req_cq INPUT_EDGE INPUT_SKEW verilog_node "`TOP.cpu.sctag4_cpx_req_cq";
input [7:0] sctag5_cpx_req_cq INPUT_EDGE INPUT_SKEW verilog_node "`TOP.cpu.sctag5_cpx_req_cq";
input [7:0] sctag6_cpx_req_cq INPUT_EDGE INPUT_SKEW verilog_node "`TOP.cpu.sctag6_cpx_req_cq";
input [7:0] sctag7_cpx_req_cq INPUT_EDGE INPUT_SKEW verilog_node "`TOP.cpu.sctag7_cpx_req_cq";
input l2b0_sio_ctag_vld INPUT_EDGE INPUT_SKEW verilog_node "`TOP.cpu.l2b0_sio_ctag_vld";
input l2b1_sio_ctag_vld INPUT_EDGE INPUT_SKEW verilog_node "`TOP.cpu.l2b1_sio_ctag_vld";
input l2b2_sio_ctag_vld INPUT_EDGE INPUT_SKEW verilog_node "`TOP.cpu.l2b2_sio_ctag_vld";
input l2b3_sio_ctag_vld INPUT_EDGE INPUT_SKEW verilog_node "`TOP.cpu.l2b3_sio_ctag_vld";
input l2b4_sio_ctag_vld INPUT_EDGE INPUT_SKEW verilog_node "`TOP.cpu.l2b4_sio_ctag_vld";
input l2b5_sio_ctag_vld INPUT_EDGE INPUT_SKEW verilog_node "`TOP.cpu.l2b5_sio_ctag_vld";
input l2b6_sio_ctag_vld INPUT_EDGE INPUT_SKEW verilog_node "`TOP.cpu.l2b6_sio_ctag_vld";
input l2b7_sio_ctag_vld INPUT_EDGE INPUT_SKEW verilog_node "`TOP.cpu.l2b7_sio_ctag_vld";
// ******************************************************************************************************
// ******************************************************************************************************
// Interface for l2 RAS coverage obj for FC
// ******************************************************************************************************
input clk CLOCK verilog_node "`TOP.cpu.l2t0.gclk";
input [145:0] l2t0_cpx_data PSAMPLE #-3 verilog_node "$L2T_PATH[0].l2t_cpx_data_ca";
input [145:0] l2t1_cpx_data PSAMPLE #-3 verilog_node "`TOP.cpu.l2t1.l2t_cpx_data_ca";
input [145:0] l2t2_cpx_data PSAMPLE #-3 verilog_node "`TOP.cpu.l2t2.l2t_cpx_data_ca";
input [145:0] l2t3_cpx_data PSAMPLE #-3 verilog_node "`TOP.cpu.l2t3.l2t_cpx_data_ca";
input [145:0] l2t4_cpx_data PSAMPLE #-3 verilog_node "`TOP.cpu.l2t4.l2t_cpx_data_ca";
input [145:0] l2t5_cpx_data PSAMPLE #-3 verilog_node "`TOP.cpu.l2t5.l2t_cpx_data_ca";
input [145:0] l2t6_cpx_data PSAMPLE #-3 verilog_node "`TOP.cpu.l2t6.l2t_cpx_data_ca";
input [145:0] l2t7_cpx_data PSAMPLE #-3 verilog_node "`TOP.cpu.l2t7.l2t_cpx_data_ca";
// ******************************************************************************************************
projects / OpenSPARC-T2-DV / blob