verif/env/common/coverage/l2sat/pcxsiu_intf_cpx_req_sample.vrhpal

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//
// OpenSPARC T2 Processor File: pcxsiu_intf_cpx_req_sample.vrhpal
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    state allcores_bank0_siu(128'h01010101_01010101_00000000_00000000);
    state allcores_bank1_siu(128'h02020202_02020202_00000000_00000000);
    state allcores_bank2_siu(128'h04040404_04040404_00000000_00000000);
    state allcores_bank3_siu(128'h08080808_08080808_00000000_00000000);
    state allcores_bank4_siu(128'h10101010_10101010_00000000_00000000);
    state allcores_bank5_siu(128'h20202020_20202020_00000000_00000000);
    state allcores_bank6_siu(128'h40404040_40404040_00000000_00000000);
    state allcores_bank7_siu(128'h80808080_80808080_00000000_00000000);

    // 2-packet requests

    state allcores_bank0_atom_siu(128'h01010101_01010101_01010101_01010101);
    state allcores_bank1_atom_siu(128'h02020202_02020202_02020202_02020202);
    state allcores_bank2_atom_siu(128'h04040404_04040404_04040404_04040404);
    state allcores_bank3_atom_siu(128'h08080808_08080808_08080808_08080808);
    state allcores_bank4_atom_siu(128'h10101010_10101010_10101010_10101010);
    state allcores_bank5_atom_siu(128'h20202020_20202020_20202020_20202020);
    state allcores_bank6_atom_siu(128'h40404040_40404040_40404040_40404040);
    state allcores_bank7_atom_siu(128'h80808080_80808080_80808080_80808080);