verif/env/common/coverage/siu/siu_l2intf_switchbanks_sample.vrhpal

// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T2 Processor File: siu_l2intf_switchbanks_sample.vrhpal
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
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#inc "siu_cov_inc.pal"

#define BANK0  (8'b00000001)
#define BANK1  (8'b00000010)
#define BANK2  (8'b00000100)
#define BANK3  (8'b00001000)
#define BANK4  (8'b00010000)
#define BANK5  (8'b00100000)
#define BANK6  (8'b01000000)
#define BANK7  (8'b10000000)
#define NOP    (8'b00000000)


sample switchbanks (switch_banks)
{
. for ($bank1=0; $bank1<8; $bank1++)
. {
.   for ($bank2=0; $bank2<8; $bank2++)
.   {
      trans t_BANK${bank1}_BANK${bank2} (BANK${bank1} -> NOP -> BANK${bank2} );

.   }
. }
}

#ifndef SIU_INTF_COV
// Not for FC
sample siu_l2_cmd_sample_this (this_l2_cmd)

{
  state DMU_RDD_ord_npt         ( 6'b101001 );
  state DMU_WR8_ord_pst         ( 6'b111010 );
  state DMU_WRI_pst_ord         ( 6'b111100 );

  state NIU_RDD_ord_npt         ( 6'b100001 );
  state NIU_RDD_byp_npt         ( 6'b000001 );

  state NIU_WRI_ord_npt         ( 6'b100100 );
  state NIU_WRI_byp_npt         ( 6'b000100 );

  state NIU_WRI_ord_pst         ( 6'b110100 );
  state NIU_WRI_byp_pst         ( 6'b010100 );

}


cross siu_switch_bank_each_cmd_cross (switchbanks, siu_l2_cmd_sample_this);
#endif