Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / env / common / coverage / siu / siu_ncu_intf_pm_bank_sample.vrhpal
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T2 Processor File: siu_ncu_intf_pm_bank_sample.vrhpal
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
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#inc "siu_cov_inc.pal";
sample siu_ncu_intf_partial_bank_dmu_1_sample (dmu_data_876)
{
state s_SIU_NCU_PM_1_1 (3'b000);
state s_SIU_NCU_PM_1_2 (3'b001);
state s_SIU_NCU_PM_1_3 (3'b010);
state s_SIU_NCU_PM_1_4 (3'b011);
state s_SIU_NCU_PM_1_5 (3'b100);
state s_SIU_NCU_PM_1_6 (3'b101);
state s_SIU_NCU_PM_1_7 (3'b110);
state s_SIU_NCU_PM_1_8 (3'b111);
}
sample siu_ncu_intf_partial_bank_dmu_2_sample (dmu_data_876_2)
{
state s_SIU_NCU_PM_2_1 (3'b000);
state s_SIU_NCU_PM_2_2 (3'b001);
state s_SIU_NCU_PM_2_3 (3'b010);
state s_SIU_NCU_PM_2_4 (3'b011);
state s_SIU_NCU_PM_2_5 (3'b100);
state s_SIU_NCU_PM_2_6 (3'b101);
state s_SIU_NCU_PM_2_7 (3'b110);
state s_SIU_NCU_PM_2_8 (3'b111);
}
sample siu_ncu_intf_partial_bank_dmu_3_sample (dmu_data_876_3)
{
state s_SIU_NCU_PM_3_1 (3'b000);
state s_SIU_NCU_PM_3_2 (3'b001);
state s_SIU_NCU_PM_3_3 (3'b010);
state s_SIU_NCU_PM_3_4 (3'b011);
state s_SIU_NCU_PM_3_5 (3'b100);
state s_SIU_NCU_PM_3_6 (3'b101);
state s_SIU_NCU_PM_3_7 (3'b110);
state s_SIU_NCU_PM_3_8 (3'b111);
}
sample siu_ncu_intf_partial_bank_dmu_4_sample (dmu_data_876_4)
{
state s_SIU_NCU_PM_4_1 (3'b000);
state s_SIU_NCU_PM_4_2 (3'b001);
state s_SIU_NCU_PM_4_3 (3'b010);
state s_SIU_NCU_PM_4_4 (3'b011);
state s_SIU_NCU_PM_4_5 (3'b100);
state s_SIU_NCU_PM_4_6 (3'b101);
state s_SIU_NCU_PM_4_7 (3'b110);
state s_SIU_NCU_PM_4_8 (3'b111);
}
sample siu_ncu_intf_partial_bank_dmu_5_sample (dmu_data_876_5)
{
state s_SIU_NCU_PM_5_1 (3'b000);
state s_SIU_NCU_PM_5_2 (3'b001);
state s_SIU_NCU_PM_5_3 (3'b010);
state s_SIU_NCU_PM_5_4 (3'b011);
state s_SIU_NCU_PM_5_5 (3'b100);
state s_SIU_NCU_PM_5_6 (3'b101);
state s_SIU_NCU_PM_5_7 (3'b110);
state s_SIU_NCU_PM_5_8 (3'b111);
}
sample siu_ncu_intf_partial_bank_dmu_6_sample (dmu_data_876_6)
{
state s_SIU_NCU_PM_6_1 (3'b000);
state s_SIU_NCU_PM_6_2 (3'b001);
state s_SIU_NCU_PM_6_3 (3'b010);
state s_SIU_NCU_PM_6_4 (3'b011);
state s_SIU_NCU_PM_6_5 (3'b100);
state s_SIU_NCU_PM_6_6 (3'b101);
state s_SIU_NCU_PM_6_7 (3'b110);
state s_SIU_NCU_PM_6_8 (3'b111);
}
sample siu_ncu_intf_partial_bank_dmu_7_sample (dmu_data_876_7)
{
state s_SIU_NCU_PM_7_1 (3'b000);
state s_SIU_NCU_PM_7_2 (3'b001);
state s_SIU_NCU_PM_7_3 (3'b010);
state s_SIU_NCU_PM_7_4 (3'b011);
state s_SIU_NCU_PM_7_5 (3'b100);
state s_SIU_NCU_PM_7_6 (3'b101);
state s_SIU_NCU_PM_7_7 (3'b110);
state s_SIU_NCU_PM_7_8 (3'b111);
}
sample siu_ncu_intf_partial_bank_dmu_8_sample (dmu_data_876_8)
{
state s_SIU_NCU_PM_8_1 (3'b000);
state s_SIU_NCU_PM_8_2 (3'b001);
state s_SIU_NCU_PM_8_3 (3'b010);
state s_SIU_NCU_PM_8_4 (3'b011);
state s_SIU_NCU_PM_8_5 (3'b100);
state s_SIU_NCU_PM_8_6 (3'b101);
state s_SIU_NCU_PM_8_7 (3'b110);
state s_SIU_NCU_PM_8_8 (3'b111);
}
sample siu_ncu_intf_partial_bank_dmu_9_sample (dmu_data_876_9)
{
state s_SIU_NCU_PM_9_1 (3'b000);
state s_SIU_NCU_PM_9_2 (3'b001);
state s_SIU_NCU_PM_9_3 (3'b010);
state s_SIU_NCU_PM_9_4 (3'b011);
state s_SIU_NCU_PM_9_5 (3'b100);
state s_SIU_NCU_PM_9_6 (3'b101);
state s_SIU_NCU_PM_9_7 (3'b110);
state s_SIU_NCU_PM_9_8 (3'b111);
}
sample siu_ncu_intf_partial_bank_dmu_10_sample (dmu_data_876_10)
{
state s_SIU_NCU_PM_10_1 (3'b000);
state s_SIU_NCU_PM_10_2 (3'b001);
state s_SIU_NCU_PM_10_3 (3'b010);
state s_SIU_NCU_PM_10_4 (3'b011);
state s_SIU_NCU_PM_10_5 (3'b100);
state s_SIU_NCU_PM_10_6 (3'b101);
state s_SIU_NCU_PM_10_7 (3'b110);
state s_SIU_NCU_PM_10_8 (3'b111);
}
sample siu_ncu_intf_partial_bank_dmu_11_sample (dmu_data_876_11)
{
state s_SIU_NCU_PM_11_1 (3'b000);
state s_SIU_NCU_PM_11_2 (3'b001);
state s_SIU_NCU_PM_11_3 (3'b010);
state s_SIU_NCU_PM_11_4 (3'b011);
state s_SIU_NCU_PM_11_5 (3'b100);
state s_SIU_NCU_PM_11_6 (3'b101);
state s_SIU_NCU_PM_11_7 (3'b110);
state s_SIU_NCU_PM_11_8 (3'b111);
}