// ========== Copyright Header Begin ==========================================
// OpenSPARC T2 Processor File: ccxDevices.if.vrh
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
// For the avoidance of doubt, and except that if any non-GPL license
// choice is available it will apply instead, Sun elects to use only
// the General Public License version 2 (GPLv2) at this time for any
// software where a choice of GPL license versions is made
// available with the language indicating that GPLv2 or any later version
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// ========== Copyright Header End ============================================
#ifndef INC_CCXDEVICE_IF_VRH
#define INC_CCXDEVICE_IF_VRH
#include <vera_defines.vrh>
// interface names MUST be unique to ALL var names in ALL vera code
// for NTB. These interface names are global names. Adding '_if'
// core asserts atomic for cas pkts only
// l2 asserts atomic for ifill responces only
//----------------------------------------------------------
input clk CLOCK hdl_node "tb_top.cpu.cmp_gclk_c3_ncu";
// CCX Interface Signals with NCU
inout [7:0] cpx_req NSAMPLE NHOLD hdl_node "tb_top.cpu.ncu_cpx_req_cq";
inout [145:0] cpx_datao NSAMPLE NHOLD hdl_node "tb_top.cpu.ncu_cpx_data_ca";
// fake atomic from ncu to cpx
//input cpx_atmo NSAMPLE #-0 hdl_node "tb_top.cpu.ccx.pcx.pcx_arbl8.src8_arb_atom_q";
//arb8_dest_atom_unused";
input [7:0] cpx_gnt NSAMPLE #-0 hdl_node "tb_top.cpu.cpx_ncu_grant_cx";
output pcx_stall NHOLD #0 hdl_node "tb_top.cpu.ncu_pcx_stall_pq";
input pcx_rdy NSAMPLE #-0 hdl_node "tb_top.cpu.pcx_ncu_data_rdy_px1";
input [129:0] pcx_datai NSAMPLE #-0 hdl_node "tb_top.cpu.pcx_ncu_data_px2";
input clk CLOCK hdl_node "tb_top.cpu.cmp_gclk_c3_l2b0";
// CCX Interface Signals with L2
inout [7:0] cpx_req NSAMPLE NHOLD hdl_node "tb_top.cpu.sctag0_cpx_req_cq";
inout [145:0] cpx_datao NSAMPLE NHOLD hdl_node "tb_top.cpu.sctag0_cpx_data_ca";
inout cpx_atmo NSAMPLE NHOLD hdl_node "tb_top.cpu.sctag0_cpx_atom_cq";
input [7:0] cpx_grant NSAMPLE #-0 hdl_node "tb_top.cpu.cpx_sctag0_grant_cx";
output pcx_stall NHOLD #0 hdl_node "tb_top.cpu.sctag0_pcx_stall_pq";
input pcx_rdy NSAMPLE #-0 hdl_node "tb_top.cpu.pcx_sctag0_data_rdy_px1";
input pcx_atmi NSAMPLE #-0 hdl_node "tb_top.cpu.pcx_sctag0_atm_px1";
input [129:0] pcx_datai NSAMPLE #-0 hdl_node "tb_top.cpu.pcx_sctag0_data_px2";
input clk CLOCK hdl_node "tb_top.cpu.cmp_gclk_c3_l2b0";
// CCX Interface Signals with L2
inout [7:0] cpx_req NSAMPLE NHOLD hdl_node "tb_top.cpu.sctag1_cpx_req_cq";
inout [145:0] cpx_datao NSAMPLE NHOLD hdl_node "tb_top.cpu.sctag1_cpx_data_ca";
inout cpx_atmo NSAMPLE NHOLD hdl_node "tb_top.cpu.sctag1_cpx_atom_cq";
input [7:0] cpx_grant NSAMPLE #-0 hdl_node "tb_top.cpu.cpx_sctag1_grant_cx";
output pcx_stall NHOLD #0 hdl_node "tb_top.cpu.sctag1_pcx_stall_pq";
input pcx_rdy NSAMPLE #-0 hdl_node "tb_top.cpu.pcx_sctag1_data_rdy_px1";
input pcx_atmi NSAMPLE #-0 hdl_node "tb_top.cpu.pcx_sctag1_atm_px1";
input [129:0] pcx_datai NSAMPLE #-0 hdl_node "tb_top.cpu.pcx_sctag1_data_px2";
input clk CLOCK hdl_node "tb_top.cpu.cmp_gclk_c3_l2b0";
// CCX Interface Signals with L2
inout [7:0] cpx_req NSAMPLE NHOLD hdl_node "tb_top.cpu.sctag2_cpx_req_cq";
inout [145:0] cpx_datao NSAMPLE NHOLD hdl_node "tb_top.cpu.sctag2_cpx_data_ca";
inout cpx_atmo NSAMPLE NHOLD hdl_node "tb_top.cpu.sctag2_cpx_atom_cq";
input [7:0] cpx_grant NSAMPLE #-0 hdl_node "tb_top.cpu.cpx_sctag2_grant_cx";
output pcx_stall NHOLD #0 hdl_node "tb_top.cpu.sctag2_pcx_stall_pq";
input pcx_rdy NSAMPLE #-0 hdl_node "tb_top.cpu.pcx_sctag2_data_rdy_px1";
input pcx_atmi NSAMPLE #-0 hdl_node "tb_top.cpu.pcx_sctag2_atm_px1";
input [129:0] pcx_datai NSAMPLE #-0 hdl_node "tb_top.cpu.pcx_sctag2_data_px2";
input clk CLOCK hdl_node "tb_top.cpu.cmp_gclk_c3_l2b0";
// CCX Interface Signals with L2
inout [7:0] cpx_req NSAMPLE NHOLD hdl_node "tb_top.cpu.sctag3_cpx_req_cq";
inout [145:0] cpx_datao NSAMPLE NHOLD hdl_node "tb_top.cpu.sctag3_cpx_data_ca";
inout cpx_atmo NSAMPLE NHOLD hdl_node "tb_top.cpu.sctag3_cpx_atom_cq";
input [7:0] cpx_grant NSAMPLE #-0 hdl_node "tb_top.cpu.cpx_sctag3_grant_cx";
output pcx_stall NHOLD #0 hdl_node "tb_top.cpu.sctag3_pcx_stall_pq";
input pcx_rdy NSAMPLE #-0 hdl_node "tb_top.cpu.pcx_sctag3_data_rdy_px1";
input pcx_atmi NSAMPLE #-0 hdl_node "tb_top.cpu.pcx_sctag3_atm_px1";
input [129:0] pcx_datai NSAMPLE #-0 hdl_node "tb_top.cpu.pcx_sctag3_data_px2";
input clk CLOCK hdl_node "tb_top.cpu.cmp_gclk_c3_l2b0";
// CCX Interface Signals with L2
inout [7:0] cpx_req NSAMPLE NHOLD hdl_node "tb_top.cpu.sctag4_cpx_req_cq";
inout [145:0] cpx_datao NSAMPLE NHOLD hdl_node "tb_top.cpu.sctag4_cpx_data_ca";
inout cpx_atmo NSAMPLE NHOLD hdl_node "tb_top.cpu.sctag4_cpx_atom_cq";
input [7:0] cpx_grant NSAMPLE #-0 hdl_node "tb_top.cpu.cpx_sctag4_grant_cx";
output pcx_stall NHOLD #0 hdl_node "tb_top.cpu.sctag4_pcx_stall_pq";
input pcx_rdy NSAMPLE #-0 hdl_node "tb_top.cpu.pcx_sctag4_data_rdy_px1";
input pcx_atmi NSAMPLE #-0 hdl_node "tb_top.cpu.pcx_sctag4_atm_px1";
input [129:0] pcx_datai NSAMPLE #-0 hdl_node "tb_top.cpu.pcx_sctag4_data_px2";
input clk CLOCK hdl_node "tb_top.cpu.cmp_gclk_c3_l2b0";
// CCX Interface Signals with L2
inout [7:0] cpx_req NSAMPLE NHOLD hdl_node "tb_top.cpu.sctag5_cpx_req_cq";
inout [145:0] cpx_datao NSAMPLE NHOLD hdl_node "tb_top.cpu.sctag5_cpx_data_ca";
inout cpx_atmo NSAMPLE NHOLD hdl_node "tb_top.cpu.sctag5_cpx_atom_cq";
input [7:0] cpx_grant NSAMPLE #-0 hdl_node "tb_top.cpu.cpx_sctag5_grant_cx";
output pcx_stall NHOLD #0 hdl_node "tb_top.cpu.sctag5_pcx_stall_pq";
input pcx_rdy NSAMPLE #-0 hdl_node "tb_top.cpu.pcx_sctag5_data_rdy_px1";
input pcx_atmi NSAMPLE #-0 hdl_node "tb_top.cpu.pcx_sctag5_atm_px1";
input [129:0] pcx_datai NSAMPLE #-0 hdl_node "tb_top.cpu.pcx_sctag5_data_px2";
input clk CLOCK hdl_node "tb_top.cpu.cmp_gclk_c3_l2b0";
// CCX Interface Signals with L2
inout [7:0] cpx_req NSAMPLE NHOLD hdl_node "tb_top.cpu.sctag6_cpx_req_cq";
inout [145:0] cpx_datao NSAMPLE NHOLD hdl_node "tb_top.cpu.sctag6_cpx_data_ca";
inout cpx_atmo NSAMPLE NHOLD hdl_node "tb_top.cpu.sctag6_cpx_atom_cq";
input [7:0] cpx_grant NSAMPLE #-0 hdl_node "tb_top.cpu.cpx_sctag6_grant_cx";
output pcx_stall NHOLD #0 hdl_node "tb_top.cpu.sctag6_pcx_stall_pq";
input pcx_rdy NSAMPLE #-0 hdl_node "tb_top.cpu.pcx_sctag6_data_rdy_px1";
input pcx_atmi NSAMPLE #-0 hdl_node "tb_top.cpu.pcx_sctag6_atm_px1";
input [129:0] pcx_datai NSAMPLE #-0 hdl_node "tb_top.cpu.pcx_sctag6_data_px2";
input clk CLOCK hdl_node "tb_top.cpu.cmp_gclk_c3_l2b0";
// CCX Interface Signals with L2
inout [7:0] cpx_req NSAMPLE NHOLD hdl_node "tb_top.cpu.sctag7_cpx_req_cq";
inout [145:0] cpx_datao NSAMPLE NHOLD hdl_node "tb_top.cpu.sctag7_cpx_data_ca";
inout cpx_atmo NSAMPLE NHOLD hdl_node "tb_top.cpu.sctag7_cpx_atom_cq";
input [7:0] cpx_grant NSAMPLE #-0 hdl_node "tb_top.cpu.cpx_sctag7_grant_cx";
output pcx_stall NHOLD #0 hdl_node "tb_top.cpu.sctag7_pcx_stall_pq";
input pcx_rdy NSAMPLE #-0 hdl_node "tb_top.cpu.pcx_sctag7_data_rdy_px1";
input pcx_atmi NSAMPLE #-0 hdl_node "tb_top.cpu.pcx_sctag7_atm_px1";
input [129:0] pcx_datai NSAMPLE #-0 hdl_node "tb_top.cpu.pcx_sctag7_data_px2";
input clk CLOCK hdl_node "tb_top.cpu.cmp_gclk_c3_spc0";
// CCX Interface Signals with SPC
inout [8:0] pcx_req BOTH_DIR hdl_node "tb_top.cpu.spc0_pcx_req_pq";
inout [129:0] pcx_datao BOTH_DIR hdl_node "tb_top.cpu.spc0_pcx_data_pa";
// atomic from spc to cpx
inout [8:0] pcx_atm BOTH_DIR hdl_node "tb_top.cpu.spc0_pcx_atm_pq";
input [8:0] pcx_grant NSAMPLE #-0 hdl_node "tb_top.cpu.pcx_spc0_grant_px";
// N/A inout cpx_stall BOTH_DIR hdl_node "always 0";
// N/A inout cpx_rdy BOTH_DIR hdl_node "none";
// atomic from cpx to spc
// N/A inout cpx_atm BOTH_DIR hdl_node "none";
input [145:0] cpx_datai NSAMPLE #-0 hdl_node "tb_top.cpu.cpx_spc0_data_cx2";
input clk CLOCK hdl_node "tb_top.cpu.cmp_gclk_c3_spc0";
// CCX Interface Signals with SPC
inout [8:0] pcx_req BOTH_DIR hdl_node "tb_top.cpu.spc1_pcx_req_pq";
inout [129:0] pcx_datao BOTH_DIR hdl_node "tb_top.cpu.spc1_pcx_data_pa";
// atomic from spc to cpx
inout [8:0] pcx_atm BOTH_DIR hdl_node "tb_top.cpu.spc1_pcx_atm_pq";
input [8:0] pcx_grant NSAMPLE #-0 hdl_node "tb_top.cpu.pcx_spc1_grant_px";
// N/A inout cpx_stall BOTH_DIR hdl_node "always 0";
// N/A inout cpx_rdy BOTH_DIR hdl_node "none";
// atomic from cpx to spc
// N/A inout cpx_atm BOTH_DIR hdl_node "none";
input [145:0] cpx_datai NSAMPLE #-0 hdl_node "tb_top.cpu.cpx_spc1_data_cx2";
input clk CLOCK hdl_node "tb_top.cpu.cmp_gclk_c3_spc0";
// CCX Interface Signals with SPC
inout [8:0] pcx_req BOTH_DIR hdl_node "tb_top.cpu.spc2_pcx_req_pq";
inout [129:0] pcx_datao BOTH_DIR hdl_node "tb_top.cpu.spc2_pcx_data_pa";
// atomic from spc to cpx
inout [8:0] pcx_atm BOTH_DIR hdl_node "tb_top.cpu.spc2_pcx_atm_pq";
input [8:0] pcx_grant NSAMPLE #-0 hdl_node "tb_top.cpu.pcx_spc2_grant_px";
// N/A inout cpx_stall BOTH_DIR hdl_node "always 0";
// N/A inout cpx_rdy BOTH_DIR hdl_node "none";
// atomic from cpx to spc
// N/A inout cpx_atm BOTH_DIR hdl_node "none";
input [145:0] cpx_datai NSAMPLE #-0 hdl_node "tb_top.cpu.cpx_spc2_data_cx2";
input clk CLOCK hdl_node "tb_top.cpu.cmp_gclk_c3_spc0";
// CCX Interface Signals with SPC
inout [8:0] pcx_req BOTH_DIR hdl_node "tb_top.cpu.spc3_pcx_req_pq";
inout [129:0] pcx_datao BOTH_DIR hdl_node "tb_top.cpu.spc3_pcx_data_pa";
// atomic from spc to cpx
inout [8:0] pcx_atm BOTH_DIR hdl_node "tb_top.cpu.spc3_pcx_atm_pq";
input [8:0] pcx_grant NSAMPLE #-0 hdl_node "tb_top.cpu.pcx_spc3_grant_px";
// N/A inout cpx_stall BOTH_DIR hdl_node "always 0";
// N/A inout cpx_rdy BOTH_DIR hdl_node "none";
// atomic from cpx to spc
// N/A inout cpx_atm BOTH_DIR hdl_node "none";
input [145:0] cpx_datai NSAMPLE #-0 hdl_node "tb_top.cpu.cpx_spc3_data_cx2";
input clk CLOCK hdl_node "tb_top.cpu.cmp_gclk_c3_spc0";
// CCX Interface Signals with SPC
inout [8:0] pcx_req BOTH_DIR hdl_node "tb_top.cpu.spc4_pcx_req_pq";
inout [129:0] pcx_datao BOTH_DIR hdl_node "tb_top.cpu.spc4_pcx_data_pa";
// atomic from spc to cpx
inout [8:0] pcx_atm BOTH_DIR hdl_node "tb_top.cpu.spc4_pcx_atm_pq";
input [8:0] pcx_grant NSAMPLE #-0 hdl_node "tb_top.cpu.pcx_spc4_grant_px";
// N/A inout cpx_stall BOTH_DIR hdl_node "always 0";
// N/A inout cpx_rdy BOTH_DIR hdl_node "none";
// atomic from cpx to spc
// N/A inout cpx_atm BOTH_DIR hdl_node "none";
input [145:0] cpx_datai NSAMPLE #-0 hdl_node "tb_top.cpu.cpx_spc4_data_cx2";
input clk CLOCK hdl_node "tb_top.cpu.cmp_gclk_c3_spc0";
// CCX Interface Signals with SPC
inout [8:0] pcx_req BOTH_DIR hdl_node "tb_top.cpu.spc5_pcx_req_pq";
inout [129:0] pcx_datao BOTH_DIR hdl_node "tb_top.cpu.spc5_pcx_data_pa";
// atomic from spc to cpx
inout [8:0] pcx_atm BOTH_DIR hdl_node "tb_top.cpu.spc5_pcx_atm_pq";
input [8:0] pcx_grant NSAMPLE #-0 hdl_node "tb_top.cpu.pcx_spc5_grant_px";
// N/A inout cpx_stall BOTH_DIR hdl_node "always 0";
// N/A inout cpx_rdy BOTH_DIR hdl_node "none";
// atomic from cpx to spc
// N/A inout cpx_atm BOTH_DIR hdl_node "none";
input [145:0] cpx_datai NSAMPLE #-0 hdl_node "tb_top.cpu.cpx_spc5_data_cx2";
input clk CLOCK hdl_node "tb_top.cpu.cmp_gclk_c3_spc0";
// CCX Interface Signals with SPC
inout [8:0] pcx_req BOTH_DIR hdl_node "tb_top.cpu.spc6_pcx_req_pq";
inout [129:0] pcx_datao BOTH_DIR hdl_node "tb_top.cpu.spc6_pcx_data_pa";
// atomic from spc to cpx
inout [8:0] pcx_atm BOTH_DIR hdl_node "tb_top.cpu.spc6_pcx_atm_pq";
input [8:0] pcx_grant NSAMPLE #-0 hdl_node "tb_top.cpu.pcx_spc6_grant_px";
// N/A inout cpx_stall BOTH_DIR hdl_node "always 0";
// N/A inout cpx_rdy BOTH_DIR hdl_node "none";
// atomic from cpx to spc
// N/A inout cpx_atm BOTH_DIR hdl_node "none";
input [145:0] cpx_datai NSAMPLE #-0 hdl_node "tb_top.cpu.cpx_spc6_data_cx2";
input clk CLOCK hdl_node "tb_top.cpu.cmp_gclk_c3_spc0";
// CCX Interface Signals with SPC
inout [8:0] pcx_req BOTH_DIR hdl_node "tb_top.cpu.spc7_pcx_req_pq";
inout [129:0] pcx_datao BOTH_DIR hdl_node "tb_top.cpu.spc7_pcx_data_pa";
// atomic from spc to cpx
inout [8:0] pcx_atm BOTH_DIR hdl_node "tb_top.cpu.spc7_pcx_atm_pq";
input [8:0] pcx_grant NSAMPLE #-0 hdl_node "tb_top.cpu.pcx_spc7_grant_px";
// N/A inout cpx_stall BOTH_DIR hdl_node "always 0";
// N/A inout cpx_rdy BOTH_DIR hdl_node "none";
// atomic from cpx to spc
// N/A inout cpx_atm BOTH_DIR hdl_node "none";
input [145:0] cpx_datai NSAMPLE #-0 hdl_node "tb_top.cpu.cpx_spc7_data_cx2";