Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / env / common / vera / classes / baseAsmToVeraIntf.vr
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//
// OpenSPARC T2 Processor File: baseAsmToVeraIntf.vr
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#include "registerSlamVerilogTasks.vri"
virtual class BaseAsmToVeraIntf {
// generic asm-to-vera user event
task generic_ev(string arg1_str,
reg [63:0] arg2_64bits,
reg [63:0] arg3_64bits)
{
error("BaseAsmToVeraIntf::generic_ev should not be called for this bench! Check your diag.\n");
}
// trig_pc_d(kind, 64'h1234567812345678) -> intp(tid, type, vector) hex, w/no 64'h
// trig_pc_d(kind, 64'h1234567812345678) -> intp(tid, type, vector, src, wait)
task intp(reg [5:0] tid = 0,
reg [63:0] type = 0,
reg [63:0] vec = 0,
integer src = 16, // 0-16 are ccx ports. 16 = NCU
integer wait = 0)
{
error("BaseAsmToVeraIntf::intp should not be called for this bench! Check your diag.\n");
}
// dump actual RAM contents
// trig_pc_d(1,expr(@VA(.MAIN.T1_ext_intr_200), 16, 16)) -> dump_mem(addr, amount)
task dump_mem(reg [63:0] addr=0,
integer amount = 8)
{
error("BaseAsmToVeraIntf::dump_mem should not be called for this bench! Check your diag.\n");
}
// trig_pc_d(1,expr(@VA(.MAIN.T1_ext_intr_200), 16, 16)) -> extint(wait/delay)
task extint(integer wait = 0, integer width = 0)
{
error("BaseAsmToVeraIntf::extint should not be called for this bench! Check your diag.\n");
}
task warmrst(integer wait = 0)
{
error("BaseAsmToVeraIntf::warmrst should not be called for this bench! Check your diag.\n");
}
// SPC BFM will do a store. Pick correct port w/ BFM!!!
// trig_pc_d(1,...) -> store(cpu/ccxPort, addr, data)
task store(reg [7:0] ccxPortMask = 0,
reg [63:0] addr=0,
reg [63:0] data=0)
{
error("BaseAsmToVeraIntf::store should not be called for this bench! Check your diag.\n");
}
// trig_pc_d(1,...) -> cpx_stall(cpu/ccxPort mask [7:0], length)
// does not use CPX stall input!
// need to force internal CCX signals.
// DO THIS IN HERE.
task cpx_stall(reg [7:0] ccxPortMask = 0, // cpu ID
integer length = 0,
integer wait = 0)
{
error("BaseAsmToVeraIntf::cpx_stall should not be called for this bench! Check your diag.\n");
}
// Task for counting the traps taken, used in random error injection
task L2ErrTrapCount( reg [8:0] count=0)
{
error("BaseAsmToVeraIntf::L2ErrTrapCount should not be called for this bench! Check your diag.\n")
;
}
// Random error injection in CCM Data Array
task L2DAErrInjection( integer injectErr=0)
{
error("BaseAsmToVeraIntf::L2DAErrInjection should not be called for this bench! Check your diag.\n")
;
}
// Random error injection in CCM tag Array
task L2TAErrInjection( integer errorInject=0)
{
error("BaseAsmToVeraIntf::L2TAErrInjection should not be called for this bench! Check your diag.\n")
;
}
task IosErrInj (string errtype, bit [15:0] ctag, bit [39:0] pa)
{
error("BaseAsmToVeraIntf::IosErrInj should not be called for this bench! Check your diag.\n");
}
task IosRandErrInj (string errtype, integer num_errs, integer weight)
{
error("BaseAsmToVeraIntf::IosRandErrInj should not be called for this bench! Check your diag.\n");
}
//SIU stub will do a dma rd starting with the address
//will do a dma rd's of that number of cache lines
task siuDmaRd(reg [63:0] addr=0,
integer amount=0)
{
error("BaseAsmToVeraIntf::siuDmaRd should not be called for this bench! Check your diag.\n");
}
//SIU stub will do a dma write starting with the address
//for the number of cache of lines shown
task siuDmaWri(reg [63:0] addr=0,
integer amount=0)
{
error("BaseAsmToVeraIntf::siuDmaWri should not be called for this bench! Check your diag.\n");
}
//SIU stun will do a merged wr8 to the address shown below
task siuDmaWr8(reg [63:0] addr=0,
reg [63:0] data=0,
reg [63:0] size=0)
{
error("BaseAsmToVeraIntf::siuDmaWr8 should not be called for this bench! Check your diag.\n");
}
// if rdwr = 0 JTAG DRIVER will do a read from the address and
// compare with data (asm to VERA)
// if rdwr = 1 JTAG DRIVER will write to address and data (VERA to asm)
task jtagRdWrL2(reg [63:0] paAddr=0,
reg [63:0] data=0,
reg [63:0] jtagDoneAddrMem=0,
reg rdwr=0)
{
error("BaseAsmToVeraIntf::jtagRdWrL2 should not be called for this bench! Check your diag.\n");
}
task pktGenConfig(integer mac_port, integer frame_type, integer frame_class, integer data_length,
(integer tx_multi_port = 0, integer data_length_p1 = -1))
{
error("BaseAsmToVeraIntf::pktGenConfig should not be called for this bench! Check your diag.\n");
}
task NIU_SetTxRingKick(integer mac_port, integer dma_no,
(integer tx_multi_port = 0, bit [15:0] tx_multi_dma_p0 = 16'h0, bit [15:0] tx_multi_dma_p1 = 16'h0))
{
error("BaseAsmToVeraIntf::NIU_SetTxRingKick should not be called for this bench! Check your diag.\n");
}
task NIU_AddTxChannels(integer mac_port, integer dma_no,
(integer tx_multi_port = 0, bit [15:0] tx_multi_dma_p0 = 16'h0, bit [15:0] tx_multi_dma_p1 = 16'h0))
{
error("BaseAsmToVeraIntf::NIU_AddTxChannels should not be called for this bench! Check your diag.\n");
}
task NIU_SetTxMaxBurst(integer mac_port, integer dma_no, integer SetTxMaxBurst_Data,
(integer tx_multi_port = 0, bit [15:0] tx_multi_dma_p0 = 16'h0, bit [15:0] tx_multi_dma_p1 = 16'h0))
{
error("BaseAsmToVeraIntf::NIU_SetTxMaxBurst should not be called for this bench! Check your diag.\n");
}
task NIU_InitTxDma(integer mac_port, integer dma_no, bit Xlate,
(integer tx_multi_port = 0, bit [15:0] tx_multi_dma_p0 = 16'h0, bit [15:0] tx_multi_dma_p1 = 16'h0))
{
error("BaseAsmToVeraIntf::NIU_InitTxDma should not be called for this bench! Check your diag.\n");
}
task NIU_TxDMAActivate(integer mac_port, integer dma_activelist,
(integer tx_multi_port = 0, bit [15:0] tx_multi_dma_p0 = 16'h0, bit [15:0] tx_multi_dma_p1 = 16'h0))
{
error("BaseAsmToVeraIntf::NIU_TxDMAActivate should not be called for this bench! Check your diag.\n");
}
task NIU_EXIT_chk(integer mac_port)
{
error("BaseAsmToVeraIntf::NIU_EXIT_chk should not be called for this bench! Check your diag.\n");
}
task TxPktGen(integer mac_port, integer dmaport, integer numofpacket,
(integer tx_multi_port = 0, bit [15:0] tx_multi_dma_p0 = 16'h0, bit [15:0] tx_multi_dma_p1 = 16'h0))
{
error("BaseAsmToVeraIntf::TxPktGen should not be called for this bench! Check your diag.\n");
}
task NIU_InitRxDma (
integer RxDmaChnlNo,
integer RxDescRingLen,
bit [39:0] RxRingStartAddr,
bit [63:0] RbrConfData,
integer RxInitKick,
bit Xlate,
(bit [15:0] rx_multi_dma=16'h0))
{
error("BaseAsmToVeraIntf::NIU_InitRxDma should not be called for this bench! Check your diag.\n");
}
task NIU_RxPktConf(integer RxPktCnt, (integer iport = 0))
{
error("BaseAsmToVeraIntf::NIU_RxPktConf should not be called for this bench! Check your diag.\n");
}
task NIU_RxGenPkt (
integer mac_port,
integer RxDmaChnlNo,
integer RxPktCnt,
integer RxPktLen,
(integer rx_multi_PORT=0,
bit [15:0] rx_multi_DMA= 16'h0))
{
error("BaseAsmToVeraIntf::NIU_RxGenPkt should not be called for this bench! Check your diag.\n");
}
task errCpxPkt(reg [2:0] tid,
reg [3:0] type,
reg [1:0] errBits,
reg [1:0] ifill2 = 0,
reg [63:0] addr = 64'hffffffffffffffff,
reg ncValue=0)
{
error("BaseAsmToVeraIntf::errCpxPkt should not be called for this bench! Check your diag.\n");
}
task IC_hard_err_inj(reg [3:0] err_type,
reg [48:0] va,
reg [2:0] way,
reg [7:0] tid)
{
error("BaseAsmToVeraIntf::IC_hard_err_inj should not be called for this bench! Check your diag.\n");
}
task DC_hard_err_inj(reg [3:0] err_type,
reg [6:0] index,
reg [1:0] way,
reg [7:0] tid)
{
error("BaseAsmToVeraIntf::DC_hard_err_inj should not be called for this bench! Check your diag.\n");
}
task DTLB_err_enable(bit [2:0] err_type=~0,
integer err_freq=-1,
bit [1:0] merr=~0,
integer burst_len=-1,
integer burst_freq=-1,
bit [7:0] tid=~0)
{
error("BaseAsmToVeraIntf::DTLB_err_enable should not be called for this bench! Check your diag.\n");
}
task ITLB_err_enable(bit [2:0] err_type=~0,
integer err_freq=-1,
bit [1:0] merr=~0,
integer burst_len=-1,
integer burst_freq=-1,
bit [7:0] tid=~0)
{
error("BaseAsmToVeraIntf::ITLB_err_enable should not be called for this bench! Check your diag.\n");
}
task DC_err_enable(bit [3:0] err_type=~0,
integer err_freq=-1,
bit [1:0] merr=~0,
integer burst_len=-1,
integer burst_freq=-1,
bit [7:0] tid=~0)
{
error("BaseAsmToVeraIntf::DC_err_enable should not be called for this bench! Check your diag.\n");
}
task IC_err_enable(bit [3:0] err_type=~0,
integer err_freq=-1,
bit [1:0] merr=~0,
integer burst_len=-1,
integer burst_freq=-1,
bit [7:0] tid=~0)
{
error("BaseAsmToVeraIntf::IC_err_enable should not be called for this bench! Check your diag.\n");
}
task STB_err_enable(bit [4:0] err_type=~0,
integer err_freq=-1,
bit [1:0] merr=~0,
integer burst_len=-1,
integer burst_freq=-1,
bit [1:0] ue_en=~0,
integer ce_wt=-1,
bit [7:0] tid=~0)
{
error("BaseAsmToVeraIntf::STB_err_enable should not be called for this bench! Check your diag.\n");
}
task L2C_err_enable(bit [5:0] err_type=~0,
integer err_freq=-1,
integer ce_wt=-1,
integer nd_wt=-1,
integer burst_len=-1,
integer burst_freq=-1,
bit [7:0] tid=~0)
{
error("BaseAsmToVeraIntf::L2C_err_enable should not be called for this bench! Check your diag.\n");
}
task IRF_err_enable(bit [2:0] err_type=~0,
integer err_freq=-1,
integer ce_wt=-1,
reg [1:0] merr=~0,
integer burst_len=-1,
integer burst_freq=-1,
bit [7:0] tid=~0)
{
error("BaseAsmToVeraIntf::IRF_err_enable should not be called for this bench! Check your diag.\n");
}
task FRF_err_enable(bit [2:0] err_type=~0,
integer err_freq=-1,
integer ce_wt=-1,
reg [1:0] merr=~0,
integer burst_len=-1,
integer burst_freq=-1,
bit [7:0] tid=~0)
{
error("BaseAsmToVeraIntf::FRF_err_enable should not be called for this bench! Check your diag.\n");
}
task MRA_err_enable(bit [1:0] err_type=~0,
integer err_freq=-1,
reg [7:0] mra_entry=~0,
reg [1:0] wr_en=~0,
integer burst_len=-1,
integer burst_freq=-1,
bit [7:0] tid=~0)
{
error("BaseAsmToVeraIntf::MRA_err_enable should not be called for this bench! Check your diag.\n");
}
task SCA_err_enable(integer err_freq=-1,
integer ce_wt=-1,
integer burst_len=-1,
integer burst_freq=-1,
bit [7:0] tid=~0)
{
error("BaseAsmToVeraIntf::SCA_err_enable should not be called for this bench! Check your diag.\n");
}
task TSA_err_enable(bit [1:0] err_type=~0,
integer err_freq=-1,
reg [6:0] tsa_entry=~0,
reg [1:0] wr_en=~0,
integer ce_wt=-1,
integer burst_len=-1,
integer burst_freq=-1,
bit [7:0] tid=~0)
{
error("BaseAsmToVeraIntf::TSA_err_enable should not be called for this bench! Check your diag.\n");
}
task TCC_err_enable(bit [1:0] err_type=~0,
integer err_freq=-1,
integer ce_wt=-1,
integer burst_len=-1,
integer burst_freq=-1,
bit [7:0] tid=~0)
{
error("BaseAsmToVeraIntf::TCC_err_enable should not be called for this bench! Check your diag.\n");
}
task registerSlam(string registerName,
reg[127:0] value,
reg[63:0] tidMask)
{
#include "registerSlam.vri"
}
// any bench that uses this will have to provide the code it wants. Othwise
// nothing happes.
task marker(string what, reg [5:0] fromTid, reg [63:0] pc)
{
// no error msg
}
task reset_now(string what)
{
// no error msg
}
task set_StartPEUTest ()
{
error("BaseAsmToVeraIntf::set_StartPEUTest should not be called for this bench! Check your diag.\n");
}
task EnablePCIeEgCmd (string cmdType,
bit [63:0] addr,
bit [31:0] txLen,
bit [31:0] startData,
string err)
{
error("BaseAsmToVeraIntf::EnablePCIeEgCmd should not be called for this bench! Check your diag.\n");
}
task EnablePCIeIgCmd (string cmdType,
bit [63:0] StartAddr,
bit [63:0] EndAddr,
// bit [31:0] txLen,
string txLen,
bit [31:0] NumCmds,
string err)
{
error("BaseAsmToVeraIntf::EnablePCIeIgCmd should not be called for this bench! Check your diag.\n");
}
task watchDebugReg(integer which, integer wait=0,
reg verbose=0, reg [1:0] checkValue) {
error("BaseAsmToVeraIntf::watchAsiOverlapMode should not be called for this bench! Check your diag.\n");
}
task spc_warm_reset()
{
error("BaseAsmToVeraIntf::spc_warm_reset should not be called for this bench! Check your diag.\n");
}
}