verif/env/common/vera/classes/l2lat_class.vr

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// OpenSPARC T2 Processor File: l2lat_class.vr
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#include <vera_defines.vrh>
#include <defines.vri>
#include <std_display_defines.vri>
#include <globals.vri>
#include <std_display_class.vrh>

#define  MON_L2LAT    24


class L2LAT {
    reg [31:0] reqid;       // request sequence number
    reg [31:0] reqcycle;    // cycle count request was make
    reg [15:0] core;        // 0..63 or tid
    reg [39:0] pa;          // physical addr
    reg [3:0] type;        // request type (IFILL, LD, ST)
    reg [31:0] latency;     // memory latency
    reg [31:0] respcycle;   // (reqcycle + latency)
    reg [7:0] momrid;       // internal MOM id (ignored)

    task new (string str) {
        sscanf(str, "Request number %d: reqcyc=%d core=%h pa=%h type=%b lat=%d respcyc=%d momrid=%h",
                reqid,reqcycle,core,pa,type,latency,respcycle,momrid);
    }

    task print_obj (string why) {

      PR_DEBUG("l2lat", MON_L2LAT,
        psprintf("%s - ReqID %d: reqcyc=%d core=%h pa=%h type=%h lat=%d respcyc=%d momrid=%h \n",
              why,reqid,reqcycle,core,pa,type,latency,respcycle,momrid));
    }

}  // END class