verif/env/common/vera/classes/sparcParams.vrh

// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T2 Processor File: sparcParams.vrh
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
//
// For the avoidance of doubt, and except that if any non-GPL license
// choice is available it will apply instead, Sun elects to use only
// the General Public License version 2 (GPLv2) at this time for any
// software where a choice of GPL license versions is made
// available with the language indicating that GPLv2 or any later version
// may be used, or where a choice of which version of the GPL is applied is
// otherwise unspecified.
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
// CA 95054 USA or visit www.sun.com if you need additional information or
// have any questions.
//
// ========== Copyright Header End ============================================
#ifndef INC__TMP_PARAMSCLASS_VRH
#define INC__TMP_PARAMSCLASS_VRH

extern class Params extends BaseParams {
  string paramPath = null;
  string paramFile = null;
  string forceParamFile = null;
  string dv_root = null;

  string veraDiagName = null;
  string asmDiagName = null;


  // SPC2 specific
  reg l2latOn;
  reg l2lat_fixed;
  integer l2lat_value;
  reg stub_l1_enable;
  reg [7:0] min_ccx_gnt_delay;
  reg [7:0] max_ccx_gnt_delay;
  reg rand_ccx_gnt_enable;
  string l2lat_in;
  integer FPl2lat;

  reg noDebugDrv;
  reg noDebugChecks;
  reg noDebugModes;
  reg showDebugCounts;
  reg wmrVecMask;
  integer ssModeFreq;
  integer ssModeMaxSessions;
  integer ssModeInterleaveWeight;
  reg [7:0] ssModeTidMask;
  integer ssModeMin;
  integer ssModeMax;
  integer ssModeBurstMin;
  integer ssModeBurstMax;
  integer ssModeHolesMin;
  integer ssModeHolesMax;
  integer doModeFreq;
  integer doModeMaxSessions;
  reg [7:0] doModeTidMask;
  integer doModeLenMin;
  integer doModeLenMax;
  integer   softStopFreq;
  integer   softStopMaxSessions;
  reg [7:0] softStopTidMask;
  integer   softStopLenMin;
  integer   softStopLenMax;
  reg nodebugParkExit;


  reg ccxPktPrint [5];
  reg [16:0] ccxPktPrintMask;
  reg ccxPktPrintOn;
  reg mcuMemPrint [2];
  reg mcuMemPrintOn;

  reg [63:0] coreAvilableReg;
  reg [63:0] coreEnableReg;
  reg [7:0] coreAvilable;
  reg [7:0] coreEnable;
  reg [2:0] coreMax;
  reg [3:0] bank_set_mask;
  reg [7:0] banksMask;

  integer mcuReq2ackDelayMin;
  integer mcuReq2ackDelayMax;
  integer mcuAck2dataDelayMin;
  integer mcuAck2dataDelayMax;
  integer mcuIntraDataDelayMin;
  integer mcuIntraDataDelayMax;
  integer mcuWrReq2ackDelayMin;
  integer mcuWrReq2ackDelayMax;
  integer mcuWrReq2ackFullDelay;

  reg [7:0] enableSpcBFM;
  reg [7:0] enableMemBFM;

  integer stallStart;   // start stalling when this many outstanding requests
  integer stallStop;    // stop  stalling when this many outstanding requests
  integer hitRate;      // percent of time that shorter "hit" latencies will be used
  integer hitDelayMin;  // min value of latency if "hit"
  integer hitDelayMax;  // max value of latency if "hit"
  integer missDelayMin; // min value of latency if NOT "hit"
  integer missDelayMax; // max value of latency if NOT "hit"
  integer pkt2DelayMin; // min value of latency for second pkt of pair
  integer pkt2DelayMax; // max value of latency for second pkt of pair

  integer evictFloodFreq;
  integer evictFloodAmount;
  reg [7:0] evictFloodTargets;
  integer bufferFloodFreq;
  integer bufferFloodAmount;
  integer bufferFloodTarget;

  integer burstAmount;
  integer burstHoldoff;
  integer burstSync;

  reg        hash_on;
  integer    por_delay_min;
  integer    por_delay_max;
  reg        show_store;
  reg        show_load;
  integer    inval_rate;
  reg [2:0]  inval_type;
  reg[39:0]  inval_pa_min;
  reg[39:0]  inval_pa_max;
  reg [1:0]  l2miss_type;

  integer intr_tid;
  integer intr_delay;
  integer intr_wait;
  reg [1:0] intr_type;
  reg [5:0] intr_vect;
  reg [63:0] intr_en;

  integer maxCycle; // max clks
  integer timeOut;  // idle

  // POR/WMR
  reg       por_enable;
  reg       lbist_enable;
  reg [2:0] mbist_mode;
  reg       mbist_enable;
  reg       mbist_errinj;
  reg [7:0] user_loop_count;
  reg       user_loop_mode;
  reg [15:0] lbist_abort_count;
  reg  [2:0] lbist_run_count;
  reg        lbist_pgm;
  reg [23:0] mbist_fail_count;

 //err
  integer err_freq;
  integer err_burst_freq;
  integer err_burst_len_min;
  integer err_burst_len_max;
  integer err_ce_wt;
  integer err_nd_wt;
  reg rand_err;

  reg err_itlb_on;
  integer err_itlb_freq;

  reg err_dtlb_on;
  integer err_dtlb_freq;

  reg err_ic_on;
  integer err_ic_freq;

  reg err_dc_on;
  integer err_dc_freq;

  reg err_irf_on;
  integer err_irf_freq;

  reg err_frf_on;
  integer err_frf_freq;

  reg err_stb_on;
  integer err_stb_freq;

  reg err_sca_on;
  integer err_sca_freq;

  reg err_tcc_on;
  integer err_tcc_freq;

  reg err_tsa_on;
  integer err_tsa_freq;

  reg err_mra_on;
  integer err_mra_freq;

  reg err_l2c_on;
  integer err_l2c_freq;

  reg err_mamem_on;
  integer err_mamem_freq;

  // Coverage Vars
  reg coverage_on;
  reg coverage_off;
  reg force_save_cov;

  reg [63:0] finishMask;

  reg forcePORstate;

  task new (
    StandardDisplay dbgin
  );
  task getCfg (
    string fileName = null
  );
  task check4conflict (
  );
}

#endif