verif/env/common/vera/classes/systemTap.if.vri

// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T2 Processor File: systemTap.if.vri
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#ifndef INC_SYSTEMTAP_IF_VRI
#define INC_SYSTEMTAP_IF_VRI

#include <vera_defines.vrh>

// #define OUTPUT_EDGE_N  NHOLD
// #define INPUT_EDGE   PSAMPLE
// #define INPUT_SKEW   #-3

interface tb_top_tck { // to support on-demand TCK
  input   TCK                 CLOCK       verilog_node "tb_top.tck";
  inout   TCK2DUT   PSAMPLE   NHOLD       verilog_node "tb_top.tck2dut";
  output  TRST_L              NHOLD       verilog_node "`CPU.TRST_L";
}

interface jtag {
  input   TCK                 CLOCK       verilog_node "`CPU.TCK";
  input   TDO                 PSAMPLE #-3 verilog_node "`CPU.TDO";
  output  TEST_MODE           NHOLD       verilog_node "`CPU.TESTMODE";
  output  TDI                 NHOLD       verilog_node "`CPU.TDI";
  output  TMS                 NHOLD       verilog_node "`CPU.TMS";
  output  SSI_MISO            NHOLD       verilog_node "`CPU.SSI_MISO";
}

interface l2clk_if {
#ifdef TCU_GATE
  input l2clk CLOCK  verilog_node "`TCU.clkgen_tcu_cmp__cclk";
#else
  input l2clk CLOCK  verilog_node "`TCU.clkgen_tcu_cmp.l2clk";
#endif
}

port tap__port {
  tck;
  tck2dut;
  trst_n;
  test_mode;
  tms;
  tdi;
  tdo;
  ssi_miso;
  l2clk;
}

bind tap__port tap_bind {
  tck           tb_top_tck.TCK;
  tck2dut       tb_top_tck.TCK2DUT;
  trst_n        tb_top_tck.TRST_L;
  test_mode     jtag.TEST_MODE;
  tms           jtag.TMS;
  tdi           jtag.TDI;
  tdo           jtag.TDO;
  ssi_miso      jtag.SSI_MISO;
  l2clk         l2clk_if.l2clk;
}


#endif