verif/env/common/verilog/axis_traps/axis_trap_top.v

// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T2 Processor File: axis_trap_top.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
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// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
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// This program is distributed in the hope that it will be useful,
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
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// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
//
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// choice is available it will apply instead, Sun elects to use only
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// ========== Copyright Header End ============================================
module axis_trap_top(pc_dmp_sz);
input [21:0] pc_dmp_sz;

//`include "defines.vh"
//`include "nas.vh"

// wires for asm user events
//`include "asmEventsProbes.vh"

//----------------------------------------------------------
// Instantiate 1-8 cores
`ifdef CORE_0
  axis_trap_core0 c0 (3'h0,pc_dmp_sz);
`endif
`ifdef CORE_1
  axis_trap_core1 c1 (3'h1,pc_dmp_sz);
`endif
`ifdef CORE_2
  axis_trap_core2 c2 (3'h2,pc_dmp_sz);
`endif
`ifdef CORE_3
  axis_trap_core3 c3 (3'h3,pc_dmp_sz);
`endif
`ifdef CORE_4
  axis_trap_core4 c4 (3'h4,pc_dmp_sz);
`endif
`ifdef CORE_5
  axis_trap_core5 c5 (3'h5,pc_dmp_sz);
`endif
`ifdef CORE_6
  axis_trap_core6 c6 (3'h6,pc_dmp_sz);
`endif
`ifdef CORE_7
  axis_trap_core7 c7 (3'h7,pc_dmp_sz);
`endif

//----------------------------------------------------------
endmodule
//----------------------------------------------------------
//----------------------------------------------------------