verif/env/common/verilog/err_random/L2_RST.v

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// OpenSPARC T2 Processor File: L2_RST.v
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module L2_RST();

//parameter DELAY = 15744276;
parameter DELAY = 12638748;

//--------------------------------------------------------------------------------------
// Enable/Disable support : MAQ
//--------------------------------------------------------------------------------------

wire L2_INT_RST = `TOP.flush_reset_complete;

// MAQ :reg L2_INT_RST;
//--------------------------------------------------------------------------------------
wire [23:0] err_cnt,cpx_pkt,desr_cnt;

l2err_ccm      l2err_ccm(L2_INT_RST,err_cnt); // Data Array CE Err injector, only bank0
l2err_checker  l2err_checker(L2_INT_RST,cpx_pkt,desr_cnt);
l2err_scrbrd   l2err_scrbrd(cpx_pkt,desr_cnt,err_cnt);
TagArray       TagArray(L2_INT_RST); //TAG Array CE err injector
vuaderr        vuaderr(L2_INT_RST); // VUAD CE Err injector
l2ue_errinj    l2ue_errinj(L2_INT_RST,err_cnt); // UE Err Injector. all banks


// MAQ :
// MAQ :initial
// MAQ :begin
// MAQ :
// MAQ :L2_INT_RST = 0;
// MAQ :forever #(DELAY)  L2_INT_RST = 1;
// MAQ :
// MAQ :end


endmodule