verif/env/common/verilog/ldst_sync/ldst_ncu.v

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//
// OpenSPARC T2 Processor File: ldst_ncu.v
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module ldst_ncu ();
`ifndef GATESIM
`ifdef NCURTL

// common defines
`include "defines.vh"
`include "nas.vh"
// PCX/CPX packet defines (see :/verif/env/common/vera/include)
`include "ccx.vri"
`include "cmp.vri"

//---------------------
// Wires

//----------------------------------------------------------
//----------------------------------------------------------
// DUT probes

  wire                     ncu_cpx_valid;
  wire              [39:0] ncu_cpx_pa;
  wire               [2:0] ncu_cpx_cid;
  wire               [2:0] ncu_cpx_tid;
  wire               [4:0] ncu_cpx_typ;
  wire               [7:0] ncu_cpx_bmask;

  // Bench is probing the PCX packet.
  // But, the signals names are "*cpx*" so they match other signals in ldst_l2.vpal.

  // These signals are probed by ldst_l2.vpal.  Do not change the names.
  assign  ncu_cpx_typ   = `CPU.ncu.ncu_fcd_ctl.ncu_c2ifcd_ctl.ncu_c2ifd_ctl.pcx_ncu_data[`PCX_RQTYP];
  assign  ncu_cpx_pa    = `CPU.ncu.ncu_fcd_ctl.ncu_c2ifcd_ctl.ncu_c2ifd_ctl.pcx_ncu_data[`PCX_ADDR];
  assign  ncu_cpx_cid   = `CPU.ncu.ncu_fcd_ctl.ncu_c2ifcd_ctl.ncu_c2ifd_ctl.pcx_ncu_data[`PCX_CID];
  assign  ncu_cpx_tid   = `CPU.ncu.ncu_fcd_ctl.ncu_c2ifcd_ctl.ncu_c2ifd_ctl.pcx_ncu_data[`PCX_TID];
  assign  ncu_cpx_valid = `CPU.ncu.ncu_fcd_ctl.ncu_c2ifcd_ctl.ncu_c2ifd_ctl.pcx_ncu_vld &&
                          `CPU.ncu.ncu_fcd_ctl.ncu_c2ifcd_ctl.ncu_c2ifc_ctl.pcx_ncu_data_rdy;
  assign  ncu_cpx_bmask = `CPU.ncu.ncu_fcd_ctl.ncu_c2ifcd_ctl.ncu_c2ifd_ctl.pcx_ncu_data[`PCX_SIZE];

//----------------------------------------------------------
`endif
`endif
endmodule

//----------------------------------------------------------