verif/env/common/verilog/monitors/monitors.v

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//
// OpenSPARC T2 Processor File: monitors.v
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module monitors;


  `ifdef CORE_0
//    ma_mon_c0 ma_mon_c0();
    lsu_mon_c0 lsu_mon_c0 ();
    lru_mon_c0 lru_mon_c0 ();
  `endif


  `ifdef CORE_1
//    ma_mon_c1 ma_mon_c1();
    lsu_mon_c1 lsu_mon_c1 ();
    lru_mon_c1 lru_mon_c1 ();
  `endif


  `ifdef CORE_2
//    ma_mon_c2 ma_mon_c2();
    lsu_mon_c2 lsu_mon_c2 ();
    lru_mon_c2 lru_mon_c2 ();
  `endif


  `ifdef CORE_3
//    ma_mon_c3 ma_mon_c3();
    lsu_mon_c3 lsu_mon_c3 ();
    lru_mon_c3 lru_mon_c3 ();
  `endif


  `ifdef CORE_4
//    ma_mon_c4 ma_mon_c4();
    lsu_mon_c4 lsu_mon_c4 ();
    lru_mon_c4 lru_mon_c4 ();
  `endif


  `ifdef CORE_5
//    ma_mon_c5 ma_mon_c5();
    lsu_mon_c5 lsu_mon_c5 ();
    lru_mon_c5 lru_mon_c5 ();
  `endif


  `ifdef CORE_6
//    ma_mon_c6 ma_mon_c6();
    lsu_mon_c6 lsu_mon_c6 ();
    lru_mon_c6 lru_mon_c6 ();
  `endif


  `ifdef CORE_7
//    ma_mon_c7 ma_mon_c7();
    lsu_mon_c7 lsu_mon_c7 ();
    lru_mon_c7 lru_mon_c7 ();
  `endif

global_chkr global_chkr();

endmodule
//----------------------------------------------------------