// ========== Copyright Header Begin ==========================================
// OpenSPARC T2 Processor File: nas.vh
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
// For the avoidance of doubt, and except that if any non-GPL license
// choice is available it will apply instead, Sun elects to use only
// the General Public License version 2 (GPLv2) at this time for any
// software where a choice of GPL license versions is made
// available with the language indicating that GPLv2 or any later version
// may be used, or where a choice of which version of the GPL is applied is
// otherwise unspecified.
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
// CA 95054 USA or visit www.sun.com if you need additional information or
// ========== Copyright Header End ============================================
//----------------------------------------------------------
`define NASTOP `TOP.nas_top
`define EXP_QUEUE `NASTOP.exp_queue
`define ACT_QUEUE `NASTOP.act_queue
`define EXP_STATUS `NASTOP.exp_status
`define ACT_STATUS `NASTOP.act_status
`define FRF0_EVEN `SPC0.fgu.frf.frf_array_e.data_array
`define FRF0_ODD `SPC0.fgu.frf.frf_array_o.data_array
`define IRF0_EXU0 `SPC0.exu0.irf.irf_array.active_window
`define IRF0_EXU1 `SPC0.exu1.irf.irf_array.active_window
`define FRF1_EVEN `SPC1.fgu.frf.frf_array_e.data_array
`define FRF1_ODD `SPC1.fgu.frf.frf_array_o.data_array
`define IRF1_EXU0 `SPC1.exu0.irf.irf_array.active_window
`define IRF1_EXU1 `SPC1.exu1.irf.irf_array.active_window
`define FRF2_EVEN `SPC2.fgu.frf.frf_array_e.data_array
`define FRF2_ODD `SPC2.fgu.frf.frf_array_o.data_array
`define IRF2_EXU0 `SPC2.exu0.irf.irf_array.active_window
`define IRF2_EXU1 `SPC2.exu1.irf.irf_array.active_window
`define FRF3_EVEN `SPC3.fgu.frf.frf_array_e.data_array
`define FRF3_ODD `SPC3.fgu.frf.frf_array_o.data_array
`define IRF3_EXU0 `SPC3.exu0.irf.irf_array.active_window
`define IRF3_EXU1 `SPC3.exu1.irf.irf_array.active_window
`define FRF4_EVEN `SPC4.fgu.frf.frf_array_e.data_array
`define FRF4_ODD `SPC4.fgu.frf.frf_array_o.data_array
`define IRF4_EXU0 `SPC4.exu0.irf.irf_array.active_window
`define IRF4_EXU1 `SPC4.exu1.irf.irf_array.active_window
`define FRF5_EVEN `SPC5.fgu.frf.frf_array_e.data_array
`define FRF5_ODD `SPC5.fgu.frf.frf_array_o.data_array
`define IRF5_EXU0 `SPC5.exu0.irf.irf_array.active_window
`define IRF5_EXU1 `SPC5.exu1.irf.irf_array.active_window
`define FRF6_EVEN `SPC6.fgu.frf.frf_array_e.data_array
`define FRF6_ODD `SPC6.fgu.frf.frf_array_o.data_array
`define IRF6_EXU0 `SPC6.exu0.irf.irf_array.active_window
`define IRF6_EXU1 `SPC6.exu1.irf.irf_array.active_window
`define FRF7_EVEN `SPC7.fgu.frf.frf_array_e.data_array
`define FRF7_ODD `SPC7.fgu.frf.frf_array_o.data_array
`define IRF7_EXU0 `SPC7.exu0.irf.irf_array.active_window
`define IRF7_EXU1 `SPC7.exu1.irf.irf_array.active_window
//----------------------------------------------------------
//----------------------------------------------------------
// Number of registers in delta_Q
`define MAX_INDEX `FIRST_INDEX+32
// Number of bits in delta reg arrays
`define DELTA_WIDTH (2+3+8+64)-1
//----------------------------------------------------------
// Note: register indexes must be the same as simics
// here's the order of regs in prev_reg
// [132-224] - C [32-124]
`define MAX_ID 224 // for prev_reg index
`define ECACHE_ERROR_ENABLE 96
`define ASYNCHRONOUS_FAULT_STATUS 97
`define ASYNCHRONOUS_FAULT_ADDRESS 98
`define OUT_INTR_DATA0 99
`define OUT_INTR_DATA1 100
`define OUT_INTR_DATA2 101
`define INTR_DISPATCH_STATUS 102
`define IN_INTR_DATA0 103
`define IN_INTR_DATA1 104
`define IN_INTR_DATA2 105
`define CTXT_PRIM_0 126 // 21/8
`define CTXT_SEC_0 127 // 21/10
`define CTXT_PRIM_1 128 // 21/108
`define CTXT_SEC_1 129 // 21/110
`define LSU_CONTROL 130 // 45/0
`define I_TAG_ACC 131 // 50/30
`define CTXT_Z_TSB_CFG0 132 // 54/10
`define CTXT_Z_TSB_CFG1 133 // 54/18
`define CTXT_Z_TSB_CFG2 134 // 54/20
`define CTXT_Z_TSB_CFG3 135 // 54/28
`define CTXT_NZ_TSB_CFG0 136 // 54/30
`define CTXT_NZ_TSB_CFG1 137 // 54/38
`define CTXT_NZ_TSB_CFG2 138 // 54/40
`define CTXT_NZ_TSB_CFG3 139 // 54/48
`define I_DATA_IN 140 // 54
`define D_TAG_ACC 141 // 58/30
`define WATCHPOINT_ADDR 142 // 58/38
`define D_DATA_IN 143 // 5c
// Can't create control register at 155 because it will collide
// with OPCODE at 255 since we add 100 to all control register IDs
`define NAS_PIPE_RESERVED 155
//----------------------------------------------------------
//----------------------------------------------------------
//----------------------------------------------------------