// ========== Copyright Header Begin ==========================================
// OpenSPARC T2 Processor File: nas_pipe.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
// For the avoidance of doubt, and except that if any non-GPL license
// choice is available it will apply instead, Sun elects to use only
// the General Public License version 2 (GPLv2) at this time for any
// software where a choice of GPL license versions is made
// available with the language indicating that GPLv2 or any later version
// may be used, or where a choice of which version of the GPL is applied is
// otherwise unspecified.
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
// CA 95054 USA or visit www.sun.com if you need additional information or
// ========== Copyright Header End ============================================
//----------------------------------------------------------
input [71:0] TICK_CMPR_reg;
input [71:0] STICK_CMPR_reg;
input [71:0] HSTICK_CMPR_reg;
input [2:0] CANRESTORE_reg;
input [2:0] OTHERWIN_reg;
input [2:0] CLEANWIN_reg;
input [16:0] SOFTINT_reg;
input [16:0] rd_SOFTINT_reg;
input [63:0] INTR_RECEIVE_reg;
input [12:0] HPSTATE_reg;
input [63:0] CTXT_PRIM_0_reg;
input [63:0] CTXT_SEC_0_reg;
input [63:0] CTXT_PRIM_1_reg;
input [63:0] CTXT_SEC_1_reg;
input [63:0] LSU_CONTROL_reg;
input [63:0] I_TAG_ACC_reg;
input [63:0] D_TAG_ACC_reg;
input [63:0] WATCHPOINT_ADDR_reg;
input [151:0] Trap_Entry_1;
input [151:0] Trap_Entry_2;
input [151:0] Trap_Entry_3;
input [151:0] Trap_Entry_4;
input [151:0] Trap_Entry_5;
input [151:0] Trap_Entry_6;
input [1:0] frf_w2_valid;
input [1:0] frf_w1_valid;
input asi_valid; // ASI/ASR/PR writes done ..
input asi_in_progress; // ASI/ASR/PR in progess
//----------------------------------------------------------
//----------------------------------------------------------
//----------------------------------------------------------
// delta_* = {type(2bits),win(3bits),regnum(8bits),value(64bits)}
reg [`DELTA_WIDTH:0] delta_fx4 [0:(`MAX_INDEX)];
reg [`DELTA_WIDTH:0] delta_fx5 [0:(`MAX_INDEX)];
reg [`DELTA_WIDTH:0] delta_fb [0:(`MAX_INDEX)];
reg [`DELTA_WIDTH:0] delta_fw [0:(`MAX_INDEX)];
reg [`DELTA_WIDTH:0] delta_fw1 [0:(`MAX_INDEX)];
reg [`DELTA_WIDTH:0] delta_fw2 [0:(`MAX_INDEX)];
reg [`DELTA_WIDTH:0] delta_prev [0:(`MAX_INDEX)];
// need to change in several places in this file
reg [63:0] prev_reg0; // includes G,W,C,F registers
reg [63:0] prev_reg1; // includes G,W,C,F registers
reg [63:0] prev_reg2; // includes G,W,C,F registers
reg [63:0] prev_reg3; // includes G,W,C,F registers
reg [63:0] prev_reg4; // includes G,W,C,F registers
reg [63:0] prev_reg5; // includes G,W,C,F registers
reg [63:0] prev_reg6; // includes G,W,C,F registers
reg [63:0] prev_reg7; // includes G,W,C,F registers
reg [63:0] prev_reg8; // includes G,W,C,F registers
reg [63:0] prev_reg9; // includes G,W,C,F registers
reg [63:0] prev_reg10; // includes G,W,C,F registers
reg [63:0] prev_reg11; // includes G,W,C,F registers
reg [63:0] prev_reg12; // includes G,W,C,F registers
reg [63:0] prev_reg13; // includes G,W,C,F registers
reg [63:0] prev_reg14; // includes G,W,C,F registers
reg [63:0] prev_reg15; // includes G,W,C,F registers
reg [63:0] prev_reg16; // includes G,W,C,F registers
reg [63:0] prev_reg17; // includes G,W,C,F registers
reg [63:0] prev_reg18; // includes G,W,C,F registers
reg [63:0] prev_reg19; // includes G,W,C,F registers
reg [63:0] prev_reg20; // includes G,W,C,F registers
reg [63:0] prev_reg21; // includes G,W,C,F registers
reg [63:0] prev_reg22; // includes G,W,C,F registers
reg [63:0] prev_reg23; // includes G,W,C,F registers
reg [63:0] prev_reg24; // includes G,W,C,F registers
reg [63:0] prev_reg25; // includes G,W,C,F registers
reg [63:0] prev_reg26; // includes G,W,C,F registers
reg [63:0] prev_reg27; // includes G,W,C,F registers
reg [63:0] prev_reg28; // includes G,W,C,F registers
reg [63:0] prev_reg29; // includes G,W,C,F registers
reg [63:0] prev_reg30; // includes G,W,C,F registers
reg [63:0] prev_reg31; // includes G,W,C,F registers
reg [63:0] prev_reg32; // includes G,W,C,F registers
reg [63:0] prev_reg33; // includes G,W,C,F registers
reg [63:0] prev_reg34; // includes G,W,C,F registers
reg [63:0] prev_reg35; // includes G,W,C,F registers
reg [63:0] prev_reg36; // includes G,W,C,F registers
reg [63:0] prev_reg37; // includes G,W,C,F registers
reg [63:0] prev_reg38; // includes G,W,C,F registers
reg [63:0] prev_reg39; // includes G,W,C,F registers
reg [63:0] prev_reg40; // includes G,W,C,F registers
reg [63:0] prev_reg41; // includes G,W,C,F registers
reg [63:0] prev_reg42; // includes G,W,C,F registers
reg [63:0] prev_reg43; // includes G,W,C,F registers
reg [63:0] prev_reg44; // includes G,W,C,F registers
reg [63:0] prev_reg45; // includes G,W,C,F registers
reg [63:0] prev_reg46; // includes G,W,C,F registers
reg [63:0] prev_reg47; // includes G,W,C,F registers
reg [63:0] prev_reg48; // includes G,W,C,F registers
reg [63:0] prev_reg49; // includes G,W,C,F registers
reg [63:0] prev_reg50; // includes G,W,C,F registers
reg [63:0] prev_reg51; // includes G,W,C,F registers
reg [63:0] prev_reg52; // includes G,W,C,F registers
reg [63:0] prev_reg53; // includes G,W,C,F registers
reg [63:0] prev_reg54; // includes G,W,C,F registers
reg [63:0] prev_reg55; // includes G,W,C,F registers
reg [63:0] prev_reg56; // includes G,W,C,F registers
reg [63:0] prev_reg57; // includes G,W,C,F registers
reg [63:0] prev_reg58; // includes G,W,C,F registers
reg [63:0] prev_reg59; // includes G,W,C,F registers
reg [63:0] prev_reg60; // includes G,W,C,F registers
reg [63:0] prev_reg61; // includes G,W,C,F registers
reg [63:0] prev_reg62; // includes G,W,C,F registers
reg [63:0] prev_reg63; // includes G,W,C,F registers
reg [63:0] prev_reg64; // includes G,W,C,F registers
reg [63:0] prev_reg65; // includes G,W,C,F registers
reg [63:0] prev_reg66; // includes G,W,C,F registers
reg [63:0] prev_reg67; // includes G,W,C,F registers
reg [63:0] prev_reg68; // includes G,W,C,F registers
reg [63:0] prev_reg69; // includes G,W,C,F registers
reg [63:0] prev_reg70; // includes G,W,C,F registers
reg [63:0] prev_reg71; // includes G,W,C,F registers
reg [63:0] prev_reg72; // includes G,W,C,F registers
reg [63:0] prev_reg73; // includes G,W,C,F registers
reg [63:0] prev_reg74; // includes G,W,C,F registers
reg [63:0] prev_reg75; // includes G,W,C,F registers
reg [63:0] prev_reg76; // includes G,W,C,F registers
reg [63:0] prev_reg77; // includes G,W,C,F registers
reg [63:0] prev_reg78; // includes G,W,C,F registers
reg [63:0] prev_reg79; // includes G,W,C,F registers
reg [63:0] prev_reg80; // includes G,W,C,F registers
reg [63:0] prev_reg81; // includes G,W,C,F registers
reg [63:0] prev_reg82; // includes G,W,C,F registers
reg [63:0] prev_reg83; // includes G,W,C,F registers
reg [63:0] prev_reg84; // includes G,W,C,F registers
reg [63:0] prev_reg85; // includes G,W,C,F registers
reg [63:0] prev_reg86; // includes G,W,C,F registers
reg [63:0] prev_reg87; // includes G,W,C,F registers
reg [63:0] prev_reg88; // includes G,W,C,F registers
reg [63:0] prev_reg89; // includes G,W,C,F registers
reg [63:0] prev_reg90; // includes G,W,C,F registers
reg [63:0] prev_reg91; // includes G,W,C,F registers
reg [63:0] prev_reg92; // includes G,W,C,F registers
reg [63:0] prev_reg93; // includes G,W,C,F registers
reg [63:0] prev_reg94; // includes G,W,C,F registers
reg [63:0] prev_reg95; // includes G,W,C,F registers
reg [63:0] prev_reg96; // includes G,W,C,F registers
reg [63:0] prev_reg97; // includes G,W,C,F registers
reg [63:0] prev_reg98; // includes G,W,C,F registers
reg [63:0] prev_reg99; // includes G,W,C,F registers
reg [63:0] prev_reg100; // includes G,W,C,F registers
reg [63:0] prev_reg101; // includes G,W,C,F registers
reg [63:0] prev_reg102; // includes G,W,C,F registers
reg [63:0] prev_reg103; // includes G,W,C,F registers
reg [63:0] prev_reg104; // includes G,W,C,F registers
reg [63:0] prev_reg105; // includes G,W,C,F registers
reg [63:0] prev_reg106; // includes G,W,C,F registers
reg [63:0] prev_reg107; // includes G,W,C,F registers
reg [63:0] prev_reg108; // includes G,W,C,F registers
reg [63:0] prev_reg109; // includes G,W,C,F registers
reg [63:0] prev_reg110; // includes G,W,C,F registers
reg [63:0] prev_reg111; // includes G,W,C,F registers
reg [63:0] prev_reg112; // includes G,W,C,F registers
reg [63:0] prev_reg113; // includes G,W,C,F registers
reg [63:0] prev_reg114; // includes G,W,C,F registers
reg [63:0] prev_reg115; // includes G,W,C,F registers
reg [63:0] prev_reg116; // includes G,W,C,F registers
reg [63:0] prev_reg117; // includes G,W,C,F registers
reg [63:0] prev_reg118; // includes G,W,C,F registers
reg [63:0] prev_reg119; // includes G,W,C,F registers
reg [63:0] prev_reg120; // includes G,W,C,F registers
reg [63:0] prev_reg121; // includes G,W,C,F registers
reg [63:0] prev_reg122; // includes G,W,C,F registers
reg [63:0] prev_reg123; // includes G,W,C,F registers
reg [63:0] prev_reg124; // includes G,W,C,F registers
reg [63:0] prev_reg125; // includes G,W,C,F registers
reg [63:0] prev_reg126; // includes G,W,C,F registers
reg [63:0] prev_reg127; // includes G,W,C,F registers
reg [63:0] prev_reg128; // includes G,W,C,F registers
reg [63:0] prev_reg129; // includes G,W,C,F registers
reg [63:0] prev_reg130; // includes G,W,C,F registers
reg [63:0] prev_reg131; // includes G,W,C,F registers
reg [63:0] prev_reg132; // includes G,W,C,F registers
reg [63:0] prev_reg133; // includes G,W,C,F registers
reg [63:0] prev_reg134; // includes G,W,C,F registers
reg [63:0] prev_reg135; // includes G,W,C,F registers
reg [63:0] prev_reg136; // includes G,W,C,F registers
reg [63:0] prev_reg137; // includes G,W,C,F registers
reg [63:0] prev_reg138; // includes G,W,C,F registers
reg [63:0] prev_reg139; // includes G,W,C,F registers
reg [63:0] prev_reg140; // includes G,W,C,F registers
reg [63:0] prev_reg141; // includes G,W,C,F registers
reg [63:0] prev_reg142; // includes G,W,C,F registers
reg [63:0] prev_reg143; // includes G,W,C,F registers
reg [63:0] prev_reg144; // includes G,W,C,F registers
reg [63:0] prev_reg145; // includes G,W,C,F registers
reg [63:0] prev_reg146; // includes G,W,C,F registers
reg [63:0] prev_reg147; // includes G,W,C,F registers
reg [63:0] prev_reg148; // includes G,W,C,F registers
reg [63:0] prev_reg149; // includes G,W,C,F registers
reg [63:0] prev_reg150; // includes G,W,C,F registers
reg [63:0] prev_reg151; // includes G,W,C,F registers
reg [63:0] prev_reg152; // includes G,W,C,F registers
reg [63:0] prev_reg153; // includes G,W,C,F registers
reg [63:0] prev_reg154; // includes G,W,C,F registers
reg [63:0] prev_reg155; // includes G,W,C,F registers
reg [63:0] prev_reg156; // includes G,W,C,F registers
reg [63:0] prev_reg157; // includes G,W,C,F registers
reg [63:0] prev_reg158; // includes G,W,C,F registers
reg [63:0] prev_reg159; // includes G,W,C,F registers
reg [63:0] prev_reg160; // includes G,W,C,F registers
reg [63:0] prev_reg161; // includes G,W,C,F registers
reg [63:0] prev_reg162; // includes G,W,C,F registers
reg [63:0] prev_reg163; // includes G,W,C,F registers
reg [63:0] prev_reg164; // includes G,W,C,F registers
reg [63:0] prev_reg165; // includes G,W,C,F registers
reg [63:0] prev_reg166; // includes G,W,C,F registers
reg [63:0] prev_reg167; // includes G,W,C,F registers
reg [63:0] prev_reg168; // includes G,W,C,F registers
reg [63:0] prev_reg169; // includes G,W,C,F registers
reg [63:0] prev_reg170; // includes G,W,C,F registers
reg [63:0] prev_reg171; // includes G,W,C,F registers
reg [63:0] prev_reg172; // includes G,W,C,F registers
reg [63:0] prev_reg173; // includes G,W,C,F registers
reg [63:0] prev_reg174; // includes G,W,C,F registers
reg [63:0] prev_reg175; // includes G,W,C,F registers
reg [63:0] prev_reg176; // includes G,W,C,F registers
reg [63:0] prev_reg177; // includes G,W,C,F registers
reg [63:0] prev_reg178; // includes G,W,C,F registers
reg [63:0] prev_reg179; // includes G,W,C,F registers
reg [63:0] prev_reg180; // includes G,W,C,F registers
reg [63:0] prev_reg181; // includes G,W,C,F registers
reg [63:0] prev_reg182; // includes G,W,C,F registers
reg [63:0] prev_reg183; // includes G,W,C,F registers
reg [63:0] prev_reg184; // includes G,W,C,F registers
reg [63:0] prev_reg185; // includes G,W,C,F registers
reg [63:0] prev_reg186; // includes G,W,C,F registers
reg [63:0] prev_reg187; // includes G,W,C,F registers
reg [63:0] prev_reg188; // includes G,W,C,F registers
reg [63:0] prev_reg189; // includes G,W,C,F registers
reg [63:0] prev_reg190; // includes G,W,C,F registers
reg [63:0] prev_reg191; // includes G,W,C,F registers
reg [63:0] prev_reg192; // includes G,W,C,F registers
reg [63:0] prev_reg193; // includes G,W,C,F registers
reg [63:0] prev_reg194; // includes G,W,C,F registers
reg [63:0] prev_reg195; // includes G,W,C,F registers
reg [63:0] prev_reg196; // includes G,W,C,F registers
reg [63:0] prev_reg197; // includes G,W,C,F registers
reg [63:0] prev_reg198; // includes G,W,C,F registers
reg [63:0] prev_reg199; // includes G,W,C,F registers
reg [63:0] prev_reg200; // includes G,W,C,F registers
reg [63:0] prev_reg201; // includes G,W,C,F registers
reg [63:0] prev_reg202; // includes G,W,C,F registers
reg [63:0] prev_reg203; // includes G,W,C,F registers
reg [63:0] prev_reg204; // includes G,W,C,F registers
reg [63:0] prev_reg205; // includes G,W,C,F registers
reg [63:0] prev_reg206; // includes G,W,C,F registers
reg [63:0] prev_reg207; // includes G,W,C,F registers
reg [63:0] prev_reg208; // includes G,W,C,F registers
reg [63:0] prev_reg209; // includes G,W,C,F registers
reg [63:0] prev_reg210; // includes G,W,C,F registers
reg [63:0] prev_reg211; // includes G,W,C,F registers
reg [63:0] prev_reg212; // includes G,W,C,F registers
reg [63:0] prev_reg213; // includes G,W,C,F registers
reg [63:0] prev_reg214; // includes G,W,C,F registers
reg [63:0] prev_reg215; // includes G,W,C,F registers
reg [63:0] prev_reg216; // includes G,W,C,F registers
reg [63:0] prev_reg217; // includes G,W,C,F registers
reg [63:0] prev_reg218; // includes G,W,C,F registers
reg [63:0] prev_reg219; // includes G,W,C,F registers
reg [63:0] prev_reg220; // includes G,W,C,F registers
reg [63:0] prev_reg221; // includes G,W,C,F registers
reg [63:0] prev_reg222; // includes G,W,C,F registers
reg [63:0] prev_reg223; // includes G,W,C,F registers
reg [63:0] prev_reg224; // includes G,W,C,F registers
reg [63:0] prev_reg225; // includes G,W,C,F registers
reg [63:0] prev_reg226; // includes G,W,C,F registers
reg [63:0] prev_reg227; // includes G,W,C,F registers
reg [63:0] prev_reg228; // includes G,W,C,F registers
reg [63:0] prev_reg229; // includes G,W,C,F registers
reg [63:0] prev_reg230; // includes G,W,C,F registers
reg [63:0] prev_reg231; // includes G,W,C,F registers
reg [63:0] prev_reg232; // includes G,W,C,F registers
reg [63:0] prev_reg233; // includes G,W,C,F registers
reg [63:0] prev_reg234; // includes G,W,C,F registers
reg [63:0] prev_reg235; // includes G,W,C,F registers
reg [63:0] prev_reg236; // includes G,W,C,F registers
reg [63:0] prev_reg237; // includes G,W,C,F registers
reg [63:0] prev_reg238; // includes G,W,C,F registers
reg [63:0] prev_reg239; // includes G,W,C,F registers
reg [63:0] prev_reg240; // includes G,W,C,F registers
reg [63:0] prev_reg241; // includes G,W,C,F registers
reg [63:0] prev_reg242; // includes G,W,C,F registers
reg [63:0] prev_reg243; // includes G,W,C,F registers
reg [63:0] prev_reg244; // includes G,W,C,F registers
reg [63:0] prev_reg245; // includes G,W,C,F registers
reg [63:0] prev_reg246; // includes G,W,C,F registers
reg [63:0] prev_reg247; // includes G,W,C,F registers
reg [63:0] prev_reg248; // includes G,W,C,F registers
reg [63:0] prev_reg249; // includes G,W,C,F registers
reg [63:0] prev_reg250; // includes G,W,C,F registers
reg [63:0] prev_reg251; // includes G,W,C,F registers
reg [63:0] prev_reg252; // includes G,W,C,F registers
reg [63:0] prev_reg253; // includes G,W,C,F registers
reg [63:0] prev_reg254; // includes G,W,C,F registers
reg [63:0] prev_reg255; // includes G,W,C,F registers
reg [1:0] th_gl; // copy of GL_reg
reg frf_w1_skip_addr4_fw1;
reg frf_w1_skip_addr4_fw2;
reg [1:0] frf_w2_valid_fw;
reg [1:0] frf_w2_valid_bn;
reg [4:0] frf_w2_addr_fw;
reg [1:0] frf_w1_valid_fw;
reg [4:0] frf_w1_addr_fw;
reg wmr; // latched to get edge
reg por_a; // latched to get edge
reg por_b; // latched to get edge
reg nas_pipe_enable; // Turns on nas_pipe capture and Riesling SSTEP
wire [4:0] frf_w1_skip_addr;
wire [4:0] frf_w2_skip_addr;
reg good_trap_detected; // Used for -nosas only.
//----------------------------------------------------------
wire [`DELTA_WIDTH:0] delta_fx4_0;
wire [`DELTA_WIDTH:0] delta_fx4_1;
wire [`DELTA_WIDTH:0] delta_fx4_2;
wire [`DELTA_WIDTH:0] delta_fx4_3;
wire [`DELTA_WIDTH:0] delta_fx4_4;
wire [`DELTA_WIDTH:0] delta_fx4_5;
wire [`DELTA_WIDTH:0] delta_fx4_6;
wire [`DELTA_WIDTH:0] delta_fx4_7;
wire [`DELTA_WIDTH:0] delta_fx5_0;
wire [`DELTA_WIDTH:0] delta_fx5_1;
wire [`DELTA_WIDTH:0] delta_fx5_2;
wire [`DELTA_WIDTH:0] delta_fx5_3;
wire [`DELTA_WIDTH:0] delta_fx5_4;
wire [`DELTA_WIDTH:0] delta_fx5_5;
wire [`DELTA_WIDTH:0] delta_fx5_6;
wire [`DELTA_WIDTH:0] delta_fx5_7;
wire [`DELTA_WIDTH:0] delta_fb_0;
wire [`DELTA_WIDTH:0] delta_fb_1;
wire [`DELTA_WIDTH:0] delta_fb_2;
wire [`DELTA_WIDTH:0] delta_fb_3;
wire [`DELTA_WIDTH:0] delta_fb_4;
wire [`DELTA_WIDTH:0] delta_fb_5;
wire [`DELTA_WIDTH:0] delta_fb_6;
wire [`DELTA_WIDTH:0] delta_fb_7;
wire [`DELTA_WIDTH:0] delta_fw_0;
wire [`DELTA_WIDTH:0] delta_fw_1;
wire [`DELTA_WIDTH:0] delta_fw_2;
wire [`DELTA_WIDTH:0] delta_fw_3;
wire [`DELTA_WIDTH:0] delta_fw_4;
wire [`DELTA_WIDTH:0] delta_fw_5;
wire [`DELTA_WIDTH:0] delta_fw_6;
wire [`DELTA_WIDTH:0] delta_fw_7;
wire [`DELTA_WIDTH:0] delta_fw1_0;
wire [`DELTA_WIDTH:0] delta_fw1_1;
wire [`DELTA_WIDTH:0] delta_fw1_2;
wire [`DELTA_WIDTH:0] delta_fw1_3;
wire [`DELTA_WIDTH:0] delta_fw1_4;
wire [`DELTA_WIDTH:0] delta_fw1_5;
wire [`DELTA_WIDTH:0] delta_fw1_6;
wire [`DELTA_WIDTH:0] delta_fw1_7;
wire [`DELTA_WIDTH:0] delta_fw2_0;
wire [`DELTA_WIDTH:0] delta_fw2_1;
wire [`DELTA_WIDTH:0] delta_fw2_2;
wire [`DELTA_WIDTH:0] delta_fw2_3;
wire [`DELTA_WIDTH:0] delta_fw2_4;
wire [`DELTA_WIDTH:0] delta_fw2_5;
wire [`DELTA_WIDTH:0] delta_fw2_6;
wire [`DELTA_WIDTH:0] delta_fw2_7;
wire [`DELTA_WIDTH:0] delta_prev_0;
wire [`DELTA_WIDTH:0] delta_prev_1;
wire [`DELTA_WIDTH:0] delta_prev_2;
wire [`DELTA_WIDTH:0] delta_prev_3;
wire [`DELTA_WIDTH:0] delta_prev_4;
wire [`DELTA_WIDTH:0] delta_prev_5;
wire [`DELTA_WIDTH:0] delta_prev_6;
wire [`DELTA_WIDTH:0] delta_prev_7;
`PR_ALWAYS ("arg", `ALWAYS,"T%0d DEBUG_PIPE turned ON",mytnum);
//----------------------------------------------------------
// Note: no remap of %g,%o,%l,%i regs based on CWP or GL
assign g0 = (mytid<=3) ? `IRF0_EXU0[( 0+irf_offset)] : `IRF0_EXU1[( 0+irf_offset)];
assign g1 = (mytid<=3) ? `IRF0_EXU0[( 1+irf_offset)] : `IRF0_EXU1[( 1+irf_offset)];
assign g2 = (mytid<=3) ? `IRF0_EXU0[( 2+irf_offset)] : `IRF0_EXU1[( 2+irf_offset)];
assign g3 = (mytid<=3) ? `IRF0_EXU0[( 3+irf_offset)] : `IRF0_EXU1[( 3+irf_offset)];
assign g4 = (mytid<=3) ? `IRF0_EXU0[( 4+irf_offset)] : `IRF0_EXU1[( 4+irf_offset)];
assign g5 = (mytid<=3) ? `IRF0_EXU0[( 5+irf_offset)] : `IRF0_EXU1[( 5+irf_offset)];
assign g6 = (mytid<=3) ? `IRF0_EXU0[( 6+irf_offset)] : `IRF0_EXU1[( 6+irf_offset)];
assign g7 = (mytid<=3) ? `IRF0_EXU0[( 7+irf_offset)] : `IRF0_EXU1[( 7+irf_offset)];
assign o0 = (mytid<=3) ? `IRF0_EXU0[( 8+irf_offset)] : `IRF0_EXU1[( 8+irf_offset)];
assign o1 = (mytid<=3) ? `IRF0_EXU0[( 9+irf_offset)] : `IRF0_EXU1[( 9+irf_offset)];
assign o2 = (mytid<=3) ? `IRF0_EXU0[(10+irf_offset)] : `IRF0_EXU1[(10+irf_offset)];
assign o3 = (mytid<=3) ? `IRF0_EXU0[(11+irf_offset)] : `IRF0_EXU1[(11+irf_offset)];
assign o4 = (mytid<=3) ? `IRF0_EXU0[(12+irf_offset)] : `IRF0_EXU1[(12+irf_offset)];
assign o5 = (mytid<=3) ? `IRF0_EXU0[(13+irf_offset)] : `IRF0_EXU1[(13+irf_offset)];
assign o6 = (mytid<=3) ? `IRF0_EXU0[(14+irf_offset)] : `IRF0_EXU1[(14+irf_offset)];
assign o7 = (mytid<=3) ? `IRF0_EXU0[(15+irf_offset)] : `IRF0_EXU1[(15+irf_offset)];
assign l0 = (mytid<=3) ? `IRF0_EXU0[(16+irf_offset)] : `IRF0_EXU1[(16+irf_offset)];
assign l1 = (mytid<=3) ? `IRF0_EXU0[(17+irf_offset)] : `IRF0_EXU1[(17+irf_offset)];
assign l2 = (mytid<=3) ? `IRF0_EXU0[(18+irf_offset)] : `IRF0_EXU1[(18+irf_offset)];
assign l3 = (mytid<=3) ? `IRF0_EXU0[(19+irf_offset)] : `IRF0_EXU1[(19+irf_offset)];
assign l4 = (mytid<=3) ? `IRF0_EXU0[(20+irf_offset)] : `IRF0_EXU1[(20+irf_offset)];
assign l5 = (mytid<=3) ? `IRF0_EXU0[(21+irf_offset)] : `IRF0_EXU1[(21+irf_offset)];
assign l6 = (mytid<=3) ? `IRF0_EXU0[(22+irf_offset)] : `IRF0_EXU1[(22+irf_offset)];
assign l7 = (mytid<=3) ? `IRF0_EXU0[(23+irf_offset)] : `IRF0_EXU1[(23+irf_offset)];
assign i0 = (mytid<=3) ? `IRF0_EXU0[(24+irf_offset)] : `IRF0_EXU1[(24+irf_offset)];
assign i1 = (mytid<=3) ? `IRF0_EXU0[(25+irf_offset)] : `IRF0_EXU1[(25+irf_offset)];
assign i2 = (mytid<=3) ? `IRF0_EXU0[(26+irf_offset)] : `IRF0_EXU1[(26+irf_offset)];
assign i3 = (mytid<=3) ? `IRF0_EXU0[(27+irf_offset)] : `IRF0_EXU1[(27+irf_offset)];
assign i4 = (mytid<=3) ? `IRF0_EXU0[(28+irf_offset)] : `IRF0_EXU1[(28+irf_offset)];
assign i5 = (mytid<=3) ? `IRF0_EXU0[(29+irf_offset)] : `IRF0_EXU1[(29+irf_offset)];
assign i6 = (mytid<=3) ? `IRF0_EXU0[(30+irf_offset)] : `IRF0_EXU1[(30+irf_offset)];
assign i7 = (mytid<=3) ? `IRF0_EXU0[(31+irf_offset)] : `IRF0_EXU1[(31+irf_offset)];
//----------------------------------------------------------
assign frf_0 = `FRF0_EVEN[(mytid*32)+ 0];
assign frf_2 = `FRF0_EVEN[(mytid*32)+ 1];
assign frf_4 = `FRF0_EVEN[(mytid*32)+ 2];
assign frf_6 = `FRF0_EVEN[(mytid*32)+ 3];
assign frf_8 = `FRF0_EVEN[(mytid*32)+ 4];
assign frf_10 = `FRF0_EVEN[(mytid*32)+ 5];
assign frf_12 = `FRF0_EVEN[(mytid*32)+ 6];
assign frf_14 = `FRF0_EVEN[(mytid*32)+ 7];
assign frf_16 = `FRF0_EVEN[(mytid*32)+ 8];
assign frf_18 = `FRF0_EVEN[(mytid*32)+ 9];
assign frf_20 = `FRF0_EVEN[(mytid*32)+ 10];
assign frf_22 = `FRF0_EVEN[(mytid*32)+ 11];
assign frf_24 = `FRF0_EVEN[(mytid*32)+ 12];
assign frf_26 = `FRF0_EVEN[(mytid*32)+ 13];
assign frf_28 = `FRF0_EVEN[(mytid*32)+ 14];
assign frf_30 = `FRF0_EVEN[(mytid*32)+ 15];
assign frf_32 = `FRF0_EVEN[(mytid*32)+ 16];
assign frf_34 = `FRF0_EVEN[(mytid*32)+ 17];
assign frf_36 = `FRF0_EVEN[(mytid*32)+ 18];
assign frf_38 = `FRF0_EVEN[(mytid*32)+ 19];
assign frf_40 = `FRF0_EVEN[(mytid*32)+ 20];
assign frf_42 = `FRF0_EVEN[(mytid*32)+ 21];
assign frf_44 = `FRF0_EVEN[(mytid*32)+ 22];
assign frf_46 = `FRF0_EVEN[(mytid*32)+ 23];
assign frf_48 = `FRF0_EVEN[(mytid*32)+ 24];
assign frf_50 = `FRF0_EVEN[(mytid*32)+ 25];
assign frf_52 = `FRF0_EVEN[(mytid*32)+ 26];
assign frf_54 = `FRF0_EVEN[(mytid*32)+ 27];
assign frf_56 = `FRF0_EVEN[(mytid*32)+ 28];
assign frf_58 = `FRF0_EVEN[(mytid*32)+ 29];
assign frf_60 = `FRF0_EVEN[(mytid*32)+ 30];
assign frf_62 = `FRF0_EVEN[(mytid*32)+ 31];
assign frf_1 = `FRF0_ODD[(mytid*32)+ 0];
assign frf_3 = `FRF0_ODD[(mytid*32)+ 1];
assign frf_5 = `FRF0_ODD[(mytid*32)+ 2];
assign frf_7 = `FRF0_ODD[(mytid*32)+ 3];
assign frf_9 = `FRF0_ODD[(mytid*32)+ 4];
assign frf_11 = `FRF0_ODD[(mytid*32)+ 5];
assign frf_13 = `FRF0_ODD[(mytid*32)+ 6];
assign frf_15 = `FRF0_ODD[(mytid*32)+ 7];
assign frf_17 = `FRF0_ODD[(mytid*32)+ 8];
assign frf_19 = `FRF0_ODD[(mytid*32)+ 9];
assign frf_21 = `FRF0_ODD[(mytid*32)+ 10];
assign frf_23 = `FRF0_ODD[(mytid*32)+ 11];
assign frf_25 = `FRF0_ODD[(mytid*32)+ 12];
assign frf_27 = `FRF0_ODD[(mytid*32)+ 13];
assign frf_29 = `FRF0_ODD[(mytid*32)+ 14];
assign frf_31 = `FRF0_ODD[(mytid*32)+ 15];
assign frf_33 = `FRF0_ODD[(mytid*32)+ 16];
assign frf_35 = `FRF0_ODD[(mytid*32)+ 17];
assign frf_37 = `FRF0_ODD[(mytid*32)+ 18];
assign frf_39 = `FRF0_ODD[(mytid*32)+ 19];
assign frf_41 = `FRF0_ODD[(mytid*32)+ 20];
assign frf_43 = `FRF0_ODD[(mytid*32)+ 21];
assign frf_45 = `FRF0_ODD[(mytid*32)+ 22];
assign frf_47 = `FRF0_ODD[(mytid*32)+ 23];
assign frf_49 = `FRF0_ODD[(mytid*32)+ 24];
assign frf_51 = `FRF0_ODD[(mytid*32)+ 25];
assign frf_53 = `FRF0_ODD[(mytid*32)+ 26];
assign frf_55 = `FRF0_ODD[(mytid*32)+ 27];
assign frf_57 = `FRF0_ODD[(mytid*32)+ 28];
assign frf_59 = `FRF0_ODD[(mytid*32)+ 29];
assign frf_61 = `FRF0_ODD[(mytid*32)+ 30];
assign frf_63 = `FRF0_ODD[(mytid*32)+ 31];
//----------------------------------------------------------
assign delta_fx4_0 = delta_fx4[0];
assign delta_fx4_1 = delta_fx4[1];
assign delta_fx4_2 = delta_fx4[2];
assign delta_fx4_3 = delta_fx4[3];
assign delta_fx4_4 = delta_fx4[4];
assign delta_fx4_5 = delta_fx4[5];
assign delta_fx4_6 = delta_fx4[6];
assign delta_fx4_7 = delta_fx4[7];
assign delta_fx5_0 = delta_fx5[0];
assign delta_fx5_1 = delta_fx5[1];
assign delta_fx5_2 = delta_fx5[2];
assign delta_fx5_3 = delta_fx5[3];
assign delta_fx5_4 = delta_fx5[4];
assign delta_fx5_5 = delta_fx5[5];
assign delta_fx5_6 = delta_fx5[6];
assign delta_fx5_7 = delta_fx5[7];
assign delta_fb_0 = delta_fb[0];
assign delta_fb_1 = delta_fb[1];
assign delta_fb_2 = delta_fb[2];
assign delta_fb_3 = delta_fb[3];
assign delta_fb_4 = delta_fb[4];
assign delta_fb_5 = delta_fb[5];
assign delta_fb_6 = delta_fb[6];
assign delta_fb_7 = delta_fb[7];
assign delta_fw_0 = delta_fw[0];
assign delta_fw_1 = delta_fw[1];
assign delta_fw_2 = delta_fw[2];
assign delta_fw_3 = delta_fw[3];
assign delta_fw_4 = delta_fw[4];
assign delta_fw_5 = delta_fw[5];
assign delta_fw_6 = delta_fw[6];
assign delta_fw_7 = delta_fw[7];
assign delta_fw1_0 = delta_fw1[0];
assign delta_fw1_1 = delta_fw1[1];
assign delta_fw1_2 = delta_fw1[2];
assign delta_fw1_3 = delta_fw1[3];
assign delta_fw1_4 = delta_fw1[4];
assign delta_fw1_5 = delta_fw1[5];
assign delta_fw1_6 = delta_fw1[6];
assign delta_fw1_7 = delta_fw1[7];
assign delta_fw2_0 = delta_fw2[0];
assign delta_fw2_1 = delta_fw2[1];
assign delta_fw2_2 = delta_fw2[2];
assign delta_fw2_3 = delta_fw2[3];
assign delta_fw2_4 = delta_fw2[4];
assign delta_fw2_5 = delta_fw2[5];
assign delta_fw2_6 = delta_fw2[6];
assign delta_fw2_7 = delta_fw2[7];
assign delta_prev_0 = delta_prev[0];
assign delta_prev_1 = delta_prev[1];
assign delta_prev_2 = delta_prev[2];
assign delta_prev_3 = delta_prev[3];
assign delta_prev_4 = delta_prev[4];
assign delta_prev_5 = delta_prev[5];
assign delta_prev_6 = delta_prev[6];
assign delta_prev_7 = delta_prev[7];
//----------------------------------------------------------
//----------------------------------------------------------
assign mytnum = (mycid*8)+mytid;
assign mytg = mytid >> 2;
assign exu_complete = exu_valid & ~(`PROBES0.clkstop_d5|`TOP.in_reset|`SPC0.tcu_scan_en);
assign imul_complete = imul_valid & ~(`TOP.in_reset|`SPC0.tcu_scan_en);
assign idiv_complete = idiv_valid & ~(`TOP.in_reset|`SPC0.tcu_scan_en);
assign tlu_complete = tlu_complete_3 ;
assign fp_complete = fp_valid & ~(`TOP.in_reset|`SPC0.tcu_scan_en);
assign fdiv_complete = fdiv_valid & ~(`TOP.in_reset|`SPC0.tcu_scan_en);
assign lsu_complete = lsu_valid & ~(`TOP.in_reset|`SPC0.tcu_scan_en);
assign asi_complete = asi_valid & ~(`TOP.in_reset|`SPC0.tcu_scan_en);
assign complete_w = (exu_complete << `EXU_INDEX) |
(lsu_complete << `LSU_INDEX) |
(tlu_complete << `TLU_INDEX) |
(asi_complete << `ASI_INDEX) ;
assign oddwin = CWP_reg % 2;
assign frf_w1_valid_even = (frf_w1_tid_fw == mytid) & frf_w1_valid_fw[1];
assign frf_w1_valid_odd = (frf_w1_tid_fw == mytid) & frf_w1_valid_fw[0];
assign frf_w2_valid_even = (frf_w2_tid_fw == mytid) & frf_w2_valid_fw[1];
assign frf_w2_valid_odd = (frf_w2_tid_fw == mytid) & frf_w2_valid_fw[0];
assign frf_w1_skip_addr = frf_w1_addr_fw;
assign frf_w2_skip_addr = frf_w2_addr_fw;
// NOTE - ADD_TSB_CFG will never be used for Axis or Tharas
wire [63:0] ctxt_z_tsb_cfg0_reg = `PROBES0.ctxt_z_tsb_cfg0_reg[mytid];
wire [63:0] ctxt_z_tsb_cfg1_reg = `PROBES0.ctxt_z_tsb_cfg1_reg[mytid];
wire [63:0] ctxt_z_tsb_cfg2_reg = `PROBES0.ctxt_z_tsb_cfg2_reg[mytid];
wire [63:0] ctxt_z_tsb_cfg3_reg = `PROBES0.ctxt_z_tsb_cfg3_reg[mytid];
wire [63:0] ctxt_nz_tsb_cfg0_reg = `PROBES0.ctxt_nz_tsb_cfg0_reg[mytid];
wire [63:0] ctxt_nz_tsb_cfg1_reg = `PROBES0.ctxt_nz_tsb_cfg1_reg[mytid];
wire [63:0] ctxt_nz_tsb_cfg2_reg = `PROBES0.ctxt_nz_tsb_cfg2_reg[mytid];
wire [63:0] ctxt_nz_tsb_cfg3_reg = `PROBES0.ctxt_nz_tsb_cfg3_reg[mytid];
//----------------------------------------------------------
always @ (posedge `BENCH_SPC0_GCLK) begin // {
// TLU is async to the execution pipeline
// but needs to be delayed to allow CWP, etc to update and be stable
// before arch state is captured and diff_reg is called.
// FDIV was moved from fw1 to fw to allow FPRS to be stable before capture
tlu_complete_1 <= tlu_valid & ~(`TOP.in_reset|`SPC0.tcu_scan_en);
tlu_complete_2 <= tlu_complete_1;
tlu_complete_3 <= tlu_complete_2;
itagacc_fx5 <= I_TAG_ACC_reg; // Signal changes in W so need to pipeline to fw2
itagacc_fb <= itagacc_fx5;
itagacc_fw <= itagacc_fb;
itagacc_fw1 <= itagacc_fw;
itagacc_fw2 <= itagacc_fw1;
dtagacc_fx5 <= D_TAG_ACC_reg; // Signal changes in W so need to pipeline to fw2
dtagacc_fb <= dtagacc_fx5;
dtagacc_fw <= dtagacc_fb;
dtagacc_fw1 <= dtagacc_fw;
dtagacc_fw2 <= dtagacc_fw1;
dsfar_fb <= DSFAR_reg; // Signal changes in W+1 so need to pipeline to fw2
complete_fx4 <= complete_w;
complete_fx5 <= complete_fx4 ;
complete_fb <= complete_fx5 |
(idiv_complete << `IDIV_INDEX);
complete_fw <= complete_fb |
(fdiv_complete << `FDIV_INDEX) |
(imul_complete << `IMUL_INDEX);
complete_fw1 <= complete_fw |
(fp_complete << `FP_INDEX);
complete_fw2 <= complete_fw1;
frf_w1_valid_fw1 <= (frf_w1_valid_odd | frf_w1_valid_even) & fp_complete;
frf_w1_valid_fw2 <= frf_w1_valid_fw1;
frf_w1_skip_addr4_fw1 <= frf_w1_skip_addr[4];
frf_w1_skip_addr4_fw2 <= frf_w1_skip_addr4_fw1;
frf_w2_valid_fw <= frf_w2_valid_bn;
frf_w2_tid_fw <= frf_w2_tid;
frf_w2_addr_fw <= frf_w2_addr;
frf_w1_valid_fw <= frf_w1_valid;
frf_w1_tid_fw <= frf_w1_tid;
frf_w1_addr_fw <= frf_w1_addr;
if (~thread_running & `SPC0.tcu_core_running[mytid])
`TOP.th_last_act_cycle[mytnum] = `TOP.core_cycle_cnt;
thread_running <= `SPC0.tcu_core_running[mytid];
// Reset some register prev state on wmr negation
if (`SPC0.rst_wmr_protect && ~wmr)
wmr <= `SPC0.rst_wmr_protect;
if (`SPC0.rst_wmr_protect)
//----------------------------------------------------------
// Holding state for registers that may be updated asynchronously
// after synchronous update, but before capture/step. Also for reads,
// when register is read and modified before capture/step ..
// We capture the value /write time, and use that for sstep,
// ignoring any async updates, which are sent in the NEXT sstep ..
reg [63:0] asi_updated_int_rec;
reg asi_wr_int_rec_delay;
reg [16:0] asi_updated_softint;
reg asi_wr_softint_delay;
reg [16:0] asi_softint_wrdata;
always @(posedge `BENCH_SPC0_GCLK) begin // {
// Corner case : If async and sync wr occur in same clock, then the async
// update takes place. In this case we have to capture the
// value of the write WITHOUT async bit being set, so that
// we can sync with Riesling's sync write ..
asi_wr_int_rec_delay <= ( `SPC0.tlu.cth.asi_wr_int_rec[mytid] |
`SPC0.tlu.asi_rd_inc_vec_2[mytid]);
if (`SPC0.tlu.cth.asi_wr_int_rec[mytid] |
((`SPC0.tlu.asi.rd_inc_vec) &&
(`SPC0.tlu.asi.rd_tid_dec[mytid])) |
(`SPC0.tlu.asi_rd_int_rec &
`SPC0.tlu.cth.int_rec_mux_sel==mytid))
if (`SPC0.tlu.cth.asi_wr_int_rec[mytid])
asi_updated_int_rec <= `SPC0.tlu.cth.int_rec ;
else if ( (`SPC0.tlu.asi.rd_inc_vec) &&
(`SPC0.tlu.asi.rd_tid_dec[mytid]) )
if (`SPC0.tlu.cth.cxi_wr_int_dis[mytid]) begin
asi_updated_int_rec <= INTR_RECEIVE_reg & `SPC0.tlu.cth.int_rec_muxed_;
asi_updated_int_rec[`SPC0.tlu.cth.incoming_vector_in] <= 1'b0 ;
asi_updated_int_rec <= `SPC0.tlu.cth.int_rec_muxed ;
asi_updated_int_rec[`SPC0.tlu.cth.incoming_vector_in] <= 1'b0 ;
asi_updated_int_rec <= INTR_RECEIVE_reg;
asi_rdwr_int_rec <= 1'b1;
else if (complete_fw1 && !`NASTOP.sstep_early[mytnum])
asi_rdwr_int_rec <= 1'b0;
asi_wr_hintp_delay <= `SPC0.tlu.asi_wr_hintp[mytid];
if (`SPC0.tlu.asi_wr_hintp[mytid] |
`SPC0.tlu.asi_rd_hintp[mytid])
if (`SPC0.tlu.asi_wr_hintp[mytid])
asi_updated_hintp <= `SPC0.tlu.asi_wr_data_0[0] ;
asi_updated_hintp <= HINTP_reg;
else if (complete_fw1 && !`NASTOP.sstep_early[mytnum])
asi_wr_softint_delay <= (`SPC0.tlu.asi_wr_softint[mytid] |
`SPC0.tlu.asi_wr_clear_softint[mytid] |
`SPC0.tlu.asi_wr_set_softint[mytid]);
if (`SPC0.tlu.asi_wr_clear_softint[mytid])
asi_softint_wrdata <= ~`SPC0.tlu.asi_wr_data_0[16:0] & rd_SOFTINT_reg;
else if (`SPC0.tlu.asi_wr_set_softint[mytid])
asi_softint_wrdata <= `SPC0.tlu.asi_wr_data_0[16:0] | rd_SOFTINT_reg;
asi_softint_wrdata <= `SPC0.tlu.asi_wr_data_0[16:0];
if (asi_wr_softint_delay | `SPC0.tlu.asi_rd_softint[mytid])
if (asi_wr_softint_delay)
asi_updated_softint <= asi_softint_wrdata ;
asi_updated_softint <= rd_SOFTINT_reg ;
asi_rdwr_softint <= 1'b1;
else if (complete_fw1 && !`NASTOP.sstep_early[mytnum])
asi_rdwr_softint <= 1'b0;
//----------------------------------------------------------
// Negedge sampling to avoid race on specific signals ..
always @ (negedge `BENCH_SPC0_GCLK) begin // {
frf_w2_valid_bn <= frf_w2_valid;
//----------------------------------------------------------
// When instruction completes,
// Push differences to simics
always @ (posedge `BENCH_SPC0_GCLK) begin // {
if (`PARGS.th_check_enable[mytnum] && nas_pipe_enable && ~`SPC0.tcu_scan_en && ~`TOP.in_por) begin // {
// Update window registers
if (CWP_reg != `NASTOP.th_cwp[mytnum]) begin // {
copy_win (CWP_reg,`NASTOP.th_cwp[mytnum]);
`NASTOP.th_cwp[mytnum] = CWP_reg;
// Update global registers
// Wait for warm-reset flush related toggling to settle
if (GL_reg != th_gl) begin // {
if (`SPC0.spc_core_running_status[mytid] &
~`SPC0.rst_wmr_protect) begin // {
copy_global (GL_reg,th_gl);
// Check for bad signal values
// if NASTOP.sstep_sent[tid]=1,
// then SSTEP was set by another module (i.e. tlb_sync)
if (`PARGS.nas_check_on) begin // {
mytime = `TOP.core_cycle_cnt-1;
if (complete_fw2 && (`NASTOP.sstep_sent[mytnum]==1'b0)) begin // {
`PR_INFO ("pli_nas", `INFO, " C%0d T%0d PLI_SSTEP tid=%d pc=%h ts=%0d ",
mycid,mytid,mytnum,pc_fw2,mytime);
junk = $sim_send(`PLI_SSTEP, mytnum);
// Always clear sstep_early
// In case tlb_sync asserted it too late for complete_fw2
`NASTOP.sstep_early[mytnum] <= 1'b0;
else if (complete_fw2) begin // {
`NASTOP.sstep_sent[mytnum] <= 1'b0; // re-arm SSTEP
`NASTOP.sstep_early[mytnum] <= 1'b0;
`PR_INFO ("pli_nas", `INFO, " C%0d T%0d PLI_SSTEP tid=%d pc=%h ts=%0d (nas_pipe: skip sstep. rearm sstep. sstep_sent=0)",
mycid,mytid,mytnum,pc_fw2,mytime);
// Only capture if something completes and not first instruction
if (complete_fw2 && !first_op) begin // {
push_simics; // Use with AXIS to keep from getting timeout
// Pipeline runs continuously
// Other than when in POR ..
// Only save to delta_prev when something completes
`TOP.last_act_cycle = `TOP.core_cycle_cnt; //$time;
`TOP.th_last_act_cycle[mytnum] = `TOP.last_act_cycle;
// If something was captured but no instruction is in the pipeline
if ((delta_fw2[`NEXT_INDEX]!=`FIRST_INDEX) && (complete_fw2 == 0))
for (myindex=`FIRST_INDEX; myindex<delta_fw2[`NEXT_INDEX]; myindex=myindex+1)
print_entry (delta_fw2[myindex]);
`PR_ERROR ("nas",`ERROR, "T%0d Unexpected Reg change in DUT. Special case - no instruction retired.", mytnum);
// End detection for non-sas runs ..
for (junk=0;junk<`PARGS.bad_trap_count;junk=junk+1)
if (({16'b0,pc_fw2}&`PC_MASK) ===
(`PARGS.bad_trap_addr[junk]&`PC_MASK)) begin // {
// Disable nas_pipe processing (capture & SSTEP)
// to speed up simulation (minimize socket traffic,etc)
if (! `PARGS.nas_check_on) begin //{
`PR_ERROR ("nas",`ERROR, "T%0d reached Bad Trap", mytnum);
for (junk=0;junk<`PARGS.good_trap_count;junk=junk+1)
if ((|complete_fw2) && (({16'b0,pc_fw2}&`PC_MASK) ===
(`PARGS.good_trap_addr[junk]&`PC_MASK))) begin // {
// Disable nas_pipe processing (capture & SSTEP)
// to speed up simulation (minimize socket traffic,etc)
if (! `PARGS.nas_check_on) begin //{
good_trap_detected = 1'b1;
// Check Thread level timeout
(`TOP.core_cycle_cnt - `TOP.th_last_act_cycle[mytnum]) > `PARGS.th_timeout)
// Note: Do not change this message because regreport parses it for certain words.
`PR_ALWAYS ("nas",`ALWAYS, "ERROR: Thread T%0d No Activity for %0d Cycles - Thread TIMEOUT!",
mytnum, `PARGS.th_timeout);
junk = incErr(9999); // must exceed users max error setting to force exit.
end // if (`PARGS.th_check_enable[mytnum] && nas_pipe_enable ...)}
// Need to make sure Store Buffer is empty before turning off th_check_enable.
//global chkr requires to wait for all outstanding pending I
if ((! `PARGS.nas_check_on) &&
(good_trap_detected==1'b1) &&
(`TOP.nas_top.lsu_stb_empty[mytnum]) && `TOP.nas_top.ireq_pending[mytnum]) begin // {
`PARGS.th_check_enable[mytnum] = 1'b0;
`TOP.finished_tids[mytnum] = 1'b1;
good_trap_detected = 1'b0;
`PR_NORMAL ("nas", `NORMAL, "T%0d reached Good Trap. Disabling checking for thread %0d", mytnum,mytnum);
//----------------------------------------------------------
//----------------------------------------------------------
// Stage FX4 of delta pipeline
delta_fx4[`NEXT_INDEX] <= `FIRST_INDEX;
delta_fx4[`TIME_INDEX] <= 0;
delta_fx4[`PC_INDEX] <= {16'b0,PC_reg};
delta_fx4[`GL_INDEX] <= GL_reg;
delta_fx4[`CWP_INDEX] <= CWP_reg;
delta_fx4[`OPCODE_INDEX] <= opcode;
delta_fx4[`FIRST_INDEX] <= 77'hx;
//----------------------------------------------------------
// Stage FX5 of delta pipeline
index = delta_fx4[`NEXT_INDEX];
// Pipeline previous stage
for (i=0; i<=delta_fx4[`NEXT_INDEX]; i=i+1) begin // {
delta_fx5[i] <= delta_fx4[i];
if (complete_fx4) begin // LSU | EXU | TLU
push_delta_fx5 (`CCR+`CTL_OFFSET,CCR_reg,index);
if (complete_fx4[`LSU_INDEX] |
complete_fx4[`EXU_INDEX]) begin
if (mytid <= 3) begin // {
for (i=0; i<=31; i=i+1) begin // {
push_delta_fx5 (i,`IRF0_EXU0[(remap(i,oddwin)+irf_offset)],index);
for (i=0; i<=31; i=i+1) begin // {
push_delta_fx5 (i,`IRF0_EXU1[(remap(i,oddwin)+irf_offset)],index);
// Update FRF0 - Loads use W2 Port.
if (complete_fx4[`LSU_INDEX]) begin // {
// IF W1 port is also being written, ignore that address
for (i=0; i<=31; i=i+1) begin // {
if (!((i == frf_w1_skip_addr) && frf_w1_valid_even)) begin // {
frf_tmp = `FRF0_EVEN[(mytid*32)+i];
push_delta_fx5 (`FP_OFFSET + (i*2), frf_tmp[31:0], index);
if (!((i == frf_w1_skip_addr) && frf_w1_valid_odd)) begin // {
frf_tmp = `FRF0_ODD[(mytid*32)+i];
push_delta_fx5 (`FP_OFFSET + (i*2)+1, frf_tmp[31:0], index);
// Update ASR/ASI registers
if (complete_fx4) begin // {
push_delta_fx5 (`PSTATE + `CTL_OFFSET,PSTATE_reg,index);
push_delta_fx5 (`HPSTATE + `CTL_OFFSET,HPSTATE_reg,index);
push_delta_fx5 (`PIL + `CTL_OFFSET,PIL_reg,index);
push_delta_fx5 (`TBA + `CTL_OFFSET,{TBA_reg,15'b0},index);
push_delta_fx5 (`GL + `CTL_OFFSET,GL_reg,index);
push_delta_fx5 (`HTBA + `CTL_OFFSET,{HTBA_reg,14'b0},index);
push_delta_fx5 (`VER + `CTL_OFFSET,VER_reg,index);
push_delta_fx5 (`Y + `CTL_OFFSET,Y_reg,index);
push_delta_fx5 (`ASI + `CTL_OFFSET,ASI_reg,index);
push_delta_fx5 (`STICK_CMPR + `CTL_OFFSET,STICK_CMPR_wire,index);
push_delta_fx5 (`HSTICK_CMPR + `CTL_OFFSET,HSTICK_CMPR_wire,index);
push_delta_fx5 (`TICK_CMPR + `CTL_OFFSET,TICK_CMPR_wire,index);
push_delta_fx5 (`CWP + `CTL_OFFSET,CWP_reg,index);
push_delta_fx5 (`CANSAVE + `CTL_OFFSET,CANSAVE_reg,index);
push_delta_fx5 (`CANRESTORE + `CTL_OFFSET,CANRESTORE_reg,index);
push_delta_fx5 (`CLEANWIN + `CTL_OFFSET,CLEANWIN_reg,index);
push_delta_fx5 (`OTHERWIN + `CTL_OFFSET,OTHERWIN_reg,index);
push_delta_fx5 (`WSTATE + `CTL_OFFSET,WSTATE_reg,index);
push_delta_fx5 (`CTXT_PRIM_0+`CTL_OFFSET,CTXT_PRIM_0_reg,index);
push_delta_fx5 (`CTXT_SEC_0+`CTL_OFFSET,CTXT_SEC_0_reg,index);
push_delta_fx5 (`CTXT_PRIM_1+`CTL_OFFSET,CTXT_PRIM_1_reg,index);
push_delta_fx5 (`CTXT_SEC_1+`CTL_OFFSET,CTXT_SEC_1_reg,index);
push_delta_fx5 (`LSU_CONTROL+`CTL_OFFSET,LSU_CONTROL_reg,index);
push_delta_fx5 (`WATCHPOINT_ADDR+`CTL_OFFSET,WATCHPOINT_ADDR_reg,index);
// NOTE - ADD_TSB_CFG will never be used for Axis or Tharas
push_delta_fx5 (`CTXT_Z_TSB_CFG0+`CTL_OFFSET,ctxt_z_tsb_cfg0_reg,index);
push_delta_fx5 (`CTXT_Z_TSB_CFG1+`CTL_OFFSET,ctxt_z_tsb_cfg1_reg,index);
push_delta_fx5 (`CTXT_Z_TSB_CFG2+`CTL_OFFSET,ctxt_z_tsb_cfg2_reg,index);
push_delta_fx5 (`CTXT_Z_TSB_CFG3+`CTL_OFFSET,ctxt_z_tsb_cfg3_reg,index);
push_delta_fx5 (`CTXT_NZ_TSB_CFG0+`CTL_OFFSET,ctxt_nz_tsb_cfg0_reg,index);
push_delta_fx5 (`CTXT_NZ_TSB_CFG1+`CTL_OFFSET,ctxt_nz_tsb_cfg1_reg,index);
push_delta_fx5 (`CTXT_NZ_TSB_CFG2+`CTL_OFFSET,ctxt_nz_tsb_cfg2_reg,index);
push_delta_fx5 (`CTXT_NZ_TSB_CFG3+`CTL_OFFSET,ctxt_nz_tsb_cfg3_reg,index);
// Update GSR for all except write ASR in progess
if (!asi_in_progress) begin // {
push_delta_fx5 (`GSR + `CTL_OFFSET,GSR_wire, index);
// If lsu_complete & fp_complete assert at same time,
// then the fp_complete is the one that will modify the FSR
if (complete_fx4[`LSU_INDEX] & !complete_fw1[`FP_INDEX]) begin
push_delta_fx5 (`FSR+`CTL_OFFSET,FSR_wire,index);
// Non Trap updates of Trap stack & level
if (complete_fx4 && !complete_fx4[`TLU_INDEX]) begin // {
push_delta_fx5 (`TL + `CTL_OFFSET,TL_reg,index);
push_delta_fx5 (`TPC1 + `CTL_OFFSET, TPC1_wire, index);
push_delta_fx5 (`TPC2 + `CTL_OFFSET, TPC2_wire, index);
push_delta_fx5 (`TPC3 + `CTL_OFFSET, TPC3_wire, index);
push_delta_fx5 (`TPC4 + `CTL_OFFSET, TPC4_wire, index);
push_delta_fx5 (`TPC5 + `CTL_OFFSET, TPC5_wire, index);
push_delta_fx5 (`TPC6 + `CTL_OFFSET, TPC6_wire, index);
push_delta_fx5 (`TNPC1 + `CTL_OFFSET, TNPC1_wire, index);
push_delta_fx5 (`TNPC2 + `CTL_OFFSET, TNPC2_wire, index);
push_delta_fx5 (`TNPC3 + `CTL_OFFSET, TNPC3_wire, index);
push_delta_fx5 (`TNPC4 + `CTL_OFFSET, TNPC4_wire, index);
push_delta_fx5 (`TNPC5 + `CTL_OFFSET, TNPC5_wire, index);
push_delta_fx5 (`TNPC6 + `CTL_OFFSET, TNPC6_wire, index);
push_delta_fx5 (`TSTATE1 + `CTL_OFFSET, TSTATE1_wire, index);
push_delta_fx5 (`TSTATE2 + `CTL_OFFSET, TSTATE2_wire, index);
push_delta_fx5 (`TSTATE3 + `CTL_OFFSET, TSTATE3_wire, index);
push_delta_fx5 (`TSTATE4 + `CTL_OFFSET, TSTATE4_wire, index);
push_delta_fx5 (`TSTATE5 + `CTL_OFFSET, TSTATE5_wire, index);
push_delta_fx5 (`TSTATE6 + `CTL_OFFSET, TSTATE6_wire, index);
push_delta_fx5 (`HTSTATE1 + `CTL_OFFSET, HTSTATE1_wire, index);
push_delta_fx5 (`HTSTATE2 + `CTL_OFFSET, HTSTATE2_wire, index);
push_delta_fx5 (`HTSTATE3 + `CTL_OFFSET, HTSTATE3_wire, index);
push_delta_fx5 (`HTSTATE4 + `CTL_OFFSET, HTSTATE4_wire, index);
push_delta_fx5 (`HTSTATE5 + `CTL_OFFSET, HTSTATE5_wire, index);
push_delta_fx5 (`HTSTATE6 + `CTL_OFFSET, HTSTATE6_wire, index);
push_delta_fx5 (`TT1 + `CTL_OFFSET, TT1_wire, index);
push_delta_fx5 (`TT2 + `CTL_OFFSET, TT2_wire, index);
push_delta_fx5 (`TT3 + `CTL_OFFSET, TT3_wire, index);
push_delta_fx5 (`TT4 + `CTL_OFFSET, TT4_wire, index);
push_delta_fx5 (`TT5 + `CTL_OFFSET, TT5_wire, index);
push_delta_fx5 (`TT6 + `CTL_OFFSET, TT6_wire, index);
//----------------------------------------------------------
// Stage FB of delta pipeline
index = delta_fx5[`NEXT_INDEX];
// Pipeline previous stage
for (i=0; i<=delta_fx5[`NEXT_INDEX]; i=i+1) begin // {
delta_fb[i] <= delta_fx5[i];
if (complete_fx5[`ASI_INDEX]) begin // {
push_delta_fb (`GSR + `CTL_OFFSET,GSR_wire, index);
//----------------------------------------------------------
// Stage FW of delta pipeline
index = delta_fb[`NEXT_INDEX];
// Pipeline previous stage
for (i=0; i<=delta_fb[`NEXT_INDEX]; i=i+1) begin // {
delta_fw[i] <= delta_fb[i];
// Capture CWP_reg for SAVE/RESTORE
delta_fw[`CWP_INDEX] <= CWP_reg;
if (complete_fb[`TLU_INDEX]) begin
if (mytid <= 3) begin // {
for (i=0; i<=31; i=i+1) begin // {
push_delta_fw (i,`IRF0_EXU0[(remap(i,oddwin)+irf_offset)],index);
for (i=0; i<=31; i=i+1) begin // {
push_delta_fw (i,`IRF0_EXU1[(remap(i,oddwin)+irf_offset)],index);
// Update FRF0 - Idivs use W2.
if (complete_fb[`IDIV_INDEX]) begin // {
// IF W1 port is also being written, ignore that address
for (i=0; i<=31; i=i+1) begin // {
if (!((i == frf_w1_skip_addr) && frf_w1_valid_even)) begin // {
frf_tmp = `FRF0_EVEN[(mytid*32)+i];
push_delta_fw (`FP_OFFSET + (i*2), frf_tmp[31:0], index);
if (!((i == frf_w1_skip_addr) && frf_w1_valid_odd)) begin // {
frf_tmp = `FRF0_ODD[(mytid*32)+i];
push_delta_fw (`FP_OFFSET + (i*2)+1,frf_tmp[31:0], index);
//----------------------------------------------------------
// Stage FW1 of delta pipeline
index = delta_fw[`NEXT_INDEX];
// Pipeline previous stage
for (i=0; i<=delta_fw[`NEXT_INDEX]; i=i+1) begin // {
delta_fw1[i] <= delta_fw[i];
// Update FRF0 - FPops use W1 port.
if (fp_complete) begin // {
// IF W2 port is also being written, ignore that address
for (i=0; i<=31; i=i+1) begin // {
if (!((i == frf_w2_skip_addr) && frf_w2_valid_even)) begin // {
frf_tmp = `FRF0_EVEN[(mytid*32)+i];
push_delta_fw1 (`FP_OFFSET + (i*2), frf_tmp[31:0], index);
if (!((i == frf_w2_skip_addr) && frf_w2_valid_odd)) begin // {
frf_tmp = `FRF0_ODD[(mytid*32)+i];
push_delta_fw1 (`FP_OFFSET + (i*2)+1,frf_tmp[31:0], index);
if (complete_fw[`IMUL_INDEX]|complete_fw[`IDIV_INDEX]) begin
push_delta_fw1 (`CCR+`CTL_OFFSET,CCR_reg,index);
push_delta_fw1 (`Y+`CTL_OFFSET,Y_reg,index);
push_delta_fw1 (`CWP+`CTL_OFFSET,CWP_reg,index);
push_delta_fw1 (`CANSAVE+`CTL_OFFSET,CANSAVE_reg,index);
push_delta_fw1 (`CANRESTORE+`CTL_OFFSET,CANRESTORE_reg,index);
push_delta_fw1 (`CLEANWIN+`CTL_OFFSET,CLEANWIN_reg,index);
push_delta_fw1 (`OTHERWIN+`CTL_OFFSET,OTHERWIN_reg,index);
push_delta_fw1 (`WSTATE+`CTL_OFFSET,WSTATE_reg,index);
if (complete_fw[`TLU_INDEX]) begin // {
push_delta_fw1 (`TL + `CTL_OFFSET,TL_reg,index);
push_delta_fw1 (`TPC1 + `CTL_OFFSET, TPC1_wire, index);
push_delta_fw1 (`TPC2 + `CTL_OFFSET, TPC2_wire, index);
push_delta_fw1 (`TPC3 + `CTL_OFFSET, TPC3_wire, index);
push_delta_fw1 (`TPC4 + `CTL_OFFSET, TPC4_wire, index);
push_delta_fw1 (`TPC5 + `CTL_OFFSET, TPC5_wire, index);
push_delta_fw1 (`TPC6 + `CTL_OFFSET, TPC6_wire, index);
push_delta_fw1 (`TNPC1 + `CTL_OFFSET, TNPC1_wire, index);
push_delta_fw1 (`TNPC2 + `CTL_OFFSET, TNPC2_wire, index);
push_delta_fw1 (`TNPC3 + `CTL_OFFSET, TNPC3_wire, index);
push_delta_fw1 (`TNPC4 + `CTL_OFFSET, TNPC4_wire, index);
push_delta_fw1 (`TNPC5 + `CTL_OFFSET, TNPC5_wire, index);
push_delta_fw1 (`TNPC6 + `CTL_OFFSET, TNPC6_wire, index);
push_delta_fw1 (`TSTATE1 + `CTL_OFFSET, TSTATE1_wire, index);
push_delta_fw1 (`TSTATE2 + `CTL_OFFSET, TSTATE2_wire, index);
push_delta_fw1 (`TSTATE3 + `CTL_OFFSET, TSTATE3_wire, index);
push_delta_fw1 (`TSTATE4 + `CTL_OFFSET, TSTATE4_wire, index);
push_delta_fw1 (`TSTATE5 + `CTL_OFFSET, TSTATE5_wire, index);
push_delta_fw1 (`TSTATE6 + `CTL_OFFSET, TSTATE6_wire, index);
push_delta_fw1 (`HTSTATE1 + `CTL_OFFSET, HTSTATE1_wire, index);
push_delta_fw1 (`HTSTATE2 + `CTL_OFFSET, HTSTATE2_wire, index);
push_delta_fw1 (`HTSTATE3 + `CTL_OFFSET, HTSTATE3_wire, index);
push_delta_fw1 (`HTSTATE4 + `CTL_OFFSET, HTSTATE4_wire, index);
push_delta_fw1 (`HTSTATE5 + `CTL_OFFSET, HTSTATE5_wire, index);
push_delta_fw1 (`HTSTATE6 + `CTL_OFFSET, HTSTATE6_wire, index);
push_delta_fw1 (`TT1 + `CTL_OFFSET, TT1_wire, index);
push_delta_fw1 (`TT2 + `CTL_OFFSET, TT2_wire, index);
push_delta_fw1 (`TT3 + `CTL_OFFSET, TT3_wire, index);
push_delta_fw1 (`TT4 + `CTL_OFFSET, TT4_wire, index);
push_delta_fw1 (`TT5 + `CTL_OFFSET, TT5_wire, index);
push_delta_fw1 (`TT6 + `CTL_OFFSET, TT6_wire, index);
//----------------------------------------------------------
// Stage FW2 of delta pipeline
index = delta_fw1[`NEXT_INDEX];
// Pipeline previous stage
for (i=0; i<=delta_fw1[`NEXT_INDEX]; i=i+1) begin // {
delta_fw2[i] <= delta_fw1[i];
delta_fw2[`TIME_INDEX] <= $time;
// Update Registers that may change asynchronously
// If sstep was already sent by another module,
// don't capture until the next sstep
if (complete_fw1 && !`NASTOP.sstep_early[mytnum]) begin // {
if ((complete_fw1[`ASI_INDEX]|complete_fw1[`LSU_INDEX]) & asi_rdwr_hintp)
push_delta_fw2 (`HINTP + `CTL_OFFSET,asi_updated_hintp,index);
push_delta_fw2 (`HINTP + `CTL_OFFSET,HINTP_reg,index);
if ((complete_fw1[`ASI_INDEX]|complete_fw1[`LSU_INDEX]) & asi_rdwr_softint)
push_delta_fw2 (`SOFTINT + `CTL_OFFSET,asi_updated_softint,index);
push_delta_fw2 (`SOFTINT + `CTL_OFFSET,rd_SOFTINT_reg,index);
if (complete_fw1[`IMUL_INDEX] |
complete_fw1[`IDIV_INDEX]) begin // {
if (mytid <= 3) begin // {
for (i=0; i<=31; i=i+1) begin // {
push_delta_fw2 (i,`IRF0_EXU0[(remap(i,oddwin)+irf_offset)],index);
for (i=0; i<=31; i=i+1) begin // {
push_delta_fw2 (i,`IRF0_EXU1[(remap(i,oddwin)+irf_offset)],index);
// Update FRF0 - fdivs and Imuls use W2 port
if (complete_fw1[`IMUL_INDEX] |
complete_fw1[`FDIV_INDEX] ) begin // {
// IF W1 port is also being written, ignore that address
for (i=0; i<=31; i=i+1) begin // {
if (!((i == frf_w1_skip_addr) && frf_w1_valid_even)) begin // {
frf_tmp = `FRF0_EVEN[(mytid*32)+i];
push_delta_fw2 (`FP_OFFSET + (i*2), frf_tmp[31:0], index);
if (!((i == frf_w1_skip_addr) && frf_w1_valid_odd)) begin // {
frf_tmp = `FRF0_ODD[(mytid*32)+i];
push_delta_fw2 (`FP_OFFSET + (i*2)+1,frf_tmp[31:0], index);
if (complete_fw1[`FP_INDEX] |
complete_fw1[`TLU_INDEX] |
complete_fw1[`FDIV_INDEX]) begin
push_delta_fw2 (`FSR+`CTL_OFFSET,FSR_wire,index);
push_delta_fw2 (`I_TAG_ACC+`CTL_OFFSET,itagacc_fw2,index);
push_delta_fw2 (`D_TAG_ACC+`CTL_OFFSET,dtagacc_fw2,index);
push_delta_fw2 (`DSFAR+`CTL_OFFSET,dsfar_fw2,index);
//----------------------------------------------------------
// Stage FW2 of delta pipeline - for signals that change FW+2 !!
index = delta_fw2[`NEXT_INDEX];
// Since FPRS for FPops may have been corrupted by o-o-o loads:
// If fprs_fw2 is != fprs_reg & there are loads in the pipeline
// then assume loads have already updated fprs.
// In that case, create our own fprs_reg by using the valids and
// skip_addr and copy of fprs for this op..
if (complete_fw2[`FP_INDEX] && frf_w1_valid_fw2) begin // {
// o-o-o load has changed fprs already - use dummy
if ((fprs_fw2 != FPRS_reg) && (complete_fw1[`LSU_INDEX] |
complete_fw[`LSU_INDEX] | complete_fb[`LSU_INDEX] |
complete_fx5[`LSU_INDEX] )) begin // {
dummy_fprs = read_prev(`FPRS + `CTL_OFFSET);
dummy_fprs = dummy_fprs |
{1'b0, frf_w1_skip_addr4_fw2, ~frf_w1_skip_addr4_fw2};
push_delta_fw2_async (`FPRS + `CTL_OFFSET,dummy_fprs,index);
// o-o-o load has NOT changed fprs already - use it
push_delta_fw2_async (`FPRS + `CTL_OFFSET,FPRS_reg,index);
// Load FPRS for loads/reads as prev|fprs_fb ..
// since loads may only 'set' bits, not clear ...
else if (complete_fw2[`LSU_INDEX]) begin // {
dummy_fprs = read_prev(`FPRS + `CTL_OFFSET);
dummy_fprs = dummy_fprs | fprs_fw1;
push_delta_fw2_async (`FPRS +`CTL_OFFSET,dummy_fprs,index);
// Load FPRS for store ASI or FDIV
// FDIV can update FPRS on w1 or w2,
// but the pipe is stalled behind it so no o-o-o loads.
else if ((complete_fw2[`ASI_INDEX]) ||
(complete_fw2[`FDIV_INDEX])) begin // {
push_delta_fw2_async (`FPRS + `CTL_OFFSET,FPRS_reg,index);
//----------------------------------------------------------
// Store latest values into delta
index = delta_prev[`NEXT_INDEX];
if (in_wmr & ~`SPC0.rst_wmr_protect) begin // {
push_delta_prev_async ( `PC+`CTL_OFFSET,{16'b0,pc_fw2|1},index);
push_delta_prev_async ( `PC+`CTL_OFFSET,{16'b0,pc_fw2},index);
//----------------------------------------------------------
//----------------------------------------------------------
// Compare with current state and capture if different
if (act_value != read_prev(id)) begin // { // Diff vs prev
calc_cwp(CWP_reg,id,win,type); // special case for 1st stage
write_prev(id,act_value);
delta_fx4[next] <= {type,win,id,act_value};
delta_fx4[next] <= 77'hx;
delta_fx4[`NEXT_INDEX] <= next;
if (`PARGS.axis_debug_on) begin
$display("AXIS: T%0d pc=%h id=%0d type=%0h win=%0h value=%h ts=%0d",
mytnum,PC_reg,id,type,win,act_value,$time);
if (`PARGS.axis_debug_on) begin
$display("AXIS: T%0d pc=%h id=%0d type=%0h win=%0h value=%h ts=%0d",
mytnum,PC_reg,id,type,win,act_value,$time);
//----------------------------------------------------------
// Compare with current state and capture if different
if (act_value != read_prev(id)) begin // { // Diff vs prev
calc_cwp(delta_fx4[`CWP_INDEX],id,win,type);
write_prev(id,act_value);
delta_fx5[next] <= {type,win,id,act_value};
delta_fx5[next] <= 77'hx;
delta_fx5[`NEXT_INDEX] <= next;
if (`PARGS.axis_debug_on) begin
$display("AXIS: T%0d pc=%h id=%0d type=%0h win=%0h value=%h ts=%0d",
mytnum,pc_fx4,id,type,win,act_value,$time);
calc_cwp(cwp_fx4,id,win,type);
if (`PARGS.axis_debug_on) begin
$display("AXIS: T%0d pc=%h id=%0d type=%0h win=%0h value=%h ts=%0d",
mytnum,pc_fx4,id,type,win,act_value,$time);
//----------------------------------------------------------
// Compare with current state and capture if different
if (act_value != read_prev(id)) begin // { // Diff vs prev
calc_cwp(delta_fx5[`CWP_INDEX],id,win,type);
write_prev(id,act_value);
delta_fb[next] <= {type,win,id,act_value};
delta_fb[`NEXT_INDEX] <= next;
if (`PARGS.axis_debug_on) begin
$display("AXIS: T%0d pc=%h id=%0d type=%0h win=%0h value=%h ts=%0d",
mytnum,pc_fx5,id,type,win,act_value,$time);
calc_cwp(cwp_fx5,id,win,type);
if (`PARGS.axis_debug_on) begin
$display("AXIS: T%0d pc=%h id=%0d type=%0h win=%0h value=%h ts=%0d",
mytnum,pc_fx5,id,type,win,act_value,$time);
//----------------------------------------------------------
// Compare with current state and capture if different
if (act_value != read_prev(id)) begin // { // Diff vs prev
calc_cwp(delta_fb[`CWP_INDEX],id,win,type);
write_prev(id,act_value);
delta_fw[next] <= {type,win,id,act_value};
delta_fw[`NEXT_INDEX] <= next;
if (`PARGS.axis_debug_on) begin
$display("AXIS: T%0d pc=%h id=%0d type=%0h win=%0h value=%h ts=%0d",
mytnum,pc_fb,id,type,win,act_value,$time);
calc_cwp(cwp_fb[`CWP_INDEX],id,win,type);
if (`PARGS.axis_debug_on) begin
$display("AXIS: T%0d pc=%h id=%0d type=%0h win=%0h value=%h ts=%0d",
mytnum,pc_fb,id,type,win,act_value,$time);
//----------------------------------------------------------
// Compare with current state and capture if different
if (act_value != read_prev(id)) begin // { // Diff vs prev
calc_cwp(delta_fw[`CWP_INDEX],id,win,type);
write_prev(id,act_value);
delta_fw1[next] <= {type,win,id,act_value};
delta_fw1[next] <= 77'hx;
delta_fw1[`NEXT_INDEX] <= next;
if (`PARGS.axis_debug_on) begin
$display("AXIS: T%0d pc=%h id=%0d type=%0h win=%0h value=%h ts=%0d",
mytnum,pc_fw,id,type,win,act_value,$time);
calc_cwp(cwp_fw,id,win,type);
if (`PARGS.axis_debug_on) begin
$display("AXIS: T%0d pc=%h id=%0d type=%0h win=%0h value=%h ts=%0d",
mytnum,pc_fw,id,type,win,act_value,$time);
//----------------------------------------------------------
// Compare with current state and capture if different
if (act_value != read_prev(id)) begin // { // Diff vs prev
calc_cwp(delta_fw1[`CWP_INDEX],id,win,type);
write_prev(id,act_value);
delta_fw2[next] <= {type,win,id,act_value};
delta_fw2[next] <= 77'hx;
delta_fw2[`NEXT_INDEX] <= next;
if (`PARGS.axis_debug_on) begin
$display("AXIS: T%0d pc=%h id=%0d type=%0h win=%0h value=%h ts=%0d",
mytnum,pc_fw1,id,type,win,act_value,$time);
calc_cwp(cwp_fw1,id,win,type);
if (`PARGS.axis_debug_on) begin
$display("AXIS: T%0d pc=%h id=%0d type=%0h win=%0h value=%h ts=%0d",
mytnum,pc_fw1,id,type,win,act_value,$time);
//----------------------------------------------------------
// Compare with current state and capture if different
// This is for late changing registers
// Use blocking assignments.
task push_delta_fw2_async;
if (act_value != read_prev(id)) begin // { // Diff vs prev
calc_cwp(delta_fw2[`CWP_INDEX],id,win,type);
write_prev_async(id,act_value);
delta_fw2[next] = {type,win,id,act_value};
delta_fw2[`NEXT_INDEX] = next;
if (`PARGS.axis_debug_on) begin
$display("AXIS: T%0d pc=%h id=%0d type=%0h win=%0h value=%h ts=%0d",
mytnum,pc_fw1,id,type,win,act_value,$time);
calc_cwp(cwp_fw2,id,win,type);
if (`PARGS.axis_debug_on) begin
$display("AXIS: T%0d pc=%h id=%0d type=%0h win=%0h value=%h ts=%0d",
mytnum,pc_fw1,id,type,win,act_value,$time);
//----------------------------------------------------------
// Compare with current state and capture if different
// Use blocking assignments so that push_simics will work
task push_delta_prev_async;
if (act_value != read_prev(id)) begin // { // Diff vs prev
calc_cwp(delta_prev[`CWP_INDEX],id,win,type);
write_prev_async(id,act_value);
delta_prev[next] = {type,win,id,act_value};
delta_prev[next] = 77'hx;
delta_prev[`NEXT_INDEX] = next;
if (`PARGS.axis_debug_on) begin
$display("AXIS: T%0d pc=%h id=%0d type=%0h win=%0h value=%h ts=%0d",
mytnum,pc_last,id,type,win,act_value,$time);
if (`PARGS.axis_debug_on) begin
calc_cwp(cwp_last,id,win,type);
$display("AXIS: T%0d pc=%h id=%0d type=%0h win=%0h value=%h ts=%0d",
mytnum,pc_last,id,type,win,act_value,$time);
//----------------------------------------------------------
// prev of delta pipeline
// Pipeline previous stage
for (i=0; i<=delta_fw2[`NEXT_INDEX]; i=i+1) begin // {
delta_prev[i] <= delta_fw2[i];
//----------------------------------------------------------
//----------------------------------------------------------
// Sort delta list in register ID order, then push to simics
// Or print deltas if sas check disabled ..
// Order of registers reported to simics must be:
// Global 0-7 aka prev_reg[0:7]
// Window 8-23 aka prev_reg[8:23]
// Floating 0-63 aka prev_reg[200:263]
// Control 32-143 aka prev_reg[32:143]
act_level = delta_prev[`GL_INDEX]; // GL
time_fw2 = delta_prev[`TIME_INDEX]; // Finish time
for (i=`FIRST_INDEX; i<delta_prev[`NEXT_INDEX]; i=i+1) begin // {
{type,win,regnum,value} = delta_prev[i];
if (regnum<=7) begin // {
if (`PARGS.nas_check_on) begin // {
`ACT_STATUS = $queue(`ACT_QUEUE, `PUSH_Q, mytnum, time_fw2, act_type,
act_level, regnum, value);
else if (`PARGS.show_delta_on) begin // {
`NASTOP.print_delta (mytnum,act_type,win,regnum,value);
else if (regnum<=23) begin // { %o0-%l7, %l0-%l7
if (`PARGS.nas_check_on) begin // {
`ACT_STATUS = $queue(`ACT_QUEUE, `PUSH_Q, mytnum, time_fw2, act_type,
else if (`PARGS.show_delta_on) begin // {
`NASTOP.print_delta (mytnum,act_type,win,regnum,value);
else if (regnum<=31) begin // { %i0-%i7
if (`PARGS.nas_check_on) begin // {
`ACT_STATUS = $queue(`ACT_QUEUE, `PUSH_Q, mytnum, time_fw2, act_type,
win, (regnum-16), value);
else if (`PARGS.show_delta_on) begin // {
`NASTOP.print_delta (mytnum,act_type,win,(regnum-16),value);
else if (regnum<=(64+`FP_OFFSET)) begin // {
if (`PARGS.nas_check_on) begin // {
`ACT_STATUS = $queue(`ACT_QUEUE, `PUSH_Q, mytnum, time_fw2, act_type,
(regnum-`FP_OFFSET), value);
else if (`PARGS.show_delta_on) begin // {
`NASTOP.print_delta (mytnum,act_type,win,(regnum-`FP_OFFSET),value);
else if ((regnum>=(32+`CTL_OFFSET))&(regnum<=(143+`CTL_OFFSET))) begin // {
if (`PARGS.nas_check_on) begin // {
`ACT_STATUS = $queue(`ACT_QUEUE, `PUSH_Q, mytnum, time_fw2, act_type,
(regnum-`CTL_OFFSET), value);
else if (`PARGS.show_delta_on) begin // {
`NASTOP.print_delta (mytnum,act_type,win,(regnum-`CTL_OFFSET),value);
`PR_ERROR ("nas", `ERROR, " - T%0d Bench problem. push_simics has bad regnum", mytnum);
value = delta_prev[`OPCODE_INDEX];
if (`PARGS.nas_check_on) begin // {
`ACT_STATUS = $queue(`ACT_QUEUE, `PUSH_Q, mytnum, time_fw2, act_type,
else if (`PARGS.show_delta_on) begin // {
`NASTOP.print_delta (mytnum,act_type,win,regnum,value);
// Push End of Instruction Delimiter
// The value field for this PUSH equals the PC for this instruction.
// so that printing to the logfile works correctly.
// prev_reg[`PC] = current instruction PC
// delta_reg[`PC] = PC at end of current instruction
pc = delta_prev[`PC_INDEX];
if (`PARGS.nas_check_on) begin // {
`ACT_STATUS = $queue(`ACT_QUEUE, `PUSH_Q, mytnum, time_fw2, act_type,
delta_fw2[`CWP_INDEX], `END_INSTR, pc);
else if (`PARGS.show_delta_on) begin // {
`NASTOP.print_delta (mytnum,act_type,delta_fw2[`CWP_INDEX],`END_INSTR,0);
if (! `PARGS.nas_check_on) begin // {
`PR_NORMAL ("nas", `NORMAL, "@%0d T%0d %h (Unchecked..)",
$time, mytnum, {16'b0,pc});
`TOP.last_act_cycle = `TOP.core_cycle_cnt; //$time;
`TOP.th_last_act_cycle[mytnum] = `TOP.last_act_cycle;
if (! `PARGS.nas_check_on) begin // {
`TOP.last_act_cycle = `TOP.core_cycle_cnt; //$time;
`TOP.th_last_act_cycle[mytnum] = `TOP.last_act_cycle;
//----------------------------------------------------------
// Save current window to previous window, then copy new window to current window
// Save current window to Old window
// Copy New window to current window
//----------------------------------------------------------
// Save current global to previous global, then copy new global to current global
// Save current global to Old global
// Copy New global current global
//----------------------------------------------------------
// Return window number and register type based on cwp and regnum as input
else if (id<=23) begin // {
else if (id<=31) begin // {
else if (id<=(64+`FP_OFFSET)) begin // {
//----------------------------------------------------------
// Check for bad signal values
8'b10000000: ; // good value
`PR_ERROR ("nas", `ERROR, " - T%0d More than one instruction retired in a single cycle for this thread.",
$write("\t\t\t\t Instructions - ");
if (complete_fw2[`EXU_INDEX]) $write("EXU op, ");
if (complete_fw2[`FP_INDEX]) $write("FP op, ");
if (complete_fw2[`LSU_INDEX]) $write("LSU op, ");
if (complete_fw2[`IMUL_INDEX]) $write("IMUL op, ");
if (complete_fw2[`IDIV_INDEX]) $write("IDIV op, ");
if (complete_fw2[`FDIV_INDEX]) $write("FDIV op, ");
if (complete_fw2[`TLU_INDEX]) $write("TLU op, ");
if (complete_fw2[`ASI_INDEX]) $write("ASI op, ");
$write(" complete_fw2 = %b \n",complete_fw2);
// This check only works if diags are written properly.
// For example, if a diag writes to one of these registers using wrpr,
// then this check must be disabled using plusarg.
// CANSAVE + CANRESTORE + OTHERWIN = NWINDOWS-2 (per Sparc V9)
if (`PARGS.win_check_on) begin // {
if (complete_fw2 & ((CANSAVE_reg + CANRESTORE_reg + OTHERWIN_reg) != 6)) begin // {
`PR_ERROR ("nas", `ERROR, "ERROR - T%0d Bad Values for window registers.", mytnum);
`PR_ERROR ("nas", `ERROR, "- CANSAVE = %0d CANRESTORE = %0d OTHERWIN = %0d",
CANSAVE_reg, CANRESTORE_reg,OTHERWIN_reg);
//----------------------------------------------------------
//----------------------------------------------------------
reg [`DELTA_WIDTH:0] temp1, temp2;
last = delta_prev[`NEXT_INDEX]-1;
for (i=`FIRST_INDEX; i <= last; i=i+1) begin // {
for (j=`FIRST_INDEX; j < last; j=j+1) begin // {
temp1 = delta_prev[j]; temp2 = delta_prev[j+1];
if (temp1[76:64] > temp2[76:64]) begin // {
delta_prev[j] = temp2; delta_prev [j+1] = temp1;
//----------------------------------------------------------
//----------------------------------------------------------
// Print one entry in delta_* array
input [`DELTA_WIDTH:0] delta_entry;
reg [(20*8)-1:0] type_str;
reg [(20*8)-1:0] regname;
{type,win,id,act_value} = delta_entry;
`NASTOP.get_regname(mytnum,type_str,win,id,regname);
`PR_NORMAL ("nas", `NORMAL, "type=%0s win=%0d RegID=%0d %0s=%h",
type_str,win,id,regname,act_value);
//----------------------------------------------------------
// Write Value to prev_reg using id as index (non-blocking)
8'd0: prev_reg0 <= value;
8'd1: prev_reg1 <= value;
8'd2: prev_reg2 <= value;
8'd3: prev_reg3 <= value;
8'd4: prev_reg4 <= value;
8'd5: prev_reg5 <= value;
8'd6: prev_reg6 <= value;
8'd7: prev_reg7 <= value;
8'd8: prev_reg8 <= value;
8'd9: prev_reg9 <= value;
8'd10: prev_reg10 <= value;
8'd11: prev_reg11 <= value;
8'd12: prev_reg12 <= value;
8'd13: prev_reg13 <= value;
8'd14: prev_reg14 <= value;
8'd15: prev_reg15 <= value;
8'd16: prev_reg16 <= value;
8'd17: prev_reg17 <= value;
8'd18: prev_reg18 <= value;
8'd19: prev_reg19 <= value;
8'd20: prev_reg20 <= value;
8'd21: prev_reg21 <= value;
8'd22: prev_reg22 <= value;
8'd23: prev_reg23 <= value;
8'd24: prev_reg24 <= value;
8'd25: prev_reg25 <= value;
8'd26: prev_reg26 <= value;
8'd27: prev_reg27 <= value;
8'd28: prev_reg28 <= value;
8'd29: prev_reg29 <= value;
8'd30: prev_reg30 <= value;
8'd31: prev_reg31 <= value;
8'd32: prev_reg32 <= value;
8'd33: prev_reg33 <= value;
8'd34: prev_reg34 <= value;
8'd35: prev_reg35 <= value;
8'd36: prev_reg36 <= value;
8'd37: prev_reg37 <= value;
8'd38: prev_reg38 <= value;
8'd39: prev_reg39 <= value;
8'd40: prev_reg40 <= value;
8'd41: prev_reg41 <= value;
8'd42: prev_reg42 <= value;
8'd43: prev_reg43 <= value;
8'd44: prev_reg44 <= value;
8'd45: prev_reg45 <= value;
8'd46: prev_reg46 <= value;
8'd47: prev_reg47 <= value;
8'd48: prev_reg48 <= value;
8'd49: prev_reg49 <= value;
8'd50: prev_reg50 <= value;
8'd51: prev_reg51 <= value;
8'd52: prev_reg52 <= value;
8'd53: prev_reg53 <= value;
8'd54: prev_reg54 <= value;
8'd55: prev_reg55 <= value;
8'd56: prev_reg56 <= value;
8'd57: prev_reg57 <= value;
8'd58: prev_reg58 <= value;
8'd59: prev_reg59 <= value;
8'd60: prev_reg60 <= value;
8'd61: prev_reg61 <= value;
8'd62: prev_reg62 <= value;
8'd63: prev_reg63 <= value;
8'd64: prev_reg64 <= value;
8'd65: prev_reg65 <= value;
8'd66: prev_reg66 <= value;
8'd67: prev_reg67 <= value;
8'd68: prev_reg68 <= value;
8'd69: prev_reg69 <= value;
8'd70: prev_reg70 <= value;
8'd71: prev_reg71 <= value;
8'd72: prev_reg72 <= value;
8'd73: prev_reg73 <= value;
8'd74: prev_reg74 <= value;
8'd75: prev_reg75 <= value;
8'd76: prev_reg76 <= value;
8'd77: prev_reg77 <= value;
8'd78: prev_reg78 <= value;
8'd79: prev_reg79 <= value;
8'd80: prev_reg80 <= value;
8'd81: prev_reg81 <= value;
8'd82: prev_reg82 <= value;
8'd83: prev_reg83 <= value;
8'd84: prev_reg84 <= value;
8'd85: prev_reg85 <= value;
8'd86: prev_reg86 <= value;
8'd87: prev_reg87 <= value;
8'd88: prev_reg88 <= value;
8'd89: prev_reg89 <= value;
8'd90: prev_reg90 <= value;
8'd91: prev_reg91 <= value;
8'd92: prev_reg92 <= value;
8'd93: prev_reg93 <= value;
8'd94: prev_reg94 <= value;
8'd95: prev_reg95 <= value;
8'd96: prev_reg96 <= value;
8'd97: prev_reg97 <= value;
8'd98: prev_reg98 <= value;
8'd99: prev_reg99 <= value;
8'd100: prev_reg100 <= value;
8'd101: prev_reg101 <= value;
8'd102: prev_reg102 <= value;
8'd103: prev_reg103 <= value;
8'd104: prev_reg104 <= value;
8'd105: prev_reg105 <= value;
8'd106: prev_reg106 <= value;
8'd107: prev_reg107 <= value;
8'd108: prev_reg108 <= value;
8'd109: prev_reg109 <= value;
8'd110: prev_reg110 <= value;
8'd111: prev_reg111 <= value;
8'd112: prev_reg112 <= value;
8'd113: prev_reg113 <= value;
8'd114: prev_reg114 <= value;
8'd115: prev_reg115 <= value;
8'd116: prev_reg116 <= value;
8'd117: prev_reg117 <= value;
8'd118: prev_reg118 <= value;
8'd119: prev_reg119 <= value;
8'd120: prev_reg120 <= value;
8'd121: prev_reg121 <= value;
8'd122: prev_reg122 <= value;
8'd123: prev_reg123 <= value;
8'd124: prev_reg124 <= value;
8'd125: prev_reg125 <= value;
8'd126: prev_reg126 <= value;
8'd127: prev_reg127 <= value;
8'd128: prev_reg128 <= value;
8'd129: prev_reg129 <= value;
8'd130: prev_reg130 <= value;
8'd131: prev_reg131 <= value;
8'd132: prev_reg132 <= value;
8'd133: prev_reg133 <= value;
8'd134: prev_reg134 <= value;
8'd135: prev_reg135 <= value;
8'd136: prev_reg136 <= value;
8'd137: prev_reg137 <= value;
8'd138: prev_reg138 <= value;
8'd139: prev_reg139 <= value;
8'd140: prev_reg140 <= value;
8'd141: prev_reg141 <= value;
8'd142: prev_reg142 <= value;
8'd143: prev_reg143 <= value;
8'd144: prev_reg144 <= value;
8'd145: prev_reg145 <= value;
8'd146: prev_reg146 <= value;
8'd147: prev_reg147 <= value;
8'd148: prev_reg148 <= value;
8'd149: prev_reg149 <= value;
8'd150: prev_reg150 <= value;
8'd151: prev_reg151 <= value;
8'd152: prev_reg152 <= value;
8'd153: prev_reg153 <= value;
8'd154: prev_reg154 <= value;
8'd155: prev_reg155 <= value;
8'd156: prev_reg156 <= value;
8'd157: prev_reg157 <= value;
8'd158: prev_reg158 <= value;
8'd159: prev_reg159 <= value;
8'd160: prev_reg160 <= value;
8'd161: prev_reg161 <= value;
8'd162: prev_reg162 <= value;
8'd163: prev_reg163 <= value;
8'd164: prev_reg164 <= value;
8'd165: prev_reg165 <= value;
8'd166: prev_reg166 <= value;
8'd167: prev_reg167 <= value;
8'd168: prev_reg168 <= value;
8'd169: prev_reg169 <= value;
8'd170: prev_reg170 <= value;
8'd171: prev_reg171 <= value;
8'd172: prev_reg172 <= value;
8'd173: prev_reg173 <= value;
8'd174: prev_reg174 <= value;
8'd175: prev_reg175 <= value;
8'd176: prev_reg176 <= value;
8'd177: prev_reg177 <= value;
8'd178: prev_reg178 <= value;
8'd179: prev_reg179 <= value;
8'd180: prev_reg180 <= value;
8'd181: prev_reg181 <= value;
8'd182: prev_reg182 <= value;
8'd183: prev_reg183 <= value;
8'd184: prev_reg184 <= value;
8'd185: prev_reg185 <= value;
8'd186: prev_reg186 <= value;
8'd187: prev_reg187 <= value;
8'd188: prev_reg188 <= value;
8'd189: prev_reg189 <= value;
8'd190: prev_reg190 <= value;
8'd191: prev_reg191 <= value;
8'd192: prev_reg192 <= value;
8'd193: prev_reg193 <= value;
8'd194: prev_reg194 <= value;
8'd195: prev_reg195 <= value;
8'd196: prev_reg196 <= value;
8'd197: prev_reg197 <= value;
8'd198: prev_reg198 <= value;
8'd199: prev_reg199 <= value;
8'd200: prev_reg200 <= value;
8'd201: prev_reg201 <= value;
8'd202: prev_reg202 <= value;
8'd203: prev_reg203 <= value;
8'd204: prev_reg204 <= value;
8'd205: prev_reg205 <= value;
8'd206: prev_reg206 <= value;
8'd207: prev_reg207 <= value;
8'd208: prev_reg208 <= value;
8'd209: prev_reg209 <= value;
8'd210: prev_reg210 <= value;
8'd211: prev_reg211 <= value;
8'd212: prev_reg212 <= value;
8'd213: prev_reg213 <= value;
8'd214: prev_reg214 <= value;
8'd215: prev_reg215 <= value;
8'd216: prev_reg216 <= value;
8'd217: prev_reg217 <= value;
8'd218: prev_reg218 <= value;
8'd219: prev_reg219 <= value;
8'd220: prev_reg220 <= value;
8'd221: prev_reg221 <= value;
8'd222: prev_reg222 <= value;
8'd223: prev_reg223 <= value;
8'd224: prev_reg224 <= value;
8'd225: prev_reg225 <= value;
8'd226: prev_reg226 <= value;
8'd227: prev_reg227 <= value;
8'd228: prev_reg228 <= value;
8'd229: prev_reg229 <= value;
8'd230: prev_reg230 <= value;
8'd231: prev_reg231 <= value;
8'd232: prev_reg232 <= value;
8'd233: prev_reg233 <= value;
8'd234: prev_reg234 <= value;
8'd235: prev_reg235 <= value;
8'd236: prev_reg236 <= value;
8'd237: prev_reg237 <= value;
8'd238: prev_reg238 <= value;
8'd239: prev_reg239 <= value;
8'd240: prev_reg240 <= value;
8'd241: prev_reg241 <= value;
8'd242: prev_reg242 <= value;
8'd243: prev_reg243 <= value;
8'd244: prev_reg244 <= value;
8'd245: prev_reg245 <= value;
8'd246: prev_reg246 <= value;
8'd247: prev_reg247 <= value;
8'd248: prev_reg248 <= value;
8'd249: prev_reg249 <= value;
8'd250: prev_reg250 <= value;
8'd251: prev_reg251 <= value;
8'd252: prev_reg252 <= value;
8'd253: prev_reg253 <= value;
8'd254: prev_reg254 <= value;
8'd255: prev_reg255 <= value;
//----------------------------------------------------------
// Write Value to prev_reg using id as index (blocking)
8'd10: prev_reg10 = value;
8'd11: prev_reg11 = value;
8'd12: prev_reg12 = value;
8'd13: prev_reg13 = value;
8'd14: prev_reg14 = value;
8'd15: prev_reg15 = value;
8'd16: prev_reg16 = value;
8'd17: prev_reg17 = value;
8'd18: prev_reg18 = value;
8'd19: prev_reg19 = value;
8'd20: prev_reg20 = value;
8'd21: prev_reg21 = value;
8'd22: prev_reg22 = value;
8'd23: prev_reg23 = value;
8'd24: prev_reg24 = value;
8'd25: prev_reg25 = value;
8'd26: prev_reg26 = value;
8'd27: prev_reg27 = value;
8'd28: prev_reg28 = value;
8'd29: prev_reg29 = value;
8'd30: prev_reg30 = value;
8'd31: prev_reg31 = value;
8'd32: prev_reg32 = value;
8'd33: prev_reg33 = value;
8'd34: prev_reg34 = value;
8'd35: prev_reg35 = value;
8'd36: prev_reg36 = value;
8'd37: prev_reg37 = value;
8'd38: prev_reg38 = value;
8'd39: prev_reg39 = value;
8'd40: prev_reg40 = value;
8'd41: prev_reg41 = value;
8'd42: prev_reg42 = value;
8'd43: prev_reg43 = value;
8'd44: prev_reg44 = value;
8'd45: prev_reg45 = value;
8'd46: prev_reg46 = value;
8'd47: prev_reg47 = value;
8'd48: prev_reg48 = value;
8'd49: prev_reg49 = value;
8'd50: prev_reg50 = value;
8'd51: prev_reg51 = value;
8'd52: prev_reg52 = value;
8'd53: prev_reg53 = value;
8'd54: prev_reg54 = value;
8'd55: prev_reg55 = value;
8'd56: prev_reg56 = value;
8'd57: prev_reg57 = value;
8'd58: prev_reg58 = value;
8'd59: prev_reg59 = value;
8'd60: prev_reg60 = value;
8'd61: prev_reg61 = value;
8'd62: prev_reg62 = value;
8'd63: prev_reg63 = value;
8'd64: prev_reg64 = value;
8'd65: prev_reg65 = value;
8'd66: prev_reg66 = value;
8'd67: prev_reg67 = value;
8'd68: prev_reg68 = value;
8'd69: prev_reg69 = value;
8'd70: prev_reg70 = value;
8'd71: prev_reg71 = value;
8'd72: prev_reg72 = value;
8'd73: prev_reg73 = value;
8'd74: prev_reg74 = value;
8'd75: prev_reg75 = value;
8'd76: prev_reg76 = value;
8'd77: prev_reg77 = value;
8'd78: prev_reg78 = value;
8'd79: prev_reg79 = value;
8'd80: prev_reg80 = value;
8'd81: prev_reg81 = value;
8'd82: prev_reg82 = value;
8'd83: prev_reg83 = value;
8'd84: prev_reg84 = value;
8'd85: prev_reg85 = value;
8'd86: prev_reg86 = value;
8'd87: prev_reg87 = value;
8'd88: prev_reg88 = value;
8'd89: prev_reg89 = value;
8'd90: prev_reg90 = value;
8'd91: prev_reg91 = value;
8'd92: prev_reg92 = value;
8'd93: prev_reg93 = value;
8'd94: prev_reg94 = value;
8'd95: prev_reg95 = value;
8'd96: prev_reg96 = value;
8'd97: prev_reg97 = value;
8'd98: prev_reg98 = value;
8'd99: prev_reg99 = value;
8'd100: prev_reg100 = value;
8'd101: prev_reg101 = value;
8'd102: prev_reg102 = value;
8'd103: prev_reg103 = value;
8'd104: prev_reg104 = value;
8'd105: prev_reg105 = value;
8'd106: prev_reg106 = value;
8'd107: prev_reg107 = value;
8'd108: prev_reg108 = value;
8'd109: prev_reg109 = value;
8'd110: prev_reg110 = value;
8'd111: prev_reg111 = value;
8'd112: prev_reg112 = value;
8'd113: prev_reg113 = value;
8'd114: prev_reg114 = value;
8'd115: prev_reg115 = value;
8'd116: prev_reg116 = value;
8'd117: prev_reg117 = value;
8'd118: prev_reg118 = value;
8'd119: prev_reg119 = value;
8'd120: prev_reg120 = value;
8'd121: prev_reg121 = value;
8'd122: prev_reg122 = value;
8'd123: prev_reg123 = value;
8'd124: prev_reg124 = value;
8'd125: prev_reg125 = value;
8'd126: prev_reg126 = value;
8'd127: prev_reg127 = value;
8'd128: prev_reg128 = value;
8'd129: prev_reg129 = value;
8'd130: prev_reg130 = value;
8'd131: prev_reg131 = value;
8'd132: prev_reg132 = value;
8'd133: prev_reg133 = value;
8'd134: prev_reg134 = value;
8'd135: prev_reg135 = value;
8'd136: prev_reg136 = value;
8'd137: prev_reg137 = value;
8'd138: prev_reg138 = value;
8'd139: prev_reg139 = value;
8'd140: prev_reg140 = value;
8'd141: prev_reg141 = value;
8'd142: prev_reg142 = value;
8'd143: prev_reg143 = value;
8'd144: prev_reg144 = value;
8'd145: prev_reg145 = value;
8'd146: prev_reg146 = value;
8'd147: prev_reg147 = value;
8'd148: prev_reg148 = value;
8'd149: prev_reg149 = value;
8'd150: prev_reg150 = value;
8'd151: prev_reg151 = value;
8'd152: prev_reg152 = value;
8'd153: prev_reg153 = value;
8'd154: prev_reg154 = value;
8'd155: prev_reg155 = value;
8'd156: prev_reg156 = value;
8'd157: prev_reg157 = value;
8'd158: prev_reg158 = value;
8'd159: prev_reg159 = value;
8'd160: prev_reg160 = value;
8'd161: prev_reg161 = value;
8'd162: prev_reg162 = value;
8'd163: prev_reg163 = value;
8'd164: prev_reg164 = value;
8'd165: prev_reg165 = value;
8'd166: prev_reg166 = value;
8'd167: prev_reg167 = value;
8'd168: prev_reg168 = value;
8'd169: prev_reg169 = value;
8'd170: prev_reg170 = value;
8'd171: prev_reg171 = value;
8'd172: prev_reg172 = value;
8'd173: prev_reg173 = value;
8'd174: prev_reg174 = value;
8'd175: prev_reg175 = value;
8'd176: prev_reg176 = value;
8'd177: prev_reg177 = value;
8'd178: prev_reg178 = value;
8'd179: prev_reg179 = value;
8'd180: prev_reg180 = value;
8'd181: prev_reg181 = value;
8'd182: prev_reg182 = value;
8'd183: prev_reg183 = value;
8'd184: prev_reg184 = value;
8'd185: prev_reg185 = value;
8'd186: prev_reg186 = value;
8'd187: prev_reg187 = value;
8'd188: prev_reg188 = value;
8'd189: prev_reg189 = value;
8'd190: prev_reg190 = value;
8'd191: prev_reg191 = value;
8'd192: prev_reg192 = value;
8'd193: prev_reg193 = value;
8'd194: prev_reg194 = value;
8'd195: prev_reg195 = value;
8'd196: prev_reg196 = value;
8'd197: prev_reg197 = value;
8'd198: prev_reg198 = value;
8'd199: prev_reg199 = value;
8'd200: prev_reg200 = value;
8'd201: prev_reg201 = value;
8'd202: prev_reg202 = value;
8'd203: prev_reg203 = value;
8'd204: prev_reg204 = value;
8'd205: prev_reg205 = value;
8'd206: prev_reg206 = value;
8'd207: prev_reg207 = value;
8'd208: prev_reg208 = value;
8'd209: prev_reg209 = value;
8'd210: prev_reg210 = value;
8'd211: prev_reg211 = value;
8'd212: prev_reg212 = value;
8'd213: prev_reg213 = value;
8'd214: prev_reg214 = value;
8'd215: prev_reg215 = value;
8'd216: prev_reg216 = value;
8'd217: prev_reg217 = value;
8'd218: prev_reg218 = value;
8'd219: prev_reg219 = value;
8'd220: prev_reg220 = value;
8'd221: prev_reg221 = value;
8'd222: prev_reg222 = value;
8'd223: prev_reg223 = value;
8'd224: prev_reg224 = value;
8'd225: prev_reg225 = value;
8'd226: prev_reg226 = value;
8'd227: prev_reg227 = value;
8'd228: prev_reg228 = value;
8'd229: prev_reg229 = value;
8'd230: prev_reg230 = value;
8'd231: prev_reg231 = value;
8'd232: prev_reg232 = value;
8'd233: prev_reg233 = value;
8'd234: prev_reg234 = value;
8'd235: prev_reg235 = value;
8'd236: prev_reg236 = value;
8'd237: prev_reg237 = value;
8'd238: prev_reg238 = value;
8'd239: prev_reg239 = value;
8'd240: prev_reg240 = value;
8'd241: prev_reg241 = value;
8'd242: prev_reg242 = value;
8'd243: prev_reg243 = value;
8'd244: prev_reg244 = value;
8'd245: prev_reg245 = value;
8'd246: prev_reg246 = value;
8'd247: prev_reg247 = value;
8'd248: prev_reg248 = value;
8'd249: prev_reg249 = value;
8'd250: prev_reg250 = value;
8'd251: prev_reg251 = value;
8'd252: prev_reg252 = value;
8'd253: prev_reg253 = value;
8'd254: prev_reg254 = value;
8'd255: prev_reg255 = value;
//----------------------------------------------------------
// Read value frpm prev_reg using id as index
function [63:0] read_prev;
8'd0: read_prev = prev_reg0;
8'd1: read_prev = prev_reg1;
8'd2: read_prev = prev_reg2;
8'd3: read_prev = prev_reg3;
8'd4: read_prev = prev_reg4;
8'd5: read_prev = prev_reg5;
8'd6: read_prev = prev_reg6;
8'd7: read_prev = prev_reg7;
8'd8: read_prev = prev_reg8;
8'd9: read_prev = prev_reg9;
8'd10: read_prev = prev_reg10;
8'd11: read_prev = prev_reg11;
8'd12: read_prev = prev_reg12;
8'd13: read_prev = prev_reg13;
8'd14: read_prev = prev_reg14;
8'd15: read_prev = prev_reg15;
8'd16: read_prev = prev_reg16;
8'd17: read_prev = prev_reg17;
8'd18: read_prev = prev_reg18;
8'd19: read_prev = prev_reg19;
8'd20: read_prev = prev_reg20;
8'd21: read_prev = prev_reg21;
8'd22: read_prev = prev_reg22;
8'd23: read_prev = prev_reg23;
8'd24: read_prev = prev_reg24;
8'd25: read_prev = prev_reg25;
8'd26: read_prev = prev_reg26;
8'd27: read_prev = prev_reg27;
8'd28: read_prev = prev_reg28;
8'd29: read_prev = prev_reg29;
8'd30: read_prev = prev_reg30;
8'd31: read_prev = prev_reg31;
8'd32: read_prev = prev_reg32;
8'd33: read_prev = prev_reg33;
8'd34: read_prev = prev_reg34;
8'd35: read_prev = prev_reg35;
8'd36: read_prev = prev_reg36;
8'd37: read_prev = prev_reg37;
8'd38: read_prev = prev_reg38;
8'd39: read_prev = prev_reg39;
8'd40: read_prev = prev_reg40;
8'd41: read_prev = prev_reg41;
8'd42: read_prev = prev_reg42;
8'd43: read_prev = prev_reg43;
8'd44: read_prev = prev_reg44;
8'd45: read_prev = prev_reg45;
8'd46: read_prev = prev_reg46;
8'd47: read_prev = prev_reg47;
8'd48: read_prev = prev_reg48;
8'd49: read_prev = prev_reg49;
8'd50: read_prev = prev_reg50;
8'd51: read_prev = prev_reg51;
8'd52: read_prev = prev_reg52;
8'd53: read_prev = prev_reg53;
8'd54: read_prev = prev_reg54;
8'd55: read_prev = prev_reg55;
8'd56: read_prev = prev_reg56;
8'd57: read_prev = prev_reg57;
8'd58: read_prev = prev_reg58;
8'd59: read_prev = prev_reg59;
8'd60: read_prev = prev_reg60;
8'd61: read_prev = prev_reg61;
8'd62: read_prev = prev_reg62;
8'd63: read_prev = prev_reg63;
8'd64: read_prev = prev_reg64;
8'd65: read_prev = prev_reg65;
8'd66: read_prev = prev_reg66;
8'd67: read_prev = prev_reg67;
8'd68: read_prev = prev_reg68;
8'd69: read_prev = prev_reg69;
8'd70: read_prev = prev_reg70;
8'd71: read_prev = prev_reg71;
8'd72: read_prev = prev_reg72;
8'd73: read_prev = prev_reg73;
8'd74: read_prev = prev_reg74;
8'd75: read_prev = prev_reg75;
8'd76: read_prev = prev_reg76;
8'd77: read_prev = prev_reg77;
8'd78: read_prev = prev_reg78;
8'd79: read_prev = prev_reg79;
8'd80: read_prev = prev_reg80;
8'd81: read_prev = prev_reg81;
8'd82: read_prev = prev_reg82;
8'd83: read_prev = prev_reg83;
8'd84: read_prev = prev_reg84;
8'd85: read_prev = prev_reg85;
8'd86: read_prev = prev_reg86;
8'd87: read_prev = prev_reg87;
8'd88: read_prev = prev_reg88;
8'd89: read_prev = prev_reg89;
8'd90: read_prev = prev_reg90;
8'd91: read_prev = prev_reg91;
8'd92: read_prev = prev_reg92;
8'd93: read_prev = prev_reg93;
8'd94: read_prev = prev_reg94;
8'd95: read_prev = prev_reg95;
8'd96: read_prev = prev_reg96;
8'd97: read_prev = prev_reg97;
8'd98: read_prev = prev_reg98;
8'd99: read_prev = prev_reg99;
8'd100: read_prev = prev_reg100;
8'd101: read_prev = prev_reg101;
8'd102: read_prev = prev_reg102;
8'd103: read_prev = prev_reg103;
8'd104: read_prev = prev_reg104;
8'd105: read_prev = prev_reg105;
8'd106: read_prev = prev_reg106;
8'd107: read_prev = prev_reg107;
8'd108: read_prev = prev_reg108;
8'd109: read_prev = prev_reg109;
8'd110: read_prev = prev_reg110;
8'd111: read_prev = prev_reg111;
8'd112: read_prev = prev_reg112;
8'd113: read_prev = prev_reg113;
8'd114: read_prev = prev_reg114;
8'd115: read_prev = prev_reg115;
8'd116: read_prev = prev_reg116;
8'd117: read_prev = prev_reg117;
8'd118: read_prev = prev_reg118;
8'd119: read_prev = prev_reg119;
8'd120: read_prev = prev_reg120;
8'd121: read_prev = prev_reg121;
8'd122: read_prev = prev_reg122;
8'd123: read_prev = prev_reg123;
8'd124: read_prev = prev_reg124;
8'd125: read_prev = prev_reg125;
8'd126: read_prev = prev_reg126;
8'd127: read_prev = prev_reg127;
8'd128: read_prev = prev_reg128;
8'd129: read_prev = prev_reg129;
8'd130: read_prev = prev_reg130;
8'd131: read_prev = prev_reg131;
8'd132: read_prev = prev_reg132;
8'd133: read_prev = prev_reg133;
8'd134: read_prev = prev_reg134;
8'd135: read_prev = prev_reg135;
8'd136: read_prev = prev_reg136;
8'd137: read_prev = prev_reg137;
8'd138: read_prev = prev_reg138;
8'd139: read_prev = prev_reg139;
8'd140: read_prev = prev_reg140;
8'd141: read_prev = prev_reg141;
8'd142: read_prev = prev_reg142;
8'd143: read_prev = prev_reg143;
8'd144: read_prev = prev_reg144;
8'd145: read_prev = prev_reg145;
8'd146: read_prev = prev_reg146;
8'd147: read_prev = prev_reg147;
8'd148: read_prev = prev_reg148;
8'd149: read_prev = prev_reg149;
8'd150: read_prev = prev_reg150;
8'd151: read_prev = prev_reg151;
8'd152: read_prev = prev_reg152;
8'd153: read_prev = prev_reg153;
8'd154: read_prev = prev_reg154;
8'd155: read_prev = prev_reg155;
8'd156: read_prev = prev_reg156;
8'd157: read_prev = prev_reg157;
8'd158: read_prev = prev_reg158;
8'd159: read_prev = prev_reg159;
8'd160: read_prev = prev_reg160;
8'd161: read_prev = prev_reg161;
8'd162: read_prev = prev_reg162;
8'd163: read_prev = prev_reg163;
8'd164: read_prev = prev_reg164;
8'd165: read_prev = prev_reg165;
8'd166: read_prev = prev_reg166;
8'd167: read_prev = prev_reg167;
8'd168: read_prev = prev_reg168;
8'd169: read_prev = prev_reg169;
8'd170: read_prev = prev_reg170;
8'd171: read_prev = prev_reg171;
8'd172: read_prev = prev_reg172;
8'd173: read_prev = prev_reg173;
8'd174: read_prev = prev_reg174;
8'd175: read_prev = prev_reg175;
8'd176: read_prev = prev_reg176;
8'd177: read_prev = prev_reg177;
8'd178: read_prev = prev_reg178;
8'd179: read_prev = prev_reg179;
8'd180: read_prev = prev_reg180;
8'd181: read_prev = prev_reg181;
8'd182: read_prev = prev_reg182;
8'd183: read_prev = prev_reg183;
8'd184: read_prev = prev_reg184;
8'd185: read_prev = prev_reg185;
8'd186: read_prev = prev_reg186;
8'd187: read_prev = prev_reg187;
8'd188: read_prev = prev_reg188;
8'd189: read_prev = prev_reg189;
8'd190: read_prev = prev_reg190;
8'd191: read_prev = prev_reg191;
8'd192: read_prev = prev_reg192;
8'd193: read_prev = prev_reg193;
8'd194: read_prev = prev_reg194;
8'd195: read_prev = prev_reg195;
8'd196: read_prev = prev_reg196;
8'd197: read_prev = prev_reg197;
8'd198: read_prev = prev_reg198;
8'd199: read_prev = prev_reg199;
8'd200: read_prev = prev_reg200;
8'd201: read_prev = prev_reg201;
8'd202: read_prev = prev_reg202;
8'd203: read_prev = prev_reg203;
8'd204: read_prev = prev_reg204;
8'd205: read_prev = prev_reg205;
8'd206: read_prev = prev_reg206;
8'd207: read_prev = prev_reg207;
8'd208: read_prev = prev_reg208;
8'd209: read_prev = prev_reg209;
8'd210: read_prev = prev_reg210;
8'd211: read_prev = prev_reg211;
8'd212: read_prev = prev_reg212;
8'd213: read_prev = prev_reg213;
8'd214: read_prev = prev_reg214;
8'd215: read_prev = prev_reg215;
8'd216: read_prev = prev_reg216;
8'd217: read_prev = prev_reg217;
8'd218: read_prev = prev_reg218;
8'd219: read_prev = prev_reg219;
8'd220: read_prev = prev_reg220;
8'd221: read_prev = prev_reg221;
8'd222: read_prev = prev_reg222;
8'd223: read_prev = prev_reg223;
8'd224: read_prev = prev_reg224;
8'd225: read_prev = prev_reg225;
8'd226: read_prev = prev_reg226;
8'd227: read_prev = prev_reg227;
8'd228: read_prev = prev_reg228;
8'd229: read_prev = prev_reg229;
8'd230: read_prev = prev_reg230;
8'd231: read_prev = prev_reg231;
8'd232: read_prev = prev_reg232;
8'd233: read_prev = prev_reg233;
8'd234: read_prev = prev_reg234;
8'd235: read_prev = prev_reg235;
8'd236: read_prev = prev_reg236;
8'd237: read_prev = prev_reg237;
8'd238: read_prev = prev_reg238;
8'd239: read_prev = prev_reg239;
8'd240: read_prev = prev_reg240;
8'd241: read_prev = prev_reg241;
8'd242: read_prev = prev_reg242;
8'd243: read_prev = prev_reg243;
8'd244: read_prev = prev_reg244;
8'd245: read_prev = prev_reg245;
8'd246: read_prev = prev_reg246;
8'd247: read_prev = prev_reg247;
8'd248: read_prev = prev_reg248;
8'd249: read_prev = prev_reg249;
8'd250: read_prev = prev_reg250;
8'd251: read_prev = prev_reg251;
8'd252: read_prev = prev_reg252;
8'd253: read_prev = prev_reg253;
8'd254: read_prev = prev_reg254;
8'd255: read_prev = prev_reg255;
//----------------------------------------------------------
remap[4] = rd[4] ^ (rd[3] & oddwin);
//----------------------------------------------------------
// Initialize nas_pipe registers
initial begin : INIT_BLOCK
nas_pipe_enable = 1'b1; // Nas_pipe always enables itself
good_trap_detected = 1'b0;
@ (posedge `BENCH_SPC0_GCLK);
`TOP.th_last_act_cycle[mytnum] = 0;
`PR_INFO ("nas", `INFO, "T%0d Init shadow registers.",mytnum);
// POR for control registers
write_prev(`FPRS +`CTL_OFFSET,3'h4);
write_prev(`CLEANWIN +`CTL_OFFSET,3'h7);
write_prev(`CANSAVE +`CTL_OFFSET,3'h6);
write_prev(`FPRS+`CTL_OFFSET,3'h4);
// POR for PSTATE = 0x14 (PEF, PRIV = 1)
write_prev(`PSTATE + `CTL_OFFSET,'h14);
// POR for HPSTATE = 0x4034 (RED, HPRIV = 1)
write_prev(`HPSTATE + `CTL_OFFSET,'h24);
// POR for TL = = 0x6 [MAXTL]
write_prev(`TL + `CTL_OFFSET,'h6);
write_prev(`TT6 + `CTL_OFFSET,'h1);
// POR for GL = MAXGL = 3
write_prev(`GL + `CTL_OFFSET,`POR_GL);
// POR for VER = {003e, 0024, 01, 0036, 07}
write_prev(`VER + `CTL_OFFSET,{32'h003e0024,VER_reg[31:24],24'h030607});
// POR for *_cmpr registers is INT_DIS = 1
write_prev(`TICK_CMPR + `CTL_OFFSET,64'h8000000000000000);
write_prev(`STICK_CMPR + `CTL_OFFSET,64'h8000000000000000);
write_prev(`HSTICK_CMPR + `CTL_OFFSET,64'h8000000000000000);
// Need to define so that 1st instruction will print correctly
write_prev(`PC+`CTL_OFFSET,`POR_PC);
delta_prev[`PC_INDEX] = `BAD_PC;
irf_offset = (mytid%4)*32;
//----------------------------------------------------------
// For WMR, we will set to 0x0, so that initial deltas
// WMR for PSTATE = 0x14 (PEF, PRIV = 1)
// write_prev(`PSTATE + `CTL_OFFSET,'h00);
// WMR for HPSTATE = 0x4034 (RED, HPRIV = 1)
// write_prev(`HPSTATE + `CTL_OFFSET,'h00);
// WMR for TL = = 0x6 [MAXTL]
// write_prev(`TL + `CTL_OFFSET,'h0);
// write_prev(`TT6 + `CTL_OFFSET,'h1);
// WMR for GL = MAXGL = 3
// write_prev(`GL + `CTL_OFFSET,0);
//----------------------------------------------------------
// For POR, we will set to 0x0, so that initial deltas
// and prev state are all consistent with DUT. No values
`PR_ALWAYS ("arg", `ALWAYS,"T%0d Resetting Nas Pipe states for POR ..",mytnum);
delta_fx4[`NEXT_INDEX] <= `FIRST_INDEX;
delta_fx4[`FIRST_INDEX] <= 77'hx;
delta_fx5[`NEXT_INDEX] <= `FIRST_INDEX;
delta_fb[`NEXT_INDEX] <= `FIRST_INDEX;
delta_fw[`NEXT_INDEX] <= `FIRST_INDEX;
delta_fw1[`NEXT_INDEX] <= `FIRST_INDEX;
delta_fw2[`NEXT_INDEX] <= `FIRST_INDEX;
`PR_INFO ("nas", `INFO, "T%0d Init shadow registers.",mytnum);
// POR for control registers
write_prev(`FPRS +`CTL_OFFSET,3'h4);
write_prev(`CLEANWIN +`CTL_OFFSET,3'h7);
write_prev(`CANSAVE +`CTL_OFFSET,3'h6);
write_prev(`FPRS+`CTL_OFFSET,3'h4);
// POR for PSTATE = 0x14 (PEF, PRIV = 1)
write_prev(`PSTATE + `CTL_OFFSET,'h14);
// POR for HPSTATE = 0x4034 (RED, HPRIV = 1)
write_prev(`HPSTATE + `CTL_OFFSET,'h24);
// POR for TL = = 0x6 [MAXTL]
write_prev(`TL + `CTL_OFFSET,'h6);
write_prev(`TT6 + `CTL_OFFSET,'h1);
// POR for GL = MAXGL = 3
write_prev(`GL + `CTL_OFFSET,`POR_GL);
// POR for VER = {003e, 0024, 01, 0036, 07}
write_prev(`VER + `CTL_OFFSET,64'h003e002410030607);
// POR for *_cmpr registers is INT_DIS = 1
write_prev(`TICK_CMPR + `CTL_OFFSET,64'h8000000000000000);
write_prev(`STICK_CMPR + `CTL_OFFSET,64'h8000000000000000);
write_prev(`HSTICK_CMPR + `CTL_OFFSET,64'h8000000000000000);
// Need to define so that 1st instruction will print correctly
write_prev(`PC+`CTL_OFFSET,`POR_PC);
//----------------------------------------------------------
//----------------------------------------------------------
// Watch for Good/Bad trap
wire [5:0] mytnum = (mycid*8)+mytid;
// Delimiter changes whether flat or hierarchical netlist
wire myclk = tb_top.cpu.spc0.gclk;
wire dec_inst_valid_m = mytg ? tb_top.cpu.spc0.dec_inst_valid_m[1] : tb_top.cpu.spc0.dec_inst_valid_m[0];
wire [1:0] dec_tid_m = mytg ? tb_top.cpu.spc0.dec_tid1_m : tb_top.cpu.spc0.dec_tid0_m;
wire dec_flush_b = mytg ? tb_top.cpu.spc0.dec_flush_b[1] : tb_top.cpu.spc0.dec_flush_b[0];
wire tlu_flush_ifu = tb_top.cpu.spc0.tlu_flush_ifu[mytid];
wire [47:0] pc_d = mytg ? {tb_top.cpu.spc0.tlu_pc_1_d[47:2],2'b0} : {tb_top.cpu.spc0.tlu_pc_0_d[47:2],2'b0};
wire [31:0] op_d = mytg ? tb_top.cpu.spc0.dec_inst1_d[31:0] : tb_top.cpu.spc0.dec_inst0_d[31:0];
wire myclk = tb_top.cpu.spc0.gclk;
wire dec_inst_valid_m = mytg ? tb_top.cpu.spc0.dec_inst_valid_m[1] : tb_top.cpu.spc0.dec_inst_valid_m[0];
wire [1:0] dec_tid_m = mytg ? tb_top.cpu.spc0.dec_tid1_m : tb_top.cpu.spc0.dec_tid0_m;
wire dec_flush_b = mytg ? tb_top.cpu.spc0.dec_flush_b[1] : tb_top.cpu.spc0.dec_flush_b[0];
wire tlu_flush_ifu = tb_top.cpu.spc0.tlu_flush_ifu[mytid];
wire [47:0] pc_d = mytg ? {tb_top.cpu.spc0.tlu_pc_1_d[47:2],2'b0} : {tb_top.cpu.spc0.tlu_pc_0_d[47:2],2'b0};
wire [31:0] op_d = mytg ? tb_top.cpu.spc0.dec_inst1_d[31:0] : tb_top.cpu.spc0.dec_inst0_d[31:0];
wire inst_valid_b = dec_inst_valid_b && (dec_tid_b==mytid[1:0]) && !(dec_flush_b || tlu_flush_ifu);
always @ (posedge myclk) begin // {
dec_inst_valid_b <= dec_inst_valid_m;
inst_valid_w <= inst_valid_b;
inst_valid_fx4 <= inst_valid_w;
inst_valid_fx5 <= inst_valid_fx4;
inst_valid_fb <= inst_valid_fx5;
inst_valid_fw <= inst_valid_fb;
inst_valid_fw1 <= inst_valid_fw;
inst_valid_fw2 <= inst_valid_fw1;
if (`PARGS.th_check_enable[mytnum] && nas_pipe_enable) begin // {
if (inst_valid_fw2) begin // {
// Print PC/opcode for debugging
`PR_NORMAL ("nas", `NORMAL, "@%0d #%0d T%0d %h [%h]", $time, inst_count, mytnum, pc_fw2, op_fw2);
inst_count = inst_count + 1;
// End detection for GateSim runs
for (junk=0;junk<`PARGS.bad_trap_count;junk=junk+1) begin // {
if (({16'b0,pc_fw2}&`PC_MASK)===(`PARGS.bad_trap_addr[junk]&`PC_MASK)) begin // {
`PR_ERROR ("nas",`ERROR, "T%0d reached Bad Trap [GATESIM]", mytnum);
for (junk=0;junk<`PARGS.good_trap_count;junk=junk+1) begin // {
if (({16'b0,pc_fw2}&`PC_MASK)===(`PARGS.good_trap_addr[junk]&`PC_MASK)) begin // {
`TOP.finished_tids[mytnum] = 1'b1;
`PARGS.th_check_enable[mytnum] = 1'b0;
`PR_NORMAL ("nas", `NORMAL, "T%0d reached Good Trap. Disabling checking for thread %0d [GATESIM]", mytnum,mytnum);
//----------------------------------------------------------
//----------------------------------------------------------
//----------------------------------------------------------
input [71:0] TICK_CMPR_reg;
input [71:0] STICK_CMPR_reg;
input [71:0] HSTICK_CMPR_reg;
input [2:0] CANRESTORE_reg;
input [2:0] OTHERWIN_reg;
input [2:0] CLEANWIN_reg;
input [16:0] SOFTINT_reg;
input [16:0] rd_SOFTINT_reg;
input [63:0] INTR_RECEIVE_reg;
input [12:0] HPSTATE_reg;
input [63:0] CTXT_PRIM_0_reg;
input [63:0] CTXT_SEC_0_reg;
input [63:0] CTXT_PRIM_1_reg;
input [63:0] CTXT_SEC_1_reg;
input [63:0] LSU_CONTROL_reg;
input [63:0] I_TAG_ACC_reg;
input [63:0] D_TAG_ACC_reg;
input [63:0] WATCHPOINT_ADDR_reg;
input [151:0] Trap_Entry_1;
input [151:0] Trap_Entry_2;
input [151:0] Trap_Entry_3;
input [151:0] Trap_Entry_4;
input [151:0] Trap_Entry_5;
input [151:0] Trap_Entry_6;
input [1:0] frf_w2_valid;
input [1:0] frf_w1_valid;
input asi_valid; // ASI/ASR/PR writes done ..
input asi_in_progress; // ASI/ASR/PR in progess
//----------------------------------------------------------
//----------------------------------------------------------
//----------------------------------------------------------
// delta_* = {type(2bits),win(3bits),regnum(8bits),value(64bits)}
reg [`DELTA_WIDTH:0] delta_fx4 [0:(`MAX_INDEX)];
reg [`DELTA_WIDTH:0] delta_fx5 [0:(`MAX_INDEX)];
reg [`DELTA_WIDTH:0] delta_fb [0:(`MAX_INDEX)];
reg [`DELTA_WIDTH:0] delta_fw [0:(`MAX_INDEX)];
reg [`DELTA_WIDTH:0] delta_fw1 [0:(`MAX_INDEX)];
reg [`DELTA_WIDTH:0] delta_fw2 [0:(`MAX_INDEX)];
reg [`DELTA_WIDTH:0] delta_prev [0:(`MAX_INDEX)];
// need to change in several places in this file
reg [63:0] prev_reg0; // includes G,W,C,F registers
reg [63:0] prev_reg1; // includes G,W,C,F registers
reg [63:0] prev_reg2; // includes G,W,C,F registers
reg [63:0] prev_reg3; // includes G,W,C,F registers
reg [63:0] prev_reg4; // includes G,W,C,F registers
reg [63:0] prev_reg5; // includes G,W,C,F registers
reg [63:0] prev_reg6; // includes G,W,C,F registers
reg [63:0] prev_reg7; // includes G,W,C,F registers
reg [63:0] prev_reg8; // includes G,W,C,F registers
reg [63:0] prev_reg9; // includes G,W,C,F registers
reg [63:0] prev_reg10; // includes G,W,C,F registers
reg [63:0] prev_reg11; // includes G,W,C,F registers
reg [63:0] prev_reg12; // includes G,W,C,F registers
reg [63:0] prev_reg13; // includes G,W,C,F registers
reg [63:0] prev_reg14; // includes G,W,C,F registers
reg [63:0] prev_reg15; // includes G,W,C,F registers
reg [63:0] prev_reg16; // includes G,W,C,F registers
reg [63:0] prev_reg17; // includes G,W,C,F registers
reg [63:0] prev_reg18; // includes G,W,C,F registers
reg [63:0] prev_reg19; // includes G,W,C,F registers
reg [63:0] prev_reg20; // includes G,W,C,F registers
reg [63:0] prev_reg21; // includes G,W,C,F registers
reg [63:0] prev_reg22; // includes G,W,C,F registers
reg [63:0] prev_reg23; // includes G,W,C,F registers
reg [63:0] prev_reg24; // includes G,W,C,F registers
reg [63:0] prev_reg25; // includes G,W,C,F registers
reg [63:0] prev_reg26; // includes G,W,C,F registers
reg [63:0] prev_reg27; // includes G,W,C,F registers
reg [63:0] prev_reg28; // includes G,W,C,F registers
reg [63:0] prev_reg29; // includes G,W,C,F registers
reg [63:0] prev_reg30; // includes G,W,C,F registers
reg [63:0] prev_reg31; // includes G,W,C,F registers
reg [63:0] prev_reg32; // includes G,W,C,F registers
reg [63:0] prev_reg33; // includes G,W,C,F registers
reg [63:0] prev_reg34; // includes G,W,C,F registers
reg [63:0] prev_reg35; // includes G,W,C,F registers
reg [63:0] prev_reg36; // includes G,W,C,F registers
reg [63:0] prev_reg37; // includes G,W,C,F registers
reg [63:0] prev_reg38; // includes G,W,C,F registers
reg [63:0] prev_reg39; // includes G,W,C,F registers
reg [63:0] prev_reg40; // includes G,W,C,F registers
reg [63:0] prev_reg41; // includes G,W,C,F registers
reg [63:0] prev_reg42; // includes G,W,C,F registers
reg [63:0] prev_reg43; // includes G,W,C,F registers
reg [63:0] prev_reg44; // includes G,W,C,F registers
reg [63:0] prev_reg45; // includes G,W,C,F registers
reg [63:0] prev_reg46; // includes G,W,C,F registers
reg [63:0] prev_reg47; // includes G,W,C,F registers
reg [63:0] prev_reg48; // includes G,W,C,F registers
reg [63:0] prev_reg49; // includes G,W,C,F registers
reg [63:0] prev_reg50; // includes G,W,C,F registers
reg [63:0] prev_reg51; // includes G,W,C,F registers
reg [63:0] prev_reg52; // includes G,W,C,F registers
reg [63:0] prev_reg53; // includes G,W,C,F registers
reg [63:0] prev_reg54; // includes G,W,C,F registers
reg [63:0] prev_reg55; // includes G,W,C,F registers
reg [63:0] prev_reg56; // includes G,W,C,F registers
reg [63:0] prev_reg57; // includes G,W,C,F registers
reg [63:0] prev_reg58; // includes G,W,C,F registers
reg [63:0] prev_reg59; // includes G,W,C,F registers
reg [63:0] prev_reg60; // includes G,W,C,F registers
reg [63:0] prev_reg61; // includes G,W,C,F registers
reg [63:0] prev_reg62; // includes G,W,C,F registers
reg [63:0] prev_reg63; // includes G,W,C,F registers
reg [63:0] prev_reg64; // includes G,W,C,F registers
reg [63:0] prev_reg65; // includes G,W,C,F registers
reg [63:0] prev_reg66; // includes G,W,C,F registers
reg [63:0] prev_reg67; // includes G,W,C,F registers
reg [63:0] prev_reg68; // includes G,W,C,F registers
reg [63:0] prev_reg69; // includes G,W,C,F registers
reg [63:0] prev_reg70; // includes G,W,C,F registers
reg [63:0] prev_reg71; // includes G,W,C,F registers
reg [63:0] prev_reg72; // includes G,W,C,F registers
reg [63:0] prev_reg73; // includes G,W,C,F registers
reg [63:0] prev_reg74; // includes G,W,C,F registers
reg [63:0] prev_reg75; // includes G,W,C,F registers
reg [63:0] prev_reg76; // includes G,W,C,F registers
reg [63:0] prev_reg77; // includes G,W,C,F registers
reg [63:0] prev_reg78; // includes G,W,C,F registers
reg [63:0] prev_reg79; // includes G,W,C,F registers
reg [63:0] prev_reg80; // includes G,W,C,F registers
reg [63:0] prev_reg81; // includes G,W,C,F registers
reg [63:0] prev_reg82; // includes G,W,C,F registers
reg [63:0] prev_reg83; // includes G,W,C,F registers
reg [63:0] prev_reg84; // includes G,W,C,F registers
reg [63:0] prev_reg85; // includes G,W,C,F registers
reg [63:0] prev_reg86; // includes G,W,C,F registers
reg [63:0] prev_reg87; // includes G,W,C,F registers
reg [63:0] prev_reg88; // includes G,W,C,F registers
reg [63:0] prev_reg89; // includes G,W,C,F registers
reg [63:0] prev_reg90; // includes G,W,C,F registers
reg [63:0] prev_reg91; // includes G,W,C,F registers
reg [63:0] prev_reg92; // includes G,W,C,F registers
reg [63:0] prev_reg93; // includes G,W,C,F registers
reg [63:0] prev_reg94; // includes G,W,C,F registers
reg [63:0] prev_reg95; // includes G,W,C,F registers
reg [63:0] prev_reg96; // includes G,W,C,F registers
reg [63:0] prev_reg97; // includes G,W,C,F registers
reg [63:0] prev_reg98; // includes G,W,C,F registers
reg [63:0] prev_reg99; // includes G,W,C,F registers
reg [63:0] prev_reg100; // includes G,W,C,F registers
reg [63:0] prev_reg101; // includes G,W,C,F registers
reg [63:0] prev_reg102; // includes G,W,C,F registers
reg [63:0] prev_reg103; // includes G,W,C,F registers
reg [63:0] prev_reg104; // includes G,W,C,F registers
reg [63:0] prev_reg105; // includes G,W,C,F registers
reg [63:0] prev_reg106; // includes G,W,C,F registers
reg [63:0] prev_reg107; // includes G,W,C,F registers
reg [63:0] prev_reg108; // includes G,W,C,F registers
reg [63:0] prev_reg109; // includes G,W,C,F registers
reg [63:0] prev_reg110; // includes G,W,C,F registers
reg [63:0] prev_reg111; // includes G,W,C,F registers
reg [63:0] prev_reg112; // includes G,W,C,F registers
reg [63:0] prev_reg113; // includes G,W,C,F registers
reg [63:0] prev_reg114; // includes G,W,C,F registers
reg [63:0] prev_reg115; // includes G,W,C,F registers
reg [63:0] prev_reg116; // includes G,W,C,F registers
reg [63:0] prev_reg117; // includes G,W,C,F registers
reg [63:0] prev_reg118; // includes G,W,C,F registers
reg [63:0] prev_reg119; // includes G,W,C,F registers
reg [63:0] prev_reg120; // includes G,W,C,F registers
reg [63:0] prev_reg121; // includes G,W,C,F registers
reg [63:0] prev_reg122; // includes G,W,C,F registers
reg [63:0] prev_reg123; // includes G,W,C,F registers
reg [63:0] prev_reg124; // includes G,W,C,F registers
reg [63:0] prev_reg125; // includes G,W,C,F registers
reg [63:0] prev_reg126; // includes G,W,C,F registers
reg [63:0] prev_reg127; // includes G,W,C,F registers
reg [63:0] prev_reg128; // includes G,W,C,F registers
reg [63:0] prev_reg129; // includes G,W,C,F registers
reg [63:0] prev_reg130; // includes G,W,C,F registers
reg [63:0] prev_reg131; // includes G,W,C,F registers
reg [63:0] prev_reg132; // includes G,W,C,F registers
reg [63:0] prev_reg133; // includes G,W,C,F registers
reg [63:0] prev_reg134; // includes G,W,C,F registers
reg [63:0] prev_reg135; // includes G,W,C,F registers
reg [63:0] prev_reg136; // includes G,W,C,F registers
reg [63:0] prev_reg137; // includes G,W,C,F registers
reg [63:0] prev_reg138; // includes G,W,C,F registers
reg [63:0] prev_reg139; // includes G,W,C,F registers
reg [63:0] prev_reg140; // includes G,W,C,F registers
reg [63:0] prev_reg141; // includes G,W,C,F registers
reg [63:0] prev_reg142; // includes G,W,C,F registers
reg [63:0] prev_reg143; // includes G,W,C,F registers
reg [63:0] prev_reg144; // includes G,W,C,F registers
reg [63:0] prev_reg145; // includes G,W,C,F registers
reg [63:0] prev_reg146; // includes G,W,C,F registers
reg [63:0] prev_reg147; // includes G,W,C,F registers
reg [63:0] prev_reg148; // includes G,W,C,F registers
reg [63:0] prev_reg149; // includes G,W,C,F registers
reg [63:0] prev_reg150; // includes G,W,C,F registers
reg [63:0] prev_reg151; // includes G,W,C,F registers
reg [63:0] prev_reg152; // includes G,W,C,F registers
reg [63:0] prev_reg153; // includes G,W,C,F registers
reg [63:0] prev_reg154; // includes G,W,C,F registers
reg [63:0] prev_reg155; // includes G,W,C,F registers
reg [63:0] prev_reg156; // includes G,W,C,F registers
reg [63:0] prev_reg157; // includes G,W,C,F registers
reg [63:0] prev_reg158; // includes G,W,C,F registers
reg [63:0] prev_reg159; // includes G,W,C,F registers
reg [63:0] prev_reg160; // includes G,W,C,F registers
reg [63:0] prev_reg161; // includes G,W,C,F registers
reg [63:0] prev_reg162; // includes G,W,C,F registers
reg [63:0] prev_reg163; // includes G,W,C,F registers
reg [63:0] prev_reg164; // includes G,W,C,F registers
reg [63:0] prev_reg165; // includes G,W,C,F registers
reg [63:0] prev_reg166; // includes G,W,C,F registers
reg [63:0] prev_reg167; // includes G,W,C,F registers
reg [63:0] prev_reg168; // includes G,W,C,F registers
reg [63:0] prev_reg169; // includes G,W,C,F registers
reg [63:0] prev_reg170; // includes G,W,C,F registers
reg [63:0] prev_reg171; // includes G,W,C,F registers
reg [63:0] prev_reg172; // includes G,W,C,F registers
reg [63:0] prev_reg173; // includes G,W,C,F registers
reg [63:0] prev_reg174; // includes G,W,C,F registers
reg [63:0] prev_reg175; // includes G,W,C,F registers
reg [63:0] prev_reg176; // includes G,W,C,F registers
reg [63:0] prev_reg177; // includes G,W,C,F registers
reg [63:0] prev_reg178; // includes G,W,C,F registers
reg [63:0] prev_reg179; // includes G,W,C,F registers
reg [63:0] prev_reg180; // includes G,W,C,F registers
reg [63:0] prev_reg181; // includes G,W,C,F registers
reg [63:0] prev_reg182; // includes G,W,C,F registers
reg [63:0] prev_reg183; // includes G,W,C,F registers
reg [63:0] prev_reg184; // includes G,W,C,F registers
reg [63:0] prev_reg185; // includes G,W,C,F registers
reg [63:0] prev_reg186; // includes G,W,C,F registers
reg [63:0] prev_reg187; // includes G,W,C,F registers
reg [63:0] prev_reg188; // includes G,W,C,F registers
reg [63:0] prev_reg189; // includes G,W,C,F registers
reg [63:0] prev_reg190; // includes G,W,C,F registers
reg [63:0] prev_reg191; // includes G,W,C,F registers
reg [63:0] prev_reg192; // includes G,W,C,F registers
reg [63:0] prev_reg193; // includes G,W,C,F registers
reg [63:0] prev_reg194; // includes G,W,C,F registers
reg [63:0] prev_reg195; // includes G,W,C,F registers
reg [63:0] prev_reg196; // includes G,W,C,F registers
reg [63:0] prev_reg197; // includes G,W,C,F registers
reg [63:0] prev_reg198; // includes G,W,C,F registers
reg [63:0] prev_reg199; // includes G,W,C,F registers
reg [63:0] prev_reg200; // includes G,W,C,F registers
reg [63:0] prev_reg201; // includes G,W,C,F registers
reg [63:0] prev_reg202; // includes G,W,C,F registers
reg [63:0] prev_reg203; // includes G,W,C,F registers
reg [63:0] prev_reg204; // includes G,W,C,F registers
reg [63:0] prev_reg205; // includes G,W,C,F registers
reg [63:0] prev_reg206; // includes G,W,C,F registers
reg [63:0] prev_reg207; // includes G,W,C,F registers
reg [63:0] prev_reg208; // includes G,W,C,F registers
reg [63:0] prev_reg209; // includes G,W,C,F registers
reg [63:0] prev_reg210; // includes G,W,C,F registers
reg [63:0] prev_reg211; // includes G,W,C,F registers
reg [63:0] prev_reg212; // includes G,W,C,F registers
reg [63:0] prev_reg213; // includes G,W,C,F registers
reg [63:0] prev_reg214; // includes G,W,C,F registers
reg [63:0] prev_reg215; // includes G,W,C,F registers
reg [63:0] prev_reg216; // includes G,W,C,F registers
reg [63:0] prev_reg217; // includes G,W,C,F registers
reg [63:0] prev_reg218; // includes G,W,C,F registers
reg [63:0] prev_reg219; // includes G,W,C,F registers
reg [63:0] prev_reg220; // includes G,W,C,F registers
reg [63:0] prev_reg221; // includes G,W,C,F registers
reg [63:0] prev_reg222; // includes G,W,C,F registers
reg [63:0] prev_reg223; // includes G,W,C,F registers
reg [63:0] prev_reg224; // includes G,W,C,F registers
reg [63:0] prev_reg225; // includes G,W,C,F registers
reg [63:0] prev_reg226; // includes G,W,C,F registers
reg [63:0] prev_reg227; // includes G,W,C,F registers
reg [63:0] prev_reg228; // includes G,W,C,F registers
reg [63:0] prev_reg229; // includes G,W,C,F registers
reg [63:0] prev_reg230; // includes G,W,C,F registers
reg [63:0] prev_reg231; // includes G,W,C,F registers
reg [63:0] prev_reg232; // includes G,W,C,F registers
reg [63:0] prev_reg233; // includes G,W,C,F registers
reg [63:0] prev_reg234; // includes G,W,C,F registers
reg [63:0] prev_reg235; // includes G,W,C,F registers
reg [63:0] prev_reg236; // includes G,W,C,F registers
reg [63:0] prev_reg237; // includes G,W,C,F registers
reg [63:0] prev_reg238; // includes G,W,C,F registers
reg [63:0] prev_reg239; // includes G,W,C,F registers
reg [63:0] prev_reg240; // includes G,W,C,F registers
reg [63:0] prev_reg241; // includes G,W,C,F registers
reg [63:0] prev_reg242; // includes G,W,C,F registers
reg [63:0] prev_reg243; // includes G,W,C,F registers
reg [63:0] prev_reg244; // includes G,W,C,F registers
reg [63:0] prev_reg245; // includes G,W,C,F registers
reg [63:0] prev_reg246; // includes G,W,C,F registers
reg [63:0] prev_reg247; // includes G,W,C,F registers
reg [63:0] prev_reg248; // includes G,W,C,F registers
reg [63:0] prev_reg249; // includes G,W,C,F registers
reg [63:0] prev_reg250; // includes G,W,C,F registers
reg [63:0] prev_reg251; // includes G,W,C,F registers
reg [63:0] prev_reg252; // includes G,W,C,F registers
reg [63:0] prev_reg253; // includes G,W,C,F registers
reg [63:0] prev_reg254; // includes G,W,C,F registers
reg [63:0] prev_reg255; // includes G,W,C,F registers
reg [1:0] th_gl; // copy of GL_reg
reg frf_w1_skip_addr4_fw1;
reg frf_w1_skip_addr4_fw2;
reg [1:0] frf_w2_valid_fw;
reg [1:0] frf_w2_valid_bn;
reg [4:0] frf_w2_addr_fw;
reg [1:0] frf_w1_valid_fw;
reg [4:0] frf_w1_addr_fw;
reg wmr; // latched to get edge
reg por_a; // latched to get edge
reg por_b; // latched to get edge
reg nas_pipe_enable; // Turns on nas_pipe capture and Riesling SSTEP
wire [4:0] frf_w1_skip_addr;
wire [4:0] frf_w2_skip_addr;
reg good_trap_detected; // Used for -nosas only.
//----------------------------------------------------------
wire [`DELTA_WIDTH:0] delta_fx4_0;
wire [`DELTA_WIDTH:0] delta_fx4_1;
wire [`DELTA_WIDTH:0] delta_fx4_2;
wire [`DELTA_WIDTH:0] delta_fx4_3;
wire [`DELTA_WIDTH:0] delta_fx4_4;
wire [`DELTA_WIDTH:0] delta_fx4_5;
wire [`DELTA_WIDTH:0] delta_fx4_6;
wire [`DELTA_WIDTH:0] delta_fx4_7;
wire [`DELTA_WIDTH:0] delta_fx5_0;
wire [`DELTA_WIDTH:0] delta_fx5_1;
wire [`DELTA_WIDTH:0] delta_fx5_2;
wire [`DELTA_WIDTH:0] delta_fx5_3;
wire [`DELTA_WIDTH:0] delta_fx5_4;
wire [`DELTA_WIDTH:0] delta_fx5_5;
wire [`DELTA_WIDTH:0] delta_fx5_6;
wire [`DELTA_WIDTH:0] delta_fx5_7;
wire [`DELTA_WIDTH:0] delta_fb_0;
wire [`DELTA_WIDTH:0] delta_fb_1;
wire [`DELTA_WIDTH:0] delta_fb_2;
wire [`DELTA_WIDTH:0] delta_fb_3;
wire [`DELTA_WIDTH:0] delta_fb_4;
wire [`DELTA_WIDTH:0] delta_fb_5;
wire [`DELTA_WIDTH:0] delta_fb_6;
wire [`DELTA_WIDTH:0] delta_fb_7;
wire [`DELTA_WIDTH:0] delta_fw_0;
wire [`DELTA_WIDTH:0] delta_fw_1;
wire [`DELTA_WIDTH:0] delta_fw_2;
wire [`DELTA_WIDTH:0] delta_fw_3;
wire [`DELTA_WIDTH:0] delta_fw_4;
wire [`DELTA_WIDTH:0] delta_fw_5;
wire [`DELTA_WIDTH:0] delta_fw_6;
wire [`DELTA_WIDTH:0] delta_fw_7;
wire [`DELTA_WIDTH:0] delta_fw1_0;
wire [`DELTA_WIDTH:0] delta_fw1_1;
wire [`DELTA_WIDTH:0] delta_fw1_2;
wire [`DELTA_WIDTH:0] delta_fw1_3;
wire [`DELTA_WIDTH:0] delta_fw1_4;
wire [`DELTA_WIDTH:0] delta_fw1_5;
wire [`DELTA_WIDTH:0] delta_fw1_6;
wire [`DELTA_WIDTH:0] delta_fw1_7;
wire [`DELTA_WIDTH:0] delta_fw2_0;
wire [`DELTA_WIDTH:0] delta_fw2_1;
wire [`DELTA_WIDTH:0] delta_fw2_2;
wire [`DELTA_WIDTH:0] delta_fw2_3;
wire [`DELTA_WIDTH:0] delta_fw2_4;
wire [`DELTA_WIDTH:0] delta_fw2_5;
wire [`DELTA_WIDTH:0] delta_fw2_6;
wire [`DELTA_WIDTH:0] delta_fw2_7;
wire [`DELTA_WIDTH:0] delta_prev_0;
wire [`DELTA_WIDTH:0] delta_prev_1;
wire [`DELTA_WIDTH:0] delta_prev_2;
wire [`DELTA_WIDTH:0] delta_prev_3;
wire [`DELTA_WIDTH:0] delta_prev_4;
wire [`DELTA_WIDTH:0] delta_prev_5;
wire [`DELTA_WIDTH:0] delta_prev_6;
wire [`DELTA_WIDTH:0] delta_prev_7;
`PR_ALWAYS ("arg", `ALWAYS,"T%0d DEBUG_PIPE turned ON",mytnum);
//----------------------------------------------------------
// Note: no remap of %g,%o,%l,%i regs based on CWP or GL
assign g0 = (mytid<=3) ? `IRF1_EXU0[( 0+irf_offset)] : `IRF1_EXU1[( 0+irf_offset)];
assign g1 = (mytid<=3) ? `IRF1_EXU0[( 1+irf_offset)] : `IRF1_EXU1[( 1+irf_offset)];
assign g2 = (mytid<=3) ? `IRF1_EXU0[( 2+irf_offset)] : `IRF1_EXU1[( 2+irf_offset)];
assign g3 = (mytid<=3) ? `IRF1_EXU0[( 3+irf_offset)] : `IRF1_EXU1[( 3+irf_offset)];
assign g4 = (mytid<=3) ? `IRF1_EXU0[( 4+irf_offset)] : `IRF1_EXU1[( 4+irf_offset)];
assign g5 = (mytid<=3) ? `IRF1_EXU0[( 5+irf_offset)] : `IRF1_EXU1[( 5+irf_offset)];
assign g6 = (mytid<=3) ? `IRF1_EXU0[( 6+irf_offset)] : `IRF1_EXU1[( 6+irf_offset)];
assign g7 = (mytid<=3) ? `IRF1_EXU0[( 7+irf_offset)] : `IRF1_EXU1[( 7+irf_offset)];
assign o0 = (mytid<=3) ? `IRF1_EXU0[( 8+irf_offset)] : `IRF1_EXU1[( 8+irf_offset)];
assign o1 = (mytid<=3) ? `IRF1_EXU0[( 9+irf_offset)] : `IRF1_EXU1[( 9+irf_offset)];
assign o2 = (mytid<=3) ? `IRF1_EXU0[(10+irf_offset)] : `IRF1_EXU1[(10+irf_offset)];
assign o3 = (mytid<=3) ? `IRF1_EXU0[(11+irf_offset)] : `IRF1_EXU1[(11+irf_offset)];
assign o4 = (mytid<=3) ? `IRF1_EXU0[(12+irf_offset)] : `IRF1_EXU1[(12+irf_offset)];
assign o5 = (mytid<=3) ? `IRF1_EXU0[(13+irf_offset)] : `IRF1_EXU1[(13+irf_offset)];
assign o6 = (mytid<=3) ? `IRF1_EXU0[(14+irf_offset)] : `IRF1_EXU1[(14+irf_offset)];
assign o7 = (mytid<=3) ? `IRF1_EXU0[(15+irf_offset)] : `IRF1_EXU1[(15+irf_offset)];
assign l0 = (mytid<=3) ? `IRF1_EXU0[(16+irf_offset)] : `IRF1_EXU1[(16+irf_offset)];
assign l1 = (mytid<=3) ? `IRF1_EXU0[(17+irf_offset)] : `IRF1_EXU1[(17+irf_offset)];
assign l2 = (mytid<=3) ? `IRF1_EXU0[(18+irf_offset)] : `IRF1_EXU1[(18+irf_offset)];
assign l3 = (mytid<=3) ? `IRF1_EXU0[(19+irf_offset)] : `IRF1_EXU1[(19+irf_offset)];
assign l4 = (mytid<=3) ? `IRF1_EXU0[(20+irf_offset)] : `IRF1_EXU1[(20+irf_offset)];
assign l5 = (mytid<=3) ? `IRF1_EXU0[(21+irf_offset)] : `IRF1_EXU1[(21+irf_offset)];
assign l6 = (mytid<=3) ? `IRF1_EXU0[(22+irf_offset)] : `IRF1_EXU1[(22+irf_offset)];
assign l7 = (mytid<=3) ? `IRF1_EXU0[(23+irf_offset)] : `IRF1_EXU1[(23+irf_offset)];
assign i0 = (mytid<=3) ? `IRF1_EXU0[(24+irf_offset)] : `IRF1_EXU1[(24+irf_offset)];
assign i1 = (mytid<=3) ? `IRF1_EXU0[(25+irf_offset)] : `IRF1_EXU1[(25+irf_offset)];
assign i2 = (mytid<=3) ? `IRF1_EXU0[(26+irf_offset)] : `IRF1_EXU1[(26+irf_offset)];
assign i3 = (mytid<=3) ? `IRF1_EXU0[(27+irf_offset)] : `IRF1_EXU1[(27+irf_offset)];
assign i4 = (mytid<=3) ? `IRF1_EXU0[(28+irf_offset)] : `IRF1_EXU1[(28+irf_offset)];
assign i5 = (mytid<=3) ? `IRF1_EXU0[(29+irf_offset)] : `IRF1_EXU1[(29+irf_offset)];
assign i6 = (mytid<=3) ? `IRF1_EXU0[(30+irf_offset)] : `IRF1_EXU1[(30+irf_offset)];
assign i7 = (mytid<=3) ? `IRF1_EXU0[(31+irf_offset)] : `IRF1_EXU1[(31+irf_offset)];
//----------------------------------------------------------
assign frf_0 = `FRF1_EVEN[(mytid*32)+ 0];
assign frf_2 = `FRF1_EVEN[(mytid*32)+ 1];
assign frf_4 = `FRF1_EVEN[(mytid*32)+ 2];
assign frf_6 = `FRF1_EVEN[(mytid*32)+ 3];
assign frf_8 = `FRF1_EVEN[(mytid*32)+ 4];
assign frf_10 = `FRF1_EVEN[(mytid*32)+ 5];
assign frf_12 = `FRF1_EVEN[(mytid*32)+ 6];
assign frf_14 = `FRF1_EVEN[(mytid*32)+ 7];
assign frf_16 = `FRF1_EVEN[(mytid*32)+ 8];
assign frf_18 = `FRF1_EVEN[(mytid*32)+ 9];
assign frf_20 = `FRF1_EVEN[(mytid*32)+ 10];
assign frf_22 = `FRF1_EVEN[(mytid*32)+ 11];
assign frf_24 = `FRF1_EVEN[(mytid*32)+ 12];
assign frf_26 = `FRF1_EVEN[(mytid*32)+ 13];
assign frf_28 = `FRF1_EVEN[(mytid*32)+ 14];
assign frf_30 = `FRF1_EVEN[(mytid*32)+ 15];
assign frf_32 = `FRF1_EVEN[(mytid*32)+ 16];
assign frf_34 = `FRF1_EVEN[(mytid*32)+ 17];
assign frf_36 = `FRF1_EVEN[(mytid*32)+ 18];
assign frf_38 = `FRF1_EVEN[(mytid*32)+ 19];
assign frf_40 = `FRF1_EVEN[(mytid*32)+ 20];
assign frf_42 = `FRF1_EVEN[(mytid*32)+ 21];
assign frf_44 = `FRF1_EVEN[(mytid*32)+ 22];
assign frf_46 = `FRF1_EVEN[(mytid*32)+ 23];
assign frf_48 = `FRF1_EVEN[(mytid*32)+ 24];
assign frf_50 = `FRF1_EVEN[(mytid*32)+ 25];
assign frf_52 = `FRF1_EVEN[(mytid*32)+ 26];
assign frf_54 = `FRF1_EVEN[(mytid*32)+ 27];
assign frf_56 = `FRF1_EVEN[(mytid*32)+ 28];
assign frf_58 = `FRF1_EVEN[(mytid*32)+ 29];
assign frf_60 = `FRF1_EVEN[(mytid*32)+ 30];
assign frf_62 = `FRF1_EVEN[(mytid*32)+ 31];
assign frf_1 = `FRF1_ODD[(mytid*32)+ 0];
assign frf_3 = `FRF1_ODD[(mytid*32)+ 1];
assign frf_5 = `FRF1_ODD[(mytid*32)+ 2];
assign frf_7 = `FRF1_ODD[(mytid*32)+ 3];
assign frf_9 = `FRF1_ODD[(mytid*32)+ 4];
assign frf_11 = `FRF1_ODD[(mytid*32)+ 5];
assign frf_13 = `FRF1_ODD[(mytid*32)+ 6];
assign frf_15 = `FRF1_ODD[(mytid*32)+ 7];
assign frf_17 = `FRF1_ODD[(mytid*32)+ 8];
assign frf_19 = `FRF1_ODD[(mytid*32)+ 9];
assign frf_21 = `FRF1_ODD[(mytid*32)+ 10];
assign frf_23 = `FRF1_ODD[(mytid*32)+ 11];
assign frf_25 = `FRF1_ODD[(mytid*32)+ 12];
assign frf_27 = `FRF1_ODD[(mytid*32)+ 13];
assign frf_29 = `FRF1_ODD[(mytid*32)+ 14];
assign frf_31 = `FRF1_ODD[(mytid*32)+ 15];
assign frf_33 = `FRF1_ODD[(mytid*32)+ 16];
assign frf_35 = `FRF1_ODD[(mytid*32)+ 17];
assign frf_37 = `FRF1_ODD[(mytid*32)+ 18];
assign frf_39 = `FRF1_ODD[(mytid*32)+ 19];
assign frf_41 = `FRF1_ODD[(mytid*32)+ 20];
assign frf_43 = `FRF1_ODD[(mytid*32)+ 21];
assign frf_45 = `FRF1_ODD[(mytid*32)+ 22];
assign frf_47 = `FRF1_ODD[(mytid*32)+ 23];
assign frf_49 = `FRF1_ODD[(mytid*32)+ 24];
assign frf_51 = `FRF1_ODD[(mytid*32)+ 25];
assign frf_53 = `FRF1_ODD[(mytid*32)+ 26];
assign frf_55 = `FRF1_ODD[(mytid*32)+ 27];
assign frf_57 = `FRF1_ODD[(mytid*32)+ 28];
assign frf_59 = `FRF1_ODD[(mytid*32)+ 29];
assign frf_61 = `FRF1_ODD[(mytid*32)+ 30];
assign frf_63 = `FRF1_ODD[(mytid*32)+ 31];
//----------------------------------------------------------
assign delta_fx4_0 = delta_fx4[0];
assign delta_fx4_1 = delta_fx4[1];
assign delta_fx4_2 = delta_fx4[2];
assign delta_fx4_3 = delta_fx4[3];
assign delta_fx4_4 = delta_fx4[4];
assign delta_fx4_5 = delta_fx4[5];
assign delta_fx4_6 = delta_fx4[6];
assign delta_fx4_7 = delta_fx4[7];
assign delta_fx5_0 = delta_fx5[0];
assign delta_fx5_1 = delta_fx5[1];
assign delta_fx5_2 = delta_fx5[2];
assign delta_fx5_3 = delta_fx5[3];
assign delta_fx5_4 = delta_fx5[4];
assign delta_fx5_5 = delta_fx5[5];
assign delta_fx5_6 = delta_fx5[6];
assign delta_fx5_7 = delta_fx5[7];
assign delta_fb_0 = delta_fb[0];
assign delta_fb_1 = delta_fb[1];
assign delta_fb_2 = delta_fb[2];
assign delta_fb_3 = delta_fb[3];
assign delta_fb_4 = delta_fb[4];
assign delta_fb_5 = delta_fb[5];
assign delta_fb_6 = delta_fb[6];
assign delta_fb_7 = delta_fb[7];
assign delta_fw_0 = delta_fw[0];
assign delta_fw_1 = delta_fw[1];
assign delta_fw_2 = delta_fw[2];
assign delta_fw_3 = delta_fw[3];
assign delta_fw_4 = delta_fw[4];
assign delta_fw_5 = delta_fw[5];
assign delta_fw_6 = delta_fw[6];
assign delta_fw_7 = delta_fw[7];
assign delta_fw1_0 = delta_fw1[0];
assign delta_fw1_1 = delta_fw1[1];
assign delta_fw1_2 = delta_fw1[2];
assign delta_fw1_3 = delta_fw1[3];
assign delta_fw1_4 = delta_fw1[4];
assign delta_fw1_5 = delta_fw1[5];
assign delta_fw1_6 = delta_fw1[6];
assign delta_fw1_7 = delta_fw1[7];
assign delta_fw2_0 = delta_fw2[0];
assign delta_fw2_1 = delta_fw2[1];
assign delta_fw2_2 = delta_fw2[2];
assign delta_fw2_3 = delta_fw2[3];
assign delta_fw2_4 = delta_fw2[4];
assign delta_fw2_5 = delta_fw2[5];
assign delta_fw2_6 = delta_fw2[6];
assign delta_fw2_7 = delta_fw2[7];
assign delta_prev_0 = delta_prev[0];
assign delta_prev_1 = delta_prev[1];
assign delta_prev_2 = delta_prev[2];
assign delta_prev_3 = delta_prev[3];
assign delta_prev_4 = delta_prev[4];
assign delta_prev_5 = delta_prev[5];
assign delta_prev_6 = delta_prev[6];
assign delta_prev_7 = delta_prev[7];
//----------------------------------------------------------
//----------------------------------------------------------
assign mytnum = (mycid*8)+mytid;
assign mytg = mytid >> 2;
assign exu_complete = exu_valid & ~(`PROBES1.clkstop_d5|`TOP.in_reset|`SPC1.tcu_scan_en);
assign imul_complete = imul_valid & ~(`TOP.in_reset|`SPC1.tcu_scan_en);
assign idiv_complete = idiv_valid & ~(`TOP.in_reset|`SPC1.tcu_scan_en);
assign tlu_complete = tlu_complete_3 ;
assign fp_complete = fp_valid & ~(`TOP.in_reset|`SPC1.tcu_scan_en);
assign fdiv_complete = fdiv_valid & ~(`TOP.in_reset|`SPC1.tcu_scan_en);
assign lsu_complete = lsu_valid & ~(`TOP.in_reset|`SPC1.tcu_scan_en);
assign asi_complete = asi_valid & ~(`TOP.in_reset|`SPC1.tcu_scan_en);
assign complete_w = (exu_complete << `EXU_INDEX) |
(lsu_complete << `LSU_INDEX) |
(tlu_complete << `TLU_INDEX) |
(asi_complete << `ASI_INDEX) ;
assign oddwin = CWP_reg % 2;
assign frf_w1_valid_even = (frf_w1_tid_fw == mytid) & frf_w1_valid_fw[1];
assign frf_w1_valid_odd = (frf_w1_tid_fw == mytid) & frf_w1_valid_fw[0];
assign frf_w2_valid_even = (frf_w2_tid_fw == mytid) & frf_w2_valid_fw[1];
assign frf_w2_valid_odd = (frf_w2_tid_fw == mytid) & frf_w2_valid_fw[0];
assign frf_w1_skip_addr = frf_w1_addr_fw;
assign frf_w2_skip_addr = frf_w2_addr_fw;
// NOTE - ADD_TSB_CFG will never be used for Axis or Tharas
wire [63:0] ctxt_z_tsb_cfg0_reg = `PROBES1.ctxt_z_tsb_cfg0_reg[mytid];
wire [63:0] ctxt_z_tsb_cfg1_reg = `PROBES1.ctxt_z_tsb_cfg1_reg[mytid];
wire [63:0] ctxt_z_tsb_cfg2_reg = `PROBES1.ctxt_z_tsb_cfg2_reg[mytid];
wire [63:0] ctxt_z_tsb_cfg3_reg = `PROBES1.ctxt_z_tsb_cfg3_reg[mytid];
wire [63:0] ctxt_nz_tsb_cfg0_reg = `PROBES1.ctxt_nz_tsb_cfg0_reg[mytid];
wire [63:0] ctxt_nz_tsb_cfg1_reg = `PROBES1.ctxt_nz_tsb_cfg1_reg[mytid];
wire [63:0] ctxt_nz_tsb_cfg2_reg = `PROBES1.ctxt_nz_tsb_cfg2_reg[mytid];
wire [63:0] ctxt_nz_tsb_cfg3_reg = `PROBES1.ctxt_nz_tsb_cfg3_reg[mytid];
//----------------------------------------------------------
always @ (posedge `BENCH_SPC1_GCLK) begin // {
// TLU is async to the execution pipeline
// but needs to be delayed to allow CWP, etc to update and be stable
// before arch state is captured and diff_reg is called.
// FDIV was moved from fw1 to fw to allow FPRS to be stable before capture
tlu_complete_1 <= tlu_valid & ~(`TOP.in_reset|`SPC1.tcu_scan_en);
tlu_complete_2 <= tlu_complete_1;
tlu_complete_3 <= tlu_complete_2;
itagacc_fx5 <= I_TAG_ACC_reg; // Signal changes in W so need to pipeline to fw2
itagacc_fb <= itagacc_fx5;
itagacc_fw <= itagacc_fb;
itagacc_fw1 <= itagacc_fw;
itagacc_fw2 <= itagacc_fw1;
dtagacc_fx5 <= D_TAG_ACC_reg; // Signal changes in W so need to pipeline to fw2
dtagacc_fb <= dtagacc_fx5;
dtagacc_fw <= dtagacc_fb;
dtagacc_fw1 <= dtagacc_fw;
dtagacc_fw2 <= dtagacc_fw1;
dsfar_fb <= DSFAR_reg; // Signal changes in W+1 so need to pipeline to fw2
complete_fx4 <= complete_w;
complete_fx5 <= complete_fx4 ;
complete_fb <= complete_fx5 |
(idiv_complete << `IDIV_INDEX);
complete_fw <= complete_fb |
(fdiv_complete << `FDIV_INDEX) |
(imul_complete << `IMUL_INDEX);
complete_fw1 <= complete_fw |
(fp_complete << `FP_INDEX);
complete_fw2 <= complete_fw1;
frf_w1_valid_fw1 <= (frf_w1_valid_odd | frf_w1_valid_even) & fp_complete;
frf_w1_valid_fw2 <= frf_w1_valid_fw1;
frf_w1_skip_addr4_fw1 <= frf_w1_skip_addr[4];
frf_w1_skip_addr4_fw2 <= frf_w1_skip_addr4_fw1;
frf_w2_valid_fw <= frf_w2_valid_bn;
frf_w2_tid_fw <= frf_w2_tid;
frf_w2_addr_fw <= frf_w2_addr;
frf_w1_valid_fw <= frf_w1_valid;
frf_w1_tid_fw <= frf_w1_tid;
frf_w1_addr_fw <= frf_w1_addr;
if (~thread_running & `SPC1.tcu_core_running[mytid])
`TOP.th_last_act_cycle[mytnum] = `TOP.core_cycle_cnt;
thread_running <= `SPC1.tcu_core_running[mytid];
// Reset some register prev state on wmr negation
if (`SPC1.rst_wmr_protect && ~wmr)
wmr <= `SPC1.rst_wmr_protect;
if (`SPC1.rst_wmr_protect)
//----------------------------------------------------------
// Holding state for registers that may be updated asynchronously
// after synchronous update, but before capture/step. Also for reads,
// when register is read and modified before capture/step ..
// We capture the value /write time, and use that for sstep,
// ignoring any async updates, which are sent in the NEXT sstep ..
reg [63:0] asi_updated_int_rec;
reg asi_wr_int_rec_delay;
reg [16:0] asi_updated_softint;
reg asi_wr_softint_delay;
reg [16:0] asi_softint_wrdata;
always @(posedge `BENCH_SPC1_GCLK) begin // {
// Corner case : If async and sync wr occur in same clock, then the async
// update takes place. In this case we have to capture the
// value of the write WITHOUT async bit being set, so that
// we can sync with Riesling's sync write ..
asi_wr_int_rec_delay <= ( `SPC1.tlu.cth.asi_wr_int_rec[mytid] |
`SPC1.tlu.asi_rd_inc_vec_2[mytid]);
if (`SPC1.tlu.cth.asi_wr_int_rec[mytid] |
((`SPC1.tlu.asi.rd_inc_vec) &&
(`SPC1.tlu.asi.rd_tid_dec[mytid])) |
(`SPC1.tlu.asi_rd_int_rec &
`SPC1.tlu.cth.int_rec_mux_sel==mytid))
if (`SPC1.tlu.cth.asi_wr_int_rec[mytid])
asi_updated_int_rec <= `SPC1.tlu.cth.int_rec ;
else if ( (`SPC1.tlu.asi.rd_inc_vec) &&
(`SPC1.tlu.asi.rd_tid_dec[mytid]) )
if (`SPC1.tlu.cth.cxi_wr_int_dis[mytid]) begin
asi_updated_int_rec <= INTR_RECEIVE_reg & `SPC1.tlu.cth.int_rec_muxed_;
asi_updated_int_rec[`SPC1.tlu.cth.incoming_vector_in] <= 1'b0 ;
asi_updated_int_rec <= `SPC1.tlu.cth.int_rec_muxed ;
asi_updated_int_rec[`SPC1.tlu.cth.incoming_vector_in] <= 1'b0 ;
asi_updated_int_rec <= INTR_RECEIVE_reg;
asi_rdwr_int_rec <= 1'b1;
else if (complete_fw1 && !`NASTOP.sstep_early[mytnum])
asi_rdwr_int_rec <= 1'b0;
asi_wr_hintp_delay <= `SPC1.tlu.asi_wr_hintp[mytid];
if (`SPC1.tlu.asi_wr_hintp[mytid] |
`SPC1.tlu.asi_rd_hintp[mytid])
if (`SPC1.tlu.asi_wr_hintp[mytid])
asi_updated_hintp <= `SPC1.tlu.asi_wr_data_0[0] ;
asi_updated_hintp <= HINTP_reg;
else if (complete_fw1 && !`NASTOP.sstep_early[mytnum])
asi_wr_softint_delay <= (`SPC1.tlu.asi_wr_softint[mytid] |
`SPC1.tlu.asi_wr_clear_softint[mytid] |
`SPC1.tlu.asi_wr_set_softint[mytid]);
if (`SPC1.tlu.asi_wr_clear_softint[mytid])
asi_softint_wrdata <= ~`SPC1.tlu.asi_wr_data_0[16:0] & rd_SOFTINT_reg;
else if (`SPC1.tlu.asi_wr_set_softint[mytid])
asi_softint_wrdata <= `SPC1.tlu.asi_wr_data_0[16:0] | rd_SOFTINT_reg;
asi_softint_wrdata <= `SPC1.tlu.asi_wr_data_0[16:0];
if (asi_wr_softint_delay | `SPC1.tlu.asi_rd_softint[mytid])
if (asi_wr_softint_delay)
asi_updated_softint <= asi_softint_wrdata ;
asi_updated_softint <= rd_SOFTINT_reg ;
asi_rdwr_softint <= 1'b1;
else if (complete_fw1 && !`NASTOP.sstep_early[mytnum])
asi_rdwr_softint <= 1'b0;
//----------------------------------------------------------
// Negedge sampling to avoid race on specific signals ..
always @ (negedge `BENCH_SPC1_GCLK) begin // {
frf_w2_valid_bn <= frf_w2_valid;
//----------------------------------------------------------
// When instruction completes,
// Push differences to simics
always @ (posedge `BENCH_SPC1_GCLK) begin // {
if (`PARGS.th_check_enable[mytnum] && nas_pipe_enable && ~`SPC1.tcu_scan_en && ~`TOP.in_por) begin // {
// Update window registers
if (CWP_reg != `NASTOP.th_cwp[mytnum]) begin // {
copy_win (CWP_reg,`NASTOP.th_cwp[mytnum]);
`NASTOP.th_cwp[mytnum] = CWP_reg;
// Update global registers
// Wait for warm-reset flush related toggling to settle
if (GL_reg != th_gl) begin // {
if (`SPC1.spc_core_running_status[mytid] &
~`SPC1.rst_wmr_protect) begin // {
copy_global (GL_reg,th_gl);
// Check for bad signal values
// if NASTOP.sstep_sent[tid]=1,
// then SSTEP was set by another module (i.e. tlb_sync)
if (`PARGS.nas_check_on) begin // {
mytime = `TOP.core_cycle_cnt-1;
if (complete_fw2 && (`NASTOP.sstep_sent[mytnum]==1'b0)) begin // {
`PR_INFO ("pli_nas", `INFO, " C%0d T%0d PLI_SSTEP tid=%d pc=%h ts=%0d ",
mycid,mytid,mytnum,pc_fw2,mytime);
junk = $sim_send(`PLI_SSTEP, mytnum);
// Always clear sstep_early
// In case tlb_sync asserted it too late for complete_fw2
`NASTOP.sstep_early[mytnum] <= 1'b0;
else if (complete_fw2) begin // {
`NASTOP.sstep_sent[mytnum] <= 1'b0; // re-arm SSTEP
`NASTOP.sstep_early[mytnum] <= 1'b0;
`PR_INFO ("pli_nas", `INFO, " C%0d T%0d PLI_SSTEP tid=%d pc=%h ts=%0d (nas_pipe: skip sstep. rearm sstep. sstep_sent=0)",
mycid,mytid,mytnum,pc_fw2,mytime);
// Only capture if something completes and not first instruction
if (complete_fw2 && !first_op) begin // {
push_simics; // Use with AXIS to keep from getting timeout
// Pipeline runs continuously
// Other than when in POR ..
// Only save to delta_prev when something completes
`TOP.last_act_cycle = `TOP.core_cycle_cnt; //$time;
`TOP.th_last_act_cycle[mytnum] = `TOP.last_act_cycle;
// If something was captured but no instruction is in the pipeline
if ((delta_fw2[`NEXT_INDEX]!=`FIRST_INDEX) && (complete_fw2 == 0))
for (myindex=`FIRST_INDEX; myindex<delta_fw2[`NEXT_INDEX]; myindex=myindex+1)
print_entry (delta_fw2[myindex]);
`PR_ERROR ("nas",`ERROR, "T%0d Unexpected Reg change in DUT. Special case - no instruction retired.", mytnum);
// End detection for non-sas runs ..
for (junk=0;junk<`PARGS.bad_trap_count;junk=junk+1)
if (({16'b0,pc_fw2}&`PC_MASK) ===
(`PARGS.bad_trap_addr[junk]&`PC_MASK)) begin // {
// Disable nas_pipe processing (capture & SSTEP)
// to speed up simulation (minimize socket traffic,etc)
if (! `PARGS.nas_check_on) begin //{
`PR_ERROR ("nas",`ERROR, "T%0d reached Bad Trap", mytnum);
for (junk=0;junk<`PARGS.good_trap_count;junk=junk+1)
if ((|complete_fw2) && (({16'b0,pc_fw2}&`PC_MASK) ===
(`PARGS.good_trap_addr[junk]&`PC_MASK))) begin // {
// Disable nas_pipe processing (capture & SSTEP)
// to speed up simulation (minimize socket traffic,etc)
if (! `PARGS.nas_check_on) begin //{
good_trap_detected = 1'b1;
// Check Thread level timeout
(`TOP.core_cycle_cnt - `TOP.th_last_act_cycle[mytnum]) > `PARGS.th_timeout)
// Note: Do not change this message because regreport parses it for certain words.
`PR_ALWAYS ("nas",`ALWAYS, "ERROR: Thread T%0d No Activity for %0d Cycles - Thread TIMEOUT!",
mytnum, `PARGS.th_timeout);
junk = incErr(9999); // must exceed users max error setting to force exit.
end // if (`PARGS.th_check_enable[mytnum] && nas_pipe_enable ...)}
// Need to make sure Store Buffer is empty before turning off th_check_enable.
//global chkr requires to wait for all outstanding pending I
if ((! `PARGS.nas_check_on) &&
(good_trap_detected==1'b1) &&
(`TOP.nas_top.lsu_stb_empty[mytnum]) && `TOP.nas_top.ireq_pending[mytnum]) begin // {
`PARGS.th_check_enable[mytnum] = 1'b0;
`TOP.finished_tids[mytnum] = 1'b1;
good_trap_detected = 1'b0;
`PR_NORMAL ("nas", `NORMAL, "T%0d reached Good Trap. Disabling checking for thread %0d", mytnum,mytnum);
//----------------------------------------------------------
//----------------------------------------------------------
// Stage FX4 of delta pipeline
delta_fx4[`NEXT_INDEX] <= `FIRST_INDEX;
delta_fx4[`TIME_INDEX] <= 0;
delta_fx4[`PC_INDEX] <= {16'b0,PC_reg};
delta_fx4[`GL_INDEX] <= GL_reg;
delta_fx4[`CWP_INDEX] <= CWP_reg;
delta_fx4[`OPCODE_INDEX] <= opcode;
delta_fx4[`FIRST_INDEX] <= 77'hx;
//----------------------------------------------------------
// Stage FX5 of delta pipeline
index = delta_fx4[`NEXT_INDEX];
// Pipeline previous stage
for (i=0; i<=delta_fx4[`NEXT_INDEX]; i=i+1) begin // {
delta_fx5[i] <= delta_fx4[i];
if (complete_fx4) begin // LSU | EXU | TLU
push_delta_fx5 (`CCR+`CTL_OFFSET,CCR_reg,index);
if (complete_fx4[`LSU_INDEX] |
complete_fx4[`EXU_INDEX]) begin
if (mytid <= 3) begin // {
for (i=0; i<=31; i=i+1) begin // {
push_delta_fx5 (i,`IRF1_EXU0[(remap(i,oddwin)+irf_offset)],index);
for (i=0; i<=31; i=i+1) begin // {
push_delta_fx5 (i,`IRF1_EXU1[(remap(i,oddwin)+irf_offset)],index);
// Update FRF1 - Loads use W2 Port.
if (complete_fx4[`LSU_INDEX]) begin // {
// IF W1 port is also being written, ignore that address
for (i=0; i<=31; i=i+1) begin // {
if (!((i == frf_w1_skip_addr) && frf_w1_valid_even)) begin // {
frf_tmp = `FRF1_EVEN[(mytid*32)+i];
push_delta_fx5 (`FP_OFFSET + (i*2), frf_tmp[31:0], index);
if (!((i == frf_w1_skip_addr) && frf_w1_valid_odd)) begin // {
frf_tmp = `FRF1_ODD[(mytid*32)+i];
push_delta_fx5 (`FP_OFFSET + (i*2)+1, frf_tmp[31:0], index);
// Update ASR/ASI registers
if (complete_fx4) begin // {
push_delta_fx5 (`PSTATE + `CTL_OFFSET,PSTATE_reg,index);
push_delta_fx5 (`HPSTATE + `CTL_OFFSET,HPSTATE_reg,index);
push_delta_fx5 (`PIL + `CTL_OFFSET,PIL_reg,index);
push_delta_fx5 (`TBA + `CTL_OFFSET,{TBA_reg,15'b0},index);
push_delta_fx5 (`GL + `CTL_OFFSET,GL_reg,index);
push_delta_fx5 (`HTBA + `CTL_OFFSET,{HTBA_reg,14'b0},index);
push_delta_fx5 (`VER + `CTL_OFFSET,VER_reg,index);
push_delta_fx5 (`Y + `CTL_OFFSET,Y_reg,index);
push_delta_fx5 (`ASI + `CTL_OFFSET,ASI_reg,index);
push_delta_fx5 (`STICK_CMPR + `CTL_OFFSET,STICK_CMPR_wire,index);
push_delta_fx5 (`HSTICK_CMPR + `CTL_OFFSET,HSTICK_CMPR_wire,index);
push_delta_fx5 (`TICK_CMPR + `CTL_OFFSET,TICK_CMPR_wire,index);
push_delta_fx5 (`CWP + `CTL_OFFSET,CWP_reg,index);
push_delta_fx5 (`CANSAVE + `CTL_OFFSET,CANSAVE_reg,index);
push_delta_fx5 (`CANRESTORE + `CTL_OFFSET,CANRESTORE_reg,index);
push_delta_fx5 (`CLEANWIN + `CTL_OFFSET,CLEANWIN_reg,index);
push_delta_fx5 (`OTHERWIN + `CTL_OFFSET,OTHERWIN_reg,index);
push_delta_fx5 (`WSTATE + `CTL_OFFSET,WSTATE_reg,index);
push_delta_fx5 (`CTXT_PRIM_0+`CTL_OFFSET,CTXT_PRIM_0_reg,index);
push_delta_fx5 (`CTXT_SEC_0+`CTL_OFFSET,CTXT_SEC_0_reg,index);
push_delta_fx5 (`CTXT_PRIM_1+`CTL_OFFSET,CTXT_PRIM_1_reg,index);
push_delta_fx5 (`CTXT_SEC_1+`CTL_OFFSET,CTXT_SEC_1_reg,index);
push_delta_fx5 (`LSU_CONTROL+`CTL_OFFSET,LSU_CONTROL_reg,index);
push_delta_fx5 (`WATCHPOINT_ADDR+`CTL_OFFSET,WATCHPOINT_ADDR_reg,index);
// NOTE - ADD_TSB_CFG will never be used for Axis or Tharas
push_delta_fx5 (`CTXT_Z_TSB_CFG0+`CTL_OFFSET,ctxt_z_tsb_cfg0_reg,index);
push_delta_fx5 (`CTXT_Z_TSB_CFG1+`CTL_OFFSET,ctxt_z_tsb_cfg1_reg,index);
push_delta_fx5 (`CTXT_Z_TSB_CFG2+`CTL_OFFSET,ctxt_z_tsb_cfg2_reg,index);
push_delta_fx5 (`CTXT_Z_TSB_CFG3+`CTL_OFFSET,ctxt_z_tsb_cfg3_reg,index);
push_delta_fx5 (`CTXT_NZ_TSB_CFG0+`CTL_OFFSET,ctxt_nz_tsb_cfg0_reg,index);
push_delta_fx5 (`CTXT_NZ_TSB_CFG1+`CTL_OFFSET,ctxt_nz_tsb_cfg1_reg,index);
push_delta_fx5 (`CTXT_NZ_TSB_CFG2+`CTL_OFFSET,ctxt_nz_tsb_cfg2_reg,index);
push_delta_fx5 (`CTXT_NZ_TSB_CFG3+`CTL_OFFSET,ctxt_nz_tsb_cfg3_reg,index);
// Update GSR for all except write ASR in progess
if (!asi_in_progress) begin // {
push_delta_fx5 (`GSR + `CTL_OFFSET,GSR_wire, index);
// If lsu_complete & fp_complete assert at same time,
// then the fp_complete is the one that will modify the FSR
if (complete_fx4[`LSU_INDEX] & !complete_fw1[`FP_INDEX]) begin
push_delta_fx5 (`FSR+`CTL_OFFSET,FSR_wire,index);
// Non Trap updates of Trap stack & level
if (complete_fx4 && !complete_fx4[`TLU_INDEX]) begin // {
push_delta_fx5 (`TL + `CTL_OFFSET,TL_reg,index);
push_delta_fx5 (`TPC1 + `CTL_OFFSET, TPC1_wire, index);
push_delta_fx5 (`TPC2 + `CTL_OFFSET, TPC2_wire, index);
push_delta_fx5 (`TPC3 + `CTL_OFFSET, TPC3_wire, index);
push_delta_fx5 (`TPC4 + `CTL_OFFSET, TPC4_wire, index);
push_delta_fx5 (`TPC5 + `CTL_OFFSET, TPC5_wire, index);
push_delta_fx5 (`TPC6 + `CTL_OFFSET, TPC6_wire, index);
push_delta_fx5 (`TNPC1 + `CTL_OFFSET, TNPC1_wire, index);
push_delta_fx5 (`TNPC2 + `CTL_OFFSET, TNPC2_wire, index);
push_delta_fx5 (`TNPC3 + `CTL_OFFSET, TNPC3_wire, index);
push_delta_fx5 (`TNPC4 + `CTL_OFFSET, TNPC4_wire, index);
push_delta_fx5 (`TNPC5 + `CTL_OFFSET, TNPC5_wire, index);
push_delta_fx5 (`TNPC6 + `CTL_OFFSET, TNPC6_wire, index);
push_delta_fx5 (`TSTATE1 + `CTL_OFFSET, TSTATE1_wire, index);
push_delta_fx5 (`TSTATE2 + `CTL_OFFSET, TSTATE2_wire, index);
push_delta_fx5 (`TSTATE3 + `CTL_OFFSET, TSTATE3_wire, index);
push_delta_fx5 (`TSTATE4 + `CTL_OFFSET, TSTATE4_wire, index);
push_delta_fx5 (`TSTATE5 + `CTL_OFFSET, TSTATE5_wire, index);
push_delta_fx5 (`TSTATE6 + `CTL_OFFSET, TSTATE6_wire, index);
push_delta_fx5 (`HTSTATE1 + `CTL_OFFSET, HTSTATE1_wire, index);
push_delta_fx5 (`HTSTATE2 + `CTL_OFFSET, HTSTATE2_wire, index);
push_delta_fx5 (`HTSTATE3 + `CTL_OFFSET, HTSTATE3_wire, index);
push_delta_fx5 (`HTSTATE4 + `CTL_OFFSET, HTSTATE4_wire, index);
push_delta_fx5 (`HTSTATE5 + `CTL_OFFSET, HTSTATE5_wire, index);
push_delta_fx5 (`HTSTATE6 + `CTL_OFFSET, HTSTATE6_wire, index);
push_delta_fx5 (`TT1 + `CTL_OFFSET, TT1_wire, index);
push_delta_fx5 (`TT2 + `CTL_OFFSET, TT2_wire, index);
push_delta_fx5 (`TT3 + `CTL_OFFSET, TT3_wire, index);
push_delta_fx5 (`TT4 + `CTL_OFFSET, TT4_wire, index);
push_delta_fx5 (`TT5 + `CTL_OFFSET, TT5_wire, index);
push_delta_fx5 (`TT6 + `CTL_OFFSET, TT6_wire, index);
//----------------------------------------------------------
// Stage FB of delta pipeline
index = delta_fx5[`NEXT_INDEX];
// Pipeline previous stage
for (i=0; i<=delta_fx5[`NEXT_INDEX]; i=i+1) begin // {
delta_fb[i] <= delta_fx5[i];
if (complete_fx5[`ASI_INDEX]) begin // {
push_delta_fb (`GSR + `CTL_OFFSET,GSR_wire, index);
//----------------------------------------------------------
// Stage FW of delta pipeline
index = delta_fb[`NEXT_INDEX];
// Pipeline previous stage
for (i=0; i<=delta_fb[`NEXT_INDEX]; i=i+1) begin // {
delta_fw[i] <= delta_fb[i];
// Capture CWP_reg for SAVE/RESTORE
delta_fw[`CWP_INDEX] <= CWP_reg;
if (complete_fb[`TLU_INDEX]) begin
if (mytid <= 3) begin // {
for (i=0; i<=31; i=i+1) begin // {
push_delta_fw (i,`IRF1_EXU0[(remap(i,oddwin)+irf_offset)],index);
for (i=0; i<=31; i=i+1) begin // {
push_delta_fw (i,`IRF1_EXU1[(remap(i,oddwin)+irf_offset)],index);
// Update FRF1 - Idivs use W2.
if (complete_fb[`IDIV_INDEX]) begin // {
// IF W1 port is also being written, ignore that address
for (i=0; i<=31; i=i+1) begin // {
if (!((i == frf_w1_skip_addr) && frf_w1_valid_even)) begin // {
frf_tmp = `FRF1_EVEN[(mytid*32)+i];
push_delta_fw (`FP_OFFSET + (i*2), frf_tmp[31:0], index);
if (!((i == frf_w1_skip_addr) && frf_w1_valid_odd)) begin // {
frf_tmp = `FRF1_ODD[(mytid*32)+i];
push_delta_fw (`FP_OFFSET + (i*2)+1,frf_tmp[31:0], index);
//----------------------------------------------------------
// Stage FW1 of delta pipeline
index = delta_fw[`NEXT_INDEX];
// Pipeline previous stage
for (i=0; i<=delta_fw[`NEXT_INDEX]; i=i+1) begin // {
delta_fw1[i] <= delta_fw[i];
// Update FRF1 - FPops use W1 port.
if (fp_complete) begin // {
// IF W2 port is also being written, ignore that address
for (i=0; i<=31; i=i+1) begin // {
if (!((i == frf_w2_skip_addr) && frf_w2_valid_even)) begin // {
frf_tmp = `FRF1_EVEN[(mytid*32)+i];
push_delta_fw1 (`FP_OFFSET + (i*2), frf_tmp[31:0], index);
if (!((i == frf_w2_skip_addr) && frf_w2_valid_odd)) begin // {
frf_tmp = `FRF1_ODD[(mytid*32)+i];
push_delta_fw1 (`FP_OFFSET + (i*2)+1,frf_tmp[31:0], index);
if (complete_fw[`IMUL_INDEX]|complete_fw[`IDIV_INDEX]) begin
push_delta_fw1 (`CCR+`CTL_OFFSET,CCR_reg,index);
push_delta_fw1 (`Y+`CTL_OFFSET,Y_reg,index);
push_delta_fw1 (`CWP+`CTL_OFFSET,CWP_reg,index);
push_delta_fw1 (`CANSAVE+`CTL_OFFSET,CANSAVE_reg,index);
push_delta_fw1 (`CANRESTORE+`CTL_OFFSET,CANRESTORE_reg,index);
push_delta_fw1 (`CLEANWIN+`CTL_OFFSET,CLEANWIN_reg,index);
push_delta_fw1 (`OTHERWIN+`CTL_OFFSET,OTHERWIN_reg,index);
push_delta_fw1 (`WSTATE+`CTL_OFFSET,WSTATE_reg,index);
if (complete_fw[`TLU_INDEX]) begin // {
push_delta_fw1 (`TL + `CTL_OFFSET,TL_reg,index);
push_delta_fw1 (`TPC1 + `CTL_OFFSET, TPC1_wire, index);
push_delta_fw1 (`TPC2 + `CTL_OFFSET, TPC2_wire, index);
push_delta_fw1 (`TPC3 + `CTL_OFFSET, TPC3_wire, index);
push_delta_fw1 (`TPC4 + `CTL_OFFSET, TPC4_wire, index);
push_delta_fw1 (`TPC5 + `CTL_OFFSET, TPC5_wire, index);
push_delta_fw1 (`TPC6 + `CTL_OFFSET, TPC6_wire, index);
push_delta_fw1 (`TNPC1 + `CTL_OFFSET, TNPC1_wire, index);
push_delta_fw1 (`TNPC2 + `CTL_OFFSET, TNPC2_wire, index);
push_delta_fw1 (`TNPC3 + `CTL_OFFSET, TNPC3_wire, index);
push_delta_fw1 (`TNPC4 + `CTL_OFFSET, TNPC4_wire, index);
push_delta_fw1 (`TNPC5 + `CTL_OFFSET, TNPC5_wire, index);
push_delta_fw1 (`TNPC6 + `CTL_OFFSET, TNPC6_wire, index);
push_delta_fw1 (`TSTATE1 + `CTL_OFFSET, TSTATE1_wire, index);
push_delta_fw1 (`TSTATE2 + `CTL_OFFSET, TSTATE2_wire, index);
push_delta_fw1 (`TSTATE3 + `CTL_OFFSET, TSTATE3_wire, index);
push_delta_fw1 (`TSTATE4 + `CTL_OFFSET, TSTATE4_wire, index);
push_delta_fw1 (`TSTATE5 + `CTL_OFFSET, TSTATE5_wire, index);
push_delta_fw1 (`TSTATE6 + `CTL_OFFSET, TSTATE6_wire, index);
push_delta_fw1 (`HTSTATE1 + `CTL_OFFSET, HTSTATE1_wire, index);
push_delta_fw1 (`HTSTATE2 + `CTL_OFFSET, HTSTATE2_wire, index);
push_delta_fw1 (`HTSTATE3 + `CTL_OFFSET, HTSTATE3_wire, index);
push_delta_fw1 (`HTSTATE4 + `CTL_OFFSET, HTSTATE4_wire, index);
push_delta_fw1 (`HTSTATE5 + `CTL_OFFSET, HTSTATE5_wire, index);
push_delta_fw1 (`HTSTATE6 + `CTL_OFFSET, HTSTATE6_wire, index);
push_delta_fw1 (`TT1 + `CTL_OFFSET, TT1_wire, index);
push_delta_fw1 (`TT2 + `CTL_OFFSET, TT2_wire, index);
push_delta_fw1 (`TT3 + `CTL_OFFSET, TT3_wire, index);
push_delta_fw1 (`TT4 + `CTL_OFFSET, TT4_wire, index);
push_delta_fw1 (`TT5 + `CTL_OFFSET, TT5_wire, index);
push_delta_fw1 (`TT6 + `CTL_OFFSET, TT6_wire, index);
//----------------------------------------------------------
// Stage FW2 of delta pipeline
index = delta_fw1[`NEXT_INDEX];
// Pipeline previous stage
for (i=0; i<=delta_fw1[`NEXT_INDEX]; i=i+1) begin // {
delta_fw2[i] <= delta_fw1[i];
delta_fw2[`TIME_INDEX] <= $time;
// Update Registers that may change asynchronously
// If sstep was already sent by another module,
// don't capture until the next sstep
if (complete_fw1 && !`NASTOP.sstep_early[mytnum]) begin // {
if ((complete_fw1[`ASI_INDEX]|complete_fw1[`LSU_INDEX]) & asi_rdwr_hintp)
push_delta_fw2 (`HINTP + `CTL_OFFSET,asi_updated_hintp,index);
push_delta_fw2 (`HINTP + `CTL_OFFSET,HINTP_reg,index);
if ((complete_fw1[`ASI_INDEX]|complete_fw1[`LSU_INDEX]) & asi_rdwr_softint)
push_delta_fw2 (`SOFTINT + `CTL_OFFSET,asi_updated_softint,index);
push_delta_fw2 (`SOFTINT + `CTL_OFFSET,rd_SOFTINT_reg,index);
if (complete_fw1[`IMUL_INDEX] |
complete_fw1[`IDIV_INDEX]) begin // {
if (mytid <= 3) begin // {
for (i=0; i<=31; i=i+1) begin // {
push_delta_fw2 (i,`IRF1_EXU0[(remap(i,oddwin)+irf_offset)],index);
for (i=0; i<=31; i=i+1) begin // {
push_delta_fw2 (i,`IRF1_EXU1[(remap(i,oddwin)+irf_offset)],index);
// Update FRF1 - fdivs and Imuls use W2 port
if (complete_fw1[`IMUL_INDEX] |
complete_fw1[`FDIV_INDEX] ) begin // {
// IF W1 port is also being written, ignore that address
for (i=0; i<=31; i=i+1) begin // {
if (!((i == frf_w1_skip_addr) && frf_w1_valid_even)) begin // {
frf_tmp = `FRF1_EVEN[(mytid*32)+i];
push_delta_fw2 (`FP_OFFSET + (i*2), frf_tmp[31:0], index);
if (!((i == frf_w1_skip_addr) && frf_w1_valid_odd)) begin // {
frf_tmp = `FRF1_ODD[(mytid*32)+i];
push_delta_fw2 (`FP_OFFSET + (i*2)+1,frf_tmp[31:0], index);
if (complete_fw1[`FP_INDEX] |
complete_fw1[`TLU_INDEX] |
complete_fw1[`FDIV_INDEX]) begin
push_delta_fw2 (`FSR+`CTL_OFFSET,FSR_wire,index);
push_delta_fw2 (`I_TAG_ACC+`CTL_OFFSET,itagacc_fw2,index);
push_delta_fw2 (`D_TAG_ACC+`CTL_OFFSET,dtagacc_fw2,index);
push_delta_fw2 (`DSFAR+`CTL_OFFSET,dsfar_fw2,index);
//----------------------------------------------------------
// Stage FW2 of delta pipeline - for signals that change FW+2 !!
index = delta_fw2[`NEXT_INDEX];
// Since FPRS for FPops may have been corrupted by o-o-o loads:
// If fprs_fw2 is != fprs_reg & there are loads in the pipeline
// then assume loads have already updated fprs.
// In that case, create our own fprs_reg by using the valids and
// skip_addr and copy of fprs for this op..
if (complete_fw2[`FP_INDEX] && frf_w1_valid_fw2) begin // {
// o-o-o load has changed fprs already - use dummy
if ((fprs_fw2 != FPRS_reg) && (complete_fw1[`LSU_INDEX] |
complete_fw[`LSU_INDEX] | complete_fb[`LSU_INDEX] |
complete_fx5[`LSU_INDEX] )) begin // {
dummy_fprs = read_prev(`FPRS + `CTL_OFFSET);
dummy_fprs = dummy_fprs |
{1'b0, frf_w1_skip_addr4_fw2, ~frf_w1_skip_addr4_fw2};
push_delta_fw2_async (`FPRS + `CTL_OFFSET,dummy_fprs,index);
// o-o-o load has NOT changed fprs already - use it
push_delta_fw2_async (`FPRS + `CTL_OFFSET,FPRS_reg,index);
// Load FPRS for loads/reads as prev|fprs_fb ..
// since loads may only 'set' bits, not clear ...
else if (complete_fw2[`LSU_INDEX]) begin // {
dummy_fprs = read_prev(`FPRS + `CTL_OFFSET);
dummy_fprs = dummy_fprs | fprs_fw1;
push_delta_fw2_async (`FPRS +`CTL_OFFSET,dummy_fprs,index);
// Load FPRS for store ASI or FDIV
// FDIV can update FPRS on w1 or w2,
// but the pipe is stalled behind it so no o-o-o loads.
else if ((complete_fw2[`ASI_INDEX]) ||
(complete_fw2[`FDIV_INDEX])) begin // {
push_delta_fw2_async (`FPRS + `CTL_OFFSET,FPRS_reg,index);
//----------------------------------------------------------
// Store latest values into delta
index = delta_prev[`NEXT_INDEX];
if (in_wmr & ~`SPC1.rst_wmr_protect) begin // {
push_delta_prev_async ( `PC+`CTL_OFFSET,{16'b0,pc_fw2|1},index);
push_delta_prev_async ( `PC+`CTL_OFFSET,{16'b0,pc_fw2},index);
//----------------------------------------------------------
//----------------------------------------------------------
// Compare with current state and capture if different
if (act_value != read_prev(id)) begin // { // Diff vs prev
calc_cwp(CWP_reg,id,win,type); // special case for 1st stage
write_prev(id,act_value);
delta_fx4[next] <= {type,win,id,act_value};
delta_fx4[next] <= 77'hx;
delta_fx4[`NEXT_INDEX] <= next;
if (`PARGS.axis_debug_on) begin
$display("AXIS: T%0d pc=%h id=%0d type=%0h win=%0h value=%h ts=%0d",
mytnum,PC_reg,id,type,win,act_value,$time);
if (`PARGS.axis_debug_on) begin
$display("AXIS: T%0d pc=%h id=%0d type=%0h win=%0h value=%h ts=%0d",
mytnum,PC_reg,id,type,win,act_value,$time);
//----------------------------------------------------------
// Compare with current state and capture if different
if (act_value != read_prev(id)) begin // { // Diff vs prev
calc_cwp(delta_fx4[`CWP_INDEX],id,win,type);
write_prev(id,act_value);
delta_fx5[next] <= {type,win,id,act_value};
delta_fx5[next] <= 77'hx;
delta_fx5[`NEXT_INDEX] <= next;
if (`PARGS.axis_debug_on) begin
$display("AXIS: T%0d pc=%h id=%0d type=%0h win=%0h value=%h ts=%0d",
mytnum,pc_fx4,id,type,win,act_value,$time);
calc_cwp(cwp_fx4,id,win,type);
if (`PARGS.axis_debug_on) begin
$display("AXIS: T%0d pc=%h id=%0d type=%0h win=%0h value=%h ts=%0d",
mytnum,pc_fx4,id,type,win,act_value,$time);
//----------------------------------------------------------
// Compare with current state and capture if different
if (act_value != read_prev(id)) begin // { // Diff vs prev
calc_cwp(delta_fx5[`CWP_INDEX],id,win,type);
write_prev(id,act_value);
delta_fb[next] <= {type,win,id,act_value};
delta_fb[`NEXT_INDEX] <= next;
if (`PARGS.axis_debug_on) begin
$display("AXIS: T%0d pc=%h id=%0d type=%0h win=%0h value=%h ts=%0d",
mytnum,pc_fx5,id,type,win,act_value,$time);
calc_cwp(cwp_fx5,id,win,type);
if (`PARGS.axis_debug_on) begin
$display("AXIS: T%0d pc=%h id=%0d type=%0h win=%0h value=%h ts=%0d",
mytnum,pc_fx5,id,type,win,act_value,$time);
//----------------------------------------------------------
// Compare with current state and capture if different
if (act_value != read_prev(id)) begin // { // Diff vs prev
calc_cwp(delta_fb[`CWP_INDEX],id,win,type);
write_prev(id,act_value);
delta_fw[next] <= {type,win,id,act_value};
delta_fw[`NEXT_INDEX] <= next;
if (`PARGS.axis_debug_on) begin
$display("AXIS: T%0d pc=%h id=%0d type=%0h win=%0h value=%h ts=%0d",
mytnum,pc_fb,id,type,win,act_value,$time);
calc_cwp(cwp_fb[`CWP_INDEX],id,win,type);
if (`PARGS.axis_debug_on) begin
$display("AXIS: T%0d pc=%h id=%0d type=%0h win=%0h value=%h ts=%0d",
mytnum,pc_fb,id,type,win,act_value,$time);
//----------------------------------------------------------
// Compare with current state and capture if different
if (act_value != read_prev(id)) begin // { // Diff vs prev
calc_cwp(delta_fw[`CWP_INDEX],id,win,type);
write_prev(id,act_value);
delta_fw1[next] <= {type,win,id,act_value};
delta_fw1[next] <= 77'hx;
delta_fw1[`NEXT_INDEX] <= next;
if (`PARGS.axis_debug_on) begin
$display("AXIS: T%0d pc=%h id=%0d type=%0h win=%0h value=%h ts=%0d",
mytnum,pc_fw,id,type,win,act_value,$time);
calc_cwp(cwp_fw,id,win,type);
if (`PARGS.axis_debug_on) begin
$display("AXIS: T%0d pc=%h id=%0d type=%0h win=%0h value=%h ts=%0d",
mytnum,pc_fw,id,type,win,act_value,$time);
//----------------------------------------------------------
// Compare with current state and capture if different
if (act_value != read_prev(id)) begin // { // Diff vs prev
calc_cwp(delta_fw1[`CWP_INDEX],id,win,type);
write_prev(id,act_value);
delta_fw2[next] <= {type,win,id,act_value};
delta_fw2[next] <= 77'hx;
delta_fw2[`NEXT_INDEX] <= next;
if (`PARGS.axis_debug_on) begin
$display("AXIS: T%0d pc=%h id=%0d type=%0h win=%0h value=%h ts=%0d",
mytnum,pc_fw1,id,type,win,act_value,$time);
calc_cwp(cwp_fw1,id,win,type);
if (`PARGS.axis_debug_on) begin
$display("AXIS: T%0d pc=%h id=%0d type=%0h win=%0h value=%h ts=%0d",
mytnum,pc_fw1,id,type,win,act_value,$time);
//----------------------------------------------------------
// Compare with current state and capture if different
// This is for late changing registers
// Use blocking assignments.
task push_delta_fw2_async;
if (act_value != read_prev(id)) begin // { // Diff vs prev
calc_cwp(delta_fw2[`CWP_INDEX],id,win,type);
write_prev_async(id,act_value);
delta_fw2[next] = {type,win,id,act_value};
delta_fw2[`NEXT_INDEX] = next;
if (`PARGS.axis_debug_on) begin
$display("AXIS: T%0d pc=%h id=%0d type=%0h win=%0h value=%h ts=%0d",
mytnum,pc_fw1,id,type,win,act_value,$time);
calc_cwp(cwp_fw2,id,win,type);
if (`PARGS.axis_debug_on) begin
$display("AXIS: T%0d pc=%h id=%0d type=%0h win=%0h value=%h ts=%0d",
mytnum,pc_fw1,id,type,win,act_value,$time);
//----------------------------------------------------------
// Compare with current state and capture if different
// Use blocking assignments so that push_simics will work
task push_delta_prev_async;
if (act_value != read_prev(id)) begin // { // Diff vs prev
calc_cwp(delta_prev[`CWP_INDEX],id,win,type);
write_prev_async(id,act_value);
delta_prev[next] = {type,win,id,act_value};
delta_prev[next] = 77'hx;
delta_prev[`NEXT_INDEX] = next;
if (`PARGS.axis_debug_on) begin
$display("AXIS: T%0d pc=%h id=%0d type=%0h win=%0h value=%h ts=%0d",
mytnum,pc_last,id,type,win,act_value,$time);
if (`PARGS.axis_debug_on) begin
calc_cwp(cwp_last,id,win,type);
$display("AXIS: T%0d pc=%h id=%0d type=%0h win=%0h value=%h ts=%0d",
mytnum,pc_last,id,type,win,act_value,$time);
//----------------------------------------------------------
// prev of delta pipeline
// Pipeline previous stage
for (i=0; i<=delta_fw2[`NEXT_INDEX]; i=i+1) begin // {
delta_prev[i] <= delta_fw2[i];
//----------------------------------------------------------
//----------------------------------------------------------
// Sort delta list in register ID order, then push to simics
// Or print deltas if sas check disabled ..
// Order of registers reported to simics must be:
// Global 0-7 aka prev_reg[0:7]
// Window 8-23 aka prev_reg[8:23]
// Floating 0-63 aka prev_reg[200:263]
// Control 32-143 aka prev_reg[32:143]
act_level = delta_prev[`GL_INDEX]; // GL
time_fw2 = delta_prev[`TIME_INDEX]; // Finish time
for (i=`FIRST_INDEX; i<delta_prev[`NEXT_INDEX]; i=i+1) begin // {
{type,win,regnum,value} = delta_prev[i];
if (regnum<=7) begin // {
if (`PARGS.nas_check_on) begin // {
`ACT_STATUS = $queue(`ACT_QUEUE, `PUSH_Q, mytnum, time_fw2, act_type,
act_level, regnum, value);
else if (`PARGS.show_delta_on) begin // {
`NASTOP.print_delta (mytnum,act_type,win,regnum,value);
else if (regnum<=23) begin // { %o0-%l7, %l0-%l7
if (`PARGS.nas_check_on) begin // {
`ACT_STATUS = $queue(`ACT_QUEUE, `PUSH_Q, mytnum, time_fw2, act_type,
else if (`PARGS.show_delta_on) begin // {
`NASTOP.print_delta (mytnum,act_type,win,regnum,value);
else if (regnum<=31) begin // { %i0-%i7
if (`PARGS.nas_check_on) begin // {
`ACT_STATUS = $queue(`ACT_QUEUE, `PUSH_Q, mytnum, time_fw2, act_type,
win, (regnum-16), value);
else if (`PARGS.show_delta_on) begin // {
`NASTOP.print_delta (mytnum,act_type,win,(regnum-16),value);
else if (regnum<=(64+`FP_OFFSET)) begin // {
if (`PARGS.nas_check_on) begin // {
`ACT_STATUS = $queue(`ACT_QUEUE, `PUSH_Q, mytnum, time_fw2, act_type,
(regnum-`FP_OFFSET), value);
else if (`PARGS.show_delta_on) begin // {
`NASTOP.print_delta (mytnum,act_type,win,(regnum-`FP_OFFSET),value);
else if ((regnum>=(32+`CTL_OFFSET))&(regnum<=(143+`CTL_OFFSET))) begin // {
if (`PARGS.nas_check_on) begin // {
`ACT_STATUS = $queue(`ACT_QUEUE, `PUSH_Q, mytnum, time_fw2, act_type,
(regnum-`CTL_OFFSET), value);
else if (`PARGS.show_delta_on) begin // {
`NASTOP.print_delta (mytnum,act_type,win,(regnum-`CTL_OFFSET),value);
`PR_ERROR ("nas", `ERROR, " - T%0d Bench problem. push_simics has bad regnum", mytnum);
value = delta_prev[`OPCODE_INDEX];
if (`PARGS.nas_check_on) begin // {
`ACT_STATUS = $queue(`ACT_QUEUE, `PUSH_Q, mytnum, time_fw2, act_type,
else if (`PARGS.show_delta_on) begin // {
`NASTOP.print_delta (mytnum,act_type,win,regnum,value);
// Push End of Instruction Delimiter
// The value field for this PUSH equals the PC for this instruction.
// so that printing to the logfile works correctly.
// prev_reg[`PC] = current instruction PC
// delta_reg[`PC] = PC at end of current instruction
pc = delta_prev[`PC_INDEX];
if (`PARGS.nas_check_on) begin // {
`ACT_STATUS = $queue(`ACT_QUEUE, `PUSH_Q, mytnum, time_fw2, act_type,
delta_fw2[`CWP_INDEX], `END_INSTR, pc);
else if (`PARGS.show_delta_on) begin // {
`NASTOP.print_delta (mytnum,act_type,delta_fw2[`CWP_INDEX],`END_INSTR,0);
if (! `PARGS.nas_check_on) begin // {
`PR_NORMAL ("nas", `NORMAL, "@%0d T%0d %h (Unchecked..)",
$time, mytnum, {16'b0,pc});
`TOP.last_act_cycle = `TOP.core_cycle_cnt; //$time;
`TOP.th_last_act_cycle[mytnum] = `TOP.last_act_cycle;
if (! `PARGS.nas_check_on) begin // {
`TOP.last_act_cycle = `TOP.core_cycle_cnt; //$time;
`TOP.th_last_act_cycle[mytnum] = `TOP.last_act_cycle;
//----------------------------------------------------------
// Save current window to previous window, then copy new window to current window
// Save current window to Old window
// Copy New window to current window
//----------------------------------------------------------
// Save current global to previous global, then copy new global to current global
// Save current global to Old global
// Copy New global current global
//----------------------------------------------------------
// Return window number and register type based on cwp and regnum as input
else if (id<=23) begin // {
else if (id<=31) begin // {
else if (id<=(64+`FP_OFFSET)) begin // {
//----------------------------------------------------------
// Check for bad signal values
8'b10000000: ; // good value
`PR_ERROR ("nas", `ERROR, " - T%0d More than one instruction retired in a single cycle for this thread.",
$write("\t\t\t\t Instructions - ");
if (complete_fw2[`EXU_INDEX]) $write("EXU op, ");
if (complete_fw2[`FP_INDEX]) $write("FP op, ");
if (complete_fw2[`LSU_INDEX]) $write("LSU op, ");
if (complete_fw2[`IMUL_INDEX]) $write("IMUL op, ");
if (complete_fw2[`IDIV_INDEX]) $write("IDIV op, ");
if (complete_fw2[`FDIV_INDEX]) $write("FDIV op, ");
if (complete_fw2[`TLU_INDEX]) $write("TLU op, ");
if (complete_fw2[`ASI_INDEX]) $write("ASI op, ");
$write(" complete_fw2 = %b \n",complete_fw2);
// This check only works if diags are written properly.
// For example, if a diag writes to one of these registers using wrpr,
// then this check must be disabled using plusarg.
// CANSAVE + CANRESTORE + OTHERWIN = NWINDOWS-2 (per Sparc V9)
if (`PARGS.win_check_on) begin // {
if (complete_fw2 & ((CANSAVE_reg + CANRESTORE_reg + OTHERWIN_reg) != 6)) begin // {
`PR_ERROR ("nas", `ERROR, "ERROR - T%0d Bad Values for window registers.", mytnum);
`PR_ERROR ("nas", `ERROR, "- CANSAVE = %0d CANRESTORE = %0d OTHERWIN = %0d",
CANSAVE_reg, CANRESTORE_reg,OTHERWIN_reg);
//----------------------------------------------------------
//----------------------------------------------------------
reg [`DELTA_WIDTH:0] temp1, temp2;
last = delta_prev[`NEXT_INDEX]-1;
for (i=`FIRST_INDEX; i <= last; i=i+1) begin // {
for (j=`FIRST_INDEX; j < last; j=j+1) begin // {
temp1 = delta_prev[j]; temp2 = delta_prev[j+1];
if (temp1[76:64] > temp2[76:64]) begin // {
delta_prev[j] = temp2; delta_prev [j+1] = temp1;
//----------------------------------------------------------
//----------------------------------------------------------
// Print one entry in delta_* array
input [`DELTA_WIDTH:0] delta_entry;
reg [(20*8)-1:0] type_str;
reg [(20*8)-1:0] regname;
{type,win,id,act_value} = delta_entry;
`NASTOP.get_regname(mytnum,type_str,win,id,regname);
`PR_NORMAL ("nas", `NORMAL, "type=%0s win=%0d RegID=%0d %0s=%h",
type_str,win,id,regname,act_value);
//----------------------------------------------------------
// Write Value to prev_reg using id as index (non-blocking)
8'd0: prev_reg0 <= value;
8'd1: prev_reg1 <= value;
8'd2: prev_reg2 <= value;
8'd3: prev_reg3 <= value;
8'd4: prev_reg4 <= value;
8'd5: prev_reg5 <= value;
8'd6: prev_reg6 <= value;
8'd7: prev_reg7 <= value;
8'd8: prev_reg8 <= value;
8'd9: prev_reg9 <= value;
8'd10: prev_reg10 <= value;
8'd11: prev_reg11 <= value;
8'd12: prev_reg12 <= value;
8'd13: prev_reg13 <= value;
8'd14: prev_reg14 <= value;
8'd15: prev_reg15 <= value;
8'd16: prev_reg16 <= value;
8'd17: prev_reg17 <= value;
8'd18: prev_reg18 <= value;
8'd19: prev_reg19 <= value;
8'd20: prev_reg20 <= value;
8'd21: prev_reg21 <= value;
8'd22: prev_reg22 <= value;
8'd23: prev_reg23 <= value;
8'd24: prev_reg24 <= value;
8'd25: prev_reg25 <= value;
8'd26: prev_reg26 <= value;
8'd27: prev_reg27 <= value;
8'd28: prev_reg28 <= value;
8'd29: prev_reg29 <= value;
8'd30: prev_reg30 <= value;
8'd31: prev_reg31 <= value;
8'd32: prev_reg32 <= value;
8'd33: prev_reg33 <= value;
8'd34: prev_reg34 <= value;
8'd35: prev_reg35 <= value;
8'd36: prev_reg36 <= value;
8'd37: prev_reg37 <= value;
8'd38: prev_reg38 <= value;
8'd39: prev_reg39 <= value;
8'd40: prev_reg40 <= value;
8'd41: prev_reg41 <= value;
8'd42: prev_reg42 <= value;
8'd43: prev_reg43 <= value;
8'd44: prev_reg44 <= value;
8'd45: prev_reg45 <= value;
8'd46: prev_reg46 <= value;
8'd47: prev_reg47 <= value;
8'd48: prev_reg48 <= value;
8'd49: prev_reg49 <= value;
8'd50: prev_reg50 <= value;
8'd51: prev_reg51 <= value;
8'd52: prev_reg52 <= value;
8'd53: prev_reg53 <= value;
8'd54: prev_reg54 <= value;
8'd55: prev_reg55 <= value;
8'd56: prev_reg56 <= value;
8'd57: prev_reg57 <= value;
8'd58: prev_reg58 <= value;
8'd59: prev_reg59 <= value;
8'd60: prev_reg60 <= value;
8'd61: prev_reg61 <= value;
8'd62: prev_reg62 <= value;
8'd63: prev_reg63 <= value;
8'd64: prev_reg64 <= value;
8'd65: prev_reg65 <= value;
8'd66: prev_reg66 <= value;
8'd67: prev_reg67 <= value;
8'd68: prev_reg68 <= value;
8'd69: prev_reg69 <= value;
8'd70: prev_reg70 <= value;
8'd71: prev_reg71 <= value;
8'd72: prev_reg72 <= value;
8'd73: prev_reg73 <= value;
8'd74: prev_reg74 <= value;
8'd75: prev_reg75 <= value;
8'd76: prev_reg76 <= value;
8'd77: prev_reg77 <= value;
8'd78: prev_reg78 <= value;
8'd79: prev_reg79 <= value;
8'd80: prev_reg80 <= value;
8'd81: prev_reg81 <= value;
8'd82: prev_reg82 <= value;
8'd83: prev_reg83 <= value;
8'd84: prev_reg84 <= value;
8'd85: prev_reg85 <= value;
8'd86: prev_reg86 <= value;
8'd87: prev_reg87 <= value;
8'd88: prev_reg88 <= value;
8'd89: prev_reg89 <= value;
8'd90: prev_reg90 <= value;
8'd91: prev_reg91 <= value;
8'd92: prev_reg92 <= value;
8'd93: prev_reg93 <= value;
8'd94: prev_reg94 <= value;
8'd95: prev_reg95 <= value;
8'd96: prev_reg96 <= value;
8'd97: prev_reg97 <= value;
8'd98: prev_reg98 <= value;
8'd99: prev_reg99 <= value;
8'd100: prev_reg100 <= value;
8'd101: prev_reg101 <= value;
8'd102: prev_reg102 <= value;
8'd103: prev_reg103 <= value;
8'd104: prev_reg104 <= value;
8'd105: prev_reg105 <= value;
8'd106: prev_reg106 <= value;
8'd107: prev_reg107 <= value;
8'd108: prev_reg108 <= value;
8'd109: prev_reg109 <= value;
8'd110: prev_reg110 <= value;
8'd111: prev_reg111 <= value;
8'd112: prev_reg112 <= value;
8'd113: prev_reg113 <= value;
8'd114: prev_reg114 <= value;
8'd115: prev_reg115 <= value;
8'd116: prev_reg116 <= value;
8'd117: prev_reg117 <= value;
8'd118: prev_reg118 <= value;
8'd119: prev_reg119 <= value;
8'd120: prev_reg120 <= value;
8'd121: prev_reg121 <= value;
8'd122: prev_reg122 <= value;
8'd123: prev_reg123 <= value;
8'd124: prev_reg124 <= value;
8'd125: prev_reg125 <= value;
8'd126: prev_reg126 <= value;
8'd127: prev_reg127 <= value;
8'd128: prev_reg128 <= value;
8'd129: prev_reg129 <= value;
8'd130: prev_reg130 <= value;
8'd131: prev_reg131 <= value;
8'd132: prev_reg132 <= value;
8'd133: prev_reg133 <= value;
8'd134: prev_reg134 <= value;
8'd135: prev_reg135 <= value;
8'd136: prev_reg136 <= value;
8'd137: prev_reg137 <= value;
8'd138: prev_reg138 <= value;
8'd139: prev_reg139 <= value;
8'd140: prev_reg140 <= value;
8'd141: prev_reg141 <= value;
8'd142: prev_reg142 <= value;
8'd143: prev_reg143 <= value;
8'd144: prev_reg144 <= value;
8'd145: prev_reg145 <= value;
8'd146: prev_reg146 <= value;
8'd147: prev_reg147 <= value;
8'd148: prev_reg148 <= value;
8'd149: prev_reg149 <= value;
8'd150: prev_reg150 <= value;
8'd151: prev_reg151 <= value;
8'd152: prev_reg152 <= value;
8'd153: prev_reg153 <= value;
8'd154: prev_reg154 <= value;
8'd155: prev_reg155 <= value;
8'd156: prev_reg156 <= value;
8'd157: prev_reg157 <= value;
8'd158: prev_reg158 <= value;
8'd159: prev_reg159 <= value;
8'd160: prev_reg160 <= value;
8'd161: prev_reg161 <= value;
8'd162: prev_reg162 <= value;
8'd163: prev_reg163 <= value;
8'd164: prev_reg164 <= value;
8'd165: prev_reg165 <= value;
8'd166: prev_reg166 <= value;
8'd167: prev_reg167 <= value;
8'd168: prev_reg168 <= value;
8'd169: prev_reg169 <= value;
8'd170: prev_reg170 <= value;
8'd171: prev_reg171 <= value;
8'd172: prev_reg172 <= value;
8'd173: prev_reg173 <= value;
8'd174: prev_reg174 <= value;
8'd175: prev_reg175 <= value;
8'd176: prev_reg176 <= value;
8'd177: prev_reg177 <= value;
8'd178: prev_reg178 <= value;
8'd179: prev_reg179 <= value;
8'd180: prev_reg180 <= value;
8'd181: prev_reg181 <= value;
8'd182: prev_reg182 <= value;
8'd183: prev_reg183 <= value;
8'd184: prev_reg184 <= value;
8'd185: prev_reg185 <= value;
8'd186: prev_reg186 <= value;
8'd187: prev_reg187 <= value;
8'd188: prev_reg188 <= value;
8'd189: prev_reg189 <= value;
8'd190: prev_reg190 <= value;
8'd191: prev_reg191 <= value;
8'd192: prev_reg192 <= value;
8'd193: prev_reg193 <= value;
8'd194: prev_reg194 <= value;
8'd195: prev_reg195 <= value;
8'd196: prev_reg196 <= value;
8'd197: prev_reg197 <= value;
8'd198: prev_reg198 <= value;
8'd199: prev_reg199 <= value;
8'd200: prev_reg200 <= value;
8'd201: prev_reg201 <= value;
8'd202: prev_reg202 <= value;
8'd203: prev_reg203 <= value;
8'd204: prev_reg204 <= value;
8'd205: prev_reg205 <= value;
8'd206: prev_reg206 <= value;
8'd207: prev_reg207 <= value;
8'd208: prev_reg208 <= value;
8'd209: prev_reg209 <= value;
8'd210: prev_reg210 <= value;
8'd211: prev_reg211 <= value;
8'd212: prev_reg212 <= value;
8'd213: prev_reg213 <= value;
8'd214: prev_reg214 <= value;
8'd215: prev_reg215 <= value;
8'd216: prev_reg216 <= value;
8'd217: prev_reg217 <= value;
8'd218: prev_reg218 <= value;
8'd219: prev_reg219 <= value;
8'd220: prev_reg220 <= value;
8'd221: prev_reg221 <= value;
8'd222: prev_reg222 <= value;
8'd223: prev_reg223 <= value;
8'd224: prev_reg224 <= value;
8'd225: prev_reg225 <= value;
8'd226: prev_reg226 <= value;
8'd227: prev_reg227 <= value;
8'd228: prev_reg228 <= value;
8'd229: prev_reg229 <= value;
8'd230: prev_reg230 <= value;
8'd231: prev_reg231 <= value;
8'd232: prev_reg232 <= value;
8'd233: prev_reg233 <= value;
8'd234: prev_reg234 <= value;
8'd235: prev_reg235 <= value;
8'd236: prev_reg236 <= value;
8'd237: prev_reg237 <= value;
8'd238: prev_reg238 <= value;
8'd239: prev_reg239 <= value;
8'd240: prev_reg240 <= value;
8'd241: prev_reg241 <= value;
8'd242: prev_reg242 <= value;
8'd243: prev_reg243 <= value;
8'd244: prev_reg244 <= value;
8'd245: prev_reg245 <= value;
8'd246: prev_reg246 <= value;
8'd247: prev_reg247 <= value;
8'd248: prev_reg248 <= value;
8'd249: prev_reg249 <= value;
8'd250: prev_reg250 <= value;
8'd251: prev_reg251 <= value;
8'd252: prev_reg252 <= value;
8'd253: prev_reg253 <= value;
8'd254: prev_reg254 <= value;
8'd255: prev_reg255 <= value;
//----------------------------------------------------------
// Write Value to prev_reg using id as index (blocking)
8'd10: prev_reg10 = value;
8'd11: prev_reg11 = value;
8'd12: prev_reg12 = value;
8'd13: prev_reg13 = value;
8'd14: prev_reg14 = value;
8'd15: prev_reg15 = value;
8'd16: prev_reg16 = value;
8'd17: prev_reg17 = value;
8'd18: prev_reg18 = value;
8'd19: prev_reg19 = value;
8'd20: prev_reg20 = value;
8'd21: prev_reg21 = value;
8'd22: prev_reg22 = value;
8'd23: prev_reg23 = value;
8'd24: prev_reg24 = value;
8'd25: prev_reg25 = value;
8'd26: prev_reg26 = value;
8'd27: prev_reg27 = value;
8'd28: prev_reg28 = value;
8'd29: prev_reg29 = value;
8'd30: prev_reg30 = value;
8'd31: prev_reg31 = value;
8'd32: prev_reg32 = value;
8'd33: prev_reg33 = value;
8'd34: prev_reg34 = value;
8'd35: prev_reg35 = value;
8'd36: prev_reg36 = value;
8'd37: prev_reg37 = value;
8'd38: prev_reg38 = value;
8'd39: prev_reg39 = value;
8'd40: prev_reg40 = value;
8'd41: prev_reg41 = value;
8'd42: prev_reg42 = value;
8'd43: prev_reg43 = value;
8'd44: prev_reg44 = value;
8'd45: prev_reg45 = value;
8'd46: prev_reg46 = value;
8'd47: prev_reg47 = value;
8'd48: prev_reg48 = value;
8'd49: prev_reg49 = value;
8'd50: prev_reg50 = value;
8'd51: prev_reg51 = value;
8'd52: prev_reg52 = value;
8'd53: prev_reg53 = value;
8'd54: prev_reg54 = value;
8'd55: prev_reg55 = value;
8'd56: prev_reg56 = value;
8'd57: prev_reg57 = value;
8'd58: prev_reg58 = value;
8'd59: prev_reg59 = value;
8'd60: prev_reg60 = value;
8'd61: prev_reg61 = value;
8'd62: prev_reg62 = value;
8'd63: prev_reg63 = value;
8'd64: prev_reg64 = value;
8'd65: prev_reg65 = value;
8'd66: prev_reg66 = value;
8'd67: prev_reg67 = value;
8'd68: prev_reg68 = value;
8'd69: prev_reg69 = value;
8'd70: prev_reg70 = value;
8'd71: prev_reg71 = value;
8'd72: prev_reg72 = value;
8'd73: prev_reg73 = value;
8'd74: prev_reg74 = value;
8'd75: prev_reg75 = value;
8'd76: prev_reg76 = value;
8'd77: prev_reg77 = value;
8'd78: prev_reg78 = value;
8'd79: prev_reg79 = value;
8'd80: prev_reg80 = value;
8'd81: prev_reg81 = value;
8'd82: prev_reg82 = value;
8'd83: prev_reg83 = value;
8'd84: prev_reg84 = value;
8'd85: prev_reg85 = value;
8'd86: prev_reg86 = value;
8'd87: prev_reg87 = value;
8'd88: prev_reg88 = value;
8'd89: prev_reg89 = value;
8'd90: prev_reg90 = value;
8'd91: prev_reg91 = value;
8'd92: prev_reg92 = value;
8'd93: prev_reg93 = value;
8'd94: prev_reg94 = value;
8'd95: prev_reg95 = value;
8'd96: prev_reg96 = value;
8'd97: prev_reg97 = value;
8'd98: prev_reg98 = value;
8'd99: prev_reg99 = value;
8'd100: prev_reg100 = value;
8'd101: prev_reg101 = value;
8'd102: prev_reg102 = value;
8'd103: prev_reg103 = value;
8'd104: prev_reg104 = value;
8'd105: prev_reg105 = value;
8'd106: prev_reg106 = value;
8'd107: prev_reg107 = value;
8'd108: prev_reg108 = value;
8'd109: prev_reg109 = value;
8'd110: prev_reg110 = value;
8'd111: prev_reg111 = value;
8'd112: prev_reg112 = value;
8'd113: prev_reg113 = value;
8'd114: prev_reg114 = value;
8'd115: prev_reg115 = value;
8'd116: prev_reg116 = value;
8'd117: prev_reg117 = value;
8'd118: prev_reg118 = value;
8'd119: prev_reg119 = value;
8'd120: prev_reg120 = value;
8'd121: prev_reg121 = value;
8'd122: prev_reg122 = value;
8'd123: prev_reg123 = value;
8'd124: prev_reg124 = value;
8'd125: prev_reg125 = value;
8'd126: prev_reg126 = value;
8'd127: prev_reg127 = value;
8'd128: prev_reg128 = value;
8'd129: prev_reg129 = value;
8'd130: prev_reg130 = value;
8'd131: prev_reg131 = value;
8'd132: prev_reg132 = value;
8'd133: prev_reg133 = value;
8'd134: prev_reg134 = value;
8'd135: prev_reg135 = value;
8'd136: prev_reg136 = value;
8'd137: prev_reg137 = value;
8'd138: prev_reg138 = value;
8'd139: prev_reg139 = value;
8'd140: prev_reg140 = value;
8'd141: prev_reg141 = value;
8'd142: prev_reg142 = value;
8'd143: prev_reg143 = value;
8'd144: prev_reg144 = value;
8'd145: prev_reg145 = value;
8'd146: prev_reg146 = value;
8'd147: prev_reg147 = value;
8'd148: prev_reg148 = value;
8'd149: prev_reg149 = value;
8'd150: prev_reg150 = value;
8'd151: prev_reg151 = value;
8'd152: prev_reg152 = value;
8'd153: prev_reg153 = value;
8'd154: prev_reg154 = value;
8'd155: prev_reg155 = value;
8'd156: prev_reg156 = value;
8'd157: prev_reg157 = value;
8'd158: prev_reg158 = value;
8'd159: prev_reg159 = value;
8'd160: prev_reg160 = value;
8'd161: prev_reg161 = value;
8'd162: prev_reg162 = value;
8'd163: prev_reg163 = value;
8'd164: prev_reg164 = value;
8'd165: prev_reg165 = value;
8'd166: prev_reg166 = value;
8'd167: prev_reg167 = value;
8'd168: prev_reg168 = value;
8'd169: prev_reg169 = value;
8'd170: prev_reg170 = value;
8'd171: prev_reg171 = value;
8'd172: prev_reg172 = value;
8'd173: prev_reg173 = value;
8'd174: prev_reg174 = value;
8'd175: prev_reg175 = value;
8'd176: prev_reg176 = value;
8'd177: prev_reg177 = value;
8'd178: prev_reg178 = value;
8'd179: prev_reg179 = value;
8'd180: prev_reg180 = value;
8'd181: prev_reg181 = value;
8'd182: prev_reg182 = value;
8'd183: prev_reg183 = value;
8'd184: prev_reg184 = value;
8'd185: prev_reg185 = value;
8'd186: prev_reg186 = value;
8'd187: prev_reg187 = value;
8'd188: prev_reg188 = value;
8'd189: prev_reg189 = value;
8'd190: prev_reg190 = value;
8'd191: prev_reg191 = value;
8'd192: prev_reg192 = value;
8'd193: prev_reg193 = value;
8'd194: prev_reg194 = value;
8'd195: prev_reg195 = value;
8'd196: prev_reg196 = value;
8'd197: prev_reg197 = value;
8'd198: prev_reg198 = value;
8'd199: prev_reg199 = value;
8'd200: prev_reg200 = value;
8'd201: prev_reg201 = value;
8'd202: prev_reg202 = value;
8'd203: prev_reg203 = value;
8'd204: prev_reg204 = value;
8'd205: prev_reg205 = value;
8'd206: prev_reg206 = value;
8'd207: prev_reg207 = value;
8'd208: prev_reg208 = value;
8'd209: prev_reg209 = value;
8'd210: prev_reg210 = value;
8'd211: prev_reg211 = value;
8'd212: prev_reg212 = value;
8'd213: prev_reg213 = value;
8'd214: prev_reg214 = value;
8'd215: prev_reg215 = value;
8'd216: prev_reg216 = value;
8'd217: prev_reg217 = value;
8'd218: prev_reg218 = value;
8'd219: prev_reg219 = value;
8'd220: prev_reg220 = value;
8'd221: prev_reg221 = value;
8'd222: prev_reg222 = value;
8'd223: prev_reg223 = value;
8'd224: prev_reg224 = value;
8'd225: prev_reg225 = value;
8'd226: prev_reg226 = value;
8'd227: prev_reg227 = value;
8'd228: prev_reg228 = value;
8'd229: prev_reg229 = value;
8'd230: prev_reg230 = value;
8'd231: prev_reg231 = value;
8'd232: prev_reg232 = value;
8'd233: prev_reg233 = value;
8'd234: prev_reg234 = value;
8'd235: prev_reg235 = value;
8'd236: prev_reg236 = value;
8'd237: prev_reg237 = value;
8'd238: prev_reg238 = value;
8'd239: prev_reg239 = value;
8'd240: prev_reg240 = value;
8'd241: prev_reg241 = value;
8'd242: prev_reg242 = value;
8'd243: prev_reg243 = value;
8'd244: prev_reg244 = value;
8'd245: prev_reg245 = value;
8'd246: prev_reg246 = value;
8'd247: prev_reg247 = value;
8'd248: prev_reg248 = value;
8'd249: prev_reg249 = value;
8'd250: prev_reg250 = value;
8'd251: prev_reg251 = value;
8'd252: prev_reg252 = value;
8'd253: prev_reg253 = value;
8'd254: prev_reg254 = value;
8'd255: prev_reg255 = value;
//----------------------------------------------------------
// Read value frpm prev_reg using id as index
function [63:0] read_prev;
8'd0: read_prev = prev_reg0;
8'd1: read_prev = prev_reg1;
8'd2: read_prev = prev_reg2;
8'd3: read_prev = prev_reg3;
8'd4: read_prev = prev_reg4;
8'd5: read_prev = prev_reg5;
8'd6: read_prev = prev_reg6;
8'd7: read_prev = prev_reg7;
8'd8: read_prev = prev_reg8;
8'd9: read_prev = prev_reg9;
8'd10: read_prev = prev_reg10;
8'd11: read_prev = prev_reg11;
8'd12: read_prev = prev_reg12;
8'd13: read_prev = prev_reg13;
8'd14: read_prev = prev_reg14;
8'd15: read_prev = prev_reg15;
8'd16: read_prev = prev_reg16;
8'd17: read_prev = prev_reg17;
8'd18: read_prev = prev_reg18;
8'd19: read_prev = prev_reg19;
8'd20: read_prev = prev_reg20;
8'd21: read_prev = prev_reg21;
8'd22: read_prev = prev_reg22;
8'd23: read_prev = prev_reg23;
8'd24: read_prev = prev_reg24;
8'd25: read_prev = prev_reg25;
8'd26: read_prev = prev_reg26;
8'd27: read_prev = prev_reg27;
8'd28: read_prev = prev_reg28;
8'd29: read_prev = prev_reg29;
8'd30: read_prev = prev_reg30;
8'd31: read_prev = prev_reg31;
8'd32: read_prev = prev_reg32;
8'd33: read_prev = prev_reg33;
8'd34: read_prev = prev_reg34;
8'd35: read_prev = prev_reg35;
8'd36: read_prev = prev_reg36;
8'd37: read_prev = prev_reg37;
8'd38: read_prev = prev_reg38;
8'd39: read_prev = prev_reg39;
8'd40: read_prev = prev_reg40;
8'd41: read_prev = prev_reg41;
8'd42: read_prev = prev_reg42;
8'd43: read_prev = prev_reg43;
8'd44: read_prev = prev_reg44;
8'd45: read_prev = prev_reg45;
8'd46: read_prev = prev_reg46;
8'd47: read_prev = prev_reg47;
8'd48: read_prev = prev_reg48;
8'd49: read_prev = prev_reg49;
8'd50: read_prev = prev_reg50;
8'd51: read_prev = prev_reg51;
8'd52: read_prev = prev_reg52;
8'd53: read_prev = prev_reg53;
8'd54: read_prev = prev_reg54;
8'd55: read_prev = prev_reg55;
8'd56: read_prev = prev_reg56;
8'd57: read_prev = prev_reg57;
8'd58: read_prev = prev_reg58;
8'd59: read_prev = prev_reg59;
8'd60: read_prev = prev_reg60;
8'd61: read_prev = prev_reg61;
8'd62: read_prev = prev_reg62;
8'd63: read_prev = prev_reg63;
8'd64: read_prev = prev_reg64;
8'd65: read_prev = prev_reg65;
8'd66: read_prev = prev_reg66;
8'd67: read_prev = prev_reg67;
8'd68: read_prev = prev_reg68;
8'd69: read_prev = prev_reg69;
8'd70: read_prev = prev_reg70;
8'd71: read_prev = prev_reg71;
8'd72: read_prev = prev_reg72;
8'd73: read_prev = prev_reg73;
8'd74: read_prev = prev_reg74;
8'd75: read_prev = prev_reg75;
8'd76: read_prev = prev_reg76;
8'd77: read_prev = prev_reg77;
8'd78: read_prev = prev_reg78;
8'd79: read_prev = prev_reg79;
8'd80: read_prev = prev_reg80;
8'd81: read_prev = prev_reg81;
8'd82: read_prev = prev_reg82;
8'd83: read_prev = prev_reg83;
8'd84: read_prev = prev_reg84;
8'd85: read_prev = prev_reg85;
8'd86: read_prev = prev_reg86;
8'd87: read_prev = prev_reg87;
8'd88: read_prev = prev_reg88;
8'd89: read_prev = prev_reg89;
8'd90: read_prev = prev_reg90;
8'd91: read_prev = prev_reg91;
8'd92: read_prev = prev_reg92;
8'd93: read_prev = prev_reg93;
8'd94: read_prev = prev_reg94;
8'd95: read_prev = prev_reg95;
8'd96: read_prev = prev_reg96;
8'd97: read_prev = prev_reg97;
8'd98: read_prev = prev_reg98;
8'd99: read_prev = prev_reg99;
8'd100: read_prev = prev_reg100;
8'd101: read_prev = prev_reg101;
8'd102: read_prev = prev_reg102;
8'd103: read_prev = prev_reg103;
8'd104: read_prev = prev_reg104;
8'd105: read_prev = prev_reg105;
8'd106: read_prev = prev_reg106;
8'd107: read_prev = prev_reg107;
8'd108: read_prev = prev_reg108;
8'd109: read_prev = prev_reg109;
8'd110: read_prev = prev_reg110;
8'd111: read_prev = prev_reg111;
8'd112: read_prev = prev_reg112;
8'd113: read_prev = prev_reg113;
8'd114: read_prev = prev_reg114;
8'd115: read_prev = prev_reg115;
8'd116: read_prev = prev_reg116;
8'd117: read_prev = prev_reg117;
8'd118: read_prev = prev_reg118;
8'd119: read_prev = prev_reg119;
8'd120: read_prev = prev_reg120;
8'd121: read_prev = prev_reg121;
8'd122: read_prev = prev_reg122;
8'd123: read_prev = prev_reg123;
8'd124: read_prev = prev_reg124;
8'd125: read_prev = prev_reg125;
8'd126: read_prev = prev_reg126;
8'd127: read_prev = prev_reg127;
8'd128: read_prev = prev_reg128;
8'd129: read_prev = prev_reg129;
8'd130: read_prev = prev_reg130;
8'd131: read_prev = prev_reg131;
8'd132: read_prev = prev_reg132;
8'd133: read_prev = prev_reg133;
8'd134: read_prev = prev_reg134;
8'd135: read_prev = prev_reg135;
8'd136: read_prev = prev_reg136;
8'd137: read_prev = prev_reg137;
8'd138: read_prev = prev_reg138;
8'd139: read_prev = prev_reg139;
8'd140: read_prev = prev_reg140;
8'd141: read_prev = prev_reg141;
8'd142: read_prev = prev_reg142;
8'd143: read_prev = prev_reg143;
8'd144: read_prev = prev_reg144;
8'd145: read_prev = prev_reg145;
8'd146: read_prev = prev_reg146;
8'd147: read_prev = prev_reg147;
8'd148: read_prev = prev_reg148;
8'd149: read_prev = prev_reg149;
8'd150: read_prev = prev_reg150;
8'd151: read_prev = prev_reg151;
8'd152: read_prev = prev_reg152;
8'd153: read_prev = prev_reg153;
8'd154: read_prev = prev_reg154;
8'd155: read_prev = prev_reg155;
8'd156: read_prev = prev_reg156;
8'd157: read_prev = prev_reg157;
8'd158: read_prev = prev_reg158;
8'd159: read_prev = prev_reg159;
8'd160: read_prev = prev_reg160;
8'd161: read_prev = prev_reg161;
8'd162: read_prev = prev_reg162;
8'd163: read_prev = prev_reg163;
8'd164: read_prev = prev_reg164;
8'd165: read_prev = prev_reg165;
8'd166: read_prev = prev_reg166;
8'd167: read_prev = prev_reg167;
8'd168: read_prev = prev_reg168;
8'd169: read_prev = prev_reg169;
8'd170: read_prev = prev_reg170;
8'd171: read_prev = prev_reg171;
8'd172: read_prev = prev_reg172;
8'd173: read_prev = prev_reg173;
8'd174: read_prev = prev_reg174;
8'd175: read_prev = prev_reg175;
8'd176: read_prev = prev_reg176;
8'd177: read_prev = prev_reg177;
8'd178: read_prev = prev_reg178;
8'd179: read_prev = prev_reg179;
8'd180: read_prev = prev_reg180;
8'd181: read_prev = prev_reg181;
8'd182: read_prev = prev_reg182;
8'd183: read_prev = prev_reg183;
8'd184: read_prev = prev_reg184;
8'd185: read_prev = prev_reg185;
8'd186: read_prev = prev_reg186;
8'd187: read_prev = prev_reg187;
8'd188: read_prev = prev_reg188;
8'd189: read_prev = prev_reg189;
8'd190: read_prev = prev_reg190;
8'd191: read_prev = prev_reg191;
8'd192: read_prev = prev_reg192;
8'd193: read_prev = prev_reg193;
8'd194: read_prev = prev_reg194;
8'd195: read_prev = prev_reg195;
8'd196: read_prev = prev_reg196;
8'd197: read_prev = prev_reg197;
8'd198: read_prev = prev_reg198;
8'd199: read_prev = prev_reg199;
8'd200: read_prev = prev_reg200;
8'd201: read_prev = prev_reg201;
8'd202: read_prev = prev_reg202;
8'd203: read_prev = prev_reg203;
8'd204: read_prev = prev_reg204;
8'd205: read_prev = prev_reg205;
8'd206: read_prev = prev_reg206;
8'd207: read_prev = prev_reg207;
8'd208: read_prev = prev_reg208;
8'd209: read_prev = prev_reg209;
8'd210: read_prev = prev_reg210;
8'd211: read_prev = prev_reg211;
8'd212: read_prev = prev_reg212;
8'd213: read_prev = prev_reg213;
8'd214: read_prev = prev_reg214;
8'd215: read_prev = prev_reg215;
8'd216: read_prev = prev_reg216;
8'd217: read_prev = prev_reg217;
8'd218: read_prev = prev_reg218;
8'd219: read_prev = prev_reg219;
8'd220: read_prev = prev_reg220;
8'd221: read_prev = prev_reg221;
8'd222: read_prev = prev_reg222;
8'd223: read_prev = prev_reg223;
8'd224: read_prev = prev_reg224;
8'd225: read_prev = prev_reg225;
8'd226: read_prev = prev_reg226;
8'd227: read_prev = prev_reg227;
8'd228: read_prev = prev_reg228;
8'd229: read_prev = prev_reg229;
8'd230: read_prev = prev_reg230;
8'd231: read_prev = prev_reg231;
8'd232: read_prev = prev_reg232;
8'd233: read_prev = prev_reg233;
8'd234: read_prev = prev_reg234;
8'd235: read_prev = prev_reg235;
8'd236: read_prev = prev_reg236;
8'd237: read_prev = prev_reg237;
8'd238: read_prev = prev_reg238;
8'd239: read_prev = prev_reg239;
8'd240: read_prev = prev_reg240;
8'd241: read_prev = prev_reg241;
8'd242: read_prev = prev_reg242;
8'd243: read_prev = prev_reg243;
8'd244: read_prev = prev_reg244;
8'd245: read_prev = prev_reg245;
8'd246: read_prev = prev_reg246;
8'd247: read_prev = prev_reg247;
8'd248: read_prev = prev_reg248;
8'd249: read_prev = prev_reg249;
8'd250: read_prev = prev_reg250;
8'd251: read_prev = prev_reg251;
8'd252: read_prev = prev_reg252;
8'd253: read_prev = prev_reg253;
8'd254: read_prev = prev_reg254;
8'd255: read_prev = prev_reg255;
//----------------------------------------------------------
remap[4] = rd[4] ^ (rd[3] & oddwin);
//----------------------------------------------------------
// Initialize nas_pipe registers
initial begin : INIT_BLOCK
nas_pipe_enable = 1'b1; // Nas_pipe always enables itself
good_trap_detected = 1'b0;
@ (posedge `BENCH_SPC1_GCLK);
`TOP.th_last_act_cycle[mytnum] = 0;
`PR_INFO ("nas", `INFO, "T%0d Init shadow registers.",mytnum);
// POR for control registers
write_prev(`FPRS +`CTL_OFFSET,3'h4);
write_prev(`CLEANWIN +`CTL_OFFSET,3'h7);
write_prev(`CANSAVE +`CTL_OFFSET,3'h6);
write_prev(`FPRS+`CTL_OFFSET,3'h4);
// POR for PSTATE = 0x14 (PEF, PRIV = 1)
write_prev(`PSTATE + `CTL_OFFSET,'h14);
// POR for HPSTATE = 0x4034 (RED, HPRIV = 1)
write_prev(`HPSTATE + `CTL_OFFSET,'h24);
// POR for TL = = 0x6 [MAXTL]
write_prev(`TL + `CTL_OFFSET,'h6);
write_prev(`TT6 + `CTL_OFFSET,'h1);
// POR for GL = MAXGL = 3
write_prev(`GL + `CTL_OFFSET,`POR_GL);
// POR for VER = {003e, 0024, 01, 0036, 07}
write_prev(`VER + `CTL_OFFSET,{32'h003e0024,VER_reg[31:24],24'h030607});
// POR for *_cmpr registers is INT_DIS = 1
write_prev(`TICK_CMPR + `CTL_OFFSET,64'h8000000000000000);
write_prev(`STICK_CMPR + `CTL_OFFSET,64'h8000000000000000);
write_prev(`HSTICK_CMPR + `CTL_OFFSET,64'h8000000000000000);
// Need to define so that 1st instruction will print correctly
write_prev(`PC+`CTL_OFFSET,`POR_PC);
delta_prev[`PC_INDEX] = `BAD_PC;
irf_offset = (mytid%4)*32;
//----------------------------------------------------------
// For WMR, we will set to 0x0, so that initial deltas
// WMR for PSTATE = 0x14 (PEF, PRIV = 1)
// write_prev(`PSTATE + `CTL_OFFSET,'h00);
// WMR for HPSTATE = 0x4034 (RED, HPRIV = 1)
// write_prev(`HPSTATE + `CTL_OFFSET,'h00);
// WMR for TL = = 0x6 [MAXTL]
// write_prev(`TL + `CTL_OFFSET,'h0);
// write_prev(`TT6 + `CTL_OFFSET,'h1);
// WMR for GL = MAXGL = 3
// write_prev(`GL + `CTL_OFFSET,0);
//----------------------------------------------------------
// For POR, we will set to 0x0, so that initial deltas
// and prev state are all consistent with DUT. No values
`PR_ALWAYS ("arg", `ALWAYS,"T%0d Resetting Nas Pipe states for POR ..",mytnum);
delta_fx4[`NEXT_INDEX] <= `FIRST_INDEX;
delta_fx4[`FIRST_INDEX] <= 77'hx;
delta_fx5[`NEXT_INDEX] <= `FIRST_INDEX;
delta_fb[`NEXT_INDEX] <= `FIRST_INDEX;
delta_fw[`NEXT_INDEX] <= `FIRST_INDEX;
delta_fw1[`NEXT_INDEX] <= `FIRST_INDEX;
delta_fw2[`NEXT_INDEX] <= `FIRST_INDEX;
`PR_INFO ("nas", `INFO, "T%0d Init shadow registers.",mytnum);
// POR for control registers
write_prev(`FPRS +`CTL_OFFSET,3'h4);
write_prev(`CLEANWIN +`CTL_OFFSET,3'h7);
write_prev(`CANSAVE +`CTL_OFFSET,3'h6);
write_prev(`FPRS+`CTL_OFFSET,3'h4);
// POR for PSTATE = 0x14 (PEF, PRIV = 1)
write_prev(`PSTATE + `CTL_OFFSET,'h14);
// POR for HPSTATE = 0x4034 (RED, HPRIV = 1)
write_prev(`HPSTATE + `CTL_OFFSET,'h24);
// POR for TL = = 0x6 [MAXTL]
write_prev(`TL + `CTL_OFFSET,'h6);
write_prev(`TT6 + `CTL_OFFSET,'h1);
// POR for GL = MAXGL = 3
write_prev(`GL + `CTL_OFFSET,`POR_GL);
// POR for VER = {003e, 0024, 01, 0036, 07}
write_prev(`VER + `CTL_OFFSET,64'h003e002410030607);
// POR for *_cmpr registers is INT_DIS = 1
write_prev(`TICK_CMPR + `CTL_OFFSET,64'h8000000000000000);
write_prev(`STICK_CMPR + `CTL_OFFSET,64'h8000000000000000);
write_prev(`HSTICK_CMPR + `CTL_OFFSET,64'h8000000000000000);
// Need to define so that 1st instruction will print correctly
write_prev(`PC+`CTL_OFFSET,`POR_PC);
//----------------------------------------------------------
//----------------------------------------------------------
// Watch for Good/Bad trap
wire [5:0] mytnum = (mycid*8)+mytid;
// Delimiter changes whether flat or hierarchical netlist
wire myclk = tb_top.cpu.spc1.gclk;
wire dec_inst_valid_m = mytg ? tb_top.cpu.spc1.dec_inst_valid_m[1] : tb_top.cpu.spc1.dec_inst_valid_m[0];
wire [1:0] dec_tid_m = mytg ? tb_top.cpu.spc1.dec_tid1_m : tb_top.cpu.spc1.dec_tid0_m;
wire dec_flush_b = mytg ? tb_top.cpu.spc1.dec_flush_b[1] : tb_top.cpu.spc1.dec_flush_b[0];
wire tlu_flush_ifu = tb_top.cpu.spc1.tlu_flush_ifu[mytid];
wire [47:0] pc_d = mytg ? {tb_top.cpu.spc1.tlu_pc_1_d[47:2],2'b0} : {tb_top.cpu.spc1.tlu_pc_0_d[47:2],2'b0};
wire [31:0] op_d = mytg ? tb_top.cpu.spc1.dec_inst1_d[31:0] : tb_top.cpu.spc1.dec_inst0_d[31:0];
wire myclk = tb_top.cpu.spc1.gclk;
wire dec_inst_valid_m = mytg ? tb_top.cpu.spc1.dec_inst_valid_m[1] : tb_top.cpu.spc1.dec_inst_valid_m[0];
wire [1:0] dec_tid_m = mytg ? tb_top.cpu.spc1.dec_tid1_m : tb_top.cpu.spc1.dec_tid0_m;
wire dec_flush_b = mytg ? tb_top.cpu.spc1.dec_flush_b[1] : tb_top.cpu.spc1.dec_flush_b[0];
wire tlu_flush_ifu = tb_top.cpu.spc1.tlu_flush_ifu[mytid];
wire [47:0] pc_d = mytg ? {tb_top.cpu.spc1.tlu_pc_1_d[47:2],2'b0} : {tb_top.cpu.spc1.tlu_pc_0_d[47:2],2'b0};
wire [31:0] op_d = mytg ? tb_top.cpu.spc1.dec_inst1_d[31:0] : tb_top.cpu.spc1.dec_inst0_d[31:0];
wire inst_valid_b = dec_inst_valid_b && (dec_tid_b==mytid[1:0]) && !(dec_flush_b || tlu_flush_ifu);
always @ (posedge myclk) begin // {
dec_inst_valid_b <= dec_inst_valid_m;
inst_valid_w <= inst_valid_b;
inst_valid_fx4 <= inst_valid_w;
inst_valid_fx5 <= inst_valid_fx4;
inst_valid_fb <= inst_valid_fx5;
inst_valid_fw <= inst_valid_fb;
inst_valid_fw1 <= inst_valid_fw;
inst_valid_fw2 <= inst_valid_fw1;
if (`PARGS.th_check_enable[mytnum] && nas_pipe_enable) begin // {
if (inst_valid_fw2) begin // {
// Print PC/opcode for debugging
`PR_NORMAL ("nas", `NORMAL, "@%0d #%0d T%0d %h [%h]", $time, inst_count, mytnum, pc_fw2, op_fw2);
inst_count = inst_count + 1;
// End detection for GateSim runs
for (junk=0;junk<`PARGS.bad_trap_count;junk=junk+1) begin // {
if (({16'b0,pc_fw2}&`PC_MASK)===(`PARGS.bad_trap_addr[junk]&`PC_MASK)) begin // {
`PR_ERROR ("nas",`ERROR, "T%0d reached Bad Trap [GATESIM]", mytnum);
for (junk=0;junk<`PARGS.good_trap_count;junk=junk+1) begin // {
if (({16'b0,pc_fw2}&`PC_MASK)===(`PARGS.good_trap_addr[junk]&`PC_MASK)) begin // {
`TOP.finished_tids[mytnum] = 1'b1;
`PARGS.th_check_enable[mytnum] = 1'b0;
`PR_NORMAL ("nas", `NORMAL, "T%0d reached Good Trap. Disabling checking for thread %0d [GATESIM]", mytnum,mytnum);
//----------------------------------------------------------
//----------------------------------------------------------
//----------------------------------------------------------
input [71:0] TICK_CMPR_reg;
input [71:0] STICK_CMPR_reg;
input [71:0] HSTICK_CMPR_reg;
input [2:0] CANRESTORE_reg;
input [2:0] OTHERWIN_reg;
input [2:0] CLEANWIN_reg;
input [16:0] SOFTINT_reg;
input [16:0] rd_SOFTINT_reg;
input [63:0] INTR_RECEIVE_reg;
input [12:0] HPSTATE_reg;
input [63:0] CTXT_PRIM_0_reg;
input [63:0] CTXT_SEC_0_reg;
input [63:0] CTXT_PRIM_1_reg;
input [63:0] CTXT_SEC_1_reg;
input [63:0] LSU_CONTROL_reg;
input [63:0] I_TAG_ACC_reg;
input [63:0] D_TAG_ACC_reg;
input [63:0] WATCHPOINT_ADDR_reg;
input [151:0] Trap_Entry_1;
input [151:0] Trap_Entry_2;
input [151:0] Trap_Entry_3;
input [151:0] Trap_Entry_4;
input [151:0] Trap_Entry_5;
input [151:0] Trap_Entry_6;
input [1:0] frf_w2_valid;
input [1:0] frf_w1_valid;
input asi_valid; // ASI/ASR/PR writes done ..
input asi_in_progress; // ASI/ASR/PR in progess
//----------------------------------------------------------
//----------------------------------------------------------
//----------------------------------------------------------
// delta_* = {type(2bits),win(3bits),regnum(8bits),value(64bits)}
reg [`DELTA_WIDTH:0] delta_fx4 [0:(`MAX_INDEX)];
reg [`DELTA_WIDTH:0] delta_fx5 [0:(`MAX_INDEX)];
reg [`DELTA_WIDTH:0] delta_fb [0:(`MAX_INDEX)];
reg [`DELTA_WIDTH:0] delta_fw [0:(`MAX_INDEX)];
reg [`DELTA_WIDTH:0] delta_fw1 [0:(`MAX_INDEX)];
reg [`DELTA_WIDTH:0] delta_fw2 [0:(`MAX_INDEX)];
reg [`DELTA_WIDTH:0] delta_prev [0:(`MAX_INDEX)];
// need to change in several places in this file
reg [63:0] prev_reg0; // includes G,W,C,F registers
reg [63:0] prev_reg1; // includes G,W,C,F registers
reg [63:0] prev_reg2; // includes G,W,C,F registers
reg [63:0] prev_reg3; // includes G,W,C,F registers
reg [63:0] prev_reg4; // includes G,W,C,F registers
reg [63:0] prev_reg5; // includes G,W,C,F registers
reg [63:0] prev_reg6; // includes G,W,C,F registers
reg [63:0] prev_reg7; // includes G,W,C,F registers
reg [63:0] prev_reg8; // includes G,W,C,F registers
reg [63:0] prev_reg9; // includes G,W,C,F registers
reg [63:0] prev_reg10; // includes G,W,C,F registers
reg [63:0] prev_reg11; // includes G,W,C,F registers
reg [63:0] prev_reg12; // includes G,W,C,F registers
reg [63:0] prev_reg13; // includes G,W,C,F registers
reg [63:0] prev_reg14; // includes G,W,C,F registers
reg [63:0] prev_reg15; // includes G,W,C,F registers
reg [63:0] prev_reg16; // includes G,W,C,F registers
reg [63:0] prev_reg17; // includes G,W,C,F registers
reg [63:0] prev_reg18; // includes G,W,C,F registers
reg [63:0] prev_reg19; // includes G,W,C,F registers
reg [63:0] prev_reg20; // includes G,W,C,F registers
reg [63:0] prev_reg21; // includes G,W,C,F registers
reg [63:0] prev_reg22; // includes G,W,C,F registers
reg [63:0] prev_reg23; // includes G,W,C,F registers
reg [63:0] prev_reg24; // includes G,W,C,F registers
reg [63:0] prev_reg25; // includes G,W,C,F registers
reg [63:0] prev_reg26; // includes G,W,C,F registers
reg [63:0] prev_reg27; // includes G,W,C,F registers
reg [63:0] prev_reg28; // includes G,W,C,F registers
reg [63:0] prev_reg29; // includes G,W,C,F registers
reg [63:0] prev_reg30; // includes G,W,C,F registers
reg [63:0] prev_reg31; // includes G,W,C,F registers
reg [63:0] prev_reg32; // includes G,W,C,F registers
reg [63:0] prev_reg33; // includes G,W,C,F registers
reg [63:0] prev_reg34; // includes G,W,C,F registers
reg [63:0] prev_reg35; // includes G,W,C,F registers
reg [63:0] prev_reg36; // includes G,W,C,F registers
reg [63:0] prev_reg37; // includes G,W,C,F registers
reg [63:0] prev_reg38; // includes G,W,C,F registers
reg [63:0] prev_reg39; // includes G,W,C,F registers
reg [63:0] prev_reg40; // includes G,W,C,F registers
reg [63:0] prev_reg41; // includes G,W,C,F registers
reg [63:0] prev_reg42; // includes G,W,C,F registers
reg [63:0] prev_reg43; // includes G,W,C,F registers
reg [63:0] prev_reg44; // includes G,W,C,F registers
reg [63:0] prev_reg45; // includes G,W,C,F registers
reg [63:0] prev_reg46; // includes G,W,C,F registers
reg [63:0] prev_reg47; // includes G,W,C,F registers
reg [63:0] prev_reg48; // includes G,W,C,F registers
reg [63:0] prev_reg49; // includes G,W,C,F registers
reg [63:0] prev_reg50; // includes G,W,C,F registers
reg [63:0] prev_reg51; // includes G,W,C,F registers
reg [63:0] prev_reg52; // includes G,W,C,F registers
reg [63:0] prev_reg53; // includes G,W,C,F registers
reg [63:0] prev_reg54; // includes G,W,C,F registers
reg [63:0] prev_reg55; // includes G,W,C,F registers
reg [63:0] prev_reg56; // includes G,W,C,F registers
reg [63:0] prev_reg57; // includes G,W,C,F registers
reg [63:0] prev_reg58; // includes G,W,C,F registers
reg [63:0] prev_reg59; // includes G,W,C,F registers
reg [63:0] prev_reg60; // includes G,W,C,F registers
reg [63:0] prev_reg61; // includes G,W,C,F registers
reg [63:0] prev_reg62; // includes G,W,C,F registers
reg [63:0] prev_reg63; // includes G,W,C,F registers
reg [63:0] prev_reg64; // includes G,W,C,F registers
reg [63:0] prev_reg65; // includes G,W,C,F registers
reg [63:0] prev_reg66; // includes G,W,C,F registers
reg [63:0] prev_reg67; // includes G,W,C,F registers
reg [63:0] prev_reg68; // includes G,W,C,F registers
reg [63:0] prev_reg69; // includes G,W,C,F registers
reg [63:0] prev_reg70; // includes G,W,C,F registers
reg [63:0] prev_reg71; // includes G,W,C,F registers
reg [63:0] prev_reg72; // includes G,W,C,F registers
reg [63:0] prev_reg73; // includes G,W,C,F registers
reg [63:0] prev_reg74; // includes G,W,C,F registers
reg [63:0] prev_reg75; // includes G,W,C,F registers
reg [63:0] prev_reg76; // includes G,W,C,F registers
reg [63:0] prev_reg77; // includes G,W,C,F registers
reg [63:0] prev_reg78; // includes G,W,C,F registers
reg [63:0] prev_reg79; // includes G,W,C,F registers
reg [63:0] prev_reg80; // includes G,W,C,F registers
reg [63:0] prev_reg81; // includes G,W,C,F registers
reg [63:0] prev_reg82; // includes G,W,C,F registers
reg [63:0] prev_reg83; // includes G,W,C,F registers
reg [63:0] prev_reg84; // includes G,W,C,F registers
reg [63:0] prev_reg85; // includes G,W,C,F registers
reg [63:0] prev_reg86; // includes G,W,C,F registers
reg [63:0] prev_reg87; // includes G,W,C,F registers
reg [63:0] prev_reg88; // includes G,W,C,F registers
reg [63:0] prev_reg89; // includes G,W,C,F registers
reg [63:0] prev_reg90; // includes G,W,C,F registers
reg [63:0] prev_reg91; // includes G,W,C,F registers
reg [63:0] prev_reg92; // includes G,W,C,F registers
reg [63:0] prev_reg93; // includes G,W,C,F registers
reg [63:0] prev_reg94; // includes G,W,C,F registers
reg [63:0] prev_reg95; // includes G,W,C,F registers
reg [63:0] prev_reg96; // includes G,W,C,F registers
reg [63:0] prev_reg97; // includes G,W,C,F registers
reg [63:0] prev_reg98; // includes G,W,C,F registers
reg [63:0] prev_reg99; // includes G,W,C,F registers
reg [63:0] prev_reg100; // includes G,W,C,F registers
reg [63:0] prev_reg101; // includes G,W,C,F registers
reg [63:0] prev_reg102; // includes G,W,C,F registers
reg [63:0] prev_reg103; // includes G,W,C,F registers
reg [63:0] prev_reg104; // includes G,W,C,F registers
reg [63:0] prev_reg105; // includes G,W,C,F registers
reg [63:0] prev_reg106; // includes G,W,C,F registers
reg [63:0] prev_reg107; // includes G,W,C,F registers
reg [63:0] prev_reg108; // includes G,W,C,F registers
reg [63:0] prev_reg109; // includes G,W,C,F registers
reg [63:0] prev_reg110; // includes G,W,C,F registers
reg [63:0] prev_reg111; // includes G,W,C,F registers
reg [63:0] prev_reg112; // includes G,W,C,F registers
reg [63:0] prev_reg113; // includes G,W,C,F registers
reg [63:0] prev_reg114; // includes G,W,C,F registers
reg [63:0] prev_reg115; // includes G,W,C,F registers
reg [63:0] prev_reg116; // includes G,W,C,F registers
reg [63:0] prev_reg117; // includes G,W,C,F registers
reg [63:0] prev_reg118; // includes G,W,C,F registers
reg [63:0] prev_reg119; // includes G,W,C,F registers
reg [63:0] prev_reg120; // includes G,W,C,F registers
reg [63:0] prev_reg121; // includes G,W,C,F registers
reg [63:0] prev_reg122; // includes G,W,C,F registers
reg [63:0] prev_reg123; // includes G,W,C,F registers
reg [63:0] prev_reg124; // includes G,W,C,F registers
reg [63:0] prev_reg125; // includes G,W,C,F registers
reg [63:0] prev_reg126; // includes G,W,C,F registers
reg [63:0] prev_reg127; // includes G,W,C,F registers
reg [63:0] prev_reg128; // includes G,W,C,F registers
reg [63:0] prev_reg129; // includes G,W,C,F registers
reg [63:0] prev_reg130; // includes G,W,C,F registers
reg [63:0] prev_reg131; // includes G,W,C,F registers
reg [63:0] prev_reg132; // includes G,W,C,F registers
reg [63:0] prev_reg133; // includes G,W,C,F registers
reg [63:0] prev_reg134; // includes G,W,C,F registers
reg [63:0] prev_reg135; // includes G,W,C,F registers
reg [63:0] prev_reg136; // includes G,W,C,F registers
reg [63:0] prev_reg137; // includes G,W,C,F registers
reg [63:0] prev_reg138; // includes G,W,C,F registers
reg [63:0] prev_reg139; // includes G,W,C,F registers
reg [63:0] prev_reg140; // includes G,W,C,F registers
reg [63:0] prev_reg141; // includes G,W,C,F registers
reg [63:0] prev_reg142; // includes G,W,C,F registers
reg [63:0] prev_reg143; // includes G,W,C,F registers
reg [63:0] prev_reg144; // includes G,W,C,F registers
reg [63:0] prev_reg145; // includes G,W,C,F registers
reg [63:0] prev_reg146; // includes G,W,C,F registers
reg [63:0] prev_reg147; // includes G,W,C,F registers
reg [63:0] prev_reg148; // includes G,W,C,F registers
reg [63:0] prev_reg149; // includes G,W,C,F registers
reg [63:0] prev_reg150; // includes G,W,C,F registers
reg [63:0] prev_reg151; // includes G,W,C,F registers
reg [63:0] prev_reg152; // includes G,W,C,F registers
reg [63:0] prev_reg153; // includes G,W,C,F registers
reg [63:0] prev_reg154; // includes G,W,C,F registers
reg [63:0] prev_reg155; // includes G,W,C,F registers
reg [63:0] prev_reg156; // includes G,W,C,F registers
reg [63:0] prev_reg157; // includes G,W,C,F registers
reg [63:0] prev_reg158; // includes G,W,C,F registers
reg [63:0] prev_reg159; // includes G,W,C,F registers
reg [63:0] prev_reg160; // includes G,W,C,F registers
reg [63:0] prev_reg161; // includes G,W,C,F registers
reg [63:0] prev_reg162; // includes G,W,C,F registers
reg [63:0] prev_reg163; // includes G,W,C,F registers
reg [63:0] prev_reg164; // includes G,W,C,F registers
reg [63:0] prev_reg165; // includes G,W,C,F registers
reg [63:0] prev_reg166; // includes G,W,C,F registers
reg [63:0] prev_reg167; // includes G,W,C,F registers
reg [63:0] prev_reg168; // includes G,W,C,F registers
reg [63:0] prev_reg169; // includes G,W,C,F registers
reg [63:0] prev_reg170; // includes G,W,C,F registers
reg [63:0] prev_reg171; // includes G,W,C,F registers
reg [63:0] prev_reg172; // includes G,W,C,F registers
reg [63:0] prev_reg173; // includes G,W,C,F registers
reg [63:0] prev_reg174; // includes G,W,C,F registers
reg [63:0] prev_reg175; // includes G,W,C,F registers
reg [63:0] prev_reg176; // includes G,W,C,F registers
reg [63:0] prev_reg177; // includes G,W,C,F registers
reg [63:0] prev_reg178; // includes G,W,C,F registers
reg [63:0] prev_reg179; // includes G,W,C,F registers
reg [63:0] prev_reg180; // includes G,W,C,F registers
reg [63:0] prev_reg181; // includes G,W,C,F registers
reg [63:0] prev_reg182; // includes G,W,C,F registers
reg [63:0] prev_reg183; // includes G,W,C,F registers
reg [63:0] prev_reg184; // includes G,W,C,F registers
reg [63:0] prev_reg185; // includes G,W,C,F registers
reg [63:0] prev_reg186; // includes G,W,C,F registers
reg [63:0] prev_reg187; // includes G,W,C,F registers
reg [63:0] prev_reg188; // includes G,W,C,F registers
reg [63:0] prev_reg189; // includes G,W,C,F registers
reg [63:0] prev_reg190; // includes G,W,C,F registers
reg [63:0] prev_reg191; // includes G,W,C,F registers
reg [63:0] prev_reg192; // includes G,W,C,F registers
reg [63:0] prev_reg193; // includes G,W,C,F registers
reg [63:0] prev_reg194; // includes G,W,C,F registers
reg [63:0] prev_reg195; // includes G,W,C,F registers
reg [63:0] prev_reg196; // includes G,W,C,F registers
reg [63:0] prev_reg197; // includes G,W,C,F registers
reg [63:0] prev_reg198; // includes G,W,C,F registers
reg [63:0] prev_reg199; // includes G,W,C,F registers
reg [63:0] prev_reg200; // includes G,W,C,F registers
reg [63:0] prev_reg201; // includes G,W,C,F registers
reg [63:0] prev_reg202; // includes G,W,C,F registers
reg [63:0] prev_reg203; // includes G,W,C,F registers
reg [63:0] prev_reg204; // includes G,W,C,F registers
reg [63:0] prev_reg205; // includes G,W,C,F registers
reg [63:0] prev_reg206; // includes G,W,C,F registers
reg [63:0] prev_reg207; // includes G,W,C,F registers
reg [63:0] prev_reg208; // includes G,W,C,F registers
reg [63:0] prev_reg209; // includes G,W,C,F registers
reg [63:0] prev_reg210; // includes G,W,C,F registers
reg [63:0] prev_reg211; // includes G,W,C,F registers
reg [63:0] prev_reg212; // includes G,W,C,F registers
reg [63:0] prev_reg213; // includes G,W,C,F registers
reg [63:0] prev_reg214; // includes G,W,C,F registers
reg [63:0] prev_reg215; // includes G,W,C,F registers
reg [63:0] prev_reg216; // includes G,W,C,F registers
reg [63:0] prev_reg217; // includes G,W,C,F registers
reg [63:0] prev_reg218; // includes G,W,C,F registers
reg [63:0] prev_reg219; // includes G,W,C,F registers
reg [63:0] prev_reg220; // includes G,W,C,F registers
reg [63:0] prev_reg221; // includes G,W,C,F registers
reg [63:0] prev_reg222; // includes G,W,C,F registers
reg [63:0] prev_reg223; // includes G,W,C,F registers
reg [63:0] prev_reg224; // includes G,W,C,F registers
reg [63:0] prev_reg225; // includes G,W,C,F registers
reg [63:0] prev_reg226; // includes G,W,C,F registers
reg [63:0] prev_reg227; // includes G,W,C,F registers
reg [63:0] prev_reg228; // includes G,W,C,F registers
reg [63:0] prev_reg229; // includes G,W,C,F registers
reg [63:0] prev_reg230; // includes G,W,C,F registers
reg [63:0] prev_reg231; // includes G,W,C,F registers
reg [63:0] prev_reg232; // includes G,W,C,F registers
reg [63:0] prev_reg233; // includes G,W,C,F registers
reg [63:0] prev_reg234; // includes G,W,C,F registers
reg [63:0] prev_reg235; // includes G,W,C,F registers
reg [63:0] prev_reg236; // includes G,W,C,F registers
reg [63:0] prev_reg237; // includes G,W,C,F registers
reg [63:0] prev_reg238; // includes G,W,C,F registers
reg [63:0] prev_reg239; // includes G,W,C,F registers
reg [63:0] prev_reg240; // includes G,W,C,F registers
reg [63:0] prev_reg241; // includes G,W,C,F registers
reg [63:0] prev_reg242; // includes G,W,C,F registers
reg [63:0] prev_reg243; // includes G,W,C,F registers
reg [63:0] prev_reg244; // includes G,W,C,F registers
reg [63:0] prev_reg245; // includes G,W,C,F registers
reg [63:0] prev_reg246; // includes G,W,C,F registers
reg [63:0] prev_reg247; // includes G,W,C,F registers
reg [63:0] prev_reg248; // includes G,W,C,F registers
reg [63:0] prev_reg249; // includes G,W,C,F registers
reg [63:0] prev_reg250; // includes G,W,C,F registers
reg [63:0] prev_reg251; // includes G,W,C,F registers
reg [63:0] prev_reg252; // includes G,W,C,F registers
reg [63:0] prev_reg253; // includes G,W,C,F registers
reg [63:0] prev_reg254; // includes G,W,C,F registers
reg [63:0] prev_reg255; // includes G,W,C,F registers
reg [1:0] th_gl; // copy of GL_reg
reg frf_w1_skip_addr4_fw1;
reg frf_w1_skip_addr4_fw2;
reg [1:0] frf_w2_valid_fw;
reg [1:0] frf_w2_valid_bn;
reg [4:0] frf_w2_addr_fw;
reg [1:0] frf_w1_valid_fw;
reg [4:0] frf_w1_addr_fw;
reg wmr; // latched to get edge
reg por_a; // latched to get edge
reg por_b; // latched to get edge
reg nas_pipe_enable; // Turns on nas_pipe capture and Riesling SSTEP
wire [4:0] frf_w1_skip_addr;
wire [4:0] frf_w2_skip_addr;
reg good_trap_detected; // Used for -nosas only.
//----------------------------------------------------------
wire [`DELTA_WIDTH:0] delta_fx4_0;
wire [`DELTA_WIDTH:0] delta_fx4_1;
wire [`DELTA_WIDTH:0] delta_fx4_2;
wire [`DELTA_WIDTH:0] delta_fx4_3;
wire [`DELTA_WIDTH:0] delta_fx4_4;
wire [`DELTA_WIDTH:0] delta_fx4_5;
wire [`DELTA_WIDTH:0] delta_fx4_6;
wire [`DELTA_WIDTH:0] delta_fx4_7;
wire [`DELTA_WIDTH:0] delta_fx5_0;
wire [`DELTA_WIDTH:0] delta_fx5_1;
wire [`DELTA_WIDTH:0] delta_fx5_2;
wire [`DELTA_WIDTH:0] delta_fx5_3;
wire [`DELTA_WIDTH:0] delta_fx5_4;
wire [`DELTA_WIDTH:0] delta_fx5_5;
wire [`DELTA_WIDTH:0] delta_fx5_6;
wire [`DELTA_WIDTH:0] delta_fx5_7;
wire [`DELTA_WIDTH:0] delta_fb_0;
wire [`DELTA_WIDTH:0] delta_fb_1;
wire [`DELTA_WIDTH:0] delta_fb_2;
wire [`DELTA_WIDTH:0] delta_fb_3;
wire [`DELTA_WIDTH:0] delta_fb_4;
wire [`DELTA_WIDTH:0] delta_fb_5;
wire [`DELTA_WIDTH:0] delta_fb_6;
wire [`DELTA_WIDTH:0] delta_fb_7;
wire [`DELTA_WIDTH:0] delta_fw_0;
wire [`DELTA_WIDTH:0] delta_fw_1;
wire [`DELTA_WIDTH:0] delta_fw_2;
wire [`DELTA_WIDTH:0] delta_fw_3;
wire [`DELTA_WIDTH:0] delta_fw_4;
wire [`DELTA_WIDTH:0] delta_fw_5;
wire [`DELTA_WIDTH:0] delta_fw_6;
wire [`DELTA_WIDTH:0] delta_fw_7;
wire [`DELTA_WIDTH:0] delta_fw1_0;
wire [`DELTA_WIDTH:0] delta_fw1_1;
wire [`DELTA_WIDTH:0] delta_fw1_2;
wire [`DELTA_WIDTH:0] delta_fw1_3;
wire [`DELTA_WIDTH:0] delta_fw1_4;
wire [`DELTA_WIDTH:0] delta_fw1_5;
wire [`DELTA_WIDTH:0] delta_fw1_6;
wire [`DELTA_WIDTH:0] delta_fw1_7;
wire [`DELTA_WIDTH:0] delta_fw2_0;
wire [`DELTA_WIDTH:0] delta_fw2_1;
wire [`DELTA_WIDTH:0] delta_fw2_2;
wire [`DELTA_WIDTH:0] delta_fw2_3;
wire [`DELTA_WIDTH:0] delta_fw2_4;
wire [`DELTA_WIDTH:0] delta_fw2_5;
wire [`DELTA_WIDTH:0] delta_fw2_6;
wire [`DELTA_WIDTH:0] delta_fw2_7;
wire [`DELTA_WIDTH:0] delta_prev_0;
wire [`DELTA_WIDTH:0] delta_prev_1;
wire [`DELTA_WIDTH:0] delta_prev_2;
wire [`DELTA_WIDTH:0] delta_prev_3;
wire [`DELTA_WIDTH:0] delta_prev_4;
wire [`DELTA_WIDTH:0] delta_prev_5;
wire [`DELTA_WIDTH:0] delta_prev_6;
wire [`DELTA_WIDTH:0] delta_prev_7;
`PR_ALWAYS ("arg", `ALWAYS,"T%0d DEBUG_PIPE turned ON",mytnum);
//----------------------------------------------------------
// Note: no remap of %g,%o,%l,%i regs based on CWP or GL
assign g0 = (mytid<=3) ? `IRF2_EXU0[( 0+irf_offset)] : `IRF2_EXU1[( 0+irf_offset)];
assign g1 = (mytid<=3) ? `IRF2_EXU0[( 1+irf_offset)] : `IRF2_EXU1[( 1+irf_offset)];
assign g2 = (mytid<=3) ? `IRF2_EXU0[( 2+irf_offset)] : `IRF2_EXU1[( 2+irf_offset)];
assign g3 = (mytid<=3) ? `IRF2_EXU0[( 3+irf_offset)] : `IRF2_EXU1[( 3+irf_offset)];
assign g4 = (mytid<=3) ? `IRF2_EXU0[( 4+irf_offset)] : `IRF2_EXU1[( 4+irf_offset)];
assign g5 = (mytid<=3) ? `IRF2_EXU0[( 5+irf_offset)] : `IRF2_EXU1[( 5+irf_offset)];
assign g6 = (mytid<=3) ? `IRF2_EXU0[( 6+irf_offset)] : `IRF2_EXU1[( 6+irf_offset)];
assign g7 = (mytid<=3) ? `IRF2_EXU0[( 7+irf_offset)] : `IRF2_EXU1[( 7+irf_offset)];
assign o0 = (mytid<=3) ? `IRF2_EXU0[( 8+irf_offset)] : `IRF2_EXU1[( 8+irf_offset)];
assign o1 = (mytid<=3) ? `IRF2_EXU0[( 9+irf_offset)] : `IRF2_EXU1[( 9+irf_offset)];
assign o2 = (mytid<=3) ? `IRF2_EXU0[(10+irf_offset)] : `IRF2_EXU1[(10+irf_offset)];
assign o3 = (mytid<=3) ? `IRF2_EXU0[(11+irf_offset)] : `IRF2_EXU1[(11+irf_offset)];
assign o4 = (mytid<=3) ? `IRF2_EXU0[(12+irf_offset)] : `IRF2_EXU1[(12+irf_offset)];
assign o5 = (mytid<=3) ? `IRF2_EXU0[(13+irf_offset)] : `IRF2_EXU1[(13+irf_offset)];
assign o6 = (mytid<=3) ? `IRF2_EXU0[(14+irf_offset)] : `IRF2_EXU1[(14+irf_offset)];
assign o7 = (mytid<=3) ? `IRF2_EXU0[(15+irf_offset)] : `IRF2_EXU1[(15+irf_offset)];
assign l0 = (mytid<=3) ? `IRF2_EXU0[(16+irf_offset)] : `IRF2_EXU1[(16+irf_offset)];
assign l1 = (mytid<=3) ? `IRF2_EXU0[(17+irf_offset)] : `IRF2_EXU1[(17+irf_offset)];
assign l2 = (mytid<=3) ? `IRF2_EXU0[(18+irf_offset)] : `IRF2_EXU1[(18+irf_offset)];
assign l3 = (mytid<=3) ? `IRF2_EXU0[(19+irf_offset)] : `IRF2_EXU1[(19+irf_offset)];
assign l4 = (mytid<=3) ? `IRF2_EXU0[(20+irf_offset)] : `IRF2_EXU1[(20+irf_offset)];
assign l5 = (mytid<=3) ? `IRF2_EXU0[(21+irf_offset)] : `IRF2_EXU1[(21+irf_offset)];
assign l6 = (mytid<=3) ? `IRF2_EXU0[(22+irf_offset)] : `IRF2_EXU1[(22+irf_offset)];
assign l7 = (mytid<=3) ? `IRF2_EXU0[(23+irf_offset)] : `IRF2_EXU1[(23+irf_offset)];
assign i0 = (mytid<=3) ? `IRF2_EXU0[(24+irf_offset)] : `IRF2_EXU1[(24+irf_offset)];
assign i1 = (mytid<=3) ? `IRF2_EXU0[(25+irf_offset)] : `IRF2_EXU1[(25+irf_offset)];
assign i2 = (mytid<=3) ? `IRF2_EXU0[(26+irf_offset)] : `IRF2_EXU1[(26+irf_offset)];
assign i3 = (mytid<=3) ? `IRF2_EXU0[(27+irf_offset)] : `IRF2_EXU1[(27+irf_offset)];
assign i4 = (mytid<=3) ? `IRF2_EXU0[(28+irf_offset)] : `IRF2_EXU1[(28+irf_offset)];
assign i5 = (mytid<=3) ? `IRF2_EXU0[(29+irf_offset)] : `IRF2_EXU1[(29+irf_offset)];
assign i6 = (mytid<=3) ? `IRF2_EXU0[(30+irf_offset)] : `IRF2_EXU1[(30+irf_offset)];
assign i7 = (mytid<=3) ? `IRF2_EXU0[(31+irf_offset)] : `IRF2_EXU1[(31+irf_offset)];
//----------------------------------------------------------
assign frf_0 = `FRF2_EVEN[(mytid*32)+ 0];
assign frf_2 = `FRF2_EVEN[(mytid*32)+ 1];
assign frf_4 = `FRF2_EVEN[(mytid*32)+ 2];
assign frf_6 = `FRF2_EVEN[(mytid*32)+ 3];
assign frf_8 = `FRF2_EVEN[(mytid*32)+ 4];
assign frf_10 = `FRF2_EVEN[(mytid*32)+ 5];
assign frf_12 = `FRF2_EVEN[(mytid*32)+ 6];
assign frf_14 = `FRF2_EVEN[(mytid*32)+ 7];
assign frf_16 = `FRF2_EVEN[(mytid*32)+ 8];
assign frf_18 = `FRF2_EVEN[(mytid*32)+ 9];
assign frf_20 = `FRF2_EVEN[(mytid*32)+ 10];
assign frf_22 = `FRF2_EVEN[(mytid*32)+ 11];
assign frf_24 = `FRF2_EVEN[(mytid*32)+ 12];
assign frf_26 = `FRF2_EVEN[(mytid*32)+ 13];
assign frf_28 = `FRF2_EVEN[(mytid*32)+ 14];
assign frf_30 = `FRF2_EVEN[(mytid*32)+ 15];
assign frf_32 = `FRF2_EVEN[(mytid*32)+ 16];
assign frf_34 = `FRF2_EVEN[(mytid*32)+ 17];
assign frf_36 = `FRF2_EVEN[(mytid*32)+ 18];
assign frf_38 = `FRF2_EVEN[(mytid*32)+ 19];
assign frf_40 = `FRF2_EVEN[(mytid*32)+ 20];
assign frf_42 = `FRF2_EVEN[(mytid*32)+ 21];
assign frf_44 = `FRF2_EVEN[(mytid*32)+ 22];
assign frf_46 = `FRF2_EVEN[(mytid*32)+ 23];
assign frf_48 = `FRF2_EVEN[(mytid*32)+ 24];
assign frf_50 = `FRF2_EVEN[(mytid*32)+ 25];
assign frf_52 = `FRF2_EVEN[(mytid*32)+ 26];
assign frf_54 = `FRF2_EVEN[(mytid*32)+ 27];
assign frf_56 = `FRF2_EVEN[(mytid*32)+ 28];
assign frf_58 = `FRF2_EVEN[(mytid*32)+ 29];
assign frf_60 = `FRF2_EVEN[(mytid*32)+ 30];
assign frf_62 = `FRF2_EVEN[(mytid*32)+ 31];
assign frf_1 = `FRF2_ODD[(mytid*32)+ 0];
assign frf_3 = `FRF2_ODD[(mytid*32)+ 1];
assign frf_5 = `FRF2_ODD[(mytid*32)+ 2];
assign frf_7 = `FRF2_ODD[(mytid*32)+ 3];
assign frf_9 = `FRF2_ODD[(mytid*32)+ 4];
assign frf_11 = `FRF2_ODD[(mytid*32)+ 5];
assign frf_13 = `FRF2_ODD[(mytid*32)+ 6];
assign frf_15 = `FRF2_ODD[(mytid*32)+ 7];
assign frf_17 = `FRF2_ODD[(mytid*32)+ 8];
assign frf_19 = `FRF2_ODD[(mytid*32)+ 9];
assign frf_21 = `FRF2_ODD[(mytid*32)+ 10];
assign frf_23 = `FRF2_ODD[(mytid*32)+ 11];
assign frf_25 = `FRF2_ODD[(mytid*32)+ 12];
assign frf_27 = `FRF2_ODD[(mytid*32)+ 13];
assign frf_29 = `FRF2_ODD[(mytid*32)+ 14];
assign frf_31 = `FRF2_ODD[(mytid*32)+ 15];
assign frf_33 = `FRF2_ODD[(mytid*32)+ 16];
assign frf_35 = `FRF2_ODD[(mytid*32)+ 17];
assign frf_37 = `FRF2_ODD[(mytid*32)+ 18];
assign frf_39 = `FRF2_ODD[(mytid*32)+ 19];
assign frf_41 = `FRF2_ODD[(mytid*32)+ 20];
assign frf_43 = `FRF2_ODD[(mytid*32)+ 21];
assign frf_45 = `FRF2_ODD[(mytid*32)+ 22];
assign frf_47 = `FRF2_ODD[(mytid*32)+ 23];
assign frf_49 = `FRF2_ODD[(mytid*32)+ 24];
assign frf_51 = `FRF2_ODD[(mytid*32)+ 25];
assign frf_53 = `FRF2_ODD[(mytid*32)+ 26];
assign frf_55 = `FRF2_ODD[(mytid*32)+ 27];
assign frf_57 = `FRF2_ODD[(mytid*32)+ 28];
assign frf_59 = `FRF2_ODD[(mytid*32)+ 29];
assign frf_61 = `FRF2_ODD[(mytid*32)+ 30];
assign frf_63 = `FRF2_ODD[(mytid*32)+ 31];
//----------------------------------------------------------
assign delta_fx4_0 = delta_fx4[0];
assign delta_fx4_1 = delta_fx4[1];
assign delta_fx4_2 = delta_fx4[2];
assign delta_fx4_3 = delta_fx4[3];
assign delta_fx4_4 = delta_fx4[4];
assign delta_fx4_5 = delta_fx4[5];
assign delta_fx4_6 = delta_fx4[6];
assign delta_fx4_7 = delta_fx4[7];
assign delta_fx5_0 = delta_fx5[0];
assign delta_fx5_1 = delta_fx5[1];
assign delta_fx5_2 = delta_fx5[2];
assign delta_fx5_3 = delta_fx5[3];
assign delta_fx5_4 = delta_fx5[4];
assign delta_fx5_5 = delta_fx5[5];
assign delta_fx5_6 = delta_fx5[6];
assign delta_fx5_7 = delta_fx5[7];
assign delta_fb_0 = delta_fb[0];
assign delta_fb_1 = delta_fb[1];
assign delta_fb_2 = delta_fb[2];
assign delta_fb_3 = delta_fb[3];
assign delta_fb_4 = delta_fb[4];
assign delta_fb_5 = delta_fb[5];
assign delta_fb_6 = delta_fb[6];
assign delta_fb_7 = delta_fb[7];
assign delta_fw_0 = delta_fw[0];
assign delta_fw_1 = delta_fw[1];
assign delta_fw_2 = delta_fw[2];
assign delta_fw_3 = delta_fw[3];
assign delta_fw_4 = delta_fw[4];
assign delta_fw_5 = delta_fw[5];
assign delta_fw_6 = delta_fw[6];
assign delta_fw_7 = delta_fw[7];
assign delta_fw1_0 = delta_fw1[0];
assign delta_fw1_1 = delta_fw1[1];
assign delta_fw1_2 = delta_fw1[2];
assign delta_fw1_3 = delta_fw1[3];
assign delta_fw1_4 = delta_fw1[4];
assign delta_fw1_5 = delta_fw1[5];
assign delta_fw1_6 = delta_fw1[6];
assign delta_fw1_7 = delta_fw1[7];
assign delta_fw2_0 = delta_fw2[0];
assign delta_fw2_1 = delta_fw2[1];
assign delta_fw2_2 = delta_fw2[2];
assign delta_fw2_3 = delta_fw2[3];
assign delta_fw2_4 = delta_fw2[4];
assign delta_fw2_5 = delta_fw2[5];
assign delta_fw2_6 = delta_fw2[6];
assign delta_fw2_7 = delta_fw2[7];
assign delta_prev_0 = delta_prev[0];
assign delta_prev_1 = delta_prev[1];
assign delta_prev_2 = delta_prev[2];
assign delta_prev_3 = delta_prev[3];
assign delta_prev_4 = delta_prev[4];
assign delta_prev_5 = delta_prev[5];
assign delta_prev_6 = delta_prev[6];
assign delta_prev_7 = delta_prev[7];
//----------------------------------------------------------
//----------------------------------------------------------
assign mytnum = (mycid*8)+mytid;
assign mytg = mytid >> 2;
assign exu_complete = exu_valid & ~(`PROBES2.clkstop_d5|`TOP.in_reset|`SPC2.tcu_scan_en);
assign imul_complete = imul_valid & ~(`TOP.in_reset|`SPC2.tcu_scan_en);
assign idiv_complete = idiv_valid & ~(`TOP.in_reset|`SPC2.tcu_scan_en);
assign tlu_complete = tlu_complete_3 ;
assign fp_complete = fp_valid & ~(`TOP.in_reset|`SPC2.tcu_scan_en);
assign fdiv_complete = fdiv_valid & ~(`TOP.in_reset|`SPC2.tcu_scan_en);
assign lsu_complete = lsu_valid & ~(`TOP.in_reset|`SPC2.tcu_scan_en);
assign asi_complete = asi_valid & ~(`TOP.in_reset|`SPC2.tcu_scan_en);
assign complete_w = (exu_complete << `EXU_INDEX) |
(lsu_complete << `LSU_INDEX) |
(tlu_complete << `TLU_INDEX) |
(asi_complete << `ASI_INDEX) ;
assign oddwin = CWP_reg % 2;
assign frf_w1_valid_even = (frf_w1_tid_fw == mytid) & frf_w1_valid_fw[1];
assign frf_w1_valid_odd = (frf_w1_tid_fw == mytid) & frf_w1_valid_fw[0];
assign frf_w2_valid_even = (frf_w2_tid_fw == mytid) & frf_w2_valid_fw[1];
assign frf_w2_valid_odd = (frf_w2_tid_fw == mytid) & frf_w2_valid_fw[0];
assign frf_w1_skip_addr = frf_w1_addr_fw;
assign frf_w2_skip_addr = frf_w2_addr_fw;
// NOTE - ADD_TSB_CFG will never be used for Axis or Tharas
wire [63:0] ctxt_z_tsb_cfg0_reg = `PROBES2.ctxt_z_tsb_cfg0_reg[mytid];
wire [63:0] ctxt_z_tsb_cfg1_reg = `PROBES2.ctxt_z_tsb_cfg1_reg[mytid];
wire [63:0] ctxt_z_tsb_cfg2_reg = `PROBES2.ctxt_z_tsb_cfg2_reg[mytid];
wire [63:0] ctxt_z_tsb_cfg3_reg = `PROBES2.ctxt_z_tsb_cfg3_reg[mytid];
wire [63:0] ctxt_nz_tsb_cfg0_reg = `PROBES2.ctxt_nz_tsb_cfg0_reg[mytid];
wire [63:0] ctxt_nz_tsb_cfg1_reg = `PROBES2.ctxt_nz_tsb_cfg1_reg[mytid];
wire [63:0] ctxt_nz_tsb_cfg2_reg = `PROBES2.ctxt_nz_tsb_cfg2_reg[mytid];
wire [63:0] ctxt_nz_tsb_cfg3_reg = `PROBES2.ctxt_nz_tsb_cfg3_reg[mytid];
//----------------------------------------------------------
always @ (posedge `BENCH_SPC2_GCLK) begin // {
// TLU is async to the execution pipeline
// but needs to be delayed to allow CWP, etc to update and be stable
// before arch state is captured and diff_reg is called.
// FDIV was moved from fw1 to fw to allow FPRS to be stable before capture
tlu_complete_1 <= tlu_valid & ~(`TOP.in_reset|`SPC2.tcu_scan_en);
tlu_complete_2 <= tlu_complete_1;
tlu_complete_3 <= tlu_complete_2;
itagacc_fx5 <= I_TAG_ACC_reg; // Signal changes in W so need to pipeline to fw2
itagacc_fb <= itagacc_fx5;
itagacc_fw <= itagacc_fb;
itagacc_fw1 <= itagacc_fw;
itagacc_fw2 <= itagacc_fw1;
dtagacc_fx5 <= D_TAG_ACC_reg; // Signal changes in W so need to pipeline to fw2
dtagacc_fb <= dtagacc_fx5;
dtagacc_fw <= dtagacc_fb;
dtagacc_fw1 <= dtagacc_fw;
dtagacc_fw2 <= dtagacc_fw1;
dsfar_fb <= DSFAR_reg; // Signal changes in W+1 so need to pipeline to fw2
complete_fx4 <= complete_w;
complete_fx5 <= complete_fx4 ;
complete_fb <= complete_fx5 |
(idiv_complete << `IDIV_INDEX);
complete_fw <= complete_fb |
(fdiv_complete << `FDIV_INDEX) |
(imul_complete << `IMUL_INDEX);
complete_fw1 <= complete_fw |
(fp_complete << `FP_INDEX);
complete_fw2 <= complete_fw1;
frf_w1_valid_fw1 <= (frf_w1_valid_odd | frf_w1_valid_even) & fp_complete;
frf_w1_valid_fw2 <= frf_w1_valid_fw1;
frf_w1_skip_addr4_fw1 <= frf_w1_skip_addr[4];
frf_w1_skip_addr4_fw2 <= frf_w1_skip_addr4_fw1;
frf_w2_valid_fw <= frf_w2_valid_bn;
frf_w2_tid_fw <= frf_w2_tid;
frf_w2_addr_fw <= frf_w2_addr;
frf_w1_valid_fw <= frf_w1_valid;
frf_w1_tid_fw <= frf_w1_tid;
frf_w1_addr_fw <= frf_w1_addr;
if (~thread_running & `SPC2.tcu_core_running[mytid])
`TOP.th_last_act_cycle[mytnum] = `TOP.core_cycle_cnt;
thread_running <= `SPC2.tcu_core_running[mytid];
// Reset some register prev state on wmr negation
if (`SPC2.rst_wmr_protect && ~wmr)
wmr <= `SPC2.rst_wmr_protect;
if (`SPC2.rst_wmr_protect)
//----------------------------------------------------------
// Holding state for registers that may be updated asynchronously
// after synchronous update, but before capture/step. Also for reads,
// when register is read and modified before capture/step ..
// We capture the value /write time, and use that for sstep,
// ignoring any async updates, which are sent in the NEXT sstep ..
reg [63:0] asi_updated_int_rec;
reg asi_wr_int_rec_delay;
reg [16:0] asi_updated_softint;
reg asi_wr_softint_delay;
reg [16:0] asi_softint_wrdata;
always @(posedge `BENCH_SPC2_GCLK) begin // {
// Corner case : If async and sync wr occur in same clock, then the async
// update takes place. In this case we have to capture the
// value of the write WITHOUT async bit being set, so that
// we can sync with Riesling's sync write ..
asi_wr_int_rec_delay <= ( `SPC2.tlu.cth.asi_wr_int_rec[mytid] |
`SPC2.tlu.asi_rd_inc_vec_2[mytid]);
if (`SPC2.tlu.cth.asi_wr_int_rec[mytid] |
((`SPC2.tlu.asi.rd_inc_vec) &&
(`SPC2.tlu.asi.rd_tid_dec[mytid])) |
(`SPC2.tlu.asi_rd_int_rec &
`SPC2.tlu.cth.int_rec_mux_sel==mytid))
if (`SPC2.tlu.cth.asi_wr_int_rec[mytid])
asi_updated_int_rec <= `SPC2.tlu.cth.int_rec ;
else if ( (`SPC2.tlu.asi.rd_inc_vec) &&
(`SPC2.tlu.asi.rd_tid_dec[mytid]) )
if (`SPC2.tlu.cth.cxi_wr_int_dis[mytid]) begin
asi_updated_int_rec <= INTR_RECEIVE_reg & `SPC2.tlu.cth.int_rec_muxed_;
asi_updated_int_rec[`SPC2.tlu.cth.incoming_vector_in] <= 1'b0 ;
asi_updated_int_rec <= `SPC2.tlu.cth.int_rec_muxed ;
asi_updated_int_rec[`SPC2.tlu.cth.incoming_vector_in] <= 1'b0 ;
asi_updated_int_rec <= INTR_RECEIVE_reg;
asi_rdwr_int_rec <= 1'b1;
else if (complete_fw1 && !`NASTOP.sstep_early[mytnum])
asi_rdwr_int_rec <= 1'b0;
asi_wr_hintp_delay <= `SPC2.tlu.asi_wr_hintp[mytid];
if (`SPC2.tlu.asi_wr_hintp[mytid] |
`SPC2.tlu.asi_rd_hintp[mytid])
if (`SPC2.tlu.asi_wr_hintp[mytid])
asi_updated_hintp <= `SPC2.tlu.asi_wr_data_0[0] ;
asi_updated_hintp <= HINTP_reg;
else if (complete_fw1 && !`NASTOP.sstep_early[mytnum])
asi_wr_softint_delay <= (`SPC2.tlu.asi_wr_softint[mytid] |
`SPC2.tlu.asi_wr_clear_softint[mytid] |
`SPC2.tlu.asi_wr_set_softint[mytid]);
if (`SPC2.tlu.asi_wr_clear_softint[mytid])
asi_softint_wrdata <= ~`SPC2.tlu.asi_wr_data_0[16:0] & rd_SOFTINT_reg;
else if (`SPC2.tlu.asi_wr_set_softint[mytid])
asi_softint_wrdata <= `SPC2.tlu.asi_wr_data_0[16:0] | rd_SOFTINT_reg;
asi_softint_wrdata <= `SPC2.tlu.asi_wr_data_0[16:0];
if (asi_wr_softint_delay | `SPC2.tlu.asi_rd_softint[mytid])
if (asi_wr_softint_delay)
asi_updated_softint <= asi_softint_wrdata ;
asi_updated_softint <= rd_SOFTINT_reg ;
asi_rdwr_softint <= 1'b1;
else if (complete_fw1 && !`NASTOP.sstep_early[mytnum])
asi_rdwr_softint <= 1'b0;
//----------------------------------------------------------
// Negedge sampling to avoid race on specific signals ..
always @ (negedge `BENCH_SPC2_GCLK) begin // {
frf_w2_valid_bn <= frf_w2_valid;
//----------------------------------------------------------
// When instruction completes,
// Push differences to simics
always @ (posedge `BENCH_SPC2_GCLK) begin // {
if (`PARGS.th_check_enable[mytnum] && nas_pipe_enable && ~`SPC2.tcu_scan_en && ~`TOP.in_por) begin // {
// Update window registers
if (CWP_reg != `NASTOP.th_cwp[mytnum]) begin // {
copy_win (CWP_reg,`NASTOP.th_cwp[mytnum]);
`NASTOP.th_cwp[mytnum] = CWP_reg;
// Update global registers
// Wait for warm-reset flush related toggling to settle
if (GL_reg != th_gl) begin // {
if (`SPC2.spc_core_running_status[mytid] &
~`SPC2.rst_wmr_protect) begin // {
copy_global (GL_reg,th_gl);
// Check for bad signal values
// if NASTOP.sstep_sent[tid]=1,
// then SSTEP was set by another module (i.e. tlb_sync)
if (`PARGS.nas_check_on) begin // {
mytime = `TOP.core_cycle_cnt-1;
if (complete_fw2 && (`NASTOP.sstep_sent[mytnum]==1'b0)) begin // {
`PR_INFO ("pli_nas", `INFO, " C%0d T%0d PLI_SSTEP tid=%d pc=%h ts=%0d ",
mycid,mytid,mytnum,pc_fw2,mytime);
junk = $sim_send(`PLI_SSTEP, mytnum);
// Always clear sstep_early
// In case tlb_sync asserted it too late for complete_fw2
`NASTOP.sstep_early[mytnum] <= 1'b0;
else if (complete_fw2) begin // {
`NASTOP.sstep_sent[mytnum] <= 1'b0; // re-arm SSTEP
`NASTOP.sstep_early[mytnum] <= 1'b0;
`PR_INFO ("pli_nas", `INFO, " C%0d T%0d PLI_SSTEP tid=%d pc=%h ts=%0d (nas_pipe: skip sstep. rearm sstep. sstep_sent=0)",
mycid,mytid,mytnum,pc_fw2,mytime);
// Only capture if something completes and not first instruction
if (complete_fw2 && !first_op) begin // {
push_simics; // Use with AXIS to keep from getting timeout
// Pipeline runs continuously
// Other than when in POR ..
// Only save to delta_prev when something completes
`TOP.last_act_cycle = `TOP.core_cycle_cnt; //$time;
`TOP.th_last_act_cycle[mytnum] = `TOP.last_act_cycle;
// If something was captured but no instruction is in the pipeline
if ((delta_fw2[`NEXT_INDEX]!=`FIRST_INDEX) && (complete_fw2 == 0))
for (myindex=`FIRST_INDEX; myindex<delta_fw2[`NEXT_INDEX]; myindex=myindex+1)
print_entry (delta_fw2[myindex]);
`PR_ERROR ("nas",`ERROR, "T%0d Unexpected Reg change in DUT. Special case - no instruction retired.", mytnum);
// End detection for non-sas runs ..
for (junk=0;junk<`PARGS.bad_trap_count;junk=junk+1)
if (({16'b0,pc_fw2}&`PC_MASK) ===
(`PARGS.bad_trap_addr[junk]&`PC_MASK)) begin // {
// Disable nas_pipe processing (capture & SSTEP)
// to speed up simulation (minimize socket traffic,etc)
if (! `PARGS.nas_check_on) begin //{
`PR_ERROR ("nas",`ERROR, "T%0d reached Bad Trap", mytnum);
for (junk=0;junk<`PARGS.good_trap_count;junk=junk+1)
if ((|complete_fw2) && (({16'b0,pc_fw2}&`PC_MASK) ===
(`PARGS.good_trap_addr[junk]&`PC_MASK))) begin // {
// Disable nas_pipe processing (capture & SSTEP)
// to speed up simulation (minimize socket traffic,etc)
if (! `PARGS.nas_check_on) begin //{
good_trap_detected = 1'b1;
// Check Thread level timeout
(`TOP.core_cycle_cnt - `TOP.th_last_act_cycle[mytnum]) > `PARGS.th_timeout)
// Note: Do not change this message because regreport parses it for certain words.
`PR_ALWAYS ("nas",`ALWAYS, "ERROR: Thread T%0d No Activity for %0d Cycles - Thread TIMEOUT!",
mytnum, `PARGS.th_timeout);
junk = incErr(9999); // must exceed users max error setting to force exit.
end // if (`PARGS.th_check_enable[mytnum] && nas_pipe_enable ...)}
// Need to make sure Store Buffer is empty before turning off th_check_enable.
//global chkr requires to wait for all outstanding pending I
if ((! `PARGS.nas_check_on) &&
(good_trap_detected==1'b1) &&
(`TOP.nas_top.lsu_stb_empty[mytnum]) && `TOP.nas_top.ireq_pending[mytnum]) begin // {
`PARGS.th_check_enable[mytnum] = 1'b0;
`TOP.finished_tids[mytnum] = 1'b1;
good_trap_detected = 1'b0;
`PR_NORMAL ("nas", `NORMAL, "T%0d reached Good Trap. Disabling checking for thread %0d", mytnum,mytnum);
//----------------------------------------------------------
//----------------------------------------------------------
// Stage FX4 of delta pipeline
delta_fx4[`NEXT_INDEX] <= `FIRST_INDEX;
delta_fx4[`TIME_INDEX] <= 0;
delta_fx4[`PC_INDEX] <= {16'b0,PC_reg};
delta_fx4[`GL_INDEX] <= GL_reg;
delta_fx4[`CWP_INDEX] <= CWP_reg;
delta_fx4[`OPCODE_INDEX] <= opcode;
delta_fx4[`FIRST_INDEX] <= 77'hx;
//----------------------------------------------------------
// Stage FX5 of delta pipeline
index = delta_fx4[`NEXT_INDEX];
// Pipeline previous stage
for (i=0; i<=delta_fx4[`NEXT_INDEX]; i=i+1) begin // {
delta_fx5[i] <= delta_fx4[i];
if (complete_fx4) begin // LSU | EXU | TLU
push_delta_fx5 (`CCR+`CTL_OFFSET,CCR_reg,index);
if (complete_fx4[`LSU_INDEX] |
complete_fx4[`EXU_INDEX]) begin
if (mytid <= 3) begin // {
for (i=0; i<=31; i=i+1) begin // {
push_delta_fx5 (i,`IRF2_EXU0[(remap(i,oddwin)+irf_offset)],index);
for (i=0; i<=31; i=i+1) begin // {
push_delta_fx5 (i,`IRF2_EXU1[(remap(i,oddwin)+irf_offset)],index);
// Update FRF2 - Loads use W2 Port.
if (complete_fx4[`LSU_INDEX]) begin // {
// IF W1 port is also being written, ignore that address
for (i=0; i<=31; i=i+1) begin // {
if (!((i == frf_w1_skip_addr) && frf_w1_valid_even)) begin // {
frf_tmp = `FRF2_EVEN[(mytid*32)+i];
push_delta_fx5 (`FP_OFFSET + (i*2), frf_tmp[31:0], index);
if (!((i == frf_w1_skip_addr) && frf_w1_valid_odd)) begin // {
frf_tmp = `FRF2_ODD[(mytid*32)+i];
push_delta_fx5 (`FP_OFFSET + (i*2)+1, frf_tmp[31:0], index);
// Update ASR/ASI registers
if (complete_fx4) begin // {
push_delta_fx5 (`PSTATE + `CTL_OFFSET,PSTATE_reg,index);
push_delta_fx5 (`HPSTATE + `CTL_OFFSET,HPSTATE_reg,index);
push_delta_fx5 (`PIL + `CTL_OFFSET,PIL_reg,index);
push_delta_fx5 (`TBA + `CTL_OFFSET,{TBA_reg,15'b0},index);
push_delta_fx5 (`GL + `CTL_OFFSET,GL_reg,index);
push_delta_fx5 (`HTBA + `CTL_OFFSET,{HTBA_reg,14'b0},index);
push_delta_fx5 (`VER + `CTL_OFFSET,VER_reg,index);
push_delta_fx5 (`Y + `CTL_OFFSET,Y_reg,index);
push_delta_fx5 (`ASI + `CTL_OFFSET,ASI_reg,index);
push_delta_fx5 (`STICK_CMPR + `CTL_OFFSET,STICK_CMPR_wire,index);
push_delta_fx5 (`HSTICK_CMPR + `CTL_OFFSET,HSTICK_CMPR_wire,index);
push_delta_fx5 (`TICK_CMPR + `CTL_OFFSET,TICK_CMPR_wire,index);
push_delta_fx5 (`CWP + `CTL_OFFSET,CWP_reg,index);
push_delta_fx5 (`CANSAVE + `CTL_OFFSET,CANSAVE_reg,index);
push_delta_fx5 (`CANRESTORE + `CTL_OFFSET,CANRESTORE_reg,index);
push_delta_fx5 (`CLEANWIN + `CTL_OFFSET,CLEANWIN_reg,index);
push_delta_fx5 (`OTHERWIN + `CTL_OFFSET,OTHERWIN_reg,index);
push_delta_fx5 (`WSTATE + `CTL_OFFSET,WSTATE_reg,index);
push_delta_fx5 (`CTXT_PRIM_0+`CTL_OFFSET,CTXT_PRIM_0_reg,index);
push_delta_fx5 (`CTXT_SEC_0+`CTL_OFFSET,CTXT_SEC_0_reg,index);
push_delta_fx5 (`CTXT_PRIM_1+`CTL_OFFSET,CTXT_PRIM_1_reg,index);
push_delta_fx5 (`CTXT_SEC_1+`CTL_OFFSET,CTXT_SEC_1_reg,index);
push_delta_fx5 (`LSU_CONTROL+`CTL_OFFSET,LSU_CONTROL_reg,index);
push_delta_fx5 (`WATCHPOINT_ADDR+`CTL_OFFSET,WATCHPOINT_ADDR_reg,index);
// NOTE - ADD_TSB_CFG will never be used for Axis or Tharas
push_delta_fx5 (`CTXT_Z_TSB_CFG0+`CTL_OFFSET,ctxt_z_tsb_cfg0_reg,index);
push_delta_fx5 (`CTXT_Z_TSB_CFG1+`CTL_OFFSET,ctxt_z_tsb_cfg1_reg,index);
push_delta_fx5 (`CTXT_Z_TSB_CFG2+`CTL_OFFSET,ctxt_z_tsb_cfg2_reg,index);
push_delta_fx5 (`CTXT_Z_TSB_CFG3+`CTL_OFFSET,ctxt_z_tsb_cfg3_reg,index);
push_delta_fx5 (`CTXT_NZ_TSB_CFG0+`CTL_OFFSET,ctxt_nz_tsb_cfg0_reg,index);
push_delta_fx5 (`CTXT_NZ_TSB_CFG1+`CTL_OFFSET,ctxt_nz_tsb_cfg1_reg,index);
push_delta_fx5 (`CTXT_NZ_TSB_CFG2+`CTL_OFFSET,ctxt_nz_tsb_cfg2_reg,index);
push_delta_fx5 (`CTXT_NZ_TSB_CFG3+`CTL_OFFSET,ctxt_nz_tsb_cfg3_reg,index);
// Update GSR for all except write ASR in progess
if (!asi_in_progress) begin // {
push_delta_fx5 (`GSR + `CTL_OFFSET,GSR_wire, index);
// If lsu_complete & fp_complete assert at same time,
// then the fp_complete is the one that will modify the FSR
if (complete_fx4[`LSU_INDEX] & !complete_fw1[`FP_INDEX]) begin
push_delta_fx5 (`FSR+`CTL_OFFSET,FSR_wire,index);
// Non Trap updates of Trap stack & level
if (complete_fx4 && !complete_fx4[`TLU_INDEX]) begin // {
push_delta_fx5 (`TL + `CTL_OFFSET,TL_reg,index);
push_delta_fx5 (`TPC1 + `CTL_OFFSET, TPC1_wire, index);
push_delta_fx5 (`TPC2 + `CTL_OFFSET, TPC2_wire, index);
push_delta_fx5 (`TPC3 + `CTL_OFFSET, TPC3_wire, index);
push_delta_fx5 (`TPC4 + `CTL_OFFSET, TPC4_wire, index);
push_delta_fx5 (`TPC5 + `CTL_OFFSET, TPC5_wire, index);
push_delta_fx5 (`TPC6 + `CTL_OFFSET, TPC6_wire, index);
push_delta_fx5 (`TNPC1 + `CTL_OFFSET, TNPC1_wire, index);
push_delta_fx5 (`TNPC2 + `CTL_OFFSET, TNPC2_wire, index);
push_delta_fx5 (`TNPC3 + `CTL_OFFSET, TNPC3_wire, index);
push_delta_fx5 (`TNPC4 + `CTL_OFFSET, TNPC4_wire, index);
push_delta_fx5 (`TNPC5 + `CTL_OFFSET, TNPC5_wire, index);
push_delta_fx5 (`TNPC6 + `CTL_OFFSET, TNPC6_wire, index);
push_delta_fx5 (`TSTATE1 + `CTL_OFFSET, TSTATE1_wire, index);
push_delta_fx5 (`TSTATE2 + `CTL_OFFSET, TSTATE2_wire, index);
push_delta_fx5 (`TSTATE3 + `CTL_OFFSET, TSTATE3_wire, index);
push_delta_fx5 (`TSTATE4 + `CTL_OFFSET, TSTATE4_wire, index);
push_delta_fx5 (`TSTATE5 + `CTL_OFFSET, TSTATE5_wire, index);
push_delta_fx5 (`TSTATE6 + `CTL_OFFSET, TSTATE6_wire, index);
push_delta_fx5 (`HTSTATE1 + `CTL_OFFSET, HTSTATE1_wire, index);
push_delta_fx5 (`HTSTATE2 + `CTL_OFFSET, HTSTATE2_wire, index);
push_delta_fx5 (`HTSTATE3 + `CTL_OFFSET, HTSTATE3_wire, index);
push_delta_fx5 (`HTSTATE4 + `CTL_OFFSET, HTSTATE4_wire, index);
push_delta_fx5 (`HTSTATE5 + `CTL_OFFSET, HTSTATE5_wire, index);
push_delta_fx5 (`HTSTATE6 + `CTL_OFFSET, HTSTATE6_wire, index);
push_delta_fx5 (`TT1 + `CTL_OFFSET, TT1_wire, index);
push_delta_fx5 (`TT2 + `CTL_OFFSET, TT2_wire, index);
push_delta_fx5 (`TT3 + `CTL_OFFSET, TT3_wire, index);
push_delta_fx5 (`TT4 + `CTL_OFFSET, TT4_wire, index);
push_delta_fx5 (`TT5 + `CTL_OFFSET, TT5_wire, index);
push_delta_fx5 (`TT6 + `CTL_OFFSET, TT6_wire, index);
//----------------------------------------------------------
// Stage FB of delta pipeline
index = delta_fx5[`NEXT_INDEX];
// Pipeline previous stage
for (i=0; i<=delta_fx5[`NEXT_INDEX]; i=i+1) begin // {
delta_fb[i] <= delta_fx5[i];
if (complete_fx5[`ASI_INDEX]) begin // {
push_delta_fb (`GSR + `CTL_OFFSET,GSR_wire, index);
//----------------------------------------------------------
// Stage FW of delta pipeline
index = delta_fb[`NEXT_INDEX];
// Pipeline previous stage
for (i=0; i<=delta_fb[`NEXT_INDEX]; i=i+1) begin // {
delta_fw[i] <= delta_fb[i];
// Capture CWP_reg for SAVE/RESTORE
delta_fw[`CWP_INDEX] <= CWP_reg;
if (complete_fb[`TLU_INDEX]) begin
if (mytid <= 3) begin // {
for (i=0; i<=31; i=i+1) begin // {
push_delta_fw (i,`IRF2_EXU0[(remap(i,oddwin)+irf_offset)],index);
for (i=0; i<=31; i=i+1) begin // {
push_delta_fw (i,`IRF2_EXU1[(remap(i,oddwin)+irf_offset)],index);
// Update FRF2 - Idivs use W2.
if (complete_fb[`IDIV_INDEX]) begin // {
// IF W1 port is also being written, ignore that address
for (i=0; i<=31; i=i+1) begin // {
if (!((i == frf_w1_skip_addr) && frf_w1_valid_even)) begin // {
frf_tmp = `FRF2_EVEN[(mytid*32)+i];
push_delta_fw (`FP_OFFSET + (i*2), frf_tmp[31:0], index);
if (!((i == frf_w1_skip_addr) && frf_w1_valid_odd)) begin // {
frf_tmp = `FRF2_ODD[(mytid*32)+i];
push_delta_fw (`FP_OFFSET + (i*2)+1,frf_tmp[31:0], index);
//----------------------------------------------------------
// Stage FW1 of delta pipeline
index = delta_fw[`NEXT_INDEX];
// Pipeline previous stage
for (i=0; i<=delta_fw[`NEXT_INDEX]; i=i+1) begin // {
delta_fw1[i] <= delta_fw[i];
// Update FRF2 - FPops use W1 port.
if (fp_complete) begin // {
// IF W2 port is also being written, ignore that address
for (i=0; i<=31; i=i+1) begin // {
if (!((i == frf_w2_skip_addr) && frf_w2_valid_even)) begin // {
frf_tmp = `FRF2_EVEN[(mytid*32)+i];
push_delta_fw1 (`FP_OFFSET + (i*2), frf_tmp[31:0], index);
if (!((i == frf_w2_skip_addr) && frf_w2_valid_odd)) begin // {
frf_tmp = `FRF2_ODD[(mytid*32)+i];
push_delta_fw1 (`FP_OFFSET + (i*2)+1,frf_tmp[31:0], index);
if (complete_fw[`IMUL_INDEX]|complete_fw[`IDIV_INDEX]) begin
push_delta_fw1 (`CCR+`CTL_OFFSET,CCR_reg,index);
push_delta_fw1 (`Y+`CTL_OFFSET,Y_reg,index);
push_delta_fw1 (`CWP+`CTL_OFFSET,CWP_reg,index);
push_delta_fw1 (`CANSAVE+`CTL_OFFSET,CANSAVE_reg,index);
push_delta_fw1 (`CANRESTORE+`CTL_OFFSET,CANRESTORE_reg,index);
push_delta_fw1 (`CLEANWIN+`CTL_OFFSET,CLEANWIN_reg,index);
push_delta_fw1 (`OTHERWIN+`CTL_OFFSET,OTHERWIN_reg,index);
push_delta_fw1 (`WSTATE+`CTL_OFFSET,WSTATE_reg,index);
if (complete_fw[`TLU_INDEX]) begin // {
push_delta_fw1 (`TL + `CTL_OFFSET,TL_reg,index);
push_delta_fw1 (`TPC1 + `CTL_OFFSET, TPC1_wire, index);
push_delta_fw1 (`TPC2 + `CTL_OFFSET, TPC2_wire, index);
push_delta_fw1 (`TPC3 + `CTL_OFFSET, TPC3_wire, index);
push_delta_fw1 (`TPC4 + `CTL_OFFSET, TPC4_wire, index);
push_delta_fw1 (`TPC5 + `CTL_OFFSET, TPC5_wire, index);
push_delta_fw1 (`TPC6 + `CTL_OFFSET, TPC6_wire, index);
push_delta_fw1 (`TNPC1 + `CTL_OFFSET, TNPC1_wire, index);
push_delta_fw1 (`TNPC2 + `CTL_OFFSET, TNPC2_wire, index);
push_delta_fw1 (`TNPC3 + `CTL_OFFSET, TNPC3_wire, index);
push_delta_fw1 (`TNPC4 + `CTL_OFFSET, TNPC4_wire, index);
push_delta_fw1 (`TNPC5 + `CTL_OFFSET, TNPC5_wire, index);
push_delta_fw1 (`TNPC6 + `CTL_OFFSET, TNPC6_wire, index);
push_delta_fw1 (`TSTATE1 + `CTL_OFFSET, TSTATE1_wire, index);
push_delta_fw1 (`TSTATE2 + `CTL_OFFSET, TSTATE2_wire, index);
push_delta_fw1 (`TSTATE3 + `CTL_OFFSET, TSTATE3_wire, index);
push_delta_fw1 (`TSTATE4 + `CTL_OFFSET, TSTATE4_wire, index);
push_delta_fw1 (`TSTATE5 + `CTL_OFFSET, TSTATE5_wire, index);
push_delta_fw1 (`TSTATE6 + `CTL_OFFSET, TSTATE6_wire, index);
push_delta_fw1 (`HTSTATE1 + `CTL_OFFSET, HTSTATE1_wire, index);
push_delta_fw1 (`HTSTATE2 + `CTL_OFFSET, HTSTATE2_wire, index);
push_delta_fw1 (`HTSTATE3 + `CTL_OFFSET, HTSTATE3_wire, index);
push_delta_fw1 (`HTSTATE4 + `CTL_OFFSET, HTSTATE4_wire, index);
push_delta_fw1 (`HTSTATE5 + `CTL_OFFSET, HTSTATE5_wire, index);
push_delta_fw1 (`HTSTATE6 + `CTL_OFFSET, HTSTATE6_wire, index);
push_delta_fw1 (`TT1 + `CTL_OFFSET, TT1_wire, index);
push_delta_fw1 (`TT2 + `CTL_OFFSET, TT2_wire, index);
push_delta_fw1 (`TT3 + `CTL_OFFSET, TT3_wire, index);
push_delta_fw1 (`TT4 + `CTL_OFFSET, TT4_wire, index);
push_delta_fw1 (`TT5 + `CTL_OFFSET, TT5_wire, index);
push_delta_fw1 (`TT6 + `CTL_OFFSET, TT6_wire, index);
//----------------------------------------------------------
// Stage FW2 of delta pipeline
index = delta_fw1[`NEXT_INDEX];
// Pipeline previous stage
for (i=0; i<=delta_fw1[`NEXT_INDEX]; i=i+1) begin // {
delta_fw2[i] <= delta_fw1[i];
delta_fw2[`TIME_INDEX] <= $time;
// Update Registers that may change asynchronously
// If sstep was already sent by another module,
// don't capture until the next sstep
if (complete_fw1 && !`NASTOP.sstep_early[mytnum]) begin // {
if ((complete_fw1[`ASI_INDEX]|complete_fw1[`LSU_INDEX]) & asi_rdwr_hintp)
push_delta_fw2 (`HINTP + `CTL_OFFSET,asi_updated_hintp,index);
push_delta_fw2 (`HINTP + `CTL_OFFSET,HINTP_reg,index);
if ((complete_fw1[`ASI_INDEX]|complete_fw1[`LSU_INDEX]) & asi_rdwr_softint)
push_delta_fw2 (`SOFTINT + `CTL_OFFSET,asi_updated_softint,index);
push_delta_fw2 (`SOFTINT + `CTL_OFFSET,rd_SOFTINT_reg,index);
if (complete_fw1[`IMUL_INDEX] |
complete_fw1[`IDIV_INDEX]) begin // {
if (mytid <= 3) begin // {
for (i=0; i<=31; i=i+1) begin // {
push_delta_fw2 (i,`IRF2_EXU0[(remap(i,oddwin)+irf_offset)],index);
for (i=0; i<=31; i=i+1) begin // {
push_delta_fw2 (i,`IRF2_EXU1[(remap(i,oddwin)+irf_offset)],index);
// Update FRF2 - fdivs and Imuls use W2 port
if (complete_fw1[`IMUL_INDEX] |
complete_fw1[`FDIV_INDEX] ) begin // {
// IF W1 port is also being written, ignore that address
for (i=0; i<=31; i=i+1) begin // {
if (!((i == frf_w1_skip_addr) && frf_w1_valid_even)) begin // {
frf_tmp = `FRF2_EVEN[(mytid*32)+i];
push_delta_fw2 (`FP_OFFSET + (i*2), frf_tmp[31:0], index);
if (!((i == frf_w1_skip_addr) && frf_w1_valid_odd)) begin // {
frf_tmp = `FRF2_ODD[(mytid*32)+i];
push_delta_fw2 (`FP_OFFSET + (i*2)+1,frf_tmp[31:0], index);
if (complete_fw1[`FP_INDEX] |
complete_fw1[`TLU_INDEX] |
complete_fw1[`FDIV_INDEX]) begin
push_delta_fw2 (`FSR+`CTL_OFFSET,FSR_wire,index);
push_delta_fw2 (`I_TAG_ACC+`CTL_OFFSET,itagacc_fw2,index);
push_delta_fw2 (`D_TAG_ACC+`CTL_OFFSET,dtagacc_fw2,index);
push_delta_fw2 (`DSFAR+`CTL_OFFSET,dsfar_fw2,index);
//----------------------------------------------------------
// Stage FW2 of delta pipeline - for signals that change FW+2 !!
index = delta_fw2[`NEXT_INDEX];
// Since FPRS for FPops may have been corrupted by o-o-o loads:
// If fprs_fw2 is != fprs_reg & there are loads in the pipeline
// then assume loads have already updated fprs.
// In that case, create our own fprs_reg by using the valids and
// skip_addr and copy of fprs for this op..
if (complete_fw2[`FP_INDEX] && frf_w1_valid_fw2) begin // {
// o-o-o load has changed fprs already - use dummy
if ((fprs_fw2 != FPRS_reg) && (complete_fw1[`LSU_INDEX] |
complete_fw[`LSU_INDEX] | complete_fb[`LSU_INDEX] |
complete_fx5[`LSU_INDEX] )) begin // {
dummy_fprs = read_prev(`FPRS + `CTL_OFFSET);
dummy_fprs = dummy_fprs |
{1'b0, frf_w1_skip_addr4_fw2, ~frf_w1_skip_addr4_fw2};
push_delta_fw2_async (`FPRS + `CTL_OFFSET,dummy_fprs,index);
// o-o-o load has NOT changed fprs already - use it
push_delta_fw2_async (`FPRS + `CTL_OFFSET,FPRS_reg,index);
// Load FPRS for loads/reads as prev|fprs_fb ..
// since loads may only 'set' bits, not clear ...
else if (complete_fw2[`LSU_INDEX]) begin // {
dummy_fprs = read_prev(`FPRS + `CTL_OFFSET);
dummy_fprs = dummy_fprs | fprs_fw1;
push_delta_fw2_async (`FPRS +`CTL_OFFSET,dummy_fprs,index);
// Load FPRS for store ASI or FDIV
// FDIV can update FPRS on w1 or w2,
// but the pipe is stalled behind it so no o-o-o loads.
else if ((complete_fw2[`ASI_INDEX]) ||
(complete_fw2[`FDIV_INDEX])) begin // {
push_delta_fw2_async (`FPRS + `CTL_OFFSET,FPRS_reg,index);
//----------------------------------------------------------
// Store latest values into delta
index = delta_prev[`NEXT_INDEX];
if (in_wmr & ~`SPC2.rst_wmr_protect) begin // {
push_delta_prev_async ( `PC+`CTL_OFFSET,{16'b0,pc_fw2|1},index);
push_delta_prev_async ( `PC+`CTL_OFFSET,{16'b0,pc_fw2},index);
//----------------------------------------------------------
//----------------------------------------------------------
// Compare with current state and capture if different
if (act_value != read_prev(id)) begin // { // Diff vs prev
calc_cwp(CWP_reg,id,win,type); // special case for 1st stage
write_prev(id,act_value);
delta_fx4[next] <= {type,win,id,act_value};
delta_fx4[next] <= 77'hx;
delta_fx4[`NEXT_INDEX] <= next;
if (`PARGS.axis_debug_on) begin
$display("AXIS: T%0d pc=%h id=%0d type=%0h win=%0h value=%h ts=%0d",
mytnum,PC_reg,id,type,win,act_value,$time);
if (`PARGS.axis_debug_on) begin
$display("AXIS: T%0d pc=%h id=%0d type=%0h win=%0h value=%h ts=%0d",
mytnum,PC_reg,id,type,win,act_value,$time);
//----------------------------------------------------------
// Compare with current state and capture if different
if (act_value != read_prev(id)) begin // { // Diff vs prev
calc_cwp(delta_fx4[`CWP_INDEX],id,win,type);
write_prev(id,act_value);
delta_fx5[next] <= {type,win,id,act_value};
delta_fx5[next] <= 77'hx;
delta_fx5[`NEXT_INDEX] <= next;
if (`PARGS.axis_debug_on) begin
$display("AXIS: T%0d pc=%h id=%0d type=%0h win=%0h value=%h ts=%0d",
mytnum,pc_fx4,id,type,win,act_value,$time);
calc_cwp(cwp_fx4,id,win,type);
if (`PARGS.axis_debug_on) begin
$display("AXIS: T%0d pc=%h id=%0d type=%0h win=%0h value=%h ts=%0d",
mytnum,pc_fx4,id,type,win,act_value,$time);
//----------------------------------------------------------
// Compare with current state and capture if different
if (act_value != read_prev(id)) begin // { // Diff vs prev
calc_cwp(delta_fx5[`CWP_INDEX],id,win,type);
write_prev(id,act_value);
delta_fb[next] <= {type,win,id,act_value};
delta_fb[`NEXT_INDEX] <= next;
if (`PARGS.axis_debug_on) begin
$display("AXIS: T%0d pc=%h id=%0d type=%0h win=%0h value=%h ts=%0d",
mytnum,pc_fx5,id,type,win,act_value,$time);
calc_cwp(cwp_fx5,id,win,type);
if (`PARGS.axis_debug_on) begin
$display("AXIS: T%0d pc=%h id=%0d type=%0h win=%0h value=%h ts=%0d",
mytnum,pc_fx5,id,type,win,act_value,$time);
//----------------------------------------------------------
// Compare with current state and capture if different
if (act_value != read_prev(id)) begin // { // Diff vs prev
calc_cwp(delta_fb[`CWP_INDEX],id,win,type);
write_prev(id,act_value);
delta_fw[next] <= {type,win,id,act_value};
delta_fw[`NEXT_INDEX] <= next;
if (`PARGS.axis_debug_on) begin
$display("AXIS: T%0d pc=%h id=%0d type=%0h win=%0h value=%h ts=%0d",
mytnum,pc_fb,id,type,win,act_value,$time);
calc_cwp(cwp_fb[`CWP_INDEX],id,win,type);
if (`PARGS.axis_debug_on) begin
$display("AXIS: T%0d pc=%h id=%0d type=%0h win=%0h value=%h ts=%0d",
mytnum,pc_fb,id,type,win,act_value,$time);
//----------------------------------------------------------
// Compare with current state and capture if different
if (act_value != read_prev(id)) begin // { // Diff vs prev
calc_cwp(delta_fw[`CWP_INDEX],id,win,type);
write_prev(id,act_value);
delta_fw1[next] <= {type,win,id,act_value};
delta_fw1[next] <= 77'hx;
delta_fw1[`NEXT_INDEX] <= next;
if (`PARGS.axis_debug_on) begin
$display("AXIS: T%0d pc=%h id=%0d type=%0h win=%0h value=%h ts=%0d",
mytnum,pc_fw,id,type,win,act_value,$time);
calc_cwp(cwp_fw,id,win,type);
if (`PARGS.axis_debug_on) begin
$display("AXIS: T%0d pc=%h id=%0d type=%0h win=%0h value=%h ts=%0d",
mytnum,pc_fw,id,type,win,act_value,$time);
//----------------------------------------------------------
// Compare with current state and capture if different
if (act_value != read_prev(id)) begin // { // Diff vs prev
calc_cwp(delta_fw1[`CWP_INDEX],id,win,type);
write_prev(id,act_value);
delta_fw2[next] <= {type,win,id,act_value};
delta_fw2[next] <= 77'hx;
delta_fw2[`NEXT_INDEX] <= next;
if (`PARGS.axis_debug_on) begin
$display("AXIS: T%0d pc=%h id=%0d type=%0h win=%0h value=%h ts=%0d",
mytnum,pc_fw1,id,type,win,act_value,$time);
calc_cwp(cwp_fw1,id,win,type);
if (`PARGS.axis_debug_on) begin
$display("AXIS: T%0d pc=%h id=%0d type=%0h win=%0h value=%h ts=%0d",
mytnum,pc_fw1,id,type,win,act_value,$time);
//----------------------------------------------------------
// Compare with current state and capture if different
// This is for late changing registers
// Use blocking assignments.
task push_delta_fw2_async;
if (act_value != read_prev(id)) begin // { // Diff vs prev
calc_cwp(delta_fw2[`CWP_INDEX],id,win,type);
write_prev_async(id,act_value);
delta_fw2[next] = {type,win,id,act_value};
delta_fw2[`NEXT_INDEX] = next;
if (`PARGS.axis_debug_on) begin
$display("AXIS: T%0d pc=%h id=%0d type=%0h win=%0h value=%h ts=%0d",
mytnum,pc_fw1,id,type,win,act_value,$time);
calc_cwp(cwp_fw2,id,win,type);
if (`PARGS.axis_debug_on) begin
$display("AXIS: T%0d pc=%h id=%0d type=%0h win=%0h value=%h ts=%0d",
mytnum,pc_fw1,id,type,win,act_value,$time);
//----------------------------------------------------------
// Compare with current state and capture if different
// Use blocking assignments so that push_simics will work
task push_delta_prev_async;
if (act_value != read_prev(id)) begin // { // Diff vs prev
calc_cwp(delta_prev[`CWP_INDEX],id,win,type);
write_prev_async(id,act_value);
delta_prev[next] = {type,win,id,act_value};
delta_prev[next] = 77'hx;
delta_prev[`NEXT_INDEX] = next;
if (`PARGS.axis_debug_on) begin
$display("AXIS: T%0d pc=%h id=%0d type=%0h win=%0h value=%h ts=%0d",
mytnum,pc_last,id,type,win,act_value,$time);
if (`PARGS.axis_debug_on) begin
calc_cwp(cwp_last,id,win,type);
$display("AXIS: T%0d pc=%h id=%0d type=%0h win=%0h value=%h ts=%0d",
mytnum,pc_last,id,type,win,act_value,$time);
//----------------------------------------------------------
// prev of delta pipeline
// Pipeline previous stage
for (i=0; i<=delta_fw2[`NEXT_INDEX]; i=i+1) begin // {
delta_prev[i] <= delta_fw2[i];
//----------------------------------------------------------
//----------------------------------------------------------
// Sort delta list in register ID order, then push to simics
// Or print deltas if sas check disabled ..
// Order of registers reported to simics must be:
// Global 0-7 aka prev_reg[0:7]
// Window 8-23 aka prev_reg[8:23]
// Floating 0-63 aka prev_reg[200:263]
// Control 32-143 aka prev_reg[32:143]
act_level = delta_prev[`GL_INDEX]; // GL
time_fw2 = delta_prev[`TIME_INDEX]; // Finish time
for (i=`FIRST_INDEX; i<delta_prev[`NEXT_INDEX]; i=i+1) begin // {
{type,win,regnum,value} = delta_prev[i];
if (regnum<=7) begin // {
if (`PARGS.nas_check_on) begin // {
`ACT_STATUS = $queue(`ACT_QUEUE, `PUSH_Q, mytnum, time_fw2, act_type,
act_level, regnum, value);
else if (`PARGS.show_delta_on) begin // {
`NASTOP.print_delta (mytnum,act_type,win,regnum,value);
else if (regnum<=23) begin // { %o0-%l7, %l0-%l7
if (`PARGS.nas_check_on) begin // {
`ACT_STATUS = $queue(`ACT_QUEUE, `PUSH_Q, mytnum, time_fw2, act_type,
else if (`PARGS.show_delta_on) begin // {
`NASTOP.print_delta (mytnum,act_type,win,regnum,value);
else if (regnum<=31) begin // { %i0-%i7
if (`PARGS.nas_check_on) begin // {
`ACT_STATUS = $queue(`ACT_QUEUE, `PUSH_Q, mytnum, time_fw2, act_type,
win, (regnum-16), value);
else if (`PARGS.show_delta_on) begin // {
`NASTOP.print_delta (mytnum,act_type,win,(regnum-16),value);
else if (regnum<=(64+`FP_OFFSET)) begin // {
if (`PARGS.nas_check_on) begin // {
`ACT_STATUS = $queue(`ACT_QUEUE, `PUSH_Q, mytnum, time_fw2, act_type,
(regnum-`FP_OFFSET), value);
else if (`PARGS.show_delta_on) begin // {
`NASTOP.print_delta (mytnum,act_type,win,(regnum-`FP_OFFSET),value);
else if ((regnum>=(32+`CTL_OFFSET))&(regnum<=(143+`CTL_OFFSET))) begin // {
if (`PARGS.nas_check_on) begin // {
`ACT_STATUS = $queue(`ACT_QUEUE, `PUSH_Q, mytnum, time_fw2, act_type,
(regnum-`CTL_OFFSET), value);
else if (`PARGS.show_delta_on) begin // {
`NASTOP.print_delta (mytnum,act_type,win,(regnum-`CTL_OFFSET),value);
`PR_ERROR ("nas", `ERROR, " - T%0d Bench problem. push_simics has bad regnum", mytnum);
value = delta_prev[`OPCODE_INDEX];
if (`PARGS.nas_check_on) begin // {
`ACT_STATUS = $queue(`ACT_QUEUE, `PUSH_Q, mytnum, time_fw2, act_type,
else if (`PARGS.show_delta_on) begin // {
`NASTOP.print_delta (mytnum,act_type,win,regnum,value);
// Push End of Instruction Delimiter
// The value field for this PUSH equals the PC for this instruction.
// so that printing to the logfile works correctly.
// prev_reg[`PC] = current instruction PC
// delta_reg[`PC] = PC at end of current instruction
pc = delta_prev[`PC_INDEX];
if (`PARGS.nas_check_on) begin // {
`ACT_STATUS = $queue(`ACT_QUEUE, `PUSH_Q, mytnum, time_fw2, act_type,
delta_fw2[`CWP_INDEX], `END_INSTR, pc);
else if (`PARGS.show_delta_on) begin // {
`NASTOP.print_delta (mytnum,act_type,delta_fw2[`CWP_INDEX],`END_INSTR,0);
if (! `PARGS.nas_check_on) begin // {
`PR_NORMAL ("nas", `NORMAL, "@%0d T%0d %h (Unchecked..)",
$time, mytnum, {16'b0,pc});
`TOP.last_act_cycle = `TOP.core_cycle_cnt; //$time;
`TOP.th_last_act_cycle[mytnum] = `TOP.last_act_cycle;
if (! `PARGS.nas_check_on) begin // {
`TOP.last_act_cycle = `TOP.core_cycle_cnt; //$time;
`TOP.th_last_act_cycle[mytnum] = `TOP.last_act_cycle;
//----------------------------------------------------------
// Save current window to previous window, then copy new window to current window
// Save current window to Old window
// Copy New window to current window
//----------------------------------------------------------
// Save current global to previous global, then copy new global to current global
// Save current global to Old global
// Copy New global current global
//----------------------------------------------------------
// Return window number and register type based on cwp and regnum as input
else if (id<=23) begin // {
else if (id<=31) begin // {
else if (id<=(64+`FP_OFFSET)) begin // {
//----------------------------------------------------------
// Check for bad signal values
8'b10000000: ; // good value
`PR_ERROR ("nas", `ERROR, " - T%0d More than one instruction retired in a single cycle for this thread.",
$write("\t\t\t\t Instructions - ");
if (complete_fw2[`EXU_INDEX]) $write("EXU op, ");
if (complete_fw2[`FP_INDEX]) $write("FP op, ");
if (complete_fw2[`LSU_INDEX]) $write("LSU op, ");
if (complete_fw2[`IMUL_INDEX]) $write("IMUL op, ");
if (complete_fw2[`IDIV_INDEX]) $write("IDIV op, ");
if (complete_fw2[`FDIV_INDEX]) $write("FDIV op, ");
if (complete_fw2[`TLU_INDEX]) $write("TLU op, ");
if (complete_fw2[`ASI_INDEX]) $write("ASI op, ");
$write(" complete_fw2 = %b \n",complete_fw2);
// This check only works if diags are written properly.
// For example, if a diag writes to one of these registers using wrpr,
// then this check must be disabled using plusarg.
// CANSAVE + CANRESTORE + OTHERWIN = NWINDOWS-2 (per Sparc V9)
if (`PARGS.win_check_on) begin // {
if (complete_fw2 & ((CANSAVE_reg + CANRESTORE_reg + OTHERWIN_reg) != 6)) begin // {
`PR_ERROR ("nas", `ERROR, "ERROR - T%0d Bad Values for window registers.", mytnum);
`PR_ERROR ("nas", `ERROR, "- CANSAVE = %0d CANRESTORE = %0d OTHERWIN = %0d",
CANSAVE_reg, CANRESTORE_reg,OTHERWIN_reg);
//----------------------------------------------------------
//----------------------------------------------------------
reg [`DELTA_WIDTH:0] temp1, temp2;
last = delta_prev[`NEXT_INDEX]-1;
for (i=`FIRST_INDEX; i <= last; i=i+1) begin // {
for (j=`FIRST_INDEX; j < last; j=j+1) begin // {
temp1 = delta_prev[j]; temp2 = delta_prev[j+1];
if (temp1[76:64] > temp2[76:64]) begin // {
delta_prev[j] = temp2; delta_prev [j+1] = temp1;
//----------------------------------------------------------
//----------------------------------------------------------
// Print one entry in delta_* array
input [`DELTA_WIDTH:0] delta_entry;
reg [(20*8)-1:0] type_str;
reg [(20*8)-1:0] regname;
{type,win,id,act_value} = delta_entry;
`NASTOP.get_regname(mytnum,type_str,win,id,regname);
`PR_NORMAL ("nas", `NORMAL, "type=%0s win=%0d RegID=%0d %0s=%h",
type_str,win,id,regname,act_value);
//----------------------------------------------------------
// Write Value to prev_reg using id as index (non-blocking)
8'd0: prev_reg0 <= value;
8'd1: prev_reg1 <= value;
8'd2: prev_reg2 <= value;
8'd3: prev_reg3 <= value;
8'd4: prev_reg4 <= value;
8'd5: prev_reg5 <= value;
8'd6: prev_reg6 <= value;
8'd7: prev_reg7 <= value;
8'd8: prev_reg8 <= value;
8'd9: prev_reg9 <= value;
8'd10: prev_reg10 <= value;
8'd11: prev_reg11 <= value;
8'd12: prev_reg12 <= value;
8'd13: prev_reg13 <= value;
8'd14: prev_reg14 <= value;
8'd15: prev_reg15 <= value;
8'd16: prev_reg16 <= value;
8'd17: prev_reg17 <= value;
8'd18: prev_reg18 <= value;
8'd19: prev_reg19 <= value;
8'd20: prev_reg20 <= value;
8'd21: prev_reg21 <= value;
8'd22: prev_reg22 <= value;
8'd23: prev_reg23 <= value;
8'd24: prev_reg24 <= value;
8'd25: prev_reg25 <= value;
8'd26: prev_reg26 <= value;
8'd27: prev_reg27 <= value;
8'd28: prev_reg28 <= value;
8'd29: prev_reg29 <= value;
8'd30: prev_reg30 <= value;
8'd31: prev_reg31 <= value;
8'd32: prev_reg32 <= value;
8'd33: prev_reg33 <= value;
8'd34: prev_reg34 <= value;
8'd35: prev_reg35 <= value;
8'd36: prev_reg36 <= value;
8'd37: prev_reg37 <= value;
8'd38: prev_reg38 <= value;
8'd39: prev_reg39 <= value;
8'd40: prev_reg40 <= value;
8'd41: prev_reg41 <= value;
8'd42: prev_reg42 <= value;
8'd43: prev_reg43 <= value;
8'd44: prev_reg44 <= value;
8'd45: prev_reg45 <= value;
8'd46: prev_reg46 <= value;
8'd47: prev_reg47 <= value;
8'd48: prev_reg48 <= value;
8'd49: prev_reg49 <= value;
8'd50: prev_reg50 <= value;
8'd51: prev_reg51 <= value;
8'd52: prev_reg52 <= value;
8'd53: prev_reg53 <= value;
8'd54: prev_reg54 <= value;
8'd55: prev_reg55 <= value;
8'd56: prev_reg56 <= value;
8'd57: prev_reg57 <= value;
8'd58: prev_reg58 <= value;
8'd59: prev_reg59 <= value;
8'd60: prev_reg60 <= value;
8'd61: prev_reg61 <= value;
8'd62: prev_reg62 <= value;
8'd63: prev_reg63 <= value;
8'd64: prev_reg64 <= value;
8'd65: prev_reg65 <= value;
8'd66: prev_reg66 <= value;
8'd67: prev_reg67 <= value;
8'd68: prev_reg68 <= value;
8'd69: prev_reg69 <= value;
8'd70: prev_reg70 <= value;
8'd71: prev_reg71 <= value;
8'd72: prev_reg72 <= value;
8'd73: prev_reg73 <= value;
8'd74: prev_reg74 <= value;
8'd75: prev_reg75 <= value;
8'd76: prev_reg76 <= value;
8'd77: prev_reg77 <= value;
8'd78: prev_reg78 <= value;
8'd79: prev_reg79 <= value;
8'd80: prev_reg80 <= value;
8'd81: prev_reg81 <= value;
8'd82: prev_reg82 <= value;
8'd83: prev_reg83 <= value;
8'd84: prev_reg84 <= value;
8'd85: prev_reg85 <= value;
8'd86: prev_reg86 <= value;
8'd87: prev_reg87 <= value;
8'd88: prev_reg88 <= value;
8'd89: prev_reg89 <= value;
8'd90: prev_reg90 <= value;
8'd91: prev_reg91 <= value;
8'd92: prev_reg92 <= value;
8'd93: prev_reg93 <= value;
8'd94: prev_reg94 <= value;
8'd95: prev_reg95 <= value;
8'd96: prev_reg96 <= value;
8'd97: prev_reg97 <= value;
8'd98: prev_reg98 <= value;
8'd99: prev_reg99 <= value;
8'd100: prev_reg100 <= value;
8'd101: prev_reg101 <= value;
8'd102: prev_reg102 <= value;
8'd103: prev_reg103 <= value;
8'd104: prev_reg104 <= value;
8'd105: prev_reg105 <= value;
8'd106: prev_reg106 <= value;
8'd107: prev_reg107 <= value;
8'd108: prev_reg108 <= value;
8'd109: prev_reg109 <= value;
8'd110: prev_reg110 <= value;
8'd111: prev_reg111 <= value;
8'd112: prev_reg112 <= value;
8'd113: prev_reg113 <= value;
8'd114: prev_reg114 <= value;
8'd115: prev_reg115 <= value;
8'd116: prev_reg116 <= value;
8'd117: prev_reg117 <= value;
8'd118: prev_reg118 <= value;
8'd119: prev_reg119 <= value;
8'd120: prev_reg120 <= value;
8'd121: prev_reg121 <= value;
8'd122: prev_reg122 <= value;
8'd123: prev_reg123 <= value;
8'd124: prev_reg124 <= value;
8'd125: prev_reg125 <= value;
8'd126: prev_reg126 <= value;
8'd127: prev_reg127 <= value;
8'd128: prev_reg128 <= value;
8'd129: prev_reg129 <= value;
8'd130: prev_reg130 <= value;
8'd131: prev_reg131 <= value;
8'd132: prev_reg132 <= value;
8'd133: prev_reg133 <= value;
8'd134: prev_reg134 <= value;
8'd135: prev_reg135 <= value;
8'd136: prev_reg136 <= value;
8'd137: prev_reg137 <= value;
8'd138: prev_reg138 <= value;
8'd139: prev_reg139 <= value;
8'd140: prev_reg140 <= value;
8'd141: prev_reg141 <= value;
8'd142: prev_reg142 <= value;
8'd143: prev_reg143 <= value;
8'd144: prev_reg144 <= value;
8'd145: prev_reg145 <= value;
8'd146: prev_reg146 <= value;
8'd147: prev_reg147 <= value;
8'd148: prev_reg148 <= value;
8'd149: prev_reg149 <= value;
8'd150: prev_reg150 <= value;
8'd151: prev_reg151 <= value;
8'd152: prev_reg152 <= value;
8'd153: prev_reg153 <= value;
8'd154: prev_reg154 <= value;
8'd155: prev_reg155 <= value;
8'd156: prev_reg156 <= value;
8'd157: prev_reg157 <= value;
8'd158: prev_reg158 <= value;
8'd159: prev_reg159 <= value;
8'd160: prev_reg160 <= value;
8'd161: prev_reg161 <= value;
8'd162: prev_reg162 <= value;
8'd163: prev_reg163 <= value;
8'd164: prev_reg164 <= value;
8'd165: prev_reg165 <= value;
8'd166: prev_reg166 <= value;
8'd167: prev_reg167 <= value;
8'd168: prev_reg168 <= value;
8'd169: prev_reg169 <= value;
8'd170: prev_reg170 <= value;
8'd171: prev_reg171 <= value;
8'd172: prev_reg172 <= value;
8'd173: prev_reg173 <= value;
8'd174: prev_reg174 <= value;
8'd175: prev_reg175 <= value;
8'd176: prev_reg176 <= value;
8'd177: prev_reg177 <= value;
8'd178: prev_reg178 <= value;
8'd179: prev_reg179 <= value;
8'd180: prev_reg180 <= value;
8'd181: prev_reg181 <= value;
8'd182: prev_reg182 <= value;
8'd183: prev_reg183 <= value;
8'd184: prev_reg184 <= value;
8'd185: prev_reg185 <= value;
8'd186: prev_reg186 <= value;
8'd187: prev_reg187 <= value;
8'd188: prev_reg188 <= value;
8'd189: prev_reg189 <= value;
8'd190: prev_reg190 <= value;
8'd191: prev_reg191 <= value;
8'd192: prev_reg192 <= value;
8'd193: prev_reg193 <= value;
8'd194: prev_reg194 <= value;
8'd195: prev_reg195 <= value;
8'd196: prev_reg196 <= value;
8'd197: prev_reg197 <= value;
8'd198: prev_reg198 <= value;
8'd199: prev_reg199 <= value;
8'd200: prev_reg200 <= value;
8'd201: prev_reg201 <= value;
8'd202: prev_reg202 <= value;
8'd203: prev_reg203 <= value;
8'd204: prev_reg204 <= value;
8'd205: prev_reg205 <= value;
8'd206: prev_reg206 <= value;
8'd207: prev_reg207 <= value;
8'd208: prev_reg208 <= value;
8'd209: prev_reg209 <= value;
8'd210: prev_reg210 <= value;
8'd211: prev_reg211 <= value;
8'd212: prev_reg212 <= value;
8'd213: prev_reg213 <= value;
8'd214: prev_reg214 <= value;
8'd215: prev_reg215 <= value;
8'd216: prev_reg216 <= value;
8'd217: prev_reg217 <= value;
8'd218: prev_reg218 <= value;
8'd219: prev_reg219 <= value;
8'd220: prev_reg220 <= value;
8'd221: prev_reg221 <= value;
8'd222: prev_reg222 <= value;
8'd223: prev_reg223 <= value;
8'd224: prev_reg224 <= value;
8'd225: prev_reg225 <= value;
8'd226: prev_reg226 <= value;
8'd227: prev_reg227 <= value;
8'd228: prev_reg228 <= value;
8'd229: prev_reg229 <= value;
8'd230: prev_reg230 <= value;
8'd231: prev_reg231 <= value;
8'd232: prev_reg232 <= value;
8'd233: prev_reg233 <= value;
8'd234: prev_reg234 <= value;
8'd235: prev_reg235 <= value;
8'd236: prev_reg236 <= value;
8'd237: prev_reg237 <= value;
8'd238: prev_reg238 <= value;
8'd239: prev_reg239 <= value;
8'd240: prev_reg240 <= value;
8'd241: prev_reg241 <= value;
8'd242: prev_reg242 <= value;
8'd243: prev_reg243 <= value;
8'd244: prev_reg244 <= value;
8'd245: prev_reg245 <= value;
8'd246: prev_reg246 <= value;
8'd247: prev_reg247 <= value;
8'd248: prev_reg248 <= value;
8'd249: prev_reg249 <= value;
8'd250: prev_reg250 <= value;
8'd251: prev_reg251 <= value;
8'd252: prev_reg252 <= value;
8'd253: prev_reg253 <= value;
8'd254: prev_reg254 <= value;
8'd255: prev_reg255 <= value;
//----------------------------------------------------------
// Write Value to prev_reg using id as index (blocking)
8'd10: prev_reg10 = value;
8'd11: prev_reg11 = value;
8'd12: prev_reg12 = value;
8'd13: prev_reg13 = value;
8'd14: prev_reg14 = value;
8'd15: prev_reg15 = value;
8'd16: prev_reg16 = value;
8'd17: prev_reg17 = value;
8'd18: prev_reg18 = value;
8'd19: prev_reg19 = value;
8'd20: prev_reg20 = value;
8'd21: prev_reg21 = value;
8'd22: prev_reg22 = value;
8'd23: prev_reg23 = value;
8'd24: prev_reg24 = value;
8'd25: prev_reg25 = value;
8'd26: prev_reg26 = value;
8'd27: prev_reg27 = value;
8'd28: prev_reg28 = value;
8'd29: prev_reg29 = value;
8'd30: prev_reg30 = value;
8'd31: prev_reg31 = value;
8'd32: prev_reg32 = value;
8'd33: prev_reg33 = value;
8'd34: prev_reg34 = value;
8'd35: prev_reg35 = value;
8'd36: prev_reg36 = value;
8'd37: prev_reg37 = value;
8'd38: prev_reg38 = value;
8'd39: prev_reg39 = value;
8'd40: prev_reg40 = value;
8'd41: prev_reg41 = value;
8'd42: prev_reg42 = value;
8'd43: prev_reg43 = value;
8'd44: prev_reg44 = value;
8'd45: prev_reg45 = value;
8'd46: prev_reg46 = value;
8'd47: prev_reg47 = value;
8'd48: prev_reg48 = value;
8'd49: prev_reg49 = value;
8'd50: prev_reg50 = value;
8'd51: prev_reg51 = value;
8'd52: prev_reg52 = value;
8'd53: prev_reg53 = value;
8'd54: prev_reg54 = value;
8'd55: prev_reg55 = value;
8'd56: prev_reg56 = value;
8'd57: prev_reg57 = value;
8'd58: prev_reg58 = value;
8'd59: prev_reg59 = value;
8'd60: prev_reg60 = value;
8'd61: prev_reg61 = value;
8'd62: prev_reg62 = value;
8'd63: prev_reg63 = value;
8'd64: prev_reg64 = value;
8'd65: prev_reg65 = value;
8'd66: prev_reg66 = value;
8'd67: prev_reg67 = value;
8'd68: prev_reg68 = value;
8'd69: prev_reg69 = value;
8'd70: prev_reg70 = value;
8'd71: prev_reg71 = value;
8'd72: prev_reg72 = value;
8'd73: prev_reg73 = value;
8'd74: prev_reg74 = value;
8'd75: prev_reg75 = value;
8'd76: prev_reg76 = value;
8'd77: prev_reg77 = value;
8'd78: prev_reg78 = value;
8'd79: prev_reg79 = value;
8'd80: prev_reg80 = value;
8'd81: prev_reg81 = value;
8'd82: prev_reg82 = value;
8'd83: prev_reg83 = value;
8'd84: prev_reg84 = value;
8'd85: prev_reg85 = value;
8'd86: prev_reg86 = value;
8'd87: prev_reg87 = value;
8'd88: prev_reg88 = value;
8'd89: prev_reg89 = value;
8'd90: prev_reg90 = value;
8'd91: prev_reg91 = value;
8'd92: prev_reg92 = value;
8'd93: prev_reg93 = value;
8'd94: prev_reg94 = value;
8'd95: prev_reg95 = value;
8'd96: prev_reg96 = value;
8'd97: prev_reg97 = value;
8'd98: prev_reg98 = value;
8'd99: prev_reg99 = value;
8'd100: prev_reg100 = value;
8'd101: prev_reg101 = value;
8'd102: prev_reg102 = value;
8'd103: prev_reg103 = value;
8'd104: prev_reg104 = value;
8'd105: prev_reg105 = value;
8'd106: prev_reg106 = value;
8'd107: prev_reg107 = value;
8'd108: prev_reg108 = value;
8'd109: prev_reg109 = value;
8'd110: prev_reg110 = value;
8'd111: prev_reg111 = value;
8'd112: prev_reg112 = value;
8'd113: prev_reg113 = value;
8'd114: prev_reg114 = value;
8'd115: prev_reg115 = value;
8'd116: prev_reg116 = value;
8'd117: prev_reg117 = value;
8'd118: prev_reg118 = value;
8'd119: prev_reg119 = value;
8'd120: prev_reg120 = value;
8'd121: prev_reg121 = value;
8'd122: prev_reg122 = value;
8'd123: prev_reg123 = value;
8'd124: prev_reg124 = value;
8'd125: prev_reg125 = value;
8'd126: prev_reg126 = value;
8'd127: prev_reg127 = value;
8'd128: prev_reg128 = value;
8'd129: prev_reg129 = value;
8'd130: prev_reg130 = value;
8'd131: prev_reg131 = value;
8'd132: prev_reg132 = value;
8'd133: prev_reg133 = value;
8'd134: prev_reg134 = value;
8'd135: prev_reg135 = value;
8'd136: prev_reg136 = value;
8'd137: prev_reg137 = value;
8'd138: prev_reg138 = value;
8'd139: prev_reg139 = value;
8'd140: prev_reg140 = value;
8'd141: prev_reg141 = value;
8'd142: prev_reg142 = value;
8'd143: prev_reg143 = value;
8'd144: prev_reg144 = value;
8'd145: prev_reg145 = value;
8'd146: prev_reg146 = value;
8'd147: prev_reg147 = value;
8'd148: prev_reg148 = value;
8'd149: prev_reg149 = value;
8'd150: prev_reg150 = value;
8'd151: prev_reg151 = value;
8'd152: prev_reg152 = value;
8'd153: prev_reg153 = value;
8'd154: prev_reg154 = value;
8'd155: prev_reg155 = value;
8'd156: prev_reg156 = value;
8'd157: prev_reg157 = value;
8'd158: prev_reg158 = value;
8'd159: prev_reg159 = value;
8'd160: prev_reg160 = value;
8'd161: prev_reg161 = value;
8'd162: prev_reg162 = value;
8'd163: prev_reg163 = value;
8'd164: prev_reg164 = value;
8'd165: prev_reg165 = value;
8'd166: prev_reg166 = value;
8'd167: prev_reg167 = value;
8'd168: prev_reg168 = value;
8'd169: prev_reg169 = value;
8'd170: prev_reg170 = value;
8'd171: prev_reg171 = value;
8'd172: prev_reg172 = value;
8'd173: prev_reg173 = value;
8'd174: prev_reg174 = value;
8'd175: prev_reg175 = value;
8'd176: prev_reg176 = value;
8'd177: prev_reg177 = value;
8'd178: prev_reg178 = value;
8'd179: prev_reg179 = value;
8'd180: prev_reg180 = value;
8'd181: prev_reg181 = value;
8'd182: prev_reg182 = value;
8'd183: prev_reg183 = value;
8'd184: prev_reg184 = value;
8'd185: prev_reg185 = value;
8'd186: prev_reg186 = value;
8'd187: prev_reg187 = value;
8'd188: prev_reg188 = value;
8'd189: prev_reg189 = value;
8'd190: prev_reg190 = value;
8'd191: prev_reg191 = value;
8'd192: prev_reg192 = value;
8'd193: prev_reg193 = value;
8'd194: prev_reg194 = value;
8'd195: prev_reg195 = value;
8'd196: prev_reg196 = value;
8'd197: prev_reg197 = value;
8'd198: prev_reg198 = value;
8'd199: prev_reg199 = value;
8'd200: prev_reg200 = value;
8'd201: prev_reg201 = value;
8'd202: prev_reg202 = value;
8'd203: prev_reg203 = value;
8'd204: prev_reg204 = value;
8'd205: prev_reg205 = value;
8'd206: prev_reg206 = value;
8'd207: prev_reg207 = value;
8'd208: prev_reg208 = value;
8'd209: prev_reg209 = value;
8'd210: prev_reg210 = value;
8'd211: prev_reg211 = value;
8'd212: prev_reg212 = value;
8'd213: prev_reg213 = value;
8'd214: prev_reg214 = value;
8'd215: prev_reg215 = value;
8'd216: prev_reg216 = value;
8'd217: prev_reg217 = value;
8'd218: prev_reg218 = value;
8'd219: prev_reg219 = value;
8'd220: prev_reg220 = value;
8'd221: prev_reg221 = value;
8'd222: prev_reg222 = value;
8'd223: prev_reg223 = value;
8'd224: prev_reg224 = value;
8'd225: prev_reg225 = value;
8'd226: prev_reg226 = value;
8'd227: prev_reg227 = value;
8'd228: prev_reg228 = value;
8'd229: prev_reg229 = value;
8'd230: prev_reg230 = value;
8'd231: prev_reg231 = value;
8'd232: prev_reg232 = value;
8'd233: prev_reg233 = value;
8'd234: prev_reg234 = value;
8'd235: prev_reg235 = value;
8'd236: prev_reg236 = value;
8'd237: prev_reg237 = value;
8'd238: prev_reg238 = value;
8'd239: prev_reg239 = value;
8'd240: prev_reg240 = value;
8'd241: prev_reg241 = value;
8'd242: prev_reg242 = value;
8'd243: prev_reg243 = value;
8'd244: prev_reg244 = value;
8'd245: prev_reg245 = value;
8'd246: prev_reg246 = value;
8'd247: prev_reg247 = value;
8'd248: prev_reg248 = value;
8'd249: prev_reg249 = value;
8'd250: prev_reg250 = value;
8'd251: prev_reg251 = value;
8'd252: prev_reg252 = value;
8'd253: prev_reg253 = value;
8'd254: prev_reg254 = value;
8'd255: prev_reg255 = value;
//----------------------------------------------------------
// Read value frpm prev_reg using id as index
function [63:0] read_prev;
8'd0: read_prev = prev_reg0;
8'd1: read_prev = prev_reg1;
8'd2: read_prev = prev_reg2;
8'd3: read_prev = prev_reg3;
8'd4: read_prev = prev_reg4;
8'd5: read_prev = prev_reg5;
8'd6: read_prev = prev_reg6;
8'd7: read_prev = prev_reg7;
8'd8: read_prev = prev_reg8;
8'd9: read_prev = prev_reg9;
8'd10: read_prev = prev_reg10;
8'd11: read_prev = prev_reg11;
8'd12: read_prev = prev_reg12;
8'd13: read_prev = prev_reg13;
8'd14: read_prev = prev_reg14;
8'd15: read_prev = prev_reg15;
8'd16: read_prev = prev_reg16;
8'd17: read_prev = prev_reg17;
8'd18: read_prev = prev_reg18;
8'd19: read_prev = prev_reg19;
8'd20: read_prev = prev_reg20;
8'd21: read_prev = prev_reg21;
8'd22: read_prev = prev_reg22;
8'd23: read_prev = prev_reg23;
8'd24: read_prev = prev_reg24;
8'd25: read_prev = prev_reg25;
8'd26: read_prev = prev_reg26;
8'd27: read_prev = prev_reg27;
8'd28: read_prev = prev_reg28;
8'd29: read_prev = prev_reg29;
8'd30: read_prev = prev_reg30;
8'd31: read_prev = prev_reg31;
8'd32: read_prev = prev_reg32;
8'd33: read_prev = prev_reg33;
8'd34: read_prev = prev_reg34;
8'd35: read_prev = prev_reg35;
8'd36: read_prev = prev_reg36;
8'd37: read_prev = prev_reg37;
8'd38: read_prev = prev_reg38;
8'd39: read_prev = prev_reg39;
8'd40: read_prev = prev_reg40;
8'd41: read_prev = prev_reg41;
8'd42: read_prev = prev_reg42;
8'd43: read_prev = prev_reg43;
8'd44: read_prev = prev_reg44;
8'd45: read_prev = prev_reg45;
8'd46: read_prev = prev_reg46;
8'd47: read_prev = prev_reg47;
8'd48: read_prev = prev_reg48;
8'd49: read_prev = prev_reg49;
8'd50: read_prev = prev_reg50;
8'd51: read_prev = prev_reg51;
8'd52: read_prev = prev_reg52;
8'd53: read_prev = prev_reg53;
8'd54: read_prev = prev_reg54;
8'd55: read_prev = prev_reg55;
8'd56: read_prev = prev_reg56;
8'd57: read_prev = prev_reg57;
8'd58: read_prev = prev_reg58;
8'd59: read_prev = prev_reg59;
8'd60: read_prev = prev_reg60;
8'd61: read_prev = prev_reg61;
8'd62: read_prev = prev_reg62;
8'd63: read_prev = prev_reg63;
8'd64: read_prev = prev_reg64;
8'd65: read_prev = prev_reg65;
8'd66: read_prev = prev_reg66;
8'd67: read_prev = prev_reg67;
8'd68: read_prev = prev_reg68;
8'd69: read_prev = prev_reg69;
8'd70: read_prev = prev_reg70;
8'd71: read_prev = prev_reg71;
8'd72: read_prev = prev_reg72;
8'd73: read_prev = prev_reg73;
8'd74: read_prev = prev_reg74;
8'd75: read_prev = prev_reg75;
8'd76: read_prev = prev_reg76;
8'd77: read_prev = prev_reg77;
8'd78: read_prev = prev_reg78;
8'd79: read_prev = prev_reg79;
8'd80: read_prev = prev_reg80;
8'd81: read_prev = prev_reg81;
8'd82: read_prev = prev_reg82;
8'd83: read_prev = prev_reg83;
8'd84: read_prev = prev_reg84;
8'd85: read_prev = prev_reg85;
8'd86: read_prev = prev_reg86;
8'd87: read_prev = prev_reg87;
8'd88: read_prev = prev_reg88;
8'd89: read_prev = prev_reg89;
8'd90: read_prev = prev_reg90;
8'd91: read_prev = prev_reg91;
8'd92: read_prev = prev_reg92;
8'd93: read_prev = prev_reg93;
8'd94: read_prev = prev_reg94;
8'd95: read_prev = prev_reg95;
8'd96: read_prev = prev_reg96;
8'd97: read_prev = prev_reg97;
8'd98: read_prev = prev_reg98;
8'd99: read_prev = prev_reg99;
8'd100: read_prev = prev_reg100;
8'd101: read_prev = prev_reg101;
8'd102: read_prev = prev_reg102;
8'd103: read_prev = prev_reg103;
8'd104: read_prev = prev_reg104;
8'd105: read_prev = prev_reg105;
8'd106: read_prev = prev_reg106;
8'd107: read_prev = prev_reg107;
8'd108: read_prev = prev_reg108;
8'd109: read_prev = prev_reg109;
8'd110: read_prev = prev_reg110;
8'd111: read_prev = prev_reg111;
8'd112: read_prev = prev_reg112;
8'd113: read_prev = prev_reg113;
8'd114: read_prev = prev_reg114;
8'd115: read_prev = prev_reg115;
8'd116: read_prev = prev_reg116;
8'd117: read_prev = prev_reg117;
8'd118: read_prev = prev_reg118;
8'd119: read_prev = prev_reg119;
8'd120: read_prev = prev_reg120;
8'd121: read_prev = prev_reg121;
8'd122: read_prev = prev_reg122;
8'd123: read_prev = prev_reg123;
8'd124: read_prev = prev_reg124;
8'd125: read_prev = prev_reg125;
8'd126: read_prev = prev_reg126;
8'd127: read_prev = prev_reg127;
8'd128: read_prev = prev_reg128;
8'd129: read_prev = prev_reg129;
8'd130: read_prev = prev_reg130;
8'd131: read_prev = prev_reg131;
8'd132: read_prev = prev_reg132;
8'd133: read_prev = prev_reg133;
8'd134: read_prev = prev_reg134;
8'd135: read_prev = prev_reg135;
8'd136: read_prev = prev_reg136;
8'd137: read_prev = prev_reg137;
8'd138: read_prev = prev_reg138;
8'd139: read_prev = prev_reg139;
8'd140: read_prev = prev_reg140;
8'd141: read_prev = prev_reg141;
8'd142: read_prev = prev_reg142;
8'd143: read_prev = prev_reg143;
8'd144: read_prev = prev_reg144;
8'd145: read_prev = prev_reg145;
8'd146: read_prev = prev_reg146;
8'd147: read_prev = prev_reg147;
8'd148: read_prev = prev_reg148;
8'd149: read_prev = prev_reg149;
8'd150: read_prev = prev_reg150;
8'd151: read_prev = prev_reg151;
8'd152: read_prev = prev_reg152;
8'd153: read_prev = prev_reg153;
8'd154: read_prev = prev_reg154;
8'd155: read_prev = prev_reg155;
8'd156: read_prev = prev_reg156;
8'd157: read_prev = prev_reg157;
8'd158: read_prev = prev_reg158;
8'd159: read_prev = prev_reg159;
8'd160: read_prev = prev_reg160;
8'd161: read_prev = prev_reg161;
8'd162: read_prev = prev_reg162;
8'd163: read_prev = prev_reg163;
8'd164: read_prev = prev_reg164;
8'd165: read_prev = prev_reg165;
8'd166: read_prev = prev_reg166;
8'd167: read_prev = prev_reg167;
8'd168: read_prev = prev_reg168;
8'd169: read_prev = prev_reg169;
8'd170: read_prev = prev_reg170;
8'd171: read_prev = prev_reg171;
8'd172: read_prev = prev_reg172;
8'd173: read_prev = prev_reg173;
8'd174: read_prev = prev_reg174;
8'd175: read_prev = prev_reg175;
8'd176: read_prev = prev_reg176;
8'd177: read_prev = prev_reg177;
8'd178: read_prev = prev_reg178;
8'd179: read_prev = prev_reg179;
8'd180: read_prev = prev_reg180;
8'd181: read_prev = prev_reg181;
8'd182: read_prev = prev_reg182;
8'd183: read_prev = prev_reg183;
8'd184: read_prev = prev_reg184;
8'd185: read_prev = prev_reg185;
8'd186: read_prev = prev_reg186;
8'd187: read_prev = prev_reg187;
8'd188: read_prev = prev_reg188;
8'd189: read_prev = prev_reg189;
8'd190: read_prev = prev_reg190;
8'd191: read_prev = prev_reg191;
8'd192: read_prev = prev_reg192;
8'd193: read_prev = prev_reg193;
8'd194: read_prev = prev_reg194;
8'd195: read_prev = prev_reg195;
8'd196: read_prev = prev_reg196;
8'd197: read_prev = prev_reg197;
8'd198: read_prev = prev_reg198;
8'd199: read_prev = prev_reg199;
8'd200: read_prev = prev_reg200;
8'd201: read_prev = prev_reg201;
8'd202: read_prev = prev_reg202;
8'd203: read_prev = prev_reg203;
8'd204: read_prev = prev_reg204;
8'd205: read_prev = prev_reg205;
8'd206: read_prev = prev_reg206;
8'd207: read_prev = prev_reg207;
8'd208: read_prev = prev_reg208;
8'd209: read_prev = prev_reg209;
8'd210: read_prev = prev_reg210;
8'd211: read_prev = prev_reg211;
8'd212: read_prev = prev_reg212;
8'd213: read_prev = prev_reg213;
8'd214: read_prev = prev_reg214;
8'd215: read_prev = prev_reg215;
8'd216: read_prev = prev_reg216;
8'd217: read_prev = prev_reg217;
8'd218: read_prev = prev_reg218;
8'd219: read_prev = prev_reg219;
8'd220: read_prev = prev_reg220;
8'd221: read_prev = prev_reg221;
8'd222: read_prev = prev_reg222;
8'd223: read_prev = prev_reg223;
8'd224: read_prev = prev_reg224;
8'd225: read_prev = prev_reg225;
8'd226: read_prev = prev_reg226;
8'd227: read_prev = prev_reg227;
8'd228: read_prev = prev_reg228;
8'd229: read_prev = prev_reg229;
8'd230: read_prev = prev_reg230;
8'd231: read_prev = prev_reg231;
8'd232: read_prev = prev_reg232;
8'd233: read_prev = prev_reg233;
8'd234: read_prev = prev_reg234;
8'd235: read_prev = prev_reg235;
8'd236: read_prev = prev_reg236;
8'd237: read_prev = prev_reg237;
8'd238: read_prev = prev_reg238;
8'd239: read_prev = prev_reg239;
8'd240: read_prev = prev_reg240;
8'd241: read_prev = prev_reg241;
8'd242: read_prev = prev_reg242;
8'd243: read_prev = prev_reg243;
8'd244: read_prev = prev_reg244;
8'd245: read_prev = prev_reg245;
8'd246: read_prev = prev_reg246;
8'd247: read_prev = prev_reg247;
8'd248: read_prev = prev_reg248;
8'd249: read_prev = prev_reg249;
8'd250: read_prev = prev_reg250;
8'd251: read_prev = prev_reg251;
8'd252: read_prev = prev_reg252;
8'd253: read_prev = prev_reg253;
8'd254: read_prev = prev_reg254;
8'd255: read_prev = prev_reg255;
//----------------------------------------------------------
remap[4] = rd[4] ^ (rd[3] & oddwin);
//----------------------------------------------------------
// Initialize nas_pipe registers
initial begin : INIT_BLOCK
nas_pipe_enable = 1'b1; // Nas_pipe always enables itself
good_trap_detected = 1'b0;
@ (posedge `BENCH_SPC2_GCLK);
`TOP.th_last_act_cycle[mytnum] = 0;
`PR_INFO ("nas", `INFO, "T%0d Init shadow registers.",mytnum);
// POR for control registers
write_prev(`FPRS +`CTL_OFFSET,3'h4);
write_prev(`CLEANWIN +`CTL_OFFSET,3'h7);
write_prev(`CANSAVE +`CTL_OFFSET,3'h6);
write_prev(`FPRS+`CTL_OFFSET,3'h4);
// POR for PSTATE = 0x14 (PEF, PRIV = 1)
write_prev(`PSTATE + `CTL_OFFSET,'h14);
// POR for HPSTATE = 0x4034 (RED, HPRIV = 1)
write_prev(`HPSTATE + `CTL_OFFSET,'h24);
// POR for TL = = 0x6 [MAXTL]
write_prev(`TL + `CTL_OFFSET,'h6);
write_prev(`TT6 + `CTL_OFFSET,'h1);
// POR for GL = MAXGL = 3
write_prev(`GL + `CTL_OFFSET,`POR_GL);
// POR for VER = {003e, 0024, 01, 0036, 07}
write_prev(`VER + `CTL_OFFSET,{32'h003e0024,VER_reg[31:24],24'h030607});
// POR for *_cmpr registers is INT_DIS = 1
write_prev(`TICK_CMPR + `CTL_OFFSET,64'h8000000000000000);
write_prev(`STICK_CMPR + `CTL_OFFSET,64'h8000000000000000);
write_prev(`HSTICK_CMPR + `CTL_OFFSET,64'h8000000000000000);
// Need to define so that 1st instruction will print correctly
write_prev(`PC+`CTL_OFFSET,`POR_PC);
delta_prev[`PC_INDEX] = `BAD_PC;
irf_offset = (mytid%4)*32;
//----------------------------------------------------------
// For WMR, we will set to 0x0, so that initial deltas
// WMR for PSTATE = 0x14 (PEF, PRIV = 1)
// write_prev(`PSTATE + `CTL_OFFSET,'h00);
// WMR for HPSTATE = 0x4034 (RED, HPRIV = 1)
// write_prev(`HPSTATE + `CTL_OFFSET,'h00);
// WMR for TL = = 0x6 [MAXTL]
// write_prev(`TL + `CTL_OFFSET,'h0);
// write_prev(`TT6 + `CTL_OFFSET,'h1);
// WMR for GL = MAXGL = 3
// write_prev(`GL + `CTL_OFFSET,0);
//----------------------------------------------------------
// For POR, we will set to 0x0, so that initial deltas
// and prev state are all consistent with DUT. No values
`PR_ALWAYS ("arg", `ALWAYS,"T%0d Resetting Nas Pipe states for POR ..",mytnum);
delta_fx4[`NEXT_INDEX] <= `FIRST_INDEX;
delta_fx4[`FIRST_INDEX] <= 77'hx;
delta_fx5[`NEXT_INDEX] <= `FIRST_INDEX;
delta_fb[`NEXT_INDEX] <= `FIRST_INDEX;
delta_fw[`NEXT_INDEX] <= `FIRST_INDEX;
delta_fw1[`NEXT_INDEX] <= `FIRST_INDEX;
delta_fw2[`NEXT_INDEX] <= `FIRST_INDEX;
`PR_INFO ("nas", `INFO, "T%0d Init shadow registers.",mytnum);
// POR for control registers
write_prev(`FPRS +`CTL_OFFSET,3'h4);
write_prev(`CLEANWIN +`CTL_OFFSET,3'h7);
write_prev(`CANSAVE +`CTL_OFFSET,3'h6);
write_prev(`FPRS+`CTL_OFFSET,3'h4);
// POR for PSTATE = 0x14 (PEF, PRIV = 1)
write_prev(`PSTATE + `CTL_OFFSET,'h14);
// POR for HPSTATE = 0x4034 (RED, HPRIV = 1)
write_prev(`HPSTATE + `CTL_OFFSET,'h24);
// POR for TL = = 0x6 [MAXTL]
write_prev(`TL + `CTL_OFFSET,'h6);
write_prev(`TT6 + `CTL_OFFSET,'h1);
// POR for GL = MAXGL = 3
write_prev(`GL + `CTL_OFFSET,`POR_GL);
// POR for VER = {003e, 0024, 01, 0036, 07}
write_prev(`VER + `CTL_OFFSET,64'h003e002410030607);
// POR for *_cmpr registers is INT_DIS = 1
write_prev(`TICK_CMPR + `CTL_OFFSET,64'h8000000000000000);
write_prev(`STICK_CMPR + `CTL_OFFSET,64'h8000000000000000);
write_prev(`HSTICK_CMPR + `CTL_OFFSET,64'h8000000000000000);
// Need to define so that 1st instruction will print correctly
write_prev(`PC+`CTL_OFFSET,`POR_PC);
//----------------------------------------------------------
//----------------------------------------------------------
// Watch for Good/Bad trap
wire [5:0] mytnum = (mycid*8)+mytid;
// Delimiter changes whether flat or hierarchical netlist
wire myclk = tb_top.cpu.spc2.gclk;
wire dec_inst_valid_m = mytg ? tb_top.cpu.spc2.dec_inst_valid_m[1] : tb_top.cpu.spc2.dec_inst_valid_m[0];
wire [1:0] dec_tid_m = mytg ? tb_top.cpu.spc2.dec_tid1_m : tb_top.cpu.spc2.dec_tid0_m;
wire dec_flush_b = mytg ? tb_top.cpu.spc2.dec_flush_b[1] : tb_top.cpu.spc2.dec_flush_b[0];
wire tlu_flush_ifu = tb_top.cpu.spc2.tlu_flush_ifu[mytid];
wire [47:0] pc_d = mytg ? {tb_top.cpu.spc2.tlu_pc_1_d[47:2],2'b0} : {tb_top.cpu.spc2.tlu_pc_0_d[47:2],2'b0};
wire [31:0] op_d = mytg ? tb_top.cpu.spc2.dec_inst1_d[31:0] : tb_top.cpu.spc2.dec_inst0_d[31:0];
wire myclk = tb_top.cpu.spc2.gclk;
wire dec_inst_valid_m = mytg ? tb_top.cpu.spc2.dec_inst_valid_m[1] : tb_top.cpu.spc2.dec_inst_valid_m[0];
wire [1:0] dec_tid_m = mytg ? tb_top.cpu.spc2.dec_tid1_m : tb_top.cpu.spc2.dec_tid0_m;
wire dec_flush_b = mytg ? tb_top.cpu.spc2.dec_flush_b[1] : tb_top.cpu.spc2.dec_flush_b[0];
wire tlu_flush_ifu = tb_top.cpu.spc2.tlu_flush_ifu[mytid];
wire [47:0] pc_d = mytg ? {tb_top.cpu.spc2.tlu_pc_1_d[47:2],2'b0} : {tb_top.cpu.spc2.tlu_pc_0_d[47:2],2'b0};
wire [31:0] op_d = mytg ? tb_top.cpu.spc2.dec_inst1_d[31:0] : tb_top.cpu.spc2.dec_inst0_d[31:0];
wire inst_valid_b = dec_inst_valid_b && (dec_tid_b==mytid[1:0]) && !(dec_flush_b || tlu_flush_ifu);
always @ (posedge myclk) begin // {
dec_inst_valid_b <= dec_inst_valid_m;
inst_valid_w <= inst_valid_b;
inst_valid_fx4 <= inst_valid_w;
inst_valid_fx5 <= inst_valid_fx4;
inst_valid_fb <= inst_valid_fx5;
inst_valid_fw <= inst_valid_fb;
inst_valid_fw1 <= inst_valid_fw;
inst_valid_fw2 <= inst_valid_fw1;
if (`PARGS.th_check_enable[mytnum] && nas_pipe_enable) begin // {
if (inst_valid_fw2) begin // {
// Print PC/opcode for debugging
`PR_NORMAL ("nas", `NORMAL, "@%0d #%0d T%0d %h [%h]", $time, inst_count, mytnum, pc_fw2, op_fw2);
inst_count = inst_count + 1;
// End detection for GateSim runs
for (junk=0;junk<`PARGS.bad_trap_count;junk=junk+1) begin // {
if (({16'b0,pc_fw2}&`PC_MASK)===(`PARGS.bad_trap_addr[junk]&`PC_MASK)) begin // {
`PR_ERROR ("nas",`ERROR, "T%0d reached Bad Trap [GATESIM]", mytnum);
for (junk=0;junk<`PARGS.good_trap_count;junk=junk+1) begin // {
if (({16'b0,pc_fw2}&`PC_MASK)===(`PARGS.good_trap_addr[junk]&`PC_MASK)) begin // {
`TOP.finished_tids[mytnum] = 1'b1;
`PARGS.th_check_enable[mytnum] = 1'b0;
`PR_NORMAL ("nas", `NORMAL, "T%0d reached Good Trap. Disabling checking for thread %0d [GATESIM]", mytnum,mytnum);
//----------------------------------------------------------
//----------------------------------------------------------
//----------------------------------------------------------
input [71:0] TICK_CMPR_reg;
input [71:0] STICK_CMPR_reg;
input [71:0] HSTICK_CMPR_reg;
input [2:0] CANRESTORE_reg;
input [2:0] OTHERWIN_reg;
input [2:0] CLEANWIN_reg;
input [16:0] SOFTINT_reg;
input [16:0] rd_SOFTINT_reg;
input [63:0] INTR_RECEIVE_reg;
input [12:0] HPSTATE_reg;
input [63:0] CTXT_PRIM_0_reg;
input [63:0] CTXT_SEC_0_reg;
input [63:0] CTXT_PRIM_1_reg;
input [63:0] CTXT_SEC_1_reg;
input [63:0] LSU_CONTROL_reg;
input [63:0] I_TAG_ACC_reg;
input [63:0] D_TAG_ACC_reg;
input [63:0] WATCHPOINT_ADDR_reg;
input [151:0] Trap_Entry_1;
input [151:0] Trap_Entry_2;
input [151:0] Trap_Entry_3;
input [151:0] Trap_Entry_4;
input [151:0] Trap_Entry_5;
input [151:0] Trap_Entry_6;
input [1:0] frf_w2_valid;
input [1:0] frf_w1_valid;
input asi_valid; // ASI/ASR/PR writes done ..
input asi_in_progress; // ASI/ASR/PR in progess
//----------------------------------------------------------
//----------------------------------------------------------
//----------------------------------------------------------
// delta_* = {type(2bits),win(3bits),regnum(8bits),value(64bits)}
reg [`DELTA_WIDTH:0] delta_fx4 [0:(`MAX_INDEX)];
reg [`DELTA_WIDTH:0] delta_fx5 [0:(`MAX_INDEX)];
reg [`DELTA_WIDTH:0] delta_fb [0:(`MAX_INDEX)];
reg [`DELTA_WIDTH:0] delta_fw [0:(`MAX_INDEX)];
reg [`DELTA_WIDTH:0] delta_fw1 [0:(`MAX_INDEX)];
reg [`DELTA_WIDTH:0] delta_fw2 [0:(`MAX_INDEX)];
reg [`DELTA_WIDTH:0] delta_prev [0:(`MAX_INDEX)];
// need to change in several places in this file
reg [63:0] prev_reg0; // includes G,W,C,F registers
reg [63:0] prev_reg1; // includes G,W,C,F registers
reg [63:0] prev_reg2; // includes G,W,C,F registers
reg [63:0] prev_reg3; // includes G,W,C,F registers
reg [63:0] prev_reg4; // includes G,W,C,F registers
reg [63:0] prev_reg5; // includes G,W,C,F registers
reg [63:0] prev_reg6; // includes G,W,C,F registers
reg [63:0] prev_reg7; // includes G,W,C,F registers
reg [63:0] prev_reg8; // includes G,W,C,F registers
reg [63:0] prev_reg9; // includes G,W,C,F registers
reg [63:0] prev_reg10; // includes G,W,C,F registers
reg [63:0] prev_reg11; // includes G,W,C,F registers
reg [63:0] prev_reg12; // includes G,W,C,F registers
reg [63:0] prev_reg13; // includes G,W,C,F registers
reg [63:0] prev_reg14; // includes G,W,C,F registers
reg [63:0] prev_reg15; // includes G,W,C,F registers
reg [63:0] prev_reg16; // includes G,W,C,F registers
reg [63:0] prev_reg17; // includes G,W,C,F registers
reg [63:0] prev_reg18; // includes G,W,C,F registers
reg [63:0] prev_reg19; // includes G,W,C,F registers
reg [63:0] prev_reg20; // includes G,W,C,F registers
reg [63:0] prev_reg21; // includes G,W,C,F registers
reg [63:0] prev_reg22; // includes G,W,C,F registers
reg [63:0] prev_reg23; // includes G,W,C,F registers
reg [63:0] prev_reg24; // includes G,W,C,F registers
reg [63:0] prev_reg25; // includes G,W,C,F registers
reg [63:0] prev_reg26; // includes G,W,C,F registers
reg [63:0] prev_reg27; // includes G,W,C,F registers
reg [63:0] prev_reg28; // includes G,W,C,F registers
reg [63:0] prev_reg29; // includes G,W,C,F registers
reg [63:0] prev_reg30; // includes G,W,C,F registers
reg [63:0] prev_reg31; // includes G,W,C,F registers
reg [63:0] prev_reg32; // includes G,W,C,F registers
reg [63:0] prev_reg33; // includes G,W,C,F registers
reg [63:0] prev_reg34; // includes G,W,C,F registers
reg [63:0] prev_reg35; // includes G,W,C,F registers
reg [63:0] prev_reg36; // includes G,W,C,F registers
reg [63:0] prev_reg37; // includes G,W,C,F registers
reg [63:0] prev_reg38; // includes G,W,C,F registers
reg [63:0] prev_reg39; // includes G,W,C,F registers
reg [63:0] prev_reg40; // includes G,W,C,F registers
reg [63:0] prev_reg41; // includes G,W,C,F registers
reg [63:0] prev_reg42; // includes G,W,C,F registers
reg [63:0] prev_reg43; // includes G,W,C,F registers
reg [63:0] prev_reg44; // includes G,W,C,F registers
reg [63:0] prev_reg45; // includes G,W,C,F registers
reg [63:0] prev_reg46; // includes G,W,C,F registers
reg [63:0] prev_reg47; // includes G,W,C,F registers
reg [63:0] prev_reg48; // includes G,W,C,F registers
reg [63:0] prev_reg49; // includes G,W,C,F registers
reg [63:0] prev_reg50; // includes G,W,C,F registers
reg [63:0] prev_reg51; // includes G,W,C,F registers
reg [63:0] prev_reg52; // includes G,W,C,F registers
reg [63:0] prev_reg53; // includes G,W,C,F registers
reg [63:0] prev_reg54; // includes G,W,C,F registers
reg [63:0] prev_reg55; // includes G,W,C,F registers
reg [63:0] prev_reg56; // includes G,W,C,F registers
reg [63:0] prev_reg57; // includes G,W,C,F registers
reg [63:0] prev_reg58; // includes G,W,C,F registers
reg [63:0] prev_reg59; // includes G,W,C,F registers
reg [63:0] prev_reg60; // includes G,W,C,F registers
reg [63:0] prev_reg61; // includes G,W,C,F registers
reg [63:0] prev_reg62; // includes G,W,C,F registers
reg [63:0] prev_reg63; // includes G,W,C,F registers
reg [63:0] prev_reg64; // includes G,W,C,F registers
reg [63:0] prev_reg65; // includes G,W,C,F registers
reg [63:0] prev_reg66; // includes G,W,C,F registers
reg [63:0] prev_reg67; // includes G,W,C,F registers
reg [63:0] prev_reg68; // includes G,W,C,F registers
reg [63:0] prev_reg69; // includes G,W,C,F registers
reg [63:0] prev_reg70; // includes G,W,C,F registers
reg [63:0] prev_reg71; // includes G,W,C,F registers
reg [63:0] prev_reg72; // includes G,W,C,F registers
reg [63:0] prev_reg73; // includes G,W,C,F registers
reg [63:0] prev_reg74; // includes G,W,C,F registers
reg [63:0] prev_reg75; // includes G,W,C,F registers
reg [63:0] prev_reg76; // includes G,W,C,F registers
reg [63:0] prev_reg77; // includes G,W,C,F registers
reg [63:0] prev_reg78; // includes G,W,C,F registers
reg [63:0] prev_reg79; // includes G,W,C,F registers
reg [63:0] prev_reg80; // includes G,W,C,F registers
reg [63:0] prev_reg81; // includes G,W,C,F registers
reg [63:0] prev_reg82; // includes G,W,C,F registers
reg [63:0] prev_reg83; // includes G,W,C,F registers
reg [63:0] prev_reg84; // includes G,W,C,F registers
reg [63:0] prev_reg85; // includes G,W,C,F registers
reg [63:0] prev_reg86; // includes G,W,C,F registers
reg [63:0] prev_reg87; // includes G,W,C,F registers
reg [63:0] prev_reg88; // includes G,W,C,F registers
reg [63:0] prev_reg89; // includes G,W,C,F registers
reg [63:0] prev_reg90; // includes G,W,C,F registers
reg [63:0] prev_reg91; // includes G,W,C,F registers
reg [63:0] prev_reg92; // includes G,W,C,F registers
reg [63:0] prev_reg93; // includes G,W,C,F registers
reg [63:0] prev_reg94; // includes G,W,C,F registers
reg [63:0] prev_reg95; // includes G,W,C,F registers
reg [63:0] prev_reg96; // includes G,W,C,F registers
reg [63:0] prev_reg97; // includes G,W,C,F registers
reg [63:0] prev_reg98; // includes G,W,C,F registers
reg [63:0] prev_reg99; // includes G,W,C,F registers
reg [63:0] prev_reg100; // includes G,W,C,F registers
reg [63:0] prev_reg101; // includes G,W,C,F registers
reg [63:0] prev_reg102; // includes G,W,C,F registers
reg [63:0] prev_reg103; // includes G,W,C,F registers
reg [63:0] prev_reg104; // includes G,W,C,F registers
reg [63:0] prev_reg105; // includes G,W,C,F registers
reg [63:0] prev_reg106; // includes G,W,C,F registers
reg [63:0] prev_reg107; // includes G,W,C,F registers
reg [63:0] prev_reg108; // includes G,W,C,F registers
reg [63:0] prev_reg109; // includes G,W,C,F registers
reg [63:0] prev_reg110; // includes G,W,C,F registers
reg [63:0] prev_reg111; // includes G,W,C,F registers
reg [63:0] prev_reg112; // includes G,W,C,F registers
reg [63:0] prev_reg113; // includes G,W,C,F registers
reg [63:0] prev_reg114; // includes G,W,C,F registers
reg [63:0] prev_reg115; // includes G,W,C,F registers
reg [63:0] prev_reg116; // includes G,W,C,F registers
reg [63:0] prev_reg117; // includes G,W,C,F registers
reg [63:0] prev_reg118; // includes G,W,C,F registers
reg [63:0] prev_reg119; // includes G,W,C,F registers
reg [63:0] prev_reg120; // includes G,W,C,F registers
reg [63:0] prev_reg121; // includes G,W,C,F registers
reg [63:0] prev_reg122; // includes G,W,C,F registers
reg [63:0] prev_reg123; // includes G,W,C,F registers
reg [63:0] prev_reg124; // includes G,W,C,F registers
reg [63:0] prev_reg125; // includes G,W,C,F registers
reg [63:0] prev_reg126; // includes G,W,C,F registers
reg [63:0] prev_reg127; // includes G,W,C,F registers
reg [63:0] prev_reg128; // includes G,W,C,F registers
reg [63:0] prev_reg129; // includes G,W,C,F registers
reg [63:0] prev_reg130; // includes G,W,C,F registers
reg [63:0] prev_reg131; // includes G,W,C,F registers
reg [63:0] prev_reg132; // includes G,W,C,F registers
reg [63:0] prev_reg133; // includes G,W,C,F registers
reg [63:0] prev_reg134; // includes G,W,C,F registers
reg [63:0] prev_reg135; // includes G,W,C,F registers
reg [63:0] prev_reg136; // includes G,W,C,F registers
reg [63:0] prev_reg137; // includes G,W,C,F registers
reg [63:0] prev_reg138; // includes G,W,C,F registers
reg [63:0] prev_reg139; // includes G,W,C,F registers
reg [63:0] prev_reg140; // includes G,W,C,F registers
reg [63:0] prev_reg141; // includes G,W,C,F registers
reg [63:0] prev_reg142; // includes G,W,C,F registers
reg [63:0] prev_reg143; // includes G,W,C,F registers
reg [63:0] prev_reg144; // includes G,W,C,F registers
reg [63:0] prev_reg145; // includes G,W,C,F registers
reg [63:0] prev_reg146; // includes G,W,C,F registers
reg [63:0] prev_reg147; // includes G,W,C,F registers
reg [63:0] prev_reg148; // includes G,W,C,F registers
reg [63:0] prev_reg149; // includes G,W,C,F registers
reg [63:0] prev_reg150; // includes G,W,C,F registers
reg [63:0] prev_reg151; // includes G,W,C,F registers
reg [63:0] prev_reg152; // includes G,W,C,F registers
reg [63:0] prev_reg153; // includes G,W,C,F registers
reg [63:0] prev_reg154; // includes G,W,C,F registers
reg [63:0] prev_reg155; // includes G,W,C,F registers
reg [63:0] prev_reg156; // includes G,W,C,F registers
reg [63:0] prev_reg157; // includes G,W,C,F registers
reg [63:0] prev_reg158; // includes G,W,C,F registers
reg [63:0] prev_reg159; // includes G,W,C,F registers
reg [63:0] prev_reg160; // includes G,W,C,F registers
reg [63:0] prev_reg161; // includes G,W,C,F registers
reg [63:0] prev_reg162; // includes G,W,C,F registers
reg [63:0] prev_reg163; // includes G,W,C,F registers
reg [63:0] prev_reg164; // includes G,W,C,F registers
reg [63:0] prev_reg165; // includes G,W,C,F registers
reg [63:0] prev_reg166; // includes G,W,C,F registers
reg [63:0] prev_reg167; // includes G,W,C,F registers
reg [63:0] prev_reg168; // includes G,W,C,F registers
reg [63:0] prev_reg169; // includes G,W,C,F registers
reg [63:0] prev_reg170; // includes G,W,C,F registers
reg [63:0] prev_reg171; // includes G,W,C,F registers
reg [63:0] prev_reg172; // includes G,W,C,F registers
reg [63:0] prev_reg173; // includes G,W,C,F registers
reg [63:0] prev_reg174; // includes G,W,C,F registers
reg [63:0] prev_reg175; // includes G,W,C,F registers
reg [63:0] prev_reg176; // includes G,W,C,F registers
reg [63:0] prev_reg177; // includes G,W,C,F registers
reg [63:0] prev_reg178; // includes G,W,C,F registers
reg [63:0] prev_reg179; // includes G,W,C,F registers
reg [63:0] prev_reg180; // includes G,W,C,F registers
reg [63:0] prev_reg181; // includes G,W,C,F registers
reg [63:0] prev_reg182; // includes G,W,C,F registers
reg [63:0] prev_reg183; // includes G,W,C,F registers
reg [63:0] prev_reg184; // includes G,W,C,F registers
reg [63:0] prev_reg185; // includes G,W,C,F registers
reg [63:0] prev_reg186; // includes G,W,C,F registers
reg [63:0] prev_reg187; // includes G,W,C,F registers
reg [63:0] prev_reg188; // includes G,W,C,F registers
reg [63:0] prev_reg189; // includes G,W,C,F registers
reg [63:0] prev_reg190; // includes G,W,C,F registers
reg [63:0] prev_reg191; // includes G,W,C,F registers
reg [63:0] prev_reg192; // includes G,W,C,F registers
reg [63:0] prev_reg193; // includes G,W,C,F registers
reg [63:0] prev_reg194; // includes G,W,C,F registers
reg [63:0] prev_reg195; // includes G,W,C,F registers
reg [63:0] prev_reg196; // includes G,W,C,F registers
reg [63:0] prev_reg197; // includes G,W,C,F registers
reg [63:0] prev_reg198; // includes G,W,C,F registers
reg [63:0] prev_reg199; // includes G,W,C,F registers
reg [63:0] prev_reg200; // includes G,W,C,F registers
reg [63:0] prev_reg201; // includes G,W,C,F registers
reg [63:0] prev_reg202; // includes G,W,C,F registers
reg [63:0] prev_reg203; // includes G,W,C,F registers
reg [63:0] prev_reg204; // includes G,W,C,F registers
reg [63:0] prev_reg205; // includes G,W,C,F registers
reg [63:0] prev_reg206; // includes G,W,C,F registers
reg [63:0] prev_reg207; // includes G,W,C,F registers
reg [63:0] prev_reg208; // includes G,W,C,F registers
reg [63:0] prev_reg209; // includes G,W,C,F registers
reg [63:0] prev_reg210; // includes G,W,C,F registers
reg [63:0] prev_reg211; // includes G,W,C,F registers
reg [63:0] prev_reg212; // includes G,W,C,F registers
reg [63:0] prev_reg213; // includes G,W,C,F registers
reg [63:0] prev_reg214; // includes G,W,C,F registers
reg [63:0] prev_reg215; // includes G,W,C,F registers
reg [63:0] prev_reg216; // includes G,W,C,F registers
reg [63:0] prev_reg217; // includes G,W,C,F registers
reg [63:0] prev_reg218; // includes G,W,C,F registers
reg [63:0] prev_reg219; // includes G,W,C,F registers
reg [63:0] prev_reg220; // includes G,W,C,F registers
reg [63:0] prev_reg221; // includes G,W,C,F registers
reg [63:0] prev_reg222; // includes G,W,C,F registers
reg [63:0] prev_reg223; // includes G,W,C,F registers
reg [63:0] prev_reg224; // includes G,W,C,F registers
reg [63:0] prev_reg225; // includes G,W,C,F registers
reg [63:0] prev_reg226; // includes G,W,C,F registers
reg [63:0] prev_reg227; // includes G,W,C,F registers
reg [63:0] prev_reg228; // includes G,W,C,F registers
reg [63:0] prev_reg229; // includes G,W,C,F registers
reg [63:0] prev_reg230; // includes G,W,C,F registers
reg [63:0] prev_reg231; // includes G,W,C,F registers
reg [63:0] prev_reg232; // includes G,W,C,F registers
reg [63:0] prev_reg233; // includes G,W,C,F registers
reg [63:0] prev_reg234; // includes G,W,C,F registers
reg [63:0] prev_reg235; // includes G,W,C,F registers
reg [63:0] prev_reg236; // includes G,W,C,F registers
reg [63:0] prev_reg237; // includes G,W,C,F registers
reg [63:0] prev_reg238; // includes G,W,C,F registers
reg [63:0] prev_reg239; // includes G,W,C,F registers
reg [63:0] prev_reg240; // includes G,W,C,F registers
reg [63:0] prev_reg241; // includes G,W,C,F registers
reg [63:0] prev_reg242; // includes G,W,C,F registers
reg [63:0] prev_reg243; // includes G,W,C,F registers
reg [63:0] prev_reg244; // includes G,W,C,F registers
reg [63:0] prev_reg245; // includes G,W,C,F registers
reg [63:0] prev_reg246; // includes G,W,C,F registers
reg [63:0] prev_reg247; // includes G,W,C,F registers
reg [63:0] prev_reg248; // includes G,W,C,F registers
reg [63:0] prev_reg249; // includes G,W,C,F registers
reg [63:0] prev_reg250; // includes G,W,C,F registers
reg [63:0] prev_reg251; // includes G,W,C,F registers
reg [63:0] prev_reg252; // includes G,W,C,F registers
reg [63:0] prev_reg253; // includes G,W,C,F registers
reg [63:0] prev_reg254; // includes G,W,C,F registers
reg [63:0] prev_reg255; // includes G,W,C,F registers
reg [1:0] th_gl; // copy of GL_reg
reg frf_w1_skip_addr4_fw1;
reg frf_w1_skip_addr4_fw2;
reg [1:0] frf_w2_valid_fw;
reg [1:0] frf_w2_valid_bn;
reg [4:0] frf_w2_addr_fw;
reg [1:0] frf_w1_valid_fw;
reg [4:0] frf_w1_addr_fw;
reg wmr; // latched to get edge
reg por_a; // latched to get edge
reg por_b; // latched to get edge
reg nas_pipe_enable; // Turns on nas_pipe capture and Riesling SSTEP
wire [4:0] frf_w1_skip_addr;
wire [4:0] frf_w2_skip_addr;
reg good_trap_detected; // Used for -nosas only.
//----------------------------------------------------------
wire [`DELTA_WIDTH:0] delta_fx4_0;
wire [`DELTA_WIDTH:0] delta_fx4_1;
wire [`DELTA_WIDTH:0] delta_fx4_2;
wire [`DELTA_WIDTH:0] delta_fx4_3;
wire [`DELTA_WIDTH:0] delta_fx4_4;
wire [`DELTA_WIDTH:0] delta_fx4_5;
wire [`DELTA_WIDTH:0] delta_fx4_6;
wire [`DELTA_WIDTH:0] delta_fx4_7;
wire [`DELTA_WIDTH:0] delta_fx5_0;
wire [`DELTA_WIDTH:0] delta_fx5_1;
wire [`DELTA_WIDTH:0] delta_fx5_2;
wire [`DELTA_WIDTH:0] delta_fx5_3;
wire [`DELTA_WIDTH:0] delta_fx5_4;
wire [`DELTA_WIDTH:0] delta_fx5_5;
wire [`DELTA_WIDTH:0] delta_fx5_6;
wire [`DELTA_WIDTH:0] delta_fx5_7;
wire [`DELTA_WIDTH:0] delta_fb_0;
wire [`DELTA_WIDTH:0] delta_fb_1;
wire [`DELTA_WIDTH:0] delta_fb_2;
wire [`DELTA_WIDTH:0] delta_fb_3;
wire [`DELTA_WIDTH:0] delta_fb_4;
wire [`DELTA_WIDTH:0] delta_fb_5;
wire [`DELTA_WIDTH:0] delta_fb_6;
wire [`DELTA_WIDTH:0] delta_fb_7;
wire [`DELTA_WIDTH:0] delta_fw_0;
wire [`DELTA_WIDTH:0] delta_fw_1;
wire [`DELTA_WIDTH:0] delta_fw_2;
wire [`DELTA_WIDTH:0] delta_fw_3;
wire [`DELTA_WIDTH:0] delta_fw_4;
wire [`DELTA_WIDTH:0] delta_fw_5;
wire [`DELTA_WIDTH:0] delta_fw_6;
wire [`DELTA_WIDTH:0] delta_fw_7;
wire [`DELTA_WIDTH:0] delta_fw1_0;
wire [`DELTA_WIDTH:0] delta_fw1_1;
wire [`DELTA_WIDTH:0] delta_fw1_2;
wire [`DELTA_WIDTH:0] delta_fw1_3;
wire [`DELTA_WIDTH:0] delta_fw1_4;
wire [`DELTA_WIDTH:0] delta_fw1_5;
wire [`DELTA_WIDTH:0] delta_fw1_6;
wire [`DELTA_WIDTH:0] delta_fw1_7;
wire [`DELTA_WIDTH:0] delta_fw2_0;
wire [`DELTA_WIDTH:0] delta_fw2_1;
wire [`DELTA_WIDTH:0] delta_fw2_2;
wire [`DELTA_WIDTH:0] delta_fw2_3;
wire [`DELTA_WIDTH:0] delta_fw2_4;
wire [`DELTA_WIDTH:0] delta_fw2_5;
wire [`DELTA_WIDTH:0] delta_fw2_6;
wire [`DELTA_WIDTH:0] delta_fw2_7;
wire [`DELTA_WIDTH:0] delta_prev_0;
wire [`DELTA_WIDTH:0] delta_prev_1;
wire [`DELTA_WIDTH:0] delta_prev_2;
wire [`DELTA_WIDTH:0] delta_prev_3;
wire [`DELTA_WIDTH:0] delta_prev_4;
wire [`DELTA_WIDTH:0] delta_prev_5;
wire [`DELTA_WIDTH:0] delta_prev_6;
wire [`DELTA_WIDTH:0] delta_prev_7;
`PR_ALWAYS ("arg", `ALWAYS,"T%0d DEBUG_PIPE turned ON",mytnum);
//----------------------------------------------------------
// Note: no remap of %g,%o,%l,%i regs based on CWP or GL
assign g0 = (mytid<=3) ? `IRF3_EXU0[( 0+irf_offset)] : `IRF3_EXU1[( 0+irf_offset)];
assign g1 = (mytid<=3) ? `IRF3_EXU0[( 1+irf_offset)] : `IRF3_EXU1[( 1+irf_offset)];
assign g2 = (mytid<=3) ? `IRF3_EXU0[( 2+irf_offset)] : `IRF3_EXU1[( 2+irf_offset)];
assign g3 = (mytid<=3) ? `IRF3_EXU0[( 3+irf_offset)] : `IRF3_EXU1[( 3+irf_offset)];
assign g4 = (mytid<=3) ? `IRF3_EXU0[( 4+irf_offset)] : `IRF3_EXU1[( 4+irf_offset)];
assign g5 = (mytid<=3) ? `IRF3_EXU0[( 5+irf_offset)] : `IRF3_EXU1[( 5+irf_offset)];
assign g6 = (mytid<=3) ? `IRF3_EXU0[( 6+irf_offset)] : `IRF3_EXU1[( 6+irf_offset)];
assign g7 = (mytid<=3) ? `IRF3_EXU0[( 7+irf_offset)] : `IRF3_EXU1[( 7+irf_offset)];
assign o0 = (mytid<=3) ? `IRF3_EXU0[( 8+irf_offset)] : `IRF3_EXU1[( 8+irf_offset)];
assign o1 = (mytid<=3) ? `IRF3_EXU0[( 9+irf_offset)] : `IRF3_EXU1[( 9+irf_offset)];
assign o2 = (mytid<=3) ? `IRF3_EXU0[(10+irf_offset)] : `IRF3_EXU1[(10+irf_offset)];
assign o3 = (mytid<=3) ? `IRF3_EXU0[(11+irf_offset)] : `IRF3_EXU1[(11+irf_offset)];
assign o4 = (mytid<=3) ? `IRF3_EXU0[(12+irf_offset)] : `IRF3_EXU1[(12+irf_offset)];
assign o5 = (mytid<=3) ? `IRF3_EXU0[(13+irf_offset)] : `IRF3_EXU1[(13+irf_offset)];
assign o6 = (mytid<=3) ? `IRF3_EXU0[(14+irf_offset)] : `IRF3_EXU1[(14+irf_offset)];
assign o7 = (mytid<=3) ? `IRF3_EXU0[(15+irf_offset)] : `IRF3_EXU1[(15+irf_offset)];
assign l0 = (mytid<=3) ? `IRF3_EXU0[(16+irf_offset)] : `IRF3_EXU1[(16+irf_offset)];
assign l1 = (mytid<=3) ? `IRF3_EXU0[(17+irf_offset)] : `IRF3_EXU1[(17+irf_offset)];
assign l2 = (mytid<=3) ? `IRF3_EXU0[(18+irf_offset)] : `IRF3_EXU1[(18+irf_offset)];
assign l3 = (mytid<=3) ? `IRF3_EXU0[(19+irf_offset)] : `IRF3_EXU1[(19+irf_offset)];
assign l4 = (mytid<=3) ? `IRF3_EXU0[(20+irf_offset)] : `IRF3_EXU1[(20+irf_offset)];
assign l5 = (mytid<=3) ? `IRF3_EXU0[(21+irf_offset)] : `IRF3_EXU1[(21+irf_offset)];
assign l6 = (mytid<=3) ? `IRF3_EXU0[(22+irf_offset)] : `IRF3_EXU1[(22+irf_offset)];
assign l7 = (mytid<=3) ? `IRF3_EXU0[(23+irf_offset)] : `IRF3_EXU1[(23+irf_offset)];
assign i0 = (mytid<=3) ? `IRF3_EXU0[(24+irf_offset)] : `IRF3_EXU1[(24+irf_offset)];
assign i1 = (mytid<=3) ? `IRF3_EXU0[(25+irf_offset)] : `IRF3_EXU1[(25+irf_offset)];
assign i2 = (mytid<=3) ? `IRF3_EXU0[(26+irf_offset)] : `IRF3_EXU1[(26+irf_offset)];
assign i3 = (mytid<=3) ? `IRF3_EXU0[(27+irf_offset)] : `IRF3_EXU1[(27+irf_offset)];
assign i4 = (mytid<=3) ? `IRF3_EXU0[(28+irf_offset)] : `IRF3_EXU1[(28+irf_offset)];
assign i5 = (mytid<=3) ? `IRF3_EXU0[(29+irf_offset)] : `IRF3_EXU1[(29+irf_offset)];
assign i6 = (mytid<=3) ? `IRF3_EXU0[(30+irf_offset)] : `IRF3_EXU1[(30+irf_offset)];
assign i7 = (mytid<=3) ? `IRF3_EXU0[(31+irf_offset)] : `IRF3_EXU1[(31+irf_offset)];
//----------------------------------------------------------
assign frf_0 = `FRF3_EVEN[(mytid*32)+ 0];
assign frf_2 = `FRF3_EVEN[(mytid*32)+ 1];
assign frf_4 = `FRF3_EVEN[(mytid*32)+ 2];
assign frf_6 = `FRF3_EVEN[(mytid*32)+ 3];
assign frf_8 = `FRF3_EVEN[(mytid*32)+ 4];
assign frf_10 = `FRF3_EVEN[(mytid*32)+ 5];
assign frf_12 = `FRF3_EVEN[(mytid*32)+ 6];
assign frf_14 = `FRF3_EVEN[(mytid*32)+ 7];
assign frf_16 = `FRF3_EVEN[(mytid*32)+ 8];
assign frf_18 = `FRF3_EVEN[(mytid*32)+ 9];
assign frf_20 = `FRF3_EVEN[(mytid*32)+ 10];
assign frf_22 = `FRF3_EVEN[(mytid*32)+ 11];
assign frf_24 = `FRF3_EVEN[(mytid*32)+ 12];
assign frf_26 = `FRF3_EVEN[(mytid*32)+ 13];
assign frf_28 = `FRF3_EVEN[(mytid*32)+ 14];
assign frf_30 = `FRF3_EVEN[(mytid*32)+ 15];
assign frf_32 = `FRF3_EVEN[(mytid*32)+ 16];
assign frf_34 = `FRF3_EVEN[(mytid*32)+ 17];
assign frf_36 = `FRF3_EVEN[(mytid*32)+ 18];
assign frf_38 = `FRF3_EVEN[(mytid*32)+ 19];
assign frf_40 = `FRF3_EVEN[(mytid*32)+ 20];
assign frf_42 = `FRF3_EVEN[(mytid*32)+ 21];
assign frf_44 = `FRF3_EVEN[(mytid*32)+ 22];
assign frf_46 = `FRF3_EVEN[(mytid*32)+ 23];
assign frf_48 = `FRF3_EVEN[(mytid*32)+ 24];
assign frf_50 = `FRF3_EVEN[(mytid*32)+ 25];
assign frf_52 = `FRF3_EVEN[(mytid*32)+ 26];
assign frf_54 = `FRF3_EVEN[(mytid*32)+ 27];
assign frf_56 = `FRF3_EVEN[(mytid*32)+ 28];
assign frf_58 = `FRF3_EVEN[(mytid*32)+ 29];
assign frf_60 = `FRF3_EVEN[(mytid*32)+ 30];
assign frf_62 = `FRF3_EVEN[(mytid*32)+ 31];
assign frf_1 = `FRF3_ODD[(mytid*32)+ 0];
assign frf_3 = `FRF3_ODD[(mytid*32)+ 1];
assign frf_5 = `FRF3_ODD[(mytid*32)+ 2];
assign frf_7 = `FRF3_ODD[(mytid*32)+ 3];
assign frf_9 = `FRF3_ODD[(mytid*32)+ 4];
assign frf_11 = `FRF3_ODD[(mytid*32)+ 5];
assign frf_13 = `FRF3_ODD[(mytid*32)+ 6];
assign frf_15 = `FRF3_ODD[(mytid*32)+ 7];
assign frf_17 = `FRF3_ODD[(mytid*32)+ 8];
assign frf_19 = `FRF3_ODD[(mytid*32)+ 9];
assign frf_21 = `FRF3_ODD[(mytid*32)+ 10];
assign frf_23 = `FRF3_ODD[(mytid*32)+ 11];
assign frf_25 = `FRF3_ODD[(mytid*32)+ 12];
assign frf_27 = `FRF3_ODD[(mytid*32)+ 13];
assign frf_29 = `FRF3_ODD[(mytid*32)+ 14];
assign frf_31 = `FRF3_ODD[(mytid*32)+ 15];
assign frf_33 = `FRF3_ODD[(mytid*32)+ 16];
assign frf_35 = `FRF3_ODD[(mytid*32)+ 17];
assign frf_37 = `FRF3_ODD[(mytid*32)+ 18];
assign frf_39 = `FRF3_ODD[(mytid*32)+ 19];
assign frf_41 = `FRF3_ODD[(mytid*32)+ 20];
assign frf_43 = `FRF3_ODD[(mytid*32)+ 21];
assign frf_45 = `FRF3_ODD[(mytid*32)+ 22];
assign frf_47 = `FRF3_ODD[(mytid*32)+ 23];
assign frf_49 = `FRF3_ODD[(mytid*32)+ 24];
assign frf_51 = `FRF3_ODD[(mytid*32)+ 25];
assign frf_53 = `FRF3_ODD[(mytid*32)+ 26];
assign frf_55 = `FRF3_ODD[(mytid*32)+ 27];
assign frf_57 = `FRF3_ODD[(mytid*32)+ 28];
assign frf_59 = `FRF3_ODD[(mytid*32)+ 29];
assign frf_61 = `FRF3_ODD[(mytid*32)+ 30];
assign frf_63 = `FRF3_ODD[(mytid*32)+ 31];
//----------------------------------------------------------
assign delta_fx4_0 = delta_fx4[0];
assign delta_fx4_1 = delta_fx4[1];
assign delta_fx4_2 = delta_fx4[2];
assign delta_fx4_3 = delta_fx4[3];
assign delta_fx4_4 = delta_fx4[4];
assign delta_fx4_5 = delta_fx4[5];
assign delta_fx4_6 = delta_fx4[6];
assign delta_fx4_7 = delta_fx4[7];
assign delta_fx5_0 = delta_fx5[0];
assign delta_fx5_1 = delta_fx5[1];
assign delta_fx5_2 = delta_fx5[2];
assign delta_fx5_3 = delta_fx5[3];
assign delta_fx5_4 = delta_fx5[4];
assign delta_fx5_5 = delta_fx5[5];
assign delta_fx5_6 = delta_fx5[6];
assign delta_fx5_7 = delta_fx5[7];
assign delta_fb_0 = delta_fb[0];
assign delta_fb_1 = delta_fb[1];
assign delta_fb_2 = delta_fb[2];
assign delta_fb_3 = delta_fb[3];
assign delta_fb_4 = delta_fb[4];
assign delta_fb_5 = delta_fb[5];
assign delta_fb_6 = delta_fb[6];
assign delta_fb_7 = delta_fb[7];
assign delta_fw_0 = delta_fw[0];
assign delta_fw_1 = delta_fw[1];
assign delta_fw_2 = delta_fw[2];
assign delta_fw_3 = delta_fw[3];
assign delta_fw_4 = delta_fw[4];
assign delta_fw_5 = delta_fw[5];
assign delta_fw_6 = delta_fw[6];
assign delta_fw_7 = delta_fw[7];
assign delta_fw1_0 = delta_fw1[0];
assign delta_fw1_1 = delta_fw1[1];
assign delta_fw1_2 = delta_fw1[2];
assign delta_fw1_3 = delta_fw1[3];
assign delta_fw1_4 = delta_fw1[4];
assign delta_fw1_5 = delta_fw1[5];
assign delta_fw1_6 = delta_fw1[6];
assign delta_fw1_7 = delta_fw1[7];
assign delta_fw2_0 = delta_fw2[0];
assign delta_fw2_1 = delta_fw2[1];
assign delta_fw2_2 = delta_fw2[2];
assign delta_fw2_3 = delta_fw2[3];
assign delta_fw2_4 = delta_fw2[4];
assign delta_fw2_5 = delta_fw2[5];
assign delta_fw2_6 = delta_fw2[6];
assign delta_fw2_7 = delta_fw2[7];
assign delta_prev_0 = delta_prev[0];
assign delta_prev_1 = delta_prev[1];
assign delta_prev_2 = delta_prev[2];
assign delta_prev_3 = delta_prev[3];
assign delta_prev_4 = delta_prev[4];
assign delta_prev_5 = delta_prev[5];
assign delta_prev_6 = delta_prev[6];
assign delta_prev_7 = delta_prev[7];
//----------------------------------------------------------
//----------------------------------------------------------
assign mytnum = (mycid*8)+mytid;
assign mytg = mytid >> 2;
assign exu_complete = exu_valid & ~(`PROBES3.clkstop_d5|`TOP.in_reset|`SPC3.tcu_scan_en);
assign imul_complete = imul_valid & ~(`TOP.in_reset|`SPC3.tcu_scan_en);
assign idiv_complete = idiv_valid & ~(`TOP.in_reset|`SPC3.tcu_scan_en);
assign tlu_complete = tlu_complete_3 ;
assign fp_complete = fp_valid & ~(`TOP.in_reset|`SPC3.tcu_scan_en);
assign fdiv_complete = fdiv_valid & ~(`TOP.in_reset|`SPC3.tcu_scan_en);
assign lsu_complete = lsu_valid & ~(`TOP.in_reset|`SPC3.tcu_scan_en);
assign asi_complete = asi_valid & ~(`TOP.in_reset|`SPC3.tcu_scan_en);
assign complete_w = (exu_complete << `EXU_INDEX) |
(lsu_complete << `LSU_INDEX) |
(tlu_complete << `TLU_INDEX) |
(asi_complete << `ASI_INDEX) ;
assign oddwin = CWP_reg % 2;
assign frf_w1_valid_even = (frf_w1_tid_fw == mytid) & frf_w1_valid_fw[1];
assign frf_w1_valid_odd = (frf_w1_tid_fw == mytid) & frf_w1_valid_fw[0];
assign frf_w2_valid_even = (frf_w2_tid_fw == mytid) & frf_w2_valid_fw[1];
assign frf_w2_valid_odd = (frf_w2_tid_fw == mytid) & frf_w2_valid_fw[0];
assign frf_w1_skip_addr = frf_w1_addr_fw;
assign frf_w2_skip_addr = frf_w2_addr_fw;
// NOTE - ADD_TSB_CFG will never be used for Axis or Tharas
wire [63:0] ctxt_z_tsb_cfg0_reg = `PROBES3.ctxt_z_tsb_cfg0_reg[mytid];
wire [63:0] ctxt_z_tsb_cfg1_reg = `PROBES3.ctxt_z_tsb_cfg1_reg[mytid];
wire [63:0] ctxt_z_tsb_cfg2_reg = `PROBES3.ctxt_z_tsb_cfg2_reg[mytid];
wire [63:0] ctxt_z_tsb_cfg3_reg = `PROBES3.ctxt_z_tsb_cfg3_reg[mytid];
wire [63:0] ctxt_nz_tsb_cfg0_reg = `PROBES3.ctxt_nz_tsb_cfg0_reg[mytid];
wire [63:0] ctxt_nz_tsb_cfg1_reg = `PROBES3.ctxt_nz_tsb_cfg1_reg[mytid];
wire [63:0] ctxt_nz_tsb_cfg2_reg = `PROBES3.ctxt_nz_tsb_cfg2_reg[mytid];
wire [63:0] ctxt_nz_tsb_cfg3_reg = `PROBES3.ctxt_nz_tsb_cfg3_reg[mytid];
//----------------------------------------------------------
always @ (posedge `BENCH_SPC3_GCLK) begin // {
// TLU is async to the execution pipeline
// but needs to be delayed to allow CWP, etc to update and be stable
// before arch state is captured and diff_reg is called.
// FDIV was moved from fw1 to fw to allow FPRS to be stable before capture
tlu_complete_1 <= tlu_valid & ~(`TOP.in_reset|`SPC3.tcu_scan_en);
tlu_complete_2 <= tlu_complete_1;
tlu_complete_3 <= tlu_complete_2;
itagacc_fx5 <= I_TAG_ACC_reg; // Signal changes in W so need to pipeline to fw2
itagacc_fb <= itagacc_fx5;
itagacc_fw <= itagacc_fb;
itagacc_fw1 <= itagacc_fw;
itagacc_fw2 <= itagacc_fw1;
dtagacc_fx5 <= D_TAG_ACC_reg; // Signal changes in W so need to pipeline to fw2
dtagacc_fb <= dtagacc_fx5;
dtagacc_fw <= dtagacc_fb;
dtagacc_fw1 <= dtagacc_fw;
dtagacc_fw2 <= dtagacc_fw1;
dsfar_fb <= DSFAR_reg; // Signal changes in W+1 so need to pipeline to fw2
complete_fx4 <= complete_w;
complete_fx5 <= complete_fx4 ;
complete_fb <= complete_fx5 |
(idiv_complete << `IDIV_INDEX);
complete_fw <= complete_fb |
(fdiv_complete << `FDIV_INDEX) |
(imul_complete << `IMUL_INDEX);
complete_fw1 <= complete_fw |
(fp_complete << `FP_INDEX);
complete_fw2 <= complete_fw1;
frf_w1_valid_fw1 <= (frf_w1_valid_odd | frf_w1_valid_even) & fp_complete;
frf_w1_valid_fw2 <= frf_w1_valid_fw1;
frf_w1_skip_addr4_fw1 <= frf_w1_skip_addr[4];
frf_w1_skip_addr4_fw2 <= frf_w1_skip_addr4_fw1;
frf_w2_valid_fw <= frf_w2_valid_bn;
frf_w2_tid_fw <= frf_w2_tid;
frf_w2_addr_fw <= frf_w2_addr;
frf_w1_valid_fw <= frf_w1_valid;
frf_w1_tid_fw <= frf_w1_tid;
frf_w1_addr_fw <= frf_w1_addr;
if (~thread_running & `SPC3.tcu_core_running[mytid])
`TOP.th_last_act_cycle[mytnum] = `TOP.core_cycle_cnt;
thread_running <= `SPC3.tcu_core_running[mytid];
// Reset some register prev state on wmr negation
if (`SPC3.rst_wmr_protect && ~wmr)
wmr <= `SPC3.rst_wmr_protect;
if (`SPC3.rst_wmr_protect)
//----------------------------------------------------------
// Holding state for registers that may be updated asynchronously
// after synchronous update, but before capture/step. Also for reads,
// when register is read and modified before capture/step ..
// We capture the value /write time, and use that for sstep,
// ignoring any async updates, which are sent in the NEXT sstep ..
reg [63:0] asi_updated_int_rec;
reg asi_wr_int_rec_delay;
reg [16:0] asi_updated_softint;
reg asi_wr_softint_delay;
reg [16:0] asi_softint_wrdata;
always @(posedge `BENCH_SPC3_GCLK) begin // {
// Corner case : If async and sync wr occur in same clock, then the async
// update takes place. In this case we have to capture the
// value of the write WITHOUT async bit being set, so that
// we can sync with Riesling's sync write ..
asi_wr_int_rec_delay <= ( `SPC3.tlu.cth.asi_wr_int_rec[mytid] |
`SPC3.tlu.asi_rd_inc_vec_2[mytid]);
if (`SPC3.tlu.cth.asi_wr_int_rec[mytid] |
((`SPC3.tlu.asi.rd_inc_vec) &&
(`SPC3.tlu.asi.rd_tid_dec[mytid])) |
(`SPC3.tlu.asi_rd_int_rec &
`SPC3.tlu.cth.int_rec_mux_sel==mytid))
if (`SPC3.tlu.cth.asi_wr_int_rec[mytid])
asi_updated_int_rec <= `SPC3.tlu.cth.int_rec ;
else if ( (`SPC3.tlu.asi.rd_inc_vec) &&
(`SPC3.tlu.asi.rd_tid_dec[mytid]) )
if (`SPC3.tlu.cth.cxi_wr_int_dis[mytid]) begin
asi_updated_int_rec <= INTR_RECEIVE_reg & `SPC3.tlu.cth.int_rec_muxed_;
asi_updated_int_rec[`SPC3.tlu.cth.incoming_vector_in] <= 1'b0 ;
asi_updated_int_rec <= `SPC3.tlu.cth.int_rec_muxed ;
asi_updated_int_rec[`SPC3.tlu.cth.incoming_vector_in] <= 1'b0 ;
asi_updated_int_rec <= INTR_RECEIVE_reg;
asi_rdwr_int_rec <= 1'b1;
else if (complete_fw1 && !`NASTOP.sstep_early[mytnum])
asi_rdwr_int_rec <= 1'b0;
asi_wr_hintp_delay <= `SPC3.tlu.asi_wr_hintp[mytid];
if (`SPC3.tlu.asi_wr_hintp[mytid] |
`SPC3.tlu.asi_rd_hintp[mytid])
if (`SPC3.tlu.asi_wr_hintp[mytid])
asi_updated_hintp <= `SPC3.tlu.asi_wr_data_0[0] ;
asi_updated_hintp <= HINTP_reg;
else if (complete_fw1 && !`NASTOP.sstep_early[mytnum])
asi_wr_softint_delay <= (`SPC3.tlu.asi_wr_softint[mytid] |
`SPC3.tlu.asi_wr_clear_softint[mytid] |
`SPC3.tlu.asi_wr_set_softint[mytid]);
if (`SPC3.tlu.asi_wr_clear_softint[mytid])
asi_softint_wrdata <= ~`SPC3.tlu.asi_wr_data_0[16:0] & rd_SOFTINT_reg;
else if (`SPC3.tlu.asi_wr_set_softint[mytid])
asi_softint_wrdata <= `SPC3.tlu.asi_wr_data_0[16:0] | rd_SOFTINT_reg;
asi_softint_wrdata <= `SPC3.tlu.asi_wr_data_0[16:0];
if (asi_wr_softint_delay | `SPC3.tlu.asi_rd_softint[mytid])
if (asi_wr_softint_delay)
asi_updated_softint <= asi_softint_wrdata ;
asi_updated_softint <= rd_SOFTINT_reg ;
asi_rdwr_softint <= 1'b1;
else if (complete_fw1 && !`NASTOP.sstep_early[mytnum])
asi_rdwr_softint <= 1'b0;
//----------------------------------------------------------
// Negedge sampling to avoid race on specific signals ..
always @ (negedge `BENCH_SPC3_GCLK) begin // {
frf_w2_valid_bn <= frf_w2_valid;
//----------------------------------------------------------
// When instruction completes,
// Push differences to simics
always @ (posedge `BENCH_SPC3_GCLK) begin // {
if (`PARGS.th_check_enable[mytnum] && nas_pipe_enable && ~`SPC3.tcu_scan_en && ~`TOP.in_por) begin // {
// Update window registers
if (CWP_reg != `NASTOP.th_cwp[mytnum]) begin // {
copy_win (CWP_reg,`NASTOP.th_cwp[mytnum]);
`NASTOP.th_cwp[mytnum] = CWP_reg;
// Update global registers
// Wait for warm-reset flush related toggling to settle
if (GL_reg != th_gl) begin // {
if (`SPC3.spc_core_running_status[mytid] &
~`SPC3.rst_wmr_protect) begin // {
copy_global (GL_reg,th_gl);
// Check for bad signal values
// if NASTOP.sstep_sent[tid]=1,
// then SSTEP was set by another module (i.e. tlb_sync)
if (`PARGS.nas_check_on) begin // {
mytime = `TOP.core_cycle_cnt-1;
if (complete_fw2 && (`NASTOP.sstep_sent[mytnum]==1'b0)) begin // {
`PR_INFO ("pli_nas", `INFO, " C%0d T%0d PLI_SSTEP tid=%d pc=%h ts=%0d ",
mycid,mytid,mytnum,pc_fw2,mytime);
junk = $sim_send(`PLI_SSTEP, mytnum);
// Always clear sstep_early
// In case tlb_sync asserted it too late for complete_fw2
`NASTOP.sstep_early[mytnum] <= 1'b0;
else if (complete_fw2) begin // {
`NASTOP.sstep_sent[mytnum] <= 1'b0; // re-arm SSTEP
`NASTOP.sstep_early[mytnum] <= 1'b0;
`PR_INFO ("pli_nas", `INFO, " C%0d T%0d PLI_SSTEP tid=%d pc=%h ts=%0d (nas_pipe: skip sstep. rearm sstep. sstep_sent=0)",
mycid,mytid,mytnum,pc_fw2,mytime);
// Only capture if something completes and not first instruction
if (complete_fw2 && !first_op) begin // {
push_simics; // Use with AXIS to keep from getting timeout
// Pipeline runs continuously
// Other than when in POR ..
// Only save to delta_prev when something completes
`TOP.last_act_cycle = `TOP.core_cycle_cnt; //$time;
`TOP.th_last_act_cycle[mytnum] = `TOP.last_act_cycle;
// If something was captured but no instruction is in the pipeline
if ((delta_fw2[`NEXT_INDEX]!=`FIRST_INDEX) && (complete_fw2 == 0))
for (myindex=`FIRST_INDEX; myindex<delta_fw2[`NEXT_INDEX]; myindex=myindex+1)
print_entry (delta_fw2[myindex]);
`PR_ERROR ("nas",`ERROR, "T%0d Unexpected Reg change in DUT. Special case - no instruction retired.", mytnum);
// End detection for non-sas runs ..
for (junk=0;junk<`PARGS.bad_trap_count;junk=junk+1)
if (({16'b0,pc_fw2}&`PC_MASK) ===
(`PARGS.bad_trap_addr[junk]&`PC_MASK)) begin // {
// Disable nas_pipe processing (capture & SSTEP)
// to speed up simulation (minimize socket traffic,etc)
if (! `PARGS.nas_check_on) begin //{
`PR_ERROR ("nas",`ERROR, "T%0d reached Bad Trap", mytnum);
for (junk=0;junk<`PARGS.good_trap_count;junk=junk+1)
if ((|complete_fw2) && (({16'b0,pc_fw2}&`PC_MASK) ===
(`PARGS.good_trap_addr[junk]&`PC_MASK))) begin // {
// Disable nas_pipe processing (capture & SSTEP)
// to speed up simulation (minimize socket traffic,etc)
if (! `PARGS.nas_check_on) begin //{
good_trap_detected = 1'b1;
// Check Thread level timeout
(`TOP.core_cycle_cnt - `TOP.th_last_act_cycle[mytnum]) > `PARGS.th_timeout)
// Note: Do not change this message because regreport parses it for certain words.
`PR_ALWAYS ("nas",`ALWAYS, "ERROR: Thread T%0d No Activity for %0d Cycles - Thread TIMEOUT!",
mytnum, `PARGS.th_timeout);
junk = incErr(9999); // must exceed users max error setting to force exit.
end // if (`PARGS.th_check_enable[mytnum] && nas_pipe_enable ...)}
// Need to make sure Store Buffer is empty before turning off th_check_enable.
//global chkr requires to wait for all outstanding pending I
if ((! `PARGS.nas_check_on) &&
(good_trap_detected==1'b1) &&
(`TOP.nas_top.lsu_stb_empty[mytnum]) && `TOP.nas_top.ireq_pending[mytnum]) begin // {
`PARGS.th_check_enable[mytnum] = 1'b0;
`TOP.finished_tids[mytnum] = 1'b1;
good_trap_detected = 1'b0;
`PR_NORMAL ("nas", `NORMAL, "T%0d reached Good Trap. Disabling checking for thread %0d", mytnum,mytnum);
//----------------------------------------------------------
//----------------------------------------------------------
// Stage FX4 of delta pipeline
delta_fx4[`NEXT_INDEX] <= `FIRST_INDEX;
delta_fx4[`TIME_INDEX] <= 0;
delta_fx4[`PC_INDEX] <= {16'b0,PC_reg};
delta_fx4[`GL_INDEX] <= GL_reg;
delta_fx4[`CWP_INDEX] <= CWP_reg;
delta_fx4[`OPCODE_INDEX] <= opcode;
delta_fx4[`FIRST_INDEX] <= 77'hx;
//----------------------------------------------------------
// Stage FX5 of delta pipeline
index = delta_fx4[`NEXT_INDEX];
// Pipeline previous stage
for (i=0; i<=delta_fx4[`NEXT_INDEX]; i=i+1) begin // {
delta_fx5[i] <= delta_fx4[i];
if (complete_fx4) begin // LSU | EXU | TLU
push_delta_fx5 (`CCR+`CTL_OFFSET,CCR_reg,index);
if (complete_fx4[`LSU_INDEX] |
complete_fx4[`EXU_INDEX]) begin
if (mytid <= 3) begin // {
for (i=0; i<=31; i=i+1) begin // {
push_delta_fx5 (i,`IRF3_EXU0[(remap(i,oddwin)+irf_offset)],index);
for (i=0; i<=31; i=i+1) begin // {
push_delta_fx5 (i,`IRF3_EXU1[(remap(i,oddwin)+irf_offset)],index);
// Update FRF3 - Loads use W2 Port.
if (complete_fx4[`LSU_INDEX]) begin // {
// IF W1 port is also being written, ignore that address
for (i=0; i<=31; i=i+1) begin // {
if (!((i == frf_w1_skip_addr) && frf_w1_valid_even)) begin // {
frf_tmp = `FRF3_EVEN[(mytid*32)+i];
push_delta_fx5 (`FP_OFFSET + (i*2), frf_tmp[31:0], index);
if (!((i == frf_w1_skip_addr) && frf_w1_valid_odd)) begin // {
frf_tmp = `FRF3_ODD[(mytid*32)+i];
push_delta_fx5 (`FP_OFFSET + (i*2)+1, frf_tmp[31:0], index);
// Update ASR/ASI registers
if (complete_fx4) begin // {
push_delta_fx5 (`PSTATE + `CTL_OFFSET,PSTATE_reg,index);
push_delta_fx5 (`HPSTATE + `CTL_OFFSET,HPSTATE_reg,index);
push_delta_fx5 (`PIL + `CTL_OFFSET,PIL_reg,index);
push_delta_fx5 (`TBA + `CTL_OFFSET,{TBA_reg,15'b0},index);
push_delta_fx5 (`GL + `CTL_OFFSET,GL_reg,index);
push_delta_fx5 (`HTBA + `CTL_OFFSET,{HTBA_reg,14'b0},index);
push_delta_fx5 (`VER + `CTL_OFFSET,VER_reg,index);
push_delta_fx5 (`Y + `CTL_OFFSET,Y_reg,index);
push_delta_fx5 (`ASI + `CTL_OFFSET,ASI_reg,index);
push_delta_fx5 (`STICK_CMPR + `CTL_OFFSET,STICK_CMPR_wire,index);
push_delta_fx5 (`HSTICK_CMPR + `CTL_OFFSET,HSTICK_CMPR_wire,index);
push_delta_fx5 (`TICK_CMPR + `CTL_OFFSET,TICK_CMPR_wire,index);
push_delta_fx5 (`CWP + `CTL_OFFSET,CWP_reg,index);
push_delta_fx5 (`CANSAVE + `CTL_OFFSET,CANSAVE_reg,index);
push_delta_fx5 (`CANRESTORE + `CTL_OFFSET,CANRESTORE_reg,index);
push_delta_fx5 (`CLEANWIN + `CTL_OFFSET,CLEANWIN_reg,index);
push_delta_fx5 (`OTHERWIN + `CTL_OFFSET,OTHERWIN_reg,index);
push_delta_fx5 (`WSTATE + `CTL_OFFSET,WSTATE_reg,index);
push_delta_fx5 (`CTXT_PRIM_0+`CTL_OFFSET,CTXT_PRIM_0_reg,index);
push_delta_fx5 (`CTXT_SEC_0+`CTL_OFFSET,CTXT_SEC_0_reg,index);
push_delta_fx5 (`CTXT_PRIM_1+`CTL_OFFSET,CTXT_PRIM_1_reg,index);
push_delta_fx5 (`CTXT_SEC_1+`CTL_OFFSET,CTXT_SEC_1_reg,index);
push_delta_fx5 (`LSU_CONTROL+`CTL_OFFSET,LSU_CONTROL_reg,index);
push_delta_fx5 (`WATCHPOINT_ADDR+`CTL_OFFSET,WATCHPOINT_ADDR_reg,index);
// NOTE - ADD_TSB_CFG will never be used for Axis or Tharas
push_delta_fx5 (`CTXT_Z_TSB_CFG0+`CTL_OFFSET,ctxt_z_tsb_cfg0_reg,index);
push_delta_fx5 (`CTXT_Z_TSB_CFG1+`CTL_OFFSET,ctxt_z_tsb_cfg1_reg,index);
push_delta_fx5 (`CTXT_Z_TSB_CFG2+`CTL_OFFSET,ctxt_z_tsb_cfg2_reg,index);
push_delta_fx5 (`CTXT_Z_TSB_CFG3+`CTL_OFFSET,ctxt_z_tsb_cfg3_reg,index);
push_delta_fx5 (`CTXT_NZ_TSB_CFG0+`CTL_OFFSET,ctxt_nz_tsb_cfg0_reg,index);
push_delta_fx5 (`CTXT_NZ_TSB_CFG1+`CTL_OFFSET,ctxt_nz_tsb_cfg1_reg,index);
push_delta_fx5 (`CTXT_NZ_TSB_CFG2+`CTL_OFFSET,ctxt_nz_tsb_cfg2_reg,index);
push_delta_fx5 (`CTXT_NZ_TSB_CFG3+`CTL_OFFSET,ctxt_nz_tsb_cfg3_reg,index);
// Update GSR for all except write ASR in progess
if (!asi_in_progress) begin // {
push_delta_fx5 (`GSR + `CTL_OFFSET,GSR_wire, index);
// If lsu_complete & fp_complete assert at same time,
// then the fp_complete is the one that will modify the FSR
if (complete_fx4[`LSU_INDEX] & !complete_fw1[`FP_INDEX]) begin
push_delta_fx5 (`FSR+`CTL_OFFSET,FSR_wire,index);
// Non Trap updates of Trap stack & level
if (complete_fx4 && !complete_fx4[`TLU_INDEX]) begin // {
push_delta_fx5 (`TL + `CTL_OFFSET,TL_reg,index);
push_delta_fx5 (`TPC1 + `CTL_OFFSET, TPC1_wire, index);
push_delta_fx5 (`TPC2 + `CTL_OFFSET, TPC2_wire, index);
push_delta_fx5 (`TPC3 + `CTL_OFFSET, TPC3_wire, index);
push_delta_fx5 (`TPC4 + `CTL_OFFSET, TPC4_wire, index);
push_delta_fx5 (`TPC5 + `CTL_OFFSET, TPC5_wire, index);
push_delta_fx5 (`TPC6 + `CTL_OFFSET, TPC6_wire, index);
push_delta_fx5 (`TNPC1 + `CTL_OFFSET, TNPC1_wire, index);
push_delta_fx5 (`TNPC2 + `CTL_OFFSET, TNPC2_wire, index);
push_delta_fx5 (`TNPC3 + `CTL_OFFSET, TNPC3_wire, index);
push_delta_fx5 (`TNPC4 + `CTL_OFFSET, TNPC4_wire, index);
push_delta_fx5 (`TNPC5 + `CTL_OFFSET, TNPC5_wire, index);
push_delta_fx5 (`TNPC6 + `CTL_OFFSET, TNPC6_wire, index);
push_delta_fx5 (`TSTATE1 + `CTL_OFFSET, TSTATE1_wire, index);
push_delta_fx5 (`TSTATE2 + `CTL_OFFSET, TSTATE2_wire, index);
push_delta_fx5 (`TSTATE3 + `CTL_OFFSET, TSTATE3_wire, index);
push_delta_fx5 (`TSTATE4 + `CTL_OFFSET, TSTATE4_wire, index);
push_delta_fx5 (`TSTATE5 + `CTL_OFFSET, TSTATE5_wire, index);
push_delta_fx5 (`TSTATE6 + `CTL_OFFSET, TSTATE6_wire, index);
push_delta_fx5 (`HTSTATE1 + `CTL_OFFSET, HTSTATE1_wire, index);
push_delta_fx5 (`HTSTATE2 + `CTL_OFFSET, HTSTATE2_wire, index);
push_delta_fx5 (`HTSTATE3 + `CTL_OFFSET, HTSTATE3_wire, index);
push_delta_fx5 (`HTSTATE4 + `CTL_OFFSET, HTSTATE4_wire, index);
push_delta_fx5 (`HTSTATE5 + `CTL_OFFSET, HTSTATE5_wire, index);
push_delta_fx5 (`HTSTATE6 + `CTL_OFFSET, HTSTATE6_wire, index);
push_delta_fx5 (`TT1 + `CTL_OFFSET, TT1_wire, index);
push_delta_fx5 (`TT2 + `CTL_OFFSET, TT2_wire, index);
push_delta_fx5 (`TT3 + `CTL_OFFSET, TT3_wire, index);
push_delta_fx5 (`TT4 + `CTL_OFFSET, TT4_wire, index);
push_delta_fx5 (`TT5 + `CTL_OFFSET, TT5_wire, index);
push_delta_fx5 (`TT6 + `CTL_OFFSET, TT6_wire, index);
//----------------------------------------------------------
// Stage FB of delta pipeline
index = delta_fx5[`NEXT_INDEX];
// Pipeline previous stage
for (i=0; i<=delta_fx5[`NEXT_INDEX]; i=i+1) begin // {
delta_fb[i] <= delta_fx5[i];
if (complete_fx5[`ASI_INDEX]) begin // {
push_delta_fb (`GSR + `CTL_OFFSET,GSR_wire, index);
//----------------------------------------------------------
// Stage FW of delta pipeline
index = delta_fb[`NEXT_INDEX];
// Pipeline previous stage
for (i=0; i<=delta_fb[`NEXT_INDEX]; i=i+1) begin // {
delta_fw[i] <= delta_fb[i];
// Capture CWP_reg for SAVE/RESTORE
delta_fw[`CWP_INDEX] <= CWP_reg;
if (complete_fb[`TLU_INDEX]) begin
if (mytid <= 3) begin // {
for (i=0; i<=31; i=i+1) begin // {
push_delta_fw (i,`IRF3_EXU0[(remap(i,oddwin)+irf_offset)],index);
for (i=0; i<=31; i=i+1) begin // {
push_delta_fw (i,`IRF3_EXU1[(remap(i,oddwin)+irf_offset)],index);
// Update FRF3 - Idivs use W2.
if (complete_fb[`IDIV_INDEX]) begin // {
// IF W1 port is also being written, ignore that address
for (i=0; i<=31; i=i+1) begin // {
if (!((i == frf_w1_skip_addr) && frf_w1_valid_even)) begin // {
frf_tmp = `FRF3_EVEN[(mytid*32)+i];
push_delta_fw (`FP_OFFSET + (i*2), frf_tmp[31:0], index);
if (!((i == frf_w1_skip_addr) && frf_w1_valid_odd)) begin // {
frf_tmp = `FRF3_ODD[(mytid*32)+i];
push_delta_fw (`FP_OFFSET + (i*2)+1,frf_tmp[31:0], index);
//----------------------------------------------------------
// Stage FW1 of delta pipeline
index = delta_fw[`NEXT_INDEX];
// Pipeline previous stage
for (i=0; i<=delta_fw[`NEXT_INDEX]; i=i+1) begin // {
delta_fw1[i] <= delta_fw[i];
// Update FRF3 - FPops use W1 port.
if (fp_complete) begin // {
// IF W2 port is also being written, ignore that address
for (i=0; i<=31; i=i+1) begin // {
if (!((i == frf_w2_skip_addr) && frf_w2_valid_even)) begin // {
frf_tmp = `FRF3_EVEN[(mytid*32)+i];
push_delta_fw1 (`FP_OFFSET + (i*2), frf_tmp[31:0], index);
if (!((i == frf_w2_skip_addr) && frf_w2_valid_odd)) begin // {
frf_tmp = `FRF3_ODD[(mytid*32)+i];
push_delta_fw1 (`FP_OFFSET + (i*2)+1,frf_tmp[31:0], index);
if (complete_fw[`IMUL_INDEX]|complete_fw[`IDIV_INDEX]) begin
push_delta_fw1 (`CCR+`CTL_OFFSET,CCR_reg,index);
push_delta_fw1 (`Y+`CTL_OFFSET,Y_reg,index);
push_delta_fw1 (`CWP+`CTL_OFFSET,CWP_reg,index);
push_delta_fw1 (`CANSAVE+`CTL_OFFSET,CANSAVE_reg,index);
push_delta_fw1 (`CANRESTORE+`CTL_OFFSET,CANRESTORE_reg,index);
push_delta_fw1 (`CLEANWIN+`CTL_OFFSET,CLEANWIN_reg,index);
push_delta_fw1 (`OTHERWIN+`CTL_OFFSET,OTHERWIN_reg,index);
push_delta_fw1 (`WSTATE+`CTL_OFFSET,WSTATE_reg,index);
if (complete_fw[`TLU_INDEX]) begin // {
push_delta_fw1 (`TL + `CTL_OFFSET,TL_reg,index);
push_delta_fw1 (`TPC1 + `CTL_OFFSET, TPC1_wire, index);
push_delta_fw1 (`TPC2 + `CTL_OFFSET, TPC2_wire, index);
push_delta_fw1 (`TPC3 + `CTL_OFFSET, TPC3_wire, index);
push_delta_fw1 (`TPC4 + `CTL_OFFSET, TPC4_wire, index);
push_delta_fw1 (`TPC5 + `CTL_OFFSET, TPC5_wire, index);
push_delta_fw1 (`TPC6 + `CTL_OFFSET, TPC6_wire, index);
push_delta_fw1 (`TNPC1 + `CTL_OFFSET, TNPC1_wire, index);
push_delta_fw1 (`TNPC2 + `CTL_OFFSET, TNPC2_wire, index);
push_delta_fw1 (`TNPC3 + `CTL_OFFSET, TNPC3_wire, index);
push_delta_fw1 (`TNPC4 + `CTL_OFFSET, TNPC4_wire, index);
push_delta_fw1 (`TNPC5 + `CTL_OFFSET, TNPC5_wire, index);
push_delta_fw1 (`TNPC6 + `CTL_OFFSET, TNPC6_wire, index);
push_delta_fw1 (`TSTATE1 + `CTL_OFFSET, TSTATE1_wire, index);
push_delta_fw1 (`TSTATE2 + `CTL_OFFSET, TSTATE2_wire, index);
push_delta_fw1 (`TSTATE3 + `CTL_OFFSET, TSTATE3_wire, index);
push_delta_fw1 (`TSTATE4 + `CTL_OFFSET, TSTATE4_wire, index);
push_delta_fw1 (`TSTATE5 + `CTL_OFFSET, TSTATE5_wire, index);
push_delta_fw1 (`TSTATE6 + `CTL_OFFSET, TSTATE6_wire, index);
push_delta_fw1 (`HTSTATE1 + `CTL_OFFSET, HTSTATE1_wire, index);
push_delta_fw1 (`HTSTATE2 + `CTL_OFFSET, HTSTATE2_wire, index);
push_delta_fw1 (`HTSTATE3 + `CTL_OFFSET, HTSTATE3_wire, index);
push_delta_fw1 (`HTSTATE4 + `CTL_OFFSET, HTSTATE4_wire, index);
push_delta_fw1 (`HTSTATE5 + `CTL_OFFSET, HTSTATE5_wire, index);
push_delta_fw1 (`HTSTATE6 + `CTL_OFFSET, HTSTATE6_wire, index);
push_delta_fw1 (`TT1 + `CTL_OFFSET, TT1_wire, index);
push_delta_fw1 (`TT2 + `CTL_OFFSET, TT2_wire, index);
push_delta_fw1 (`TT3 + `CTL_OFFSET, TT3_wire, index);
push_delta_fw1 (`TT4 + `CTL_OFFSET, TT4_wire, index);
push_delta_fw1 (`TT5 + `CTL_OFFSET, TT5_wire, index);
push_delta_fw1 (`TT6 + `CTL_OFFSET, TT6_wire, index);
//----------------------------------------------------------
// Stage FW2 of delta pipeline
index = delta_fw1[`NEXT_INDEX];
// Pipeline previous stage
for (i=0; i<=delta_fw1[`NEXT_INDEX]; i=i+1) begin // {
delta_fw2[i] <= delta_fw1[i];
delta_fw2[`TIME_INDEX] <= $time;
// Update Registers that may change asynchronously
// If sstep was already sent by another module,
// don't capture until the next sstep
if (complete_fw1 && !`NASTOP.sstep_early[mytnum]) begin // {
if ((complete_fw1[`ASI_INDEX]|complete_fw1[`LSU_INDEX]) & asi_rdwr_hintp)
push_delta_fw2 (`HINTP + `CTL_OFFSET,asi_updated_hintp,index);
push_delta_fw2 (`HINTP + `CTL_OFFSET,HINTP_reg,index);
if ((complete_fw1[`ASI_INDEX]|complete_fw1[`LSU_INDEX]) & asi_rdwr_softint)
push_delta_fw2 (`SOFTINT + `CTL_OFFSET,asi_updated_softint,index);
push_delta_fw2 (`SOFTINT + `CTL_OFFSET,rd_SOFTINT_reg,index);
if (complete_fw1[`IMUL_INDEX] |
complete_fw1[`IDIV_INDEX]) begin // {
if (mytid <= 3) begin // {
for (i=0; i<=31; i=i+1) begin // {
push_delta_fw2 (i,`IRF3_EXU0[(remap(i,oddwin)+irf_offset)],index);
for (i=0; i<=31; i=i+1) begin // {
push_delta_fw2 (i,`IRF3_EXU1[(remap(i,oddwin)+irf_offset)],index);
// Update FRF3 - fdivs and Imuls use W2 port
if (complete_fw1[`IMUL_INDEX] |
complete_fw1[`FDIV_INDEX] ) begin // {
// IF W1 port is also being written, ignore that address
for (i=0; i<=31; i=i+1) begin // {
if (!((i == frf_w1_skip_addr) && frf_w1_valid_even)) begin // {
frf_tmp = `FRF3_EVEN[(mytid*32)+i];
push_delta_fw2 (`FP_OFFSET + (i*2), frf_tmp[31:0], index);
if (!((i == frf_w1_skip_addr) && frf_w1_valid_odd)) begin // {
frf_tmp = `FRF3_ODD[(mytid*32)+i];
push_delta_fw2 (`FP_OFFSET + (i*2)+1,frf_tmp[31:0], index);
if (complete_fw1[`FP_INDEX] |
complete_fw1[`TLU_INDEX] |
complete_fw1[`FDIV_INDEX]) begin
push_delta_fw2 (`FSR+`CTL_OFFSET,FSR_wire,index);
push_delta_fw2 (`I_TAG_ACC+`CTL_OFFSET,itagacc_fw2,index);
push_delta_fw2 (`D_TAG_ACC+`CTL_OFFSET,dtagacc_fw2,index);
push_delta_fw2 (`DSFAR+`CTL_OFFSET,dsfar_fw2,index);
//----------------------------------------------------------
// Stage FW2 of delta pipeline - for signals that change FW+2 !!
index = delta_fw2[`NEXT_INDEX];
// Since FPRS for FPops may have been corrupted by o-o-o loads:
// If fprs_fw2 is != fprs_reg & there are loads in the pipeline
// then assume loads have already updated fprs.
// In that case, create our own fprs_reg by using the valids and
// skip_addr and copy of fprs for this op..
if (complete_fw2[`FP_INDEX] && frf_w1_valid_fw2) begin // {
// o-o-o load has changed fprs already - use dummy
if ((fprs_fw2 != FPRS_reg) && (complete_fw1[`LSU_INDEX] |
complete_fw[`LSU_INDEX] | complete_fb[`LSU_INDEX] |
complete_fx5[`LSU_INDEX] )) begin // {
dummy_fprs = read_prev(`FPRS + `CTL_OFFSET);
dummy_fprs = dummy_fprs |
{1'b0, frf_w1_skip_addr4_fw2, ~frf_w1_skip_addr4_fw2};
push_delta_fw2_async (`FPRS + `CTL_OFFSET,dummy_fprs,index);
// o-o-o load has NOT changed fprs already - use it
push_delta_fw2_async (`FPRS + `CTL_OFFSET,FPRS_reg,index);
// Load FPRS for loads/reads as prev|fprs_fb ..
// since loads may only 'set' bits, not clear ...
else if (complete_fw2[`LSU_INDEX]) begin // {
dummy_fprs = read_prev(`FPRS + `CTL_OFFSET);
dummy_fprs = dummy_fprs | fprs_fw1;
push_delta_fw2_async (`FPRS +`CTL_OFFSET,dummy_fprs,index);
// Load FPRS for store ASI or FDIV
// FDIV can update FPRS on w1 or w2,
// but the pipe is stalled behind it so no o-o-o loads.
else if ((complete_fw2[`ASI_INDEX]) ||
(complete_fw2[`FDIV_INDEX])) begin // {
push_delta_fw2_async (`FPRS + `CTL_OFFSET,FPRS_reg,index);
//----------------------------------------------------------
// Store latest values into delta
index = delta_prev[`NEXT_INDEX];
if (in_wmr & ~`SPC3.rst_wmr_protect) begin // {
push_delta_prev_async ( `PC+`CTL_OFFSET,{16'b0,pc_fw2|1},index);
push_delta_prev_async ( `PC+`CTL_OFFSET,{16'b0,pc_fw2},index);
//----------------------------------------------------------
//----------------------------------------------------------
// Compare with current state and capture if different
if (act_value != read_prev(id)) begin // { // Diff vs prev
calc_cwp(CWP_reg,id,win,type); // special case for 1st stage
write_prev(id,act_value);
delta_fx4[next] <= {type,win,id,act_value};
delta_fx4[next] <= 77'hx;
delta_fx4[`NEXT_INDEX] <= next;
if (`PARGS.axis_debug_on) begin
$display("AXIS: T%0d pc=%h id=%0d type=%0h win=%0h value=%h ts=%0d",
mytnum,PC_reg,id,type,win,act_value,$time);
if (`PARGS.axis_debug_on) begin
$display("AXIS: T%0d pc=%h id=%0d type=%0h win=%0h value=%h ts=%0d",
mytnum,PC_reg,id,type,win,act_value,$time);
//----------------------------------------------------------
// Compare with current state and capture if different
if (act_value != read_prev(id)) begin // { // Diff vs prev
calc_cwp(delta_fx4[`CWP_INDEX],id,win,type);
write_prev(id,act_value);
delta_fx5[next] <= {type,win,id,act_value};
delta_fx5[next] <= 77'hx;
delta_fx5[`NEXT_INDEX] <= next;
if (`PARGS.axis_debug_on) begin
$display("AXIS: T%0d pc=%h id=%0d type=%0h win=%0h value=%h ts=%0d",
mytnum,pc_fx4,id,type,win,act_value,$time);
calc_cwp(cwp_fx4,id,win,type);
if (`PARGS.axis_debug_on) begin
$display("AXIS: T%0d pc=%h id=%0d type=%0h win=%0h value=%h ts=%0d",
mytnum,pc_fx4,id,type,win,act_value,$time);
//----------------------------------------------------------
// Compare with current state and capture if different
if (act_value != read_prev(id)) begin // { // Diff vs prev
calc_cwp(delta_fx5[`CWP_INDEX],id,win,type);
write_prev(id,act_value);
delta_fb[next] <= {type,win,id,act_value};
delta_fb[`NEXT_INDEX] <= next;
if (`PARGS.axis_debug_on) begin
$display("AXIS: T%0d pc=%h id=%0d type=%0h win=%0h value=%h ts=%0d",
mytnum,pc_fx5,id,type,win,act_value,$time);
calc_cwp(cwp_fx5,id,win,type);
if (`PARGS.axis_debug_on) begin
$display("AXIS: T%0d pc=%h id=%0d type=%0h win=%0h value=%h ts=%0d",
mytnum,pc_fx5,id,type,win,act_value,$time);
//----------------------------------------------------------
// Compare with current state and capture if different
if (act_value != read_prev(id)) begin // { // Diff vs prev
calc_cwp(delta_fb[`CWP_INDEX],id,win,type);
write_prev(id,act_value);
delta_fw[next] <= {type,win,id,act_value};
delta_fw[`NEXT_INDEX] <= next;
if (`PARGS.axis_debug_on) begin
$display("AXIS: T%0d pc=%h id=%0d type=%0h win=%0h value=%h ts=%0d",
mytnum,pc_fb,id,type,win,act_value,$time);
calc_cwp(cwp_fb[`CWP_INDEX],id,win,type);
if (`PARGS.axis_debug_on) begin
$display("AXIS: T%0d pc=%h id=%0d type=%0h win=%0h value=%h ts=%0d",
mytnum,pc_fb,id,type,win,act_value,$time);
//----------------------------------------------------------
// Compare with current state and capture if different
if (act_value != read_prev(id)) begin // { // Diff vs prev
calc_cwp(delta_fw[`CWP_INDEX],id,win,type);
write_prev(id,act_value);
delta_fw1[next] <= {type,win,id,act_value};
delta_fw1[next] <= 77'hx;
delta_fw1[`NEXT_INDEX] <= next;
if (`PARGS.axis_debug_on) begin
$display("AXIS: T%0d pc=%h id=%0d type=%0h win=%0h value=%h ts=%0d",
mytnum,pc_fw,id,type,win,act_value,$time);
calc_cwp(cwp_fw,id,win,type);
if (`PARGS.axis_debug_on) begin
$display("AXIS: T%0d pc=%h id=%0d type=%0h win=%0h value=%h ts=%0d",
mytnum,pc_fw,id,type,win,act_value,$time);
//----------------------------------------------------------
// Compare with current state and capture if different
if (act_value != read_prev(id)) begin // { // Diff vs prev
calc_cwp(delta_fw1[`CWP_INDEX],id,win,type);
write_prev(id,act_value);
delta_fw2[next] <= {type,win,id,act_value};
delta_fw2[next] <= 77'hx;
delta_fw2[`NEXT_INDEX] <= next;
if (`PARGS.axis_debug_on) begin
$display("AXIS: T%0d pc=%h id=%0d type=%0h win=%0h value=%h ts=%0d",
mytnum,pc_fw1,id,type,win,act_value,$time);
calc_cwp(cwp_fw1,id,win,type);
if (`PARGS.axis_debug_on) begin
$display("AXIS: T%0d pc=%h id=%0d type=%0h win=%0h value=%h ts=%0d",
mytnum,pc_fw1,id,type,win,act_value,$time);
//----------------------------------------------------------
// Compare with current state and capture if different
// This is for late changing registers
// Use blocking assignments.
task push_delta_fw2_async;
if (act_value != read_prev(id)) begin // { // Diff vs prev
calc_cwp(delta_fw2[`CWP_INDEX],id,win,type);
write_prev_async(id,act_value);
delta_fw2[next] = {type,win,id,act_value};
delta_fw2[`NEXT_INDEX] = next;
if (`PARGS.axis_debug_on) begin
$display("AXIS: T%0d pc=%h id=%0d type=%0h win=%0h value=%h ts=%0d",
mytnum,pc_fw1,id,type,win,act_value,$time);
calc_cwp(cwp_fw2,id,win,type);
if (`PARGS.axis_debug_on) begin
$display("AXIS: T%0d pc=%h id=%0d type=%0h win=%0h value=%h ts=%0d",
mytnum,pc_fw1,id,type,win,act_value,$time);
//----------------------------------------------------------
// Compare with current state and capture if different
// Use blocking assignments so that push_simics will work
task push_delta_prev_async;
if (act_value != read_prev(id)) begin // { // Diff vs prev
calc_cwp(delta_prev[`CWP_INDEX],id,win,type);
write_prev_async(id,act_value);
delta_prev[next] = {type,win,id,act_value};
delta_prev[next] = 77'hx;
delta_prev[`NEXT_INDEX] = next;
if (`PARGS.axis_debug_on) begin
$display("AXIS: T%0d pc=%h id=%0d type=%0h win=%0h value=%h ts=%0d",
mytnum,pc_last,id,type,win,act_value,$time);
if (`PARGS.axis_debug_on) begin
calc_cwp(cwp_last,id,win,type);
$display("AXIS: T%0d pc=%h id=%0d type=%0h win=%0h value=%h ts=%0d",
mytnum,pc_last,id,type,win,act_value,$time);
//----------------------------------------------------------
// prev of delta pipeline
// Pipeline previous stage
for (i=0; i<=delta_fw2[`NEXT_INDEX]; i=i+1) begin // {
delta_prev[i] <= delta_fw2[i];
//----------------------------------------------------------
//----------------------------------------------------------
// Sort delta list in register ID order, then push to simics
// Or print deltas if sas check disabled ..
// Order of registers reported to simics must be:
// Global 0-7 aka prev_reg[0:7]
// Window 8-23 aka prev_reg[8:23]
// Floating 0-63 aka prev_reg[200:263]
// Control 32-143 aka prev_reg[32:143]
act_level = delta_prev[`GL_INDEX]; // GL
time_fw2 = delta_prev[`TIME_INDEX]; // Finish time
for (i=`FIRST_INDEX; i<delta_prev[`NEXT_INDEX]; i=i+1) begin // {
{type,win,regnum,value} = delta_prev[i];
if (regnum<=7) begin // {
if (`PARGS.nas_check_on) begin // {
`ACT_STATUS = $queue(`ACT_QUEUE, `PUSH_Q, mytnum, time_fw2, act_type,
act_level, regnum, value);
else if (`PARGS.show_delta_on) begin // {
`NASTOP.print_delta (mytnum,act_type,win,regnum,value);
else if (regnum<=23) begin // { %o0-%l7, %l0-%l7
if (`PARGS.nas_check_on) begin // {
`ACT_STATUS = $queue(`ACT_QUEUE, `PUSH_Q, mytnum, time_fw2, act_type,
else if (`PARGS.show_delta_on) begin // {
`NASTOP.print_delta (mytnum,act_type,win,regnum,value);
else if (regnum<=31) begin // { %i0-%i7
if (`PARGS.nas_check_on) begin // {
`ACT_STATUS = $queue(`ACT_QUEUE, `PUSH_Q, mytnum, time_fw2, act_type,
win, (regnum-16), value);
else if (`PARGS.show_delta_on) begin // {
`NASTOP.print_delta (mytnum,act_type,win,(regnum-16),value);
else if (regnum<=(64+`FP_OFFSET)) begin // {
if (`PARGS.nas_check_on) begin // {
`ACT_STATUS = $queue(`ACT_QUEUE, `PUSH_Q, mytnum, time_fw2, act_type,
(regnum-`FP_OFFSET), value);
else if (`PARGS.show_delta_on) begin // {
`NASTOP.print_delta (mytnum,act_type,win,(regnum-`FP_OFFSET),value);
else if ((regnum>=(32+`CTL_OFFSET))&(regnum<=(143+`CTL_OFFSET))) begin // {
if (`PARGS.nas_check_on) begin // {
`ACT_STATUS = $queue(`ACT_QUEUE, `PUSH_Q, mytnum, time_fw2, act_type,
(regnum-`CTL_OFFSET), value);
else if (`PARGS.show_delta_on) begin // {
`NASTOP.print_delta (mytnum,act_type,win,(regnum-`CTL_OFFSET),value);
`PR_ERROR ("nas", `ERROR, " - T%0d Bench problem. push_simics has bad regnum", mytnum);
value = delta_prev[`OPCODE_INDEX];
if (`PARGS.nas_check_on) begin // {
`ACT_STATUS = $queue(`ACT_QUEUE, `PUSH_Q, mytnum, time_fw2, act_type,
else if (`PARGS.show_delta_on) begin // {
`NASTOP.print_delta (mytnum,act_type,win,regnum,value);
// Push End of Instruction Delimiter
// The value field for this PUSH equals the PC for this instruction.
// so that printing to the logfile works correctly.
// prev_reg[`PC] = current instruction PC
// delta_reg[`PC] = PC at end of current instruction
pc = delta_prev[`PC_INDEX];
if (`PARGS.nas_check_on) begin // {
`ACT_STATUS = $queue(`ACT_QUEUE, `PUSH_Q, mytnum, time_fw2, act_type,
delta_fw2[`CWP_INDEX], `END_INSTR, pc);
else if (`PARGS.show_delta_on) begin // {
`NASTOP.print_delta (mytnum,act_type,delta_fw2[`CWP_INDEX],`END_INSTR,0);
if (! `PARGS.nas_check_on) begin // {
`PR_NORMAL ("nas", `NORMAL, "@%0d T%0d %h (Unchecked..)",
$time, mytnum, {16'b0,pc});
`TOP.last_act_cycle = `TOP.core_cycle_cnt; //$time;
`TOP.th_last_act_cycle[mytnum] = `TOP.last_act_cycle;
if (! `PARGS.nas_check_on) begin // {
`TOP.last_act_cycle = `TOP.core_cycle_cnt; //$time;
`TOP.th_last_act_cycle[mytnum] = `TOP.last_act_cycle;
//----------------------------------------------------------
// Save current window to previous window, then copy new window to current window
// Save current window to Old window
// Copy New window to current window
//----------------------------------------------------------
// Save current global to previous global, then copy new global to current global
// Save current global to Old global
// Copy New global current global
//----------------------------------------------------------
// Return window number and register type based on cwp and regnum as input
else if (id<=23) begin // {
else if (id<=31) begin // {
else if (id<=(64+`FP_OFFSET)) begin // {
//----------------------------------------------------------
// Check for bad signal values
8'b10000000: ; // good value
`PR_ERROR ("nas", `ERROR, " - T%0d More than one instruction retired in a single cycle for this thread.",
$write("\t\t\t\t Instructions - ");
if (complete_fw2[`EXU_INDEX]) $write("EXU op, ");
if (complete_fw2[`FP_INDEX]) $write("FP op, ");
if (complete_fw2[`LSU_INDEX]) $write("LSU op, ");
if (complete_fw2[`IMUL_INDEX]) $write("IMUL op, ");
if (complete_fw2[`IDIV_INDEX]) $write("IDIV op, ");
if (complete_fw2[`FDIV_INDEX]) $write("FDIV op, ");
if (complete_fw2[`TLU_INDEX]) $write("TLU op, ");
if (complete_fw2[`ASI_INDEX]) $write("ASI op, ");
$write(" complete_fw2 = %b \n",complete_fw2);
// This check only works if diags are written properly.
// For example, if a diag writes to one of these registers using wrpr,
// then this check must be disabled using plusarg.
// CANSAVE + CANRESTORE + OTHERWIN = NWINDOWS-2 (per Sparc V9)
if (`PARGS.win_check_on) begin // {
if (complete_fw2 & ((CANSAVE_reg + CANRESTORE_reg + OTHERWIN_reg) != 6)) begin // {
`PR_ERROR ("nas", `ERROR, "ERROR - T%0d Bad Values for window registers.", mytnum);
`PR_ERROR ("nas", `ERROR, "- CANSAVE = %0d CANRESTORE = %0d OTHERWIN = %0d",
CANSAVE_reg, CANRESTORE_reg,OTHERWIN_reg);
//----------------------------------------------------------
//----------------------------------------------------------
reg [`DELTA_WIDTH:0] temp1, temp2;
last = delta_prev[`NEXT_INDEX]-1;
for (i=`FIRST_INDEX; i <= last; i=i+1) begin // {
for (j=`FIRST_INDEX; j < last; j=j+1) begin // {
temp1 = delta_prev[j]; temp2 = delta_prev[j+1];
if (temp1[76:64] > temp2[76:64]) begin // {
delta_prev[j] = temp2; delta_prev [j+1] = temp1;
//----------------------------------------------------------
//----------------------------------------------------------
// Print one entry in delta_* array
input [`DELTA_WIDTH:0] delta_entry;
reg [(20*8)-1:0] type_str;
reg [(20*8)-1:0] regname;
{type,win,id,act_value} = delta_entry;
`NASTOP.get_regname(mytnum,type_str,win,id,regname);
`PR_NORMAL ("nas", `NORMAL, "type=%0s win=%0d RegID=%0d %0s=%h",
type_str,win,id,regname,act_value);
//----------------------------------------------------------
// Write Value to prev_reg using id as index (non-blocking)
8'd0: prev_reg0 <= value;
8'd1: prev_reg1 <= value;
8'd2: prev_reg2 <= value;
8'd3: prev_reg3 <= value;
8'd4: prev_reg4 <= value;
8'd5: prev_reg5 <= value;
8'd6: prev_reg6 <= value;
8'd7: prev_reg7 <= value;
8'd8: prev_reg8 <= value;
8'd9: prev_reg9 <= value;
8'd10: prev_reg10 <= value;
8'd11: prev_reg11 <= value;
8'd12: prev_reg12 <= value;
8'd13: prev_reg13 <= value;
8'd14: prev_reg14 <= value;
8'd15: prev_reg15 <= value;
8'd16: prev_reg16 <= value;
8'd17: prev_reg17 <= value;
8'd18: prev_reg18 <= value;
8'd19: prev_reg19 <= value;
8'd20: prev_reg20 <= value;
8'd21: prev_reg21 <= value;
8'd22: prev_reg22 <= value;
8'd23: prev_reg23 <= value;
8'd24: prev_reg24 <= value;
8'd25: prev_reg25 <= value;
8'd26: prev_reg26 <= value;
8'd27: prev_reg27 <= value;
8'd28: prev_reg28 <= value;
8'd29: prev_reg29 <= value;
8'd30: prev_reg30 <= value;
8'd31: prev_reg31 <= value;
8'd32: prev_reg32 <= value;
8'd33: prev_reg33 <= value;
8'd34: prev_reg34 <= value;
8'd35: prev_reg35 <= value;
8'd36: prev_reg36 <= value;
8'd37: prev_reg37 <= value;
8'd38: prev_reg38 <= value;
8'd39: prev_reg39 <= value;
8'd40: prev_reg40 <= value;
8'd41: prev_reg41 <= value;
8'd42: prev_reg42 <= value;
8'd43: prev_reg43 <= value;
8'd44: prev_reg44 <= value;
8'd45: prev_reg45 <= value;
8'd46: prev_reg46 <= value;
8'd47: prev_reg47 <= value;
8'd48: prev_reg48 <= value;
8'd49: prev_reg49 <= value;
8'd50: prev_reg50 <= value;
8'd51: prev_reg51 <= value;
8'd52: prev_reg52 <= value;
8'd53: prev_reg53 <= value;
8'd54: prev_reg54 <= value;
8'd55: prev_reg55 <= value;
8'd56: prev_reg56 <= value;
8'd57: prev_reg57 <= value;
8'd58: prev_reg58 <= value;
8'd59: prev_reg59 <= value;
8'd60: prev_reg60 <= value;
8'd61: prev_reg61 <= value;
8'd62: prev_reg62 <= value;
8'd63: prev_reg63 <= value;
8'd64: prev_reg64 <= value;
8'd65: prev_reg65 <= value;
8'd66: prev_reg66 <= value;
8'd67: prev_reg67 <= value;
8'd68: prev_reg68 <= value;
8'd69: prev_reg69 <= value;
8'd70: prev_reg70 <= value;
8'd71: prev_reg71 <= value;
8'd72: prev_reg72 <= value;
8'd73: prev_reg73 <= value;
8'd74: prev_reg74 <= value;
8'd75: prev_reg75 <= value;
8'd76: prev_reg76 <= value;
8'd77: prev_reg77 <= value;
8'd78: prev_reg78 <= value;
8'd79: prev_reg79 <= value;
8'd80: prev_reg80 <= value;
8'd81: prev_reg81 <= value;
8'd82: prev_reg82 <= value;
8'd83: prev_reg83 <= value;
8'd84: prev_reg84 <= value;
8'd85: prev_reg85 <= value;
8'd86: prev_reg86 <= value;
8'd87: prev_reg87 <= value;
8'd88: prev_reg88 <= value;
8'd89: prev_reg89 <= value;
8'd90: prev_reg90 <= value;
8'd91: prev_reg91 <= value;
8'd92: prev_reg92 <= value;
8'd93: prev_reg93 <= value;
8'd94: prev_reg94 <= value;
8'd95: prev_reg95 <= value;
8'd96: prev_reg96 <= value;
8'd97: prev_reg97 <= value;
8'd98: prev_reg98 <= value;
8'd99: prev_reg99 <= value;
8'd100: prev_reg100 <= value;
8'd101: prev_reg101 <= value;
8'd102: prev_reg102 <= value;
8'd103: prev_reg103 <= value;
8'd104: prev_reg104 <= value;
8'd105: prev_reg105 <= value;
8'd106: prev_reg106 <= value;
8'd107: prev_reg107 <= value;
8'd108: prev_reg108 <= value;
8'd109: prev_reg109 <= value;
8'd110: prev_reg110 <= value;
8'd111: prev_reg111 <= value;
8'd112: prev_reg112 <= value;
8'd113: prev_reg113 <= value;
8'd114: prev_reg114 <= value;
8'd115: prev_reg115 <= value;
8'd116: prev_reg116 <= value;
8'd117: prev_reg117 <= value;
8'd118: prev_reg118 <= value;
8'd119: prev_reg119 <= value;
8'd120: prev_reg120 <= value;
8'd121: prev_reg121 <= value;
8'd122: prev_reg122 <= value;
8'd123: prev_reg123 <= value;
8'd124: prev_reg124 <= value;
8'd125: prev_reg125 <= value;
8'd126: prev_reg126 <= value;
8'd127: prev_reg127 <= value;
8'd128: prev_reg128 <= value;
8'd129: prev_reg129 <= value;
8'd130: prev_reg130 <= value;
8'd131: prev_reg131 <= value;
8'd132: prev_reg132 <= value;
8'd133: prev_reg133 <= value;
8'd134: prev_reg134 <= value;
8'd135: prev_reg135 <= value;
8'd136: prev_reg136 <= value;
8'd137: prev_reg137 <= value;
8'd138: prev_reg138 <= value;
8'd139: prev_reg139 <= value;
8'd140: prev_reg140 <= value;
8'd141: prev_reg141 <= value;
8'd142: prev_reg142 <= value;
8'd143: prev_reg143 <= value;
8'd144: prev_reg144 <= value;
8'd145: prev_reg145 <= value;
8'd146: prev_reg146 <= value;
8'd147: prev_reg147 <= value;
8'd148: prev_reg148 <= value;
8'd149: prev_reg149 <= value;
8'd150: prev_reg150 <= value;
8'd151: prev_reg151 <= value;
8'd152: prev_reg152 <= value;
8'd153: prev_reg153 <= value;
8'd154: prev_reg154 <= value;
8'd155: prev_reg155 <= value;
8'd156: prev_reg156 <= value;
8'd157: prev_reg157 <= value;
8'd158: prev_reg158 <= value;
8'd159: prev_reg159 <= value;
8'd160: prev_reg160 <= value;
8'd161: prev_reg161 <= value;
8'd162: prev_reg162 <= value;
8'd163: prev_reg163 <= value;
8'd164: prev_reg164 <= value;
8'd165: prev_reg165 <= value;
8'd166: prev_reg166 <= value;
8'd167: prev_reg167 <= value;
8'd168: prev_reg168 <= value;
8'd169: prev_reg169 <= value;
8'd170: prev_reg170 <= value;
8'd171: prev_reg171 <= value;
8'd172: prev_reg172 <= value;
8'd173: prev_reg173 <= value;
8'd174: prev_reg174 <= value;
8'd175: prev_reg175 <= value;
8'd176: prev_reg176 <= value;
8'd177: prev_reg177 <= value;
8'd178: prev_reg178 <= value;
8'd179: prev_reg179 <= value;
8'd180: prev_reg180 <= value;
8'd181: prev_reg181 <= value;
8'd182: prev_reg182 <= value;
8'd183: prev_reg183 <= value;
8'd184: prev_reg184 <= value;
8'd185: prev_reg185 <= value;
8'd186: prev_reg186 <= value;
8'd187: prev_reg187 <= value;
8'd188: prev_reg188 <= value;
8'd189: prev_reg189 <= value;
8'd190: prev_reg190 <= value;
8'd191: prev_reg191 <= value;
8'd192: prev_reg192 <= value;
8'd193: prev_reg193 <= value;
8'd194: prev_reg194 <= value;
8'd195: prev_reg195 <= value;
8'd196: prev_reg196 <= value;
8'd197: prev_reg197 <= value;
8'd198: prev_reg198 <= value;
8'd199: prev_reg199 <= value;
8'd200: prev_reg200 <= value;
8'd201: prev_reg201 <= value;
8'd202: prev_reg202 <= value;
8'd203: prev_reg203 <= value;
8'd204: prev_reg204 <= value;
8'd205: prev_reg205 <= value;
8'd206: prev_reg206 <= value;
8'd207: prev_reg207 <= value;
8'd208: prev_reg208 <= value;
8'd209: prev_reg209 <= value;
8'd210: prev_reg210 <= value;
8'd211: prev_reg211 <= value;
8'd212: prev_reg212 <= value;
8'd213: prev_reg213 <= value;
8'd214: prev_reg214 <= value;
8'd215: prev_reg215 <= value;
8'd216: prev_reg216 <= value;
8'd217: prev_reg217 <= value;
8'd218: prev_reg218 <= value;
8'd219: prev_reg219 <= value;
8'd220: prev_reg220 <= value;
8'd221: prev_reg221 <= value;
8'd222: prev_reg222 <= value;
8'd223: prev_reg223 <= value;
8'd224: prev_reg224 <= value;
8'd225: prev_reg225 <= value;
8'd226: prev_reg226 <= value;
8'd227: prev_reg227 <= value;
8'd228: prev_reg228 <= value;
8'd229: prev_reg229 <= value;
8'd230: prev_reg230 <= value;
8'd231: prev_reg231 <= value;
8'd232: prev_reg232 <= value;
8'd233: prev_reg233 <= value;
8'd234: prev_reg234 <= value;
8'd235: prev_reg235 <= value;
8'd236: prev_reg236 <= value;
8'd237: prev_reg237 <= value;
8'd238: prev_reg238 <= value;
8'd239: prev_reg239 <= value;
8'd240: prev_reg240 <= value;
8'd241: prev_reg241 <= value;
8'd242: prev_reg242 <= value;
8'd243: prev_reg243 <= value;
8'd244: prev_reg244 <= value;
8'd245: prev_reg245 <= value;
8'd246: prev_reg246 <= value;
8'd247: prev_reg247 <= value;
8'd248: prev_reg248 <= value;
8'd249: prev_reg249 <= value;
8'd250: prev_reg250 <= value;
8'd251: prev_reg251 <= value;
8'd252: prev_reg252 <= value;
8'd253: prev_reg253 <= value;
8'd254: prev_reg254 <= value;
8'd255: prev_reg255 <= value;
//----------------------------------------------------------
// Write Value to prev_reg using id as index (blocking)
8'd10: prev_reg10 = value;
8'd11: prev_reg11 = value;
8'd12: prev_reg12 = value;
8'd13: prev_reg13 = value;
8'd14: prev_reg14 = value;
8'd15: prev_reg15 = value;
8'd16: prev_reg16 = value;
8'd17: prev_reg17 = value;
8'd18: prev_reg18 = value;
8'd19: prev_reg19 = value;
8'd20: prev_reg20 = value;
8'd21: prev_reg21 = value;
8'd22: prev_reg22 = value;
8'd23: prev_reg23 = value;
8'd24: prev_reg24 = value;
8'd25: prev_reg25 = value;
8'd26: prev_reg26 = value;
8'd27: prev_reg27 = value;
8'd28: prev_reg28 = value;
8'd29: prev_reg29 = value;
8'd30: prev_reg30 = value;
8'd31: prev_reg31 = value;
8'd32: prev_reg32 = value;
8'd33: prev_reg33 = value;
8'd34: prev_reg34 = value;
8'd35: prev_reg35 = value;
8'd36: prev_reg36 = value;
8'd37: prev_reg37 = value;
8'd38: prev_reg38 = value;
8'd39: prev_reg39 = value;
8'd40: prev_reg40 = value;
8'd41: prev_reg41 = value;
8'd42: prev_reg42 = value;
8'd43: prev_reg43 = value;
8'd44: prev_reg44 = value;
8'd45: prev_reg45 = value;
8'd46: prev_reg46 = value;
8'd47: prev_reg47 = value;
8'd48: prev_reg48 = value;
8'd49: prev_reg49 = value;
8'd50: prev_reg50 = value;
8'd51: prev_reg51 = value;
8'd52: prev_reg52 = value;
8'd53: prev_reg53 = value;
8'd54: prev_reg54 = value;
8'd55: prev_reg55 = value;
8'd56: prev_reg56 = value;
8'd57: prev_reg57 = value;
8'd58: prev_reg58 = value;
8'd59: prev_reg59 = value;
8'd60: prev_reg60 = value;
8'd61: prev_reg61 = value;
8'd62: prev_reg62 = value;
8'd63: prev_reg63 = value;
8'd64: prev_reg64 = value;
8'd65: prev_reg65 = value;
8'd66: prev_reg66 = value;
8'd67: prev_reg67 = value;
8'd68: prev_reg68 = value;
8'd69: prev_reg69 = value;
8'd70: prev_reg70 = value;
8'd71: prev_reg71 = value;
8'd72: prev_reg72 = value;
8'd73: prev_reg73 = value;
8'd74: prev_reg74 = value;
8'd75: prev_reg75 = value;
8'd76: prev_reg76 = value;
8'd77: prev_reg77 = value;
8'd78: prev_reg78 = value;
8'd79: prev_reg79 = value;
8'd80: prev_reg80 = value;
8'd81: prev_reg81 = value;
8'd82: prev_reg82 = value;
8'd83: prev_reg83 = value;
8'd84: prev_reg84 = value;
8'd85: prev_reg85 = value;
8'd86: prev_reg86 = value;
8'd87: prev_reg87 = value;
8'd88: prev_reg88 = value;
8'd89: prev_reg89 = value;
8'd90: prev_reg90 = value;
8'd91: prev_reg91 = value;
8'd92: prev_reg92 = value;
8'd93: prev_reg93 = value;
8'd94: prev_reg94 = value;
8'd95: prev_reg95 = value;
8'd96: prev_reg96 = value;
8'd97: prev_reg97 = value;
8'd98: prev_reg98 = value;
8'd99: prev_reg99 = value;
8'd100: prev_reg100 = value;
8'd101: prev_reg101 = value;
8'd102: prev_reg102 = value;
8'd103: prev_reg103 = value;
8'd104: prev_reg104 = value;
8'd105: prev_reg105 = value;
8'd106: prev_reg106 = value;
8'd107: prev_reg107 = value;
8'd108: prev_reg108 = value;
8'd109: prev_reg109 = value;
8'd110: prev_reg110 = value;
8'd111: prev_reg111 = value;
8'd112: prev_reg112 = value;
8'd113: prev_reg113 = value;
8'd114: prev_reg114 = value;
8'd115: prev_reg115 = value;
8'd116: prev_reg116 = value;
8'd117: prev_reg117 = value;
8'd118: prev_reg118 = value;
8'd119: prev_reg119 = value;
8'd120: prev_reg120 = value;
8'd121: prev_reg121 = value;
8'd122: prev_reg122 = value;
8'd123: prev_reg123 = value;
8'd124: prev_reg124 = value;
8'd125: prev_reg125 = value;
8'd126: prev_reg126 = value;
8'd127: prev_reg127 = value;
8'd128: prev_reg128 = value;
8'd129: prev_reg129 = value;
8'd130: prev_reg130 = value;
8'd131: prev_reg131 = value;
8'd132: prev_reg132 = value;
8'd133: prev_reg133 = value;
8'd134: prev_reg134 = value;
8'd135: prev_reg135 = value;
8'd136: prev_reg136 = value;
8'd137: prev_reg137 = value;
8'd138: prev_reg138 = value;
8'd139: prev_reg139 = value;
8'd140: prev_reg140 = value;
8'd141: prev_reg141 = value;
8'd142: prev_reg142 = value;
8'd143: prev_reg143 = value;
8'd144: prev_reg144 = value;
8'd145: prev_reg145 = value;
8'd146: prev_reg146 = value;
8'd147: prev_reg147 = value;
8'd148: prev_reg148 = value;
8'd149: prev_reg149 = value;
8'd150: prev_reg150 = value;
8'd151: prev_reg151 = value;
8'd152: prev_reg152 = value;
8'd153: prev_reg153 = value;
8'd154: prev_reg154 = value;
8'd155: prev_reg155 = value;
8'd156: prev_reg156 = value;
8'd157: prev_reg157 = value;
8'd158: prev_reg158 = value;
8'd159: prev_reg159 = value;
8'd160: prev_reg160 = value;
8'd161: prev_reg161 = value;
8'd162: prev_reg162 = value;
8'd163: prev_reg163 = value;
8'd164: prev_reg164 = value;
8'd165: prev_reg165 = value;
8'd166: prev_reg166 = value;
8'd167: prev_reg167 = value;
8'd168: prev_reg168 = value;
8'd169: prev_reg169 = value;
8'd170: prev_reg170 = value;
8'd171: prev_reg171 = value;
8'd172: prev_reg172 = value;
8'd173: prev_reg173 = value;
8'd174: prev_reg174 = value;
8'd175: prev_reg175 = value;
8'd176: prev_reg176 = value;
8'd177: prev_reg177 = value;
8'd178: prev_reg178 = value;
8'd179: prev_reg179 = value;
8'd180: prev_reg180 = value;
8'd181: prev_reg181 = value;
8'd182: prev_reg182 = value;
8'd183: prev_reg183 = value;
8'd184: prev_reg184 = value;
8'd185: prev_reg185 = value;
8'd186: prev_reg186 = value;
8'd187: prev_reg187 = value;
8'd188: prev_reg188 = value;
8'd189: prev_reg189 = value;
8'd190: prev_reg190 = value;
8'd191: prev_reg191 = value;
8'd192: prev_reg192 = value;
8'd193: prev_reg193 = value;
8'd194: prev_reg194 = value;
8'd195: prev_reg195 = value;
8'd196: prev_reg196 = value;
8'd197: prev_reg197 = value;
8'd198: prev_reg198 = value;
8'd199: prev_reg199 = value;
8'd200: prev_reg200 = value;
8'd201: prev_reg201 = value;
8'd202: prev_reg202 = value;
8'd203: prev_reg203 = value;
8'd204: prev_reg204 = value;
8'd205: prev_reg205 = value;
8'd206: prev_reg206 = value;
8'd207: prev_reg207 = value;
8'd208: prev_reg208 = value;
8'd209: prev_reg209 = value;
8'd210: prev_reg210 = value;
8'd211: prev_reg211 = value;
8'd212: prev_reg212 = value;
8'd213: prev_reg213 = value;
8'd214: prev_reg214 = value;
8'd215: prev_reg215 = value;
8'd216: prev_reg216 = value;
8'd217: prev_reg217 = value;
8'd218: prev_reg218 = value;
8'd219: prev_reg219 = value;
8'd220: prev_reg220 = value;
8'd221: prev_reg221 = value;
8'd222: prev_reg222 = value;
8'd223: prev_reg223 = value;
8'd224: prev_reg224 = value;
8'd225: prev_reg225 = value;
8'd226: prev_reg226 = value;
8'd227: prev_reg227 = value;
8'd228: prev_reg228 = value;
8'd229: prev_reg229 = value;
8'd230: prev_reg230 = value;
8'd231: prev_reg231 = value;
8'd232: prev_reg232 = value;
8'd233: prev_reg233 = value;
8'd234: prev_reg234 = value;
8'd235: prev_reg235 = value;
8'd236: prev_reg236 = value;
8'd237: prev_reg237 = value;
8'd238: prev_reg238 = value;
8'd239: prev_reg239 = value;
8'd240: prev_reg240 = value;
8'd241: prev_reg241 = value;
8'd242: prev_reg242 = value;
8'd243: prev_reg243 = value;
8'd244: prev_reg244 = value;
8'd245: prev_reg245 = value;
8'd246: prev_reg246 = value;
8'd247: prev_reg247 = value;
8'd248: prev_reg248 = value;
8'd249: prev_reg249 = value;
8'd250: prev_reg250 = value;
8'd251: prev_reg251 = value;
8'd252: prev_reg252 = value;
8'd253: prev_reg253 = value;
8'd254: prev_reg254 = value;
8'd255: prev_reg255 = value;
//----------------------------------------------------------
// Read value frpm prev_reg using id as index
function [63:0] read_prev;
8'd0: read_prev = prev_reg0;
8'd1: read_prev = prev_reg1;
8'd2: read_prev = prev_reg2;
8'd3: read_prev = prev_reg3;
8'd4: read_prev = prev_reg4;
8'd5: read_prev = prev_reg5;
8'd6: read_prev = prev_reg6;
8'd7: read_prev = prev_reg7;
8'd8: read_prev = prev_reg8;
8'd9: read_prev = prev_reg9;
8'd10: read_prev = prev_reg10;
8'd11: read_prev = prev_reg11;
8'd12: read_prev = prev_reg12;
8'd13: read_prev = prev_reg13;
8'd14: read_prev = prev_reg14;
8'd15: read_prev = prev_reg15;
8'd16: read_prev = prev_reg16;
8'd17: read_prev = prev_reg17;
8'd18: read_prev = prev_reg18;
8'd19: read_prev = prev_reg19;
8'd20: read_prev = prev_reg20;
8'd21: read_prev = prev_reg21;
8'd22: read_prev = prev_reg22;
8'd23: read_prev = prev_reg23;
8'd24: read_prev = prev_reg24;
8'd25: read_prev = prev_reg25;
8'd26: read_prev = prev_reg26;
8'd27: read_prev = prev_reg27;
8'd28: read_prev = prev_reg28;
8'd29: read_prev = prev_reg29;
8'd30: read_prev = prev_reg30;
8'd31: read_prev = prev_reg31;
8'd32: read_prev = prev_reg32;
8'd33: read_prev = prev_reg33;
8'd34: read_prev = prev_reg34;
8'd35: read_prev = prev_reg35;
8'd36: read_prev = prev_reg36;
8'd37: read_prev = prev_reg37;
8'd38: read_prev = prev_reg38;
8'd39: read_prev = prev_reg39;
8'd40: read_prev = prev_reg40;
8'd41: read_prev = prev_reg41;
8'd42: read_prev = prev_reg42;
8'd43: read_prev = prev_reg43;
8'd44: read_prev = prev_reg44;
8'd45: read_prev = prev_reg45;
8'd46: read_prev = prev_reg46;
8'd47: read_prev = prev_reg47;
8'd48: read_prev = prev_reg48;
8'd49: read_prev = prev_reg49;
8'd50: read_prev = prev_reg50;
8'd51: read_prev = prev_reg51;
8'd52: read_prev = prev_reg52;
8'd53: read_prev = prev_reg53;
8'd54: read_prev = prev_reg54;
8'd55: read_prev = prev_reg55;
8'd56: read_prev = prev_reg56;
8'd57: read_prev = prev_reg57;
8'd58: read_prev = prev_reg58;
8'd59: read_prev = prev_reg59;
8'd60: read_prev = prev_reg60;
8'd61: read_prev = prev_reg61;
8'd62: read_prev = prev_reg62;
8'd63: read_prev = prev_reg63;
8'd64: read_prev = prev_reg64;
8'd65: read_prev = prev_reg65;
8'd66: read_prev = prev_reg66;
8'd67: read_prev = prev_reg67;
8'd68: read_prev = prev_reg68;
8'd69: read_prev = prev_reg69;
8'd70: read_prev = prev_reg70;
8'd71: read_prev = prev_reg71;
8'd72: read_prev = prev_reg72;
8'd73: read_prev = prev_reg73;
8'd74: read_prev = prev_reg74;
8'd75: read_prev = prev_reg75;
8'd76: read_prev = prev_reg76;
8'd77: read_prev = prev_reg77;
8'd78: read_prev = prev_reg78;
8'd79: read_prev = prev_reg79;
8'd80: read_prev = prev_reg80;
8'd81: read_prev = prev_reg81;
8'd82: read_prev = prev_reg82;
8'd83: read_prev = prev_reg83;
8'd84: read_prev = prev_reg84;
8'd85: read_prev = prev_reg85;
8'd86: read_prev = prev_reg86;
8'd87: read_prev = prev_reg87;
8'd88: read_prev = prev_reg88;
8'd89: read_prev = prev_reg89;
8'd90: read_prev = prev_reg90;
8'd91: read_prev = prev_reg91;
8'd92: read_prev = prev_reg92;
8'd93: read_prev = prev_reg93;
8'd94: read_prev = prev_reg94;
8'd95: read_prev = prev_reg95;
8'd96: read_prev = prev_reg96;
8'd97: read_prev = prev_reg97;
8'd98: read_prev = prev_reg98;
8'd99: read_prev = prev_reg99;
8'd100: read_prev = prev_reg100;
8'd101: read_prev = prev_reg101;
8'd102: read_prev = prev_reg102;
8'd103: read_prev = prev_reg103;
8'd104: read_prev = prev_reg104;
8'd105: read_prev = prev_reg105;
8'd106: read_prev = prev_reg106;
8'd107: read_prev = prev_reg107;
8'd108: read_prev = prev_reg108;
8'd109: read_prev = prev_reg109;
8'd110: read_prev = prev_reg110;
8'd111: read_prev = prev_reg111;
8'd112: read_prev = prev_reg112;
8'd113: read_prev = prev_reg113;
8'd114: read_prev = prev_reg114;
8'd115: read_prev = prev_reg115;
8'd116: read_prev = prev_reg116;
8'd117: read_prev = prev_reg117;
8'd118: read_prev = prev_reg118;
8'd119: read_prev = prev_reg119;
8'd120: read_prev = prev_reg120;
8'd121: read_prev = prev_reg121;
8'd122: read_prev = prev_reg122;
8'd123: read_prev = prev_reg123;
8'd124: read_prev = prev_reg124;
8'd125: read_prev = prev_reg125;
8'd126: read_prev = prev_reg126;
8'd127: read_prev = prev_reg127;
8'd128: read_prev = prev_reg128;
8'd129: read_prev = prev_reg129;
8'd130: read_prev = prev_reg130;
8'd131: read_prev = prev_reg131;
8'd132: read_prev = prev_reg132;
8'd133: read_prev = prev_reg133;
8'd134: read_prev = prev_reg134;
8'd135: read_prev = prev_reg135;
8'd136: read_prev = prev_reg136;
8'd137: read_prev = prev_reg137;
8'd138: read_prev = prev_reg138;
8'd139: read_prev = prev_reg139;
8'd140: read_prev = prev_reg140;
8'd141: read_prev = prev_reg141;
8'd142: read_prev = prev_reg142;
8'd143: read_prev = prev_reg143;
8'd144: read_prev = prev_reg144;
8'd145: read_prev = prev_reg145;
8'd146: read_prev = prev_reg146;
8'd147: read_prev = prev_reg147;
8'd148: read_prev = prev_reg148;
8'd149: read_prev = prev_reg149;
8'd150: read_prev = prev_reg150;
8'd151: read_prev = prev_reg151;
8'd152: read_prev = prev_reg152;
8'd153: read_prev = prev_reg153;
8'd154: read_prev = prev_reg154;
8'd155: read_prev = prev_reg155;
8'd156: read_prev = prev_reg156;
8'd157: read_prev = prev_reg157;
8'd158: read_prev = prev_reg158;
8'd159: read_prev = prev_reg159;
8'd160: read_prev = prev_reg160;
8'd161: read_prev = prev_reg161;
8'd162: read_prev = prev_reg162;
8'd163: read_prev = prev_reg163;
8'd164: read_prev = prev_reg164;
8'd165: read_prev = prev_reg165;
8'd166: read_prev = prev_reg166;
8'd167: read_prev = prev_reg167;
8'd168: read_prev = prev_reg168;
8'd169: read_prev = prev_reg169;
8'd170: read_prev = prev_reg170;
8'd171: read_prev = prev_reg171;
8'd172: read_prev = prev_reg172;
8'd173: read_prev = prev_reg173;
8'd174: read_prev = prev_reg174;
8'd175: read_prev = prev_reg175;
8'd176: read_prev = prev_reg176;
8'd177: read_prev = prev_reg177;
8'd178: read_prev = prev_reg178;
8'd179: read_prev = prev_reg179;
8'd180: read_prev = prev_reg180;
8'd181: read_prev = prev_reg181;
8'd182: read_prev = prev_reg182;
8'd183: read_prev = prev_reg183;
8'd184: read_prev = prev_reg184;
8'd185: read_prev = prev_reg185;
8'd186: read_prev = prev_reg186;
8'd187: read_prev = prev_reg187;
8'd188: read_prev = prev_reg188;
8'd189: read_prev = prev_reg189;
8'd190: read_prev = prev_reg190;
8'd191: read_prev = prev_reg191;
8'd192: read_prev = prev_reg192;
8'd193: read_prev = prev_reg193;
8'd194: read_prev = prev_reg194;
8'd195: read_prev = prev_reg195;
8'd196: read_prev = prev_reg196;
8'd197: read_prev = prev_reg197;
8'd198: read_prev = prev_reg198;
8'd199: read_prev = prev_reg199;
8'd200: read_prev = prev_reg200;
8'd201: read_prev = prev_reg201;
8'd202: read_prev = prev_reg202;
8'd203: read_prev = prev_reg203;
8'd204: read_prev = prev_reg204;
8'd205: read_prev = prev_reg205;
8'd206: read_prev = prev_reg206;
8'd207: read_prev = prev_reg207;
8'd208: read_prev = prev_reg208;
8'd209: read_prev = prev_reg209;
8'd210: read_prev = prev_reg210;
8'd211: read_prev = prev_reg211;
8'd212: read_prev = prev_reg212;
8'd213: read_prev = prev_reg213;
8'd214: read_prev = prev_reg214;
8'd215: read_prev = prev_reg215;
8'd216: read_prev = prev_reg216;
8'd217: read_prev = prev_reg217;
8'd218: read_prev = prev_reg218;
8'd219: read_prev = prev_reg219;
8'd220: read_prev = prev_reg220;
8'd221: read_prev = prev_reg221;
8'd222: read_prev = prev_reg222;
8'd223: read_prev = prev_reg223;
8'd224: read_prev = prev_reg224;
8'd225: read_prev = prev_reg225;
8'd226: read_prev = prev_reg226;
8'd227: read_prev = prev_reg227;
8'd228: read_prev = prev_reg228;
8'd229: read_prev = prev_reg229;
8'd230: read_prev = prev_reg230;
8'd231: read_prev = prev_reg231;
8'd232: read_prev = prev_reg232;
8'd233: read_prev = prev_reg233;
8'd234: read_prev = prev_reg234;
8'd235: read_prev = prev_reg235;
8'd236: read_prev = prev_reg236;
8'd237: read_prev = prev_reg237;
8'd238: read_prev = prev_reg238;
8'd239: read_prev = prev_reg239;
8'd240: read_prev = prev_reg240;
8'd241: read_prev = prev_reg241;
8'd242: read_prev = prev_reg242;
8'd243: read_prev = prev_reg243;
8'd244: read_prev = prev_reg244;
8'd245: read_prev = prev_reg245;
8'd246: read_prev = prev_reg246;
8'd247: read_prev = prev_reg247;
8'd248: read_prev = prev_reg248;
8'd249: read_prev = prev_reg249;
8'd250: read_prev = prev_reg250;
8'd251: read_prev = prev_reg251;
8'd252: read_prev = prev_reg252;
8'd253: read_prev = prev_reg253;
8'd254: read_prev = prev_reg254;
8'd255: read_prev = prev_reg255;
//----------------------------------------------------------
remap[4] = rd[4] ^ (rd[3] & oddwin);
//----------------------------------------------------------
// Initialize nas_pipe registers
initial begin : INIT_BLOCK
nas_pipe_enable = 1'b1; // Nas_pipe always enables itself
good_trap_detected = 1'b0;
@ (posedge `BENCH_SPC3_GCLK);
`TOP.th_last_act_cycle[mytnum] = 0;
`PR_INFO ("nas", `INFO, "T%0d Init shadow registers.",mytnum);
// POR for control registers
write_prev(`FPRS +`CTL_OFFSET,3'h4);
write_prev(`CLEANWIN +`CTL_OFFSET,3'h7);
write_prev(`CANSAVE +`CTL_OFFSET,3'h6);
write_prev(`FPRS+`CTL_OFFSET,3'h4);
// POR for PSTATE = 0x14 (PEF, PRIV = 1)
write_prev(`PSTATE + `CTL_OFFSET,'h14);
// POR for HPSTATE = 0x4034 (RED, HPRIV = 1)
write_prev(`HPSTATE + `CTL_OFFSET,'h24);
// POR for TL = = 0x6 [MAXTL]
write_prev(`TL + `CTL_OFFSET,'h6);
write_prev(`TT6 + `CTL_OFFSET,'h1);
// POR for GL = MAXGL = 3
write_prev(`GL + `CTL_OFFSET,`POR_GL);
// POR for VER = {003e, 0024, 01, 0036, 07}
write_prev(`VER + `CTL_OFFSET,{32'h003e0024,VER_reg[31:24],24'h030607});
// POR for *_cmpr registers is INT_DIS = 1
write_prev(`TICK_CMPR + `CTL_OFFSET,64'h8000000000000000);
write_prev(`STICK_CMPR + `CTL_OFFSET,64'h8000000000000000);
write_prev(`HSTICK_CMPR + `CTL_OFFSET,64'h8000000000000000);
// Need to define so that 1st instruction will print correctly
write_prev(`PC+`CTL_OFFSET,`POR_PC);
delta_prev[`PC_INDEX] = `BAD_PC;
irf_offset = (mytid%4)*32;
//----------------------------------------------------------
// For WMR, we will set to 0x0, so that initial deltas
// WMR for PSTATE = 0x14 (PEF, PRIV = 1)
// write_prev(`PSTATE + `CTL_OFFSET,'h00);
// WMR for HPSTATE = 0x4034 (RED, HPRIV = 1)
// write_prev(`HPSTATE + `CTL_OFFSET,'h00);
// WMR for TL = = 0x6 [MAXTL]
// write_prev(`TL + `CTL_OFFSET,'h0);
// write_prev(`TT6 + `CTL_OFFSET,'h1);
// WMR for GL = MAXGL = 3
// write_prev(`GL + `CTL_OFFSET,0);
//----------------------------------------------------------
// For POR, we will set to 0x0, so that initial deltas
// and prev state are all consistent with DUT. No values
`PR_ALWAYS ("arg", `ALWAYS,"T%0d Resetting Nas Pipe states for POR ..",mytnum);
delta_fx4[`NEXT_INDEX] <= `FIRST_INDEX;
delta_fx4[`FIRST_INDEX] <= 77'hx;
delta_fx5[`NEXT_INDEX] <= `FIRST_INDEX;
delta_fb[`NEXT_INDEX] <= `FIRST_INDEX;
delta_fw[`NEXT_INDEX] <= `FIRST_INDEX;
delta_fw1[`NEXT_INDEX] <= `FIRST_INDEX;
delta_fw2[`NEXT_INDEX] <= `FIRST_INDEX;
`PR_INFO ("nas", `INFO, "T%0d Init shadow registers.",mytnum);
// POR for control registers
write_prev(`FPRS +`CTL_OFFSET,3'h4);
write_prev(`CLEANWIN +`CTL_OFFSET,3'h7);
write_prev(`CANSAVE +`CTL_OFFSET,3'h6);
write_prev(`FPRS+`CTL_OFFSET,3'h4);
// POR for PSTATE = 0x14 (PEF, PRIV = 1)
write_prev(`PSTATE + `CTL_OFFSET,'h14);
// POR for HPSTATE = 0x4034 (RED, HPRIV = 1)
write_prev(`HPSTATE + `CTL_OFFSET,'h24);
// POR for TL = = 0x6 [MAXTL]
write_prev(`TL + `CTL_OFFSET,'h6);
write_prev(`TT6 + `CTL_OFFSET,'h1);
// POR for GL = MAXGL = 3
write_prev(`GL + `CTL_OFFSET,`POR_GL);
// POR for VER = {003e, 0024, 01, 0036, 07}
write_prev(`VER + `CTL_OFFSET,64'h003e002410030607);
// POR for *_cmpr registers is INT_DIS = 1
write_prev(`TICK_CMPR + `CTL_OFFSET,64'h8000000000000000);
write_prev(`STICK_CMPR + `CTL_OFFSET,64'h8000000000000000);
write_prev(`HSTICK_CMPR + `CTL_OFFSET,64'h8000000000000000);
// Need to define so that 1st instruction will print correctly
write_prev(`PC+`CTL_OFFSET,`POR_PC);
//----------------------------------------------------------
//----------------------------------------------------------
// Watch for Good/Bad trap
wire [5:0] mytnum = (mycid*8)+mytid;
// Delimiter changes whether flat or hierarchical netlist
wire myclk = tb_top.cpu.spc3.gclk;
wire dec_inst_valid_m = mytg ? tb_top.cpu.spc3.dec_inst_valid_m[1] : tb_top.cpu.spc3.dec_inst_valid_m[0];
wire [1:0] dec_tid_m = mytg ? tb_top.cpu.spc3.dec_tid1_m : tb_top.cpu.spc3.dec_tid0_m;
wire dec_flush_b = mytg ? tb_top.cpu.spc3.dec_flush_b[1] : tb_top.cpu.spc3.dec_flush_b[0];
wire tlu_flush_ifu = tb_top.cpu.spc3.tlu_flush_ifu[mytid];
wire [47:0] pc_d = mytg ? {tb_top.cpu.spc3.tlu_pc_1_d[47:2],2'b0} : {tb_top.cpu.spc3.tlu_pc_0_d[47:2],2'b0};
wire [31:0] op_d = mytg ? tb_top.cpu.spc3.dec_inst1_d[31:0] : tb_top.cpu.spc3.dec_inst0_d[31:0];
wire myclk = tb_top.cpu.spc3.gclk;
wire dec_inst_valid_m = mytg ? tb_top.cpu.spc3.dec_inst_valid_m[1] : tb_top.cpu.spc3.dec_inst_valid_m[0];
wire [1:0] dec_tid_m = mytg ? tb_top.cpu.spc3.dec_tid1_m : tb_top.cpu.spc3.dec_tid0_m;
wire dec_flush_b = mytg ? tb_top.cpu.spc3.dec_flush_b[1] : tb_top.cpu.spc3.dec_flush_b[0];
wire tlu_flush_ifu = tb_top.cpu.spc3.tlu_flush_ifu[mytid];
wire [47:0] pc_d = mytg ? {tb_top.cpu.spc3.tlu_pc_1_d[47:2],2'b0} : {tb_top.cpu.spc3.tlu_pc_0_d[47:2],2'b0};
wire [31:0] op_d = mytg ? tb_top.cpu.spc3.dec_inst1_d[31:0] : tb_top.cpu.spc3.dec_inst0_d[31:0];
wire inst_valid_b = dec_inst_valid_b && (dec_tid_b==mytid[1:0]) && !(dec_flush_b || tlu_flush_ifu);
always @ (posedge myclk) begin // {
dec_inst_valid_b <= dec_inst_valid_m;
inst_valid_w <= inst_valid_b;
inst_valid_fx4 <= inst_valid_w;
inst_valid_fx5 <= inst_valid_fx4;
inst_valid_fb <= inst_valid_fx5;
inst_valid_fw <= inst_valid_fb;
inst_valid_fw1 <= inst_valid_fw;
inst_valid_fw2 <= inst_valid_fw1;
if (`PARGS.th_check_enable[mytnum] && nas_pipe_enable) begin // {
if (inst_valid_fw2) begin // {
// Print PC/opcode for debugging
`PR_NORMAL ("nas", `NORMAL, "@%0d #%0d T%0d %h [%h]", $time, inst_count, mytnum, pc_fw2, op_fw2);
inst_count = inst_count + 1;
// End detection for GateSim runs
for (junk=0;junk<`PARGS.bad_trap_count;junk=junk+1) begin // {
if (({16'b0,pc_fw2}&`PC_MASK)===(`PARGS.bad_trap_addr[junk]&`PC_MASK)) begin // {
`PR_ERROR ("nas",`ERROR, "T%0d reached Bad Trap [GATESIM]", mytnum);
for (junk=0;junk<`PARGS.good_trap_count;junk=junk+1) begin // {
if (({16'b0,pc_fw2}&`PC_MASK)===(`PARGS.good_trap_addr[junk]&`PC_MASK)) begin // {
`TOP.finished_tids[mytnum] = 1'b1;
`PARGS.th_check_enable[mytnum] = 1'b0;
`PR_NORMAL ("nas", `NORMAL, "T%0d reached Good Trap. Disabling checking for thread %0d [GATESIM]", mytnum,mytnum);
//----------------------------------------------------------
//----------------------------------------------------------
//----------------------------------------------------------
input [71:0] TICK_CMPR_reg;
input [71:0] STICK_CMPR_reg;
input [71:0] HSTICK_CMPR_reg;
input [2:0] CANRESTORE_reg;
input [2:0] OTHERWIN_reg;
input [2:0] CLEANWIN_reg;
input [16:0] SOFTINT_reg;
input [16:0] rd_SOFTINT_reg;
input [63:0] INTR_RECEIVE_reg;
input [12:0] HPSTATE_reg;
input [63:0] CTXT_PRIM_0_reg;
input [63:0] CTXT_SEC_0_reg;
input [63:0] CTXT_PRIM_1_reg;
input [63:0] CTXT_SEC_1_reg;
input [63:0] LSU_CONTROL_reg;
input [63:0] I_TAG_ACC_reg;
input [63:0] D_TAG_ACC_reg;
input [63:0] WATCHPOINT_ADDR_reg;
input [151:0] Trap_Entry_1;
input [151:0] Trap_Entry_2;
input [151:0] Trap_Entry_3;
input [151:0] Trap_Entry_4;
input [151:0] Trap_Entry_5;
input [151:0] Trap_Entry_6;
input [1:0] frf_w2_valid;
input [1:0] frf_w1_valid;
input asi_valid; // ASI/ASR/PR writes done ..
input asi_in_progress; // ASI/ASR/PR in progess
//----------------------------------------------------------
//----------------------------------------------------------
//----------------------------------------------------------
// delta_* = {type(2bits),win(3bits),regnum(8bits),value(64bits)}
reg [`DELTA_WIDTH:0] delta_fx4 [0:(`MAX_INDEX)];
reg [`DELTA_WIDTH:0] delta_fx5 [0:(`MAX_INDEX)];
reg [`DELTA_WIDTH:0] delta_fb [0:(`MAX_INDEX)];
reg [`DELTA_WIDTH:0] delta_fw [0:(`MAX_INDEX)];
reg [`DELTA_WIDTH:0] delta_fw1 [0:(`MAX_INDEX)];
reg [`DELTA_WIDTH:0] delta_fw2 [0:(`MAX_INDEX)];
reg [`DELTA_WIDTH:0] delta_prev [0:(`MAX_INDEX)];
// need to change in several places in this file
reg [63:0] prev_reg0; // includes G,W,C,F registers
reg [63:0] prev_reg1; // includes G,W,C,F registers
reg [63:0] prev_reg2; // includes G,W,C,F registers
reg [63:0] prev_reg3; // includes G,W,C,F registers
reg [63:0] prev_reg4; // includes G,W,C,F registers
reg [63:0] prev_reg5; // includes G,W,C,F registers
reg [63:0] prev_reg6; // includes G,W,C,F registers
reg [63:0] prev_reg7; // includes G,W,C,F registers
reg [63:0] prev_reg8; // includes G,W,C,F registers
reg [63:0] prev_reg9; // includes G,W,C,F registers
reg [63:0] prev_reg10; // includes G,W,C,F registers
reg [63:0] prev_reg11; // includes G,W,C,F registers
reg [63:0] prev_reg12; // includes G,W,C,F registers
reg [63:0] prev_reg13; // includes G,W,C,F registers
reg [63:0] prev_reg14; // includes G,W,C,F registers
reg [63:0] prev_reg15; // includes G,W,C,F registers
reg [63:0] prev_reg16; // includes G,W,C,F registers
reg [63:0] prev_reg17; // includes G,W,C,F registers
reg [63:0] prev_reg18; // includes G,W,C,F registers
reg [63:0] prev_reg19; // includes G,W,C,F registers
reg [63:0] prev_reg20; // includes G,W,C,F registers
reg [63:0] prev_reg21; // includes G,W,C,F registers
reg [63:0] prev_reg22; // includes G,W,C,F registers
reg [63:0] prev_reg23; // includes G,W,C,F registers
reg [63:0] prev_reg24; // includes G,W,C,F registers
reg [63:0] prev_reg25; // includes G,W,C,F registers
reg [63:0] prev_reg26; // includes G,W,C,F registers
reg [63:0] prev_reg27; // includes G,W,C,F registers
reg [63:0] prev_reg28; // includes G,W,C,F registers
reg [63:0] prev_reg29; // includes G,W,C,F registers
reg [63:0] prev_reg30; // includes G,W,C,F registers
reg [63:0] prev_reg31; // includes G,W,C,F registers
reg [63:0] prev_reg32; // includes G,W,C,F registers
reg [63:0] prev_reg33; // includes G,W,C,F registers
reg [63:0] prev_reg34; // includes G,W,C,F registers
reg [63:0] prev_reg35; // includes G,W,C,F registers
reg [63:0] prev_reg36; // includes G,W,C,F registers
reg [63:0] prev_reg37; // includes G,W,C,F registers
reg [63:0] prev_reg38; // includes G,W,C,F registers
reg [63:0] prev_reg39; // includes G,W,C,F registers
reg [63:0] prev_reg40; // includes G,W,C,F registers
reg [63:0] prev_reg41; // includes G,W,C,F registers
reg [63:0] prev_reg42; // includes G,W,C,F registers
reg [63:0] prev_reg43; // includes G,W,C,F registers
reg [63:0] prev_reg44; // includes G,W,C,F registers
reg [63:0] prev_reg45; // includes G,W,C,F registers
reg [63:0] prev_reg46; // includes G,W,C,F registers
reg [63:0] prev_reg47; // includes G,W,C,F registers
reg [63:0] prev_reg48; // includes G,W,C,F registers
reg [63:0] prev_reg49; // includes G,W,C,F registers
reg [63:0] prev_reg50; // includes G,W,C,F registers
reg [63:0] prev_reg51; // includes G,W,C,F registers
reg [63:0] prev_reg52; // includes G,W,C,F registers
reg [63:0] prev_reg53; // includes G,W,C,F registers
reg [63:0] prev_reg54; // includes G,W,C,F registers
reg [63:0] prev_reg55; // includes G,W,C,F registers
reg [63:0] prev_reg56; // includes G,W,C,F registers
reg [63:0] prev_reg57; // includes G,W,C,F registers
reg [63:0] prev_reg58; // includes G,W,C,F registers
reg [63:0] prev_reg59; // includes G,W,C,F registers
reg [63:0] prev_reg60; // includes G,W,C,F registers
reg [63:0] prev_reg61; // includes G,W,C,F registers
reg [63:0] prev_reg62; // includes G,W,C,F registers
reg [63:0] prev_reg63; // includes G,W,C,F registers
reg [63:0] prev_reg64; // includes G,W,C,F registers
reg [63:0] prev_reg65; // includes G,W,C,F registers
reg [63:0] prev_reg66; // includes G,W,C,F registers
reg [63:0] prev_reg67; // includes G,W,C,F registers
reg [63:0] prev_reg68; // includes G,W,C,F registers
reg [63:0] prev_reg69; // includes G,W,C,F registers
reg [63:0] prev_reg70; // includes G,W,C,F registers
reg [63:0] prev_reg71; // includes G,W,C,F registers
reg [63:0] prev_reg72; // includes G,W,C,F registers
reg [63:0] prev_reg73; // includes G,W,C,F registers
reg [63:0] prev_reg74; // includes G,W,C,F registers
reg [63:0] prev_reg75; // includes G,W,C,F registers
reg [63:0] prev_reg76; // includes G,W,C,F registers
reg [63:0] prev_reg77; // includes G,W,C,F registers
reg [63:0] prev_reg78; // includes G,W,C,F registers
reg [63:0] prev_reg79; // includes G,W,C,F registers
reg [63:0] prev_reg80; // includes G,W,C,F registers
reg [63:0] prev_reg81; // includes G,W,C,F registers
reg [63:0] prev_reg82; // includes G,W,C,F registers
reg [63:0] prev_reg83; // includes G,W,C,F registers
reg [63:0] prev_reg84; // includes G,W,C,F registers
reg [63:0] prev_reg85; // includes G,W,C,F registers
reg [63:0] prev_reg86; // includes G,W,C,F registers
reg [63:0] prev_reg87; // includes G,W,C,F registers
reg [63:0] prev_reg88; // includes G,W,C,F registers
reg [63:0] prev_reg89; // includes G,W,C,F registers
reg [63:0] prev_reg90; // includes G,W,C,F registers
reg [63:0] prev_reg91; // includes G,W,C,F registers
reg [63:0] prev_reg92; // includes G,W,C,F registers
reg [63:0] prev_reg93; // includes G,W,C,F registers
reg [63:0] prev_reg94; // includes G,W,C,F registers
reg [63:0] prev_reg95; // includes G,W,C,F registers
reg [63:0] prev_reg96; // includes G,W,C,F registers
reg [63:0] prev_reg97; // includes G,W,C,F registers
reg [63:0] prev_reg98; // includes G,W,C,F registers
reg [63:0] prev_reg99; // includes G,W,C,F registers
reg [63:0] prev_reg100; // includes G,W,C,F registers
reg [63:0] prev_reg101; // includes G,W,C,F registers
reg [63:0] prev_reg102; // includes G,W,C,F registers
reg [63:0] prev_reg103; // includes G,W,C,F registers
reg [63:0] prev_reg104; // includes G,W,C,F registers
reg [63:0] prev_reg105; // includes G,W,C,F registers
reg [63:0] prev_reg106; // includes G,W,C,F registers
reg [63:0] prev_reg107; // includes G,W,C,F registers
reg [63:0] prev_reg108; // includes G,W,C,F registers
reg [63:0] prev_reg109; // includes G,W,C,F registers
reg [63:0] prev_reg110; // includes G,W,C,F registers
reg [63:0] prev_reg111; // includes G,W,C,F registers
reg [63:0] prev_reg112; // includes G,W,C,F registers
reg [63:0] prev_reg113; // includes G,W,C,F registers
reg [63:0] prev_reg114; // includes G,W,C,F registers
reg [63:0] prev_reg115; // includes G,W,C,F registers
reg [63:0] prev_reg116; // includes G,W,C,F registers
reg [63:0] prev_reg117; // includes G,W,C,F registers
reg [63:0] prev_reg118; // includes G,W,C,F registers
reg [63:0] prev_reg119; // includes G,W,C,F registers
reg [63:0] prev_reg120; // includes G,W,C,F registers
reg [63:0] prev_reg121; // includes G,W,C,F registers
reg [63:0] prev_reg122; // includes G,W,C,F registers
reg [63:0] prev_reg123; // includes G,W,C,F registers
reg [63:0] prev_reg124; // includes G,W,C,F registers
reg [63:0] prev_reg125; // includes G,W,C,F registers
reg [63:0] prev_reg126; // includes G,W,C,F registers
reg [63:0] prev_reg127; // includes G,W,C,F registers
reg [63:0] prev_reg128; // includes G,W,C,F registers
reg [63:0] prev_reg129; // includes G,W,C,F registers
reg [63:0] prev_reg130; // includes G,W,C,F registers
reg [63:0] prev_reg131; // includes G,W,C,F registers
reg [63:0] prev_reg132; // includes G,W,C,F registers
reg [63:0] prev_reg133; // includes G,W,C,F registers
reg [63:0] prev_reg134; // includes G,W,C,F registers
reg [63:0] prev_reg135; // includes G,W,C,F registers
reg [63:0] prev_reg136; // includes G,W,C,F registers
reg [63:0] prev_reg137; // includes G,W,C,F registers
reg [63:0] prev_reg138; // includes G,W,C,F registers
reg [63:0] prev_reg139; // includes G,W,C,F registers
reg [63:0] prev_reg140; // includes G,W,C,F registers
reg [63:0] prev_reg141; // includes G,W,C,F registers
reg [63:0] prev_reg142; // includes G,W,C,F registers
reg [63:0] prev_reg143; // includes G,W,C,F registers
reg [63:0] prev_reg144; // includes G,W,C,F registers
reg [63:0] prev_reg145; // includes G,W,C,F registers
reg [63:0] prev_reg146; // includes G,W,C,F registers
reg [63:0] prev_reg147; // includes G,W,C,F registers
reg [63:0] prev_reg148; // includes G,W,C,F registers
reg [63:0] prev_reg149; // includes G,W,C,F registers
reg [63:0] prev_reg150; // includes G,W,C,F registers
reg [63:0] prev_reg151; // includes G,W,C,F registers
reg [63:0] prev_reg152; // includes G,W,C,F registers
reg [63:0] prev_reg153; // includes G,W,C,F registers
reg [63:0] prev_reg154; // includes G,W,C,F registers
reg [63:0] prev_reg155; // includes G,W,C,F registers
reg [63:0] prev_reg156; // includes G,W,C,F registers
reg [63:0] prev_reg157; // includes G,W,C,F registers
reg [63:0] prev_reg158; // includes G,W,C,F registers
reg [63:0] prev_reg159; // includes G,W,C,F registers
reg [63:0] prev_reg160; // includes G,W,C,F registers
reg [63:0] prev_reg161; // includes G,W,C,F registers
reg [63:0] prev_reg162; // includes G,W,C,F registers
reg [63:0] prev_reg163; // includes G,W,C,F registers
reg [63:0] prev_reg164; // includes G,W,C,F registers
reg [63:0] prev_reg165; // includes G,W,C,F registers
reg [63:0] prev_reg166; // includes G,W,C,F registers
reg [63:0] prev_reg167; // includes G,W,C,F registers
reg [63:0] prev_reg168; // includes G,W,C,F registers
reg [63:0] prev_reg169; // includes G,W,C,F registers
reg [63:0] prev_reg170; // includes G,W,C,F registers
reg [63:0] prev_reg171; // includes G,W,C,F registers
reg [63:0] prev_reg172; // includes G,W,C,F registers
reg [63:0] prev_reg173; // includes G,W,C,F registers
reg [63:0] prev_reg174; // includes G,W,C,F registers
reg [63:0] prev_reg175; // includes G,W,C,F registers
reg [63:0] prev_reg176; // includes G,W,C,F registers
reg [63:0] prev_reg177; // includes G,W,C,F registers
reg [63:0] prev_reg178; // includes G,W,C,F registers
reg [63:0] prev_reg179; // includes G,W,C,F registers
reg [63:0] prev_reg180; // includes G,W,C,F registers
reg [63:0] prev_reg181; // includes G,W,C,F registers
reg [63:0] prev_reg182; // includes G,W,C,F registers
reg [63:0] prev_reg183; // includes G,W,C,F registers
reg [63:0] prev_reg184; // includes G,W,C,F registers
reg [63:0] prev_reg185; // includes G,W,C,F registers
reg [63:0] prev_reg186; // includes G,W,C,F registers
reg [63:0] prev_reg187; // includes G,W,C,F registers
reg [63:0] prev_reg188; // includes G,W,C,F registers
reg [63:0] prev_reg189; // includes G,W,C,F registers
reg [63:0] prev_reg190; // includes G,W,C,F registers
reg [63:0] prev_reg191; // includes G,W,C,F registers
reg [63:0] prev_reg192; // includes G,W,C,F registers
reg [63:0] prev_reg193; // includes G,W,C,F registers
reg [63:0] prev_reg194; // includes G,W,C,F registers
reg [63:0] prev_reg195; // includes G,W,C,F registers
reg [63:0] prev_reg196; // includes G,W,C,F registers
reg [63:0] prev_reg197; // includes G,W,C,F registers
reg [63:0] prev_reg198; // includes G,W,C,F registers
reg [63:0] prev_reg199; // includes G,W,C,F registers
reg [63:0] prev_reg200; // includes G,W,C,F registers
reg [63:0] prev_reg201; // includes G,W,C,F registers
reg [63:0] prev_reg202; // includes G,W,C,F registers
reg [63:0] prev_reg203; // includes G,W,C,F registers
reg [63:0] prev_reg204; // includes G,W,C,F registers
reg [63:0] prev_reg205; // includes G,W,C,F registers
reg [63:0] prev_reg206; // includes G,W,C,F registers
reg [63:0] prev_reg207; // includes G,W,C,F registers
reg [63:0] prev_reg208; // includes G,W,C,F registers
reg [63:0] prev_reg209; // includes G,W,C,F registers
reg [63:0] prev_reg210; // includes G,W,C,F registers
reg [63:0] prev_reg211; // includes G,W,C,F registers
reg [63:0] prev_reg212; // includes G,W,C,F registers
reg [63:0] prev_reg213; // includes G,W,C,F registers
reg [63:0] prev_reg214; // includes G,W,C,F registers
reg [63:0] prev_reg215; // includes G,W,C,F registers
reg [63:0] prev_reg216; // includes G,W,C,F registers
reg [63:0] prev_reg217; // includes G,W,C,F registers
reg [63:0] prev_reg218; // includes G,W,C,F registers
reg [63:0] prev_reg219; // includes G,W,C,F registers
reg [63:0] prev_reg220; // includes G,W,C,F registers
reg [63:0] prev_reg221; // includes G,W,C,F registers
reg [63:0] prev_reg222; // includes G,W,C,F registers
reg [63:0] prev_reg223; // includes G,W,C,F registers
reg [63:0] prev_reg224; // includes G,W,C,F registers
reg [63:0] prev_reg225; // includes G,W,C,F registers
reg [63:0] prev_reg226; // includes G,W,C,F registers
reg [63:0] prev_reg227; // includes G,W,C,F registers
reg [63:0] prev_reg228; // includes G,W,C,F registers
reg [63:0] prev_reg229; // includes G,W,C,F registers
reg [63:0] prev_reg230; // includes G,W,C,F registers
reg [63:0] prev_reg231; // includes G,W,C,F registers
reg [63:0] prev_reg232; // includes G,W,C,F registers
reg [63:0] prev_reg233; // includes G,W,C,F registers
reg [63:0] prev_reg234; // includes G,W,C,F registers
reg [63:0] prev_reg235; // includes G,W,C,F registers
reg [63:0] prev_reg236; // includes G,W,C,F registers
reg [63:0] prev_reg237; // includes G,W,C,F registers
reg [63:0] prev_reg238; // includes G,W,C,F registers
reg [63:0] prev_reg239; // includes G,W,C,F registers
reg [63:0] prev_reg240; // includes G,W,C,F registers
reg [63:0] prev_reg241; // includes G,W,C,F registers
reg [63:0] prev_reg242; // includes G,W,C,F registers
reg [63:0] prev_reg243; // includes G,W,C,F registers
reg [63:0] prev_reg244; // includes G,W,C,F registers
reg [63:0] prev_reg245; // includes G,W,C,F registers
reg [63:0] prev_reg246; // includes G,W,C,F registers
reg [63:0] prev_reg247; // includes G,W,C,F registers
reg [63:0] prev_reg248; // includes G,W,C,F registers
reg [63:0] prev_reg249; // includes G,W,C,F registers
reg [63:0] prev_reg250; // includes G,W,C,F registers
reg [63:0] prev_reg251; // includes G,W,C,F registers
reg [63:0] prev_reg252; // includes G,W,C,F registers
reg [63:0] prev_reg253; // includes G,W,C,F registers
reg [63:0] prev_reg254; // includes G,W,C,F registers
reg [63:0] prev_reg255; // includes G,W,C,F registers
reg [1:0] th_gl; // copy of GL_reg
reg frf_w1_skip_addr4_fw1;
reg frf_w1_skip_addr4_fw2;
reg [1:0] frf_w2_valid_fw;
reg [1:0] frf_w2_valid_bn;
reg [4:0] frf_w2_addr_fw;
reg [1:0] frf_w1_valid_fw;
reg [4:0] frf_w1_addr_fw;
reg wmr; // latched to get edge
reg por_a; // latched to get edge
reg por_b; // latched to get edge
reg nas_pipe_enable; // Turns on nas_pipe capture and Riesling SSTEP
wire [4:0] frf_w1_skip_addr;
wire [4:0] frf_w2_skip_addr;
reg good_trap_detected; // Used for -nosas only.
//----------------------------------------------------------
wire [`DELTA_WIDTH:0] delta_fx4_0;
wire [`DELTA_WIDTH:0] delta_fx4_1;
wire [`DELTA_WIDTH:0] delta_fx4_2;
wire [`DELTA_WIDTH:0] delta_fx4_3;
wire [`DELTA_WIDTH:0] delta_fx4_4;
wire [`DELTA_WIDTH:0] delta_fx4_5;
wire [`DELTA_WIDTH:0] delta_fx4_6;
wire [`DELTA_WIDTH:0] delta_fx4_7;
wire [`DELTA_WIDTH:0] delta_fx5_0;
wire [`DELTA_WIDTH:0] delta_fx5_1;
wire [`DELTA_WIDTH:0] delta_fx5_2;
wire [`DELTA_WIDTH:0] delta_fx5_3;
wire [`DELTA_WIDTH:0] delta_fx5_4;
wire [`DELTA_WIDTH:0] delta_fx5_5;
wire [`DELTA_WIDTH:0] delta_fx5_6;
wire [`DELTA_WIDTH:0] delta_fx5_7;
wire [`DELTA_WIDTH:0] delta_fb_0;
wire [`DELTA_WIDTH:0] delta_fb_1;
wire [`DELTA_WIDTH:0] delta_fb_2;
wire [`DELTA_WIDTH:0] delta_fb_3;
wire [`DELTA_WIDTH:0] delta_fb_4;
wire [`DELTA_WIDTH:0] delta_fb_5;
wire [`DELTA_WIDTH:0] delta_fb_6;
wire [`DELTA_WIDTH:0] delta_fb_7;
wire [`DELTA_WIDTH:0] delta_fw_0;
wire [`DELTA_WIDTH:0] delta_fw_1;
wire [`DELTA_WIDTH:0] delta_fw_2;
wire [`DELTA_WIDTH:0] delta_fw_3;
wire [`DELTA_WIDTH:0] delta_fw_4;
wire [`DELTA_WIDTH:0] delta_fw_5;
wire [`DELTA_WIDTH:0] delta_fw_6;
wire [`DELTA_WIDTH:0] delta_fw_7;
wire [`DELTA_WIDTH:0] delta_fw1_0;
wire [`DELTA_WIDTH:0] delta_fw1_1;
wire [`DELTA_WIDTH:0] delta_fw1_2;
wire [`DELTA_WIDTH:0] delta_fw1_3;
wire [`DELTA_WIDTH:0] delta_fw1_4;
wire [`DELTA_WIDTH:0] delta_fw1_5;
wire [`DELTA_WIDTH:0] delta_fw1_6;
wire [`DELTA_WIDTH:0] delta_fw1_7;
wire [`DELTA_WIDTH:0] delta_fw2_0;
wire [`DELTA_WIDTH:0] delta_fw2_1;
wire [`DELTA_WIDTH:0] delta_fw2_2;
wire [`DELTA_WIDTH:0] delta_fw2_3;
wire [`DELTA_WIDTH:0] delta_fw2_4;
wire [`DELTA_WIDTH:0] delta_fw2_5;
wire [`DELTA_WIDTH:0] delta_fw2_6;
wire [`DELTA_WIDTH:0] delta_fw2_7;
wire [`DELTA_WIDTH:0] delta_prev_0;
wire [`DELTA_WIDTH:0] delta_prev_1;
wire [`DELTA_WIDTH:0] delta_prev_2;
wire [`DELTA_WIDTH:0] delta_prev_3;
wire [`DELTA_WIDTH:0] delta_prev_4;
wire [`DELTA_WIDTH:0] delta_prev_5;
wire [`DELTA_WIDTH:0] delta_prev_6;
wire [`DELTA_WIDTH:0] delta_prev_7;
`PR_ALWAYS ("arg", `ALWAYS,"T%0d DEBUG_PIPE turned ON",mytnum);
//----------------------------------------------------------
// Note: no remap of %g,%o,%l,%i regs based on CWP or GL
assign g0 = (mytid<=3) ? `IRF4_EXU0[( 0+irf_offset)] : `IRF4_EXU1[( 0+irf_offset)];
assign g1 = (mytid<=3) ? `IRF4_EXU0[( 1+irf_offset)] : `IRF4_EXU1[( 1+irf_offset)];
assign g2 = (mytid<=3) ? `IRF4_EXU0[( 2+irf_offset)] : `IRF4_EXU1[( 2+irf_offset)];
assign g3 = (mytid<=3) ? `IRF4_EXU0[( 3+irf_offset)] : `IRF4_EXU1[( 3+irf_offset)];
assign g4 = (mytid<=3) ? `IRF4_EXU0[( 4+irf_offset)] : `IRF4_EXU1[( 4+irf_offset)];
assign g5 = (mytid<=3) ? `IRF4_EXU0[( 5+irf_offset)] : `IRF4_EXU1[( 5+irf_offset)];
assign g6 = (mytid<=3) ? `IRF4_EXU0[( 6+irf_offset)] : `IRF4_EXU1[( 6+irf_offset)];
assign g7 = (mytid<=3) ? `IRF4_EXU0[( 7+irf_offset)] : `IRF4_EXU1[( 7+irf_offset)];
assign o0 = (mytid<=3) ? `IRF4_EXU0[( 8+irf_offset)] : `IRF4_EXU1[( 8+irf_offset)];
assign o1 = (mytid<=3) ? `IRF4_EXU0[( 9+irf_offset)] : `IRF4_EXU1[( 9+irf_offset)];
assign o2 = (mytid<=3) ? `IRF4_EXU0[(10+irf_offset)] : `IRF4_EXU1[(10+irf_offset)];
assign o3 = (mytid<=3) ? `IRF4_EXU0[(11+irf_offset)] : `IRF4_EXU1[(11+irf_offset)];
assign o4 = (mytid<=3) ? `IRF4_EXU0[(12+irf_offset)] : `IRF4_EXU1[(12+irf_offset)];
assign o5 = (mytid<=3) ? `IRF4_EXU0[(13+irf_offset)] : `IRF4_EXU1[(13+irf_offset)];
assign o6 = (mytid<=3) ? `IRF4_EXU0[(14+irf_offset)] : `IRF4_EXU1[(14+irf_offset)];
assign o7 = (mytid<=3) ? `IRF4_EXU0[(15+irf_offset)] : `IRF4_EXU1[(15+irf_offset)];
assign l0 = (mytid<=3) ? `IRF4_EXU0[(16+irf_offset)] : `IRF4_EXU1[(16+irf_offset)];
assign l1 = (mytid<=3) ? `IRF4_EXU0[(17+irf_offset)] : `IRF4_EXU1[(17+irf_offset)];
assign l2 = (mytid<=3) ? `IRF4_EXU0[(18+irf_offset)] : `IRF4_EXU1[(18+irf_offset)];
assign l3 = (mytid<=3) ? `IRF4_EXU0[(19+irf_offset)] : `IRF4_EXU1[(19+irf_offset)];
assign l4 = (mytid<=3) ? `IRF4_EXU0[(20+irf_offset)] : `IRF4_EXU1[(20+irf_offset)];
assign l5 = (mytid<=3) ? `IRF4_EXU0[(21+irf_offset)] : `IRF4_EXU1[(21+irf_offset)];
assign l6 = (mytid<=3) ? `IRF4_EXU0[(22+irf_offset)] : `IRF4_EXU1[(22+irf_offset)];
assign l7 = (mytid<=3) ? `IRF4_EXU0[(23+irf_offset)] : `IRF4_EXU1[(23+irf_offset)];
assign i0 = (mytid<=3) ? `IRF4_EXU0[(24+irf_offset)] : `IRF4_EXU1[(24+irf_offset)];
assign i1 = (mytid<=3) ? `IRF4_EXU0[(25+irf_offset)] : `IRF4_EXU1[(25+irf_offset)];
assign i2 = (mytid<=3) ? `IRF4_EXU0[(26+irf_offset)] : `IRF4_EXU1[(26+irf_offset)];
assign i3 = (mytid<=3) ? `IRF4_EXU0[(27+irf_offset)] : `IRF4_EXU1[(27+irf_offset)];
assign i4 = (mytid<=3) ? `IRF4_EXU0[(28+irf_offset)] : `IRF4_EXU1[(28+irf_offset)];
assign i5 = (mytid<=3) ? `IRF4_EXU0[(29+irf_offset)] : `IRF4_EXU1[(29+irf_offset)];
assign i6 = (mytid<=3) ? `IRF4_EXU0[(30+irf_offset)] : `IRF4_EXU1[(30+irf_offset)];
assign i7 = (mytid<=3) ? `IRF4_EXU0[(31+irf_offset)] : `IRF4_EXU1[(31+irf_offset)];
//----------------------------------------------------------
assign frf_0 = `FRF4_EVEN[(mytid*32)+ 0];
assign frf_2 = `FRF4_EVEN[(mytid*32)+ 1];
assign frf_4 = `FRF4_EVEN[(mytid*32)+ 2];
assign frf_6 = `FRF4_EVEN[(mytid*32)+ 3];
assign frf_8 = `FRF4_EVEN[(mytid*32)+ 4];
assign frf_10 = `FRF4_EVEN[(mytid*32)+ 5];
assign frf_12 = `FRF4_EVEN[(mytid*32)+ 6];
assign frf_14 = `FRF4_EVEN[(mytid*32)+ 7];
assign frf_16 = `FRF4_EVEN[(mytid*32)+ 8];
assign frf_18 = `FRF4_EVEN[(mytid*32)+ 9];
assign frf_20 = `FRF4_EVEN[(mytid*32)+ 10];
assign frf_22 = `FRF4_EVEN[(mytid*32)+ 11];
assign frf_24 = `FRF4_EVEN[(mytid*32)+ 12];
assign frf_26 = `FRF4_EVEN[(mytid*32)+ 13];
assign frf_28 = `FRF4_EVEN[(mytid*32)+ 14];
assign frf_30 = `FRF4_EVEN[(mytid*32)+ 15];
assign frf_32 = `FRF4_EVEN[(mytid*32)+ 16];
assign frf_34 = `FRF4_EVEN[(mytid*32)+ 17];
assign frf_36 = `FRF4_EVEN[(mytid*32)+ 18];
assign frf_38 = `FRF4_EVEN[(mytid*32)+ 19];
assign frf_40 = `FRF4_EVEN[(mytid*32)+ 20];
assign frf_42 = `FRF4_EVEN[(mytid*32)+ 21];
assign frf_44 = `FRF4_EVEN[(mytid*32)+ 22];
assign frf_46 = `FRF4_EVEN[(mytid*32)+ 23];
assign frf_48 = `FRF4_EVEN[(mytid*32)+ 24];
assign frf_50 = `FRF4_EVEN[(mytid*32)+ 25];
assign frf_52 = `FRF4_EVEN[(mytid*32)+ 26];
assign frf_54 = `FRF4_EVEN[(mytid*32)+ 27];
assign frf_56 = `FRF4_EVEN[(mytid*32)+ 28];
assign frf_58 = `FRF4_EVEN[(mytid*32)+ 29];
assign frf_60 = `FRF4_EVEN[(mytid*32)+ 30];
assign frf_62 = `FRF4_EVEN[(mytid*32)+ 31];
assign frf_1 = `FRF4_ODD[(mytid*32)+ 0];
assign frf_3 = `FRF4_ODD[(mytid*32)+ 1];
assign frf_5 = `FRF4_ODD[(mytid*32)+ 2];
assign frf_7 = `FRF4_ODD[(mytid*32)+ 3];
assign frf_9 = `FRF4_ODD[(mytid*32)+ 4];
assign frf_11 = `FRF4_ODD[(mytid*32)+ 5];
assign frf_13 = `FRF4_ODD[(mytid*32)+ 6];
assign frf_15 = `FRF4_ODD[(mytid*32)+ 7];
assign frf_17 = `FRF4_ODD[(mytid*32)+ 8];
assign frf_19 = `FRF4_ODD[(mytid*32)+ 9];
assign frf_21 = `FRF4_ODD[(mytid*32)+ 10];
assign frf_23 = `FRF4_ODD[(mytid*32)+ 11];
assign frf_25 = `FRF4_ODD[(mytid*32)+ 12];
assign frf_27 = `FRF4_ODD[(mytid*32)+ 13];
assign frf_29 = `FRF4_ODD[(mytid*32)+ 14];
assign frf_31 = `FRF4_ODD[(mytid*32)+ 15];
assign frf_33 = `FRF4_ODD[(mytid*32)+ 16];
assign frf_35 = `FRF4_ODD[(mytid*32)+ 17];
assign frf_37 = `FRF4_ODD[(mytid*32)+ 18];
assign frf_39 = `FRF4_ODD[(mytid*32)+ 19];
assign frf_41 = `FRF4_ODD[(mytid*32)+ 20];
assign frf_43 = `FRF4_ODD[(mytid*32)+ 21];
assign frf_45 = `FRF4_ODD[(mytid*32)+ 22];
assign frf_47 = `FRF4_ODD[(mytid*32)+ 23];
assign frf_49 = `FRF4_ODD[(mytid*32)+ 24];
assign frf_51 = `FRF4_ODD[(mytid*32)+ 25];
assign frf_53 = `FRF4_ODD[(mytid*32)+ 26];
assign frf_55 = `FRF4_ODD[(mytid*32)+ 27];
assign frf_57 = `FRF4_ODD[(mytid*32)+ 28];
assign frf_59 = `FRF4_ODD[(mytid*32)+ 29];
assign frf_61 = `FRF4_ODD[(mytid*32)+ 30];
assign frf_63 = `FRF4_ODD[(mytid*32)+ 31];
//----------------------------------------------------------
assign delta_fx4_0 = delta_fx4[0];
assign delta_fx4_1 = delta_fx4[1];
assign delta_fx4_2 = delta_fx4[2];
assign delta_fx4_3 = delta_fx4[3];
assign delta_fx4_4 = delta_fx4[4];
assign delta_fx4_5 = delta_fx4[5];
assign delta_fx4_6 = delta_fx4[6];
assign delta_fx4_7 = delta_fx4[7];
assign delta_fx5_0 = delta_fx5[0];
assign delta_fx5_1 = delta_fx5[1];
assign delta_fx5_2 = delta_fx5[2];
assign delta_fx5_3 = delta_fx5[3];
assign delta_fx5_4 = delta_fx5[4];
assign delta_fx5_5 = delta_fx5[5];
assign delta_fx5_6 = delta_fx5[6];
assign delta_fx5_7 = delta_fx5[7];
assign delta_fb_0 = delta_fb[0];
assign delta_fb_1 = delta_fb[1];
assign delta_fb_2 = delta_fb[2];
assign delta_fb_3 = delta_fb[3];
assign delta_fb_4 = delta_fb[4];
assign delta_fb_5 = delta_fb[5];
assign delta_fb_6 = delta_fb[6];
assign delta_fb_7 = delta_fb[7];
assign delta_fw_0 = delta_fw[0];
assign delta_fw_1 = delta_fw[1];
assign delta_fw_2 = delta_fw[2];
assign delta_fw_3 = delta_fw[3];
assign delta_fw_4 = delta_fw[4];
assign delta_fw_5 = delta_fw[5];
assign delta_fw_6 = delta_fw[6];
assign delta_fw_7 = delta_fw[7];
assign delta_fw1_0 = delta_fw1[0];
assign delta_fw1_1 = delta_fw1[1];
assign delta_fw1_2 = delta_fw1[2];
assign delta_fw1_3 = delta_fw1[3];
assign delta_fw1_4 = delta_fw1[4];
assign delta_fw1_5 = delta_fw1[5];
assign delta_fw1_6 = delta_fw1[6];
assign delta_fw1_7 = delta_fw1[7];
assign delta_fw2_0 = delta_fw2[0];
assign delta_fw2_1 = delta_fw2[1];
assign delta_fw2_2 = delta_fw2[2];
assign delta_fw2_3 = delta_fw2[3];
assign delta_fw2_4 = delta_fw2[4];
assign delta_fw2_5 = delta_fw2[5];
assign delta_fw2_6 = delta_fw2[6];
assign delta_fw2_7 = delta_fw2[7];
assign delta_prev_0 = delta_prev[0];
assign delta_prev_1 = delta_prev[1];
assign delta_prev_2 = delta_prev[2];
assign delta_prev_3 = delta_prev[3];
assign delta_prev_4 = delta_prev[4];
assign delta_prev_5 = delta_prev[5];
assign delta_prev_6 = delta_prev[6];
assign delta_prev_7 = delta_prev[7];
//----------------------------------------------------------
//----------------------------------------------------------
assign mytnum = (mycid*8)+mytid;
assign mytg = mytid >> 2;
assign exu_complete = exu_valid & ~(`PROBES4.clkstop_d5|`TOP.in_reset|`SPC4.tcu_scan_en);
assign imul_complete = imul_valid & ~(`TOP.in_reset|`SPC4.tcu_scan_en);
assign idiv_complete = idiv_valid & ~(`TOP.in_reset|`SPC4.tcu_scan_en);
assign tlu_complete = tlu_complete_3 ;
assign fp_complete = fp_valid & ~(`TOP.in_reset|`SPC4.tcu_scan_en);
assign fdiv_complete = fdiv_valid & ~(`TOP.in_reset|`SPC4.tcu_scan_en);
assign lsu_complete = lsu_valid & ~(`TOP.in_reset|`SPC4.tcu_scan_en);
assign asi_complete = asi_valid & ~(`TOP.in_reset|`SPC4.tcu_scan_en);
assign complete_w = (exu_complete << `EXU_INDEX) |
(lsu_complete << `LSU_INDEX) |
(tlu_complete << `TLU_INDEX) |
(asi_complete << `ASI_INDEX) ;
assign oddwin = CWP_reg % 2;
assign frf_w1_valid_even = (frf_w1_tid_fw == mytid) & frf_w1_valid_fw[1];
assign frf_w1_valid_odd = (frf_w1_tid_fw == mytid) & frf_w1_valid_fw[0];
assign frf_w2_valid_even = (frf_w2_tid_fw == mytid) & frf_w2_valid_fw[1];
assign frf_w2_valid_odd = (frf_w2_tid_fw == mytid) & frf_w2_valid_fw[0];
assign frf_w1_skip_addr = frf_w1_addr_fw;
assign frf_w2_skip_addr = frf_w2_addr_fw;
// NOTE - ADD_TSB_CFG will never be used for Axis or Tharas
wire [63:0] ctxt_z_tsb_cfg0_reg = `PROBES4.ctxt_z_tsb_cfg0_reg[mytid];
wire [63:0] ctxt_z_tsb_cfg1_reg = `PROBES4.ctxt_z_tsb_cfg1_reg[mytid];
wire [63:0] ctxt_z_tsb_cfg2_reg = `PROBES4.ctxt_z_tsb_cfg2_reg[mytid];
wire [63:0] ctxt_z_tsb_cfg3_reg = `PROBES4.ctxt_z_tsb_cfg3_reg[mytid];
wire [63:0] ctxt_nz_tsb_cfg0_reg = `PROBES4.ctxt_nz_tsb_cfg0_reg[mytid];
wire [63:0] ctxt_nz_tsb_cfg1_reg = `PROBES4.ctxt_nz_tsb_cfg1_reg[mytid];
wire [63:0] ctxt_nz_tsb_cfg2_reg = `PROBES4.ctxt_nz_tsb_cfg2_reg[mytid];
wire [63:0] ctxt_nz_tsb_cfg3_reg = `PROBES4.ctxt_nz_tsb_cfg3_reg[mytid];
//----------------------------------------------------------
always @ (posedge `BENCH_SPC4_GCLK) begin // {
// TLU is async to the execution pipeline
// but needs to be delayed to allow CWP, etc to update and be stable
// before arch state is captured and diff_reg is called.
// FDIV was moved from fw1 to fw to allow FPRS to be stable before capture
tlu_complete_1 <= tlu_valid & ~(`TOP.in_reset|`SPC4.tcu_scan_en);
tlu_complete_2 <= tlu_complete_1;
tlu_complete_3 <= tlu_complete_2;
itagacc_fx5 <= I_TAG_ACC_reg; // Signal changes in W so need to pipeline to fw2
itagacc_fb <= itagacc_fx5;
itagacc_fw <= itagacc_fb;
itagacc_fw1 <= itagacc_fw;
itagacc_fw2 <= itagacc_fw1;
dtagacc_fx5 <= D_TAG_ACC_reg; // Signal changes in W so need to pipeline to fw2
dtagacc_fb <= dtagacc_fx5;
dtagacc_fw <= dtagacc_fb;
dtagacc_fw1 <= dtagacc_fw;
dtagacc_fw2 <= dtagacc_fw1;
dsfar_fb <= DSFAR_reg; // Signal changes in W+1 so need to pipeline to fw2
complete_fx4 <= complete_w;
complete_fx5 <= complete_fx4 ;
complete_fb <= complete_fx5 |
(idiv_complete << `IDIV_INDEX);
complete_fw <= complete_fb |
(fdiv_complete << `FDIV_INDEX) |
(imul_complete << `IMUL_INDEX);
complete_fw1 <= complete_fw |
(fp_complete << `FP_INDEX);
complete_fw2 <= complete_fw1;
frf_w1_valid_fw1 <= (frf_w1_valid_odd | frf_w1_valid_even) & fp_complete;
frf_w1_valid_fw2 <= frf_w1_valid_fw1;
frf_w1_skip_addr4_fw1 <= frf_w1_skip_addr[4];
frf_w1_skip_addr4_fw2 <= frf_w1_skip_addr4_fw1;
frf_w2_valid_fw <= frf_w2_valid_bn;
frf_w2_tid_fw <= frf_w2_tid;
frf_w2_addr_fw <= frf_w2_addr;
frf_w1_valid_fw <= frf_w1_valid;
frf_w1_tid_fw <= frf_w1_tid;
frf_w1_addr_fw <= frf_w1_addr;
if (~thread_running & `SPC4.tcu_core_running[mytid])
`TOP.th_last_act_cycle[mytnum] = `TOP.core_cycle_cnt;
thread_running <= `SPC4.tcu_core_running[mytid];
// Reset some register prev state on wmr negation
if (`SPC4.rst_wmr_protect && ~wmr)
wmr <= `SPC4.rst_wmr_protect;
if (`SPC4.rst_wmr_protect)
//----------------------------------------------------------
// Holding state for registers that may be updated asynchronously
// after synchronous update, but before capture/step. Also for reads,
// when register is read and modified before capture/step ..
// We capture the value /write time, and use that for sstep,
// ignoring any async updates, which are sent in the NEXT sstep ..
reg [63:0] asi_updated_int_rec;
reg asi_wr_int_rec_delay;
reg [16:0] asi_updated_softint;
reg asi_wr_softint_delay;
reg [16:0] asi_softint_wrdata;
always @(posedge `BENCH_SPC4_GCLK) begin // {
// Corner case : If async and sync wr occur in same clock, then the async
// update takes place. In this case we have to capture the
// value of the write WITHOUT async bit being set, so that
// we can sync with Riesling's sync write ..
asi_wr_int_rec_delay <= ( `SPC4.tlu.cth.asi_wr_int_rec[mytid] |
`SPC4.tlu.asi_rd_inc_vec_2[mytid]);
if (`SPC4.tlu.cth.asi_wr_int_rec[mytid] |
((`SPC4.tlu.asi.rd_inc_vec) &&
(`SPC4.tlu.asi.rd_tid_dec[mytid])) |
(`SPC4.tlu.asi_rd_int_rec &
`SPC4.tlu.cth.int_rec_mux_sel==mytid))
if (`SPC4.tlu.cth.asi_wr_int_rec[mytid])
asi_updated_int_rec <= `SPC4.tlu.cth.int_rec ;
else if ( (`SPC4.tlu.asi.rd_inc_vec) &&
(`SPC4.tlu.asi.rd_tid_dec[mytid]) )
if (`SPC4.tlu.cth.cxi_wr_int_dis[mytid]) begin
asi_updated_int_rec <= INTR_RECEIVE_reg & `SPC4.tlu.cth.int_rec_muxed_;
asi_updated_int_rec[`SPC4.tlu.cth.incoming_vector_in] <= 1'b0 ;
asi_updated_int_rec <= `SPC4.tlu.cth.int_rec_muxed ;
asi_updated_int_rec[`SPC4.tlu.cth.incoming_vector_in] <= 1'b0 ;
asi_updated_int_rec <= INTR_RECEIVE_reg;
asi_rdwr_int_rec <= 1'b1;
else if (complete_fw1 && !`NASTOP.sstep_early[mytnum])
asi_rdwr_int_rec <= 1'b0;
asi_wr_hintp_delay <= `SPC4.tlu.asi_wr_hintp[mytid];
if (`SPC4.tlu.asi_wr_hintp[mytid] |
`SPC4.tlu.asi_rd_hintp[mytid])
if (`SPC4.tlu.asi_wr_hintp[mytid])
asi_updated_hintp <= `SPC4.tlu.asi_wr_data_0[0] ;
asi_updated_hintp <= HINTP_reg;
else if (complete_fw1 && !`NASTOP.sstep_early[mytnum])
asi_wr_softint_delay <= (`SPC4.tlu.asi_wr_softint[mytid] |
`SPC4.tlu.asi_wr_clear_softint[mytid] |
`SPC4.tlu.asi_wr_set_softint[mytid]);
if (`SPC4.tlu.asi_wr_clear_softint[mytid])
asi_softint_wrdata <= ~`SPC4.tlu.asi_wr_data_0[16:0] & rd_SOFTINT_reg;
else if (`SPC4.tlu.asi_wr_set_softint[mytid])
asi_softint_wrdata <= `SPC4.tlu.asi_wr_data_0[16:0] | rd_SOFTINT_reg;
asi_softint_wrdata <= `SPC4.tlu.asi_wr_data_0[16:0];
if (asi_wr_softint_delay | `SPC4.tlu.asi_rd_softint[mytid])
if (asi_wr_softint_delay)
asi_updated_softint <= asi_softint_wrdata ;
asi_updated_softint <= rd_SOFTINT_reg ;
asi_rdwr_softint <= 1'b1;
else if (complete_fw1 && !`NASTOP.sstep_early[mytnum])
asi_rdwr_softint <= 1'b0;
//----------------------------------------------------------
// Negedge sampling to avoid race on specific signals ..
always @ (negedge `BENCH_SPC4_GCLK) begin // {
frf_w2_valid_bn <= frf_w2_valid;
//----------------------------------------------------------
// When instruction completes,
// Push differences to simics
always @ (posedge `BENCH_SPC4_GCLK) begin // {
if (`PARGS.th_check_enable[mytnum] && nas_pipe_enable && ~`SPC4.tcu_scan_en && ~`TOP.in_por) begin // {
// Update window registers
if (CWP_reg != `NASTOP.th_cwp[mytnum]) begin // {
copy_win (CWP_reg,`NASTOP.th_cwp[mytnum]);
`NASTOP.th_cwp[mytnum] = CWP_reg;
// Update global registers
// Wait for warm-reset flush related toggling to settle
if (GL_reg != th_gl) begin // {
if (`SPC4.spc_core_running_status[mytid] &
~`SPC4.rst_wmr_protect) begin // {
copy_global (GL_reg,th_gl);
// Check for bad signal values
// if NASTOP.sstep_sent[tid]=1,
// then SSTEP was set by another module (i.e. tlb_sync)
if (`PARGS.nas_check_on) begin // {
mytime = `TOP.core_cycle_cnt-1;
if (complete_fw2 && (`NASTOP.sstep_sent[mytnum]==1'b0)) begin // {
`PR_INFO ("pli_nas", `INFO, " C%0d T%0d PLI_SSTEP tid=%d pc=%h ts=%0d ",
mycid,mytid,mytnum,pc_fw2,mytime);
junk = $sim_send(`PLI_SSTEP, mytnum);
// Always clear sstep_early
// In case tlb_sync asserted it too late for complete_fw2
`NASTOP.sstep_early[mytnum] <= 1'b0;
else if (complete_fw2) begin // {
`NASTOP.sstep_sent[mytnum] <= 1'b0; // re-arm SSTEP
`NASTOP.sstep_early[mytnum] <= 1'b0;
`PR_INFO ("pli_nas", `INFO, " C%0d T%0d PLI_SSTEP tid=%d pc=%h ts=%0d (nas_pipe: skip sstep. rearm sstep. sstep_sent=0)",
mycid,mytid,mytnum,pc_fw2,mytime);
// Only capture if something completes and not first instruction
if (complete_fw2 && !first_op) begin // {
push_simics; // Use with AXIS to keep from getting timeout
// Pipeline runs continuously
// Other than when in POR ..
// Only save to delta_prev when something completes
`TOP.last_act_cycle = `TOP.core_cycle_cnt; //$time;
`TOP.th_last_act_cycle[mytnum] = `TOP.last_act_cycle;
// If something was captured but no instruction is in the pipeline
if ((delta_fw2[`NEXT_INDEX]!=`FIRST_INDEX) && (complete_fw2 == 0))
for (myindex=`FIRST_INDEX; myindex<delta_fw2[`NEXT_INDEX]; myindex=myindex+1)
print_entry (delta_fw2[myindex]);
`PR_ERROR ("nas",`ERROR, "T%0d Unexpected Reg change in DUT. Special case - no instruction retired.", mytnum);
// End detection for non-sas runs ..
for (junk=0;junk<`PARGS.bad_trap_count;junk=junk+1)
if (({16'b0,pc_fw2}&`PC_MASK) ===
(`PARGS.bad_trap_addr[junk]&`PC_MASK)) begin // {
// Disable nas_pipe processing (capture & SSTEP)
// to speed up simulation (minimize socket traffic,etc)
if (! `PARGS.nas_check_on) begin //{
`PR_ERROR ("nas",`ERROR, "T%0d reached Bad Trap", mytnum);
for (junk=0;junk<`PARGS.good_trap_count;junk=junk+1)
if ((|complete_fw2) && (({16'b0,pc_fw2}&`PC_MASK) ===
(`PARGS.good_trap_addr[junk]&`PC_MASK))) begin // {
// Disable nas_pipe processing (capture & SSTEP)
// to speed up simulation (minimize socket traffic,etc)
if (! `PARGS.nas_check_on) begin //{
good_trap_detected = 1'b1;
// Check Thread level timeout
(`TOP.core_cycle_cnt - `TOP.th_last_act_cycle[mytnum]) > `PARGS.th_timeout)
// Note: Do not change this message because regreport parses it for certain words.
`PR_ALWAYS ("nas",`ALWAYS, "ERROR: Thread T%0d No Activity for %0d Cycles - Thread TIMEOUT!",
mytnum, `PARGS.th_timeout);
junk = incErr(9999); // must exceed users max error setting to force exit.
end // if (`PARGS.th_check_enable[mytnum] && nas_pipe_enable ...)}
// Need to make sure Store Buffer is empty before turning off th_check_enable.
//global chkr requires to wait for all outstanding pending I
if ((! `PARGS.nas_check_on) &&
(good_trap_detected==1'b1) &&
(`TOP.nas_top.lsu_stb_empty[mytnum]) && `TOP.nas_top.ireq_pending[mytnum]) begin // {
`PARGS.th_check_enable[mytnum] = 1'b0;
`TOP.finished_tids[mytnum] = 1'b1;
good_trap_detected = 1'b0;
`PR_NORMAL ("nas", `NORMAL, "T%0d reached Good Trap. Disabling checking for thread %0d", mytnum,mytnum);
//----------------------------------------------------------
//----------------------------------------------------------
// Stage FX4 of delta pipeline
delta_fx4[`NEXT_INDEX] <= `FIRST_INDEX;
delta_fx4[`TIME_INDEX] <= 0;
delta_fx4[`PC_INDEX] <= {16'b0,PC_reg};
delta_fx4[`GL_INDEX] <= GL_reg;
delta_fx4[`CWP_INDEX] <= CWP_reg;
delta_fx4[`OPCODE_INDEX] <= opcode;
delta_fx4[`FIRST_INDEX] <= 77'hx;
//----------------------------------------------------------
// Stage FX5 of delta pipeline
index = delta_fx4[`NEXT_INDEX];
// Pipeline previous stage
for (i=0; i<=delta_fx4[`NEXT_INDEX]; i=i+1) begin // {
delta_fx5[i] <= delta_fx4[i];
if (complete_fx4) begin // LSU | EXU | TLU
push_delta_fx5 (`CCR+`CTL_OFFSET,CCR_reg,index);
if (complete_fx4[`LSU_INDEX] |
complete_fx4[`EXU_INDEX]) begin
if (mytid <= 3) begin // {
for (i=0; i<=31; i=i+1) begin // {
push_delta_fx5 (i,`IRF4_EXU0[(remap(i,oddwin)+irf_offset)],index);
for (i=0; i<=31; i=i+1) begin // {
push_delta_fx5 (i,`IRF4_EXU1[(remap(i,oddwin)+irf_offset)],index);
// Update FRF4 - Loads use W2 Port.
if (complete_fx4[`LSU_INDEX]) begin // {
// IF W1 port is also being written, ignore that address
for (i=0; i<=31; i=i+1) begin // {
if (!((i == frf_w1_skip_addr) && frf_w1_valid_even)) begin // {
frf_tmp = `FRF4_EVEN[(mytid*32)+i];
push_delta_fx5 (`FP_OFFSET + (i*2), frf_tmp[31:0], index);
if (!((i == frf_w1_skip_addr) && frf_w1_valid_odd)) begin // {
frf_tmp = `FRF4_ODD[(mytid*32)+i];
push_delta_fx5 (`FP_OFFSET + (i*2)+1, frf_tmp[31:0], index);
// Update ASR/ASI registers
if (complete_fx4) begin // {
push_delta_fx5 (`PSTATE + `CTL_OFFSET,PSTATE_reg,index);
push_delta_fx5 (`HPSTATE + `CTL_OFFSET,HPSTATE_reg,index);
push_delta_fx5 (`PIL + `CTL_OFFSET,PIL_reg,index);
push_delta_fx5 (`TBA + `CTL_OFFSET,{TBA_reg,15'b0},index);
push_delta_fx5 (`GL + `CTL_OFFSET,GL_reg,index);
push_delta_fx5 (`HTBA + `CTL_OFFSET,{HTBA_reg,14'b0},index);
push_delta_fx5 (`VER + `CTL_OFFSET,VER_reg,index);
push_delta_fx5 (`Y + `CTL_OFFSET,Y_reg,index);
push_delta_fx5 (`ASI + `CTL_OFFSET,ASI_reg,index);
push_delta_fx5 (`STICK_CMPR + `CTL_OFFSET,STICK_CMPR_wire,index);
push_delta_fx5 (`HSTICK_CMPR + `CTL_OFFSET,HSTICK_CMPR_wire,index);
push_delta_fx5 (`TICK_CMPR + `CTL_OFFSET,TICK_CMPR_wire,index);
push_delta_fx5 (`CWP + `CTL_OFFSET,CWP_reg,index);
push_delta_fx5 (`CANSAVE + `CTL_OFFSET,CANSAVE_reg,index);
push_delta_fx5 (`CANRESTORE + `CTL_OFFSET,CANRESTORE_reg,index);
push_delta_fx5 (`CLEANWIN + `CTL_OFFSET,CLEANWIN_reg,index);
push_delta_fx5 (`OTHERWIN + `CTL_OFFSET,OTHERWIN_reg,index);
push_delta_fx5 (`WSTATE + `CTL_OFFSET,WSTATE_reg,index);
push_delta_fx5 (`CTXT_PRIM_0+`CTL_OFFSET,CTXT_PRIM_0_reg,index);
push_delta_fx5 (`CTXT_SEC_0+`CTL_OFFSET,CTXT_SEC_0_reg,index);
push_delta_fx5 (`CTXT_PRIM_1+`CTL_OFFSET,CTXT_PRIM_1_reg,index);
push_delta_fx5 (`CTXT_SEC_1+`CTL_OFFSET,CTXT_SEC_1_reg,index);
push_delta_fx5 (`LSU_CONTROL+`CTL_OFFSET,LSU_CONTROL_reg,index);
push_delta_fx5 (`WATCHPOINT_ADDR+`CTL_OFFSET,WATCHPOINT_ADDR_reg,index);
// NOTE - ADD_TSB_CFG will never be used for Axis or Tharas
push_delta_fx5 (`CTXT_Z_TSB_CFG0+`CTL_OFFSET,ctxt_z_tsb_cfg0_reg,index);
push_delta_fx5 (`CTXT_Z_TSB_CFG1+`CTL_OFFSET,ctxt_z_tsb_cfg1_reg,index);
push_delta_fx5 (`CTXT_Z_TSB_CFG2+`CTL_OFFSET,ctxt_z_tsb_cfg2_reg,index);
push_delta_fx5 (`CTXT_Z_TSB_CFG3+`CTL_OFFSET,ctxt_z_tsb_cfg3_reg,index);
push_delta_fx5 (`CTXT_NZ_TSB_CFG0+`CTL_OFFSET,ctxt_nz_tsb_cfg0_reg,index);
push_delta_fx5 (`CTXT_NZ_TSB_CFG1+`CTL_OFFSET,ctxt_nz_tsb_cfg1_reg,index);
push_delta_fx5 (`CTXT_NZ_TSB_CFG2+`CTL_OFFSET,ctxt_nz_tsb_cfg2_reg,index);
push_delta_fx5 (`CTXT_NZ_TSB_CFG3+`CTL_OFFSET,ctxt_nz_tsb_cfg3_reg,index);
// Update GSR for all except write ASR in progess
if (!asi_in_progress) begin // {
push_delta_fx5 (`GSR + `CTL_OFFSET,GSR_wire, index);
// If lsu_complete & fp_complete assert at same time,
// then the fp_complete is the one that will modify the FSR
if (complete_fx4[`LSU_INDEX] & !complete_fw1[`FP_INDEX]) begin
push_delta_fx5 (`FSR+`CTL_OFFSET,FSR_wire,index);
// Non Trap updates of Trap stack & level
if (complete_fx4 && !complete_fx4[`TLU_INDEX]) begin // {
push_delta_fx5 (`TL + `CTL_OFFSET,TL_reg,index);
push_delta_fx5 (`TPC1 + `CTL_OFFSET, TPC1_wire, index);
push_delta_fx5 (`TPC2 + `CTL_OFFSET, TPC2_wire, index);
push_delta_fx5 (`TPC3 + `CTL_OFFSET, TPC3_wire, index);
push_delta_fx5 (`TPC4 + `CTL_OFFSET, TPC4_wire, index);
push_delta_fx5 (`TPC5 + `CTL_OFFSET, TPC5_wire, index);
push_delta_fx5 (`TPC6 + `CTL_OFFSET, TPC6_wire, index);
push_delta_fx5 (`TNPC1 + `CTL_OFFSET, TNPC1_wire, index);
push_delta_fx5 (`TNPC2 + `CTL_OFFSET, TNPC2_wire, index);
push_delta_fx5 (`TNPC3 + `CTL_OFFSET, TNPC3_wire, index);
push_delta_fx5 (`TNPC4 + `CTL_OFFSET, TNPC4_wire, index);
push_delta_fx5 (`TNPC5 + `CTL_OFFSET, TNPC5_wire, index);
push_delta_fx5 (`TNPC6 + `CTL_OFFSET, TNPC6_wire, index);
push_delta_fx5 (`TSTATE1 + `CTL_OFFSET, TSTATE1_wire, index);
push_delta_fx5 (`TSTATE2 + `CTL_OFFSET, TSTATE2_wire, index);
push_delta_fx5 (`TSTATE3 + `CTL_OFFSET, TSTATE3_wire, index);
push_delta_fx5 (`TSTATE4 + `CTL_OFFSET, TSTATE4_wire, index);
push_delta_fx5 (`TSTATE5 + `CTL_OFFSET, TSTATE5_wire, index);
push_delta_fx5 (`TSTATE6 + `CTL_OFFSET, TSTATE6_wire, index);
push_delta_fx5 (`HTSTATE1 + `CTL_OFFSET, HTSTATE1_wire, index);
push_delta_fx5 (`HTSTATE2 + `CTL_OFFSET, HTSTATE2_wire, index);
push_delta_fx5 (`HTSTATE3 + `CTL_OFFSET, HTSTATE3_wire, index);
push_delta_fx5 (`HTSTATE4 + `CTL_OFFSET, HTSTATE4_wire, index);
push_delta_fx5 (`HTSTATE5 + `CTL_OFFSET, HTSTATE5_wire, index);
push_delta_fx5 (`HTSTATE6 + `CTL_OFFSET, HTSTATE6_wire, index);
push_delta_fx5 (`TT1 + `CTL_OFFSET, TT1_wire, index);
push_delta_fx5 (`TT2 + `CTL_OFFSET, TT2_wire, index);
push_delta_fx5 (`TT3 + `CTL_OFFSET, TT3_wire, index);
push_delta_fx5 (`TT4 + `CTL_OFFSET, TT4_wire, index);
push_delta_fx5 (`TT5 + `CTL_OFFSET, TT5_wire, index);
push_delta_fx5 (`TT6 + `CTL_OFFSET, TT6_wire, index);
//----------------------------------------------------------
// Stage FB of delta pipeline
index = delta_fx5[`NEXT_INDEX];
// Pipeline previous stage
for (i=0; i<=delta_fx5[`NEXT_INDEX]; i=i+1) begin // {
delta_fb[i] <= delta_fx5[i];
if (complete_fx5[`ASI_INDEX]) begin // {
push_delta_fb (`GSR + `CTL_OFFSET,GSR_wire, index);
//----------------------------------------------------------
// Stage FW of delta pipeline
index = delta_fb[`NEXT_INDEX];
// Pipeline previous stage
for (i=0; i<=delta_fb[`NEXT_INDEX]; i=i+1) begin // {
delta_fw[i] <= delta_fb[i];
// Capture CWP_reg for SAVE/RESTORE
delta_fw[`CWP_INDEX] <= CWP_reg;
if (complete_fb[`TLU_INDEX]) begin
if (mytid <= 3) begin // {
for (i=0; i<=31; i=i+1) begin // {
push_delta_fw (i,`IRF4_EXU0[(remap(i,oddwin)+irf_offset)],index);
for (i=0; i<=31; i=i+1) begin // {
push_delta_fw (i,`IRF4_EXU1[(remap(i,oddwin)+irf_offset)],index);
// Update FRF4 - Idivs use W2.
if (complete_fb[`IDIV_INDEX]) begin // {
// IF W1 port is also being written, ignore that address
for (i=0; i<=31; i=i+1) begin // {
if (!((i == frf_w1_skip_addr) && frf_w1_valid_even)) begin // {
frf_tmp = `FRF4_EVEN[(mytid*32)+i];
push_delta_fw (`FP_OFFSET + (i*2), frf_tmp[31:0], index);
if (!((i == frf_w1_skip_addr) && frf_w1_valid_odd)) begin // {
frf_tmp = `FRF4_ODD[(mytid*32)+i];
push_delta_fw (`FP_OFFSET + (i*2)+1,frf_tmp[31:0], index);
//----------------------------------------------------------
// Stage FW1 of delta pipeline
index = delta_fw[`NEXT_INDEX];
// Pipeline previous stage
for (i=0; i<=delta_fw[`NEXT_INDEX]; i=i+1) begin // {
delta_fw1[i] <= delta_fw[i];
// Update FRF4 - FPops use W1 port.
if (fp_complete) begin // {
// IF W2 port is also being written, ignore that address
for (i=0; i<=31; i=i+1) begin // {
if (!((i == frf_w2_skip_addr) && frf_w2_valid_even)) begin // {
frf_tmp = `FRF4_EVEN[(mytid*32)+i];
push_delta_fw1 (`FP_OFFSET + (i*2), frf_tmp[31:0], index);
if (!((i == frf_w2_skip_addr) && frf_w2_valid_odd)) begin // {
frf_tmp = `FRF4_ODD[(mytid*32)+i];
push_delta_fw1 (`FP_OFFSET + (i*2)+1,frf_tmp[31:0], index);
if (complete_fw[`IMUL_INDEX]|complete_fw[`IDIV_INDEX]) begin
push_delta_fw1 (`CCR+`CTL_OFFSET,CCR_reg,index);
push_delta_fw1 (`Y+`CTL_OFFSET,Y_reg,index);
push_delta_fw1 (`CWP+`CTL_OFFSET,CWP_reg,index);
push_delta_fw1 (`CANSAVE+`CTL_OFFSET,CANSAVE_reg,index);
push_delta_fw1 (`CANRESTORE+`CTL_OFFSET,CANRESTORE_reg,index);
push_delta_fw1 (`CLEANWIN+`CTL_OFFSET,CLEANWIN_reg,index);
push_delta_fw1 (`OTHERWIN+`CTL_OFFSET,OTHERWIN_reg,index);
push_delta_fw1 (`WSTATE+`CTL_OFFSET,WSTATE_reg,index);
if (complete_fw[`TLU_INDEX]) begin // {
push_delta_fw1 (`TL + `CTL_OFFSET,TL_reg,index);
push_delta_fw1 (`TPC1 + `CTL_OFFSET, TPC1_wire, index);
push_delta_fw1 (`TPC2 + `CTL_OFFSET, TPC2_wire, index);
push_delta_fw1 (`TPC3 + `CTL_OFFSET, TPC3_wire, index);
push_delta_fw1 (`TPC4 + `CTL_OFFSET, TPC4_wire, index);
push_delta_fw1 (`TPC5 + `CTL_OFFSET, TPC5_wire, index);
push_delta_fw1 (`TPC6 + `CTL_OFFSET, TPC6_wire, index);
push_delta_fw1 (`TNPC1 + `CTL_OFFSET, TNPC1_wire, index);
push_delta_fw1 (`TNPC2 + `CTL_OFFSET, TNPC2_wire, index);
push_delta_fw1 (`TNPC3 + `CTL_OFFSET, TNPC3_wire, index);
push_delta_fw1 (`TNPC4 + `CTL_OFFSET, TNPC4_wire, index);
push_delta_fw1 (`TNPC5 + `CTL_OFFSET, TNPC5_wire, index);
push_delta_fw1 (`TNPC6 + `CTL_OFFSET, TNPC6_wire, index);
push_delta_fw1 (`TSTATE1 + `CTL_OFFSET, TSTATE1_wire, index);
push_delta_fw1 (`TSTATE2 + `CTL_OFFSET, TSTATE2_wire, index);
push_delta_fw1 (`TSTATE3 + `CTL_OFFSET, TSTATE3_wire, index);
push_delta_fw1 (`TSTATE4 + `CTL_OFFSET, TSTATE4_wire, index);
push_delta_fw1 (`TSTATE5 + `CTL_OFFSET, TSTATE5_wire, index);
push_delta_fw1 (`TSTATE6 + `CTL_OFFSET, TSTATE6_wire, index);
push_delta_fw1 (`HTSTATE1 + `CTL_OFFSET, HTSTATE1_wire, index);
push_delta_fw1 (`HTSTATE2 + `CTL_OFFSET, HTSTATE2_wire, index);
push_delta_fw1 (`HTSTATE3 + `CTL_OFFSET, HTSTATE3_wire, index);
push_delta_fw1 (`HTSTATE4 + `CTL_OFFSET, HTSTATE4_wire, index);
push_delta_fw1 (`HTSTATE5 + `CTL_OFFSET, HTSTATE5_wire, index);
push_delta_fw1 (`HTSTATE6 + `CTL_OFFSET, HTSTATE6_wire, index);
push_delta_fw1 (`TT1 + `CTL_OFFSET, TT1_wire, index);
push_delta_fw1 (`TT2 + `CTL_OFFSET, TT2_wire, index);
push_delta_fw1 (`TT3 + `CTL_OFFSET, TT3_wire, index);
push_delta_fw1 (`TT4 + `CTL_OFFSET, TT4_wire, index);
push_delta_fw1 (`TT5 + `CTL_OFFSET, TT5_wire, index);
push_delta_fw1 (`TT6 + `CTL_OFFSET, TT6_wire, index);
//----------------------------------------------------------
// Stage FW2 of delta pipeline
index = delta_fw1[`NEXT_INDEX];
// Pipeline previous stage
for (i=0; i<=delta_fw1[`NEXT_INDEX]; i=i+1) begin // {
delta_fw2[i] <= delta_fw1[i];
delta_fw2[`TIME_INDEX] <= $time;
// Update Registers that may change asynchronously
// If sstep was already sent by another module,
// don't capture until the next sstep
if (complete_fw1 && !`NASTOP.sstep_early[mytnum]) begin // {
if ((complete_fw1[`ASI_INDEX]|complete_fw1[`LSU_INDEX]) & asi_rdwr_hintp)
push_delta_fw2 (`HINTP + `CTL_OFFSET,asi_updated_hintp,index);
push_delta_fw2 (`HINTP + `CTL_OFFSET,HINTP_reg,index);
if ((complete_fw1[`ASI_INDEX]|complete_fw1[`LSU_INDEX]) & asi_rdwr_softint)
push_delta_fw2 (`SOFTINT + `CTL_OFFSET,asi_updated_softint,index);
push_delta_fw2 (`SOFTINT + `CTL_OFFSET,rd_SOFTINT_reg,index);
if (complete_fw1[`IMUL_INDEX] |
complete_fw1[`IDIV_INDEX]) begin // {
if (mytid <= 3) begin // {
for (i=0; i<=31; i=i+1) begin // {
push_delta_fw2 (i,`IRF4_EXU0[(remap(i,oddwin)+irf_offset)],index);
for (i=0; i<=31; i=i+1) begin // {
push_delta_fw2 (i,`IRF4_EXU1[(remap(i,oddwin)+irf_offset)],index);
// Update FRF4 - fdivs and Imuls use W2 port
if (complete_fw1[`IMUL_INDEX] |
complete_fw1[`FDIV_INDEX] ) begin // {
// IF W1 port is also being written, ignore that address
for (i=0; i<=31; i=i+1) begin // {
if (!((i == frf_w1_skip_addr) && frf_w1_valid_even)) begin // {
frf_tmp = `FRF4_EVEN[(mytid*32)+i];
push_delta_fw2 (`FP_OFFSET + (i*2), frf_tmp[31:0], index);
if (!((i == frf_w1_skip_addr) && frf_w1_valid_odd)) begin // {
frf_tmp = `FRF4_ODD[(mytid*32)+i];
push_delta_fw2 (`FP_OFFSET + (i*2)+1,frf_tmp[31:0], index);
if (complete_fw1[`FP_INDEX] |
complete_fw1[`TLU_INDEX] |
complete_fw1[`FDIV_INDEX]) begin
push_delta_fw2 (`FSR+`CTL_OFFSET,FSR_wire,index);
push_delta_fw2 (`I_TAG_ACC+`CTL_OFFSET,itagacc_fw2,index);
push_delta_fw2 (`D_TAG_ACC+`CTL_OFFSET,dtagacc_fw2,index);
push_delta_fw2 (`DSFAR+`CTL_OFFSET,dsfar_fw2,index);
//----------------------------------------------------------
// Stage FW2 of delta pipeline - for signals that change FW+2 !!
index = delta_fw2[`NEXT_INDEX];
// Since FPRS for FPops may have been corrupted by o-o-o loads:
// If fprs_fw2 is != fprs_reg & there are loads in the pipeline
// then assume loads have already updated fprs.
// In that case, create our own fprs_reg by using the valids and
// skip_addr and copy of fprs for this op..
if (complete_fw2[`FP_INDEX] && frf_w1_valid_fw2) begin // {
// o-o-o load has changed fprs already - use dummy
if ((fprs_fw2 != FPRS_reg) && (complete_fw1[`LSU_INDEX] |
complete_fw[`LSU_INDEX] | complete_fb[`LSU_INDEX] |
complete_fx5[`LSU_INDEX] )) begin // {
dummy_fprs = read_prev(`FPRS + `CTL_OFFSET);
dummy_fprs = dummy_fprs |
{1'b0, frf_w1_skip_addr4_fw2, ~frf_w1_skip_addr4_fw2};
push_delta_fw2_async (`FPRS + `CTL_OFFSET,dummy_fprs,index);
// o-o-o load has NOT changed fprs already - use it
push_delta_fw2_async (`FPRS + `CTL_OFFSET,FPRS_reg,index);
// Load FPRS for loads/reads as prev|fprs_fb ..
// since loads may only 'set' bits, not clear ...
else if (complete_fw2[`LSU_INDEX]) begin // {
dummy_fprs = read_prev(`FPRS + `CTL_OFFSET);
dummy_fprs = dummy_fprs | fprs_fw1;
push_delta_fw2_async (`FPRS +`CTL_OFFSET,dummy_fprs,index);
// Load FPRS for store ASI or FDIV
// FDIV can update FPRS on w1 or w2,
// but the pipe is stalled behind it so no o-o-o loads.
else if ((complete_fw2[`ASI_INDEX]) ||
(complete_fw2[`FDIV_INDEX])) begin // {
push_delta_fw2_async (`FPRS + `CTL_OFFSET,FPRS_reg,index);
//----------------------------------------------------------
// Store latest values into delta
index = delta_prev[`NEXT_INDEX];
if (in_wmr & ~`SPC4.rst_wmr_protect) begin // {
push_delta_prev_async ( `PC+`CTL_OFFSET,{16'b0,pc_fw2|1},index);
push_delta_prev_async ( `PC+`CTL_OFFSET,{16'b0,pc_fw2},index);
//----------------------------------------------------------
//----------------------------------------------------------
// Compare with current state and capture if different
if (act_value != read_prev(id)) begin // { // Diff vs prev
calc_cwp(CWP_reg,id,win,type); // special case for 1st stage
write_prev(id,act_value);
delta_fx4[next] <= {type,win,id,act_value};
delta_fx4[next] <= 77'hx;
delta_fx4[`NEXT_INDEX] <= next;
if (`PARGS.axis_debug_on) begin
$display("AXIS: T%0d pc=%h id=%0d type=%0h win=%0h value=%h ts=%0d",
mytnum,PC_reg,id,type,win,act_value,$time);
if (`PARGS.axis_debug_on) begin
$display("AXIS: T%0d pc=%h id=%0d type=%0h win=%0h value=%h ts=%0d",
mytnum,PC_reg,id,type,win,act_value,$time);
//----------------------------------------------------------
// Compare with current state and capture if different
if (act_value != read_prev(id)) begin // { // Diff vs prev
calc_cwp(delta_fx4[`CWP_INDEX],id,win,type);
write_prev(id,act_value);
delta_fx5[next] <= {type,win,id,act_value};
delta_fx5[next] <= 77'hx;
delta_fx5[`NEXT_INDEX] <= next;
if (`PARGS.axis_debug_on) begin
$display("AXIS: T%0d pc=%h id=%0d type=%0h win=%0h value=%h ts=%0d",
mytnum,pc_fx4,id,type,win,act_value,$time);
calc_cwp(cwp_fx4,id,win,type);
if (`PARGS.axis_debug_on) begin
$display("AXIS: T%0d pc=%h id=%0d type=%0h win=%0h value=%h ts=%0d",
mytnum,pc_fx4,id,type,win,act_value,$time);
//----------------------------------------------------------
// Compare with current state and capture if different
if (act_value != read_prev(id)) begin // { // Diff vs prev
calc_cwp(delta_fx5[`CWP_INDEX],id,win,type);
write_prev(id,act_value);
delta_fb[next] <= {type,win,id,act_value};
delta_fb[`NEXT_INDEX] <= next;
if (`PARGS.axis_debug_on) begin
$display("AXIS: T%0d pc=%h id=%0d type=%0h win=%0h value=%h ts=%0d",
mytnum,pc_fx5,id,type,win,act_value,$time);
calc_cwp(cwp_fx5,id,win,type);
if (`PARGS.axis_debug_on) begin
$display("AXIS: T%0d pc=%h id=%0d type=%0h win=%0h value=%h ts=%0d",
mytnum,pc_fx5,id,type,win,act_value,$time);
//----------------------------------------------------------
// Compare with current state and capture if different
if (act_value != read_prev(id)) begin // { // Diff vs prev
calc_cwp(delta_fb[`CWP_INDEX],id,win,type);
write_prev(id,act_value);
delta_fw[next] <= {type,win,id,act_value};
delta_fw[`NEXT_INDEX] <= next;
if (`PARGS.axis_debug_on) begin
$display("AXIS: T%0d pc=%h id=%0d type=%0h win=%0h value=%h ts=%0d",
mytnum,pc_fb,id,type,win,act_value,$time);
calc_cwp(cwp_fb[`CWP_INDEX],id,win,type);
if (`PARGS.axis_debug_on) begin
$display("AXIS: T%0d pc=%h id=%0d type=%0h win=%0h value=%h ts=%0d",
mytnum,pc_fb,id,type,win,act_value,$time);
//----------------------------------------------------------
// Compare with current state and capture if different
if (act_value != read_prev(id)) begin // { // Diff vs prev
calc_cwp(delta_fw[`CWP_INDEX],id,win,type);
write_prev(id,act_value);
delta_fw1[next] <= {type,win,id,act_value};
delta_fw1[next] <= 77'hx;
delta_fw1[`NEXT_INDEX] <= next;
if (`PARGS.axis_debug_on) begin
$display("AXIS: T%0d pc=%h id=%0d type=%0h win=%0h value=%h ts=%0d",
mytnum,pc_fw,id,type,win,act_value,$time);
calc_cwp(cwp_fw,id,win,type);
if (`PARGS.axis_debug_on) begin
$display("AXIS: T%0d pc=%h id=%0d type=%0h win=%0h value=%h ts=%0d",
mytnum,pc_fw,id,type,win,act_value,$time);
//----------------------------------------------------------
// Compare with current state and capture if different
if (act_value != read_prev(id)) begin // { // Diff vs prev
calc_cwp(delta_fw1[`CWP_INDEX],id,win,type);
write_prev(id,act_value);
delta_fw2[next] <= {type,win,id,act_value};
delta_fw2[next] <= 77'hx;
delta_fw2[`NEXT_INDEX] <= next;
if (`PARGS.axis_debug_on) begin
$display("AXIS: T%0d pc=%h id=%0d type=%0h win=%0h value=%h ts=%0d",
mytnum,pc_fw1,id,type,win,act_value,$time);
calc_cwp(cwp_fw1,id,win,type);
if (`PARGS.axis_debug_on) begin
$display("AXIS: T%0d pc=%h id=%0d type=%0h win=%0h value=%h ts=%0d",
mytnum,pc_fw1,id,type,win,act_value,$time);
//----------------------------------------------------------
// Compare with current state and capture if different
// This is for late changing registers
// Use blocking assignments.
task push_delta_fw2_async;
if (act_value != read_prev(id)) begin // { // Diff vs prev
calc_cwp(delta_fw2[`CWP_INDEX],id,win,type);
write_prev_async(id,act_value);
delta_fw2[next] = {type,win,id,act_value};
delta_fw2[`NEXT_INDEX] = next;
if (`PARGS.axis_debug_on) begin
$display("AXIS: T%0d pc=%h id=%0d type=%0h win=%0h value=%h ts=%0d",
mytnum,pc_fw1,id,type,win,act_value,$time);
calc_cwp(cwp_fw2,id,win,type);
if (`PARGS.axis_debug_on) begin
$display("AXIS: T%0d pc=%h id=%0d type=%0h win=%0h value=%h ts=%0d",
mytnum,pc_fw1,id,type,win,act_value,$time);
//----------------------------------------------------------
// Compare with current state and capture if different
// Use blocking assignments so that push_simics will work
task push_delta_prev_async;
if (act_value != read_prev(id)) begin // { // Diff vs prev
calc_cwp(delta_prev[`CWP_INDEX],id,win,type);
write_prev_async(id,act_value);
delta_prev[next] = {type,win,id,act_value};
delta_prev[next] = 77'hx;
delta_prev[`NEXT_INDEX] = next;
if (`PARGS.axis_debug_on) begin
$display("AXIS: T%0d pc=%h id=%0d type=%0h win=%0h value=%h ts=%0d",
mytnum,pc_last,id,type,win,act_value,$time);
if (`PARGS.axis_debug_on) begin
calc_cwp(cwp_last,id,win,type);
$display("AXIS: T%0d pc=%h id=%0d type=%0h win=%0h value=%h ts=%0d",
mytnum,pc_last,id,type,win,act_value,$time);
//----------------------------------------------------------
// prev of delta pipeline
// Pipeline previous stage
for (i=0; i<=delta_fw2[`NEXT_INDEX]; i=i+1) begin // {
delta_prev[i] <= delta_fw2[i];
//----------------------------------------------------------
//----------------------------------------------------------
// Sort delta list in register ID order, then push to simics
// Or print deltas if sas check disabled ..
// Order of registers reported to simics must be:
// Global 0-7 aka prev_reg[0:7]
// Window 8-23 aka prev_reg[8:23]
// Floating 0-63 aka prev_reg[200:263]
// Control 32-143 aka prev_reg[32:143]
act_level = delta_prev[`GL_INDEX]; // GL
time_fw2 = delta_prev[`TIME_INDEX]; // Finish time
for (i=`FIRST_INDEX; i<delta_prev[`NEXT_INDEX]; i=i+1) begin // {
{type,win,regnum,value} = delta_prev[i];
if (regnum<=7) begin // {
if (`PARGS.nas_check_on) begin // {
`ACT_STATUS = $queue(`ACT_QUEUE, `PUSH_Q, mytnum, time_fw2, act_type,
act_level, regnum, value);
else if (`PARGS.show_delta_on) begin // {
`NASTOP.print_delta (mytnum,act_type,win,regnum,value);
else if (regnum<=23) begin // { %o0-%l7, %l0-%l7
if (`PARGS.nas_check_on) begin // {
`ACT_STATUS = $queue(`ACT_QUEUE, `PUSH_Q, mytnum, time_fw2, act_type,
else if (`PARGS.show_delta_on) begin // {
`NASTOP.print_delta (mytnum,act_type,win,regnum,value);
else if (regnum<=31) begin // { %i0-%i7
if (`PARGS.nas_check_on) begin // {
`ACT_STATUS = $queue(`ACT_QUEUE, `PUSH_Q, mytnum, time_fw2, act_type,
win, (regnum-16), value);
else if (`PARGS.show_delta_on) begin // {
`NASTOP.print_delta (mytnum,act_type,win,(regnum-16),value);
else if (regnum<=(64+`FP_OFFSET)) begin // {
if (`PARGS.nas_check_on) begin // {
`ACT_STATUS = $queue(`ACT_QUEUE, `PUSH_Q, mytnum, time_fw2, act_type,
(regnum-`FP_OFFSET), value);
else if (`PARGS.show_delta_on) begin // {
`NASTOP.print_delta (mytnum,act_type,win,(regnum-`FP_OFFSET),value);
else if ((regnum>=(32+`CTL_OFFSET))&(regnum<=(143+`CTL_OFFSET))) begin // {
if (`PARGS.nas_check_on) begin // {
`ACT_STATUS = $queue(`ACT_QUEUE, `PUSH_Q, mytnum, time_fw2, act_type,
(regnum-`CTL_OFFSET), value);
else if (`PARGS.show_delta_on) begin // {
`NASTOP.print_delta (mytnum,act_type,win,(regnum-`CTL_OFFSET),value);
`PR_ERROR ("nas", `ERROR, " - T%0d Bench problem. push_simics has bad regnum", mytnum);
value = delta_prev[`OPCODE_INDEX];
if (`PARGS.nas_check_on) begin // {
`ACT_STATUS = $queue(`ACT_QUEUE, `PUSH_Q, mytnum, time_fw2, act_type,
else if (`PARGS.show_delta_on) begin // {
`NASTOP.print_delta (mytnum,act_type,win,regnum,value);
// Push End of Instruction Delimiter
// The value field for this PUSH equals the PC for this instruction.
// so that printing to the logfile works correctly.
// prev_reg[`PC] = current instruction PC
// delta_reg[`PC] = PC at end of current instruction
pc = delta_prev[`PC_INDEX];
if (`PARGS.nas_check_on) begin // {
`ACT_STATUS = $queue(`ACT_QUEUE, `PUSH_Q, mytnum, time_fw2, act_type,
delta_fw2[`CWP_INDEX], `END_INSTR, pc);
else if (`PARGS.show_delta_on) begin // {
`NASTOP.print_delta (mytnum,act_type,delta_fw2[`CWP_INDEX],`END_INSTR,0);
if (! `PARGS.nas_check_on) begin // {
`PR_NORMAL ("nas", `NORMAL, "@%0d T%0d %h (Unchecked..)",
$time, mytnum, {16'b0,pc});
`TOP.last_act_cycle = `TOP.core_cycle_cnt; //$time;
`TOP.th_last_act_cycle[mytnum] = `TOP.last_act_cycle;
if (! `PARGS.nas_check_on) begin // {
`TOP.last_act_cycle = `TOP.core_cycle_cnt; //$time;
`TOP.th_last_act_cycle[mytnum] = `TOP.last_act_cycle;
//----------------------------------------------------------
// Save current window to previous window, then copy new window to current window
// Save current window to Old window
// Copy New window to current window
//----------------------------------------------------------
// Save current global to previous global, then copy new global to current global
// Save current global to Old global
// Copy New global current global
//----------------------------------------------------------
// Return window number and register type based on cwp and regnum as input
else if (id<=23) begin // {
else if (id<=31) begin // {
else if (id<=(64+`FP_OFFSET)) begin // {
//----------------------------------------------------------
// Check for bad signal values
8'b10000000: ; // good value
`PR_ERROR ("nas", `ERROR, " - T%0d More than one instruction retired in a single cycle for this thread.",
$write("\t\t\t\t Instructions - ");
if (complete_fw2[`EXU_INDEX]) $write("EXU op, ");
if (complete_fw2[`FP_INDEX]) $write("FP op, ");
if (complete_fw2[`LSU_INDEX]) $write("LSU op, ");
if (complete_fw2[`IMUL_INDEX]) $write("IMUL op, ");
if (complete_fw2[`IDIV_INDEX]) $write("IDIV op, ");
if (complete_fw2[`FDIV_INDEX]) $write("FDIV op, ");
if (complete_fw2[`TLU_INDEX]) $write("TLU op, ");
if (complete_fw2[`ASI_INDEX]) $write("ASI op, ");
$write(" complete_fw2 = %b \n",complete_fw2);
// This check only works if diags are written properly.
// For example, if a diag writes to one of these registers using wrpr,
// then this check must be disabled using plusarg.
// CANSAVE + CANRESTORE + OTHERWIN = NWINDOWS-2 (per Sparc V9)
if (`PARGS.win_check_on) begin // {
if (complete_fw2 & ((CANSAVE_reg + CANRESTORE_reg + OTHERWIN_reg) != 6)) begin // {
`PR_ERROR ("nas", `ERROR, "ERROR - T%0d Bad Values for window registers.", mytnum);
`PR_ERROR ("nas", `ERROR, "- CANSAVE = %0d CANRESTORE = %0d OTHERWIN = %0d",
CANSAVE_reg, CANRESTORE_reg,OTHERWIN_reg);
//----------------------------------------------------------
//----------------------------------------------------------
reg [`DELTA_WIDTH:0] temp1, temp2;
last = delta_prev[`NEXT_INDEX]-1;
for (i=`FIRST_INDEX; i <= last; i=i+1) begin // {
for (j=`FIRST_INDEX; j < last; j=j+1) begin // {
temp1 = delta_prev[j]; temp2 = delta_prev[j+1];
if (temp1[76:64] > temp2[76:64]) begin // {
delta_prev[j] = temp2; delta_prev [j+1] = temp1;
//----------------------------------------------------------
//----------------------------------------------------------
// Print one entry in delta_* array
input [`DELTA_WIDTH:0] delta_entry;
reg [(20*8)-1:0] type_str;
reg [(20*8)-1:0] regname;
{type,win,id,act_value} = delta_entry;
`NASTOP.get_regname(mytnum,type_str,win,id,regname);
`PR_NORMAL ("nas", `NORMAL, "type=%0s win=%0d RegID=%0d %0s=%h",
type_str,win,id,regname,act_value);
//----------------------------------------------------------
// Write Value to prev_reg using id as index (non-blocking)
8'd0: prev_reg0 <= value;
8'd1: prev_reg1 <= value;
8'd2: prev_reg2 <= value;
8'd3: prev_reg3 <= value;
8'd4: prev_reg4 <= value;
8'd5: prev_reg5 <= value;
8'd6: prev_reg6 <= value;
8'd7: prev_reg7 <= value;
8'd8: prev_reg8 <= value;
8'd9: prev_reg9 <= value;
8'd10: prev_reg10 <= value;
8'd11: prev_reg11 <= value;
8'd12: prev_reg12 <= value;
8'd13: prev_reg13 <= value;
8'd14: prev_reg14 <= value;
8'd15: prev_reg15 <= value;
8'd16: prev_reg16 <= value;
8'd17: prev_reg17 <= value;
8'd18: prev_reg18 <= value;
8'd19: prev_reg19 <= value;
8'd20: prev_reg20 <= value;
8'd21: prev_reg21 <= value;
8'd22: prev_reg22 <= value;
8'd23: prev_reg23 <= value;
8'd24: prev_reg24 <= value;
8'd25: prev_reg25 <= value;
8'd26: prev_reg26 <= value;
8'd27: prev_reg27 <= value;
8'd28: prev_reg28 <= value;
8'd29: prev_reg29 <= value;
8'd30: prev_reg30 <= value;
8'd31: prev_reg31 <= value;
8'd32: prev_reg32 <= value;
8'd33: prev_reg33 <= value;
8'd34: prev_reg34 <= value;
8'd35: prev_reg35 <= value;
8'd36: prev_reg36 <= value;
8'd37: prev_reg37 <= value;
8'd38: prev_reg38 <= value;
8'd39: prev_reg39 <= value;
8'd40: prev_reg40 <= value;
8'd41: prev_reg41 <= value;
8'd42: prev_reg42 <= value;
8'd43: prev_reg43 <= value;
8'd44: prev_reg44 <= value;
8'd45: prev_reg45 <= value;
8'd46: prev_reg46 <= value;
8'd47: prev_reg47 <= value;
8'd48: prev_reg48 <= value;
8'd49: prev_reg49 <= value;
8'd50: prev_reg50 <= value;
8'd51: prev_reg51 <= value;
8'd52: prev_reg52 <= value;
8'd53: prev_reg53 <= value;
8'd54: prev_reg54 <= value;
8'd55: prev_reg55 <= value;
8'd56: prev_reg56 <= value;
8'd57: prev_reg57 <= value;
8'd58: prev_reg58 <= value;
8'd59: prev_reg59 <= value;
8'd60: prev_reg60 <= value;
8'd61: prev_reg61 <= value;
8'd62: prev_reg62 <= value;
8'd63: prev_reg63 <= value;
8'd64: prev_reg64 <= value;
8'd65: prev_reg65 <= value;
8'd66: prev_reg66 <= value;
8'd67: prev_reg67 <= value;
8'd68: prev_reg68 <= value;
8'd69: prev_reg69 <= value;
8'd70: prev_reg70 <= value;
8'd71: prev_reg71 <= value;
8'd72: prev_reg72 <= value;
8'd73: prev_reg73 <= value;
8'd74: prev_reg74 <= value;
8'd75: prev_reg75 <= value;
8'd76: prev_reg76 <= value;
8'd77: prev_reg77 <= value;
8'd78: prev_reg78 <= value;
8'd79: prev_reg79 <= value;
8'd80: prev_reg80 <= value;
8'd81: prev_reg81 <= value;
8'd82: prev_reg82 <= value;
8'd83: prev_reg83 <= value;
8'd84: prev_reg84 <= value;
8'd85: prev_reg85 <= value;
8'd86: prev_reg86 <= value;
8'd87: prev_reg87 <= value;
8'd88: prev_reg88 <= value;
8'd89: prev_reg89 <= value;
8'd90: prev_reg90 <= value;
8'd91: prev_reg91 <= value;
8'd92: prev_reg92 <= value;
8'd93: prev_reg93 <= value;
8'd94: prev_reg94 <= value;
8'd95: prev_reg95 <= value;
8'd96: prev_reg96 <= value;
8'd97: prev_reg97 <= value;
8'd98: prev_reg98 <= value;
8'd99: prev_reg99 <= value;
8'd100: prev_reg100 <= value;
8'd101: prev_reg101 <= value;
8'd102: prev_reg102 <= value;
8'd103: prev_reg103 <= value;
8'd104: prev_reg104 <= value;
8'd105: prev_reg105 <= value;
8'd106: prev_reg106 <= value;
8'd107: prev_reg107 <= value;
8'd108: prev_reg108 <= value;
8'd109: prev_reg109 <= value;
8'd110: prev_reg110 <= value;
8'd111: prev_reg111 <= value;
8'd112: prev_reg112 <= value;
8'd113: prev_reg113 <= value;
8'd114: prev_reg114 <= value;
8'd115: prev_reg115 <= value;
8'd116: prev_reg116 <= value;
8'd117: prev_reg117 <= value;
8'd118: prev_reg118 <= value;
8'd119: prev_reg119 <= value;
8'd120: prev_reg120 <= value;
8'd121: prev_reg121 <= value;
8'd122: prev_reg122 <= value;
8'd123: prev_reg123 <= value;
8'd124: prev_reg124 <= value;
8'd125: prev_reg125 <= value;
8'd126: prev_reg126 <= value;
8'd127: prev_reg127 <= value;
8'd128: prev_reg128 <= value;
8'd129: prev_reg129 <= value;
8'd130: prev_reg130 <= value;
8'd131: prev_reg131 <= value;
8'd132: prev_reg132 <= value;
8'd133: prev_reg133 <= value;
8'd134: prev_reg134 <= value;
8'd135: prev_reg135 <= value;
8'd136: prev_reg136 <= value;
8'd137: prev_reg137 <= value;
8'd138: prev_reg138 <= value;
8'd139: prev_reg139 <= value;
8'd140: prev_reg140 <= value;
8'd141: prev_reg141 <= value;
8'd142: prev_reg142 <= value;
8'd143: prev_reg143 <= value;
8'd144: prev_reg144 <= value;
8'd145: prev_reg145 <= value;
8'd146: prev_reg146 <= value;
8'd147: prev_reg147 <= value;
8'd148: prev_reg148 <= value;
8'd149: prev_reg149 <= value;
8'd150: prev_reg150 <= value;
8'd151: prev_reg151 <= value;
8'd152: prev_reg152 <= value;
8'd153: prev_reg153 <= value;
8'd154: prev_reg154 <= value;
8'd155: prev_reg155 <= value;
8'd156: prev_reg156 <= value;
8'd157: prev_reg157 <= value;
8'd158: prev_reg158 <= value;
8'd159: prev_reg159 <= value;
8'd160: prev_reg160 <= value;
8'd161: prev_reg161 <= value;
8'd162: prev_reg162 <= value;
8'd163: prev_reg163 <= value;
8'd164: prev_reg164 <= value;
8'd165: prev_reg165 <= value;
8'd166: prev_reg166 <= value;
8'd167: prev_reg167 <= value;
8'd168: prev_reg168 <= value;
8'd169: prev_reg169 <= value;
8'd170: prev_reg170 <= value;
8'd171: prev_reg171 <= value;
8'd172: prev_reg172 <= value;
8'd173: prev_reg173 <= value;
8'd174: prev_reg174 <= value;
8'd175: prev_reg175 <= value;
8'd176: prev_reg176 <= value;
8'd177: prev_reg177 <= value;
8'd178: prev_reg178 <= value;
8'd179: prev_reg179 <= value;
8'd180: prev_reg180 <= value;
8'd181: prev_reg181 <= value;
8'd182: prev_reg182 <= value;
8'd183: prev_reg183 <= value;
8'd184: prev_reg184 <= value;
8'd185: prev_reg185 <= value;
8'd186: prev_reg186 <= value;
8'd187: prev_reg187 <= value;
8'd188: prev_reg188 <= value;
8'd189: prev_reg189 <= value;
8'd190: prev_reg190 <= value;
8'd191: prev_reg191 <= value;
8'd192: prev_reg192 <= value;
8'd193: prev_reg193 <= value;
8'd194: prev_reg194 <= value;
8'd195: prev_reg195 <= value;
8'd196: prev_reg196 <= value;
8'd197: prev_reg197 <= value;
8'd198: prev_reg198 <= value;
8'd199: prev_reg199 <= value;
8'd200: prev_reg200 <= value;
8'd201: prev_reg201 <= value;
8'd202: prev_reg202 <= value;
8'd203: prev_reg203 <= value;
8'd204: prev_reg204 <= value;
8'd205: prev_reg205 <= value;
8'd206: prev_reg206 <= value;
8'd207: prev_reg207 <= value;
8'd208: prev_reg208 <= value;
8'd209: prev_reg209 <= value;
8'd210: prev_reg210 <= value;
8'd211: prev_reg211 <= value;
8'd212: prev_reg212 <= value;
8'd213: prev_reg213 <= value;
8'd214: prev_reg214 <= value;
8'd215: prev_reg215 <= value;
8'd216: prev_reg216 <= value;
8'd217: prev_reg217 <= value;
8'd218: prev_reg218 <= value;
8'd219: prev_reg219 <= value;
8'd220: prev_reg220 <= value;
8'd221: prev_reg221 <= value;
8'd222: prev_reg222 <= value;
8'd223: prev_reg223 <= value;
8'd224: prev_reg224 <= value;
8'd225: prev_reg225 <= value;
8'd226: prev_reg226 <= value;
8'd227: prev_reg227 <= value;
8'd228: prev_reg228 <= value;
8'd229: prev_reg229 <= value;
8'd230: prev_reg230 <= value;
8'd231: prev_reg231 <= value;
8'd232: prev_reg232 <= value;
8'd233: prev_reg233 <= value;
8'd234: prev_reg234 <= value;
8'd235: prev_reg235 <= value;
8'd236: prev_reg236 <= value;
8'd237: prev_reg237 <= value;
8'd238: prev_reg238 <= value;
8'd239: prev_reg239 <= value;
8'd240: prev_reg240 <= value;
8'd241: prev_reg241 <= value;
8'd242: prev_reg242 <= value;
8'd243: prev_reg243 <= value;
8'd244: prev_reg244 <= value;
8'd245: prev_reg245 <= value;
8'd246: prev_reg246 <= value;
8'd247: prev_reg247 <= value;
8'd248: prev_reg248 <= value;
8'd249: prev_reg249 <= value;
8'd250: prev_reg250 <= value;
8'd251: prev_reg251 <= value;
8'd252: prev_reg252 <= value;
8'd253: prev_reg253 <= value;
8'd254: prev_reg254 <= value;
8'd255: prev_reg255 <= value;
//----------------------------------------------------------
// Write Value to prev_reg using id as index (blocking)
8'd10: prev_reg10 = value;
8'd11: prev_reg11 = value;
8'd12: prev_reg12 = value;
8'd13: prev_reg13 = value;
8'd14: prev_reg14 = value;
8'd15: prev_reg15 = value;
8'd16: prev_reg16 = value;
8'd17: prev_reg17 = value;
8'd18: prev_reg18 = value;
8'd19: prev_reg19 = value;
8'd20: prev_reg20 = value;
8'd21: prev_reg21 = value;
8'd22: prev_reg22 = value;
8'd23: prev_reg23 = value;
8'd24: prev_reg24 = value;
8'd25: prev_reg25 = value;
8'd26: prev_reg26 = value;
8'd27: prev_reg27 = value;
8'd28: prev_reg28 = value;
8'd29: prev_reg29 = value;
8'd30: prev_reg30 = value;
8'd31: prev_reg31 = value;
8'd32: prev_reg32 = value;
8'd33: prev_reg33 = value;
8'd34: prev_reg34 = value;
8'd35: prev_reg35 = value;
8'd36: prev_reg36 = value;
8'd37: prev_reg37 = value;
8'd38: prev_reg38 = value;
8'd39: prev_reg39 = value;
8'd40: prev_reg40 = value;
8'd41: prev_reg41 = value;
8'd42: prev_reg42 = value;
8'd43: prev_reg43 = value;
8'd44: prev_reg44 = value;
8'd45: prev_reg45 = value;
8'd46: prev_reg46 = value;
8'd47: prev_reg47 = value;
8'd48: prev_reg48 = value;
8'd49: prev_reg49 = value;
8'd50: prev_reg50 = value;
8'd51: prev_reg51 = value;
8'd52: prev_reg52 = value;
8'd53: prev_reg53 = value;
8'd54: prev_reg54 = value;
8'd55: prev_reg55 = value;
8'd56: prev_reg56 = value;
8'd57: prev_reg57 = value;
8'd58: prev_reg58 = value;
8'd59: prev_reg59 = value;
8'd60: prev_reg60 = value;
8'd61: prev_reg61 = value;
8'd62: prev_reg62 = value;
8'd63: prev_reg63 = value;
8'd64: prev_reg64 = value;
8'd65: prev_reg65 = value;
8'd66: prev_reg66 = value;
8'd67: prev_reg67 = value;
8'd68: prev_reg68 = value;
8'd69: prev_reg69 = value;
8'd70: prev_reg70 = value;
8'd71: prev_reg71 = value;
8'd72: prev_reg72 = value;
8'd73: prev_reg73 = value;
8'd74: prev_reg74 = value;
8'd75: prev_reg75 = value;
8'd76: prev_reg76 = value;
8'd77: prev_reg77 = value;
8'd78: prev_reg78 = value;
8'd79: prev_reg79 = value;
8'd80: prev_reg80 = value;
8'd81: prev_reg81 = value;
8'd82: prev_reg82 = value;
8'd83: prev_reg83 = value;
8'd84: prev_reg84 = value;
8'd85: prev_reg85 = value;
8'd86: prev_reg86 = value;
8'd87: prev_reg87 = value;
8'd88: prev_reg88 = value;
8'd89: prev_reg89 = value;
8'd90: prev_reg90 = value;
8'd91: prev_reg91 = value;
8'd92: prev_reg92 = value;
8'd93: prev_reg93 = value;
8'd94: prev_reg94 = value;
8'd95: prev_reg95 = value;
8'd96: prev_reg96 = value;
8'd97: prev_reg97 = value;
8'd98: prev_reg98 = value;
8'd99: prev_reg99 = value;
8'd100: prev_reg100 = value;
8'd101: prev_reg101 = value;
8'd102: prev_reg102 = value;
8'd103: prev_reg103 = value;
8'd104: prev_reg104 = value;
8'd105: prev_reg105 = value;
8'd106: prev_reg106 = value;
8'd107: prev_reg107 = value;
8'd108: prev_reg108 = value;
8'd109: prev_reg109 = value;
8'd110: prev_reg110 = value;
8'd111: prev_reg111 = value;
8'd112: prev_reg112 = value;
8'd113: prev_reg113 = value;
8'd114: prev_reg114 = value;
8'd115: prev_reg115 = value;
8'd116: prev_reg116 = value;
8'd117: prev_reg117 = value;
8'd118: prev_reg118 = value;
8'd119: prev_reg119 = value;
8'd120: prev_reg120 = value;
8'd121: prev_reg121 = value;
8'd122: prev_reg122 = value;
8'd123: prev_reg123 = value;
8'd124: prev_reg124 = value;
8'd125: prev_reg125 = value;
8'd126: prev_reg126 = value;
8'd127: prev_reg127 = value;
8'd128: prev_reg128 = value;
8'd129: prev_reg129 = value;
8'd130: prev_reg130 = value;
8'd131: prev_reg131 = value;
8'd132: prev_reg132 = value;
8'd133: prev_reg133 = value;
8'd134: prev_reg134 = value;
8'd135: prev_reg135 = value;
8'd136: prev_reg136 = value;
8'd137: prev_reg137 = value;
8'd138: prev_reg138 = value;
8'd139: prev_reg139 = value;
8'd140: prev_reg140 = value;
8'd141: prev_reg141 = value;
8'd142: prev_reg142 = value;
8'd143: prev_reg143 = value;
8'd144: prev_reg144 = value;
8'd145: prev_reg145 = value;
8'd146: prev_reg146 = value;
8'd147: prev_reg147 = value;
8'd148: prev_reg148 = value;
8'd149: prev_reg149 = value;
8'd150: prev_reg150 = value;
8'd151: prev_reg151 = value;
8'd152: prev_reg152 = value;
8'd153: prev_reg153 = value;
8'd154: prev_reg154 = value;
8'd155: prev_reg155 = value;
8'd156: prev_reg156 = value;
8'd157: prev_reg157 = value;
8'd158: prev_reg158 = value;
8'd159: prev_reg159 = value;
8'd160: prev_reg160 = value;
8'd161: prev_reg161 = value;
8'd162: prev_reg162 = value;
8'd163: prev_reg163 = value;
8'd164: prev_reg164 = value;
8'd165: prev_reg165 = value;
8'd166: prev_reg166 = value;
8'd167: prev_reg167 = value;
8'd168: prev_reg168 = value;
8'd169: prev_reg169 = value;
8'd170: prev_reg170 = value;
8'd171: prev_reg171 = value;
8'd172: prev_reg172 = value;
8'd173: prev_reg173 = value;
8'd174: prev_reg174 = value;
8'd175: prev_reg175 = value;
8'd176: prev_reg176 = value;
8'd177: prev_reg177 = value;
8'd178: prev_reg178 = value;
8'd179: prev_reg179 = value;
8'd180: prev_reg180 = value;
8'd181: prev_reg181 = value;
8'd182: prev_reg182 = value;
8'd183: prev_reg183 = value;
8'd184: prev_reg184 = value;
8'd185: prev_reg185 = value;
8'd186: prev_reg186 = value;
8'd187: prev_reg187 = value;
8'd188: prev_reg188 = value;
8'd189: prev_reg189 = value;
8'd190: prev_reg190 = value;
8'd191: prev_reg191 = value;
8'd192: prev_reg192 = value;
8'd193: prev_reg193 = value;
8'd194: prev_reg194 = value;
8'd195: prev_reg195 = value;
8'd196: prev_reg196 = value;
8'd197: prev_reg197 = value;
8'd198: prev_reg198 = value;
8'd199: prev_reg199 = value;
8'd200: prev_reg200 = value;
8'd201: prev_reg201 = value;
8'd202: prev_reg202 = value;
8'd203: prev_reg203 = value;
8'd204: prev_reg204 = value;
8'd205: prev_reg205 = value;
8'd206: prev_reg206 = value;
8'd207: prev_reg207 = value;
8'd208: prev_reg208 = value;
8'd209: prev_reg209 = value;
8'd210: prev_reg210 = value;
8'd211: prev_reg211 = value;
8'd212: prev_reg212 = value;
8'd213: prev_reg213 = value;
8'd214: prev_reg214 = value;
8'd215: prev_reg215 = value;
8'd216: prev_reg216 = value;
8'd217: prev_reg217 = value;
8'd218: prev_reg218 = value;
8'd219: prev_reg219 = value;
8'd220: prev_reg220 = value;
8'd221: prev_reg221 = value;
8'd222: prev_reg222 = value;
8'd223: prev_reg223 = value;
8'd224: prev_reg224 = value;
8'd225: prev_reg225 = value;
8'd226: prev_reg226 = value;
8'd227: prev_reg227 = value;
8'd228: prev_reg228 = value;
8'd229: prev_reg229 = value;
8'd230: prev_reg230 = value;
8'd231: prev_reg231 = value;
8'd232: prev_reg232 = value;
8'd233: prev_reg233 = value;
8'd234: prev_reg234 = value;
8'd235: prev_reg235 = value;
8'd236: prev_reg236 = value;
8'd237: prev_reg237 = value;
8'd238: prev_reg238 = value;
8'd239: prev_reg239 = value;
8'd240: prev_reg240 = value;
8'd241: prev_reg241 = value;
8'd242: prev_reg242 = value;
8'd243: prev_reg243 = value;
8'd244: prev_reg244 = value;
8'd245: prev_reg245 = value;
8'd246: prev_reg246 = value;
8'd247: prev_reg247 = value;
8'd248: prev_reg248 = value;
8'd249: prev_reg249 = value;
8'd250: prev_reg250 = value;
8'd251: prev_reg251 = value;
8'd252: prev_reg252 = value;
8'd253: prev_reg253 = value;
8'd254: prev_reg254 = value;
8'd255: prev_reg255 = value;
//----------------------------------------------------------
// Read value frpm prev_reg using id as index
function [63:0] read_prev;
8'd0: read_prev = prev_reg0;
8'd1: read_prev = prev_reg1;
8'd2: read_prev = prev_reg2;
8'd3: read_prev = prev_reg3;
8'd4: read_prev = prev_reg4;
8'd5: read_prev = prev_reg5;
8'd6: read_prev = prev_reg6;
8'd7: read_prev = prev_reg7;
8'd8: read_prev = prev_reg8;
8'd9: read_prev = prev_reg9;
8'd10: read_prev = prev_reg10;
8'd11: read_prev = prev_reg11;
8'd12: read_prev = prev_reg12;
8'd13: read_prev = prev_reg13;
8'd14: read_prev = prev_reg14;
8'd15: read_prev = prev_reg15;
8'd16: read_prev = prev_reg16;
8'd17: read_prev = prev_reg17;
8'd18: read_prev = prev_reg18;
8'd19: read_prev = prev_reg19;
8'd20: read_prev = prev_reg20;
8'd21: read_prev = prev_reg21;
8'd22: read_prev = prev_reg22;
8'd23: read_prev = prev_reg23;
8'd24: read_prev = prev_reg24;
8'd25: read_prev = prev_reg25;
8'd26: read_prev = prev_reg26;
8'd27: read_prev = prev_reg27;
8'd28: read_prev = prev_reg28;
8'd29: read_prev = prev_reg29;
8'd30: read_prev = prev_reg30;
8'd31: read_prev = prev_reg31;
8'd32: read_prev = prev_reg32;
8'd33: read_prev = prev_reg33;
8'd34: read_prev = prev_reg34;
8'd35: read_prev = prev_reg35;
8'd36: read_prev = prev_reg36;
8'd37: read_prev = prev_reg37;
8'd38: read_prev = prev_reg38;
8'd39: read_prev = prev_reg39;
8'd40: read_prev = prev_reg40;
8'd41: read_prev = prev_reg41;
8'd42: read_prev = prev_reg42;
8'd43: read_prev = prev_reg43;
8'd44: read_prev = prev_reg44;
8'd45: read_prev = prev_reg45;
8'd46: read_prev = prev_reg46;
8'd47: read_prev = prev_reg47;
8'd48: read_prev = prev_reg48;
8'd49: read_prev = prev_reg49;
8'd50: read_prev = prev_reg50;
8'd51: read_prev = prev_reg51;
8'd52: read_prev = prev_reg52;
8'd53: read_prev = prev_reg53;
8'd54: read_prev = prev_reg54;
8'd55: read_prev = prev_reg55;
8'd56: read_prev = prev_reg56;
8'd57: read_prev = prev_reg57;
8'd58: read_prev = prev_reg58;
8'd59: read_prev = prev_reg59;
8'd60: read_prev = prev_reg60;
8'd61: read_prev = prev_reg61;
8'd62: read_prev = prev_reg62;
8'd63: read_prev = prev_reg63;
8'd64: read_prev = prev_reg64;
8'd65: read_prev = prev_reg65;
8'd66: read_prev = prev_reg66;
8'd67: read_prev = prev_reg67;
8'd68: read_prev = prev_reg68;
8'd69: read_prev = prev_reg69;
8'd70: read_prev = prev_reg70;
8'd71: read_prev = prev_reg71;
8'd72: read_prev = prev_reg72;
8'd73: read_prev = prev_reg73;
8'd74: read_prev = prev_reg74;
8'd75: read_prev = prev_reg75;
8'd76: read_prev = prev_reg76;
8'd77: read_prev = prev_reg77;
8'd78: read_prev = prev_reg78;
8'd79: read_prev = prev_reg79;
8'd80: read_prev = prev_reg80;
8'd81: read_prev = prev_reg81;
8'd82: read_prev = prev_reg82;
8'd83: read_prev = prev_reg83;
8'd84: read_prev = prev_reg84;
8'd85: read_prev = prev_reg85;
8'd86: read_prev = prev_reg86;
8'd87: read_prev = prev_reg87;
8'd88: read_prev = prev_reg88;
8'd89: read_prev = prev_reg89;
8'd90: read_prev = prev_reg90;
8'd91: read_prev = prev_reg91;
8'd92: read_prev = prev_reg92;
8'd93: read_prev = prev_reg93;
8'd94: read_prev = prev_reg94;
8'd95: read_prev = prev_reg95;
8'd96: read_prev = prev_reg96;
8'd97: read_prev = prev_reg97;
8'd98: read_prev = prev_reg98;
8'd99: read_prev = prev_reg99;
8'd100: read_prev = prev_reg100;
8'd101: read_prev = prev_reg101;
8'd102: read_prev = prev_reg102;
8'd103: read_prev = prev_reg103;
8'd104: read_prev = prev_reg104;
8'd105: read_prev = prev_reg105;
8'd106: read_prev = prev_reg106;
8'd107: read_prev = prev_reg107;
8'd108: read_prev = prev_reg108;
8'd109: read_prev = prev_reg109;
8'd110: read_prev = prev_reg110;
8'd111: read_prev = prev_reg111;
8'd112: read_prev = prev_reg112;
8'd113: read_prev = prev_reg113;
8'd114: read_prev = prev_reg114;
8'd115: read_prev = prev_reg115;
8'd116: read_prev = prev_reg116;
8'd117: read_prev = prev_reg117;
8'd118: read_prev = prev_reg118;
8'd119: read_prev = prev_reg119;
8'd120: read_prev = prev_reg120;
8'd121: read_prev = prev_reg121;
8'd122: read_prev = prev_reg122;
8'd123: read_prev = prev_reg123;
8'd124: read_prev = prev_reg124;
8'd125: read_prev = prev_reg125;
8'd126: read_prev = prev_reg126;
8'd127: read_prev = prev_reg127;
8'd128: read_prev = prev_reg128;
8'd129: read_prev = prev_reg129;
8'd130: read_prev = prev_reg130;
8'd131: read_prev = prev_reg131;
8'd132: read_prev = prev_reg132;
8'd133: read_prev = prev_reg133;
8'd134: read_prev = prev_reg134;
8'd135: read_prev = prev_reg135;
8'd136: read_prev = prev_reg136;
8'd137: read_prev = prev_reg137;
8'd138: read_prev = prev_reg138;
8'd139: read_prev = prev_reg139;
8'd140: read_prev = prev_reg140;
8'd141: read_prev = prev_reg141;
8'd142: read_prev = prev_reg142;
8'd143: read_prev = prev_reg143;
8'd144: read_prev = prev_reg144;
8'd145: read_prev = prev_reg145;
8'd146: read_prev = prev_reg146;
8'd147: read_prev = prev_reg147;
8'd148: read_prev = prev_reg148;
8'd149: read_prev = prev_reg149;
8'd150: read_prev = prev_reg150;
8'd151: read_prev = prev_reg151;
8'd152: read_prev = prev_reg152;
8'd153: read_prev = prev_reg153;
8'd154: read_prev = prev_reg154;
8'd155: read_prev = prev_reg155;
8'd156: read_prev = prev_reg156;
8'd157: read_prev = prev_reg157;
8'd158: read_prev = prev_reg158;
8'd159: read_prev = prev_reg159;
8'd160: read_prev = prev_reg160;
8'd161: read_prev = prev_reg161;
8'd162: read_prev = prev_reg162;
8'd163: read_prev = prev_reg163;
8'd164: read_prev = prev_reg164;
8'd165: read_prev = prev_reg165;
8'd166: read_prev = prev_reg166;
8'd167: read_prev = prev_reg167;
8'd168: read_prev = prev_reg168;
8'd169: read_prev = prev_reg169;
8'd170: read_prev = prev_reg170;
8'd171: read_prev = prev_reg171;
8'd172: read_prev = prev_reg172;
8'd173: read_prev = prev_reg173;
8'd174: read_prev = prev_reg174;
8'd175: read_prev = prev_reg175;
8'd176: read_prev = prev_reg176;
8'd177: read_prev = prev_reg177;
8'd178: read_prev = prev_reg178;
8'd179: read_prev = prev_reg179;
8'd180: read_prev = prev_reg180;
8'd181: read_prev = prev_reg181;
8'd182: read_prev = prev_reg182;
8'd183: read_prev = prev_reg183;
8'd184: read_prev = prev_reg184;
8'd185: read_prev = prev_reg185;
8'd186: read_prev = prev_reg186;
8'd187: read_prev = prev_reg187;
8'd188: read_prev = prev_reg188;
8'd189: read_prev = prev_reg189;
8'd190: read_prev = prev_reg190;
8'd191: read_prev = prev_reg191;
8'd192: read_prev = prev_reg192;
8'd193: read_prev = prev_reg193;
8'd194: read_prev = prev_reg194;
8'd195: read_prev = prev_reg195;
8'd196: read_prev = prev_reg196;
8'd197: read_prev = prev_reg197;
8'd198: read_prev = prev_reg198;
8'd199: read_prev = prev_reg199;
8'd200: read_prev = prev_reg200;
8'd201: read_prev = prev_reg201;
8'd202: read_prev = prev_reg202;
8'd203: read_prev = prev_reg203;
8'd204: read_prev = prev_reg204;
8'd205: read_prev = prev_reg205;
8'd206: read_prev = prev_reg206;
8'd207: read_prev = prev_reg207;
8'd208: read_prev = prev_reg208;
8'd209: read_prev = prev_reg209;
8'd210: read_prev = prev_reg210;
8'd211: read_prev = prev_reg211;
8'd212: read_prev = prev_reg212;
8'd213: read_prev = prev_reg213;
8'd214: read_prev = prev_reg214;
8'd215: read_prev = prev_reg215;
8'd216: read_prev = prev_reg216;
8'd217: read_prev = prev_reg217;
8'd218: read_prev = prev_reg218;
8'd219: read_prev = prev_reg219;
8'd220: read_prev = prev_reg220;
8'd221: read_prev = prev_reg221;
8'd222: read_prev = prev_reg222;
8'd223: read_prev = prev_reg223;
8'd224: read_prev = prev_reg224;
8'd225: read_prev = prev_reg225;
8'd226: read_prev = prev_reg226;
8'd227: read_prev = prev_reg227;
8'd228: read_prev = prev_reg228;
8'd229: read_prev = prev_reg229;
8'd230: read_prev = prev_reg230;
8'd231: read_prev = prev_reg231;
8'd232: read_prev = prev_reg232;
8'd233: read_prev = prev_reg233;
8'd234: read_prev = prev_reg234;
8'd235: read_prev = prev_reg235;
8'd236: read_prev = prev_reg236;
8'd237: read_prev = prev_reg237;
8'd238: read_prev = prev_reg238;
8'd239: read_prev = prev_reg239;
8'd240: read_prev = prev_reg240;
8'd241: read_prev = prev_reg241;
8'd242: read_prev = prev_reg242;
8'd243: read_prev = prev_reg243;
8'd244: read_prev = prev_reg244;
8'd245: read_prev = prev_reg245;
8'd246: read_prev = prev_reg246;
8'd247: read_prev = prev_reg247;
8'd248: read_prev = prev_reg248;
8'd249: read_prev = prev_reg249;
8'd250: read_prev = prev_reg250;
8'd251: read_prev = prev_reg251;
8'd252: read_prev = prev_reg252;
8'd253: read_prev = prev_reg253;
8'd254: read_prev = prev_reg254;
8'd255: read_prev = prev_reg255;
//----------------------------------------------------------
remap[4] = rd[4] ^ (rd[3] & oddwin);
//----------------------------------------------------------
// Initialize nas_pipe registers
initial begin : INIT_BLOCK
nas_pipe_enable = 1'b1; // Nas_pipe always enables itself
good_trap_detected = 1'b0;
@ (posedge `BENCH_SPC4_GCLK);
`TOP.th_last_act_cycle[mytnum] = 0;
`PR_INFO ("nas", `INFO, "T%0d Init shadow registers.",mytnum);
// POR for control registers
write_prev(`FPRS +`CTL_OFFSET,3'h4);
write_prev(`CLEANWIN +`CTL_OFFSET,3'h7);
write_prev(`CANSAVE +`CTL_OFFSET,3'h6);
write_prev(`FPRS+`CTL_OFFSET,3'h4);
// POR for PSTATE = 0x14 (PEF, PRIV = 1)
write_prev(`PSTATE + `CTL_OFFSET,'h14);
// POR for HPSTATE = 0x4034 (RED, HPRIV = 1)
write_prev(`HPSTATE + `CTL_OFFSET,'h24);
// POR for TL = = 0x6 [MAXTL]
write_prev(`TL + `CTL_OFFSET,'h6);
write_prev(`TT6 + `CTL_OFFSET,'h1);
// POR for GL = MAXGL = 3
write_prev(`GL + `CTL_OFFSET,`POR_GL);
// POR for VER = {003e, 0024, 01, 0036, 07}
write_prev(`VER + `CTL_OFFSET,{32'h003e0024,VER_reg[31:24],24'h030607});
// POR for *_cmpr registers is INT_DIS = 1
write_prev(`TICK_CMPR + `CTL_OFFSET,64'h8000000000000000);
write_prev(`STICK_CMPR + `CTL_OFFSET,64'h8000000000000000);
write_prev(`HSTICK_CMPR + `CTL_OFFSET,64'h8000000000000000);
// Need to define so that 1st instruction will print correctly
write_prev(`PC+`CTL_OFFSET,`POR_PC);
delta_prev[`PC_INDEX] = `BAD_PC;
irf_offset = (mytid%4)*32;
//----------------------------------------------------------
// For WMR, we will set to 0x0, so that initial deltas
// WMR for PSTATE = 0x14 (PEF, PRIV = 1)
// write_prev(`PSTATE + `CTL_OFFSET,'h00);
// WMR for HPSTATE = 0x4034 (RED, HPRIV = 1)
// write_prev(`HPSTATE + `CTL_OFFSET,'h00);
// WMR for TL = = 0x6 [MAXTL]
// write_prev(`TL + `CTL_OFFSET,'h0);
// write_prev(`TT6 + `CTL_OFFSET,'h1);
// WMR for GL = MAXGL = 3
// write_prev(`GL + `CTL_OFFSET,0);
//----------------------------------------------------------
// For POR, we will set to 0x0, so that initial deltas
// and prev state are all consistent with DUT. No values
`PR_ALWAYS ("arg", `ALWAYS,"T%0d Resetting Nas Pipe states for POR ..",mytnum);
delta_fx4[`NEXT_INDEX] <= `FIRST_INDEX;
delta_fx4[`FIRST_INDEX] <= 77'hx;
delta_fx5[`NEXT_INDEX] <= `FIRST_INDEX;
delta_fb[`NEXT_INDEX] <= `FIRST_INDEX;
delta_fw[`NEXT_INDEX] <= `FIRST_INDEX;
delta_fw1[`NEXT_INDEX] <= `FIRST_INDEX;
delta_fw2[`NEXT_INDEX] <= `FIRST_INDEX;
`PR_INFO ("nas", `INFO, "T%0d Init shadow registers.",mytnum);
// POR for control registers
write_prev(`FPRS +`CTL_OFFSET,3'h4);
write_prev(`CLEANWIN +`CTL_OFFSET,3'h7);
write_prev(`CANSAVE +`CTL_OFFSET,3'h6);
write_prev(`FPRS+`CTL_OFFSET,3'h4);
// POR for PSTATE = 0x14 (PEF, PRIV = 1)
write_prev(`PSTATE + `CTL_OFFSET,'h14);
// POR for HPSTATE = 0x4034 (RED, HPRIV = 1)
write_prev(`HPSTATE + `CTL_OFFSET,'h24);
// POR for TL = = 0x6 [MAXTL]
write_prev(`TL + `CTL_OFFSET,'h6);
write_prev(`TT6 + `CTL_OFFSET,'h1);
// POR for GL = MAXGL = 3
write_prev(`GL + `CTL_OFFSET,`POR_GL);
// POR for VER = {003e, 0024, 01, 0036, 07}
write_prev(`VER + `CTL_OFFSET,64'h003e002410030607);
// POR for *_cmpr registers is INT_DIS = 1
write_prev(`TICK_CMPR + `CTL_OFFSET,64'h8000000000000000);
write_prev(`STICK_CMPR + `CTL_OFFSET,64'h8000000000000000);
write_prev(`HSTICK_CMPR + `CTL_OFFSET,64'h8000000000000000);
// Need to define so that 1st instruction will print correctly
write_prev(`PC+`CTL_OFFSET,`POR_PC);
//----------------------------------------------------------
//----------------------------------------------------------
// Watch for Good/Bad trap
wire [5:0] mytnum = (mycid*8)+mytid;
// Delimiter changes whether flat or hierarchical netlist
wire myclk = tb_top.cpu.spc4.gclk;
wire dec_inst_valid_m = mytg ? tb_top.cpu.spc4.dec_inst_valid_m[1] : tb_top.cpu.spc4.dec_inst_valid_m[0];
wire [1:0] dec_tid_m = mytg ? tb_top.cpu.spc4.dec_tid1_m : tb_top.cpu.spc4.dec_tid0_m;
wire dec_flush_b = mytg ? tb_top.cpu.spc4.dec_flush_b[1] : tb_top.cpu.spc4.dec_flush_b[0];
wire tlu_flush_ifu = tb_top.cpu.spc4.tlu_flush_ifu[mytid];
wire [47:0] pc_d = mytg ? {tb_top.cpu.spc4.tlu_pc_1_d[47:2],2'b0} : {tb_top.cpu.spc4.tlu_pc_0_d[47:2],2'b0};
wire [31:0] op_d = mytg ? tb_top.cpu.spc4.dec_inst1_d[31:0] : tb_top.cpu.spc4.dec_inst0_d[31:0];
wire myclk = tb_top.cpu.spc4.gclk;
wire dec_inst_valid_m = mytg ? tb_top.cpu.spc4.dec_inst_valid_m[1] : tb_top.cpu.spc4.dec_inst_valid_m[0];
wire [1:0] dec_tid_m = mytg ? tb_top.cpu.spc4.dec_tid1_m : tb_top.cpu.spc4.dec_tid0_m;
wire dec_flush_b = mytg ? tb_top.cpu.spc4.dec_flush_b[1] : tb_top.cpu.spc4.dec_flush_b[0];
wire tlu_flush_ifu = tb_top.cpu.spc4.tlu_flush_ifu[mytid];
wire [47:0] pc_d = mytg ? {tb_top.cpu.spc4.tlu_pc_1_d[47:2],2'b0} : {tb_top.cpu.spc4.tlu_pc_0_d[47:2],2'b0};
wire [31:0] op_d = mytg ? tb_top.cpu.spc4.dec_inst1_d[31:0] : tb_top.cpu.spc4.dec_inst0_d[31:0];
wire inst_valid_b = dec_inst_valid_b && (dec_tid_b==mytid[1:0]) && !(dec_flush_b || tlu_flush_ifu);
always @ (posedge myclk) begin // {
dec_inst_valid_b <= dec_inst_valid_m;
inst_valid_w <= inst_valid_b;
inst_valid_fx4 <= inst_valid_w;
inst_valid_fx5 <= inst_valid_fx4;
inst_valid_fb <= inst_valid_fx5;
inst_valid_fw <= inst_valid_fb;
inst_valid_fw1 <= inst_valid_fw;
inst_valid_fw2 <= inst_valid_fw1;
if (`PARGS.th_check_enable[mytnum] && nas_pipe_enable) begin // {
if (inst_valid_fw2) begin // {
// Print PC/opcode for debugging
`PR_NORMAL ("nas", `NORMAL, "@%0d #%0d T%0d %h [%h]", $time, inst_count, mytnum, pc_fw2, op_fw2);
inst_count = inst_count + 1;
// End detection for GateSim runs
for (junk=0;junk<`PARGS.bad_trap_count;junk=junk+1) begin // {
if (({16'b0,pc_fw2}&`PC_MASK)===(`PARGS.bad_trap_addr[junk]&`PC_MASK)) begin // {
`PR_ERROR ("nas",`ERROR, "T%0d reached Bad Trap [GATESIM]", mytnum);
for (junk=0;junk<`PARGS.good_trap_count;junk=junk+1) begin // {
if (({16'b0,pc_fw2}&`PC_MASK)===(`PARGS.good_trap_addr[junk]&`PC_MASK)) begin // {
`TOP.finished_tids[mytnum] = 1'b1;
`PARGS.th_check_enable[mytnum] = 1'b0;
`PR_NORMAL ("nas", `NORMAL, "T%0d reached Good Trap. Disabling checking for thread %0d [GATESIM]", mytnum,mytnum);
//----------------------------------------------------------
//----------------------------------------------------------
//----------------------------------------------------------
input [71:0] TICK_CMPR_reg;
input [71:0] STICK_CMPR_reg;
input [71:0] HSTICK_CMPR_reg;
input [2:0] CANRESTORE_reg;
input [2:0] OTHERWIN_reg;
input [2:0] CLEANWIN_reg;
input [16:0] SOFTINT_reg;
input [16:0] rd_SOFTINT_reg;
input [63:0] INTR_RECEIVE_reg;
input [12:0] HPSTATE_reg;
input [63:0] CTXT_PRIM_0_reg;
input [63:0] CTXT_SEC_0_reg;
input [63:0] CTXT_PRIM_1_reg;
input [63:0] CTXT_SEC_1_reg;
input [63:0] LSU_CONTROL_reg;
input [63:0] I_TAG_ACC_reg;
input [63:0] D_TAG_ACC_reg;
input [63:0] WATCHPOINT_ADDR_reg;
input [151:0] Trap_Entry_1;
input [151:0] Trap_Entry_2;
input [151:0] Trap_Entry_3;
input [151:0] Trap_Entry_4;
input [151:0] Trap_Entry_5;
input [151:0] Trap_Entry_6;
input [1:0] frf_w2_valid;
input [1:0] frf_w1_valid;
input asi_valid; // ASI/ASR/PR writes done ..
input asi_in_progress; // ASI/ASR/PR in progess
//----------------------------------------------------------
//----------------------------------------------------------
//----------------------------------------------------------
// delta_* = {type(2bits),win(3bits),regnum(8bits),value(64bits)}
reg [`DELTA_WIDTH:0] delta_fx4 [0:(`MAX_INDEX)];
reg [`DELTA_WIDTH:0] delta_fx5 [0:(`MAX_INDEX)];
reg [`DELTA_WIDTH:0] delta_fb [0:(`MAX_INDEX)];
reg [`DELTA_WIDTH:0] delta_fw [0:(`MAX_INDEX)];
reg [`DELTA_WIDTH:0] delta_fw1 [0:(`MAX_INDEX)];
reg [`DELTA_WIDTH:0] delta_fw2 [0:(`MAX_INDEX)];
reg [`DELTA_WIDTH:0] delta_prev [0:(`MAX_INDEX)];
// need to change in several places in this file
reg [63:0] prev_reg0; // includes G,W,C,F registers
reg [63:0] prev_reg1; // includes G,W,C,F registers
reg [63:0] prev_reg2; // includes G,W,C,F registers
reg [63:0] prev_reg3; // includes G,W,C,F registers
reg [63:0] prev_reg4; // includes G,W,C,F registers
reg [63:0] prev_reg5; // includes G,W,C,F registers
reg [63:0] prev_reg6; // includes G,W,C,F registers
reg [63:0] prev_reg7; // includes G,W,C,F registers
reg [63:0] prev_reg8; // includes G,W,C,F registers
reg [63:0] prev_reg9; // includes G,W,C,F registers
reg [63:0] prev_reg10; // includes G,W,C,F registers
reg [63:0] prev_reg11; // includes G,W,C,F registers
reg [63:0] prev_reg12; // includes G,W,C,F registers
reg [63:0] prev_reg13; // includes G,W,C,F registers
reg [63:0] prev_reg14; // includes G,W,C,F registers
reg [63:0] prev_reg15; // includes G,W,C,F registers
reg [63:0] prev_reg16; // includes G,W,C,F registers
reg [63:0] prev_reg17; // includes G,W,C,F registers
reg [63:0] prev_reg18; // includes G,W,C,F registers
reg [63:0] prev_reg19; // includes G,W,C,F registers
reg [63:0] prev_reg20; // includes G,W,C,F registers
reg [63:0] prev_reg21; // includes G,W,C,F registers
reg [63:0] prev_reg22; // includes G,W,C,F registers
reg [63:0] prev_reg23; // includes G,W,C,F registers
reg [63:0] prev_reg24; // includes G,W,C,F registers
reg [63:0] prev_reg25; // includes G,W,C,F registers
reg [63:0] prev_reg26; // includes G,W,C,F registers
reg [63:0] prev_reg27; // includes G,W,C,F registers
reg [63:0] prev_reg28; // includes G,W,C,F registers
reg [63:0] prev_reg29; // includes G,W,C,F registers
reg [63:0] prev_reg30; // includes G,W,C,F registers
reg [63:0] prev_reg31; // includes G,W,C,F registers
reg [63:0] prev_reg32; // includes G,W,C,F registers
reg [63:0] prev_reg33; // includes G,W,C,F registers
reg [63:0] prev_reg34; // includes G,W,C,F registers
reg [63:0] prev_reg35; // includes G,W,C,F registers
reg [63:0] prev_reg36; // includes G,W,C,F registers
reg [63:0] prev_reg37; // includes G,W,C,F registers
reg [63:0] prev_reg38; // includes G,W,C,F registers
reg [63:0] prev_reg39; // includes G,W,C,F registers
reg [63:0] prev_reg40; // includes G,W,C,F registers
reg [63:0] prev_reg41; // includes G,W,C,F registers
reg [63:0] prev_reg42; // includes G,W,C,F registers
reg [63:0] prev_reg43; // includes G,W,C,F registers
reg [63:0] prev_reg44; // includes G,W,C,F registers
reg [63:0] prev_reg45; // includes G,W,C,F registers
reg [63:0] prev_reg46; // includes G,W,C,F registers
reg [63:0] prev_reg47; // includes G,W,C,F registers
reg [63:0] prev_reg48; // includes G,W,C,F registers
reg [63:0] prev_reg49; // includes G,W,C,F registers
reg [63:0] prev_reg50; // includes G,W,C,F registers
reg [63:0] prev_reg51; // includes G,W,C,F registers
reg [63:0] prev_reg52; // includes G,W,C,F registers
reg [63:0] prev_reg53; // includes G,W,C,F registers
reg [63:0] prev_reg54; // includes G,W,C,F registers
reg [63:0] prev_reg55; // includes G,W,C,F registers
reg [63:0] prev_reg56; // includes G,W,C,F registers
reg [63:0] prev_reg57; // includes G,W,C,F registers
reg [63:0] prev_reg58; // includes G,W,C,F registers
reg [63:0] prev_reg59; // includes G,W,C,F registers
reg [63:0] prev_reg60; // includes G,W,C,F registers
reg [63:0] prev_reg61; // includes G,W,C,F registers
reg [63:0] prev_reg62; // includes G,W,C,F registers
reg [63:0] prev_reg63; // includes G,W,C,F registers
reg [63:0] prev_reg64; // includes G,W,C,F registers
reg [63:0] prev_reg65; // includes G,W,C,F registers
reg [63:0] prev_reg66; // includes G,W,C,F registers
reg [63:0] prev_reg67; // includes G,W,C,F registers
reg [63:0] prev_reg68; // includes G,W,C,F registers
reg [63:0] prev_reg69; // includes G,W,C,F registers
reg [63:0] prev_reg70; // includes G,W,C,F registers
reg [63:0] prev_reg71; // includes G,W,C,F registers
reg [63:0] prev_reg72; // includes G,W,C,F registers
reg [63:0] prev_reg73; // includes G,W,C,F registers
reg [63:0] prev_reg74; // includes G,W,C,F registers
reg [63:0] prev_reg75; // includes G,W,C,F registers
reg [63:0] prev_reg76; // includes G,W,C,F registers
reg [63:0] prev_reg77; // includes G,W,C,F registers
reg [63:0] prev_reg78; // includes G,W,C,F registers
reg [63:0] prev_reg79; // includes G,W,C,F registers
reg [63:0] prev_reg80; // includes G,W,C,F registers
reg [63:0] prev_reg81; // includes G,W,C,F registers
reg [63:0] prev_reg82; // includes G,W,C,F registers
reg [63:0] prev_reg83; // includes G,W,C,F registers
reg [63:0] prev_reg84; // includes G,W,C,F registers
reg [63:0] prev_reg85; // includes G,W,C,F registers
reg [63:0] prev_reg86; // includes G,W,C,F registers
reg [63:0] prev_reg87; // includes G,W,C,F registers
reg [63:0] prev_reg88; // includes G,W,C,F registers
reg [63:0] prev_reg89; // includes G,W,C,F registers
reg [63:0] prev_reg90; // includes G,W,C,F registers
reg [63:0] prev_reg91; // includes G,W,C,F registers
reg [63:0] prev_reg92; // includes G,W,C,F registers
reg [63:0] prev_reg93; // includes G,W,C,F registers
reg [63:0] prev_reg94; // includes G,W,C,F registers
reg [63:0] prev_reg95; // includes G,W,C,F registers
reg [63:0] prev_reg96; // includes G,W,C,F registers
reg [63:0] prev_reg97; // includes G,W,C,F registers
reg [63:0] prev_reg98; // includes G,W,C,F registers
reg [63:0] prev_reg99; // includes G,W,C,F registers
reg [63:0] prev_reg100; // includes G,W,C,F registers
reg [63:0] prev_reg101; // includes G,W,C,F registers
reg [63:0] prev_reg102; // includes G,W,C,F registers
reg [63:0] prev_reg103; // includes G,W,C,F registers
reg [63:0] prev_reg104; // includes G,W,C,F registers
reg [63:0] prev_reg105; // includes G,W,C,F registers
reg [63:0] prev_reg106; // includes G,W,C,F registers
reg [63:0] prev_reg107; // includes G,W,C,F registers
reg [63:0] prev_reg108; // includes G,W,C,F registers
reg [63:0] prev_reg109; // includes G,W,C,F registers
reg [63:0] prev_reg110; // includes G,W,C,F registers
reg [63:0] prev_reg111; // includes G,W,C,F registers
reg [63:0] prev_reg112; // includes G,W,C,F registers
reg [63:0] prev_reg113; // includes G,W,C,F registers
reg [63:0] prev_reg114; // includes G,W,C,F registers
reg [63:0] prev_reg115; // includes G,W,C,F registers
reg [63:0] prev_reg116; // includes G,W,C,F registers
reg [63:0] prev_reg117; // includes G,W,C,F registers
reg [63:0] prev_reg118; // includes G,W,C,F registers
reg [63:0] prev_reg119; // includes G,W,C,F registers
reg [63:0] prev_reg120; // includes G,W,C,F registers
reg [63:0] prev_reg121; // includes G,W,C,F registers
reg [63:0] prev_reg122; // includes G,W,C,F registers
reg [63:0] prev_reg123; // includes G,W,C,F registers
reg [63:0] prev_reg124; // includes G,W,C,F registers
reg [63:0] prev_reg125; // includes G,W,C,F registers
reg [63:0] prev_reg126; // includes G,W,C,F registers
reg [63:0] prev_reg127; // includes G,W,C,F registers
reg [63:0] prev_reg128; // includes G,W,C,F registers
reg [63:0] prev_reg129; // includes G,W,C,F registers
reg [63:0] prev_reg130; // includes G,W,C,F registers
reg [63:0] prev_reg131; // includes G,W,C,F registers
reg [63:0] prev_reg132; // includes G,W,C,F registers
reg [63:0] prev_reg133; // includes G,W,C,F registers
reg [63:0] prev_reg134; // includes G,W,C,F registers
reg [63:0] prev_reg135; // includes G,W,C,F registers
reg [63:0] prev_reg136; // includes G,W,C,F registers
reg [63:0] prev_reg137; // includes G,W,C,F registers
reg [63:0] prev_reg138; // includes G,W,C,F registers
reg [63:0] prev_reg139; // includes G,W,C,F registers
reg [63:0] prev_reg140; // includes G,W,C,F registers
reg [63:0] prev_reg141; // includes G,W,C,F registers
reg [63:0] prev_reg142; // includes G,W,C,F registers
reg [63:0] prev_reg143; // includes G,W,C,F registers
reg [63:0] prev_reg144; // includes G,W,C,F registers
reg [63:0] prev_reg145; // includes G,W,C,F registers
reg [63:0] prev_reg146; // includes G,W,C,F registers
reg [63:0] prev_reg147; // includes G,W,C,F registers
reg [63:0] prev_reg148; // includes G,W,C,F registers
reg [63:0] prev_reg149; // includes G,W,C,F registers
reg [63:0] prev_reg150; // includes G,W,C,F registers
reg [63:0] prev_reg151; // includes G,W,C,F registers
reg [63:0] prev_reg152; // includes G,W,C,F registers
reg [63:0] prev_reg153; // includes G,W,C,F registers
reg [63:0] prev_reg154; // includes G,W,C,F registers
reg [63:0] prev_reg155; // includes G,W,C,F registers
reg [63:0] prev_reg156; // includes G,W,C,F registers
reg [63:0] prev_reg157; // includes G,W,C,F registers
reg [63:0] prev_reg158; // includes G,W,C,F registers
reg [63:0] prev_reg159; // includes G,W,C,F registers
reg [63:0] prev_reg160; // includes G,W,C,F registers
reg [63:0] prev_reg161; // includes G,W,C,F registers
reg [63:0] prev_reg162; // includes G,W,C,F registers
reg [63:0] prev_reg163; // includes G,W,C,F registers
reg [63:0] prev_reg164; // includes G,W,C,F registers
reg [63:0] prev_reg165; // includes G,W,C,F registers
reg [63:0] prev_reg166; // includes G,W,C,F registers
reg [63:0] prev_reg167; // includes G,W,C,F registers
reg [63:0] prev_reg168; // includes G,W,C,F registers
reg [63:0] prev_reg169; // includes G,W,C,F registers
reg [63:0] prev_reg170; // includes G,W,C,F registers
reg [63:0] prev_reg171; // includes G,W,C,F registers
reg [63:0] prev_reg172; // includes G,W,C,F registers
reg [63:0] prev_reg173; // includes G,W,C,F registers
reg [63:0] prev_reg174; // includes G,W,C,F registers
reg [63:0] prev_reg175; // includes G,W,C,F registers
reg [63:0] prev_reg176; // includes G,W,C,F registers
reg [63:0] prev_reg177; // includes G,W,C,F registers
reg [63:0] prev_reg178; // includes G,W,C,F registers
reg [63:0] prev_reg179; // includes G,W,C,F registers
reg [63:0] prev_reg180; // includes G,W,C,F registers
reg [63:0] prev_reg181; // includes G,W,C,F registers
reg [63:0] prev_reg182; // includes G,W,C,F registers
reg [63:0] prev_reg183; // includes G,W,C,F registers
reg [63:0] prev_reg184; // includes G,W,C,F registers
reg [63:0] prev_reg185; // includes G,W,C,F registers
reg [63:0] prev_reg186; // includes G,W,C,F registers
reg [63:0] prev_reg187; // includes G,W,C,F registers
reg [63:0] prev_reg188; // includes G,W,C,F registers
reg [63:0] prev_reg189; // includes G,W,C,F registers
reg [63:0] prev_reg190; // includes G,W,C,F registers
reg [63:0] prev_reg191; // includes G,W,C,F registers
reg [63:0] prev_reg192; // includes G,W,C,F registers
reg [63:0] prev_reg193; // includes G,W,C,F registers
reg [63:0] prev_reg194; // includes G,W,C,F registers
reg [63:0] prev_reg195; // includes G,W,C,F registers
reg [63:0] prev_reg196; // includes G,W,C,F registers
reg [63:0] prev_reg197; // includes G,W,C,F registers
reg [63:0] prev_reg198; // includes G,W,C,F registers
reg [63:0] prev_reg199; // includes G,W,C,F registers
reg [63:0] prev_reg200; // includes G,W,C,F registers
reg [63:0] prev_reg201; // includes G,W,C,F registers
reg [63:0] prev_reg202; // includes G,W,C,F registers
reg [63:0] prev_reg203; // includes G,W,C,F registers
reg [63:0] prev_reg204; // includes G,W,C,F registers
reg [63:0] prev_reg205; // includes G,W,C,F registers
reg [63:0] prev_reg206; // includes G,W,C,F registers
reg [63:0] prev_reg207; // includes G,W,C,F registers
reg [63:0] prev_reg208; // includes G,W,C,F registers
reg [63:0] prev_reg209; // includes G,W,C,F registers
reg [63:0] prev_reg210; // includes G,W,C,F registers
reg [63:0] prev_reg211; // includes G,W,C,F registers
reg [63:0] prev_reg212; // includes G,W,C,F registers
reg [63:0] prev_reg213; // includes G,W,C,F registers
reg [63:0] prev_reg214; // includes G,W,C,F registers
reg [63:0] prev_reg215; // includes G,W,C,F registers
reg [63:0] prev_reg216; // includes G,W,C,F registers
reg [63:0] prev_reg217; // includes G,W,C,F registers
reg [63:0] prev_reg218; // includes G,W,C,F registers
reg [63:0] prev_reg219; // includes G,W,C,F registers
reg [63:0] prev_reg220; // includes G,W,C,F registers
reg [63:0] prev_reg221; // includes G,W,C,F registers
reg [63:0] prev_reg222; // includes G,W,C,F registers
reg [63:0] prev_reg223; // includes G,W,C,F registers
reg [63:0] prev_reg224; // includes G,W,C,F registers
reg [63:0] prev_reg225; // includes G,W,C,F registers
reg [63:0] prev_reg226; // includes G,W,C,F registers
reg [63:0] prev_reg227; // includes G,W,C,F registers
reg [63:0] prev_reg228; // includes G,W,C,F registers
reg [63:0] prev_reg229; // includes G,W,C,F registers
reg [63:0] prev_reg230; // includes G,W,C,F registers
reg [63:0] prev_reg231; // includes G,W,C,F registers
reg [63:0] prev_reg232; // includes G,W,C,F registers
reg [63:0] prev_reg233; // includes G,W,C,F registers
reg [63:0] prev_reg234; // includes G,W,C,F registers
reg [63:0] prev_reg235; // includes G,W,C,F registers
reg [63:0] prev_reg236; // includes G,W,C,F registers
reg [63:0] prev_reg237; // includes G,W,C,F registers
reg [63:0] prev_reg238; // includes G,W,C,F registers
reg [63:0] prev_reg239; // includes G,W,C,F registers
reg [63:0] prev_reg240; // includes G,W,C,F registers
reg [63:0] prev_reg241; // includes G,W,C,F registers
reg [63:0] prev_reg242; // includes G,W,C,F registers
reg [63:0] prev_reg243; // includes G,W,C,F registers
reg [63:0] prev_reg244; // includes G,W,C,F registers
reg [63:0] prev_reg245; // includes G,W,C,F registers
reg [63:0] prev_reg246; // includes G,W,C,F registers
reg [63:0] prev_reg247; // includes G,W,C,F registers
reg [63:0] prev_reg248; // includes G,W,C,F registers
reg [63:0] prev_reg249; // includes G,W,C,F registers
reg [63:0] prev_reg250; // includes G,W,C,F registers
reg [63:0] prev_reg251; // includes G,W,C,F registers
reg [63:0] prev_reg252; // includes G,W,C,F registers
reg [63:0] prev_reg253; // includes G,W,C,F registers
reg [63:0] prev_reg254; // includes G,W,C,F registers
reg [63:0] prev_reg255; // includes G,W,C,F registers
reg [1:0] th_gl; // copy of GL_reg
reg frf_w1_skip_addr4_fw1;
reg frf_w1_skip_addr4_fw2;
reg [1:0] frf_w2_valid_fw;
reg [1:0] frf_w2_valid_bn;
reg [4:0] frf_w2_addr_fw;
reg [1:0] frf_w1_valid_fw;
reg [4:0] frf_w1_addr_fw;
reg wmr; // latched to get edge
reg por_a; // latched to get edge
reg por_b; // latched to get edge
reg nas_pipe_enable; // Turns on nas_pipe capture and Riesling SSTEP
wire [4:0] frf_w1_skip_addr;
wire [4:0] frf_w2_skip_addr;
reg good_trap_detected; // Used for -nosas only.
//----------------------------------------------------------
wire [`DELTA_WIDTH:0] delta_fx4_0;
wire [`DELTA_WIDTH:0] delta_fx4_1;
wire [`DELTA_WIDTH:0] delta_fx4_2;
wire [`DELTA_WIDTH:0] delta_fx4_3;
wire [`DELTA_WIDTH:0] delta_fx4_4;
wire [`DELTA_WIDTH:0] delta_fx4_5;
wire [`DELTA_WIDTH:0] delta_fx4_6;
wire [`DELTA_WIDTH:0] delta_fx4_7;
wire [`DELTA_WIDTH:0] delta_fx5_0;
wire [`DELTA_WIDTH:0] delta_fx5_1;
wire [`DELTA_WIDTH:0] delta_fx5_2;
wire [`DELTA_WIDTH:0] delta_fx5_3;
wire [`DELTA_WIDTH:0] delta_fx5_4;
wire [`DELTA_WIDTH:0] delta_fx5_5;
wire [`DELTA_WIDTH:0] delta_fx5_6;
wire [`DELTA_WIDTH:0] delta_fx5_7;
wire [`DELTA_WIDTH:0] delta_fb_0;
wire [`DELTA_WIDTH:0] delta_fb_1;
wire [`DELTA_WIDTH:0] delta_fb_2;
wire [`DELTA_WIDTH:0] delta_fb_3;
wire [`DELTA_WIDTH:0] delta_fb_4;
wire [`DELTA_WIDTH:0] delta_fb_5;
wire [`DELTA_WIDTH:0] delta_fb_6;
wire [`DELTA_WIDTH:0] delta_fb_7;
wire [`DELTA_WIDTH:0] delta_fw_0;
wire [`DELTA_WIDTH:0] delta_fw_1;
wire [`DELTA_WIDTH:0] delta_fw_2;
wire [`DELTA_WIDTH:0] delta_fw_3;
wire [`DELTA_WIDTH:0] delta_fw_4;
wire [`DELTA_WIDTH:0] delta_fw_5;
wire [`DELTA_WIDTH:0] delta_fw_6;
wire [`DELTA_WIDTH:0] delta_fw_7;
wire [`DELTA_WIDTH:0] delta_fw1_0;
wire [`DELTA_WIDTH:0] delta_fw1_1;
wire [`DELTA_WIDTH:0] delta_fw1_2;
wire [`DELTA_WIDTH:0] delta_fw1_3;
wire [`DELTA_WIDTH:0] delta_fw1_4;
wire [`DELTA_WIDTH:0] delta_fw1_5;
wire [`DELTA_WIDTH:0] delta_fw1_6;
wire [`DELTA_WIDTH:0] delta_fw1_7;
wire [`DELTA_WIDTH:0] delta_fw2_0;
wire [`DELTA_WIDTH:0] delta_fw2_1;
wire [`DELTA_WIDTH:0] delta_fw2_2;
wire [`DELTA_WIDTH:0] delta_fw2_3;
wire [`DELTA_WIDTH:0] delta_fw2_4;
wire [`DELTA_WIDTH:0] delta_fw2_5;
wire [`DELTA_WIDTH:0] delta_fw2_6;
wire [`DELTA_WIDTH:0] delta_fw2_7;
wire [`DELTA_WIDTH:0] delta_prev_0;
wire [`DELTA_WIDTH:0] delta_prev_1;
wire [`DELTA_WIDTH:0] delta_prev_2;
wire [`DELTA_WIDTH:0] delta_prev_3;
wire [`DELTA_WIDTH:0] delta_prev_4;
wire [`DELTA_WIDTH:0] delta_prev_5;
wire [`DELTA_WIDTH:0] delta_prev_6;
wire [`DELTA_WIDTH:0] delta_prev_7;
`PR_ALWAYS ("arg", `ALWAYS,"T%0d DEBUG_PIPE turned ON",mytnum);
//----------------------------------------------------------
// Note: no remap of %g,%o,%l,%i regs based on CWP or GL
assign g0 = (mytid<=3) ? `IRF5_EXU0[( 0+irf_offset)] : `IRF5_EXU1[( 0+irf_offset)];
assign g1 = (mytid<=3) ? `IRF5_EXU0[( 1+irf_offset)] : `IRF5_EXU1[( 1+irf_offset)];
assign g2 = (mytid<=3) ? `IRF5_EXU0[( 2+irf_offset)] : `IRF5_EXU1[( 2+irf_offset)];
assign g3 = (mytid<=3) ? `IRF5_EXU0[( 3+irf_offset)] : `IRF5_EXU1[( 3+irf_offset)];
assign g4 = (mytid<=3) ? `IRF5_EXU0[( 4+irf_offset)] : `IRF5_EXU1[( 4+irf_offset)];
assign g5 = (mytid<=3) ? `IRF5_EXU0[( 5+irf_offset)] : `IRF5_EXU1[( 5+irf_offset)];
assign g6 = (mytid<=3) ? `IRF5_EXU0[( 6+irf_offset)] : `IRF5_EXU1[( 6+irf_offset)];
assign g7 = (mytid<=3) ? `IRF5_EXU0[( 7+irf_offset)] : `IRF5_EXU1[( 7+irf_offset)];
assign o0 = (mytid<=3) ? `IRF5_EXU0[( 8+irf_offset)] : `IRF5_EXU1[( 8+irf_offset)];
assign o1 = (mytid<=3) ? `IRF5_EXU0[( 9+irf_offset)] : `IRF5_EXU1[( 9+irf_offset)];
assign o2 = (mytid<=3) ? `IRF5_EXU0[(10+irf_offset)] : `IRF5_EXU1[(10+irf_offset)];
assign o3 = (mytid<=3) ? `IRF5_EXU0[(11+irf_offset)] : `IRF5_EXU1[(11+irf_offset)];
assign o4 = (mytid<=3) ? `IRF5_EXU0[(12+irf_offset)] : `IRF5_EXU1[(12+irf_offset)];
assign o5 = (mytid<=3) ? `IRF5_EXU0[(13+irf_offset)] : `IRF5_EXU1[(13+irf_offset)];
assign o6 = (mytid<=3) ? `IRF5_EXU0[(14+irf_offset)] : `IRF5_EXU1[(14+irf_offset)];
assign o7 = (mytid<=3) ? `IRF5_EXU0[(15+irf_offset)] : `IRF5_EXU1[(15+irf_offset)];
assign l0 = (mytid<=3) ? `IRF5_EXU0[(16+irf_offset)] : `IRF5_EXU1[(16+irf_offset)];
assign l1 = (mytid<=3) ? `IRF5_EXU0[(17+irf_offset)] : `IRF5_EXU1[(17+irf_offset)];
assign l2 = (mytid<=3) ? `IRF5_EXU0[(18+irf_offset)] : `IRF5_EXU1[(18+irf_offset)];
assign l3 = (mytid<=3) ? `IRF5_EXU0[(19+irf_offset)] : `IRF5_EXU1[(19+irf_offset)];
assign l4 = (mytid<=3) ? `IRF5_EXU0[(20+irf_offset)] : `IRF5_EXU1[(20+irf_offset)];
assign l5 = (mytid<=3) ? `IRF5_EXU0[(21+irf_offset)] : `IRF5_EXU1[(21+irf_offset)];
assign l6 = (mytid<=3) ? `IRF5_EXU0[(22+irf_offset)] : `IRF5_EXU1[(22+irf_offset)];
assign l7 = (mytid<=3) ? `IRF5_EXU0[(23+irf_offset)] : `IRF5_EXU1[(23+irf_offset)];
assign i0 = (mytid<=3) ? `IRF5_EXU0[(24+irf_offset)] : `IRF5_EXU1[(24+irf_offset)];
assign i1 = (mytid<=3) ? `IRF5_EXU0[(25+irf_offset)] : `IRF5_EXU1[(25+irf_offset)];
assign i2 = (mytid<=3) ? `IRF5_EXU0[(26+irf_offset)] : `IRF5_EXU1[(26+irf_offset)];
assign i3 = (mytid<=3) ? `IRF5_EXU0[(27+irf_offset)] : `IRF5_EXU1[(27+irf_offset)];
assign i4 = (mytid<=3) ? `IRF5_EXU0[(28+irf_offset)] : `IRF5_EXU1[(28+irf_offset)];
assign i5 = (mytid<=3) ? `IRF5_EXU0[(29+irf_offset)] : `IRF5_EXU1[(29+irf_offset)];
assign i6 = (mytid<=3) ? `IRF5_EXU0[(30+irf_offset)] : `IRF5_EXU1[(30+irf_offset)];
assign i7 = (mytid<=3) ? `IRF5_EXU0[(31+irf_offset)] : `IRF5_EXU1[(31+irf_offset)];
//----------------------------------------------------------
assign frf_0 = `FRF5_EVEN[(mytid*32)+ 0];
assign frf_2 = `FRF5_EVEN[(mytid*32)+ 1];
assign frf_4 = `FRF5_EVEN[(mytid*32)+ 2];
assign frf_6 = `FRF5_EVEN[(mytid*32)+ 3];
assign frf_8 = `FRF5_EVEN[(mytid*32)+ 4];
assign frf_10 = `FRF5_EVEN[(mytid*32)+ 5];
assign frf_12 = `FRF5_EVEN[(mytid*32)+ 6];
assign frf_14 = `FRF5_EVEN[(mytid*32)+ 7];
assign frf_16 = `FRF5_EVEN[(mytid*32)+ 8];
assign frf_18 = `FRF5_EVEN[(mytid*32)+ 9];
assign frf_20 = `FRF5_EVEN[(mytid*32)+ 10];
assign frf_22 = `FRF5_EVEN[(mytid*32)+ 11];
assign frf_24 = `FRF5_EVEN[(mytid*32)+ 12];
assign frf_26 = `FRF5_EVEN[(mytid*32)+ 13];
assign frf_28 = `FRF5_EVEN[(mytid*32)+ 14];
assign frf_30 = `FRF5_EVEN[(mytid*32)+ 15];
assign frf_32 = `FRF5_EVEN[(mytid*32)+ 16];
assign frf_34 = `FRF5_EVEN[(mytid*32)+ 17];
assign frf_36 = `FRF5_EVEN[(mytid*32)+ 18];
assign frf_38 = `FRF5_EVEN[(mytid*32)+ 19];
assign frf_40 = `FRF5_EVEN[(mytid*32)+ 20];
assign frf_42 = `FRF5_EVEN[(mytid*32)+ 21];
assign frf_44 = `FRF5_EVEN[(mytid*32)+ 22];
assign frf_46 = `FRF5_EVEN[(mytid*32)+ 23];
assign frf_48 = `FRF5_EVEN[(mytid*32)+ 24];
assign frf_50 = `FRF5_EVEN[(mytid*32)+ 25];
assign frf_52 = `FRF5_EVEN[(mytid*32)+ 26];
assign frf_54 = `FRF5_EVEN[(mytid*32)+ 27];
assign frf_56 = `FRF5_EVEN[(mytid*32)+ 28];
assign frf_58 = `FRF5_EVEN[(mytid*32)+ 29];
assign frf_60 = `FRF5_EVEN[(mytid*32)+ 30];
assign frf_62 = `FRF5_EVEN[(mytid*32)+ 31];
assign frf_1 = `FRF5_ODD[(mytid*32)+ 0];
assign frf_3 = `FRF5_ODD[(mytid*32)+ 1];
assign frf_5 = `FRF5_ODD[(mytid*32)+ 2];
assign frf_7 = `FRF5_ODD[(mytid*32)+ 3];
assign frf_9 = `FRF5_ODD[(mytid*32)+ 4];
assign frf_11 = `FRF5_ODD[(mytid*32)+ 5];
assign frf_13 = `FRF5_ODD[(mytid*32)+ 6];
assign frf_15 = `FRF5_ODD[(mytid*32)+ 7];
assign frf_17 = `FRF5_ODD[(mytid*32)+ 8];
assign frf_19 = `FRF5_ODD[(mytid*32)+ 9];
assign frf_21 = `FRF5_ODD[(mytid*32)+ 10];
assign frf_23 = `FRF5_ODD[(mytid*32)+ 11];
assign frf_25 = `FRF5_ODD[(mytid*32)+ 12];
assign frf_27 = `FRF5_ODD[(mytid*32)+ 13];
assign frf_29 = `FRF5_ODD[(mytid*32)+ 14];
assign frf_31 = `FRF5_ODD[(mytid*32)+ 15];
assign frf_33 = `FRF5_ODD[(mytid*32)+ 16];
assign frf_35 = `FRF5_ODD[(mytid*32)+ 17];
assign frf_37 = `FRF5_ODD[(mytid*32)+ 18];
assign frf_39 = `FRF5_ODD[(mytid*32)+ 19];
assign frf_41 = `FRF5_ODD[(mytid*32)+ 20];
assign frf_43 = `FRF5_ODD[(mytid*32)+ 21];
assign frf_45 = `FRF5_ODD[(mytid*32)+ 22];
assign frf_47 = `FRF5_ODD[(mytid*32)+ 23];
assign frf_49 = `FRF5_ODD[(mytid*32)+ 24];
assign frf_51 = `FRF5_ODD[(mytid*32)+ 25];
assign frf_53 = `FRF5_ODD[(mytid*32)+ 26];
assign frf_55 = `FRF5_ODD[(mytid*32)+ 27];
assign frf_57 = `FRF5_ODD[(mytid*32)+ 28];
assign frf_59 = `FRF5_ODD[(mytid*32)+ 29];
assign frf_61 = `FRF5_ODD[(mytid*32)+ 30];
assign frf_63 = `FRF5_ODD[(mytid*32)+ 31];
//----------------------------------------------------------
assign delta_fx4_0 = delta_fx4[0];
assign delta_fx4_1 = delta_fx4[1];
assign delta_fx4_2 = delta_fx4[2];
assign delta_fx4_3 = delta_fx4[3];
assign delta_fx4_4 = delta_fx4[4];
assign delta_fx4_5 = delta_fx4[5];
assign delta_fx4_6 = delta_fx4[6];
assign delta_fx4_7 = delta_fx4[7];
assign delta_fx5_0 = delta_fx5[0];
assign delta_fx5_1 = delta_fx5[1];
assign delta_fx5_2 = delta_fx5[2];
assign delta_fx5_3 = delta_fx5[3];
assign delta_fx5_4 = delta_fx5[4];
assign delta_fx5_5 = delta_fx5[5];
assign delta_fx5_6 = delta_fx5[6];
assign delta_fx5_7 = delta_fx5[7];
assign delta_fb_0 = delta_fb[0];
assign delta_fb_1 = delta_fb[1];
assign delta_fb_2 = delta_fb[2];
assign delta_fb_3 = delta_fb[3];
assign delta_fb_4 = delta_fb[4];
assign delta_fb_5 = delta_fb[5];
assign delta_fb_6 = delta_fb[6];
assign delta_fb_7 = delta_fb[7];
assign delta_fw_0 = delta_fw[0];
assign delta_fw_1 = delta_fw[1];
assign delta_fw_2 = delta_fw[2];
assign delta_fw_3 = delta_fw[3];
assign delta_fw_4 = delta_fw[4];
assign delta_fw_5 = delta_fw[5];
assign delta_fw_6 = delta_fw[6];
assign delta_fw_7 = delta_fw[7];
assign delta_fw1_0 = delta_fw1[0];
assign delta_fw1_1 = delta_fw1[1];
assign delta_fw1_2 = delta_fw1[2];
assign delta_fw1_3 = delta_fw1[3];
assign delta_fw1_4 = delta_fw1[4];
assign delta_fw1_5 = delta_fw1[5];
assign delta_fw1_6 = delta_fw1[6];
assign delta_fw1_7 = delta_fw1[7];
assign delta_fw2_0 = delta_fw2[0];
assign delta_fw2_1 = delta_fw2[1];
assign delta_fw2_2 = delta_fw2[2];
assign delta_fw2_3 = delta_fw2[3];
assign delta_fw2_4 = delta_fw2[4];
assign delta_fw2_5 = delta_fw2[5];
assign delta_fw2_6 = delta_fw2[6];
assign delta_fw2_7 = delta_fw2[7];
assign delta_prev_0 = delta_prev[0];
assign delta_prev_1 = delta_prev[1];
assign delta_prev_2 = delta_prev[2];
assign delta_prev_3 = delta_prev[3];
assign delta_prev_4 = delta_prev[4];
assign delta_prev_5 = delta_prev[5];
assign delta_prev_6 = delta_prev[6];
assign delta_prev_7 = delta_prev[7];
//----------------------------------------------------------
//----------------------------------------------------------
assign mytnum = (mycid*8)+mytid;
assign mytg = mytid >> 2;
assign exu_complete = exu_valid & ~(`PROBES5.clkstop_d5|`TOP.in_reset|`SPC5.tcu_scan_en);
assign imul_complete = imul_valid & ~(`TOP.in_reset|`SPC5.tcu_scan_en);
assign idiv_complete = idiv_valid & ~(`TOP.in_reset|`SPC5.tcu_scan_en);
assign tlu_complete = tlu_complete_3 ;
assign fp_complete = fp_valid & ~(`TOP.in_reset|`SPC5.tcu_scan_en);
assign fdiv_complete = fdiv_valid & ~(`TOP.in_reset|`SPC5.tcu_scan_en);
assign lsu_complete = lsu_valid & ~(`TOP.in_reset|`SPC5.tcu_scan_en);
assign asi_complete = asi_valid & ~(`TOP.in_reset|`SPC5.tcu_scan_en);
assign complete_w = (exu_complete << `EXU_INDEX) |
(lsu_complete << `LSU_INDEX) |
(tlu_complete << `TLU_INDEX) |
(asi_complete << `ASI_INDEX) ;
assign oddwin = CWP_reg % 2;
assign frf_w1_valid_even = (frf_w1_tid_fw == mytid) & frf_w1_valid_fw[1];
assign frf_w1_valid_odd = (frf_w1_tid_fw == mytid) & frf_w1_valid_fw[0];
assign frf_w2_valid_even = (frf_w2_tid_fw == mytid) & frf_w2_valid_fw[1];
assign frf_w2_valid_odd = (frf_w2_tid_fw == mytid) & frf_w2_valid_fw[0];
assign frf_w1_skip_addr = frf_w1_addr_fw;
assign frf_w2_skip_addr = frf_w2_addr_fw;
// NOTE - ADD_TSB_CFG will never be used for Axis or Tharas
wire [63:0] ctxt_z_tsb_cfg0_reg = `PROBES5.ctxt_z_tsb_cfg0_reg[mytid];
wire [63:0] ctxt_z_tsb_cfg1_reg = `PROBES5.ctxt_z_tsb_cfg1_reg[mytid];
wire [63:0] ctxt_z_tsb_cfg2_reg = `PROBES5.ctxt_z_tsb_cfg2_reg[mytid];
wire [63:0] ctxt_z_tsb_cfg3_reg = `PROBES5.ctxt_z_tsb_cfg3_reg[mytid];
wire [63:0] ctxt_nz_tsb_cfg0_reg = `PROBES5.ctxt_nz_tsb_cfg0_reg[mytid];
wire [63:0] ctxt_nz_tsb_cfg1_reg = `PROBES5.ctxt_nz_tsb_cfg1_reg[mytid];
wire [63:0] ctxt_nz_tsb_cfg2_reg = `PROBES5.ctxt_nz_tsb_cfg2_reg[mytid];
wire [63:0] ctxt_nz_tsb_cfg3_reg = `PROBES5.ctxt_nz_tsb_cfg3_reg[mytid];
//----------------------------------------------------------
always @ (posedge `BENCH_SPC5_GCLK) begin // {
// TLU is async to the execution pipeline
// but needs to be delayed to allow CWP, etc to update and be stable
// before arch state is captured and diff_reg is called.
// FDIV was moved from fw1 to fw to allow FPRS to be stable before capture
tlu_complete_1 <= tlu_valid & ~(`TOP.in_reset|`SPC5.tcu_scan_en);
tlu_complete_2 <= tlu_complete_1;
tlu_complete_3 <= tlu_complete_2;
itagacc_fx5 <= I_TAG_ACC_reg; // Signal changes in W so need to pipeline to fw2
itagacc_fb <= itagacc_fx5;
itagacc_fw <= itagacc_fb;
itagacc_fw1 <= itagacc_fw;
itagacc_fw2 <= itagacc_fw1;
dtagacc_fx5 <= D_TAG_ACC_reg; // Signal changes in W so need to pipeline to fw2
dtagacc_fb <= dtagacc_fx5;
dtagacc_fw <= dtagacc_fb;
dtagacc_fw1 <= dtagacc_fw;
dtagacc_fw2 <= dtagacc_fw1;
dsfar_fb <= DSFAR_reg; // Signal changes in W+1 so need to pipeline to fw2
complete_fx4 <= complete_w;
complete_fx5 <= complete_fx4 ;
complete_fb <= complete_fx5 |
(idiv_complete << `IDIV_INDEX);
complete_fw <= complete_fb |
(fdiv_complete << `FDIV_INDEX) |
(imul_complete << `IMUL_INDEX);
complete_fw1 <= complete_fw |
(fp_complete << `FP_INDEX);
complete_fw2 <= complete_fw1;
frf_w1_valid_fw1 <= (frf_w1_valid_odd | frf_w1_valid_even) & fp_complete;
frf_w1_valid_fw2 <= frf_w1_valid_fw1;
frf_w1_skip_addr4_fw1 <= frf_w1_skip_addr[4];
frf_w1_skip_addr4_fw2 <= frf_w1_skip_addr4_fw1;
frf_w2_valid_fw <= frf_w2_valid_bn;
frf_w2_tid_fw <= frf_w2_tid;
frf_w2_addr_fw <= frf_w2_addr;
frf_w1_valid_fw <= frf_w1_valid;
frf_w1_tid_fw <= frf_w1_tid;
frf_w1_addr_fw <= frf_w1_addr;
if (~thread_running & `SPC5.tcu_core_running[mytid])
`TOP.th_last_act_cycle[mytnum] = `TOP.core_cycle_cnt;
thread_running <= `SPC5.tcu_core_running[mytid];
// Reset some register prev state on wmr negation
if (`SPC5.rst_wmr_protect && ~wmr)
wmr <= `SPC5.rst_wmr_protect;
if (`SPC5.rst_wmr_protect)
//----------------------------------------------------------
// Holding state for registers that may be updated asynchronously
// after synchronous update, but before capture/step. Also for reads,
// when register is read and modified before capture/step ..
// We capture the value /write time, and use that for sstep,
// ignoring any async updates, which are sent in the NEXT sstep ..
reg [63:0] asi_updated_int_rec;
reg asi_wr_int_rec_delay;
reg [16:0] asi_updated_softint;
reg asi_wr_softint_delay;
reg [16:0] asi_softint_wrdata;
always @(posedge `BENCH_SPC5_GCLK) begin // {
// Corner case : If async and sync wr occur in same clock, then the async
// update takes place. In this case we have to capture the
// value of the write WITHOUT async bit being set, so that
// we can sync with Riesling's sync write ..
asi_wr_int_rec_delay <= ( `SPC5.tlu.cth.asi_wr_int_rec[mytid] |
`SPC5.tlu.asi_rd_inc_vec_2[mytid]);
if (`SPC5.tlu.cth.asi_wr_int_rec[mytid] |
((`SPC5.tlu.asi.rd_inc_vec) &&
(`SPC5.tlu.asi.rd_tid_dec[mytid])) |
(`SPC5.tlu.asi_rd_int_rec &
`SPC5.tlu.cth.int_rec_mux_sel==mytid))
if (`SPC5.tlu.cth.asi_wr_int_rec[mytid])
asi_updated_int_rec <= `SPC5.tlu.cth.int_rec ;
else if ( (`SPC5.tlu.asi.rd_inc_vec) &&
(`SPC5.tlu.asi.rd_tid_dec[mytid]) )
if (`SPC5.tlu.cth.cxi_wr_int_dis[mytid]) begin
asi_updated_int_rec <= INTR_RECEIVE_reg & `SPC5.tlu.cth.int_rec_muxed_;
asi_updated_int_rec[`SPC5.tlu.cth.incoming_vector_in] <= 1'b0 ;
asi_updated_int_rec <= `SPC5.tlu.cth.int_rec_muxed ;
asi_updated_int_rec[`SPC5.tlu.cth.incoming_vector_in] <= 1'b0 ;
asi_updated_int_rec <= INTR_RECEIVE_reg;
asi_rdwr_int_rec <= 1'b1;
else if (complete_fw1 && !`NASTOP.sstep_early[mytnum])
asi_rdwr_int_rec <= 1'b0;
asi_wr_hintp_delay <= `SPC5.tlu.asi_wr_hintp[mytid];
if (`SPC5.tlu.asi_wr_hintp[mytid] |
`SPC5.tlu.asi_rd_hintp[mytid])
if (`SPC5.tlu.asi_wr_hintp[mytid])
asi_updated_hintp <= `SPC5.tlu.asi_wr_data_0[0] ;
asi_updated_hintp <= HINTP_reg;
else if (complete_fw1 && !`NASTOP.sstep_early[mytnum])
asi_wr_softint_delay <= (`SPC5.tlu.asi_wr_softint[mytid] |
`SPC5.tlu.asi_wr_clear_softint[mytid] |
`SPC5.tlu.asi_wr_set_softint[mytid]);
if (`SPC5.tlu.asi_wr_clear_softint[mytid])
asi_softint_wrdata <= ~`SPC5.tlu.asi_wr_data_0[16:0] & rd_SOFTINT_reg;
else if (`SPC5.tlu.asi_wr_set_softint[mytid])
asi_softint_wrdata <= `SPC5.tlu.asi_wr_data_0[16:0] | rd_SOFTINT_reg;
asi_softint_wrdata <= `SPC5.tlu.asi_wr_data_0[16:0];
if (asi_wr_softint_delay | `SPC5.tlu.asi_rd_softint[mytid])
if (asi_wr_softint_delay)
asi_updated_softint <= asi_softint_wrdata ;
asi_updated_softint <= rd_SOFTINT_reg ;
asi_rdwr_softint <= 1'b1;
else if (complete_fw1 && !`NASTOP.sstep_early[mytnum])
asi_rdwr_softint <= 1'b0;
//----------------------------------------------------------
// Negedge sampling to avoid race on specific signals ..
always @ (negedge `BENCH_SPC5_GCLK) begin // {
frf_w2_valid_bn <= frf_w2_valid;
//----------------------------------------------------------
// When instruction completes,
// Push differences to simics
always @ (posedge `BENCH_SPC5_GCLK) begin // {
if (`PARGS.th_check_enable[mytnum] && nas_pipe_enable && ~`SPC5.tcu_scan_en && ~`TOP.in_por) begin // {
// Update window registers
if (CWP_reg != `NASTOP.th_cwp[mytnum]) begin // {
copy_win (CWP_reg,`NASTOP.th_cwp[mytnum]);
`NASTOP.th_cwp[mytnum] = CWP_reg;
// Update global registers
// Wait for warm-reset flush related toggling to settle
if (GL_reg != th_gl) begin // {
if (`SPC5.spc_core_running_status[mytid] &
~`SPC5.rst_wmr_protect) begin // {
copy_global (GL_reg,th_gl);
// Check for bad signal values
// if NASTOP.sstep_sent[tid]=1,
// then SSTEP was set by another module (i.e. tlb_sync)
if (`PARGS.nas_check_on) begin // {
mytime = `TOP.core_cycle_cnt-1;
if (complete_fw2 && (`NASTOP.sstep_sent[mytnum]==1'b0)) begin // {
`PR_INFO ("pli_nas", `INFO, " C%0d T%0d PLI_SSTEP tid=%d pc=%h ts=%0d ",
mycid,mytid,mytnum,pc_fw2,mytime);
junk = $sim_send(`PLI_SSTEP, mytnum);
// Always clear sstep_early
// In case tlb_sync asserted it too late for complete_fw2
`NASTOP.sstep_early[mytnum] <= 1'b0;
else if (complete_fw2) begin // {
`NASTOP.sstep_sent[mytnum] <= 1'b0; // re-arm SSTEP
`NASTOP.sstep_early[mytnum] <= 1'b0;
`PR_INFO ("pli_nas", `INFO, " C%0d T%0d PLI_SSTEP tid=%d pc=%h ts=%0d (nas_pipe: skip sstep. rearm sstep. sstep_sent=0)",
mycid,mytid,mytnum,pc_fw2,mytime);
// Only capture if something completes and not first instruction
if (complete_fw2 && !first_op) begin // {
push_simics; // Use with AXIS to keep from getting timeout
// Pipeline runs continuously
// Other than when in POR ..
// Only save to delta_prev when something completes
`TOP.last_act_cycle = `TOP.core_cycle_cnt; //$time;
`TOP.th_last_act_cycle[mytnum] = `TOP.last_act_cycle;
// If something was captured but no instruction is in the pipeline
if ((delta_fw2[`NEXT_INDEX]!=`FIRST_INDEX) && (complete_fw2 == 0))
for (myindex=`FIRST_INDEX; myindex<delta_fw2[`NEXT_INDEX]; myindex=myindex+1)
print_entry (delta_fw2[myindex]);
`PR_ERROR ("nas",`ERROR, "T%0d Unexpected Reg change in DUT. Special case - no instruction retired.", mytnum);
// End detection for non-sas runs ..
for (junk=0;junk<`PARGS.bad_trap_count;junk=junk+1)
if (({16'b0,pc_fw2}&`PC_MASK) ===
(`PARGS.bad_trap_addr[junk]&`PC_MASK)) begin // {
// Disable nas_pipe processing (capture & SSTEP)
// to speed up simulation (minimize socket traffic,etc)
if (! `PARGS.nas_check_on) begin //{
`PR_ERROR ("nas",`ERROR, "T%0d reached Bad Trap", mytnum);
for (junk=0;junk<`PARGS.good_trap_count;junk=junk+1)
if ((|complete_fw2) && (({16'b0,pc_fw2}&`PC_MASK) ===
(`PARGS.good_trap_addr[junk]&`PC_MASK))) begin // {
// Disable nas_pipe processing (capture & SSTEP)
// to speed up simulation (minimize socket traffic,etc)
if (! `PARGS.nas_check_on) begin //{
good_trap_detected = 1'b1;
// Check Thread level timeout
(`TOP.core_cycle_cnt - `TOP.th_last_act_cycle[mytnum]) > `PARGS.th_timeout)
// Note: Do not change this message because regreport parses it for certain words.
`PR_ALWAYS ("nas",`ALWAYS, "ERROR: Thread T%0d No Activity for %0d Cycles - Thread TIMEOUT!",
mytnum, `PARGS.th_timeout);
junk = incErr(9999); // must exceed users max error setting to force exit.
end // if (`PARGS.th_check_enable[mytnum] && nas_pipe_enable ...)}
// Need to make sure Store Buffer is empty before turning off th_check_enable.
//global chkr requires to wait for all outstanding pending I
if ((! `PARGS.nas_check_on) &&
(good_trap_detected==1'b1) &&
(`TOP.nas_top.lsu_stb_empty[mytnum]) && `TOP.nas_top.ireq_pending[mytnum]) begin // {
`PARGS.th_check_enable[mytnum] = 1'b0;
`TOP.finished_tids[mytnum] = 1'b1;
good_trap_detected = 1'b0;
`PR_NORMAL ("nas", `NORMAL, "T%0d reached Good Trap. Disabling checking for thread %0d", mytnum,mytnum);
//----------------------------------------------------------
//----------------------------------------------------------
// Stage FX4 of delta pipeline
delta_fx4[`NEXT_INDEX] <= `FIRST_INDEX;
delta_fx4[`TIME_INDEX] <= 0;
delta_fx4[`PC_INDEX] <= {16'b0,PC_reg};
delta_fx4[`GL_INDEX] <= GL_reg;
delta_fx4[`CWP_INDEX] <= CWP_reg;
delta_fx4[`OPCODE_INDEX] <= opcode;
delta_fx4[`FIRST_INDEX] <= 77'hx;
//----------------------------------------------------------
// Stage FX5 of delta pipeline
index = delta_fx4[`NEXT_INDEX];
// Pipeline previous stage
for (i=0; i<=delta_fx4[`NEXT_INDEX]; i=i+1) begin // {
delta_fx5[i] <= delta_fx4[i];
if (complete_fx4) begin // LSU | EXU | TLU
push_delta_fx5 (`CCR+`CTL_OFFSET,CCR_reg,index);
if (complete_fx4[`LSU_INDEX] |
complete_fx4[`EXU_INDEX]) begin
if (mytid <= 3) begin // {
for (i=0; i<=31; i=i+1) begin // {
push_delta_fx5 (i,`IRF5_EXU0[(remap(i,oddwin)+irf_offset)],index);
for (i=0; i<=31; i=i+1) begin // {
push_delta_fx5 (i,`IRF5_EXU1[(remap(i,oddwin)+irf_offset)],index);
// Update FRF5 - Loads use W2 Port.
if (complete_fx4[`LSU_INDEX]) begin // {
// IF W1 port is also being written, ignore that address
for (i=0; i<=31; i=i+1) begin // {
if (!((i == frf_w1_skip_addr) && frf_w1_valid_even)) begin // {
frf_tmp = `FRF5_EVEN[(mytid*32)+i];
push_delta_fx5 (`FP_OFFSET + (i*2), frf_tmp[31:0], index);
if (!((i == frf_w1_skip_addr) && frf_w1_valid_odd)) begin // {
frf_tmp = `FRF5_ODD[(mytid*32)+i];
push_delta_fx5 (`FP_OFFSET + (i*2)+1, frf_tmp[31:0], index);
// Update ASR/ASI registers
if (complete_fx4) begin // {
push_delta_fx5 (`PSTATE + `CTL_OFFSET,PSTATE_reg,index);
push_delta_fx5 (`HPSTATE + `CTL_OFFSET,HPSTATE_reg,index);
push_delta_fx5 (`PIL + `CTL_OFFSET,PIL_reg,index);
push_delta_fx5 (`TBA + `CTL_OFFSET,{TBA_reg,15'b0},index);
push_delta_fx5 (`GL + `CTL_OFFSET,GL_reg,index);
push_delta_fx5 (`HTBA + `CTL_OFFSET,{HTBA_reg,14'b0},index);
push_delta_fx5 (`VER + `CTL_OFFSET,VER_reg,index);
push_delta_fx5 (`Y + `CTL_OFFSET,Y_reg,index);
push_delta_fx5 (`ASI + `CTL_OFFSET,ASI_reg,index);
push_delta_fx5 (`STICK_CMPR + `CTL_OFFSET,STICK_CMPR_wire,index);
push_delta_fx5 (`HSTICK_CMPR + `CTL_OFFSET,HSTICK_CMPR_wire,index);
push_delta_fx5 (`TICK_CMPR + `CTL_OFFSET,TICK_CMPR_wire,index);
push_delta_fx5 (`CWP + `CTL_OFFSET,CWP_reg,index);
push_delta_fx5 (`CANSAVE + `CTL_OFFSET,CANSAVE_reg,index);
push_delta_fx5 (`CANRESTORE + `CTL_OFFSET,CANRESTORE_reg,index);
push_delta_fx5 (`CLEANWIN + `CTL_OFFSET,CLEANWIN_reg,index);
push_delta_fx5 (`OTHERWIN + `CTL_OFFSET,OTHERWIN_reg,index);
push_delta_fx5 (`WSTATE + `CTL_OFFSET,WSTATE_reg,index);
push_delta_fx5 (`CTXT_PRIM_0+`CTL_OFFSET,CTXT_PRIM_0_reg,index);
push_delta_fx5 (`CTXT_SEC_0+`CTL_OFFSET,CTXT_SEC_0_reg,index);
push_delta_fx5 (`CTXT_PRIM_1+`CTL_OFFSET,CTXT_PRIM_1_reg,index);
push_delta_fx5 (`CTXT_SEC_1+`CTL_OFFSET,CTXT_SEC_1_reg,index);
push_delta_fx5 (`LSU_CONTROL+`CTL_OFFSET,LSU_CONTROL_reg,index);
push_delta_fx5 (`WATCHPOINT_ADDR+`CTL_OFFSET,WATCHPOINT_ADDR_reg,index);
// NOTE - ADD_TSB_CFG will never be used for Axis or Tharas
push_delta_fx5 (`CTXT_Z_TSB_CFG0+`CTL_OFFSET,ctxt_z_tsb_cfg0_reg,index);
push_delta_fx5 (`CTXT_Z_TSB_CFG1+`CTL_OFFSET,ctxt_z_tsb_cfg1_reg,index);
push_delta_fx5 (`CTXT_Z_TSB_CFG2+`CTL_OFFSET,ctxt_z_tsb_cfg2_reg,index);
push_delta_fx5 (`CTXT_Z_TSB_CFG3+`CTL_OFFSET,ctxt_z_tsb_cfg3_reg,index);
push_delta_fx5 (`CTXT_NZ_TSB_CFG0+`CTL_OFFSET,ctxt_nz_tsb_cfg0_reg,index);
push_delta_fx5 (`CTXT_NZ_TSB_CFG1+`CTL_OFFSET,ctxt_nz_tsb_cfg1_reg,index);
push_delta_fx5 (`CTXT_NZ_TSB_CFG2+`CTL_OFFSET,ctxt_nz_tsb_cfg2_reg,index);
push_delta_fx5 (`CTXT_NZ_TSB_CFG3+`CTL_OFFSET,ctxt_nz_tsb_cfg3_reg,index);
// Update GSR for all except write ASR in progess
if (!asi_in_progress) begin // {
push_delta_fx5 (`GSR + `CTL_OFFSET,GSR_wire, index);
// If lsu_complete & fp_complete assert at same time,
// then the fp_complete is the one that will modify the FSR
if (complete_fx4[`LSU_INDEX] & !complete_fw1[`FP_INDEX]) begin
push_delta_fx5 (`FSR+`CTL_OFFSET,FSR_wire,index);
// Non Trap updates of Trap stack & level
if (complete_fx4 && !complete_fx4[`TLU_INDEX]) begin // {
push_delta_fx5 (`TL + `CTL_OFFSET,TL_reg,index);
push_delta_fx5 (`TPC1 + `CTL_OFFSET, TPC1_wire, index);
push_delta_fx5 (`TPC2 + `CTL_OFFSET, TPC2_wire, index);
push_delta_fx5 (`TPC3 + `CTL_OFFSET, TPC3_wire, index);
push_delta_fx5 (`TPC4 + `CTL_OFFSET, TPC4_wire, index);
push_delta_fx5 (`TPC5 + `CTL_OFFSET, TPC5_wire, index);
push_delta_fx5 (`TPC6 + `CTL_OFFSET, TPC6_wire, index);
push_delta_fx5 (`TNPC1 + `CTL_OFFSET, TNPC1_wire, index);
push_delta_fx5 (`TNPC2 + `CTL_OFFSET, TNPC2_wire, index);
push_delta_fx5 (`TNPC3 + `CTL_OFFSET, TNPC3_wire, index);
push_delta_fx5 (`TNPC4 + `CTL_OFFSET, TNPC4_wire, index);
push_delta_fx5 (`TNPC5 + `CTL_OFFSET, TNPC5_wire, index);
push_delta_fx5 (`TNPC6 + `CTL_OFFSET, TNPC6_wire, index);
push_delta_fx5 (`TSTATE1 + `CTL_OFFSET, TSTATE1_wire, index);
push_delta_fx5 (`TSTATE2 + `CTL_OFFSET, TSTATE2_wire, index);
push_delta_fx5 (`TSTATE3 + `CTL_OFFSET, TSTATE3_wire, index);
push_delta_fx5 (`TSTATE4 + `CTL_OFFSET, TSTATE4_wire, index);
push_delta_fx5 (`TSTATE5 + `CTL_OFFSET, TSTATE5_wire, index);
push_delta_fx5 (`TSTATE6 + `CTL_OFFSET, TSTATE6_wire, index);
push_delta_fx5 (`HTSTATE1 + `CTL_OFFSET, HTSTATE1_wire, index);
push_delta_fx5 (`HTSTATE2 + `CTL_OFFSET, HTSTATE2_wire, index);
push_delta_fx5 (`HTSTATE3 + `CTL_OFFSET, HTSTATE3_wire, index);
push_delta_fx5 (`HTSTATE4 + `CTL_OFFSET, HTSTATE4_wire, index);
push_delta_fx5 (`HTSTATE5 + `CTL_OFFSET, HTSTATE5_wire, index);
push_delta_fx5 (`HTSTATE6 + `CTL_OFFSET, HTSTATE6_wire, index);
push_delta_fx5 (`TT1 + `CTL_OFFSET, TT1_wire, index);
push_delta_fx5 (`TT2 + `CTL_OFFSET, TT2_wire, index);
push_delta_fx5 (`TT3 + `CTL_OFFSET, TT3_wire, index);
push_delta_fx5 (`TT4 + `CTL_OFFSET, TT4_wire, index);
push_delta_fx5 (`TT5 + `CTL_OFFSET, TT5_wire, index);
push_delta_fx5 (`TT6 + `CTL_OFFSET, TT6_wire, index);
//----------------------------------------------------------
// Stage FB of delta pipeline
index = delta_fx5[`NEXT_INDEX];
// Pipeline previous stage
for (i=0; i<=delta_fx5[`NEXT_INDEX]; i=i+1) begin // {
delta_fb[i] <= delta_fx5[i];
if (complete_fx5[`ASI_INDEX]) begin // {
push_delta_fb (`GSR + `CTL_OFFSET,GSR_wire, index);
//----------------------------------------------------------
// Stage FW of delta pipeline
index = delta_fb[`NEXT_INDEX];
// Pipeline previous stage
for (i=0; i<=delta_fb[`NEXT_INDEX]; i=i+1) begin // {
delta_fw[i] <= delta_fb[i];
// Capture CWP_reg for SAVE/RESTORE
delta_fw[`CWP_INDEX] <= CWP_reg;
if (complete_fb[`TLU_INDEX]) begin
if (mytid <= 3) begin // {
for (i=0; i<=31; i=i+1) begin // {
push_delta_fw (i,`IRF5_EXU0[(remap(i,oddwin)+irf_offset)],index);
for (i=0; i<=31; i=i+1) begin // {
push_delta_fw (i,`IRF5_EXU1[(remap(i,oddwin)+irf_offset)],index);
// Update FRF5 - Idivs use W2.
if (complete_fb[`IDIV_INDEX]) begin // {
// IF W1 port is also being written, ignore that address
for (i=0; i<=31; i=i+1) begin // {
if (!((i == frf_w1_skip_addr) && frf_w1_valid_even)) begin // {
frf_tmp = `FRF5_EVEN[(mytid*32)+i];
push_delta_fw (`FP_OFFSET + (i*2), frf_tmp[31:0], index);
if (!((i == frf_w1_skip_addr) && frf_w1_valid_odd)) begin // {
frf_tmp = `FRF5_ODD[(mytid*32)+i];
push_delta_fw (`FP_OFFSET + (i*2)+1,frf_tmp[31:0], index);
//----------------------------------------------------------
// Stage FW1 of delta pipeline
index = delta_fw[`NEXT_INDEX];
// Pipeline previous stage
for (i=0; i<=delta_fw[`NEXT_INDEX]; i=i+1) begin // {
delta_fw1[i] <= delta_fw[i];
// Update FRF5 - FPops use W1 port.
if (fp_complete) begin // {
// IF W2 port is also being written, ignore that address
for (i=0; i<=31; i=i+1) begin // {
if (!((i == frf_w2_skip_addr) && frf_w2_valid_even)) begin // {
frf_tmp = `FRF5_EVEN[(mytid*32)+i];
push_delta_fw1 (`FP_OFFSET + (i*2), frf_tmp[31:0], index);
if (!((i == frf_w2_skip_addr) && frf_w2_valid_odd)) begin // {
frf_tmp = `FRF5_ODD[(mytid*32)+i];
push_delta_fw1 (`FP_OFFSET + (i*2)+1,frf_tmp[31:0], index);
if (complete_fw[`IMUL_INDEX]|complete_fw[`IDIV_INDEX]) begin
push_delta_fw1 (`CCR+`CTL_OFFSET,CCR_reg,index);
push_delta_fw1 (`Y+`CTL_OFFSET,Y_reg,index);
push_delta_fw1 (`CWP+`CTL_OFFSET,CWP_reg,index);
push_delta_fw1 (`CANSAVE+`CTL_OFFSET,CANSAVE_reg,index);
push_delta_fw1 (`CANRESTORE+`CTL_OFFSET,CANRESTORE_reg,index);
push_delta_fw1 (`CLEANWIN+`CTL_OFFSET,CLEANWIN_reg,index);
push_delta_fw1 (`OTHERWIN+`CTL_OFFSET,OTHERWIN_reg,index);
push_delta_fw1 (`WSTATE+`CTL_OFFSET,WSTATE_reg,index);
if (complete_fw[`TLU_INDEX]) begin // {
push_delta_fw1 (`TL + `CTL_OFFSET,TL_reg,index);
push_delta_fw1 (`TPC1 + `CTL_OFFSET, TPC1_wire, index);
push_delta_fw1 (`TPC2 + `CTL_OFFSET, TPC2_wire, index);
push_delta_fw1 (`TPC3 + `CTL_OFFSET, TPC3_wire, index);
push_delta_fw1 (`TPC4 + `CTL_OFFSET, TPC4_wire, index);
push_delta_fw1 (`TPC5 + `CTL_OFFSET, TPC5_wire, index);
push_delta_fw1 (`TPC6 + `CTL_OFFSET, TPC6_wire, index);
push_delta_fw1 (`TNPC1 + `CTL_OFFSET, TNPC1_wire, index);
push_delta_fw1 (`TNPC2 + `CTL_OFFSET, TNPC2_wire, index);
push_delta_fw1 (`TNPC3 + `CTL_OFFSET, TNPC3_wire, index);
push_delta_fw1 (`TNPC4 + `CTL_OFFSET, TNPC4_wire, index);
push_delta_fw1 (`TNPC5 + `CTL_OFFSET, TNPC5_wire, index);
push_delta_fw1 (`TNPC6 + `CTL_OFFSET, TNPC6_wire, index);
push_delta_fw1 (`TSTATE1 + `CTL_OFFSET, TSTATE1_wire, index);
push_delta_fw1 (`TSTATE2 + `CTL_OFFSET, TSTATE2_wire, index);
push_delta_fw1 (`TSTATE3 + `CTL_OFFSET, TSTATE3_wire, index);
push_delta_fw1 (`TSTATE4 + `CTL_OFFSET, TSTATE4_wire, index);
push_delta_fw1 (`TSTATE5 + `CTL_OFFSET, TSTATE5_wire, index);
push_delta_fw1 (`TSTATE6 + `CTL_OFFSET, TSTATE6_wire, index);
push_delta_fw1 (`HTSTATE1 + `CTL_OFFSET, HTSTATE1_wire, index);
push_delta_fw1 (`HTSTATE2 + `CTL_OFFSET, HTSTATE2_wire, index);
push_delta_fw1 (`HTSTATE3 + `CTL_OFFSET, HTSTATE3_wire, index);
push_delta_fw1 (`HTSTATE4 + `CTL_OFFSET, HTSTATE4_wire, index);
push_delta_fw1 (`HTSTATE5 + `CTL_OFFSET, HTSTATE5_wire, index);
push_delta_fw1 (`HTSTATE6 + `CTL_OFFSET, HTSTATE6_wire, index);
push_delta_fw1 (`TT1 + `CTL_OFFSET, TT1_wire, index);
push_delta_fw1 (`TT2 + `CTL_OFFSET, TT2_wire, index);
push_delta_fw1 (`TT3 + `CTL_OFFSET, TT3_wire, index);
push_delta_fw1 (`TT4 + `CTL_OFFSET, TT4_wire, index);
push_delta_fw1 (`TT5 + `CTL_OFFSET, TT5_wire, index);
push_delta_fw1 (`TT6 + `CTL_OFFSET, TT6_wire, index);
//----------------------------------------------------------
// Stage FW2 of delta pipeline
index = delta_fw1[`NEXT_INDEX];
// Pipeline previous stage
for (i=0; i<=delta_fw1[`NEXT_INDEX]; i=i+1) begin // {
delta_fw2[i] <= delta_fw1[i];
delta_fw2[`TIME_INDEX] <= $time;
// Update Registers that may change asynchronously
// If sstep was already sent by another module,
// don't capture until the next sstep
if (complete_fw1 && !`NASTOP.sstep_early[mytnum]) begin // {
if ((complete_fw1[`ASI_INDEX]|complete_fw1[`LSU_INDEX]) & asi_rdwr_hintp)
push_delta_fw2 (`HINTP + `CTL_OFFSET,asi_updated_hintp,index);
push_delta_fw2 (`HINTP + `CTL_OFFSET,HINTP_reg,index);
if ((complete_fw1[`ASI_INDEX]|complete_fw1[`LSU_INDEX]) & asi_rdwr_softint)
push_delta_fw2 (`SOFTINT + `CTL_OFFSET,asi_updated_softint,index);
push_delta_fw2 (`SOFTINT + `CTL_OFFSET,rd_SOFTINT_reg,index);
if (complete_fw1[`IMUL_INDEX] |
complete_fw1[`IDIV_INDEX]) begin // {
if (mytid <= 3) begin // {
for (i=0; i<=31; i=i+1) begin // {
push_delta_fw2 (i,`IRF5_EXU0[(remap(i,oddwin)+irf_offset)],index);
for (i=0; i<=31; i=i+1) begin // {
push_delta_fw2 (i,`IRF5_EXU1[(remap(i,oddwin)+irf_offset)],index);
// Update FRF5 - fdivs and Imuls use W2 port
if (complete_fw1[`IMUL_INDEX] |
complete_fw1[`FDIV_INDEX] ) begin // {
// IF W1 port is also being written, ignore that address
for (i=0; i<=31; i=i+1) begin // {
if (!((i == frf_w1_skip_addr) && frf_w1_valid_even)) begin // {
frf_tmp = `FRF5_EVEN[(mytid*32)+i];
push_delta_fw2 (`FP_OFFSET + (i*2), frf_tmp[31:0], index);
if (!((i == frf_w1_skip_addr) && frf_w1_valid_odd)) begin // {
frf_tmp = `FRF5_ODD[(mytid*32)+i];
push_delta_fw2 (`FP_OFFSET + (i*2)+1,frf_tmp[31:0], index);
if (complete_fw1[`FP_INDEX] |
complete_fw1[`TLU_INDEX] |
complete_fw1[`FDIV_INDEX]) begin
push_delta_fw2 (`FSR+`CTL_OFFSET,FSR_wire,index);
push_delta_fw2 (`I_TAG_ACC+`CTL_OFFSET,itagacc_fw2,index);
push_delta_fw2 (`D_TAG_ACC+`CTL_OFFSET,dtagacc_fw2,index);
push_delta_fw2 (`DSFAR+`CTL_OFFSET,dsfar_fw2,index);
//----------------------------------------------------------
// Stage FW2 of delta pipeline - for signals that change FW+2 !!
index = delta_fw2[`NEXT_INDEX];
// Since FPRS for FPops may have been corrupted by o-o-o loads:
// If fprs_fw2 is != fprs_reg & there are loads in the pipeline
// then assume loads have already updated fprs.
// In that case, create our own fprs_reg by using the valids and
// skip_addr and copy of fprs for this op..
if (complete_fw2[`FP_INDEX] && frf_w1_valid_fw2) begin // {
// o-o-o load has changed fprs already - use dummy
if ((fprs_fw2 != FPRS_reg) && (complete_fw1[`LSU_INDEX] |
complete_fw[`LSU_INDEX] | complete_fb[`LSU_INDEX] |
complete_fx5[`LSU_INDEX] )) begin // {
dummy_fprs = read_prev(`FPRS + `CTL_OFFSET);
dummy_fprs = dummy_fprs |
{1'b0, frf_w1_skip_addr4_fw2, ~frf_w1_skip_addr4_fw2};
push_delta_fw2_async (`FPRS + `CTL_OFFSET,dummy_fprs,index);
// o-o-o load has NOT changed fprs already - use it
push_delta_fw2_async (`FPRS + `CTL_OFFSET,FPRS_reg,index);
// Load FPRS for loads/reads as prev|fprs_fb ..
// since loads may only 'set' bits, not clear ...
else if (complete_fw2[`LSU_INDEX]) begin // {
dummy_fprs = read_prev(`FPRS + `CTL_OFFSET);
dummy_fprs = dummy_fprs | fprs_fw1;
push_delta_fw2_async (`FPRS +`CTL_OFFSET,dummy_fprs,index);
// Load FPRS for store ASI or FDIV
// FDIV can update FPRS on w1 or w2,
// but the pipe is stalled behind it so no o-o-o loads.
else if ((complete_fw2[`ASI_INDEX]) ||
(complete_fw2[`FDIV_INDEX])) begin // {
push_delta_fw2_async (`FPRS + `CTL_OFFSET,FPRS_reg,index);
//----------------------------------------------------------
// Store latest values into delta
index = delta_prev[`NEXT_INDEX];
if (in_wmr & ~`SPC5.rst_wmr_protect) begin // {
push_delta_prev_async ( `PC+`CTL_OFFSET,{16'b0,pc_fw2|1},index);
push_delta_prev_async ( `PC+`CTL_OFFSET,{16'b0,pc_fw2},index);
//----------------------------------------------------------
//----------------------------------------------------------
// Compare with current state and capture if different
if (act_value != read_prev(id)) begin // { // Diff vs prev
calc_cwp(CWP_reg,id,win,type); // special case for 1st stage
write_prev(id,act_value);
delta_fx4[next] <= {type,win,id,act_value};
delta_fx4[next] <= 77'hx;
delta_fx4[`NEXT_INDEX] <= next;
if (`PARGS.axis_debug_on) begin
$display("AXIS: T%0d pc=%h id=%0d type=%0h win=%0h value=%h ts=%0d",
mytnum,PC_reg,id,type,win,act_value,$time);
if (`PARGS.axis_debug_on) begin
$display("AXIS: T%0d pc=%h id=%0d type=%0h win=%0h value=%h ts=%0d",
mytnum,PC_reg,id,type,win,act_value,$time);
//----------------------------------------------------------
// Compare with current state and capture if different
if (act_value != read_prev(id)) begin // { // Diff vs prev
calc_cwp(delta_fx4[`CWP_INDEX],id,win,type);
write_prev(id,act_value);
delta_fx5[next] <= {type,win,id,act_value};
delta_fx5[next] <= 77'hx;
delta_fx5[`NEXT_INDEX] <= next;
if (`PARGS.axis_debug_on) begin
$display("AXIS: T%0d pc=%h id=%0d type=%0h win=%0h value=%h ts=%0d",
mytnum,pc_fx4,id,type,win,act_value,$time);
calc_cwp(cwp_fx4,id,win,type);
if (`PARGS.axis_debug_on) begin
$display("AXIS: T%0d pc=%h id=%0d type=%0h win=%0h value=%h ts=%0d",
mytnum,pc_fx4,id,type,win,act_value,$time);
//----------------------------------------------------------
// Compare with current state and capture if different
if (act_value != read_prev(id)) begin // { // Diff vs prev
calc_cwp(delta_fx5[`CWP_INDEX],id,win,type);
write_prev(id,act_value);
delta_fb[next] <= {type,win,id,act_value};
delta_fb[`NEXT_INDEX] <= next;
if (`PARGS.axis_debug_on) begin
$display("AXIS: T%0d pc=%h id=%0d type=%0h win=%0h value=%h ts=%0d",
mytnum,pc_fx5,id,type,win,act_value,$time);
calc_cwp(cwp_fx5,id,win,type);
if (`PARGS.axis_debug_on) begin
$display("AXIS: T%0d pc=%h id=%0d type=%0h win=%0h value=%h ts=%0d",
mytnum,pc_fx5,id,type,win,act_value,$time);
//----------------------------------------------------------
// Compare with current state and capture if different
if (act_value != read_prev(id)) begin // { // Diff vs prev
calc_cwp(delta_fb[`CWP_INDEX],id,win,type);
write_prev(id,act_value);
delta_fw[next] <= {type,win,id,act_value};
delta_fw[`NEXT_INDEX] <= next;
if (`PARGS.axis_debug_on) begin
$display("AXIS: T%0d pc=%h id=%0d type=%0h win=%0h value=%h ts=%0d",
mytnum,pc_fb,id,type,win,act_value,$time);
calc_cwp(cwp_fb[`CWP_INDEX],id,win,type);
if (`PARGS.axis_debug_on) begin
$display("AXIS: T%0d pc=%h id=%0d type=%0h win=%0h value=%h ts=%0d",
mytnum,pc_fb,id,type,win,act_value,$time);
//----------------------------------------------------------
// Compare with current state and capture if different
if (act_value != read_prev(id)) begin // { // Diff vs prev
calc_cwp(delta_fw[`CWP_INDEX],id,win,type);
write_prev(id,act_value);
delta_fw1[next] <= {type,win,id,act_value};
delta_fw1[next] <= 77'hx;
delta_fw1[`NEXT_INDEX] <= next;
if (`PARGS.axis_debug_on) begin
$display("AXIS: T%0d pc=%h id=%0d type=%0h win=%0h value=%h ts=%0d",
mytnum,pc_fw,id,type,win,act_value,$time);
calc_cwp(cwp_fw,id,win,type);
if (`PARGS.axis_debug_on) begin
$display("AXIS: T%0d pc=%h id=%0d type=%0h win=%0h value=%h ts=%0d",
mytnum,pc_fw,id,type,win,act_value,$time);
//----------------------------------------------------------
// Compare with current state and capture if different
if (act_value != read_prev(id)) begin // { // Diff vs prev
calc_cwp(delta_fw1[`CWP_INDEX],id,win,type);
write_prev(id,act_value);
delta_fw2[next] <= {type,win,id,act_value};
delta_fw2[next] <= 77'hx;
delta_fw2[`NEXT_INDEX] <= next;
if (`PARGS.axis_debug_on) begin
$display("AXIS: T%0d pc=%h id=%0d type=%0h win=%0h value=%h ts=%0d",
mytnum,pc_fw1,id,type,win,act_value,$time);
calc_cwp(cwp_fw1,id,win,type);
if (`PARGS.axis_debug_on) begin
$display("AXIS: T%0d pc=%h id=%0d type=%0h win=%0h value=%h ts=%0d",
mytnum,pc_fw1,id,type,win,act_value,$time);
//----------------------------------------------------------
// Compare with current state and capture if different
// This is for late changing registers
// Use blocking assignments.
task push_delta_fw2_async;
if (act_value != read_prev(id)) begin // { // Diff vs prev
calc_cwp(delta_fw2[`CWP_INDEX],id,win,type);
write_prev_async(id,act_value);
delta_fw2[next] = {type,win,id,act_value};
delta_fw2[`NEXT_INDEX] = next;
if (`PARGS.axis_debug_on) begin
$display("AXIS: T%0d pc=%h id=%0d type=%0h win=%0h value=%h ts=%0d",
mytnum,pc_fw1,id,type,win,act_value,$time);
calc_cwp(cwp_fw2,id,win,type);
if (`PARGS.axis_debug_on) begin
$display("AXIS: T%0d pc=%h id=%0d type=%0h win=%0h value=%h ts=%0d",
mytnum,pc_fw1,id,type,win,act_value,$time);
//----------------------------------------------------------
// Compare with current state and capture if different
// Use blocking assignments so that push_simics will work
task push_delta_prev_async;
if (act_value != read_prev(id)) begin // { // Diff vs prev
calc_cwp(delta_prev[`CWP_INDEX],id,win,type);
write_prev_async(id,act_value);
delta_prev[next] = {type,win,id,act_value};
delta_prev[next] = 77'hx;
delta_prev[`NEXT_INDEX] = next;
if (`PARGS.axis_debug_on) begin
$display("AXIS: T%0d pc=%h id=%0d type=%0h win=%0h value=%h ts=%0d",
mytnum,pc_last,id,type,win,act_value,$time);
if (`PARGS.axis_debug_on) begin
calc_cwp(cwp_last,id,win,type);
$display("AXIS: T%0d pc=%h id=%0d type=%0h win=%0h value=%h ts=%0d",
mytnum,pc_last,id,type,win,act_value,$time);
//----------------------------------------------------------
// prev of delta pipeline
// Pipeline previous stage
for (i=0; i<=delta_fw2[`NEXT_INDEX]; i=i+1) begin // {
delta_prev[i] <= delta_fw2[i];
//----------------------------------------------------------
//----------------------------------------------------------
// Sort delta list in register ID order, then push to simics
// Or print deltas if sas check disabled ..
// Order of registers reported to simics must be:
// Global 0-7 aka prev_reg[0:7]
// Window 8-23 aka prev_reg[8:23]
// Floating 0-63 aka prev_reg[200:263]
// Control 32-143 aka prev_reg[32:143]
act_level = delta_prev[`GL_INDEX]; // GL
time_fw2 = delta_prev[`TIME_INDEX]; // Finish time
for (i=`FIRST_INDEX; i<delta_prev[`NEXT_INDEX]; i=i+1) begin // {
{type,win,regnum,value} = delta_prev[i];
if (regnum<=7) begin // {
if (`PARGS.nas_check_on) begin // {
`ACT_STATUS = $queue(`ACT_QUEUE, `PUSH_Q, mytnum, time_fw2, act_type,
act_level, regnum, value);
else if (`PARGS.show_delta_on) begin // {
`NASTOP.print_delta (mytnum,act_type,win,regnum,value);
else if (regnum<=23) begin // { %o0-%l7, %l0-%l7
if (`PARGS.nas_check_on) begin // {
`ACT_STATUS = $queue(`ACT_QUEUE, `PUSH_Q, mytnum, time_fw2, act_type,
else if (`PARGS.show_delta_on) begin // {
`NASTOP.print_delta (mytnum,act_type,win,regnum,value);
else if (regnum<=31) begin // { %i0-%i7
if (`PARGS.nas_check_on) begin // {
`ACT_STATUS = $queue(`ACT_QUEUE, `PUSH_Q, mytnum, time_fw2, act_type,
win, (regnum-16), value);
else if (`PARGS.show_delta_on) begin // {
`NASTOP.print_delta (mytnum,act_type,win,(regnum-16),value);
else if (regnum<=(64+`FP_OFFSET)) begin // {
if (`PARGS.nas_check_on) begin // {
`ACT_STATUS = $queue(`ACT_QUEUE, `PUSH_Q, mytnum, time_fw2, act_type,
(regnum-`FP_OFFSET), value);
else if (`PARGS.show_delta_on) begin // {
`NASTOP.print_delta (mytnum,act_type,win,(regnum-`FP_OFFSET),value);
else if ((regnum>=(32+`CTL_OFFSET))&(regnum<=(143+`CTL_OFFSET))) begin // {
if (`PARGS.nas_check_on) begin // {
`ACT_STATUS = $queue(`ACT_QUEUE, `PUSH_Q, mytnum, time_fw2, act_type,
(regnum-`CTL_OFFSET), value);
else if (`PARGS.show_delta_on) begin // {
`NASTOP.print_delta (mytnum,act_type,win,(regnum-`CTL_OFFSET),value);
`PR_ERROR ("nas", `ERROR, " - T%0d Bench problem. push_simics has bad regnum", mytnum);
value = delta_prev[`OPCODE_INDEX];
if (`PARGS.nas_check_on) begin // {
`ACT_STATUS = $queue(`ACT_QUEUE, `PUSH_Q, mytnum, time_fw2, act_type,
else if (`PARGS.show_delta_on) begin // {
`NASTOP.print_delta (mytnum,act_type,win,regnum,value);
// Push End of Instruction Delimiter
// The value field for this PUSH equals the PC for this instruction.
// so that printing to the logfile works correctly.
// prev_reg[`PC] = current instruction PC
// delta_reg[`PC] = PC at end of current instruction
pc = delta_prev[`PC_INDEX];
if (`PARGS.nas_check_on) begin // {
`ACT_STATUS = $queue(`ACT_QUEUE, `PUSH_Q, mytnum, time_fw2, act_type,
delta_fw2[`CWP_INDEX], `END_INSTR, pc);
else if (`PARGS.show_delta_on) begin // {
`NASTOP.print_delta (mytnum,act_type,delta_fw2[`CWP_INDEX],`END_INSTR,0);
if (! `PARGS.nas_check_on) begin // {
`PR_NORMAL ("nas", `NORMAL, "@%0d T%0d %h (Unchecked..)",
$time, mytnum, {16'b0,pc});
`TOP.last_act_cycle = `TOP.core_cycle_cnt; //$time;
`TOP.th_last_act_cycle[mytnum] = `TOP.last_act_cycle;
if (! `PARGS.nas_check_on) begin // {
`TOP.last_act_cycle = `TOP.core_cycle_cnt; //$time;
`TOP.th_last_act_cycle[mytnum] = `TOP.last_act_cycle;
//----------------------------------------------------------
// Save current window to previous window, then copy new window to current window
// Save current window to Old window
// Copy New window to current window
//----------------------------------------------------------
// Save current global to previous global, then copy new global to current global
// Save current global to Old global
// Copy New global current global
//----------------------------------------------------------
// Return window number and register type based on cwp and regnum as input
else if (id<=23) begin // {
else if (id<=31) begin // {
else if (id<=(64+`FP_OFFSET)) begin // {
//----------------------------------------------------------
// Check for bad signal values
8'b10000000: ; // good value
`PR_ERROR ("nas", `ERROR, " - T%0d More than one instruction retired in a single cycle for this thread.",
$write("\t\t\t\t Instructions - ");
if (complete_fw2[`EXU_INDEX]) $write("EXU op, ");
if (complete_fw2[`FP_INDEX]) $write("FP op, ");
if (complete_fw2[`LSU_INDEX]) $write("LSU op, ");
if (complete_fw2[`IMUL_INDEX]) $write("IMUL op, ");
if (complete_fw2[`IDIV_INDEX]) $write("IDIV op, ");
if (complete_fw2[`FDIV_INDEX]) $write("FDIV op, ");
if (complete_fw2[`TLU_INDEX]) $write("TLU op, ");
if (complete_fw2[`ASI_INDEX]) $write("ASI op, ");
$write(" complete_fw2 = %b \n",complete_fw2);
// This check only works if diags are written properly.
// For example, if a diag writes to one of these registers using wrpr,
// then this check must be disabled using plusarg.
// CANSAVE + CANRESTORE + OTHERWIN = NWINDOWS-2 (per Sparc V9)
if (`PARGS.win_check_on) begin // {
if (complete_fw2 & ((CANSAVE_reg + CANRESTORE_reg + OTHERWIN_reg) != 6)) begin // {
`PR_ERROR ("nas", `ERROR, "ERROR - T%0d Bad Values for window registers.", mytnum);
`PR_ERROR ("nas", `ERROR, "- CANSAVE = %0d CANRESTORE = %0d OTHERWIN = %0d",
CANSAVE_reg, CANRESTORE_reg,OTHERWIN_reg);
//----------------------------------------------------------
//----------------------------------------------------------
reg [`DELTA_WIDTH:0] temp1, temp2;
last = delta_prev[`NEXT_INDEX]-1;
for (i=`FIRST_INDEX; i <= last; i=i+1) begin // {
for (j=`FIRST_INDEX; j < last; j=j+1) begin // {
temp1 = delta_prev[j]; temp2 = delta_prev[j+1];
if (temp1[76:64] > temp2[76:64]) begin // {
delta_prev[j] = temp2; delta_prev [j+1] = temp1;
//----------------------------------------------------------
//----------------------------------------------------------
// Print one entry in delta_* array
input [`DELTA_WIDTH:0] delta_entry;
reg [(20*8)-1:0] type_str;
reg [(20*8)-1:0] regname;
{type,win,id,act_value} = delta_entry;
`NASTOP.get_regname(mytnum,type_str,win,id,regname);
`PR_NORMAL ("nas", `NORMAL, "type=%0s win=%0d RegID=%0d %0s=%h",
type_str,win,id,regname,act_value);
//----------------------------------------------------------
// Write Value to prev_reg using id as index (non-blocking)
8'd0: prev_reg0 <= value;
8'd1: prev_reg1 <= value;
8'd2: prev_reg2 <= value;
8'd3: prev_reg3 <= value;
8'd4: prev_reg4 <= value;
8'd5: prev_reg5 <= value;
8'd6: prev_reg6 <= value;
8'd7: prev_reg7 <= value;
8'd8: prev_reg8 <= value;
8'd9: prev_reg9 <= value;
8'd10: prev_reg10 <= value;
8'd11: prev_reg11 <= value;
8'd12: prev_reg12 <= value;
8'd13: prev_reg13 <= value;
8'd14: prev_reg14 <= value;
8'd15: prev_reg15 <= value;
8'd16: prev_reg16 <= value;
8'd17: prev_reg17 <= value;
8'd18: prev_reg18 <= value;
8'd19: prev_reg19 <= value;
8'd20: prev_reg20 <= value;
8'd21: prev_reg21 <= value;
8'd22: prev_reg22 <= value;
8'd23: prev_reg23 <= value;
8'd24: prev_reg24 <= value;
8'd25: prev_reg25 <= value;
8'd26: prev_reg26 <= value;
8'd27: prev_reg27 <= value;
8'd28: prev_reg28 <= value;
8'd29: prev_reg29 <= value;
8'd30: prev_reg30 <= value;
8'd31: prev_reg31 <= value;
8'd32: prev_reg32 <= value;
8'd33: prev_reg33 <= value;
8'd34: prev_reg34 <= value;
8'd35: prev_reg35 <= value;
8'd36: prev_reg36 <= value;
8'd37: prev_reg37 <= value;
8'd38: prev_reg38 <= value;
8'd39: prev_reg39 <= value;
8'd40: prev_reg40 <= value;
8'd41: prev_reg41 <= value;
8'd42: prev_reg42 <= value;
8'd43: prev_reg43 <= value;
8'd44: prev_reg44 <= value;
8'd45: prev_reg45 <= value;
8'd46: prev_reg46 <= value;
8'd47: prev_reg47 <= value;
8'd48: prev_reg48 <= value;
8'd49: prev_reg49 <= value;
8'd50: prev_reg50 <= value;
8'd51: prev_reg51 <= value;
8'd52: prev_reg52 <= value;
8'd53: prev_reg53 <= value;
8'd54: prev_reg54 <= value;
8'd55: prev_reg55 <= value;
8'd56: prev_reg56 <= value;
8'd57: prev_reg57 <= value;
8'd58: prev_reg58 <= value;
8'd59: prev_reg59 <= value;
8'd60: prev_reg60 <= value;
8'd61: prev_reg61 <= value;
8'd62: prev_reg62 <= value;
8'd63: prev_reg63 <= value;
8'd64: prev_reg64 <= value;
8'd65: prev_reg65 <= value;
8'd66: prev_reg66 <= value;
8'd67: prev_reg67 <= value;
8'd68: prev_reg68 <= value;
8'd69: prev_reg69 <= value;
8'd70: prev_reg70 <= value;
8'd71: prev_reg71 <= value;
8'd72: prev_reg72 <= value;
8'd73: prev_reg73 <= value;
8'd74: prev_reg74 <= value;
8'd75: prev_reg75 <= value;
8'd76: prev_reg76 <= value;
8'd77: prev_reg77 <= value;
8'd78: prev_reg78 <= value;
8'd79: prev_reg79 <= value;
8'd80: prev_reg80 <= value;
8'd81: prev_reg81 <= value;
8'd82: prev_reg82 <= value;
8'd83: prev_reg83 <= value;
8'd84: prev_reg84 <= value;
8'd85: prev_reg85 <= value;
8'd86: prev_reg86 <= value;
8'd87: prev_reg87 <= value;
8'd88: prev_reg88 <= value;
8'd89: prev_reg89 <= value;
8'd90: prev_reg90 <= value;
8'd91: prev_reg91 <= value;
8'd92: prev_reg92 <= value;
8'd93: prev_reg93 <= value;
8'd94: prev_reg94 <= value;
8'd95: prev_reg95 <= value;
8'd96: prev_reg96 <= value;
8'd97: prev_reg97 <= value;
8'd98: prev_reg98 <= value;
8'd99: prev_reg99 <= value;
8'd100: prev_reg100 <= value;
8'd101: prev_reg101 <= value;
8'd102: prev_reg102 <= value;
8'd103: prev_reg103 <= value;
8'd104: prev_reg104 <= value;
8'd105: prev_reg105 <= value;
8'd106: prev_reg106 <= value;
8'd107: prev_reg107 <= value;
8'd108: prev_reg108 <= value;
8'd109: prev_reg109 <= value;
8'd110: prev_reg110 <= value;
8'd111: prev_reg111 <= value;
8'd112: prev_reg112 <= value;
8'd113: prev_reg113 <= value;
8'd114: prev_reg114 <= value;
8'd115: prev_reg115 <= value;
8'd116: prev_reg116 <= value;
8'd117: prev_reg117 <= value;
8'd118: prev_reg118 <= value;
8'd119: prev_reg119 <= value;
8'd120: prev_reg120 <= value;
8'd121: prev_reg121 <= value;
8'd122: prev_reg122 <= value;
8'd123: prev_reg123 <= value;
8'd124: prev_reg124 <= value;
8'd125: prev_reg125 <= value;
8'd126: prev_reg126 <= value;
8'd127: prev_reg127 <= value;
8'd128: prev_reg128 <= value;
8'd129: prev_reg129 <= value;
8'd130: prev_reg130 <= value;
8'd131: prev_reg131 <= value;
8'd132: prev_reg132 <= value;
8'd133: prev_reg133 <= value;
8'd134: prev_reg134 <= value;
8'd135: prev_reg135 <= value;
8'd136: prev_reg136 <= value;
8'd137: prev_reg137 <= value;
8'd138: prev_reg138 <= value;
8'd139: prev_reg139 <= value;
8'd140: prev_reg140 <= value;
8'd141: prev_reg141 <= value;
8'd142: prev_reg142 <= value;
8'd143: prev_reg143 <= value;
8'd144: prev_reg144 <= value;
8'd145: prev_reg145 <= value;
8'd146: prev_reg146 <= value;
8'd147: prev_reg147 <= value;
8'd148: prev_reg148 <= value;
8'd149: prev_reg149 <= value;
8'd150: prev_reg150 <= value;
8'd151: prev_reg151 <= value;
8'd152: prev_reg152 <= value;
8'd153: prev_reg153 <= value;
8'd154: prev_reg154 <= value;
8'd155: prev_reg155 <= value;
8'd156: prev_reg156 <= value;
8'd157: prev_reg157 <= value;
8'd158: prev_reg158 <= value;
8'd159: prev_reg159 <= value;
8'd160: prev_reg160 <= value;
8'd161: prev_reg161 <= value;
8'd162: prev_reg162 <= value;
8'd163: prev_reg163 <= value;
8'd164: prev_reg164 <= value;
8'd165: prev_reg165 <= value;
8'd166: prev_reg166 <= value;
8'd167: prev_reg167 <= value;
8'd168: prev_reg168 <= value;
8'd169: prev_reg169 <= value;
8'd170: prev_reg170 <= value;
8'd171: prev_reg171 <= value;
8'd172: prev_reg172 <= value;
8'd173: prev_reg173 <= value;
8'd174: prev_reg174 <= value;
8'd175: prev_reg175 <= value;
8'd176: prev_reg176 <= value;
8'd177: prev_reg177 <= value;
8'd178: prev_reg178 <= value;
8'd179: prev_reg179 <= value;
8'd180: prev_reg180 <= value;
8'd181: prev_reg181 <= value;
8'd182: prev_reg182 <= value;
8'd183: prev_reg183 <= value;
8'd184: prev_reg184 <= value;
8'd185: prev_reg185 <= value;
8'd186: prev_reg186 <= value;
8'd187: prev_reg187 <= value;
8'd188: prev_reg188 <= value;
8'd189: prev_reg189 <= value;
8'd190: prev_reg190 <= value;
8'd191: prev_reg191 <= value;
8'd192: prev_reg192 <= value;
8'd193: prev_reg193 <= value;
8'd194: prev_reg194 <= value;
8'd195: prev_reg195 <= value;
8'd196: prev_reg196 <= value;
8'd197: prev_reg197 <= value;
8'd198: prev_reg198 <= value;
8'd199: prev_reg199 <= value;
8'd200: prev_reg200 <= value;
8'd201: prev_reg201 <= value;
8'd202: prev_reg202 <= value;
8'd203: prev_reg203 <= value;
8'd204: prev_reg204 <= value;
8'd205: prev_reg205 <= value;
8'd206: prev_reg206 <= value;
8'd207: prev_reg207 <= value;
8'd208: prev_reg208 <= value;
8'd209: prev_reg209 <= value;
8'd210: prev_reg210 <= value;
8'd211: prev_reg211 <= value;
8'd212: prev_reg212 <= value;
8'd213: prev_reg213 <= value;
8'd214: prev_reg214 <= value;
8'd215: prev_reg215 <= value;
8'd216: prev_reg216 <= value;
8'd217: prev_reg217 <= value;
8'd218: prev_reg218 <= value;
8'd219: prev_reg219 <= value;
8'd220: prev_reg220 <= value;
8'd221: prev_reg221 <= value;
8'd222: prev_reg222 <= value;
8'd223: prev_reg223 <= value;
8'd224: prev_reg224 <= value;
8'd225: prev_reg225 <= value;
8'd226: prev_reg226 <= value;
8'd227: prev_reg227 <= value;
8'd228: prev_reg228 <= value;
8'd229: prev_reg229 <= value;
8'd230: prev_reg230 <= value;
8'd231: prev_reg231 <= value;
8'd232: prev_reg232 <= value;
8'd233: prev_reg233 <= value;
8'd234: prev_reg234 <= value;
8'd235: prev_reg235 <= value;
8'd236: prev_reg236 <= value;
8'd237: prev_reg237 <= value;
8'd238: prev_reg238 <= value;
8'd239: prev_reg239 <= value;
8'd240: prev_reg240 <= value;
8'd241: prev_reg241 <= value;
8'd242: prev_reg242 <= value;
8'd243: prev_reg243 <= value;
8'd244: prev_reg244 <= value;
8'd245: prev_reg245 <= value;
8'd246: prev_reg246 <= value;
8'd247: prev_reg247 <= value;
8'd248: prev_reg248 <= value;
8'd249: prev_reg249 <= value;
8'd250: prev_reg250 <= value;
8'd251: prev_reg251 <= value;
8'd252: prev_reg252 <= value;
8'd253: prev_reg253 <= value;
8'd254: prev_reg254 <= value;
8'd255: prev_reg255 <= value;
//----------------------------------------------------------
// Write Value to prev_reg using id as index (blocking)
8'd10: prev_reg10 = value;
8'd11: prev_reg11 = value;
8'd12: prev_reg12 = value;
8'd13: prev_reg13 = value;
8'd14: prev_reg14 = value;
8'd15: prev_reg15 = value;
8'd16: prev_reg16 = value;
8'd17: prev_reg17 = value;
8'd18: prev_reg18 = value;
8'd19: prev_reg19 = value;
8'd20: prev_reg20 = value;
8'd21: prev_reg21 = value;
8'd22: prev_reg22 = value;
8'd23: prev_reg23 = value;
8'd24: prev_reg24 = value;
8'd25: prev_reg25 = value;
8'd26: prev_reg26 = value;
8'd27: prev_reg27 = value;
8'd28: prev_reg28 = value;
8'd29: prev_reg29 = value;
8'd30: prev_reg30 = value;
8'd31: prev_reg31 = value;
8'd32: prev_reg32 = value;
8'd33: prev_reg33 = value;
8'd34: prev_reg34 = value;
8'd35: prev_reg35 = value;
8'd36: prev_reg36 = value;
8'd37: prev_reg37 = value;
8'd38: prev_reg38 = value;
8'd39: prev_reg39 = value;
8'd40: prev_reg40 = value;
8'd41: prev_reg41 = value;
8'd42: prev_reg42 = value;
8'd43: prev_reg43 = value;
8'd44: prev_reg44 = value;
8'd45: prev_reg45 = value;
8'd46: prev_reg46 = value;
8'd47: prev_reg47 = value;
8'd48: prev_reg48 = value;
8'd49: prev_reg49 = value;
8'd50: prev_reg50 = value;
8'd51: prev_reg51 = value;
8'd52: prev_reg52 = value;
8'd53: prev_reg53 = value;
8'd54: prev_reg54 = value;
8'd55: prev_reg55 = value;
8'd56: prev_reg56 = value;
8'd57: prev_reg57 = value;
8'd58: prev_reg58 = value;
8'd59: prev_reg59 = value;
8'd60: prev_reg60 = value;
8'd61: prev_reg61 = value;
8'd62: prev_reg62 = value;
8'd63: prev_reg63 = value;
8'd64: prev_reg64 = value;
8'd65: prev_reg65 = value;
8'd66: prev_reg66 = value;
8'd67: prev_reg67 = value;
8'd68: prev_reg68 = value;
8'd69: prev_reg69 = value;
8'd70: prev_reg70 = value;
8'd71: prev_reg71 = value;
8'd72: prev_reg72 = value;
8'd73: prev_reg73 = value;
8'd74: prev_reg74 = value;
8'd75: prev_reg75 = value;
8'd76: prev_reg76 = value;
8'd77: prev_reg77 = value;
8'd78: prev_reg78 = value;
8'd79: prev_reg79 = value;
8'd80: prev_reg80 = value;
8'd81: prev_reg81 = value;
8'd82: prev_reg82 = value;
8'd83: prev_reg83 = value;
8'd84: prev_reg84 = value;
8'd85: prev_reg85 = value;
8'd86: prev_reg86 = value;
8'd87: prev_reg87 = value;
8'd88: prev_reg88 = value;
8'd89: prev_reg89 = value;
8'd90: prev_reg90 = value;
8'd91: prev_reg91 = value;
8'd92: prev_reg92 = value;
8'd93: prev_reg93 = value;
8'd94: prev_reg94 = value;
8'd95: prev_reg95 = value;
8'd96: prev_reg96 = value;
8'd97: prev_reg97 = value;
8'd98: prev_reg98 = value;
8'd99: prev_reg99 = value;
8'd100: prev_reg100 = value;
8'd101: prev_reg101 = value;
8'd102: prev_reg102 = value;
8'd103: prev_reg103 = value;
8'd104: prev_reg104 = value;
8'd105: prev_reg105 = value;
8'd106: prev_reg106 = value;
8'd107: prev_reg107 = value;
8'd108: prev_reg108 = value;
8'd109: prev_reg109 = value;
8'd110: prev_reg110 = value;
8'd111: prev_reg111 = value;
8'd112: prev_reg112 = value;
8'd113: prev_reg113 = value;
8'd114: prev_reg114 = value;
8'd115: prev_reg115 = value;
8'd116: prev_reg116 = value;
8'd117: prev_reg117 = value;
8'd118: prev_reg118 = value;
8'd119: prev_reg119 = value;
8'd120: prev_reg120 = value;
8'd121: prev_reg121 = value;
8'd122: prev_reg122 = value;
8'd123: prev_reg123 = value;
8'd124: prev_reg124 = value;
8'd125: prev_reg125 = value;
8'd126: prev_reg126 = value;
8'd127: prev_reg127 = value;
8'd128: prev_reg128 = value;
8'd129: prev_reg129 = value;
8'd130: prev_reg130 = value;
8'd131: prev_reg131 = value;
8'd132: prev_reg132 = value;
8'd133: prev_reg133 = value;
8'd134: prev_reg134 = value;
8'd135: prev_reg135 = value;
8'd136: prev_reg136 = value;
8'd137: prev_reg137 = value;
8'd138: prev_reg138 = value;
8'd139: prev_reg139 = value;
8'd140: prev_reg140 = value;
8'd141: prev_reg141 = value;
8'd142: prev_reg142 = value;
8'd143: prev_reg143 = value;
8'd144: prev_reg144 = value;
8'd145: prev_reg145 = value;
8'd146: prev_reg146 = value;
8'd147: prev_reg147 = value;
8'd148: prev_reg148 = value;
8'd149: prev_reg149 = value;
8'd150: prev_reg150 = value;
8'd151: prev_reg151 = value;
8'd152: prev_reg152 = value;
8'd153: prev_reg153 = value;
8'd154: prev_reg154 = value;
8'd155: prev_reg155 = value;
8'd156: prev_reg156 = value;
8'd157: prev_reg157 = value;
8'd158: prev_reg158 = value;
8'd159: prev_reg159 = value;
8'd160: prev_reg160 = value;
8'd161: prev_reg161 = value;
8'd162: prev_reg162 = value;
8'd163: prev_reg163 = value;
8'd164: prev_reg164 = value;
8'd165: prev_reg165 = value;
8'd166: prev_reg166 = value;
8'd167: prev_reg167 = value;
8'd168: prev_reg168 = value;
8'd169: prev_reg169 = value;
8'd170: prev_reg170 = value;
8'd171: prev_reg171 = value;
8'd172: prev_reg172 = value;
8'd173: prev_reg173 = value;
8'd174: prev_reg174 = value;
8'd175: prev_reg175 = value;
8'd176: prev_reg176 = value;
8'd177: prev_reg177 = value;
8'd178: prev_reg178 = value;
8'd179: prev_reg179 = value;
8'd180: prev_reg180 = value;
8'd181: prev_reg181 = value;
8'd182: prev_reg182 = value;
8'd183: prev_reg183 = value;
8'd184: prev_reg184 = value;
8'd185: prev_reg185 = value;
8'd186: prev_reg186 = value;
8'd187: prev_reg187 = value;
8'd188: prev_reg188 = value;
8'd189: prev_reg189 = value;
8'd190: prev_reg190 = value;
8'd191: prev_reg191 = value;
8'd192: prev_reg192 = value;
8'd193: prev_reg193 = value;
8'd194: prev_reg194 = value;
8'd195: prev_reg195 = value;
8'd196: prev_reg196 = value;
8'd197: prev_reg197 = value;
8'd198: prev_reg198 = value;
8'd199: prev_reg199 = value;
8'd200: prev_reg200 = value;
8'd201: prev_reg201 = value;
8'd202: prev_reg202 = value;
8'd203: prev_reg203 = value;
8'd204: prev_reg204 = value;
8'd205: prev_reg205 = value;
8'd206: prev_reg206 = value;
8'd207: prev_reg207 = value;
8'd208: prev_reg208 = value;
8'd209: prev_reg209 = value;
8'd210: prev_reg210 = value;
8'd211: prev_reg211 = value;
8'd212: prev_reg212 = value;
8'd213: prev_reg213 = value;
8'd214: prev_reg214 = value;
8'd215: prev_reg215 = value;
8'd216: prev_reg216 = value;
8'd217: prev_reg217 = value;
8'd218: prev_reg218 = value;
8'd219: prev_reg219 = value;
8'd220: prev_reg220 = value;
8'd221: prev_reg221 = value;
8'd222: prev_reg222 = value;
8'd223: prev_reg223 = value;
8'd224: prev_reg224 = value;
8'd225: prev_reg225 = value;
8'd226: prev_reg226 = value;
8'd227: prev_reg227 = value;
8'd228: prev_reg228 = value;
8'd229: prev_reg229 = value;
8'd230: prev_reg230 = value;
8'd231: prev_reg231 = value;
8'd232: prev_reg232 = value;
8'd233: prev_reg233 = value;
8'd234: prev_reg234 = value;
8'd235: prev_reg235 = value;
8'd236: prev_reg236 = value;
8'd237: prev_reg237 = value;
8'd238: prev_reg238 = value;
8'd239: prev_reg239 = value;
8'd240: prev_reg240 = value;
8'd241: prev_reg241 = value;
8'd242: prev_reg242 = value;
8'd243: prev_reg243 = value;
8'd244: prev_reg244 = value;
8'd245: prev_reg245 = value;
8'd246: prev_reg246 = value;
8'd247: prev_reg247 = value;
8'd248: prev_reg248 = value;
8'd249: prev_reg249 = value;
8'd250: prev_reg250 = value;
8'd251: prev_reg251 = value;
8'd252: prev_reg252 = value;
8'd253: prev_reg253 = value;
8'd254: prev_reg254 = value;
8'd255: prev_reg255 = value;
//----------------------------------------------------------
// Read value frpm prev_reg using id as index
function [63:0] read_prev;
8'd0: read_prev = prev_reg0;
8'd1: read_prev = prev_reg1;
8'd2: read_prev = prev_reg2;
8'd3: read_prev = prev_reg3;
8'd4: read_prev = prev_reg4;
8'd5: read_prev = prev_reg5;
8'd6: read_prev = prev_reg6;
8'd7: read_prev = prev_reg7;
8'd8: read_prev = prev_reg8;
8'd9: read_prev = prev_reg9;
8'd10: read_prev = prev_reg10;
8'd11: read_prev = prev_reg11;
8'd12: read_prev = prev_reg12;
8'd13: read_prev = prev_reg13;
8'd14: read_prev = prev_reg14;
8'd15: read_prev = prev_reg15;
8'd16: read_prev = prev_reg16;
8'd17: read_prev = prev_reg17;
8'd18: read_prev = prev_reg18;
8'd19: read_prev = prev_reg19;
8'd20: read_prev = prev_reg20;
8'd21: read_prev = prev_reg21;
8'd22: read_prev = prev_reg22;
8'd23: read_prev = prev_reg23;
8'd24: read_prev = prev_reg24;
8'd25: read_prev = prev_reg25;
8'd26: read_prev = prev_reg26;
8'd27: read_prev = prev_reg27;
8'd28: read_prev = prev_reg28;
8'd29: read_prev = prev_reg29;
8'd30: read_prev = prev_reg30;
8'd31: read_prev = prev_reg31;
8'd32: read_prev = prev_reg32;
8'd33: read_prev = prev_reg33;
8'd34: read_prev = prev_reg34;
8'd35: read_prev = prev_reg35;
8'd36: read_prev = prev_reg36;
8'd37: read_prev = prev_reg37;
8'd38: read_prev = prev_reg38;
8'd39: read_prev = prev_reg39;
8'd40: read_prev = prev_reg40;
8'd41: read_prev = prev_reg41;
8'd42: read_prev = prev_reg42;
8'd43: read_prev = prev_reg43;
8'd44: read_prev = prev_reg44;
8'd45: read_prev = prev_reg45;
8'd46: read_prev = prev_reg46;
8'd47: read_prev = prev_reg47;
8'd48: read_prev = prev_reg48;
8'd49: read_prev = prev_reg49;
8'd50: read_prev = prev_reg50;
8'd51: read_prev = prev_reg51;
8'd52: read_prev = prev_reg52;
8'd53: read_prev = prev_reg53;
8'd54: read_prev = prev_reg54;
8'd55: read_prev = prev_reg55;
8'd56: read_prev = prev_reg56;
8'd57: read_prev = prev_reg57;
8'd58: read_prev = prev_reg58;
8'd59: read_prev = prev_reg59;
8'd60: read_prev = prev_reg60;
8'd61: read_prev = prev_reg61;
8'd62: read_prev = prev_reg62;
8'd63: read_prev = prev_reg63;
8'd64: read_prev = prev_reg64;
8'd65: read_prev = prev_reg65;
8'd66: read_prev = prev_reg66;
8'd67: read_prev = prev_reg67;
8'd68: read_prev = prev_reg68;
8'd69: read_prev = prev_reg69;
8'd70: read_prev = prev_reg70;
8'd71: read_prev = prev_reg71;
8'd72: read_prev = prev_reg72;
8'd73: read_prev = prev_reg73;
8'd74: read_prev = prev_reg74;
8'd75: read_prev = prev_reg75;
8'd76: read_prev = prev_reg76;
8'd77: read_prev = prev_reg77;
8'd78: read_prev = prev_reg78;
8'd79: read_prev = prev_reg79;
8'd80: read_prev = prev_reg80;
8'd81: read_prev = prev_reg81;
8'd82: read_prev = prev_reg82;
8'd83: read_prev = prev_reg83;
8'd84: read_prev = prev_reg84;
8'd85: read_prev = prev_reg85;
8'd86: read_prev = prev_reg86;
8'd87: read_prev = prev_reg87;
8'd88: read_prev = prev_reg88;
8'd89: read_prev = prev_reg89;
8'd90: read_prev = prev_reg90;
8'd91: read_prev = prev_reg91;
8'd92: read_prev = prev_reg92;
8'd93: read_prev = prev_reg93;
8'd94: read_prev = prev_reg94;
8'd95: read_prev = prev_reg95;
8'd96: read_prev = prev_reg96;
8'd97: read_prev = prev_reg97;
8'd98: read_prev = prev_reg98;
8'd99: read_prev = prev_reg99;
8'd100: read_prev = prev_reg100;
8'd101: read_prev = prev_reg101;
8'd102: read_prev = prev_reg102;
8'd103: read_prev = prev_reg103;
8'd104: read_prev = prev_reg104;
8'd105: read_prev = prev_reg105;
8'd106: read_prev = prev_reg106;
8'd107: read_prev = prev_reg107;
8'd108: read_prev = prev_reg108;
8'd109: read_prev = prev_reg109;
8'd110: read_prev = prev_reg110;
8'd111: read_prev = prev_reg111;
8'd112: read_prev = prev_reg112;
8'd113: read_prev = prev_reg113;
8'd114: read_prev = prev_reg114;
8'd115: read_prev = prev_reg115;
8'd116: read_prev = prev_reg116;
8'd117: read_prev = prev_reg117;
8'd118: read_prev = prev_reg118;
8'd119: read_prev = prev_reg119;
8'd120: read_prev = prev_reg120;
8'd121: read_prev = prev_reg121;
8'd122: read_prev = prev_reg122;
8'd123: read_prev = prev_reg123;
8'd124: read_prev = prev_reg124;
8'd125: read_prev = prev_reg125;
8'd126: read_prev = prev_reg126;
8'd127: read_prev = prev_reg127;
8'd128: read_prev = prev_reg128;
8'd129: read_prev = prev_reg129;
8'd130: read_prev = prev_reg130;
8'd131: read_prev = prev_reg131;
8'd132: read_prev = prev_reg132;
8'd133: read_prev = prev_reg133;
8'd134: read_prev = prev_reg134;
8'd135: read_prev = prev_reg135;
8'd136: read_prev = prev_reg136;
8'd137: read_prev = prev_reg137;
8'd138: read_prev = prev_reg138;
8'd139: read_prev = prev_reg139;
8'd140: read_prev = prev_reg140;
8'd141: read_prev = prev_reg141;
8'd142: read_prev = prev_reg142;
8'd143: read_prev = prev_reg143;
8'd144: read_prev = prev_reg144;
8'd145: read_prev = prev_reg145;
8'd146: read_prev = prev_reg146;
8'd147: read_prev = prev_reg147;
8'd148: read_prev = prev_reg148;
8'd149: read_prev = prev_reg149;
8'd150: read_prev = prev_reg150;
8'd151: read_prev = prev_reg151;
8'd152: read_prev = prev_reg152;
8'd153: read_prev = prev_reg153;
8'd154: read_prev = prev_reg154;
8'd155: read_prev = prev_reg155;
8'd156: read_prev = prev_reg156;
8'd157: read_prev = prev_reg157;
8'd158: read_prev = prev_reg158;
8'd159: read_prev = prev_reg159;
8'd160: read_prev = prev_reg160;
8'd161: read_prev = prev_reg161;
8'd162: read_prev = prev_reg162;
8'd163: read_prev = prev_reg163;
8'd164: read_prev = prev_reg164;
8'd165: read_prev = prev_reg165;
8'd166: read_prev = prev_reg166;
8'd167: read_prev = prev_reg167;
8'd168: read_prev = prev_reg168;
8'd169: read_prev = prev_reg169;
8'd170: read_prev = prev_reg170;
8'd171: read_prev = prev_reg171;
8'd172: read_prev = prev_reg172;
8'd173: read_prev = prev_reg173;
8'd174: read_prev = prev_reg174;
8'd175: read_prev = prev_reg175;
8'd176: read_prev = prev_reg176;
8'd177: read_prev = prev_reg177;
8'd178: read_prev = prev_reg178;
8'd179: read_prev = prev_reg179;
8'd180: read_prev = prev_reg180;
8'd181: read_prev = prev_reg181;
8'd182: read_prev = prev_reg182;
8'd183: read_prev = prev_reg183;
8'd184: read_prev = prev_reg184;
8'd185: read_prev = prev_reg185;
8'd186: read_prev = prev_reg186;
8'd187: read_prev = prev_reg187;
8'd188: read_prev = prev_reg188;
8'd189: read_prev = prev_reg189;
8'd190: read_prev = prev_reg190;
8'd191: read_prev = prev_reg191;
8'd192: read_prev = prev_reg192;
8'd193: read_prev = prev_reg193;
8'd194: read_prev = prev_reg194;
8'd195: read_prev = prev_reg195;
8'd196: read_prev = prev_reg196;
8'd197: read_prev = prev_reg197;
8'd198: read_prev = prev_reg198;
8'd199: read_prev = prev_reg199;
8'd200: read_prev = prev_reg200;
8'd201: read_prev = prev_reg201;
8'd202: read_prev = prev_reg202;
8'd203: read_prev = prev_reg203;
8'd204: read_prev = prev_reg204;
8'd205: read_prev = prev_reg205;
8'd206: read_prev = prev_reg206;
8'd207: read_prev = prev_reg207;
8'd208: read_prev = prev_reg208;
8'd209: read_prev = prev_reg209;
8'd210: read_prev = prev_reg210;
8'd211: read_prev = prev_reg211;
8'd212: read_prev = prev_reg212;
8'd213: read_prev = prev_reg213;
8'd214: read_prev = prev_reg214;
8'd215: read_prev = prev_reg215;
8'd216: read_prev = prev_reg216;
8'd217: read_prev = prev_reg217;
8'd218: read_prev = prev_reg218;
8'd219: read_prev = prev_reg219;
8'd220: read_prev = prev_reg220;
8'd221: read_prev = prev_reg221;
8'd222: read_prev = prev_reg222;
8'd223: read_prev = prev_reg223;
8'd224: read_prev = prev_reg224;
8'd225: read_prev = prev_reg225;
8'd226: read_prev = prev_reg226;
8'd227: read_prev = prev_reg227;
8'd228: read_prev = prev_reg228;
8'd229: read_prev = prev_reg229;
8'd230: read_prev = prev_reg230;
8'd231: read_prev = prev_reg231;
8'd232: read_prev = prev_reg232;
8'd233: read_prev = prev_reg233;
8'd234: read_prev = prev_reg234;
8'd235: read_prev = prev_reg235;
8'd236: read_prev = prev_reg236;
8'd237: read_prev = prev_reg237;
8'd238: read_prev = prev_reg238;
8'd239: read_prev = prev_reg239;
8'd240: read_prev = prev_reg240;
8'd241: read_prev = prev_reg241;
8'd242: read_prev = prev_reg242;
8'd243: read_prev = prev_reg243;
8'd244: read_prev = prev_reg244;
8'd245: read_prev = prev_reg245;
8'd246: read_prev = prev_reg246;
8'd247: read_prev = prev_reg247;
8'd248: read_prev = prev_reg248;
8'd249: read_prev = prev_reg249;
8'd250: read_prev = prev_reg250;
8'd251: read_prev = prev_reg251;
8'd252: read_prev = prev_reg252;
8'd253: read_prev = prev_reg253;
8'd254: read_prev = prev_reg254;
8'd255: read_prev = prev_reg255;
//----------------------------------------------------------
remap[4] = rd[4] ^ (rd[3] & oddwin);
//----------------------------------------------------------
// Initialize nas_pipe registers
initial begin : INIT_BLOCK
nas_pipe_enable = 1'b1; // Nas_pipe always enables itself
good_trap_detected = 1'b0;
@ (posedge `BENCH_SPC5_GCLK);
`TOP.th_last_act_cycle[mytnum] = 0;
`PR_INFO ("nas", `INFO, "T%0d Init shadow registers.",mytnum);
// POR for control registers
write_prev(`FPRS +`CTL_OFFSET,3'h4);
write_prev(`CLEANWIN +`CTL_OFFSET,3'h7);
write_prev(`CANSAVE +`CTL_OFFSET,3'h6);
write_prev(`FPRS+`CTL_OFFSET,3'h4);
// POR for PSTATE = 0x14 (PEF, PRIV = 1)
write_prev(`PSTATE + `CTL_OFFSET,'h14);
// POR for HPSTATE = 0x4034 (RED, HPRIV = 1)
write_prev(`HPSTATE + `CTL_OFFSET,'h24);
// POR for TL = = 0x6 [MAXTL]
write_prev(`TL + `CTL_OFFSET,'h6);
write_prev(`TT6 + `CTL_OFFSET,'h1);
// POR for GL = MAXGL = 3
write_prev(`GL + `CTL_OFFSET,`POR_GL);
// POR for VER = {003e, 0024, 01, 0036, 07}
write_prev(`VER + `CTL_OFFSET,{32'h003e0024,VER_reg[31:24],24'h030607});
// POR for *_cmpr registers is INT_DIS = 1
write_prev(`TICK_CMPR + `CTL_OFFSET,64'h8000000000000000);
write_prev(`STICK_CMPR + `CTL_OFFSET,64'h8000000000000000);
write_prev(`HSTICK_CMPR + `CTL_OFFSET,64'h8000000000000000);
// Need to define so that 1st instruction will print correctly
write_prev(`PC+`CTL_OFFSET,`POR_PC);
delta_prev[`PC_INDEX] = `BAD_PC;
irf_offset = (mytid%4)*32;
//----------------------------------------------------------
// For WMR, we will set to 0x0, so that initial deltas
// WMR for PSTATE = 0x14 (PEF, PRIV = 1)
// write_prev(`PSTATE + `CTL_OFFSET,'h00);
// WMR for HPSTATE = 0x4034 (RED, HPRIV = 1)
// write_prev(`HPSTATE + `CTL_OFFSET,'h00);
// WMR for TL = = 0x6 [MAXTL]
// write_prev(`TL + `CTL_OFFSET,'h0);
// write_prev(`TT6 + `CTL_OFFSET,'h1);
// WMR for GL = MAXGL = 3
// write_prev(`GL + `CTL_OFFSET,0);
//----------------------------------------------------------
// For POR, we will set to 0x0, so that initial deltas
// and prev state are all consistent with DUT. No values
`PR_ALWAYS ("arg", `ALWAYS,"T%0d Resetting Nas Pipe states for POR ..",mytnum);
delta_fx4[`NEXT_INDEX] <= `FIRST_INDEX;
delta_fx4[`FIRST_INDEX] <= 77'hx;
delta_fx5[`NEXT_INDEX] <= `FIRST_INDEX;
delta_fb[`NEXT_INDEX] <= `FIRST_INDEX;
delta_fw[`NEXT_INDEX] <= `FIRST_INDEX;
delta_fw1[`NEXT_INDEX] <= `FIRST_INDEX;
delta_fw2[`NEXT_INDEX] <= `FIRST_INDEX;
`PR_INFO ("nas", `INFO, "T%0d Init shadow registers.",mytnum);
// POR for control registers
write_prev(`FPRS +`CTL_OFFSET,3'h4);
write_prev(`CLEANWIN +`CTL_OFFSET,3'h7);
write_prev(`CANSAVE +`CTL_OFFSET,3'h6);
write_prev(`FPRS+`CTL_OFFSET,3'h4);
// POR for PSTATE = 0x14 (PEF, PRIV = 1)
write_prev(`PSTATE + `CTL_OFFSET,'h14);
// POR for HPSTATE = 0x4034 (RED, HPRIV = 1)
write_prev(`HPSTATE + `CTL_OFFSET,'h24);
// POR for TL = = 0x6 [MAXTL]
write_prev(`TL + `CTL_OFFSET,'h6);
write_prev(`TT6 + `CTL_OFFSET,'h1);
// POR for GL = MAXGL = 3
write_prev(`GL + `CTL_OFFSET,`POR_GL);
// POR for VER = {003e, 0024, 01, 0036, 07}
write_prev(`VER + `CTL_OFFSET,64'h003e002410030607);
// POR for *_cmpr registers is INT_DIS = 1
write_prev(`TICK_CMPR + `CTL_OFFSET,64'h8000000000000000);
write_prev(`STICK_CMPR + `CTL_OFFSET,64'h8000000000000000);
write_prev(`HSTICK_CMPR + `CTL_OFFSET,64'h8000000000000000);
// Need to define so that 1st instruction will print correctly
write_prev(`PC+`CTL_OFFSET,`POR_PC);
//----------------------------------------------------------
//----------------------------------------------------------
// Watch for Good/Bad trap
wire [5:0] mytnum = (mycid*8)+mytid;
// Delimiter changes whether flat or hierarchical netlist
wire myclk = tb_top.cpu.spc5.gclk;
wire dec_inst_valid_m = mytg ? tb_top.cpu.spc5.dec_inst_valid_m[1] : tb_top.cpu.spc5.dec_inst_valid_m[0];
wire [1:0] dec_tid_m = mytg ? tb_top.cpu.spc5.dec_tid1_m : tb_top.cpu.spc5.dec_tid0_m;
wire dec_flush_b = mytg ? tb_top.cpu.spc5.dec_flush_b[1] : tb_top.cpu.spc5.dec_flush_b[0];
wire tlu_flush_ifu = tb_top.cpu.spc5.tlu_flush_ifu[mytid];
wire [47:0] pc_d = mytg ? {tb_top.cpu.spc5.tlu_pc_1_d[47:2],2'b0} : {tb_top.cpu.spc5.tlu_pc_0_d[47:2],2'b0};
wire [31:0] op_d = mytg ? tb_top.cpu.spc5.dec_inst1_d[31:0] : tb_top.cpu.spc5.dec_inst0_d[31:0];
wire myclk = tb_top.cpu.spc5.gclk;
wire dec_inst_valid_m = mytg ? tb_top.cpu.spc5.dec_inst_valid_m[1] : tb_top.cpu.spc5.dec_inst_valid_m[0];
wire [1:0] dec_tid_m = mytg ? tb_top.cpu.spc5.dec_tid1_m : tb_top.cpu.spc5.dec_tid0_m;
wire dec_flush_b = mytg ? tb_top.cpu.spc5.dec_flush_b[1] : tb_top.cpu.spc5.dec_flush_b[0];
wire tlu_flush_ifu = tb_top.cpu.spc5.tlu_flush_ifu[mytid];
wire [47:0] pc_d = mytg ? {tb_top.cpu.spc5.tlu_pc_1_d[47:2],2'b0} : {tb_top.cpu.spc5.tlu_pc_0_d[47:2],2'b0};
wire [31:0] op_d = mytg ? tb_top.cpu.spc5.dec_inst1_d[31:0] : tb_top.cpu.spc5.dec_inst0_d[31:0];
wire inst_valid_b = dec_inst_valid_b && (dec_tid_b==mytid[1:0]) && !(dec_flush_b || tlu_flush_ifu);
always @ (posedge myclk) begin // {
dec_inst_valid_b <= dec_inst_valid_m;
inst_valid_w <= inst_valid_b;
inst_valid_fx4 <= inst_valid_w;
inst_valid_fx5 <= inst_valid_fx4;
inst_valid_fb <= inst_valid_fx5;
inst_valid_fw <= inst_valid_fb;
inst_valid_fw1 <= inst_valid_fw;
inst_valid_fw2 <= inst_valid_fw1;
if (`PARGS.th_check_enable[mytnum] && nas_pipe_enable) begin // {
if (inst_valid_fw2) begin // {
// Print PC/opcode for debugging
`PR_NORMAL ("nas", `NORMAL, "@%0d #%0d T%0d %h [%h]", $time, inst_count, mytnum, pc_fw2, op_fw2);
inst_count = inst_count + 1;
// End detection for GateSim runs
for (junk=0;junk<`PARGS.bad_trap_count;junk=junk+1) begin // {
if (({16'b0,pc_fw2}&`PC_MASK)===(`PARGS.bad_trap_addr[junk]&`PC_MASK)) begin // {
`PR_ERROR ("nas",`ERROR, "T%0d reached Bad Trap [GATESIM]", mytnum);
for (junk=0;junk<`PARGS.good_trap_count;junk=junk+1) begin // {
if (({16'b0,pc_fw2}&`PC_MASK)===(`PARGS.good_trap_addr[junk]&`PC_MASK)) begin // {
`TOP.finished_tids[mytnum] = 1'b1;
`PARGS.th_check_enable[mytnum] = 1'b0;
`PR_NORMAL ("nas", `NORMAL, "T%0d reached Good Trap. Disabling checking for thread %0d [GATESIM]", mytnum,mytnum);
//----------------------------------------------------------
//----------------------------------------------------------
//----------------------------------------------------------
input [71:0] TICK_CMPR_reg;
input [71:0] STICK_CMPR_reg;
input [71:0] HSTICK_CMPR_reg;
input [2:0] CANRESTORE_reg;
input [2:0] OTHERWIN_reg;
input [2:0] CLEANWIN_reg;
input [16:0] SOFTINT_reg;
input [16:0] rd_SOFTINT_reg;
input [63:0] INTR_RECEIVE_reg;
input [12:0] HPSTATE_reg;
input [63:0] CTXT_PRIM_0_reg;
input [63:0] CTXT_SEC_0_reg;
input [63:0] CTXT_PRIM_1_reg;
input [63:0] CTXT_SEC_1_reg;
input [63:0] LSU_CONTROL_reg;
input [63:0] I_TAG_ACC_reg;
input [63:0] D_TAG_ACC_reg;
input [63:0] WATCHPOINT_ADDR_reg;
input [151:0] Trap_Entry_1;
input [151:0] Trap_Entry_2;
input [151:0] Trap_Entry_3;
input [151:0] Trap_Entry_4;
input [151:0] Trap_Entry_5;
input [151:0] Trap_Entry_6;
input [1:0] frf_w2_valid;
input [1:0] frf_w1_valid;
input asi_valid; // ASI/ASR/PR writes done ..
input asi_in_progress; // ASI/ASR/PR in progess
//----------------------------------------------------------
//----------------------------------------------------------
//----------------------------------------------------------
// delta_* = {type(2bits),win(3bits),regnum(8bits),value(64bits)}
reg [`DELTA_WIDTH:0] delta_fx4 [0:(`MAX_INDEX)];
reg [`DELTA_WIDTH:0] delta_fx5 [0:(`MAX_INDEX)];
reg [`DELTA_WIDTH:0] delta_fb [0:(`MAX_INDEX)];
reg [`DELTA_WIDTH:0] delta_fw [0:(`MAX_INDEX)];
reg [`DELTA_WIDTH:0] delta_fw1 [0:(`MAX_INDEX)];
reg [`DELTA_WIDTH:0] delta_fw2 [0:(`MAX_INDEX)];
reg [`DELTA_WIDTH:0] delta_prev [0:(`MAX_INDEX)];
// need to change in several places in this file
reg [63:0] prev_reg0; // includes G,W,C,F registers
reg [63:0] prev_reg1; // includes G,W,C,F registers
reg [63:0] prev_reg2; // includes G,W,C,F registers
reg [63:0] prev_reg3; // includes G,W,C,F registers
reg [63:0] prev_reg4; // includes G,W,C,F registers
reg [63:0] prev_reg5; // includes G,W,C,F registers
reg [63:0] prev_reg6; // includes G,W,C,F registers
reg [63:0] prev_reg7; // includes G,W,C,F registers
reg [63:0] prev_reg8; // includes G,W,C,F registers
reg [63:0] prev_reg9; // includes G,W,C,F registers
reg [63:0] prev_reg10; // includes G,W,C,F registers
reg [63:0] prev_reg11; // includes G,W,C,F registers
reg [63:0] prev_reg12; // includes G,W,C,F registers
reg [63:0] prev_reg13; // includes G,W,C,F registers
reg [63:0] prev_reg14; // includes G,W,C,F registers
reg [63:0] prev_reg15; // includes G,W,C,F registers
reg [63:0] prev_reg16; // includes G,W,C,F registers
reg [63:0] prev_reg17; // includes G,W,C,F registers
reg [63:0] prev_reg18; // includes G,W,C,F registers
reg [63:0] prev_reg19; // includes G,W,C,F registers
reg [63:0] prev_reg20; // includes G,W,C,F registers
reg [63:0] prev_reg21; // includes G,W,C,F registers
reg [63:0] prev_reg22; // includes G,W,C,F registers
reg [63:0] prev_reg23; // includes G,W,C,F registers
reg [63:0] prev_reg24; // includes G,W,C,F registers
reg [63:0] prev_reg25; // includes G,W,C,F registers
reg [63:0] prev_reg26; // includes G,W,C,F registers
reg [63:0] prev_reg27; // includes G,W,C,F registers
reg [63:0] prev_reg28; // includes G,W,C,F registers
reg [63:0] prev_reg29; // includes G,W,C,F registers
reg [63:0] prev_reg30; // includes G,W,C,F registers
reg [63:0] prev_reg31; // includes G,W,C,F registers
reg [63:0] prev_reg32; // includes G,W,C,F registers
reg [63:0] prev_reg33; // includes G,W,C,F registers
reg [63:0] prev_reg34; // includes G,W,C,F registers
reg [63:0] prev_reg35; // includes G,W,C,F registers
reg [63:0] prev_reg36; // includes G,W,C,F registers
reg [63:0] prev_reg37; // includes G,W,C,F registers
reg [63:0] prev_reg38; // includes G,W,C,F registers
reg [63:0] prev_reg39; // includes G,W,C,F registers
reg [63:0] prev_reg40; // includes G,W,C,F registers
reg [63:0] prev_reg41; // includes G,W,C,F registers
reg [63:0] prev_reg42; // includes G,W,C,F registers
reg [63:0] prev_reg43; // includes G,W,C,F registers
reg [63:0] prev_reg44; // includes G,W,C,F registers
reg [63:0] prev_reg45; // includes G,W,C,F registers
reg [63:0] prev_reg46; // includes G,W,C,F registers
reg [63:0] prev_reg47; // includes G,W,C,F registers
reg [63:0] prev_reg48; // includes G,W,C,F registers
reg [63:0] prev_reg49; // includes G,W,C,F registers
reg [63:0] prev_reg50; // includes G,W,C,F registers
reg [63:0] prev_reg51; // includes G,W,C,F registers
reg [63:0] prev_reg52; // includes G,W,C,F registers
reg [63:0] prev_reg53; // includes G,W,C,F registers
reg [63:0] prev_reg54; // includes G,W,C,F registers
reg [63:0] prev_reg55; // includes G,W,C,F registers
reg [63:0] prev_reg56; // includes G,W,C,F registers
reg [63:0] prev_reg57; // includes G,W,C,F registers
reg [63:0] prev_reg58; // includes G,W,C,F registers
reg [63:0] prev_reg59; // includes G,W,C,F registers
reg [63:0] prev_reg60; // includes G,W,C,F registers
reg [63:0] prev_reg61; // includes G,W,C,F registers
reg [63:0] prev_reg62; // includes G,W,C,F registers
reg [63:0] prev_reg63; // includes G,W,C,F registers
reg [63:0] prev_reg64; // includes G,W,C,F registers
reg [63:0] prev_reg65; // includes G,W,C,F registers
reg [63:0] prev_reg66; // includes G,W,C,F registers
reg [63:0] prev_reg67; // includes G,W,C,F registers
reg [63:0] prev_reg68; // includes G,W,C,F registers
reg [63:0] prev_reg69; // includes G,W,C,F registers
reg [63:0] prev_reg70; // includes G,W,C,F registers
reg [63:0] prev_reg71; // includes G,W,C,F registers
reg [63:0] prev_reg72; // includes G,W,C,F registers
reg [63:0] prev_reg73; // includes G,W,C,F registers
reg [63:0] prev_reg74; // includes G,W,C,F registers
reg [63:0] prev_reg75; // includes G,W,C,F registers
reg [63:0] prev_reg76; // includes G,W,C,F registers
reg [63:0] prev_reg77; // includes G,W,C,F registers
reg [63:0] prev_reg78; // includes G,W,C,F registers
reg [63:0] prev_reg79; // includes G,W,C,F registers
reg [63:0] prev_reg80; // includes G,W,C,F registers
reg [63:0] prev_reg81; // includes G,W,C,F registers
reg [63:0] prev_reg82; // includes G,W,C,F registers
reg [63:0] prev_reg83; // includes G,W,C,F registers
reg [63:0] prev_reg84; // includes G,W,C,F registers
reg [63:0] prev_reg85; // includes G,W,C,F registers
reg [63:0] prev_reg86; // includes G,W,C,F registers
reg [63:0] prev_reg87; // includes G,W,C,F registers
reg [63:0] prev_reg88; // includes G,W,C,F registers
reg [63:0] prev_reg89; // includes G,W,C,F registers
reg [63:0] prev_reg90; // includes G,W,C,F registers
reg [63:0] prev_reg91; // includes G,W,C,F registers
reg [63:0] prev_reg92; // includes G,W,C,F registers
reg [63:0] prev_reg93; // includes G,W,C,F registers
reg [63:0] prev_reg94; // includes G,W,C,F registers
reg [63:0] prev_reg95; // includes G,W,C,F registers
reg [63:0] prev_reg96; // includes G,W,C,F registers
reg [63:0] prev_reg97; // includes G,W,C,F registers
reg [63:0] prev_reg98; // includes G,W,C,F registers
reg [63:0] prev_reg99; // includes G,W,C,F registers
reg [63:0] prev_reg100; // includes G,W,C,F registers
reg [63:0] prev_reg101; // includes G,W,C,F registers
reg [63:0] prev_reg102; // includes G,W,C,F registers
reg [63:0] prev_reg103; // includes G,W,C,F registers
reg [63:0] prev_reg104; // includes G,W,C,F registers
reg [63:0] prev_reg105; // includes G,W,C,F registers
reg [63:0] prev_reg106; // includes G,W,C,F registers
reg [63:0] prev_reg107; // includes G,W,C,F registers
reg [63:0] prev_reg108; // includes G,W,C,F registers
reg [63:0] prev_reg109; // includes G,W,C,F registers
reg [63:0] prev_reg110; // includes G,W,C,F registers
reg [63:0] prev_reg111; // includes G,W,C,F registers
reg [63:0] prev_reg112; // includes G,W,C,F registers
reg [63:0] prev_reg113; // includes G,W,C,F registers
reg [63:0] prev_reg114; // includes G,W,C,F registers
reg [63:0] prev_reg115; // includes G,W,C,F registers
reg [63:0] prev_reg116; // includes G,W,C,F registers
reg [63:0] prev_reg117; // includes G,W,C,F registers
reg [63:0] prev_reg118; // includes G,W,C,F registers
reg [63:0] prev_reg119; // includes G,W,C,F registers
reg [63:0] prev_reg120; // includes G,W,C,F registers
reg [63:0] prev_reg121; // includes G,W,C,F registers
reg [63:0] prev_reg122; // includes G,W,C,F registers
reg [63:0] prev_reg123; // includes G,W,C,F registers
reg [63:0] prev_reg124; // includes G,W,C,F registers
reg [63:0] prev_reg125; // includes G,W,C,F registers
reg [63:0] prev_reg126; // includes G,W,C,F registers
reg [63:0] prev_reg127; // includes G,W,C,F registers
reg [63:0] prev_reg128; // includes G,W,C,F registers
reg [63:0] prev_reg129; // includes G,W,C,F registers
reg [63:0] prev_reg130; // includes G,W,C,F registers
reg [63:0] prev_reg131; // includes G,W,C,F registers
reg [63:0] prev_reg132; // includes G,W,C,F registers
reg [63:0] prev_reg133; // includes G,W,C,F registers
reg [63:0] prev_reg134; // includes G,W,C,F registers
reg [63:0] prev_reg135; // includes G,W,C,F registers
reg [63:0] prev_reg136; // includes G,W,C,F registers
reg [63:0] prev_reg137; // includes G,W,C,F registers
reg [63:0] prev_reg138; // includes G,W,C,F registers
reg [63:0] prev_reg139; // includes G,W,C,F registers
reg [63:0] prev_reg140; // includes G,W,C,F registers
reg [63:0] prev_reg141; // includes G,W,C,F registers
reg [63:0] prev_reg142; // includes G,W,C,F registers
reg [63:0] prev_reg143; // includes G,W,C,F registers
reg [63:0] prev_reg144; // includes G,W,C,F registers
reg [63:0] prev_reg145; // includes G,W,C,F registers
reg [63:0] prev_reg146; // includes G,W,C,F registers
reg [63:0] prev_reg147; // includes G,W,C,F registers
reg [63:0] prev_reg148; // includes G,W,C,F registers
reg [63:0] prev_reg149; // includes G,W,C,F registers
reg [63:0] prev_reg150; // includes G,W,C,F registers
reg [63:0] prev_reg151; // includes G,W,C,F registers
reg [63:0] prev_reg152; // includes G,W,C,F registers
reg [63:0] prev_reg153; // includes G,W,C,F registers
reg [63:0] prev_reg154; // includes G,W,C,F registers
reg [63:0] prev_reg155; // includes G,W,C,F registers
reg [63:0] prev_reg156; // includes G,W,C,F registers
reg [63:0] prev_reg157; // includes G,W,C,F registers
reg [63:0] prev_reg158; // includes G,W,C,F registers
reg [63:0] prev_reg159; // includes G,W,C,F registers
reg [63:0] prev_reg160; // includes G,W,C,F registers
reg [63:0] prev_reg161; // includes G,W,C,F registers
reg [63:0] prev_reg162; // includes G,W,C,F registers
reg [63:0] prev_reg163; // includes G,W,C,F registers
reg [63:0] prev_reg164; // includes G,W,C,F registers
reg [63:0] prev_reg165; // includes G,W,C,F registers
reg [63:0] prev_reg166; // includes G,W,C,F registers
reg [63:0] prev_reg167; // includes G,W,C,F registers
reg [63:0] prev_reg168; // includes G,W,C,F registers
reg [63:0] prev_reg169; // includes G,W,C,F registers
reg [63:0] prev_reg170; // includes G,W,C,F registers
reg [63:0] prev_reg171; // includes G,W,C,F registers
reg [63:0] prev_reg172; // includes G,W,C,F registers
reg [63:0] prev_reg173; // includes G,W,C,F registers
reg [63:0] prev_reg174; // includes G,W,C,F registers
reg [63:0] prev_reg175; // includes G,W,C,F registers
reg [63:0] prev_reg176; // includes G,W,C,F registers
reg [63:0] prev_reg177; // includes G,W,C,F registers
reg [63:0] prev_reg178; // includes G,W,C,F registers
reg [63:0] prev_reg179; // includes G,W,C,F registers
reg [63:0] prev_reg180; // includes G,W,C,F registers
reg [63:0] prev_reg181; // includes G,W,C,F registers
reg [63:0] prev_reg182; // includes G,W,C,F registers
reg [63:0] prev_reg183; // includes G,W,C,F registers
reg [63:0] prev_reg184; // includes G,W,C,F registers
reg [63:0] prev_reg185; // includes G,W,C,F registers
reg [63:0] prev_reg186; // includes G,W,C,F registers
reg [63:0] prev_reg187; // includes G,W,C,F registers
reg [63:0] prev_reg188; // includes G,W,C,F registers
reg [63:0] prev_reg189; // includes G,W,C,F registers
reg [63:0] prev_reg190; // includes G,W,C,F registers
reg [63:0] prev_reg191; // includes G,W,C,F registers
reg [63:0] prev_reg192; // includes G,W,C,F registers
reg [63:0] prev_reg193; // includes G,W,C,F registers
reg [63:0] prev_reg194; // includes G,W,C,F registers
reg [63:0] prev_reg195; // includes G,W,C,F registers
reg [63:0] prev_reg196; // includes G,W,C,F registers
reg [63:0] prev_reg197; // includes G,W,C,F registers
reg [63:0] prev_reg198; // includes G,W,C,F registers
reg [63:0] prev_reg199; // includes G,W,C,F registers
reg [63:0] prev_reg200; // includes G,W,C,F registers
reg [63:0] prev_reg201; // includes G,W,C,F registers
reg [63:0] prev_reg202; // includes G,W,C,F registers
reg [63:0] prev_reg203; // includes G,W,C,F registers
reg [63:0] prev_reg204; // includes G,W,C,F registers
reg [63:0] prev_reg205; // includes G,W,C,F registers
reg [63:0] prev_reg206; // includes G,W,C,F registers
reg [63:0] prev_reg207; // includes G,W,C,F registers
reg [63:0] prev_reg208; // includes G,W,C,F registers
reg [63:0] prev_reg209; // includes G,W,C,F registers
reg [63:0] prev_reg210; // includes G,W,C,F registers
reg [63:0] prev_reg211; // includes G,W,C,F registers
reg [63:0] prev_reg212; // includes G,W,C,F registers
reg [63:0] prev_reg213; // includes G,W,C,F registers
reg [63:0] prev_reg214; // includes G,W,C,F registers
reg [63:0] prev_reg215; // includes G,W,C,F registers
reg [63:0] prev_reg216; // includes G,W,C,F registers
reg [63:0] prev_reg217; // includes G,W,C,F registers
reg [63:0] prev_reg218; // includes G,W,C,F registers
reg [63:0] prev_reg219; // includes G,W,C,F registers
reg [63:0] prev_reg220; // includes G,W,C,F registers
reg [63:0] prev_reg221; // includes G,W,C,F registers
reg [63:0] prev_reg222; // includes G,W,C,F registers
reg [63:0] prev_reg223; // includes G,W,C,F registers
reg [63:0] prev_reg224; // includes G,W,C,F registers
reg [63:0] prev_reg225; // includes G,W,C,F registers
reg [63:0] prev_reg226; // includes G,W,C,F registers
reg [63:0] prev_reg227; // includes G,W,C,F registers
reg [63:0] prev_reg228; // includes G,W,C,F registers
reg [63:0] prev_reg229; // includes G,W,C,F registers
reg [63:0] prev_reg230; // includes G,W,C,F registers
reg [63:0] prev_reg231; // includes G,W,C,F registers
reg [63:0] prev_reg232; // includes G,W,C,F registers
reg [63:0] prev_reg233; // includes G,W,C,F registers
reg [63:0] prev_reg234; // includes G,W,C,F registers
reg [63:0] prev_reg235; // includes G,W,C,F registers
reg [63:0] prev_reg236; // includes G,W,C,F registers
reg [63:0] prev_reg237; // includes G,W,C,F registers
reg [63:0] prev_reg238; // includes G,W,C,F registers
reg [63:0] prev_reg239; // includes G,W,C,F registers
reg [63:0] prev_reg240; // includes G,W,C,F registers
reg [63:0] prev_reg241; // includes G,W,C,F registers
reg [63:0] prev_reg242; // includes G,W,C,F registers
reg [63:0] prev_reg243; // includes G,W,C,F registers
reg [63:0] prev_reg244; // includes G,W,C,F registers
reg [63:0] prev_reg245; // includes G,W,C,F registers
reg [63:0] prev_reg246; // includes G,W,C,F registers
reg [63:0] prev_reg247; // includes G,W,C,F registers
reg [63:0] prev_reg248; // includes G,W,C,F registers
reg [63:0] prev_reg249; // includes G,W,C,F registers
reg [63:0] prev_reg250; // includes G,W,C,F registers
reg [63:0] prev_reg251; // includes G,W,C,F registers
reg [63:0] prev_reg252; // includes G,W,C,F registers
reg [63:0] prev_reg253; // includes G,W,C,F registers
reg [63:0] prev_reg254; // includes G,W,C,F registers
reg [63:0] prev_reg255; // includes G,W,C,F registers
reg [1:0] th_gl; // copy of GL_reg
reg frf_w1_skip_addr4_fw1;
reg frf_w1_skip_addr4_fw2;
reg [1:0] frf_w2_valid_fw;
reg [1:0] frf_w2_valid_bn;
reg [4:0] frf_w2_addr_fw;
reg [1:0] frf_w1_valid_fw;
reg [4:0] frf_w1_addr_fw;
reg wmr; // latched to get edge
reg por_a; // latched to get edge
reg por_b; // latched to get edge
reg nas_pipe_enable; // Turns on nas_pipe capture and Riesling SSTEP
wire [4:0] frf_w1_skip_addr;
wire [4:0] frf_w2_skip_addr;
reg good_trap_detected; // Used for -nosas only.
//----------------------------------------------------------
wire [`DELTA_WIDTH:0] delta_fx4_0;
wire [`DELTA_WIDTH:0] delta_fx4_1;
wire [`DELTA_WIDTH:0] delta_fx4_2;
wire [`DELTA_WIDTH:0] delta_fx4_3;
wire [`DELTA_WIDTH:0] delta_fx4_4;
wire [`DELTA_WIDTH:0] delta_fx4_5;
wire [`DELTA_WIDTH:0] delta_fx4_6;
wire [`DELTA_WIDTH:0] delta_fx4_7;
wire [`DELTA_WIDTH:0] delta_fx5_0;
wire [`DELTA_WIDTH:0] delta_fx5_1;
wire [`DELTA_WIDTH:0] delta_fx5_2;
wire [`DELTA_WIDTH:0] delta_fx5_3;
wire [`DELTA_WIDTH:0] delta_fx5_4;
wire [`DELTA_WIDTH:0] delta_fx5_5;
wire [`DELTA_WIDTH:0] delta_fx5_6;
wire [`DELTA_WIDTH:0] delta_fx5_7;
wire [`DELTA_WIDTH:0] delta_fb_0;
wire [`DELTA_WIDTH:0] delta_fb_1;
wire [`DELTA_WIDTH:0] delta_fb_2;
wire [`DELTA_WIDTH:0] delta_fb_3;
wire [`DELTA_WIDTH:0] delta_fb_4;
wire [`DELTA_WIDTH:0] delta_fb_5;
wire [`DELTA_WIDTH:0] delta_fb_6;
wire [`DELTA_WIDTH:0] delta_fb_7;
wire [`DELTA_WIDTH:0] delta_fw_0;
wire [`DELTA_WIDTH:0] delta_fw_1;
wire [`DELTA_WIDTH:0] delta_fw_2;
wire [`DELTA_WIDTH:0] delta_fw_3;
wire [`DELTA_WIDTH:0] delta_fw_4;
wire [`DELTA_WIDTH:0] delta_fw_5;
wire [`DELTA_WIDTH:0] delta_fw_6;
wire [`DELTA_WIDTH:0] delta_fw_7;
wire [`DELTA_WIDTH:0] delta_fw1_0;
wire [`DELTA_WIDTH:0] delta_fw1_1;
wire [`DELTA_WIDTH:0] delta_fw1_2;
wire [`DELTA_WIDTH:0] delta_fw1_3;
wire [`DELTA_WIDTH:0] delta_fw1_4;
wire [`DELTA_WIDTH:0] delta_fw1_5;
wire [`DELTA_WIDTH:0] delta_fw1_6;
wire [`DELTA_WIDTH:0] delta_fw1_7;
wire [`DELTA_WIDTH:0] delta_fw2_0;
wire [`DELTA_WIDTH:0] delta_fw2_1;
wire [`DELTA_WIDTH:0] delta_fw2_2;
wire [`DELTA_WIDTH:0] delta_fw2_3;
wire [`DELTA_WIDTH:0] delta_fw2_4;
wire [`DELTA_WIDTH:0] delta_fw2_5;
wire [`DELTA_WIDTH:0] delta_fw2_6;
wire [`DELTA_WIDTH:0] delta_fw2_7;
wire [`DELTA_WIDTH:0] delta_prev_0;
wire [`DELTA_WIDTH:0] delta_prev_1;
wire [`DELTA_WIDTH:0] delta_prev_2;
wire [`DELTA_WIDTH:0] delta_prev_3;
wire [`DELTA_WIDTH:0] delta_prev_4;
wire [`DELTA_WIDTH:0] delta_prev_5;
wire [`DELTA_WIDTH:0] delta_prev_6;
wire [`DELTA_WIDTH:0] delta_prev_7;
`PR_ALWAYS ("arg", `ALWAYS,"T%0d DEBUG_PIPE turned ON",mytnum);
//----------------------------------------------------------
// Note: no remap of %g,%o,%l,%i regs based on CWP or GL
assign g0 = (mytid<=3) ? `IRF6_EXU0[( 0+irf_offset)] : `IRF6_EXU1[( 0+irf_offset)];
assign g1 = (mytid<=3) ? `IRF6_EXU0[( 1+irf_offset)] : `IRF6_EXU1[( 1+irf_offset)];
assign g2 = (mytid<=3) ? `IRF6_EXU0[( 2+irf_offset)] : `IRF6_EXU1[( 2+irf_offset)];
assign g3 = (mytid<=3) ? `IRF6_EXU0[( 3+irf_offset)] : `IRF6_EXU1[( 3+irf_offset)];
assign g4 = (mytid<=3) ? `IRF6_EXU0[( 4+irf_offset)] : `IRF6_EXU1[( 4+irf_offset)];
assign g5 = (mytid<=3) ? `IRF6_EXU0[( 5+irf_offset)] : `IRF6_EXU1[( 5+irf_offset)];
assign g6 = (mytid<=3) ? `IRF6_EXU0[( 6+irf_offset)] : `IRF6_EXU1[( 6+irf_offset)];
assign g7 = (mytid<=3) ? `IRF6_EXU0[( 7+irf_offset)] : `IRF6_EXU1[( 7+irf_offset)];
assign o0 = (mytid<=3) ? `IRF6_EXU0[( 8+irf_offset)] : `IRF6_EXU1[( 8+irf_offset)];
assign o1 = (mytid<=3) ? `IRF6_EXU0[( 9+irf_offset)] : `IRF6_EXU1[( 9+irf_offset)];
assign o2 = (mytid<=3) ? `IRF6_EXU0[(10+irf_offset)] : `IRF6_EXU1[(10+irf_offset)];
assign o3 = (mytid<=3) ? `IRF6_EXU0[(11+irf_offset)] : `IRF6_EXU1[(11+irf_offset)];
assign o4 = (mytid<=3) ? `IRF6_EXU0[(12+irf_offset)] : `IRF6_EXU1[(12+irf_offset)];
assign o5 = (mytid<=3) ? `IRF6_EXU0[(13+irf_offset)] : `IRF6_EXU1[(13+irf_offset)];
assign o6 = (mytid<=3) ? `IRF6_EXU0[(14+irf_offset)] : `IRF6_EXU1[(14+irf_offset)];
assign o7 = (mytid<=3) ? `IRF6_EXU0[(15+irf_offset)] : `IRF6_EXU1[(15+irf_offset)];
assign l0 = (mytid<=3) ? `IRF6_EXU0[(16+irf_offset)] : `IRF6_EXU1[(16+irf_offset)];
assign l1 = (mytid<=3) ? `IRF6_EXU0[(17+irf_offset)] : `IRF6_EXU1[(17+irf_offset)];
assign l2 = (mytid<=3) ? `IRF6_EXU0[(18+irf_offset)] : `IRF6_EXU1[(18+irf_offset)];
assign l3 = (mytid<=3) ? `IRF6_EXU0[(19+irf_offset)] : `IRF6_EXU1[(19+irf_offset)];
assign l4 = (mytid<=3) ? `IRF6_EXU0[(20+irf_offset)] : `IRF6_EXU1[(20+irf_offset)];
assign l5 = (mytid<=3) ? `IRF6_EXU0[(21+irf_offset)] : `IRF6_EXU1[(21+irf_offset)];
assign l6 = (mytid<=3) ? `IRF6_EXU0[(22+irf_offset)] : `IRF6_EXU1[(22+irf_offset)];
assign l7 = (mytid<=3) ? `IRF6_EXU0[(23+irf_offset)] : `IRF6_EXU1[(23+irf_offset)];
assign i0 = (mytid<=3) ? `IRF6_EXU0[(24+irf_offset)] : `IRF6_EXU1[(24+irf_offset)];
assign i1 = (mytid<=3) ? `IRF6_EXU0[(25+irf_offset)] : `IRF6_EXU1[(25+irf_offset)];
assign i2 = (mytid<=3) ? `IRF6_EXU0[(26+irf_offset)] : `IRF6_EXU1[(26+irf_offset)];
assign i3 = (mytid<=3) ? `IRF6_EXU0[(27+irf_offset)] : `IRF6_EXU1[(27+irf_offset)];
assign i4 = (mytid<=3) ? `IRF6_EXU0[(28+irf_offset)] : `IRF6_EXU1[(28+irf_offset)];
assign i5 = (mytid<=3) ? `IRF6_EXU0[(29+irf_offset)] : `IRF6_EXU1[(29+irf_offset)];
assign i6 = (mytid<=3) ? `IRF6_EXU0[(30+irf_offset)] : `IRF6_EXU1[(30+irf_offset)];
assign i7 = (mytid<=3) ? `IRF6_EXU0[(31+irf_offset)] : `IRF6_EXU1[(31+irf_offset)];
//----------------------------------------------------------
assign frf_0 = `FRF6_EVEN[(mytid*32)+ 0];
assign frf_2 = `FRF6_EVEN[(mytid*32)+ 1];
assign frf_4 = `FRF6_EVEN[(mytid*32)+ 2];
assign frf_6 = `FRF6_EVEN[(mytid*32)+ 3];
assign frf_8 = `FRF6_EVEN[(mytid*32)+ 4];
assign frf_10 = `FRF6_EVEN[(mytid*32)+ 5];
assign frf_12 = `FRF6_EVEN[(mytid*32)+ 6];
assign frf_14 = `FRF6_EVEN[(mytid*32)+ 7];
assign frf_16 = `FRF6_EVEN[(mytid*32)+ 8];
assign frf_18 = `FRF6_EVEN[(mytid*32)+ 9];
assign frf_20 = `FRF6_EVEN[(mytid*32)+ 10];
assign frf_22 = `FRF6_EVEN[(mytid*32)+ 11];
assign frf_24 = `FRF6_EVEN[(mytid*32)+ 12];
assign frf_26 = `FRF6_EVEN[(mytid*32)+ 13];
assign frf_28 = `FRF6_EVEN[(mytid*32)+ 14];
assign frf_30 = `FRF6_EVEN[(mytid*32)+ 15];
assign frf_32 = `FRF6_EVEN[(mytid*32)+ 16];
assign frf_34 = `FRF6_EVEN[(mytid*32)+ 17];
assign frf_36 = `FRF6_EVEN[(mytid*32)+ 18];
assign frf_38 = `FRF6_EVEN[(mytid*32)+ 19];
assign frf_40 = `FRF6_EVEN[(mytid*32)+ 20];
assign frf_42 = `FRF6_EVEN[(mytid*32)+ 21];
assign frf_44 = `FRF6_EVEN[(mytid*32)+ 22];
assign frf_46 = `FRF6_EVEN[(mytid*32)+ 23];
assign frf_48 = `FRF6_EVEN[(mytid*32)+ 24];
assign frf_50 = `FRF6_EVEN[(mytid*32)+ 25];
assign frf_52 = `FRF6_EVEN[(mytid*32)+ 26];
assign frf_54 = `FRF6_EVEN[(mytid*32)+ 27];
assign frf_56 = `FRF6_EVEN[(mytid*32)+ 28];
assign frf_58 = `FRF6_EVEN[(mytid*32)+ 29];
assign frf_60 = `FRF6_EVEN[(mytid*32)+ 30];
assign frf_62 = `FRF6_EVEN[(mytid*32)+ 31];
assign frf_1 = `FRF6_ODD[(mytid*32)+ 0];
assign frf_3 = `FRF6_ODD[(mytid*32)+ 1];
assign frf_5 = `FRF6_ODD[(mytid*32)+ 2];
assign frf_7 = `FRF6_ODD[(mytid*32)+ 3];
assign frf_9 = `FRF6_ODD[(mytid*32)+ 4];
assign frf_11 = `FRF6_ODD[(mytid*32)+ 5];
assign frf_13 = `FRF6_ODD[(mytid*32)+ 6];
assign frf_15 = `FRF6_ODD[(mytid*32)+ 7];
assign frf_17 = `FRF6_ODD[(mytid*32)+ 8];
assign frf_19 = `FRF6_ODD[(mytid*32)+ 9];
assign frf_21 = `FRF6_ODD[(mytid*32)+ 10];
assign frf_23 = `FRF6_ODD[(mytid*32)+ 11];
assign frf_25 = `FRF6_ODD[(mytid*32)+ 12];
assign frf_27 = `FRF6_ODD[(mytid*32)+ 13];
assign frf_29 = `FRF6_ODD[(mytid*32)+ 14];
assign frf_31 = `FRF6_ODD[(mytid*32)+ 15];
assign frf_33 = `FRF6_ODD[(mytid*32)+ 16];
assign frf_35 = `FRF6_ODD[(mytid*32)+ 17];
assign frf_37 = `FRF6_ODD[(mytid*32)+ 18];
assign frf_39 = `FRF6_ODD[(mytid*32)+ 19];
assign frf_41 = `FRF6_ODD[(mytid*32)+ 20];
assign frf_43 = `FRF6_ODD[(mytid*32)+ 21];
assign frf_45 = `FRF6_ODD[(mytid*32)+ 22];
assign frf_47 = `FRF6_ODD[(mytid*32)+ 23];
assign frf_49 = `FRF6_ODD[(mytid*32)+ 24];
assign frf_51 = `FRF6_ODD[(mytid*32)+ 25];
assign frf_53 = `FRF6_ODD[(mytid*32)+ 26];
assign frf_55 = `FRF6_ODD[(mytid*32)+ 27];
assign frf_57 = `FRF6_ODD[(mytid*32)+ 28];
assign frf_59 = `FRF6_ODD[(mytid*32)+ 29];
assign frf_61 = `FRF6_ODD[(mytid*32)+ 30];
assign frf_63 = `FRF6_ODD[(mytid*32)+ 31];
//----------------------------------------------------------
assign delta_fx4_0 = delta_fx4[0];
assign delta_fx4_1 = delta_fx4[1];
assign delta_fx4_2 = delta_fx4[2];
assign delta_fx4_3 = delta_fx4[3];
assign delta_fx4_4 = delta_fx4[4];
assign delta_fx4_5 = delta_fx4[5];
assign delta_fx4_6 = delta_fx4[6];
assign delta_fx4_7 = delta_fx4[7];
assign delta_fx5_0 = delta_fx5[0];
assign delta_fx5_1 = delta_fx5[1];
assign delta_fx5_2 = delta_fx5[2];
assign delta_fx5_3 = delta_fx5[3];
assign delta_fx5_4 = delta_fx5[4];
assign delta_fx5_5 = delta_fx5[5];
assign delta_fx5_6 = delta_fx5[6];
assign delta_fx5_7 = delta_fx5[7];
assign delta_fb_0 = delta_fb[0];
assign delta_fb_1 = delta_fb[1];
assign delta_fb_2 = delta_fb[2];
assign delta_fb_3 = delta_fb[3];
assign delta_fb_4 = delta_fb[4];
assign delta_fb_5 = delta_fb[5];
assign delta_fb_6 = delta_fb[6];
assign delta_fb_7 = delta_fb[7];
assign delta_fw_0 = delta_fw[0];
assign delta_fw_1 = delta_fw[1];
assign delta_fw_2 = delta_fw[2];
assign delta_fw_3 = delta_fw[3];
assign delta_fw_4 = delta_fw[4];
assign delta_fw_5 = delta_fw[5];
assign delta_fw_6 = delta_fw[6];
assign delta_fw_7 = delta_fw[7];
assign delta_fw1_0 = delta_fw1[0];
assign delta_fw1_1 = delta_fw1[1];
assign delta_fw1_2 = delta_fw1[2];
assign delta_fw1_3 = delta_fw1[3];
assign delta_fw1_4 = delta_fw1[4];
assign delta_fw1_5 = delta_fw1[5];
assign delta_fw1_6 = delta_fw1[6];
assign delta_fw1_7 = delta_fw1[7];
assign delta_fw2_0 = delta_fw2[0];
assign delta_fw2_1 = delta_fw2[1];
assign delta_fw2_2 = delta_fw2[2];
assign delta_fw2_3 = delta_fw2[3];
assign delta_fw2_4 = delta_fw2[4];
assign delta_fw2_5 = delta_fw2[5];
assign delta_fw2_6 = delta_fw2[6];
assign delta_fw2_7 = delta_fw2[7];
assign delta_prev_0 = delta_prev[0];
assign delta_prev_1 = delta_prev[1];
assign delta_prev_2 = delta_prev[2];
assign delta_prev_3 = delta_prev[3];
assign delta_prev_4 = delta_prev[4];
assign delta_prev_5 = delta_prev[5];
assign delta_prev_6 = delta_prev[6];
assign delta_prev_7 = delta_prev[7];
//----------------------------------------------------------
//----------------------------------------------------------
assign mytnum = (mycid*8)+mytid;
assign mytg = mytid >> 2;
assign exu_complete = exu_valid & ~(`PROBES6.clkstop_d5|`TOP.in_reset|`SPC6.tcu_scan_en);
assign imul_complete = imul_valid & ~(`TOP.in_reset|`SPC6.tcu_scan_en);
assign idiv_complete = idiv_valid & ~(`TOP.in_reset|`SPC6.tcu_scan_en);
assign tlu_complete = tlu_complete_3 ;
assign fp_complete = fp_valid & ~(`TOP.in_reset|`SPC6.tcu_scan_en);
assign fdiv_complete = fdiv_valid & ~(`TOP.in_reset|`SPC6.tcu_scan_en);
assign lsu_complete = lsu_valid & ~(`TOP.in_reset|`SPC6.tcu_scan_en);
assign asi_complete = asi_valid & ~(`TOP.in_reset|`SPC6.tcu_scan_en);
assign complete_w = (exu_complete << `EXU_INDEX) |
(lsu_complete << `LSU_INDEX) |
(tlu_complete << `TLU_INDEX) |
(asi_complete << `ASI_INDEX) ;
assign oddwin = CWP_reg % 2;
assign frf_w1_valid_even = (frf_w1_tid_fw == mytid) & frf_w1_valid_fw[1];
assign frf_w1_valid_odd = (frf_w1_tid_fw == mytid) & frf_w1_valid_fw[0];
assign frf_w2_valid_even = (frf_w2_tid_fw == mytid) & frf_w2_valid_fw[1];
assign frf_w2_valid_odd = (frf_w2_tid_fw == mytid) & frf_w2_valid_fw[0];
assign frf_w1_skip_addr = frf_w1_addr_fw;
assign frf_w2_skip_addr = frf_w2_addr_fw;
// NOTE - ADD_TSB_CFG will never be used for Axis or Tharas
wire [63:0] ctxt_z_tsb_cfg0_reg = `PROBES6.ctxt_z_tsb_cfg0_reg[mytid];
wire [63:0] ctxt_z_tsb_cfg1_reg = `PROBES6.ctxt_z_tsb_cfg1_reg[mytid];
wire [63:0] ctxt_z_tsb_cfg2_reg = `PROBES6.ctxt_z_tsb_cfg2_reg[mytid];
wire [63:0] ctxt_z_tsb_cfg3_reg = `PROBES6.ctxt_z_tsb_cfg3_reg[mytid];
wire [63:0] ctxt_nz_tsb_cfg0_reg = `PROBES6.ctxt_nz_tsb_cfg0_reg[mytid];
wire [63:0] ctxt_nz_tsb_cfg1_reg = `PROBES6.ctxt_nz_tsb_cfg1_reg[mytid];
wire [63:0] ctxt_nz_tsb_cfg2_reg = `PROBES6.ctxt_nz_tsb_cfg2_reg[mytid];
wire [63:0] ctxt_nz_tsb_cfg3_reg = `PROBES6.ctxt_nz_tsb_cfg3_reg[mytid];
//----------------------------------------------------------
always @ (posedge `BENCH_SPC6_GCLK) begin // {
// TLU is async to the execution pipeline
// but needs to be delayed to allow CWP, etc to update and be stable
// before arch state is captured and diff_reg is called.
// FDIV was moved from fw1 to fw to allow FPRS to be stable before capture
tlu_complete_1 <= tlu_valid & ~(`TOP.in_reset|`SPC6.tcu_scan_en);
tlu_complete_2 <= tlu_complete_1;
tlu_complete_3 <= tlu_complete_2;
itagacc_fx5 <= I_TAG_ACC_reg; // Signal changes in W so need to pipeline to fw2
itagacc_fb <= itagacc_fx5;
itagacc_fw <= itagacc_fb;
itagacc_fw1 <= itagacc_fw;
itagacc_fw2 <= itagacc_fw1;
dtagacc_fx5 <= D_TAG_ACC_reg; // Signal changes in W so need to pipeline to fw2
dtagacc_fb <= dtagacc_fx5;
dtagacc_fw <= dtagacc_fb;
dtagacc_fw1 <= dtagacc_fw;
dtagacc_fw2 <= dtagacc_fw1;
dsfar_fb <= DSFAR_reg; // Signal changes in W+1 so need to pipeline to fw2
complete_fx4 <= complete_w;
complete_fx5 <= complete_fx4 ;
complete_fb <= complete_fx5 |
(idiv_complete << `IDIV_INDEX);
complete_fw <= complete_fb |
(fdiv_complete << `FDIV_INDEX) |
(imul_complete << `IMUL_INDEX);
complete_fw1 <= complete_fw |
(fp_complete << `FP_INDEX);
complete_fw2 <= complete_fw1;
frf_w1_valid_fw1 <= (frf_w1_valid_odd | frf_w1_valid_even) & fp_complete;
frf_w1_valid_fw2 <= frf_w1_valid_fw1;
frf_w1_skip_addr4_fw1 <= frf_w1_skip_addr[4];
frf_w1_skip_addr4_fw2 <= frf_w1_skip_addr4_fw1;
frf_w2_valid_fw <= frf_w2_valid_bn;
frf_w2_tid_fw <= frf_w2_tid;
frf_w2_addr_fw <= frf_w2_addr;
frf_w1_valid_fw <= frf_w1_valid;
frf_w1_tid_fw <= frf_w1_tid;
frf_w1_addr_fw <= frf_w1_addr;
if (~thread_running & `SPC6.tcu_core_running[mytid])
`TOP.th_last_act_cycle[mytnum] = `TOP.core_cycle_cnt;
thread_running <= `SPC6.tcu_core_running[mytid];
// Reset some register prev state on wmr negation
if (`SPC6.rst_wmr_protect && ~wmr)
wmr <= `SPC6.rst_wmr_protect;
if (`SPC6.rst_wmr_protect)
//----------------------------------------------------------
// Holding state for registers that may be updated asynchronously
// after synchronous update, but before capture/step. Also for reads,
// when register is read and modified before capture/step ..
// We capture the value /write time, and use that for sstep,
// ignoring any async updates, which are sent in the NEXT sstep ..
reg [63:0] asi_updated_int_rec;
reg asi_wr_int_rec_delay;
reg [16:0] asi_updated_softint;
reg asi_wr_softint_delay;
reg [16:0] asi_softint_wrdata;
always @(posedge `BENCH_SPC6_GCLK) begin // {
// Corner case : If async and sync wr occur in same clock, then the async
// update takes place. In this case we have to capture the
// value of the write WITHOUT async bit being set, so that
// we can sync with Riesling's sync write ..
asi_wr_int_rec_delay <= ( `SPC6.tlu.cth.asi_wr_int_rec[mytid] |
`SPC6.tlu.asi_rd_inc_vec_2[mytid]);
if (`SPC6.tlu.cth.asi_wr_int_rec[mytid] |
((`SPC6.tlu.asi.rd_inc_vec) &&
(`SPC6.tlu.asi.rd_tid_dec[mytid])) |
(`SPC6.tlu.asi_rd_int_rec &
`SPC6.tlu.cth.int_rec_mux_sel==mytid))
if (`SPC6.tlu.cth.asi_wr_int_rec[mytid])
asi_updated_int_rec <= `SPC6.tlu.cth.int_rec ;
else if ( (`SPC6.tlu.asi.rd_inc_vec) &&
(`SPC6.tlu.asi.rd_tid_dec[mytid]) )
if (`SPC6.tlu.cth.cxi_wr_int_dis[mytid]) begin
asi_updated_int_rec <= INTR_RECEIVE_reg & `SPC6.tlu.cth.int_rec_muxed_;
asi_updated_int_rec[`SPC6.tlu.cth.incoming_vector_in] <= 1'b0 ;
asi_updated_int_rec <= `SPC6.tlu.cth.int_rec_muxed ;
asi_updated_int_rec[`SPC6.tlu.cth.incoming_vector_in] <= 1'b0 ;
asi_updated_int_rec <= INTR_RECEIVE_reg;
asi_rdwr_int_rec <= 1'b1;
else if (complete_fw1 && !`NASTOP.sstep_early[mytnum])
asi_rdwr_int_rec <= 1'b0;
asi_wr_hintp_delay <= `SPC6.tlu.asi_wr_hintp[mytid];
if (`SPC6.tlu.asi_wr_hintp[mytid] |
`SPC6.tlu.asi_rd_hintp[mytid])
if (`SPC6.tlu.asi_wr_hintp[mytid])
asi_updated_hintp <= `SPC6.tlu.asi_wr_data_0[0] ;
asi_updated_hintp <= HINTP_reg;
else if (complete_fw1 && !`NASTOP.sstep_early[mytnum])
asi_wr_softint_delay <= (`SPC6.tlu.asi_wr_softint[mytid] |
`SPC6.tlu.asi_wr_clear_softint[mytid] |
`SPC6.tlu.asi_wr_set_softint[mytid]);
if (`SPC6.tlu.asi_wr_clear_softint[mytid])
asi_softint_wrdata <= ~`SPC6.tlu.asi_wr_data_0[16:0] & rd_SOFTINT_reg;
else if (`SPC6.tlu.asi_wr_set_softint[mytid])
asi_softint_wrdata <= `SPC6.tlu.asi_wr_data_0[16:0] | rd_SOFTINT_reg;
asi_softint_wrdata <= `SPC6.tlu.asi_wr_data_0[16:0];
if (asi_wr_softint_delay | `SPC6.tlu.asi_rd_softint[mytid])
if (asi_wr_softint_delay)
asi_updated_softint <= asi_softint_wrdata ;
asi_updated_softint <= rd_SOFTINT_reg ;
asi_rdwr_softint <= 1'b1;
else if (complete_fw1 && !`NASTOP.sstep_early[mytnum])
asi_rdwr_softint <= 1'b0;
//----------------------------------------------------------
// Negedge sampling to avoid race on specific signals ..
always @ (negedge `BENCH_SPC6_GCLK) begin // {
frf_w2_valid_bn <= frf_w2_valid;
//----------------------------------------------------------
// When instruction completes,
// Push differences to simics
always @ (posedge `BENCH_SPC6_GCLK) begin // {
if (`PARGS.th_check_enable[mytnum] && nas_pipe_enable && ~`SPC6.tcu_scan_en && ~`TOP.in_por) begin // {
// Update window registers
if (CWP_reg != `NASTOP.th_cwp[mytnum]) begin // {
copy_win (CWP_reg,`NASTOP.th_cwp[mytnum]);
`NASTOP.th_cwp[mytnum] = CWP_reg;
// Update global registers
// Wait for warm-reset flush related toggling to settle
if (GL_reg != th_gl) begin // {
if (`SPC6.spc_core_running_status[mytid] &
~`SPC6.rst_wmr_protect) begin // {
copy_global (GL_reg,th_gl);
// Check for bad signal values
// if NASTOP.sstep_sent[tid]=1,
// then SSTEP was set by another module (i.e. tlb_sync)
if (`PARGS.nas_check_on) begin // {
mytime = `TOP.core_cycle_cnt-1;
if (complete_fw2 && (`NASTOP.sstep_sent[mytnum]==1'b0)) begin // {
`PR_INFO ("pli_nas", `INFO, " C%0d T%0d PLI_SSTEP tid=%d pc=%h ts=%0d ",
mycid,mytid,mytnum,pc_fw2,mytime);
junk = $sim_send(`PLI_SSTEP, mytnum);
// Always clear sstep_early
// In case tlb_sync asserted it too late for complete_fw2
`NASTOP.sstep_early[mytnum] <= 1'b0;
else if (complete_fw2) begin // {
`NASTOP.sstep_sent[mytnum] <= 1'b0; // re-arm SSTEP
`NASTOP.sstep_early[mytnum] <= 1'b0;
`PR_INFO ("pli_nas", `INFO, " C%0d T%0d PLI_SSTEP tid=%d pc=%h ts=%0d (nas_pipe: skip sstep. rearm sstep. sstep_sent=0)",
mycid,mytid,mytnum,pc_fw2,mytime);
// Only capture if something completes and not first instruction
if (complete_fw2 && !first_op) begin // {
push_simics; // Use with AXIS to keep from getting timeout
// Pipeline runs continuously
// Other than when in POR ..
// Only save to delta_prev when something completes
`TOP.last_act_cycle = `TOP.core_cycle_cnt; //$time;
`TOP.th_last_act_cycle[mytnum] = `TOP.last_act_cycle;
// If something was captured but no instruction is in the pipeline
if ((delta_fw2[`NEXT_INDEX]!=`FIRST_INDEX) && (complete_fw2 == 0))
for (myindex=`FIRST_INDEX; myindex<delta_fw2[`NEXT_INDEX]; myindex=myindex+1)
print_entry (delta_fw2[myindex]);
`PR_ERROR ("nas",`ERROR, "T%0d Unexpected Reg change in DUT. Special case - no instruction retired.", mytnum);
// End detection for non-sas runs ..
for (junk=0;junk<`PARGS.bad_trap_count;junk=junk+1)
if (({16'b0,pc_fw2}&`PC_MASK) ===
(`PARGS.bad_trap_addr[junk]&`PC_MASK)) begin // {
// Disable nas_pipe processing (capture & SSTEP)
// to speed up simulation (minimize socket traffic,etc)
if (! `PARGS.nas_check_on) begin //{
`PR_ERROR ("nas",`ERROR, "T%0d reached Bad Trap", mytnum);
for (junk=0;junk<`PARGS.good_trap_count;junk=junk+1)
if ((|complete_fw2) && (({16'b0,pc_fw2}&`PC_MASK) ===
(`PARGS.good_trap_addr[junk]&`PC_MASK))) begin // {
// Disable nas_pipe processing (capture & SSTEP)
// to speed up simulation (minimize socket traffic,etc)
if (! `PARGS.nas_check_on) begin //{
good_trap_detected = 1'b1;
// Check Thread level timeout
(`TOP.core_cycle_cnt - `TOP.th_last_act_cycle[mytnum]) > `PARGS.th_timeout)
// Note: Do not change this message because regreport parses it for certain words.
`PR_ALWAYS ("nas",`ALWAYS, "ERROR: Thread T%0d No Activity for %0d Cycles - Thread TIMEOUT!",
mytnum, `PARGS.th_timeout);
junk = incErr(9999); // must exceed users max error setting to force exit.
end // if (`PARGS.th_check_enable[mytnum] && nas_pipe_enable ...)}
// Need to make sure Store Buffer is empty before turning off th_check_enable.
//global chkr requires to wait for all outstanding pending I
if ((! `PARGS.nas_check_on) &&
(good_trap_detected==1'b1) &&
(`TOP.nas_top.lsu_stb_empty[mytnum]) && `TOP.nas_top.ireq_pending[mytnum]) begin // {
`PARGS.th_check_enable[mytnum] = 1'b0;
`TOP.finished_tids[mytnum] = 1'b1;
good_trap_detected = 1'b0;
`PR_NORMAL ("nas", `NORMAL, "T%0d reached Good Trap. Disabling checking for thread %0d", mytnum,mytnum);
//----------------------------------------------------------
//----------------------------------------------------------
// Stage FX4 of delta pipeline
delta_fx4[`NEXT_INDEX] <= `FIRST_INDEX;
delta_fx4[`TIME_INDEX] <= 0;
delta_fx4[`PC_INDEX] <= {16'b0,PC_reg};
delta_fx4[`GL_INDEX] <= GL_reg;
delta_fx4[`CWP_INDEX] <= CWP_reg;
delta_fx4[`OPCODE_INDEX] <= opcode;
delta_fx4[`FIRST_INDEX] <= 77'hx;
//----------------------------------------------------------
// Stage FX5 of delta pipeline
index = delta_fx4[`NEXT_INDEX];
// Pipeline previous stage
for (i=0; i<=delta_fx4[`NEXT_INDEX]; i=i+1) begin // {
delta_fx5[i] <= delta_fx4[i];
if (complete_fx4) begin // LSU | EXU | TLU
push_delta_fx5 (`CCR+`CTL_OFFSET,CCR_reg,index);
if (complete_fx4[`LSU_INDEX] |
complete_fx4[`EXU_INDEX]) begin
if (mytid <= 3) begin // {
for (i=0; i<=31; i=i+1) begin // {
push_delta_fx5 (i,`IRF6_EXU0[(remap(i,oddwin)+irf_offset)],index);
for (i=0; i<=31; i=i+1) begin // {
push_delta_fx5 (i,`IRF6_EXU1[(remap(i,oddwin)+irf_offset)],index);
// Update FRF6 - Loads use W2 Port.
if (complete_fx4[`LSU_INDEX]) begin // {
// IF W1 port is also being written, ignore that address
for (i=0; i<=31; i=i+1) begin // {
if (!((i == frf_w1_skip_addr) && frf_w1_valid_even)) begin // {
frf_tmp = `FRF6_EVEN[(mytid*32)+i];
push_delta_fx5 (`FP_OFFSET + (i*2), frf_tmp[31:0], index);
if (!((i == frf_w1_skip_addr) && frf_w1_valid_odd)) begin // {
frf_tmp = `FRF6_ODD[(mytid*32)+i];
push_delta_fx5 (`FP_OFFSET + (i*2)+1, frf_tmp[31:0], index);
// Update ASR/ASI registers
if (complete_fx4) begin // {
push_delta_fx5 (`PSTATE + `CTL_OFFSET,PSTATE_reg,index);
push_delta_fx5 (`HPSTATE + `CTL_OFFSET,HPSTATE_reg,index);
push_delta_fx5 (`PIL + `CTL_OFFSET,PIL_reg,index);
push_delta_fx5 (`TBA + `CTL_OFFSET,{TBA_reg,15'b0},index);
push_delta_fx5 (`GL + `CTL_OFFSET,GL_reg,index);
push_delta_fx5 (`HTBA + `CTL_OFFSET,{HTBA_reg,14'b0},index);
push_delta_fx5 (`VER + `CTL_OFFSET,VER_reg,index);
push_delta_fx5 (`Y + `CTL_OFFSET,Y_reg,index);
push_delta_fx5 (`ASI + `CTL_OFFSET,ASI_reg,index);
push_delta_fx5 (`STICK_CMPR + `CTL_OFFSET,STICK_CMPR_wire,index);
push_delta_fx5 (`HSTICK_CMPR + `CTL_OFFSET,HSTICK_CMPR_wire,index);
push_delta_fx5 (`TICK_CMPR + `CTL_OFFSET,TICK_CMPR_wire,index);
push_delta_fx5 (`CWP + `CTL_OFFSET,CWP_reg,index);
push_delta_fx5 (`CANSAVE + `CTL_OFFSET,CANSAVE_reg,index);
push_delta_fx5 (`CANRESTORE + `CTL_OFFSET,CANRESTORE_reg,index);
push_delta_fx5 (`CLEANWIN + `CTL_OFFSET,CLEANWIN_reg,index);
push_delta_fx5 (`OTHERWIN + `CTL_OFFSET,OTHERWIN_reg,index);
push_delta_fx5 (`WSTATE + `CTL_OFFSET,WSTATE_reg,index);
push_delta_fx5 (`CTXT_PRIM_0+`CTL_OFFSET,CTXT_PRIM_0_reg,index);
push_delta_fx5 (`CTXT_SEC_0+`CTL_OFFSET,CTXT_SEC_0_reg,index);
push_delta_fx5 (`CTXT_PRIM_1+`CTL_OFFSET,CTXT_PRIM_1_reg,index);
push_delta_fx5 (`CTXT_SEC_1+`CTL_OFFSET,CTXT_SEC_1_reg,index);
push_delta_fx5 (`LSU_CONTROL+`CTL_OFFSET,LSU_CONTROL_reg,index);
push_delta_fx5 (`WATCHPOINT_ADDR+`CTL_OFFSET,WATCHPOINT_ADDR_reg,index);
// NOTE - ADD_TSB_CFG will never be used for Axis or Tharas
push_delta_fx5 (`CTXT_Z_TSB_CFG0+`CTL_OFFSET,ctxt_z_tsb_cfg0_reg,index);
push_delta_fx5 (`CTXT_Z_TSB_CFG1+`CTL_OFFSET,ctxt_z_tsb_cfg1_reg,index);
push_delta_fx5 (`CTXT_Z_TSB_CFG2+`CTL_OFFSET,ctxt_z_tsb_cfg2_reg,index);
push_delta_fx5 (`CTXT_Z_TSB_CFG3+`CTL_OFFSET,ctxt_z_tsb_cfg3_reg,index);
push_delta_fx5 (`CTXT_NZ_TSB_CFG0+`CTL_OFFSET,ctxt_nz_tsb_cfg0_reg,index);
push_delta_fx5 (`CTXT_NZ_TSB_CFG1+`CTL_OFFSET,ctxt_nz_tsb_cfg1_reg,index);
push_delta_fx5 (`CTXT_NZ_TSB_CFG2+`CTL_OFFSET,ctxt_nz_tsb_cfg2_reg,index);
push_delta_fx5 (`CTXT_NZ_TSB_CFG3+`CTL_OFFSET,ctxt_nz_tsb_cfg3_reg,index);
// Update GSR for all except write ASR in progess
if (!asi_in_progress) begin // {
push_delta_fx5 (`GSR + `CTL_OFFSET,GSR_wire, index);
// If lsu_complete & fp_complete assert at same time,
// then the fp_complete is the one that will modify the FSR
if (complete_fx4[`LSU_INDEX] & !complete_fw1[`FP_INDEX]) begin
push_delta_fx5 (`FSR+`CTL_OFFSET,FSR_wire,index);
// Non Trap updates of Trap stack & level
if (complete_fx4 && !complete_fx4[`TLU_INDEX]) begin // {
push_delta_fx5 (`TL + `CTL_OFFSET,TL_reg,index);
push_delta_fx5 (`TPC1 + `CTL_OFFSET, TPC1_wire, index);
push_delta_fx5 (`TPC2 + `CTL_OFFSET, TPC2_wire, index);
push_delta_fx5 (`TPC3 + `CTL_OFFSET, TPC3_wire, index);
push_delta_fx5 (`TPC4 + `CTL_OFFSET, TPC4_wire, index);
push_delta_fx5 (`TPC5 + `CTL_OFFSET, TPC5_wire, index);
push_delta_fx5 (`TPC6 + `CTL_OFFSET, TPC6_wire, index);
push_delta_fx5 (`TNPC1 + `CTL_OFFSET, TNPC1_wire, index);
push_delta_fx5 (`TNPC2 + `CTL_OFFSET, TNPC2_wire, index);
push_delta_fx5 (`TNPC3 + `CTL_OFFSET, TNPC3_wire, index);
push_delta_fx5 (`TNPC4 + `CTL_OFFSET, TNPC4_wire, index);
push_delta_fx5 (`TNPC5 + `CTL_OFFSET, TNPC5_wire, index);
push_delta_fx5 (`TNPC6 + `CTL_OFFSET, TNPC6_wire, index);
push_delta_fx5 (`TSTATE1 + `CTL_OFFSET, TSTATE1_wire, index);
push_delta_fx5 (`TSTATE2 + `CTL_OFFSET, TSTATE2_wire, index);
push_delta_fx5 (`TSTATE3 + `CTL_OFFSET, TSTATE3_wire, index);
push_delta_fx5 (`TSTATE4 + `CTL_OFFSET, TSTATE4_wire, index);
push_delta_fx5 (`TSTATE5 + `CTL_OFFSET, TSTATE5_wire, index);
push_delta_fx5 (`TSTATE6 + `CTL_OFFSET, TSTATE6_wire, index);
push_delta_fx5 (`HTSTATE1 + `CTL_OFFSET, HTSTATE1_wire, index);
push_delta_fx5 (`HTSTATE2 + `CTL_OFFSET, HTSTATE2_wire, index);
push_delta_fx5 (`HTSTATE3 + `CTL_OFFSET, HTSTATE3_wire, index);
push_delta_fx5 (`HTSTATE4 + `CTL_OFFSET, HTSTATE4_wire, index);
push_delta_fx5 (`HTSTATE5 + `CTL_OFFSET, HTSTATE5_wire, index);
push_delta_fx5 (`HTSTATE6 + `CTL_OFFSET, HTSTATE6_wire, index);
push_delta_fx5 (`TT1 + `CTL_OFFSET, TT1_wire, index);
push_delta_fx5 (`TT2 + `CTL_OFFSET, TT2_wire, index);
push_delta_fx5 (`TT3 + `CTL_OFFSET, TT3_wire, index);
push_delta_fx5 (`TT4 + `CTL_OFFSET, TT4_wire, index);
push_delta_fx5 (`TT5 + `CTL_OFFSET, TT5_wire, index);
push_delta_fx5 (`TT6 + `CTL_OFFSET, TT6_wire, index);
//----------------------------------------------------------
// Stage FB of delta pipeline
index = delta_fx5[`NEXT_INDEX];
// Pipeline previous stage
for (i=0; i<=delta_fx5[`NEXT_INDEX]; i=i+1) begin // {
delta_fb[i] <= delta_fx5[i];
if (complete_fx5[`ASI_INDEX]) begin // {
push_delta_fb (`GSR + `CTL_OFFSET,GSR_wire, index);
//----------------------------------------------------------
// Stage FW of delta pipeline
index = delta_fb[`NEXT_INDEX];
// Pipeline previous stage
for (i=0; i<=delta_fb[`NEXT_INDEX]; i=i+1) begin // {
delta_fw[i] <= delta_fb[i];
// Capture CWP_reg for SAVE/RESTORE
delta_fw[`CWP_INDEX] <= CWP_reg;
if (complete_fb[`TLU_INDEX]) begin
if (mytid <= 3) begin // {
for (i=0; i<=31; i=i+1) begin // {
push_delta_fw (i,`IRF6_EXU0[(remap(i,oddwin)+irf_offset)],index);
for (i=0; i<=31; i=i+1) begin // {
push_delta_fw (i,`IRF6_EXU1[(remap(i,oddwin)+irf_offset)],index);
// Update FRF6 - Idivs use W2.
if (complete_fb[`IDIV_INDEX]) begin // {
// IF W1 port is also being written, ignore that address
for (i=0; i<=31; i=i+1) begin // {
if (!((i == frf_w1_skip_addr) && frf_w1_valid_even)) begin // {
frf_tmp = `FRF6_EVEN[(mytid*32)+i];
push_delta_fw (`FP_OFFSET + (i*2), frf_tmp[31:0], index);
if (!((i == frf_w1_skip_addr) && frf_w1_valid_odd)) begin // {
frf_tmp = `FRF6_ODD[(mytid*32)+i];
push_delta_fw (`FP_OFFSET + (i*2)+1,frf_tmp[31:0], index);
//----------------------------------------------------------
// Stage FW1 of delta pipeline
index = delta_fw[`NEXT_INDEX];
// Pipeline previous stage
for (i=0; i<=delta_fw[`NEXT_INDEX]; i=i+1) begin // {
delta_fw1[i] <= delta_fw[i];
// Update FRF6 - FPops use W1 port.
if (fp_complete) begin // {
// IF W2 port is also being written, ignore that address
for (i=0; i<=31; i=i+1) begin // {
if (!((i == frf_w2_skip_addr) && frf_w2_valid_even)) begin // {
frf_tmp = `FRF6_EVEN[(mytid*32)+i];
push_delta_fw1 (`FP_OFFSET + (i*2), frf_tmp[31:0], index);
if (!((i == frf_w2_skip_addr) && frf_w2_valid_odd)) begin // {
frf_tmp = `FRF6_ODD[(mytid*32)+i];
push_delta_fw1 (`FP_OFFSET + (i*2)+1,frf_tmp[31:0], index);
if (complete_fw[`IMUL_INDEX]|complete_fw[`IDIV_INDEX]) begin
push_delta_fw1 (`CCR+`CTL_OFFSET,CCR_reg,index);
push_delta_fw1 (`Y+`CTL_OFFSET,Y_reg,index);
push_delta_fw1 (`CWP+`CTL_OFFSET,CWP_reg,index);
push_delta_fw1 (`CANSAVE+`CTL_OFFSET,CANSAVE_reg,index);
push_delta_fw1 (`CANRESTORE+`CTL_OFFSET,CANRESTORE_reg,index);
push_delta_fw1 (`CLEANWIN+`CTL_OFFSET,CLEANWIN_reg,index);
push_delta_fw1 (`OTHERWIN+`CTL_OFFSET,OTHERWIN_reg,index);
push_delta_fw1 (`WSTATE+`CTL_OFFSET,WSTATE_reg,index);
if (complete_fw[`TLU_INDEX]) begin // {
push_delta_fw1 (`TL + `CTL_OFFSET,TL_reg,index);
push_delta_fw1 (`TPC1 + `CTL_OFFSET, TPC1_wire, index);
push_delta_fw1 (`TPC2 + `CTL_OFFSET, TPC2_wire, index);
push_delta_fw1 (`TPC3 + `CTL_OFFSET, TPC3_wire, index);
push_delta_fw1 (`TPC4 + `CTL_OFFSET, TPC4_wire, index);
push_delta_fw1 (`TPC5 + `CTL_OFFSET, TPC5_wire, index);
push_delta_fw1 (`TPC6 + `CTL_OFFSET, TPC6_wire, index);
push_delta_fw1 (`TNPC1 + `CTL_OFFSET, TNPC1_wire, index);
push_delta_fw1 (`TNPC2 + `CTL_OFFSET, TNPC2_wire, index);
push_delta_fw1 (`TNPC3 + `CTL_OFFSET, TNPC3_wire, index);
push_delta_fw1 (`TNPC4 + `CTL_OFFSET, TNPC4_wire, index);
push_delta_fw1 (`TNPC5 + `CTL_OFFSET, TNPC5_wire, index);
push_delta_fw1 (`TNPC6 + `CTL_OFFSET, TNPC6_wire, index);
push_delta_fw1 (`TSTATE1 + `CTL_OFFSET, TSTATE1_wire, index);
push_delta_fw1 (`TSTATE2 + `CTL_OFFSET, TSTATE2_wire, index);
push_delta_fw1 (`TSTATE3 + `CTL_OFFSET, TSTATE3_wire, index);
push_delta_fw1 (`TSTATE4 + `CTL_OFFSET, TSTATE4_wire, index);
push_delta_fw1 (`TSTATE5 + `CTL_OFFSET, TSTATE5_wire, index);
push_delta_fw1 (`TSTATE6 + `CTL_OFFSET, TSTATE6_wire, index);
push_delta_fw1 (`HTSTATE1 + `CTL_OFFSET, HTSTATE1_wire, index);
push_delta_fw1 (`HTSTATE2 + `CTL_OFFSET, HTSTATE2_wire, index);
push_delta_fw1 (`HTSTATE3 + `CTL_OFFSET, HTSTATE3_wire, index);
push_delta_fw1 (`HTSTATE4 + `CTL_OFFSET, HTSTATE4_wire, index);
push_delta_fw1 (`HTSTATE5 + `CTL_OFFSET, HTSTATE5_wire, index);
push_delta_fw1 (`HTSTATE6 + `CTL_OFFSET, HTSTATE6_wire, index);
push_delta_fw1 (`TT1 + `CTL_OFFSET, TT1_wire, index);
push_delta_fw1 (`TT2 + `CTL_OFFSET, TT2_wire, index);
push_delta_fw1 (`TT3 + `CTL_OFFSET, TT3_wire, index);
push_delta_fw1 (`TT4 + `CTL_OFFSET, TT4_wire, index);
push_delta_fw1 (`TT5 + `CTL_OFFSET, TT5_wire, index);
push_delta_fw1 (`TT6 + `CTL_OFFSET, TT6_wire, index);
//----------------------------------------------------------
// Stage FW2 of delta pipeline
index = delta_fw1[`NEXT_INDEX];
// Pipeline previous stage
for (i=0; i<=delta_fw1[`NEXT_INDEX]; i=i+1) begin // {
delta_fw2[i] <= delta_fw1[i];
delta_fw2[`TIME_INDEX] <= $time;
// Update Registers that may change asynchronously
// If sstep was already sent by another module,
// don't capture until the next sstep
if (complete_fw1 && !`NASTOP.sstep_early[mytnum]) begin // {
if ((complete_fw1[`ASI_INDEX]|complete_fw1[`LSU_INDEX]) & asi_rdwr_hintp)
push_delta_fw2 (`HINTP + `CTL_OFFSET,asi_updated_hintp,index);
push_delta_fw2 (`HINTP + `CTL_OFFSET,HINTP_reg,index);
if ((complete_fw1[`ASI_INDEX]|complete_fw1[`LSU_INDEX]) & asi_rdwr_softint)
push_delta_fw2 (`SOFTINT + `CTL_OFFSET,asi_updated_softint,index);
push_delta_fw2 (`SOFTINT + `CTL_OFFSET,rd_SOFTINT_reg,index);
if (complete_fw1[`IMUL_INDEX] |
complete_fw1[`IDIV_INDEX]) begin // {
if (mytid <= 3) begin // {
for (i=0; i<=31; i=i+1) begin // {
push_delta_fw2 (i,`IRF6_EXU0[(remap(i,oddwin)+irf_offset)],index);
for (i=0; i<=31; i=i+1) begin // {
push_delta_fw2 (i,`IRF6_EXU1[(remap(i,oddwin)+irf_offset)],index);
// Update FRF6 - fdivs and Imuls use W2 port
if (complete_fw1[`IMUL_INDEX] |
complete_fw1[`FDIV_INDEX] ) begin // {
// IF W1 port is also being written, ignore that address
for (i=0; i<=31; i=i+1) begin // {
if (!((i == frf_w1_skip_addr) && frf_w1_valid_even)) begin // {
frf_tmp = `FRF6_EVEN[(mytid*32)+i];
push_delta_fw2 (`FP_OFFSET + (i*2), frf_tmp[31:0], index);
if (!((i == frf_w1_skip_addr) && frf_w1_valid_odd)) begin // {
frf_tmp = `FRF6_ODD[(mytid*32)+i];
push_delta_fw2 (`FP_OFFSET + (i*2)+1,frf_tmp[31:0], index);
if (complete_fw1[`FP_INDEX] |
complete_fw1[`TLU_INDEX] |
complete_fw1[`FDIV_INDEX]) begin
push_delta_fw2 (`FSR+`CTL_OFFSET,FSR_wire,index);
push_delta_fw2 (`I_TAG_ACC+`CTL_OFFSET,itagacc_fw2,index);
push_delta_fw2 (`D_TAG_ACC+`CTL_OFFSET,dtagacc_fw2,index);
push_delta_fw2 (`DSFAR+`CTL_OFFSET,dsfar_fw2,index);
//----------------------------------------------------------
// Stage FW2 of delta pipeline - for signals that change FW+2 !!
index = delta_fw2[`NEXT_INDEX];
// Since FPRS for FPops may have been corrupted by o-o-o loads:
// If fprs_fw2 is != fprs_reg & there are loads in the pipeline
// then assume loads have already updated fprs.
// In that case, create our own fprs_reg by using the valids and
// skip_addr and copy of fprs for this op..
if (complete_fw2[`FP_INDEX] && frf_w1_valid_fw2) begin // {
// o-o-o load has changed fprs already - use dummy
if ((fprs_fw2 != FPRS_reg) && (complete_fw1[`LSU_INDEX] |
complete_fw[`LSU_INDEX] | complete_fb[`LSU_INDEX] |
complete_fx5[`LSU_INDEX] )) begin // {
dummy_fprs = read_prev(`FPRS + `CTL_OFFSET);
dummy_fprs = dummy_fprs |
{1'b0, frf_w1_skip_addr4_fw2, ~frf_w1_skip_addr4_fw2};
push_delta_fw2_async (`FPRS + `CTL_OFFSET,dummy_fprs,index);
// o-o-o load has NOT changed fprs already - use it
push_delta_fw2_async (`FPRS + `CTL_OFFSET,FPRS_reg,index);
// Load FPRS for loads/reads as prev|fprs_fb ..
// since loads may only 'set' bits, not clear ...
else if (complete_fw2[`LSU_INDEX]) begin // {
dummy_fprs = read_prev(`FPRS + `CTL_OFFSET);
dummy_fprs = dummy_fprs | fprs_fw1;
push_delta_fw2_async (`FPRS +`CTL_OFFSET,dummy_fprs,index);
// Load FPRS for store ASI or FDIV
// FDIV can update FPRS on w1 or w2,
// but the pipe is stalled behind it so no o-o-o loads.
else if ((complete_fw2[`ASI_INDEX]) ||
(complete_fw2[`FDIV_INDEX])) begin // {
push_delta_fw2_async (`FPRS + `CTL_OFFSET,FPRS_reg,index);
//----------------------------------------------------------
// Store latest values into delta
index = delta_prev[`NEXT_INDEX];
if (in_wmr & ~`SPC6.rst_wmr_protect) begin // {
push_delta_prev_async ( `PC+`CTL_OFFSET,{16'b0,pc_fw2|1},index);
push_delta_prev_async ( `PC+`CTL_OFFSET,{16'b0,pc_fw2},index);
//----------------------------------------------------------
//----------------------------------------------------------
// Compare with current state and capture if different
if (act_value != read_prev(id)) begin // { // Diff vs prev
calc_cwp(CWP_reg,id,win,type); // special case for 1st stage
write_prev(id,act_value);
delta_fx4[next] <= {type,win,id,act_value};
delta_fx4[next] <= 77'hx;
delta_fx4[`NEXT_INDEX] <= next;
if (`PARGS.axis_debug_on) begin
$display("AXIS: T%0d pc=%h id=%0d type=%0h win=%0h value=%h ts=%0d",
mytnum,PC_reg,id,type,win,act_value,$time);
if (`PARGS.axis_debug_on) begin
$display("AXIS: T%0d pc=%h id=%0d type=%0h win=%0h value=%h ts=%0d",
mytnum,PC_reg,id,type,win,act_value,$time);
//----------------------------------------------------------
// Compare with current state and capture if different
if (act_value != read_prev(id)) begin // { // Diff vs prev
calc_cwp(delta_fx4[`CWP_INDEX],id,win,type);
write_prev(id,act_value);
delta_fx5[next] <= {type,win,id,act_value};
delta_fx5[next] <= 77'hx;
delta_fx5[`NEXT_INDEX] <= next;
if (`PARGS.axis_debug_on) begin
$display("AXIS: T%0d pc=%h id=%0d type=%0h win=%0h value=%h ts=%0d",
mytnum,pc_fx4,id,type,win,act_value,$time);
calc_cwp(cwp_fx4,id,win,type);
if (`PARGS.axis_debug_on) begin
$display("AXIS: T%0d pc=%h id=%0d type=%0h win=%0h value=%h ts=%0d",
mytnum,pc_fx4,id,type,win,act_value,$time);
//----------------------------------------------------------
// Compare with current state and capture if different
if (act_value != read_prev(id)) begin // { // Diff vs prev
calc_cwp(delta_fx5[`CWP_INDEX],id,win,type);
write_prev(id,act_value);
delta_fb[next] <= {type,win,id,act_value};
delta_fb[`NEXT_INDEX] <= next;
if (`PARGS.axis_debug_on) begin
$display("AXIS: T%0d pc=%h id=%0d type=%0h win=%0h value=%h ts=%0d",
mytnum,pc_fx5,id,type,win,act_value,$time);
calc_cwp(cwp_fx5,id,win,type);
if (`PARGS.axis_debug_on) begin
$display("AXIS: T%0d pc=%h id=%0d type=%0h win=%0h value=%h ts=%0d",
mytnum,pc_fx5,id,type,win,act_value,$time);
//----------------------------------------------------------
// Compare with current state and capture if different
if (act_value != read_prev(id)) begin // { // Diff vs prev
calc_cwp(delta_fb[`CWP_INDEX],id,win,type);
write_prev(id,act_value);
delta_fw[next] <= {type,win,id,act_value};
delta_fw[`NEXT_INDEX] <= next;
if (`PARGS.axis_debug_on) begin
$display("AXIS: T%0d pc=%h id=%0d type=%0h win=%0h value=%h ts=%0d",
mytnum,pc_fb,id,type,win,act_value,$time);
calc_cwp(cwp_fb[`CWP_INDEX],id,win,type);
if (`PARGS.axis_debug_on) begin
$display("AXIS: T%0d pc=%h id=%0d type=%0h win=%0h value=%h ts=%0d",
mytnum,pc_fb,id,type,win,act_value,$time);
//----------------------------------------------------------
// Compare with current state and capture if different
if (act_value != read_prev(id)) begin // { // Diff vs prev
calc_cwp(delta_fw[`CWP_INDEX],id,win,type);
write_prev(id,act_value);
delta_fw1[next] <= {type,win,id,act_value};
delta_fw1[next] <= 77'hx;
delta_fw1[`NEXT_INDEX] <= next;
if (`PARGS.axis_debug_on) begin
$display("AXIS: T%0d pc=%h id=%0d type=%0h win=%0h value=%h ts=%0d",
mytnum,pc_fw,id,type,win,act_value,$time);
calc_cwp(cwp_fw,id,win,type);
if (`PARGS.axis_debug_on) begin
$display("AXIS: T%0d pc=%h id=%0d type=%0h win=%0h value=%h ts=%0d",
mytnum,pc_fw,id,type,win,act_value,$time);
//----------------------------------------------------------
// Compare with current state and capture if different
if (act_value != read_prev(id)) begin // { // Diff vs prev
calc_cwp(delta_fw1[`CWP_INDEX],id,win,type);
write_prev(id,act_value);
delta_fw2[next] <= {type,win,id,act_value};
delta_fw2[next] <= 77'hx;
delta_fw2[`NEXT_INDEX] <= next;
if (`PARGS.axis_debug_on) begin
$display("AXIS: T%0d pc=%h id=%0d type=%0h win=%0h value=%h ts=%0d",
mytnum,pc_fw1,id,type,win,act_value,$time);
calc_cwp(cwp_fw1,id,win,type);
if (`PARGS.axis_debug_on) begin
$display("AXIS: T%0d pc=%h id=%0d type=%0h win=%0h value=%h ts=%0d",
mytnum,pc_fw1,id,type,win,act_value,$time);
//----------------------------------------------------------
// Compare with current state and capture if different
// This is for late changing registers
// Use blocking assignments.
task push_delta_fw2_async;
if (act_value != read_prev(id)) begin // { // Diff vs prev
calc_cwp(delta_fw2[`CWP_INDEX],id,win,type);
write_prev_async(id,act_value);
delta_fw2[next] = {type,win,id,act_value};
delta_fw2[`NEXT_INDEX] = next;
if (`PARGS.axis_debug_on) begin
$display("AXIS: T%0d pc=%h id=%0d type=%0h win=%0h value=%h ts=%0d",
mytnum,pc_fw1,id,type,win,act_value,$time);
calc_cwp(cwp_fw2,id,win,type);
if (`PARGS.axis_debug_on) begin
$display("AXIS: T%0d pc=%h id=%0d type=%0h win=%0h value=%h ts=%0d",
mytnum,pc_fw1,id,type,win,act_value,$time);
//----------------------------------------------------------
// Compare with current state and capture if different
// Use blocking assignments so that push_simics will work
task push_delta_prev_async;
if (act_value != read_prev(id)) begin // { // Diff vs prev
calc_cwp(delta_prev[`CWP_INDEX],id,win,type);
write_prev_async(id,act_value);
delta_prev[next] = {type,win,id,act_value};
delta_prev[next] = 77'hx;
delta_prev[`NEXT_INDEX] = next;
if (`PARGS.axis_debug_on) begin
$display("AXIS: T%0d pc=%h id=%0d type=%0h win=%0h value=%h ts=%0d",
mytnum,pc_last,id,type,win,act_value,$time);
if (`PARGS.axis_debug_on) begin
calc_cwp(cwp_last,id,win,type);
$display("AXIS: T%0d pc=%h id=%0d type=%0h win=%0h value=%h ts=%0d",
mytnum,pc_last,id,type,win,act_value,$time);
//----------------------------------------------------------
// prev of delta pipeline
// Pipeline previous stage
for (i=0; i<=delta_fw2[`NEXT_INDEX]; i=i+1) begin // {
delta_prev[i] <= delta_fw2[i];
//----------------------------------------------------------
//----------------------------------------------------------
// Sort delta list in register ID order, then push to simics
// Or print deltas if sas check disabled ..
// Order of registers reported to simics must be:
// Global 0-7 aka prev_reg[0:7]
// Window 8-23 aka prev_reg[8:23]
// Floating 0-63 aka prev_reg[200:263]
// Control 32-143 aka prev_reg[32:143]
act_level = delta_prev[`GL_INDEX]; // GL
time_fw2 = delta_prev[`TIME_INDEX]; // Finish time
for (i=`FIRST_INDEX; i<delta_prev[`NEXT_INDEX]; i=i+1) begin // {
{type,win,regnum,value} = delta_prev[i];
if (regnum<=7) begin // {
if (`PARGS.nas_check_on) begin // {
`ACT_STATUS = $queue(`ACT_QUEUE, `PUSH_Q, mytnum, time_fw2, act_type,
act_level, regnum, value);
else if (`PARGS.show_delta_on) begin // {
`NASTOP.print_delta (mytnum,act_type,win,regnum,value);
else if (regnum<=23) begin // { %o0-%l7, %l0-%l7
if (`PARGS.nas_check_on) begin // {
`ACT_STATUS = $queue(`ACT_QUEUE, `PUSH_Q, mytnum, time_fw2, act_type,
else if (`PARGS.show_delta_on) begin // {
`NASTOP.print_delta (mytnum,act_type,win,regnum,value);
else if (regnum<=31) begin // { %i0-%i7
if (`PARGS.nas_check_on) begin // {
`ACT_STATUS = $queue(`ACT_QUEUE, `PUSH_Q, mytnum, time_fw2, act_type,
win, (regnum-16), value);
else if (`PARGS.show_delta_on) begin // {
`NASTOP.print_delta (mytnum,act_type,win,(regnum-16),value);
else if (regnum<=(64+`FP_OFFSET)) begin // {
if (`PARGS.nas_check_on) begin // {
`ACT_STATUS = $queue(`ACT_QUEUE, `PUSH_Q, mytnum, time_fw2, act_type,
(regnum-`FP_OFFSET), value);
else if (`PARGS.show_delta_on) begin // {
`NASTOP.print_delta (mytnum,act_type,win,(regnum-`FP_OFFSET),value);
else if ((regnum>=(32+`CTL_OFFSET))&(regnum<=(143+`CTL_OFFSET))) begin // {
if (`PARGS.nas_check_on) begin // {
`ACT_STATUS = $queue(`ACT_QUEUE, `PUSH_Q, mytnum, time_fw2, act_type,
(regnum-`CTL_OFFSET), value);
else if (`PARGS.show_delta_on) begin // {
`NASTOP.print_delta (mytnum,act_type,win,(regnum-`CTL_OFFSET),value);
`PR_ERROR ("nas", `ERROR, " - T%0d Bench problem. push_simics has bad regnum", mytnum);
value = delta_prev[`OPCODE_INDEX];
if (`PARGS.nas_check_on) begin // {
`ACT_STATUS = $queue(`ACT_QUEUE, `PUSH_Q, mytnum, time_fw2, act_type,
else if (`PARGS.show_delta_on) begin // {
`NASTOP.print_delta (mytnum,act_type,win,regnum,value);
// Push End of Instruction Delimiter
// The value field for this PUSH equals the PC for this instruction.
// so that printing to the logfile works correctly.
// prev_reg[`PC] = current instruction PC
// delta_reg[`PC] = PC at end of current instruction
pc = delta_prev[`PC_INDEX];
if (`PARGS.nas_check_on) begin // {
`ACT_STATUS = $queue(`ACT_QUEUE, `PUSH_Q, mytnum, time_fw2, act_type,
delta_fw2[`CWP_INDEX], `END_INSTR, pc);
else if (`PARGS.show_delta_on) begin // {
`NASTOP.print_delta (mytnum,act_type,delta_fw2[`CWP_INDEX],`END_INSTR,0);
if (! `PARGS.nas_check_on) begin // {
`PR_NORMAL ("nas", `NORMAL, "@%0d T%0d %h (Unchecked..)",
$time, mytnum, {16'b0,pc});
`TOP.last_act_cycle = `TOP.core_cycle_cnt; //$time;
`TOP.th_last_act_cycle[mytnum] = `TOP.last_act_cycle;
if (! `PARGS.nas_check_on) begin // {
`TOP.last_act_cycle = `TOP.core_cycle_cnt; //$time;
`TOP.th_last_act_cycle[mytnum] = `TOP.last_act_cycle;
//----------------------------------------------------------
// Save current window to previous window, then copy new window to current window
// Save current window to Old window
// Copy New window to current window
//----------------------------------------------------------
// Save current global to previous global, then copy new global to current global
// Save current global to Old global
// Copy New global current global
//----------------------------------------------------------
// Return window number and register type based on cwp and regnum as input
else if (id<=23) begin // {
else if (id<=31) begin // {
else if (id<=(64+`FP_OFFSET)) begin // {
//----------------------------------------------------------
// Check for bad signal values
8'b10000000: ; // good value
`PR_ERROR ("nas", `ERROR, " - T%0d More than one instruction retired in a single cycle for this thread.",
$write("\t\t\t\t Instructions - ");
if (complete_fw2[`EXU_INDEX]) $write("EXU op, ");
if (complete_fw2[`FP_INDEX]) $write("FP op, ");
if (complete_fw2[`LSU_INDEX]) $write("LSU op, ");
if (complete_fw2[`IMUL_INDEX]) $write("IMUL op, ");
if (complete_fw2[`IDIV_INDEX]) $write("IDIV op, ");
if (complete_fw2[`FDIV_INDEX]) $write("FDIV op, ");
if (complete_fw2[`TLU_INDEX]) $write("TLU op, ");
if (complete_fw2[`ASI_INDEX]) $write("ASI op, ");
$write(" complete_fw2 = %b \n",complete_fw2);
// This check only works if diags are written properly.
// For example, if a diag writes to one of these registers using wrpr,
// then this check must be disabled using plusarg.
// CANSAVE + CANRESTORE + OTHERWIN = NWINDOWS-2 (per Sparc V9)
if (`PARGS.win_check_on) begin // {
if (complete_fw2 & ((CANSAVE_reg + CANRESTORE_reg + OTHERWIN_reg) != 6)) begin // {
`PR_ERROR ("nas", `ERROR, "ERROR - T%0d Bad Values for window registers.", mytnum);
`PR_ERROR ("nas", `ERROR, "- CANSAVE = %0d CANRESTORE = %0d OTHERWIN = %0d",
CANSAVE_reg, CANRESTORE_reg,OTHERWIN_reg);
//----------------------------------------------------------
//----------------------------------------------------------
reg [`DELTA_WIDTH:0] temp1, temp2;
last = delta_prev[`NEXT_INDEX]-1;
for (i=`FIRST_INDEX; i <= last; i=i+1) begin // {
for (j=`FIRST_INDEX; j < last; j=j+1) begin // {
temp1 = delta_prev[j]; temp2 = delta_prev[j+1];
if (temp1[76:64] > temp2[76:64]) begin // {
delta_prev[j] = temp2; delta_prev [j+1] = temp1;
//----------------------------------------------------------
//----------------------------------------------------------
// Print one entry in delta_* array
input [`DELTA_WIDTH:0] delta_entry;
reg [(20*8)-1:0] type_str;
reg [(20*8)-1:0] regname;
{type,win,id,act_value} = delta_entry;
`NASTOP.get_regname(mytnum,type_str,win,id,regname);
`PR_NORMAL ("nas", `NORMAL, "type=%0s win=%0d RegID=%0d %0s=%h",
type_str,win,id,regname,act_value);
//----------------------------------------------------------
// Write Value to prev_reg using id as index (non-blocking)
8'd0: prev_reg0 <= value;
8'd1: prev_reg1 <= value;
8'd2: prev_reg2 <= value;
8'd3: prev_reg3 <= value;
8'd4: prev_reg4 <= value;
8'd5: prev_reg5 <= value;
8'd6: prev_reg6 <= value;
8'd7: prev_reg7 <= value;
8'd8: prev_reg8 <= value;
8'd9: prev_reg9 <= value;
8'd10: prev_reg10 <= value;
8'd11: prev_reg11 <= value;
8'd12: prev_reg12 <= value;
8'd13: prev_reg13 <= value;
8'd14: prev_reg14 <= value;
8'd15: prev_reg15 <= value;
8'd16: prev_reg16 <= value;
8'd17: prev_reg17 <= value;
8'd18: prev_reg18 <= value;
8'd19: prev_reg19 <= value;
8'd20: prev_reg20 <= value;
8'd21: prev_reg21 <= value;
8'd22: prev_reg22 <= value;
8'd23: prev_reg23 <= value;
8'd24: prev_reg24 <= value;
8'd25: prev_reg25 <= value;
8'd26: prev_reg26 <= value;
8'd27: prev_reg27 <= value;
8'd28: prev_reg28 <= value;
8'd29: prev_reg29 <= value;
8'd30: prev_reg30 <= value;
8'd31: prev_reg31 <= value;
8'd32: prev_reg32 <= value;
8'd33: prev_reg33 <= value;
8'd34: prev_reg34 <= value;
8'd35: prev_reg35 <= value;
8'd36: prev_reg36 <= value;
8'd37: prev_reg37 <= value;
8'd38: prev_reg38 <= value;
8'd39: prev_reg39 <= value;
8'd40: prev_reg40 <= value;
8'd41: prev_reg41 <= value;
8'd42: prev_reg42 <= value;
8'd43: prev_reg43 <= value;
8'd44: prev_reg44 <= value;
8'd45: prev_reg45 <= value;
8'd46: prev_reg46 <= value;
8'd47: prev_reg47 <= value;
8'd48: prev_reg48 <= value;
8'd49: prev_reg49 <= value;
8'd50: prev_reg50 <= value;
8'd51: prev_reg51 <= value;
8'd52: prev_reg52 <= value;
8'd53: prev_reg53 <= value;
8'd54: prev_reg54 <= value;
8'd55: prev_reg55 <= value;
8'd56: prev_reg56 <= value;
8'd57: prev_reg57 <= value;
8'd58: prev_reg58 <= value;
8'd59: prev_reg59 <= value;
8'd60: prev_reg60 <= value;
8'd61: prev_reg61 <= value;
8'd62: prev_reg62 <= value;
8'd63: prev_reg63 <= value;
8'd64: prev_reg64 <= value;
8'd65: prev_reg65 <= value;
8'd66: prev_reg66 <= value;
8'd67: prev_reg67 <= value;
8'd68: prev_reg68 <= value;
8'd69: prev_reg69 <= value;
8'd70: prev_reg70 <= value;
8'd71: prev_reg71 <= value;
8'd72: prev_reg72 <= value;
8'd73: prev_reg73 <= value;
8'd74: prev_reg74 <= value;
8'd75: prev_reg75 <= value;
8'd76: prev_reg76 <= value;
8'd77: prev_reg77 <= value;
8'd78: prev_reg78 <= value;
8'd79: prev_reg79 <= value;
8'd80: prev_reg80 <= value;
8'd81: prev_reg81 <= value;
8'd82: prev_reg82 <= value;
8'd83: prev_reg83 <= value;
8'd84: prev_reg84 <= value;
8'd85: prev_reg85 <= value;
8'd86: prev_reg86 <= value;
8'd87: prev_reg87 <= value;
8'd88: prev_reg88 <= value;
8'd89: prev_reg89 <= value;
8'd90: prev_reg90 <= value;
8'd91: prev_reg91 <= value;
8'd92: prev_reg92 <= value;
8'd93: prev_reg93 <= value;
8'd94: prev_reg94 <= value;
8'd95: prev_reg95 <= value;
8'd96: prev_reg96 <= value;
8'd97: prev_reg97 <= value;
8'd98: prev_reg98 <= value;
8'd99: prev_reg99 <= value;
8'd100: prev_reg100 <= value;
8'd101: prev_reg101 <= value;
8'd102: prev_reg102 <= value;
8'd103: prev_reg103 <= value;
8'd104: prev_reg104 <= value;
8'd105: prev_reg105 <= value;
8'd106: prev_reg106 <= value;
8'd107: prev_reg107 <= value;
8'd108: prev_reg108 <= value;
8'd109: prev_reg109 <= value;
8'd110: prev_reg110 <= value;
8'd111: prev_reg111 <= value;
8'd112: prev_reg112 <= value;
8'd113: prev_reg113 <= value;
8'd114: prev_reg114 <= value;
8'd115: prev_reg115 <= value;
8'd116: prev_reg116 <= value;
8'd117: prev_reg117 <= value;
8'd118: prev_reg118 <= value;
8'd119: prev_reg119 <= value;
8'd120: prev_reg120 <= value;
8'd121: prev_reg121 <= value;
8'd122: prev_reg122 <= value;
8'd123: prev_reg123 <= value;
8'd124: prev_reg124 <= value;
8'd125: prev_reg125 <= value;
8'd126: prev_reg126 <= value;
8'd127: prev_reg127 <= value;
8'd128: prev_reg128 <= value;
8'd129: prev_reg129 <= value;
8'd130: prev_reg130 <= value;
8'd131: prev_reg131 <= value;
8'd132: prev_reg132 <= value;
8'd133: prev_reg133 <= value;
8'd134: prev_reg134 <= value;
8'd135: prev_reg135 <= value;
8'd136: prev_reg136 <= value;
8'd137: prev_reg137 <= value;
8'd138: prev_reg138 <= value;
8'd139: prev_reg139 <= value;
8'd140: prev_reg140 <= value;
8'd141: prev_reg141 <= value;
8'd142: prev_reg142 <= value;
8'd143: prev_reg143 <= value;
8'd144: prev_reg144 <= value;
8'd145: prev_reg145 <= value;
8'd146: prev_reg146 <= value;
8'd147: prev_reg147 <= value;
8'd148: prev_reg148 <= value;
8'd149: prev_reg149 <= value;
8'd150: prev_reg150 <= value;
8'd151: prev_reg151 <= value;
8'd152: prev_reg152 <= value;
8'd153: prev_reg153 <= value;
8'd154: prev_reg154 <= value;
8'd155: prev_reg155 <= value;
8'd156: prev_reg156 <= value;
8'd157: prev_reg157 <= value;
8'd158: prev_reg158 <= value;
8'd159: prev_reg159 <= value;
8'd160: prev_reg160 <= value;
8'd161: prev_reg161 <= value;
8'd162: prev_reg162 <= value;
8'd163: prev_reg163 <= value;
8'd164: prev_reg164 <= value;
8'd165: prev_reg165 <= value;
8'd166: prev_reg166 <= value;
8'd167: prev_reg167 <= value;
8'd168: prev_reg168 <= value;
8'd169: prev_reg169 <= value;
8'd170: prev_reg170 <= value;
8'd171: prev_reg171 <= value;
8'd172: prev_reg172 <= value;
8'd173: prev_reg173 <= value;
8'd174: prev_reg174 <= value;
8'd175: prev_reg175 <= value;
8'd176: prev_reg176 <= value;
8'd177: prev_reg177 <= value;
8'd178: prev_reg178 <= value;
8'd179: prev_reg179 <= value;
8'd180: prev_reg180 <= value;
8'd181: prev_reg181 <= value;
8'd182: prev_reg182 <= value;
8'd183: prev_reg183 <= value;
8'd184: prev_reg184 <= value;
8'd185: prev_reg185 <= value;
8'd186: prev_reg186 <= value;
8'd187: prev_reg187 <= value;
8'd188: prev_reg188 <= value;
8'd189: prev_reg189 <= value;
8'd190: prev_reg190 <= value;
8'd191: prev_reg191 <= value;
8'd192: prev_reg192 <= value;
8'd193: prev_reg193 <= value;
8'd194: prev_reg194 <= value;
8'd195: prev_reg195 <= value;
8'd196: prev_reg196 <= value;
8'd197: prev_reg197 <= value;
8'd198: prev_reg198 <= value;
8'd199: prev_reg199 <= value;
8'd200: prev_reg200 <= value;
8'd201: prev_reg201 <= value;
8'd202: prev_reg202 <= value;
8'd203: prev_reg203 <= value;
8'd204: prev_reg204 <= value;
8'd205: prev_reg205 <= value;
8'd206: prev_reg206 <= value;
8'd207: prev_reg207 <= value;
8'd208: prev_reg208 <= value;
8'd209: prev_reg209 <= value;
8'd210: prev_reg210 <= value;
8'd211: prev_reg211 <= value;
8'd212: prev_reg212 <= value;
8'd213: prev_reg213 <= value;
8'd214: prev_reg214 <= value;
8'd215: prev_reg215 <= value;
8'd216: prev_reg216 <= value;
8'd217: prev_reg217 <= value;
8'd218: prev_reg218 <= value;
8'd219: prev_reg219 <= value;
8'd220: prev_reg220 <= value;
8'd221: prev_reg221 <= value;
8'd222: prev_reg222 <= value;
8'd223: prev_reg223 <= value;
8'd224: prev_reg224 <= value;
8'd225: prev_reg225 <= value;
8'd226: prev_reg226 <= value;
8'd227: prev_reg227 <= value;
8'd228: prev_reg228 <= value;
8'd229: prev_reg229 <= value;
8'd230: prev_reg230 <= value;
8'd231: prev_reg231 <= value;
8'd232: prev_reg232 <= value;
8'd233: prev_reg233 <= value;
8'd234: prev_reg234 <= value;
8'd235: prev_reg235 <= value;
8'd236: prev_reg236 <= value;
8'd237: prev_reg237 <= value;
8'd238: prev_reg238 <= value;
8'd239: prev_reg239 <= value;
8'd240: prev_reg240 <= value;
8'd241: prev_reg241 <= value;
8'd242: prev_reg242 <= value;
8'd243: prev_reg243 <= value;
8'd244: prev_reg244 <= value;
8'd245: prev_reg245 <= value;
8'd246: prev_reg246 <= value;
8'd247: prev_reg247 <= value;
8'd248: prev_reg248 <= value;
8'd249: prev_reg249 <= value;
8'd250: prev_reg250 <= value;
8'd251: prev_reg251 <= value;
8'd252: prev_reg252 <= value;
8'd253: prev_reg253 <= value;
8'd254: prev_reg254 <= value;
8'd255: prev_reg255 <= value;
//----------------------------------------------------------
// Write Value to prev_reg using id as index (blocking)
8'd10: prev_reg10 = value;
8'd11: prev_reg11 = value;
8'd12: prev_reg12 = value;
8'd13: prev_reg13 = value;
8'd14: prev_reg14 = value;
8'd15: prev_reg15 = value;
8'd16: prev_reg16 = value;
8'd17: prev_reg17 = value;
8'd18: prev_reg18 = value;
8'd19: prev_reg19 = value;
8'd20: prev_reg20 = value;
8'd21: prev_reg21 = value;
8'd22: prev_reg22 = value;
8'd23: prev_reg23 = value;
8'd24: prev_reg24 = value;
8'd25: prev_reg25 = value;
8'd26: prev_reg26 = value;
8'd27: prev_reg27 = value;
8'd28: prev_reg28 = value;
8'd29: prev_reg29 = value;
8'd30: prev_reg30 = value;
8'd31: prev_reg31 = value;
8'd32: prev_reg32 = value;
8'd33: prev_reg33 = value;
8'd34: prev_reg34 = value;
8'd35: prev_reg35 = value;
8'd36: prev_reg36 = value;
8'd37: prev_reg37 = value;
8'd38: prev_reg38 = value;
8'd39: prev_reg39 = value;
8'd40: prev_reg40 = value;
8'd41: prev_reg41 = value;
8'd42: prev_reg42 = value;
8'd43: prev_reg43 = value;
8'd44: prev_reg44 = value;
8'd45: prev_reg45 = value;
8'd46: prev_reg46 = value;
8'd47: prev_reg47 = value;
8'd48: prev_reg48 = value;
8'd49: prev_reg49 = value;
8'd50: prev_reg50 = value;
8'd51: prev_reg51 = value;
8'd52: prev_reg52 = value;
8'd53: prev_reg53 = value;
8'd54: prev_reg54 = value;
8'd55: prev_reg55 = value;
8'd56: prev_reg56 = value;
8'd57: prev_reg57 = value;
8'd58: prev_reg58 = value;
8'd59: prev_reg59 = value;
8'd60: prev_reg60 = value;
8'd61: prev_reg61 = value;
8'd62: prev_reg62 = value;
8'd63: prev_reg63 = value;
8'd64: prev_reg64 = value;
8'd65: prev_reg65 = value;
8'd66: prev_reg66 = value;
8'd67: prev_reg67 = value;
8'd68: prev_reg68 = value;
8'd69: prev_reg69 = value;
8'd70: prev_reg70 = value;
8'd71: prev_reg71 = value;
8'd72: prev_reg72 = value;
8'd73: prev_reg73 = value;
8'd74: prev_reg74 = value;
8'd75: prev_reg75 = value;
8'd76: prev_reg76 = value;
8'd77: prev_reg77 = value;
8'd78: prev_reg78 = value;
8'd79: prev_reg79 = value;
8'd80: prev_reg80 = value;
8'd81: prev_reg81 = value;
8'd82: prev_reg82 = value;
8'd83: prev_reg83 = value;
8'd84: prev_reg84 = value;
8'd85: prev_reg85 = value;
8'd86: prev_reg86 = value;
8'd87: prev_reg87 = value;
8'd88: prev_reg88 = value;
8'd89: prev_reg89 = value;
8'd90: prev_reg90 = value;
8'd91: prev_reg91 = value;
8'd92: prev_reg92 = value;
8'd93: prev_reg93 = value;
8'd94: prev_reg94 = value;
8'd95: prev_reg95 = value;
8'd96: prev_reg96 = value;
8'd97: prev_reg97 = value;
8'd98: prev_reg98 = value;
8'd99: prev_reg99 = value;
8'd100: prev_reg100 = value;
8'd101: prev_reg101 = value;
8'd102: prev_reg102 = value;
8'd103: prev_reg103 = value;
8'd104: prev_reg104 = value;
8'd105: prev_reg105 = value;
8'd106: prev_reg106 = value;
8'd107: prev_reg107 = value;
8'd108: prev_reg108 = value;
8'd109: prev_reg109 = value;
8'd110: prev_reg110 = value;
8'd111: prev_reg111 = value;
8'd112: prev_reg112 = value;
8'd113: prev_reg113 = value;
8'd114: prev_reg114 = value;
8'd115: prev_reg115 = value;
8'd116: prev_reg116 = value;
8'd117: prev_reg117 = value;
8'd118: prev_reg118 = value;
8'd119: prev_reg119 = value;
8'd120: prev_reg120 = value;
8'd121: prev_reg121 = value;
8'd122: prev_reg122 = value;
8'd123: prev_reg123 = value;
8'd124: prev_reg124 = value;
8'd125: prev_reg125 = value;
8'd126: prev_reg126 = value;
8'd127: prev_reg127 = value;
8'd128: prev_reg128 = value;
8'd129: prev_reg129 = value;
8'd130: prev_reg130 = value;
8'd131: prev_reg131 = value;
8'd132: prev_reg132 = value;
8'd133: prev_reg133 = value;
8'd134: prev_reg134 = value;
8'd135: prev_reg135 = value;
8'd136: prev_reg136 = value;
8'd137: prev_reg137 = value;
8'd138: prev_reg138 = value;
8'd139: prev_reg139 = value;
8'd140: prev_reg140 = value;
8'd141: prev_reg141 = value;
8'd142: prev_reg142 = value;
8'd143: prev_reg143 = value;
8'd144: prev_reg144 = value;
8'd145: prev_reg145 = value;
8'd146: prev_reg146 = value;
8'd147: prev_reg147 = value;
8'd148: prev_reg148 = value;
8'd149: prev_reg149 = value;
8'd150: prev_reg150 = value;
8'd151: prev_reg151 = value;
8'd152: prev_reg152 = value;
8'd153: prev_reg153 = value;
8'd154: prev_reg154 = value;
8'd155: prev_reg155 = value;
8'd156: prev_reg156 = value;
8'd157: prev_reg157 = value;
8'd158: prev_reg158 = value;
8'd159: prev_reg159 = value;
8'd160: prev_reg160 = value;
8'd161: prev_reg161 = value;
8'd162: prev_reg162 = value;
8'd163: prev_reg163 = value;
8'd164: prev_reg164 = value;
8'd165: prev_reg165 = value;
8'd166: prev_reg166 = value;
8'd167: prev_reg167 = value;
8'd168: prev_reg168 = value;
8'd169: prev_reg169 = value;
8'd170: prev_reg170 = value;
8'd171: prev_reg171 = value;
8'd172: prev_reg172 = value;
8'd173: prev_reg173 = value;
8'd174: prev_reg174 = value;
8'd175: prev_reg175 = value;
8'd176: prev_reg176 = value;
8'd177: prev_reg177 = value;
8'd178: prev_reg178 = value;
8'd179: prev_reg179 = value;
8'd180: prev_reg180 = value;
8'd181: prev_reg181 = value;
8'd182: prev_reg182 = value;
8'd183: prev_reg183 = value;
8'd184: prev_reg184 = value;
8'd185: prev_reg185 = value;
8'd186: prev_reg186 = value;
8'd187: prev_reg187 = value;
8'd188: prev_reg188 = value;
8'd189: prev_reg189 = value;
8'd190: prev_reg190 = value;
8'd191: prev_reg191 = value;
8'd192: prev_reg192 = value;
8'd193: prev_reg193 = value;
8'd194: prev_reg194 = value;
8'd195: prev_reg195 = value;
8'd196: prev_reg196 = value;
8'd197: prev_reg197 = value;
8'd198: prev_reg198 = value;
8'd199: prev_reg199 = value;
8'd200: prev_reg200 = value;
8'd201: prev_reg201 = value;
8'd202: prev_reg202 = value;
8'd203: prev_reg203 = value;
8'd204: prev_reg204 = value;
8'd205: prev_reg205 = value;
8'd206: prev_reg206 = value;
8'd207: prev_reg207 = value;
8'd208: prev_reg208 = value;
8'd209: prev_reg209 = value;
8'd210: prev_reg210 = value;
8'd211: prev_reg211 = value;
8'd212: prev_reg212 = value;
8'd213: prev_reg213 = value;
8'd214: prev_reg214 = value;
8'd215: prev_reg215 = value;
8'd216: prev_reg216 = value;
8'd217: prev_reg217 = value;
8'd218: prev_reg218 = value;
8'd219: prev_reg219 = value;
8'd220: prev_reg220 = value;
8'd221: prev_reg221 = value;
8'd222: prev_reg222 = value;
8'd223: prev_reg223 = value;
8'd224: prev_reg224 = value;
8'd225: prev_reg225 = value;
8'd226: prev_reg226 = value;
8'd227: prev_reg227 = value;
8'd228: prev_reg228 = value;
8'd229: prev_reg229 = value;
8'd230: prev_reg230 = value;
8'd231: prev_reg231 = value;
8'd232: prev_reg232 = value;
8'd233: prev_reg233 = value;
8'd234: prev_reg234 = value;
8'd235: prev_reg235 = value;
8'd236: prev_reg236 = value;
8'd237: prev_reg237 = value;
8'd238: prev_reg238 = value;
8'd239: prev_reg239 = value;
8'd240: prev_reg240 = value;
8'd241: prev_reg241 = value;
8'd242: prev_reg242 = value;
8'd243: prev_reg243 = value;
8'd244: prev_reg244 = value;
8'd245: prev_reg245 = value;
8'd246: prev_reg246 = value;
8'd247: prev_reg247 = value;
8'd248: prev_reg248 = value;
8'd249: prev_reg249 = value;
8'd250: prev_reg250 = value;
8'd251: prev_reg251 = value;
8'd252: prev_reg252 = value;
8'd253: prev_reg253 = value;
8'd254: prev_reg254 = value;
8'd255: prev_reg255 = value;
//----------------------------------------------------------
// Read value frpm prev_reg using id as index
function [63:0] read_prev;
8'd0: read_prev = prev_reg0;
8'd1: read_prev = prev_reg1;
8'd2: read_prev = prev_reg2;
8'd3: read_prev = prev_reg3;
8'd4: read_prev = prev_reg4;
8'd5: read_prev = prev_reg5;
8'd6: read_prev = prev_reg6;
8'd7: read_prev = prev_reg7;
8'd8: read_prev = prev_reg8;
8'd9: read_prev = prev_reg9;
8'd10: read_prev = prev_reg10;
8'd11: read_prev = prev_reg11;
8'd12: read_prev = prev_reg12;
8'd13: read_prev = prev_reg13;
8'd14: read_prev = prev_reg14;
8'd15: read_prev = prev_reg15;
8'd16: read_prev = prev_reg16;
8'd17: read_prev = prev_reg17;
8'd18: read_prev = prev_reg18;
8'd19: read_prev = prev_reg19;
8'd20: read_prev = prev_reg20;
8'd21: read_prev = prev_reg21;
8'd22: read_prev = prev_reg22;
8'd23: read_prev = prev_reg23;
8'd24: read_prev = prev_reg24;
8'd25: read_prev = prev_reg25;
8'd26: read_prev = prev_reg26;
8'd27: read_prev = prev_reg27;
8'd28: read_prev = prev_reg28;
8'd29: read_prev = prev_reg29;
8'd30: read_prev = prev_reg30;
8'd31: read_prev = prev_reg31;
8'd32: read_prev = prev_reg32;
8'd33: read_prev = prev_reg33;
8'd34: read_prev = prev_reg34;
8'd35: read_prev = prev_reg35;
8'd36: read_prev = prev_reg36;
8'd37: read_prev = prev_reg37;
8'd38: read_prev = prev_reg38;
8'd39: read_prev = prev_reg39;
8'd40: read_prev = prev_reg40;
8'd41: read_prev = prev_reg41;
8'd42: read_prev = prev_reg42;
8'd43: read_prev = prev_reg43;
8'd44: read_prev = prev_reg44;
8'd45: read_prev = prev_reg45;
8'd46: read_prev = prev_reg46;
8'd47: read_prev = prev_reg47;
8'd48: read_prev = prev_reg48;
8'd49: read_prev = prev_reg49;
8'd50: read_prev = prev_reg50;
8'd51: read_prev = prev_reg51;
8'd52: read_prev = prev_reg52;
8'd53: read_prev = prev_reg53;
8'd54: read_prev = prev_reg54;
8'd55: read_prev = prev_reg55;
8'd56: read_prev = prev_reg56;
8'd57: read_prev = prev_reg57;
8'd58: read_prev = prev_reg58;
8'd59: read_prev = prev_reg59;
8'd60: read_prev = prev_reg60;
8'd61: read_prev = prev_reg61;
8'd62: read_prev = prev_reg62;
8'd63: read_prev = prev_reg63;
8'd64: read_prev = prev_reg64;
8'd65: read_prev = prev_reg65;
8'd66: read_prev = prev_reg66;
8'd67: read_prev = prev_reg67;
8'd68: read_prev = prev_reg68;
8'd69: read_prev = prev_reg69;
8'd70: read_prev = prev_reg70;
8'd71: read_prev = prev_reg71;
8'd72: read_prev = prev_reg72;
8'd73: read_prev = prev_reg73;
8'd74: read_prev = prev_reg74;
8'd75: read_prev = prev_reg75;
8'd76: read_prev = prev_reg76;
8'd77: read_prev = prev_reg77;
8'd78: read_prev = prev_reg78;
8'd79: read_prev = prev_reg79;
8'd80: read_prev = prev_reg80;
8'd81: read_prev = prev_reg81;
8'd82: read_prev = prev_reg82;
8'd83: read_prev = prev_reg83;
8'd84: read_prev = prev_reg84;
8'd85: read_prev = prev_reg85;
8'd86: read_prev = prev_reg86;
8'd87: read_prev = prev_reg87;
8'd88: read_prev = prev_reg88;
8'd89: read_prev = prev_reg89;
8'd90: read_prev = prev_reg90;
8'd91: read_prev = prev_reg91;
8'd92: read_prev = prev_reg92;
8'd93: read_prev = prev_reg93;
8'd94: read_prev = prev_reg94;
8'd95: read_prev = prev_reg95;
8'd96: read_prev = prev_reg96;
8'd97: read_prev = prev_reg97;
8'd98: read_prev = prev_reg98;
8'd99: read_prev = prev_reg99;
8'd100: read_prev = prev_reg100;
8'd101: read_prev = prev_reg101;
8'd102: read_prev = prev_reg102;
8'd103: read_prev = prev_reg103;
8'd104: read_prev = prev_reg104;
8'd105: read_prev = prev_reg105;
8'd106: read_prev = prev_reg106;
8'd107: read_prev = prev_reg107;
8'd108: read_prev = prev_reg108;
8'd109: read_prev = prev_reg109;
8'd110: read_prev = prev_reg110;
8'd111: read_prev = prev_reg111;
8'd112: read_prev = prev_reg112;
8'd113: read_prev = prev_reg113;
8'd114: read_prev = prev_reg114;
8'd115: read_prev = prev_reg115;
8'd116: read_prev = prev_reg116;
8'd117: read_prev = prev_reg117;
8'd118: read_prev = prev_reg118;
8'd119: read_prev = prev_reg119;
8'd120: read_prev = prev_reg120;
8'd121: read_prev = prev_reg121;
8'd122: read_prev = prev_reg122;
8'd123: read_prev = prev_reg123;
8'd124: read_prev = prev_reg124;
8'd125: read_prev = prev_reg125;
8'd126: read_prev = prev_reg126;
8'd127: read_prev = prev_reg127;
8'd128: read_prev = prev_reg128;
8'd129: read_prev = prev_reg129;
8'd130: read_prev = prev_reg130;
8'd131: read_prev = prev_reg131;
8'd132: read_prev = prev_reg132;
8'd133: read_prev = prev_reg133;
8'd134: read_prev = prev_reg134;
8'd135: read_prev = prev_reg135;
8'd136: read_prev = prev_reg136;
8'd137: read_prev = prev_reg137;
8'd138: read_prev = prev_reg138;
8'd139: read_prev = prev_reg139;
8'd140: read_prev = prev_reg140;
8'd141: read_prev = prev_reg141;
8'd142: read_prev = prev_reg142;
8'd143: read_prev = prev_reg143;
8'd144: read_prev = prev_reg144;
8'd145: read_prev = prev_reg145;
8'd146: read_prev = prev_reg146;
8'd147: read_prev = prev_reg147;
8'd148: read_prev = prev_reg148;
8'd149: read_prev = prev_reg149;
8'd150: read_prev = prev_reg150;
8'd151: read_prev = prev_reg151;
8'd152: read_prev = prev_reg152;
8'd153: read_prev = prev_reg153;
8'd154: read_prev = prev_reg154;
8'd155: read_prev = prev_reg155;
8'd156: read_prev = prev_reg156;
8'd157: read_prev = prev_reg157;
8'd158: read_prev = prev_reg158;
8'd159: read_prev = prev_reg159;
8'd160: read_prev = prev_reg160;
8'd161: read_prev = prev_reg161;
8'd162: read_prev = prev_reg162;
8'd163: read_prev = prev_reg163;
8'd164: read_prev = prev_reg164;
8'd165: read_prev = prev_reg165;
8'd166: read_prev = prev_reg166;
8'd167: read_prev = prev_reg167;
8'd168: read_prev = prev_reg168;
8'd169: read_prev = prev_reg169;
8'd170: read_prev = prev_reg170;
8'd171: read_prev = prev_reg171;
8'd172: read_prev = prev_reg172;
8'd173: read_prev = prev_reg173;
8'd174: read_prev = prev_reg174;
8'd175: read_prev = prev_reg175;
8'd176: read_prev = prev_reg176;
8'd177: read_prev = prev_reg177;
8'd178: read_prev = prev_reg178;
8'd179: read_prev = prev_reg179;
8'd180: read_prev = prev_reg180;
8'd181: read_prev = prev_reg181;
8'd182: read_prev = prev_reg182;
8'd183: read_prev = prev_reg183;
8'd184: read_prev = prev_reg184;
8'd185: read_prev = prev_reg185;
8'd186: read_prev = prev_reg186;
8'd187: read_prev = prev_reg187;
8'd188: read_prev = prev_reg188;
8'd189: read_prev = prev_reg189;
8'd190: read_prev = prev_reg190;
8'd191: read_prev = prev_reg191;
8'd192: read_prev = prev_reg192;
8'd193: read_prev = prev_reg193;
8'd194: read_prev = prev_reg194;
8'd195: read_prev = prev_reg195;
8'd196: read_prev = prev_reg196;
8'd197: read_prev = prev_reg197;
8'd198: read_prev = prev_reg198;
8'd199: read_prev = prev_reg199;
8'd200: read_prev = prev_reg200;
8'd201: read_prev = prev_reg201;
8'd202: read_prev = prev_reg202;
8'd203: read_prev = prev_reg203;
8'd204: read_prev = prev_reg204;
8'd205: read_prev = prev_reg205;
8'd206: read_prev = prev_reg206;
8'd207: read_prev = prev_reg207;
8'd208: read_prev = prev_reg208;
8'd209: read_prev = prev_reg209;
8'd210: read_prev = prev_reg210;
8'd211: read_prev = prev_reg211;
8'd212: read_prev = prev_reg212;
8'd213: read_prev = prev_reg213;
8'd214: read_prev = prev_reg214;
8'd215: read_prev = prev_reg215;
8'd216: read_prev = prev_reg216;
8'd217: read_prev = prev_reg217;
8'd218: read_prev = prev_reg218;
8'd219: read_prev = prev_reg219;
8'd220: read_prev = prev_reg220;
8'd221: read_prev = prev_reg221;
8'd222: read_prev = prev_reg222;
8'd223: read_prev = prev_reg223;
8'd224: read_prev = prev_reg224;
8'd225: read_prev = prev_reg225;
8'd226: read_prev = prev_reg226;
8'd227: read_prev = prev_reg227;
8'd228: read_prev = prev_reg228;
8'd229: read_prev = prev_reg229;
8'd230: read_prev = prev_reg230;
8'd231: read_prev = prev_reg231;
8'd232: read_prev = prev_reg232;
8'd233: read_prev = prev_reg233;
8'd234: read_prev = prev_reg234;
8'd235: read_prev = prev_reg235;
8'd236: read_prev = prev_reg236;
8'd237: read_prev = prev_reg237;
8'd238: read_prev = prev_reg238;
8'd239: read_prev = prev_reg239;
8'd240: read_prev = prev_reg240;
8'd241: read_prev = prev_reg241;
8'd242: read_prev = prev_reg242;
8'd243: read_prev = prev_reg243;
8'd244: read_prev = prev_reg244;
8'd245: read_prev = prev_reg245;
8'd246: read_prev = prev_reg246;
8'd247: read_prev = prev_reg247;
8'd248: read_prev = prev_reg248;
8'd249: read_prev = prev_reg249;
8'd250: read_prev = prev_reg250;
8'd251: read_prev = prev_reg251;
8'd252: read_prev = prev_reg252;
8'd253: read_prev = prev_reg253;
8'd254: read_prev = prev_reg254;
8'd255: read_prev = prev_reg255;
//----------------------------------------------------------
remap[4] = rd[4] ^ (rd[3] & oddwin);
//----------------------------------------------------------
// Initialize nas_pipe registers
initial begin : INIT_BLOCK
nas_pipe_enable = 1'b1; // Nas_pipe always enables itself
good_trap_detected = 1'b0;
@ (posedge `BENCH_SPC6_GCLK);
`TOP.th_last_act_cycle[mytnum] = 0;
`PR_INFO ("nas", `INFO, "T%0d Init shadow registers.",mytnum);
// POR for control registers
write_prev(`FPRS +`CTL_OFFSET,3'h4);
write_prev(`CLEANWIN +`CTL_OFFSET,3'h7);
write_prev(`CANSAVE +`CTL_OFFSET,3'h6);
write_prev(`FPRS+`CTL_OFFSET,3'h4);
// POR for PSTATE = 0x14 (PEF, PRIV = 1)
write_prev(`PSTATE + `CTL_OFFSET,'h14);
// POR for HPSTATE = 0x4034 (RED, HPRIV = 1)
write_prev(`HPSTATE + `CTL_OFFSET,'h24);
// POR for TL = = 0x6 [MAXTL]
write_prev(`TL + `CTL_OFFSET,'h6);
write_prev(`TT6 + `CTL_OFFSET,'h1);
// POR for GL = MAXGL = 3
write_prev(`GL + `CTL_OFFSET,`POR_GL);
// POR for VER = {003e, 0024, 01, 0036, 07}
write_prev(`VER + `CTL_OFFSET,{32'h003e0024,VER_reg[31:24],24'h030607});
// POR for *_cmpr registers is INT_DIS = 1
write_prev(`TICK_CMPR + `CTL_OFFSET,64'h8000000000000000);
write_prev(`STICK_CMPR + `CTL_OFFSET,64'h8000000000000000);
write_prev(`HSTICK_CMPR + `CTL_OFFSET,64'h8000000000000000);
// Need to define so that 1st instruction will print correctly
write_prev(`PC+`CTL_OFFSET,`POR_PC);
delta_prev[`PC_INDEX] = `BAD_PC;
irf_offset = (mytid%4)*32;
//----------------------------------------------------------
// For WMR, we will set to 0x0, so that initial deltas
// WMR for PSTATE = 0x14 (PEF, PRIV = 1)
// write_prev(`PSTATE + `CTL_OFFSET,'h00);
// WMR for HPSTATE = 0x4034 (RED, HPRIV = 1)
// write_prev(`HPSTATE + `CTL_OFFSET,'h00);
// WMR for TL = = 0x6 [MAXTL]
// write_prev(`TL + `CTL_OFFSET,'h0);
// write_prev(`TT6 + `CTL_OFFSET,'h1);
// WMR for GL = MAXGL = 3
// write_prev(`GL + `CTL_OFFSET,0);
//----------------------------------------------------------
// For POR, we will set to 0x0, so that initial deltas
// and prev state are all consistent with DUT. No values
`PR_ALWAYS ("arg", `ALWAYS,"T%0d Resetting Nas Pipe states for POR ..",mytnum);
delta_fx4[`NEXT_INDEX] <= `FIRST_INDEX;
delta_fx4[`FIRST_INDEX] <= 77'hx;
delta_fx5[`NEXT_INDEX] <= `FIRST_INDEX;
delta_fb[`NEXT_INDEX] <= `FIRST_INDEX;
delta_fw[`NEXT_INDEX] <= `FIRST_INDEX;
delta_fw1[`NEXT_INDEX] <= `FIRST_INDEX;
delta_fw2[`NEXT_INDEX] <= `FIRST_INDEX;
`PR_INFO ("nas", `INFO, "T%0d Init shadow registers.",mytnum);
// POR for control registers
write_prev(`FPRS +`CTL_OFFSET,3'h4);
write_prev(`CLEANWIN +`CTL_OFFSET,3'h7);
write_prev(`CANSAVE +`CTL_OFFSET,3'h6);
write_prev(`FPRS+`CTL_OFFSET,3'h4);
// POR for PSTATE = 0x14 (PEF, PRIV = 1)
write_prev(`PSTATE + `CTL_OFFSET,'h14);
// POR for HPSTATE = 0x4034 (RED, HPRIV = 1)
write_prev(`HPSTATE + `CTL_OFFSET,'h24);
// POR for TL = = 0x6 [MAXTL]
write_prev(`TL + `CTL_OFFSET,'h6);
write_prev(`TT6 + `CTL_OFFSET,'h1);
// POR for GL = MAXGL = 3
write_prev(`GL + `CTL_OFFSET,`POR_GL);
// POR for VER = {003e, 0024, 01, 0036, 07}
write_prev(`VER + `CTL_OFFSET,64'h003e002410030607);
// POR for *_cmpr registers is INT_DIS = 1
write_prev(`TICK_CMPR + `CTL_OFFSET,64'h8000000000000000);
write_prev(`STICK_CMPR + `CTL_OFFSET,64'h8000000000000000);
write_prev(`HSTICK_CMPR + `CTL_OFFSET,64'h8000000000000000);
// Need to define so that 1st instruction will print correctly
write_prev(`PC+`CTL_OFFSET,`POR_PC);
//----------------------------------------------------------
//----------------------------------------------------------
// Watch for Good/Bad trap
wire [5:0] mytnum = (mycid*8)+mytid;
// Delimiter changes whether flat or hierarchical netlist
wire myclk = tb_top.cpu.spc6.gclk;
wire dec_inst_valid_m = mytg ? tb_top.cpu.spc6.dec_inst_valid_m[1] : tb_top.cpu.spc6.dec_inst_valid_m[0];
wire [1:0] dec_tid_m = mytg ? tb_top.cpu.spc6.dec_tid1_m : tb_top.cpu.spc6.dec_tid0_m;
wire dec_flush_b = mytg ? tb_top.cpu.spc6.dec_flush_b[1] : tb_top.cpu.spc6.dec_flush_b[0];
wire tlu_flush_ifu = tb_top.cpu.spc6.tlu_flush_ifu[mytid];
wire [47:0] pc_d = mytg ? {tb_top.cpu.spc6.tlu_pc_1_d[47:2],2'b0} : {tb_top.cpu.spc6.tlu_pc_0_d[47:2],2'b0};
wire [31:0] op_d = mytg ? tb_top.cpu.spc6.dec_inst1_d[31:0] : tb_top.cpu.spc6.dec_inst0_d[31:0];
wire myclk = tb_top.cpu.spc6.gclk;
wire dec_inst_valid_m = mytg ? tb_top.cpu.spc6.dec_inst_valid_m[1] : tb_top.cpu.spc6.dec_inst_valid_m[0];
wire [1:0] dec_tid_m = mytg ? tb_top.cpu.spc6.dec_tid1_m : tb_top.cpu.spc6.dec_tid0_m;
wire dec_flush_b = mytg ? tb_top.cpu.spc6.dec_flush_b[1] : tb_top.cpu.spc6.dec_flush_b[0];
wire tlu_flush_ifu = tb_top.cpu.spc6.tlu_flush_ifu[mytid];
wire [47:0] pc_d = mytg ? {tb_top.cpu.spc6.tlu_pc_1_d[47:2],2'b0} : {tb_top.cpu.spc6.tlu_pc_0_d[47:2],2'b0};
wire [31:0] op_d = mytg ? tb_top.cpu.spc6.dec_inst1_d[31:0] : tb_top.cpu.spc6.dec_inst0_d[31:0];
wire inst_valid_b = dec_inst_valid_b && (dec_tid_b==mytid[1:0]) && !(dec_flush_b || tlu_flush_ifu);
always @ (posedge myclk) begin // {
dec_inst_valid_b <= dec_inst_valid_m;
inst_valid_w <= inst_valid_b;
inst_valid_fx4 <= inst_valid_w;
inst_valid_fx5 <= inst_valid_fx4;
inst_valid_fb <= inst_valid_fx5;
inst_valid_fw <= inst_valid_fb;
inst_valid_fw1 <= inst_valid_fw;
inst_valid_fw2 <= inst_valid_fw1;
if (`PARGS.th_check_enable[mytnum] && nas_pipe_enable) begin // {
if (inst_valid_fw2) begin // {
// Print PC/opcode for debugging
`PR_NORMAL ("nas", `NORMAL, "@%0d #%0d T%0d %h [%h]", $time, inst_count, mytnum, pc_fw2, op_fw2);
inst_count = inst_count + 1;
// End detection for GateSim runs
for (junk=0;junk<`PARGS.bad_trap_count;junk=junk+1) begin // {
if (({16'b0,pc_fw2}&`PC_MASK)===(`PARGS.bad_trap_addr[junk]&`PC_MASK)) begin // {
`PR_ERROR ("nas",`ERROR, "T%0d reached Bad Trap [GATESIM]", mytnum);
for (junk=0;junk<`PARGS.good_trap_count;junk=junk+1) begin // {
if (({16'b0,pc_fw2}&`PC_MASK)===(`PARGS.good_trap_addr[junk]&`PC_MASK)) begin // {
`TOP.finished_tids[mytnum] = 1'b1;
`PARGS.th_check_enable[mytnum] = 1'b0;
`PR_NORMAL ("nas", `NORMAL, "T%0d reached Good Trap. Disabling checking for thread %0d [GATESIM]", mytnum,mytnum);
//----------------------------------------------------------
//----------------------------------------------------------
//----------------------------------------------------------
input [71:0] TICK_CMPR_reg;
input [71:0] STICK_CMPR_reg;
input [71:0] HSTICK_CMPR_reg;
input [2:0] CANRESTORE_reg;
input [2:0] OTHERWIN_reg;
input [2:0] CLEANWIN_reg;
input [16:0] SOFTINT_reg;
input [16:0] rd_SOFTINT_reg;
input [63:0] INTR_RECEIVE_reg;
input [12:0] HPSTATE_reg;
input [63:0] CTXT_PRIM_0_reg;
input [63:0] CTXT_SEC_0_reg;
input [63:0] CTXT_PRIM_1_reg;
input [63:0] CTXT_SEC_1_reg;
input [63:0] LSU_CONTROL_reg;
input [63:0] I_TAG_ACC_reg;
input [63:0] D_TAG_ACC_reg;
input [63:0] WATCHPOINT_ADDR_reg;
input [151:0] Trap_Entry_1;
input [151:0] Trap_Entry_2;
input [151:0] Trap_Entry_3;
input [151:0] Trap_Entry_4;
input [151:0] Trap_Entry_5;
input [151:0] Trap_Entry_6;
input [1:0] frf_w2_valid;
input [1:0] frf_w1_valid;
input asi_valid; // ASI/ASR/PR writes done ..
input asi_in_progress; // ASI/ASR/PR in progess
//----------------------------------------------------------
//----------------------------------------------------------
//----------------------------------------------------------
// delta_* = {type(2bits),win(3bits),regnum(8bits),value(64bits)}
reg [`DELTA_WIDTH:0] delta_fx4 [0:(`MAX_INDEX)];
reg [`DELTA_WIDTH:0] delta_fx5 [0:(`MAX_INDEX)];
reg [`DELTA_WIDTH:0] delta_fb [0:(`MAX_INDEX)];
reg [`DELTA_WIDTH:0] delta_fw [0:(`MAX_INDEX)];
reg [`DELTA_WIDTH:0] delta_fw1 [0:(`MAX_INDEX)];
reg [`DELTA_WIDTH:0] delta_fw2 [0:(`MAX_INDEX)];
reg [`DELTA_WIDTH:0] delta_prev [0:(`MAX_INDEX)];
// need to change in several places in this file
reg [63:0] prev_reg0; // includes G,W,C,F registers
reg [63:0] prev_reg1; // includes G,W,C,F registers
reg [63:0] prev_reg2; // includes G,W,C,F registers
reg [63:0] prev_reg3; // includes G,W,C,F registers
reg [63:0] prev_reg4; // includes G,W,C,F registers
reg [63:0] prev_reg5; // includes G,W,C,F registers
reg [63:0] prev_reg6; // includes G,W,C,F registers
reg [63:0] prev_reg7; // includes G,W,C,F registers
reg [63:0] prev_reg8; // includes G,W,C,F registers
reg [63:0] prev_reg9; // includes G,W,C,F registers
reg [63:0] prev_reg10; // includes G,W,C,F registers
reg [63:0] prev_reg11; // includes G,W,C,F registers
reg [63:0] prev_reg12; // includes G,W,C,F registers
reg [63:0] prev_reg13; // includes G,W,C,F registers
reg [63:0] prev_reg14; // includes G,W,C,F registers
reg [63:0] prev_reg15; // includes G,W,C,F registers
reg [63:0] prev_reg16; // includes G,W,C,F registers
reg [63:0] prev_reg17; // includes G,W,C,F registers
reg [63:0] prev_reg18; // includes G,W,C,F registers
reg [63:0] prev_reg19; // includes G,W,C,F registers
reg [63:0] prev_reg20; // includes G,W,C,F registers
reg [63:0] prev_reg21; // includes G,W,C,F registers
reg [63:0] prev_reg22; // includes G,W,C,F registers
reg [63:0] prev_reg23; // includes G,W,C,F registers
reg [63:0] prev_reg24; // includes G,W,C,F registers
reg [63:0] prev_reg25; // includes G,W,C,F registers
reg [63:0] prev_reg26; // includes G,W,C,F registers
reg [63:0] prev_reg27; // includes G,W,C,F registers
reg [63:0] prev_reg28; // includes G,W,C,F registers
reg [63:0] prev_reg29; // includes G,W,C,F registers
reg [63:0] prev_reg30; // includes G,W,C,F registers
reg [63:0] prev_reg31; // includes G,W,C,F registers
reg [63:0] prev_reg32; // includes G,W,C,F registers
reg [63:0] prev_reg33; // includes G,W,C,F registers
reg [63:0] prev_reg34; // includes G,W,C,F registers
reg [63:0] prev_reg35; // includes G,W,C,F registers
reg [63:0] prev_reg36; // includes G,W,C,F registers
reg [63:0] prev_reg37; // includes G,W,C,F registers
reg [63:0] prev_reg38; // includes G,W,C,F registers
reg [63:0] prev_reg39; // includes G,W,C,F registers
reg [63:0] prev_reg40; // includes G,W,C,F registers
reg [63:0] prev_reg41; // includes G,W,C,F registers
reg [63:0] prev_reg42; // includes G,W,C,F registers
reg [63:0] prev_reg43; // includes G,W,C,F registers
reg [63:0] prev_reg44; // includes G,W,C,F registers
reg [63:0] prev_reg45; // includes G,W,C,F registers
reg [63:0] prev_reg46; // includes G,W,C,F registers
reg [63:0] prev_reg47; // includes G,W,C,F registers
reg [63:0] prev_reg48; // includes G,W,C,F registers
reg [63:0] prev_reg49; // includes G,W,C,F registers
reg [63:0] prev_reg50; // includes G,W,C,F registers
reg [63:0] prev_reg51; // includes G,W,C,F registers
reg [63:0] prev_reg52; // includes G,W,C,F registers
reg [63:0] prev_reg53; // includes G,W,C,F registers
reg [63:0] prev_reg54; // includes G,W,C,F registers
reg [63:0] prev_reg55; // includes G,W,C,F registers
reg [63:0] prev_reg56; // includes G,W,C,F registers
reg [63:0] prev_reg57; // includes G,W,C,F registers
reg [63:0] prev_reg58; // includes G,W,C,F registers
reg [63:0] prev_reg59; // includes G,W,C,F registers
reg [63:0] prev_reg60; // includes G,W,C,F registers
reg [63:0] prev_reg61; // includes G,W,C,F registers
reg [63:0] prev_reg62; // includes G,W,C,F registers
reg [63:0] prev_reg63; // includes G,W,C,F registers
reg [63:0] prev_reg64; // includes G,W,C,F registers
reg [63:0] prev_reg65; // includes G,W,C,F registers
reg [63:0] prev_reg66; // includes G,W,C,F registers
reg [63:0] prev_reg67; // includes G,W,C,F registers
reg [63:0] prev_reg68; // includes G,W,C,F registers
reg [63:0] prev_reg69; // includes G,W,C,F registers
reg [63:0] prev_reg70; // includes G,W,C,F registers
reg [63:0] prev_reg71; // includes G,W,C,F registers
reg [63:0] prev_reg72; // includes G,W,C,F registers
reg [63:0] prev_reg73; // includes G,W,C,F registers
reg [63:0] prev_reg74; // includes G,W,C,F registers
reg [63:0] prev_reg75; // includes G,W,C,F registers
reg [63:0] prev_reg76; // includes G,W,C,F registers
reg [63:0] prev_reg77; // includes G,W,C,F registers
reg [63:0] prev_reg78; // includes G,W,C,F registers
reg [63:0] prev_reg79; // includes G,W,C,F registers
reg [63:0] prev_reg80; // includes G,W,C,F registers
reg [63:0] prev_reg81; // includes G,W,C,F registers
reg [63:0] prev_reg82; // includes G,W,C,F registers
reg [63:0] prev_reg83; // includes G,W,C,F registers
reg [63:0] prev_reg84; // includes G,W,C,F registers
reg [63:0] prev_reg85; // includes G,W,C,F registers
reg [63:0] prev_reg86; // includes G,W,C,F registers
reg [63:0] prev_reg87; // includes G,W,C,F registers
reg [63:0] prev_reg88; // includes G,W,C,F registers
reg [63:0] prev_reg89; // includes G,W,C,F registers
reg [63:0] prev_reg90; // includes G,W,C,F registers
reg [63:0] prev_reg91; // includes G,W,C,F registers
reg [63:0] prev_reg92; // includes G,W,C,F registers
reg [63:0] prev_reg93; // includes G,W,C,F registers
reg [63:0] prev_reg94; // includes G,W,C,F registers
reg [63:0] prev_reg95; // includes G,W,C,F registers
reg [63:0] prev_reg96; // includes G,W,C,F registers
reg [63:0] prev_reg97; // includes G,W,C,F registers
reg [63:0] prev_reg98; // includes G,W,C,F registers
reg [63:0] prev_reg99; // includes G,W,C,F registers
reg [63:0] prev_reg100; // includes G,W,C,F registers
reg [63:0] prev_reg101; // includes G,W,C,F registers
reg [63:0] prev_reg102; // includes G,W,C,F registers
reg [63:0] prev_reg103; // includes G,W,C,F registers
reg [63:0] prev_reg104; // includes G,W,C,F registers
reg [63:0] prev_reg105; // includes G,W,C,F registers
reg [63:0] prev_reg106; // includes G,W,C,F registers
reg [63:0] prev_reg107; // includes G,W,C,F registers
reg [63:0] prev_reg108; // includes G,W,C,F registers
reg [63:0] prev_reg109; // includes G,W,C,F registers
reg [63:0] prev_reg110; // includes G,W,C,F registers
reg [63:0] prev_reg111; // includes G,W,C,F registers
reg [63:0] prev_reg112; // includes G,W,C,F registers
reg [63:0] prev_reg113; // includes G,W,C,F registers
reg [63:0] prev_reg114; // includes G,W,C,F registers
reg [63:0] prev_reg115; // includes G,W,C,F registers
reg [63:0] prev_reg116; // includes G,W,C,F registers
reg [63:0] prev_reg117; // includes G,W,C,F registers
reg [63:0] prev_reg118; // includes G,W,C,F registers
reg [63:0] prev_reg119; // includes G,W,C,F registers
reg [63:0] prev_reg120; // includes G,W,C,F registers
reg [63:0] prev_reg121; // includes G,W,C,F registers
reg [63:0] prev_reg122; // includes G,W,C,F registers
reg [63:0] prev_reg123; // includes G,W,C,F registers
reg [63:0] prev_reg124; // includes G,W,C,F registers
reg [63:0] prev_reg125; // includes G,W,C,F registers
reg [63:0] prev_reg126; // includes G,W,C,F registers
reg [63:0] prev_reg127; // includes G,W,C,F registers
reg [63:0] prev_reg128; // includes G,W,C,F registers
reg [63:0] prev_reg129; // includes G,W,C,F registers
reg [63:0] prev_reg130; // includes G,W,C,F registers
reg [63:0] prev_reg131; // includes G,W,C,F registers
reg [63:0] prev_reg132; // includes G,W,C,F registers
reg [63:0] prev_reg133; // includes G,W,C,F registers
reg [63:0] prev_reg134; // includes G,W,C,F registers
reg [63:0] prev_reg135; // includes G,W,C,F registers
reg [63:0] prev_reg136; // includes G,W,C,F registers
reg [63:0] prev_reg137; // includes G,W,C,F registers
reg [63:0] prev_reg138; // includes G,W,C,F registers
reg [63:0] prev_reg139; // includes G,W,C,F registers
reg [63:0] prev_reg140; // includes G,W,C,F registers
reg [63:0] prev_reg141; // includes G,W,C,F registers
reg [63:0] prev_reg142; // includes G,W,C,F registers
reg [63:0] prev_reg143; // includes G,W,C,F registers
reg [63:0] prev_reg144; // includes G,W,C,F registers
reg [63:0] prev_reg145; // includes G,W,C,F registers
reg [63:0] prev_reg146; // includes G,W,C,F registers
reg [63:0] prev_reg147; // includes G,W,C,F registers
reg [63:0] prev_reg148; // includes G,W,C,F registers
reg [63:0] prev_reg149; // includes G,W,C,F registers
reg [63:0] prev_reg150; // includes G,W,C,F registers
reg [63:0] prev_reg151; // includes G,W,C,F registers
reg [63:0] prev_reg152; // includes G,W,C,F registers
reg [63:0] prev_reg153; // includes G,W,C,F registers
reg [63:0] prev_reg154; // includes G,W,C,F registers
reg [63:0] prev_reg155; // includes G,W,C,F registers
reg [63:0] prev_reg156; // includes G,W,C,F registers
reg [63:0] prev_reg157; // includes G,W,C,F registers
reg [63:0] prev_reg158; // includes G,W,C,F registers
reg [63:0] prev_reg159; // includes G,W,C,F registers
reg [63:0] prev_reg160; // includes G,W,C,F registers
reg [63:0] prev_reg161; // includes G,W,C,F registers
reg [63:0] prev_reg162; // includes G,W,C,F registers
reg [63:0] prev_reg163; // includes G,W,C,F registers
reg [63:0] prev_reg164; // includes G,W,C,F registers
reg [63:0] prev_reg165; // includes G,W,C,F registers
reg [63:0] prev_reg166; // includes G,W,C,F registers
reg [63:0] prev_reg167; // includes G,W,C,F registers
reg [63:0] prev_reg168; // includes G,W,C,F registers
reg [63:0] prev_reg169; // includes G,W,C,F registers
reg [63:0] prev_reg170; // includes G,W,C,F registers
reg [63:0] prev_reg171; // includes G,W,C,F registers
reg [63:0] prev_reg172; // includes G,W,C,F registers
reg [63:0] prev_reg173; // includes G,W,C,F registers
reg [63:0] prev_reg174; // includes G,W,C,F registers
reg [63:0] prev_reg175; // includes G,W,C,F registers
reg [63:0] prev_reg176; // includes G,W,C,F registers
reg [63:0] prev_reg177; // includes G,W,C,F registers
reg [63:0] prev_reg178; // includes G,W,C,F registers
reg [63:0] prev_reg179; // includes G,W,C,F registers
reg [63:0] prev_reg180; // includes G,W,C,F registers
reg [63:0] prev_reg181; // includes G,W,C,F registers
reg [63:0] prev_reg182; // includes G,W,C,F registers
reg [63:0] prev_reg183; // includes G,W,C,F registers
reg [63:0] prev_reg184; // includes G,W,C,F registers
reg [63:0] prev_reg185; // includes G,W,C,F registers
reg [63:0] prev_reg186; // includes G,W,C,F registers
reg [63:0] prev_reg187; // includes G,W,C,F registers
reg [63:0] prev_reg188; // includes G,W,C,F registers
reg [63:0] prev_reg189; // includes G,W,C,F registers
reg [63:0] prev_reg190; // includes G,W,C,F registers
reg [63:0] prev_reg191; // includes G,W,C,F registers
reg [63:0] prev_reg192; // includes G,W,C,F registers
reg [63:0] prev_reg193; // includes G,W,C,F registers
reg [63:0] prev_reg194; // includes G,W,C,F registers
reg [63:0] prev_reg195; // includes G,W,C,F registers
reg [63:0] prev_reg196; // includes G,W,C,F registers
reg [63:0] prev_reg197; // includes G,W,C,F registers
reg [63:0] prev_reg198; // includes G,W,C,F registers
reg [63:0] prev_reg199; // includes G,W,C,F registers
reg [63:0] prev_reg200; // includes G,W,C,F registers
reg [63:0] prev_reg201; // includes G,W,C,F registers
reg [63:0] prev_reg202; // includes G,W,C,F registers
reg [63:0] prev_reg203; // includes G,W,C,F registers
reg [63:0] prev_reg204; // includes G,W,C,F registers
reg [63:0] prev_reg205; // includes G,W,C,F registers
reg [63:0] prev_reg206; // includes G,W,C,F registers
reg [63:0] prev_reg207; // includes G,W,C,F registers
reg [63:0] prev_reg208; // includes G,W,C,F registers
reg [63:0] prev_reg209; // includes G,W,C,F registers
reg [63:0] prev_reg210; // includes G,W,C,F registers
reg [63:0] prev_reg211; // includes G,W,C,F registers
reg [63:0] prev_reg212; // includes G,W,C,F registers
reg [63:0] prev_reg213; // includes G,W,C,F registers
reg [63:0] prev_reg214; // includes G,W,C,F registers
reg [63:0] prev_reg215; // includes G,W,C,F registers
reg [63:0] prev_reg216; // includes G,W,C,F registers
reg [63:0] prev_reg217; // includes G,W,C,F registers
reg [63:0] prev_reg218; // includes G,W,C,F registers
reg [63:0] prev_reg219; // includes G,W,C,F registers
reg [63:0] prev_reg220; // includes G,W,C,F registers
reg [63:0] prev_reg221; // includes G,W,C,F registers
reg [63:0] prev_reg222; // includes G,W,C,F registers
reg [63:0] prev_reg223; // includes G,W,C,F registers
reg [63:0] prev_reg224; // includes G,W,C,F registers
reg [63:0] prev_reg225; // includes G,W,C,F registers
reg [63:0] prev_reg226; // includes G,W,C,F registers
reg [63:0] prev_reg227; // includes G,W,C,F registers
reg [63:0] prev_reg228; // includes G,W,C,F registers
reg [63:0] prev_reg229; // includes G,W,C,F registers
reg [63:0] prev_reg230; // includes G,W,C,F registers
reg [63:0] prev_reg231; // includes G,W,C,F registers
reg [63:0] prev_reg232; // includes G,W,C,F registers
reg [63:0] prev_reg233; // includes G,W,C,F registers
reg [63:0] prev_reg234; // includes G,W,C,F registers
reg [63:0] prev_reg235; // includes G,W,C,F registers
reg [63:0] prev_reg236; // includes G,W,C,F registers
reg [63:0] prev_reg237; // includes G,W,C,F registers
reg [63:0] prev_reg238; // includes G,W,C,F registers
reg [63:0] prev_reg239; // includes G,W,C,F registers
reg [63:0] prev_reg240; // includes G,W,C,F registers
reg [63:0] prev_reg241; // includes G,W,C,F registers
reg [63:0] prev_reg242; // includes G,W,C,F registers
reg [63:0] prev_reg243; // includes G,W,C,F registers
reg [63:0] prev_reg244; // includes G,W,C,F registers
reg [63:0] prev_reg245; // includes G,W,C,F registers
reg [63:0] prev_reg246; // includes G,W,C,F registers
reg [63:0] prev_reg247; // includes G,W,C,F registers
reg [63:0] prev_reg248; // includes G,W,C,F registers
reg [63:0] prev_reg249; // includes G,W,C,F registers
reg [63:0] prev_reg250; // includes G,W,C,F registers
reg [63:0] prev_reg251; // includes G,W,C,F registers
reg [63:0] prev_reg252; // includes G,W,C,F registers
reg [63:0] prev_reg253; // includes G,W,C,F registers
reg [63:0] prev_reg254; // includes G,W,C,F registers
reg [63:0] prev_reg255; // includes G,W,C,F registers
reg [1:0] th_gl; // copy of GL_reg
reg frf_w1_skip_addr4_fw1;
reg frf_w1_skip_addr4_fw2;
reg [1:0] frf_w2_valid_fw;
reg [1:0] frf_w2_valid_bn;
reg [4:0] frf_w2_addr_fw;
reg [1:0] frf_w1_valid_fw;
reg [4:0] frf_w1_addr_fw;
reg wmr; // latched to get edge
reg por_a; // latched to get edge
reg por_b; // latched to get edge
reg nas_pipe_enable; // Turns on nas_pipe capture and Riesling SSTEP
wire [4:0] frf_w1_skip_addr;
wire [4:0] frf_w2_skip_addr;
reg good_trap_detected; // Used for -nosas only.
//----------------------------------------------------------
wire [`DELTA_WIDTH:0] delta_fx4_0;
wire [`DELTA_WIDTH:0] delta_fx4_1;
wire [`DELTA_WIDTH:0] delta_fx4_2;
wire [`DELTA_WIDTH:0] delta_fx4_3;
wire [`DELTA_WIDTH:0] delta_fx4_4;
wire [`DELTA_WIDTH:0] delta_fx4_5;
wire [`DELTA_WIDTH:0] delta_fx4_6;
wire [`DELTA_WIDTH:0] delta_fx4_7;
wire [`DELTA_WIDTH:0] delta_fx5_0;
wire [`DELTA_WIDTH:0] delta_fx5_1;
wire [`DELTA_WIDTH:0] delta_fx5_2;
wire [`DELTA_WIDTH:0] delta_fx5_3;
wire [`DELTA_WIDTH:0] delta_fx5_4;
wire [`DELTA_WIDTH:0] delta_fx5_5;
wire [`DELTA_WIDTH:0] delta_fx5_6;
wire [`DELTA_WIDTH:0] delta_fx5_7;
wire [`DELTA_WIDTH:0] delta_fb_0;
wire [`DELTA_WIDTH:0] delta_fb_1;
wire [`DELTA_WIDTH:0] delta_fb_2;
wire [`DELTA_WIDTH:0] delta_fb_3;
wire [`DELTA_WIDTH:0] delta_fb_4;
wire [`DELTA_WIDTH:0] delta_fb_5;
wire [`DELTA_WIDTH:0] delta_fb_6;
wire [`DELTA_WIDTH:0] delta_fb_7;
wire [`DELTA_WIDTH:0] delta_fw_0;
wire [`DELTA_WIDTH:0] delta_fw_1;
wire [`DELTA_WIDTH:0] delta_fw_2;
wire [`DELTA_WIDTH:0] delta_fw_3;
wire [`DELTA_WIDTH:0] delta_fw_4;
wire [`DELTA_WIDTH:0] delta_fw_5;
wire [`DELTA_WIDTH:0] delta_fw_6;
wire [`DELTA_WIDTH:0] delta_fw_7;
wire [`DELTA_WIDTH:0] delta_fw1_0;
wire [`DELTA_WIDTH:0] delta_fw1_1;
wire [`DELTA_WIDTH:0] delta_fw1_2;
wire [`DELTA_WIDTH:0] delta_fw1_3;
wire [`DELTA_WIDTH:0] delta_fw1_4;
wire [`DELTA_WIDTH:0] delta_fw1_5;
wire [`DELTA_WIDTH:0] delta_fw1_6;
wire [`DELTA_WIDTH:0] delta_fw1_7;
wire [`DELTA_WIDTH:0] delta_fw2_0;
wire [`DELTA_WIDTH:0] delta_fw2_1;
wire [`DELTA_WIDTH:0] delta_fw2_2;
wire [`DELTA_WIDTH:0] delta_fw2_3;
wire [`DELTA_WIDTH:0] delta_fw2_4;
wire [`DELTA_WIDTH:0] delta_fw2_5;
wire [`DELTA_WIDTH:0] delta_fw2_6;
wire [`DELTA_WIDTH:0] delta_fw2_7;
wire [`DELTA_WIDTH:0] delta_prev_0;
wire [`DELTA_WIDTH:0] delta_prev_1;
wire [`DELTA_WIDTH:0] delta_prev_2;
wire [`DELTA_WIDTH:0] delta_prev_3;
wire [`DELTA_WIDTH:0] delta_prev_4;
wire [`DELTA_WIDTH:0] delta_prev_5;
wire [`DELTA_WIDTH:0] delta_prev_6;
wire [`DELTA_WIDTH:0] delta_prev_7;
`PR_ALWAYS ("arg", `ALWAYS,"T%0d DEBUG_PIPE turned ON",mytnum);
//----------------------------------------------------------
// Note: no remap of %g,%o,%l,%i regs based on CWP or GL
assign g0 = (mytid<=3) ? `IRF7_EXU0[( 0+irf_offset)] : `IRF7_EXU1[( 0+irf_offset)];
assign g1 = (mytid<=3) ? `IRF7_EXU0[( 1+irf_offset)] : `IRF7_EXU1[( 1+irf_offset)];
assign g2 = (mytid<=3) ? `IRF7_EXU0[( 2+irf_offset)] : `IRF7_EXU1[( 2+irf_offset)];
assign g3 = (mytid<=3) ? `IRF7_EXU0[( 3+irf_offset)] : `IRF7_EXU1[( 3+irf_offset)];
assign g4 = (mytid<=3) ? `IRF7_EXU0[( 4+irf_offset)] : `IRF7_EXU1[( 4+irf_offset)];
assign g5 = (mytid<=3) ? `IRF7_EXU0[( 5+irf_offset)] : `IRF7_EXU1[( 5+irf_offset)];
assign g6 = (mytid<=3) ? `IRF7_EXU0[( 6+irf_offset)] : `IRF7_EXU1[( 6+irf_offset)];
assign g7 = (mytid<=3) ? `IRF7_EXU0[( 7+irf_offset)] : `IRF7_EXU1[( 7+irf_offset)];
assign o0 = (mytid<=3) ? `IRF7_EXU0[( 8+irf_offset)] : `IRF7_EXU1[( 8+irf_offset)];
assign o1 = (mytid<=3) ? `IRF7_EXU0[( 9+irf_offset)] : `IRF7_EXU1[( 9+irf_offset)];
assign o2 = (mytid<=3) ? `IRF7_EXU0[(10+irf_offset)] : `IRF7_EXU1[(10+irf_offset)];
assign o3 = (mytid<=3) ? `IRF7_EXU0[(11+irf_offset)] : `IRF7_EXU1[(11+irf_offset)];
assign o4 = (mytid<=3) ? `IRF7_EXU0[(12+irf_offset)] : `IRF7_EXU1[(12+irf_offset)];
assign o5 = (mytid<=3) ? `IRF7_EXU0[(13+irf_offset)] : `IRF7_EXU1[(13+irf_offset)];
assign o6 = (mytid<=3) ? `IRF7_EXU0[(14+irf_offset)] : `IRF7_EXU1[(14+irf_offset)];
assign o7 = (mytid<=3) ? `IRF7_EXU0[(15+irf_offset)] : `IRF7_EXU1[(15+irf_offset)];
assign l0 = (mytid<=3) ? `IRF7_EXU0[(16+irf_offset)] : `IRF7_EXU1[(16+irf_offset)];
assign l1 = (mytid<=3) ? `IRF7_EXU0[(17+irf_offset)] : `IRF7_EXU1[(17+irf_offset)];
assign l2 = (mytid<=3) ? `IRF7_EXU0[(18+irf_offset)] : `IRF7_EXU1[(18+irf_offset)];
assign l3 = (mytid<=3) ? `IRF7_EXU0[(19+irf_offset)] : `IRF7_EXU1[(19+irf_offset)];
assign l4 = (mytid<=3) ? `IRF7_EXU0[(20+irf_offset)] : `IRF7_EXU1[(20+irf_offset)];
assign l5 = (mytid<=3) ? `IRF7_EXU0[(21+irf_offset)] : `IRF7_EXU1[(21+irf_offset)];
assign l6 = (mytid<=3) ? `IRF7_EXU0[(22+irf_offset)] : `IRF7_EXU1[(22+irf_offset)];
assign l7 = (mytid<=3) ? `IRF7_EXU0[(23+irf_offset)] : `IRF7_EXU1[(23+irf_offset)];
assign i0 = (mytid<=3) ? `IRF7_EXU0[(24+irf_offset)] : `IRF7_EXU1[(24+irf_offset)];
assign i1 = (mytid<=3) ? `IRF7_EXU0[(25+irf_offset)] : `IRF7_EXU1[(25+irf_offset)];
assign i2 = (mytid<=3) ? `IRF7_EXU0[(26+irf_offset)] : `IRF7_EXU1[(26+irf_offset)];
assign i3 = (mytid<=3) ? `IRF7_EXU0[(27+irf_offset)] : `IRF7_EXU1[(27+irf_offset)];
assign i4 = (mytid<=3) ? `IRF7_EXU0[(28+irf_offset)] : `IRF7_EXU1[(28+irf_offset)];
assign i5 = (mytid<=3) ? `IRF7_EXU0[(29+irf_offset)] : `IRF7_EXU1[(29+irf_offset)];
assign i6 = (mytid<=3) ? `IRF7_EXU0[(30+irf_offset)] : `IRF7_EXU1[(30+irf_offset)];
assign i7 = (mytid<=3) ? `IRF7_EXU0[(31+irf_offset)] : `IRF7_EXU1[(31+irf_offset)];
//----------------------------------------------------------
assign frf_0 = `FRF7_EVEN[(mytid*32)+ 0];
assign frf_2 = `FRF7_EVEN[(mytid*32)+ 1];
assign frf_4 = `FRF7_EVEN[(mytid*32)+ 2];
assign frf_6 = `FRF7_EVEN[(mytid*32)+ 3];
assign frf_8 = `FRF7_EVEN[(mytid*32)+ 4];
assign frf_10 = `FRF7_EVEN[(mytid*32)+ 5];
assign frf_12 = `FRF7_EVEN[(mytid*32)+ 6];
assign frf_14 = `FRF7_EVEN[(mytid*32)+ 7];
assign frf_16 = `FRF7_EVEN[(mytid*32)+ 8];
assign frf_18 = `FRF7_EVEN[(mytid*32)+ 9];
assign frf_20 = `FRF7_EVEN[(mytid*32)+ 10];
assign frf_22 = `FRF7_EVEN[(mytid*32)+ 11];
assign frf_24 = `FRF7_EVEN[(mytid*32)+ 12];
assign frf_26 = `FRF7_EVEN[(mytid*32)+ 13];
assign frf_28 = `FRF7_EVEN[(mytid*32)+ 14];
assign frf_30 = `FRF7_EVEN[(mytid*32)+ 15];
assign frf_32 = `FRF7_EVEN[(mytid*32)+ 16];
assign frf_34 = `FRF7_EVEN[(mytid*32)+ 17];
assign frf_36 = `FRF7_EVEN[(mytid*32)+ 18];
assign frf_38 = `FRF7_EVEN[(mytid*32)+ 19];
assign frf_40 = `FRF7_EVEN[(mytid*32)+ 20];
assign frf_42 = `FRF7_EVEN[(mytid*32)+ 21];
assign frf_44 = `FRF7_EVEN[(mytid*32)+ 22];
assign frf_46 = `FRF7_EVEN[(mytid*32)+ 23];
assign frf_48 = `FRF7_EVEN[(mytid*32)+ 24];
assign frf_50 = `FRF7_EVEN[(mytid*32)+ 25];
assign frf_52 = `FRF7_EVEN[(mytid*32)+ 26];
assign frf_54 = `FRF7_EVEN[(mytid*32)+ 27];
assign frf_56 = `FRF7_EVEN[(mytid*32)+ 28];
assign frf_58 = `FRF7_EVEN[(mytid*32)+ 29];
assign frf_60 = `FRF7_EVEN[(mytid*32)+ 30];
assign frf_62 = `FRF7_EVEN[(mytid*32)+ 31];
assign frf_1 = `FRF7_ODD[(mytid*32)+ 0];
assign frf_3 = `FRF7_ODD[(mytid*32)+ 1];
assign frf_5 = `FRF7_ODD[(mytid*32)+ 2];
assign frf_7 = `FRF7_ODD[(mytid*32)+ 3];
assign frf_9 = `FRF7_ODD[(mytid*32)+ 4];
assign frf_11 = `FRF7_ODD[(mytid*32)+ 5];
assign frf_13 = `FRF7_ODD[(mytid*32)+ 6];
assign frf_15 = `FRF7_ODD[(mytid*32)+ 7];
assign frf_17 = `FRF7_ODD[(mytid*32)+ 8];
assign frf_19 = `FRF7_ODD[(mytid*32)+ 9];
assign frf_21 = `FRF7_ODD[(mytid*32)+ 10];
assign frf_23 = `FRF7_ODD[(mytid*32)+ 11];
assign frf_25 = `FRF7_ODD[(mytid*32)+ 12];
assign frf_27 = `FRF7_ODD[(mytid*32)+ 13];
assign frf_29 = `FRF7_ODD[(mytid*32)+ 14];
assign frf_31 = `FRF7_ODD[(mytid*32)+ 15];
assign frf_33 = `FRF7_ODD[(mytid*32)+ 16];
assign frf_35 = `FRF7_ODD[(mytid*32)+ 17];
assign frf_37 = `FRF7_ODD[(mytid*32)+ 18];
assign frf_39 = `FRF7_ODD[(mytid*32)+ 19];
assign frf_41 = `FRF7_ODD[(mytid*32)+ 20];
assign frf_43 = `FRF7_ODD[(mytid*32)+ 21];
assign frf_45 = `FRF7_ODD[(mytid*32)+ 22];
assign frf_47 = `FRF7_ODD[(mytid*32)+ 23];
assign frf_49 = `FRF7_ODD[(mytid*32)+ 24];
assign frf_51 = `FRF7_ODD[(mytid*32)+ 25];
assign frf_53 = `FRF7_ODD[(mytid*32)+ 26];
assign frf_55 = `FRF7_ODD[(mytid*32)+ 27];
assign frf_57 = `FRF7_ODD[(mytid*32)+ 28];
assign frf_59 = `FRF7_ODD[(mytid*32)+ 29];
assign frf_61 = `FRF7_ODD[(mytid*32)+ 30];
assign frf_63 = `FRF7_ODD[(mytid*32)+ 31];
//----------------------------------------------------------
assign delta_fx4_0 = delta_fx4[0];
assign delta_fx4_1 = delta_fx4[1];
assign delta_fx4_2 = delta_fx4[2];
assign delta_fx4_3 = delta_fx4[3];
assign delta_fx4_4 = delta_fx4[4];
assign delta_fx4_5 = delta_fx4[5];
assign delta_fx4_6 = delta_fx4[6];
assign delta_fx4_7 = delta_fx4[7];
assign delta_fx5_0 = delta_fx5[0];
assign delta_fx5_1 = delta_fx5[1];
assign delta_fx5_2 = delta_fx5[2];
assign delta_fx5_3 = delta_fx5[3];
assign delta_fx5_4 = delta_fx5[4];
assign delta_fx5_5 = delta_fx5[5];
assign delta_fx5_6 = delta_fx5[6];
assign delta_fx5_7 = delta_fx5[7];
assign delta_fb_0 = delta_fb[0];
assign delta_fb_1 = delta_fb[1];
assign delta_fb_2 = delta_fb[2];
assign delta_fb_3 = delta_fb[3];
assign delta_fb_4 = delta_fb[4];
assign delta_fb_5 = delta_fb[5];
assign delta_fb_6 = delta_fb[6];
assign delta_fb_7 = delta_fb[7];
assign delta_fw_0 = delta_fw[0];
assign delta_fw_1 = delta_fw[1];
assign delta_fw_2 = delta_fw[2];
assign delta_fw_3 = delta_fw[3];
assign delta_fw_4 = delta_fw[4];
assign delta_fw_5 = delta_fw[5];
assign delta_fw_6 = delta_fw[6];
assign delta_fw_7 = delta_fw[7];
assign delta_fw1_0 = delta_fw1[0];
assign delta_fw1_1 = delta_fw1[1];
assign delta_fw1_2 = delta_fw1[2];
assign delta_fw1_3 = delta_fw1[3];
assign delta_fw1_4 = delta_fw1[4];
assign delta_fw1_5 = delta_fw1[5];
assign delta_fw1_6 = delta_fw1[6];
assign delta_fw1_7 = delta_fw1[7];
assign delta_fw2_0 = delta_fw2[0];
assign delta_fw2_1 = delta_fw2[1];
assign delta_fw2_2 = delta_fw2[2];
assign delta_fw2_3 = delta_fw2[3];
assign delta_fw2_4 = delta_fw2[4];
assign delta_fw2_5 = delta_fw2[5];
assign delta_fw2_6 = delta_fw2[6];
assign delta_fw2_7 = delta_fw2[7];
assign delta_prev_0 = delta_prev[0];
assign delta_prev_1 = delta_prev[1];
assign delta_prev_2 = delta_prev[2];
assign delta_prev_3 = delta_prev[3];
assign delta_prev_4 = delta_prev[4];
assign delta_prev_5 = delta_prev[5];
assign delta_prev_6 = delta_prev[6];
assign delta_prev_7 = delta_prev[7];
//----------------------------------------------------------
//----------------------------------------------------------
assign mytnum = (mycid*8)+mytid;
assign mytg = mytid >> 2;
assign exu_complete = exu_valid & ~(`PROBES7.clkstop_d5|`TOP.in_reset|`SPC7.tcu_scan_en);
assign imul_complete = imul_valid & ~(`TOP.in_reset|`SPC7.tcu_scan_en);
assign idiv_complete = idiv_valid & ~(`TOP.in_reset|`SPC7.tcu_scan_en);
assign tlu_complete = tlu_complete_3 ;
assign fp_complete = fp_valid & ~(`TOP.in_reset|`SPC7.tcu_scan_en);
assign fdiv_complete = fdiv_valid & ~(`TOP.in_reset|`SPC7.tcu_scan_en);
assign lsu_complete = lsu_valid & ~(`TOP.in_reset|`SPC7.tcu_scan_en);
assign asi_complete = asi_valid & ~(`TOP.in_reset|`SPC7.tcu_scan_en);
assign complete_w = (exu_complete << `EXU_INDEX) |
(lsu_complete << `LSU_INDEX) |
(tlu_complete << `TLU_INDEX) |
(asi_complete << `ASI_INDEX) ;
assign oddwin = CWP_reg % 2;
assign frf_w1_valid_even = (frf_w1_tid_fw == mytid) & frf_w1_valid_fw[1];
assign frf_w1_valid_odd = (frf_w1_tid_fw == mytid) & frf_w1_valid_fw[0];
assign frf_w2_valid_even = (frf_w2_tid_fw == mytid) & frf_w2_valid_fw[1];
assign frf_w2_valid_odd = (frf_w2_tid_fw == mytid) & frf_w2_valid_fw[0];
assign frf_w1_skip_addr = frf_w1_addr_fw;
assign frf_w2_skip_addr = frf_w2_addr_fw;
// NOTE - ADD_TSB_CFG will never be used for Axis or Tharas
wire [63:0] ctxt_z_tsb_cfg0_reg = `PROBES7.ctxt_z_tsb_cfg0_reg[mytid];
wire [63:0] ctxt_z_tsb_cfg1_reg = `PROBES7.ctxt_z_tsb_cfg1_reg[mytid];
wire [63:0] ctxt_z_tsb_cfg2_reg = `PROBES7.ctxt_z_tsb_cfg2_reg[mytid];
wire [63:0] ctxt_z_tsb_cfg3_reg = `PROBES7.ctxt_z_tsb_cfg3_reg[mytid];
wire [63:0] ctxt_nz_tsb_cfg0_reg = `PROBES7.ctxt_nz_tsb_cfg0_reg[mytid];
wire [63:0] ctxt_nz_tsb_cfg1_reg = `PROBES7.ctxt_nz_tsb_cfg1_reg[mytid];
wire [63:0] ctxt_nz_tsb_cfg2_reg = `PROBES7.ctxt_nz_tsb_cfg2_reg[mytid];
wire [63:0] ctxt_nz_tsb_cfg3_reg = `PROBES7.ctxt_nz_tsb_cfg3_reg[mytid];
//----------------------------------------------------------
always @ (posedge `BENCH_SPC7_GCLK) begin // {
// TLU is async to the execution pipeline
// but needs to be delayed to allow CWP, etc to update and be stable
// before arch state is captured and diff_reg is called.
// FDIV was moved from fw1 to fw to allow FPRS to be stable before capture
tlu_complete_1 <= tlu_valid & ~(`TOP.in_reset|`SPC7.tcu_scan_en);
tlu_complete_2 <= tlu_complete_1;
tlu_complete_3 <= tlu_complete_2;
itagacc_fx5 <= I_TAG_ACC_reg; // Signal changes in W so need to pipeline to fw2
itagacc_fb <= itagacc_fx5;
itagacc_fw <= itagacc_fb;
itagacc_fw1 <= itagacc_fw;
itagacc_fw2 <= itagacc_fw1;
dtagacc_fx5 <= D_TAG_ACC_reg; // Signal changes in W so need to pipeline to fw2
dtagacc_fb <= dtagacc_fx5;
dtagacc_fw <= dtagacc_fb;
dtagacc_fw1 <= dtagacc_fw;
dtagacc_fw2 <= dtagacc_fw1;
dsfar_fb <= DSFAR_reg; // Signal changes in W+1 so need to pipeline to fw2
complete_fx4 <= complete_w;
complete_fx5 <= complete_fx4 ;
complete_fb <= complete_fx5 |
(idiv_complete << `IDIV_INDEX);
complete_fw <= complete_fb |
(fdiv_complete << `FDIV_INDEX) |
(imul_complete << `IMUL_INDEX);
complete_fw1 <= complete_fw |
(fp_complete << `FP_INDEX);
complete_fw2 <= complete_fw1;
frf_w1_valid_fw1 <= (frf_w1_valid_odd | frf_w1_valid_even) & fp_complete;
frf_w1_valid_fw2 <= frf_w1_valid_fw1;
frf_w1_skip_addr4_fw1 <= frf_w1_skip_addr[4];
frf_w1_skip_addr4_fw2 <= frf_w1_skip_addr4_fw1;
frf_w2_valid_fw <= frf_w2_valid_bn;
frf_w2_tid_fw <= frf_w2_tid;
frf_w2_addr_fw <= frf_w2_addr;
frf_w1_valid_fw <= frf_w1_valid;
frf_w1_tid_fw <= frf_w1_tid;
frf_w1_addr_fw <= frf_w1_addr;
if (~thread_running & `SPC7.tcu_core_running[mytid])
`TOP.th_last_act_cycle[mytnum] = `TOP.core_cycle_cnt;
thread_running <= `SPC7.tcu_core_running[mytid];
// Reset some register prev state on wmr negation
if (`SPC7.rst_wmr_protect && ~wmr)
wmr <= `SPC7.rst_wmr_protect;
if (`SPC7.rst_wmr_protect)
//----------------------------------------------------------
// Holding state for registers that may be updated asynchronously
// after synchronous update, but before capture/step. Also for reads,
// when register is read and modified before capture/step ..
// We capture the value /write time, and use that for sstep,
// ignoring any async updates, which are sent in the NEXT sstep ..
reg [63:0] asi_updated_int_rec;
reg asi_wr_int_rec_delay;
reg [16:0] asi_updated_softint;
reg asi_wr_softint_delay;
reg [16:0] asi_softint_wrdata;
always @(posedge `BENCH_SPC7_GCLK) begin // {
// Corner case : If async and sync wr occur in same clock, then the async
// update takes place. In this case we have to capture the
// value of the write WITHOUT async bit being set, so that
// we can sync with Riesling's sync write ..
asi_wr_int_rec_delay <= ( `SPC7.tlu.cth.asi_wr_int_rec[mytid] |
`SPC7.tlu.asi_rd_inc_vec_2[mytid]);
if (`SPC7.tlu.cth.asi_wr_int_rec[mytid] |
((`SPC7.tlu.asi.rd_inc_vec) &&
(`SPC7.tlu.asi.rd_tid_dec[mytid])) |
(`SPC7.tlu.asi_rd_int_rec &
`SPC7.tlu.cth.int_rec_mux_sel==mytid))
if (`SPC7.tlu.cth.asi_wr_int_rec[mytid])
asi_updated_int_rec <= `SPC7.tlu.cth.int_rec ;
else if ( (`SPC7.tlu.asi.rd_inc_vec) &&
(`SPC7.tlu.asi.rd_tid_dec[mytid]) )
if (`SPC7.tlu.cth.cxi_wr_int_dis[mytid]) begin
asi_updated_int_rec <= INTR_RECEIVE_reg & `SPC7.tlu.cth.int_rec_muxed_;
asi_updated_int_rec[`SPC7.tlu.cth.incoming_vector_in] <= 1'b0 ;
asi_updated_int_rec <= `SPC7.tlu.cth.int_rec_muxed ;
asi_updated_int_rec[`SPC7.tlu.cth.incoming_vector_in] <= 1'b0 ;
asi_updated_int_rec <= INTR_RECEIVE_reg;
asi_rdwr_int_rec <= 1'b1;
else if (complete_fw1 && !`NASTOP.sstep_early[mytnum])
asi_rdwr_int_rec <= 1'b0;
asi_wr_hintp_delay <= `SPC7.tlu.asi_wr_hintp[mytid];
if (`SPC7.tlu.asi_wr_hintp[mytid] |
`SPC7.tlu.asi_rd_hintp[mytid])
if (`SPC7.tlu.asi_wr_hintp[mytid])
asi_updated_hintp <= `SPC7.tlu.asi_wr_data_0[0] ;
asi_updated_hintp <= HINTP_reg;
else if (complete_fw1 && !`NASTOP.sstep_early[mytnum])
asi_wr_softint_delay <= (`SPC7.tlu.asi_wr_softint[mytid] |
`SPC7.tlu.asi_wr_clear_softint[mytid] |
`SPC7.tlu.asi_wr_set_softint[mytid]);
if (`SPC7.tlu.asi_wr_clear_softint[mytid])
asi_softint_wrdata <= ~`SPC7.tlu.asi_wr_data_0[16:0] & rd_SOFTINT_reg;
else if (`SPC7.tlu.asi_wr_set_softint[mytid])
asi_softint_wrdata <= `SPC7.tlu.asi_wr_data_0[16:0] | rd_SOFTINT_reg;
asi_softint_wrdata <= `SPC7.tlu.asi_wr_data_0[16:0];
if (asi_wr_softint_delay | `SPC7.tlu.asi_rd_softint[mytid])
if (asi_wr_softint_delay)
asi_updated_softint <= asi_softint_wrdata ;
asi_updated_softint <= rd_SOFTINT_reg ;
asi_rdwr_softint <= 1'b1;
else if (complete_fw1 && !`NASTOP.sstep_early[mytnum])
asi_rdwr_softint <= 1'b0;
//----------------------------------------------------------
// Negedge sampling to avoid race on specific signals ..
always @ (negedge `BENCH_SPC7_GCLK) begin // {
frf_w2_valid_bn <= frf_w2_valid;
//----------------------------------------------------------
// When instruction completes,
// Push differences to simics
always @ (posedge `BENCH_SPC7_GCLK) begin // {
if (`PARGS.th_check_enable[mytnum] && nas_pipe_enable && ~`SPC7.tcu_scan_en && ~`TOP.in_por) begin // {
// Update window registers
if (CWP_reg != `NASTOP.th_cwp[mytnum]) begin // {
copy_win (CWP_reg,`NASTOP.th_cwp[mytnum]);
`NASTOP.th_cwp[mytnum] = CWP_reg;
// Update global registers
// Wait for warm-reset flush related toggling to settle
if (GL_reg != th_gl) begin // {
if (`SPC7.spc_core_running_status[mytid] &
~`SPC7.rst_wmr_protect) begin // {
copy_global (GL_reg,th_gl);
// Check for bad signal values
// if NASTOP.sstep_sent[tid]=1,
// then SSTEP was set by another module (i.e. tlb_sync)
if (`PARGS.nas_check_on) begin // {
mytime = `TOP.core_cycle_cnt-1;
if (complete_fw2 && (`NASTOP.sstep_sent[mytnum]==1'b0)) begin // {
`PR_INFO ("pli_nas", `INFO, " C%0d T%0d PLI_SSTEP tid=%d pc=%h ts=%0d ",
mycid,mytid,mytnum,pc_fw2,mytime);
junk = $sim_send(`PLI_SSTEP, mytnum);
// Always clear sstep_early
// In case tlb_sync asserted it too late for complete_fw2
`NASTOP.sstep_early[mytnum] <= 1'b0;
else if (complete_fw2) begin // {
`NASTOP.sstep_sent[mytnum] <= 1'b0; // re-arm SSTEP
`NASTOP.sstep_early[mytnum] <= 1'b0;
`PR_INFO ("pli_nas", `INFO, " C%0d T%0d PLI_SSTEP tid=%d pc=%h ts=%0d (nas_pipe: skip sstep. rearm sstep. sstep_sent=0)",
mycid,mytid,mytnum,pc_fw2,mytime);
// Only capture if something completes and not first instruction
if (complete_fw2 && !first_op) begin // {
push_simics; // Use with AXIS to keep from getting timeout
// Pipeline runs continuously
// Other than when in POR ..
// Only save to delta_prev when something completes
`TOP.last_act_cycle = `TOP.core_cycle_cnt; //$time;
`TOP.th_last_act_cycle[mytnum] = `TOP.last_act_cycle;
// If something was captured but no instruction is in the pipeline
if ((delta_fw2[`NEXT_INDEX]!=`FIRST_INDEX) && (complete_fw2 == 0))
for (myindex=`FIRST_INDEX; myindex<delta_fw2[`NEXT_INDEX]; myindex=myindex+1)
print_entry (delta_fw2[myindex]);
`PR_ERROR ("nas",`ERROR, "T%0d Unexpected Reg change in DUT. Special case - no instruction retired.", mytnum);
// End detection for non-sas runs ..
for (junk=0;junk<`PARGS.bad_trap_count;junk=junk+1)
if (({16'b0,pc_fw2}&`PC_MASK) ===
(`PARGS.bad_trap_addr[junk]&`PC_MASK)) begin // {
// Disable nas_pipe processing (capture & SSTEP)
// to speed up simulation (minimize socket traffic,etc)
if (! `PARGS.nas_check_on) begin //{
`PR_ERROR ("nas",`ERROR, "T%0d reached Bad Trap", mytnum);
for (junk=0;junk<`PARGS.good_trap_count;junk=junk+1)
if ((|complete_fw2) && (({16'b0,pc_fw2}&`PC_MASK) ===
(`PARGS.good_trap_addr[junk]&`PC_MASK))) begin // {
// Disable nas_pipe processing (capture & SSTEP)
// to speed up simulation (minimize socket traffic,etc)
if (! `PARGS.nas_check_on) begin //{
good_trap_detected = 1'b1;
// Check Thread level timeout
(`TOP.core_cycle_cnt - `TOP.th_last_act_cycle[mytnum]) > `PARGS.th_timeout)
// Note: Do not change this message because regreport parses it for certain words.
`PR_ALWAYS ("nas",`ALWAYS, "ERROR: Thread T%0d No Activity for %0d Cycles - Thread TIMEOUT!",
mytnum, `PARGS.th_timeout);
junk = incErr(9999); // must exceed users max error setting to force exit.
end // if (`PARGS.th_check_enable[mytnum] && nas_pipe_enable ...)}
// Need to make sure Store Buffer is empty before turning off th_check_enable.
//global chkr requires to wait for all outstanding pending I
if ((! `PARGS.nas_check_on) &&
(good_trap_detected==1'b1) &&
(`TOP.nas_top.lsu_stb_empty[mytnum]) && `TOP.nas_top.ireq_pending[mytnum]) begin // {
`PARGS.th_check_enable[mytnum] = 1'b0;
`TOP.finished_tids[mytnum] = 1'b1;
good_trap_detected = 1'b0;
`PR_NORMAL ("nas", `NORMAL, "T%0d reached Good Trap. Disabling checking for thread %0d", mytnum,mytnum);
//----------------------------------------------------------
//----------------------------------------------------------
// Stage FX4 of delta pipeline
delta_fx4[`NEXT_INDEX] <= `FIRST_INDEX;
delta_fx4[`TIME_INDEX] <= 0;
delta_fx4[`PC_INDEX] <= {16'b0,PC_reg};
delta_fx4[`GL_INDEX] <= GL_reg;
delta_fx4[`CWP_INDEX] <= CWP_reg;
delta_fx4[`OPCODE_INDEX] <= opcode;
delta_fx4[`FIRST_INDEX] <= 77'hx;
//----------------------------------------------------------
// Stage FX5 of delta pipeline
index = delta_fx4[`NEXT_INDEX];
// Pipeline previous stage
for (i=0; i<=delta_fx4[`NEXT_INDEX]; i=i+1) begin // {
delta_fx5[i] <= delta_fx4[i];
if (complete_fx4) begin // LSU | EXU | TLU
push_delta_fx5 (`CCR+`CTL_OFFSET,CCR_reg,index);
if (complete_fx4[`LSU_INDEX] |
complete_fx4[`EXU_INDEX]) begin
if (mytid <= 3) begin // {
for (i=0; i<=31; i=i+1) begin // {
push_delta_fx5 (i,`IRF7_EXU0[(remap(i,oddwin)+irf_offset)],index);
for (i=0; i<=31; i=i+1) begin // {
push_delta_fx5 (i,`IRF7_EXU1[(remap(i,oddwin)+irf_offset)],index);
// Update FRF7 - Loads use W2 Port.
if (complete_fx4[`LSU_INDEX]) begin // {
// IF W1 port is also being written, ignore that address
for (i=0; i<=31; i=i+1) begin // {
if (!((i == frf_w1_skip_addr) && frf_w1_valid_even)) begin // {
frf_tmp = `FRF7_EVEN[(mytid*32)+i];
push_delta_fx5 (`FP_OFFSET + (i*2), frf_tmp[31:0], index);
if (!((i == frf_w1_skip_addr) && frf_w1_valid_odd)) begin // {
frf_tmp = `FRF7_ODD[(mytid*32)+i];
push_delta_fx5 (`FP_OFFSET + (i*2)+1, frf_tmp[31:0], index);
// Update ASR/ASI registers
if (complete_fx4) begin // {
push_delta_fx5 (`PSTATE + `CTL_OFFSET,PSTATE_reg,index);
push_delta_fx5 (`HPSTATE + `CTL_OFFSET,HPSTATE_reg,index);
push_delta_fx5 (`PIL + `CTL_OFFSET,PIL_reg,index);
push_delta_fx5 (`TBA + `CTL_OFFSET,{TBA_reg,15'b0},index);
push_delta_fx5 (`GL + `CTL_OFFSET,GL_reg,index);
push_delta_fx5 (`HTBA + `CTL_OFFSET,{HTBA_reg,14'b0},index);
push_delta_fx5 (`VER + `CTL_OFFSET,VER_reg,index);
push_delta_fx5 (`Y + `CTL_OFFSET,Y_reg,index);
push_delta_fx5 (`ASI + `CTL_OFFSET,ASI_reg,index);
push_delta_fx5 (`STICK_CMPR + `CTL_OFFSET,STICK_CMPR_wire,index);
push_delta_fx5 (`HSTICK_CMPR + `CTL_OFFSET,HSTICK_CMPR_wire,index);
push_delta_fx5 (`TICK_CMPR + `CTL_OFFSET,TICK_CMPR_wire,index);
push_delta_fx5 (`CWP + `CTL_OFFSET,CWP_reg,index);
push_delta_fx5 (`CANSAVE + `CTL_OFFSET,CANSAVE_reg,index);
push_delta_fx5 (`CANRESTORE + `CTL_OFFSET,CANRESTORE_reg,index);
push_delta_fx5 (`CLEANWIN + `CTL_OFFSET,CLEANWIN_reg,index);
push_delta_fx5 (`OTHERWIN + `CTL_OFFSET,OTHERWIN_reg,index);
push_delta_fx5 (`WSTATE + `CTL_OFFSET,WSTATE_reg,index);
push_delta_fx5 (`CTXT_PRIM_0+`CTL_OFFSET,CTXT_PRIM_0_reg,index);
push_delta_fx5 (`CTXT_SEC_0+`CTL_OFFSET,CTXT_SEC_0_reg,index);
push_delta_fx5 (`CTXT_PRIM_1+`CTL_OFFSET,CTXT_PRIM_1_reg,index);
push_delta_fx5 (`CTXT_SEC_1+`CTL_OFFSET,CTXT_SEC_1_reg,index);
push_delta_fx5 (`LSU_CONTROL+`CTL_OFFSET,LSU_CONTROL_reg,index);
push_delta_fx5 (`WATCHPOINT_ADDR+`CTL_OFFSET,WATCHPOINT_ADDR_reg,index);
// NOTE - ADD_TSB_CFG will never be used for Axis or Tharas
push_delta_fx5 (`CTXT_Z_TSB_CFG0+`CTL_OFFSET,ctxt_z_tsb_cfg0_reg,index);
push_delta_fx5 (`CTXT_Z_TSB_CFG1+`CTL_OFFSET,ctxt_z_tsb_cfg1_reg,index);
push_delta_fx5 (`CTXT_Z_TSB_CFG2+`CTL_OFFSET,ctxt_z_tsb_cfg2_reg,index);
push_delta_fx5 (`CTXT_Z_TSB_CFG3+`CTL_OFFSET,ctxt_z_tsb_cfg3_reg,index);
push_delta_fx5 (`CTXT_NZ_TSB_CFG0+`CTL_OFFSET,ctxt_nz_tsb_cfg0_reg,index);
push_delta_fx5 (`CTXT_NZ_TSB_CFG1+`CTL_OFFSET,ctxt_nz_tsb_cfg1_reg,index);
push_delta_fx5 (`CTXT_NZ_TSB_CFG2+`CTL_OFFSET,ctxt_nz_tsb_cfg2_reg,index);
push_delta_fx5 (`CTXT_NZ_TSB_CFG3+`CTL_OFFSET,ctxt_nz_tsb_cfg3_reg,index);
// Update GSR for all except write ASR in progess
if (!asi_in_progress) begin // {
push_delta_fx5 (`GSR + `CTL_OFFSET,GSR_wire, index);
// If lsu_complete & fp_complete assert at same time,
// then the fp_complete is the one that will modify the FSR
if (complete_fx4[`LSU_INDEX] & !complete_fw1[`FP_INDEX]) begin
push_delta_fx5 (`FSR+`CTL_OFFSET,FSR_wire,index);
// Non Trap updates of Trap stack & level
if (complete_fx4 && !complete_fx4[`TLU_INDEX]) begin // {
push_delta_fx5 (`TL + `CTL_OFFSET,TL_reg,index);
push_delta_fx5 (`TPC1 + `CTL_OFFSET, TPC1_wire, index);
push_delta_fx5 (`TPC2 + `CTL_OFFSET, TPC2_wire, index);
push_delta_fx5 (`TPC3 + `CTL_OFFSET, TPC3_wire, index);
push_delta_fx5 (`TPC4 + `CTL_OFFSET, TPC4_wire, index);
push_delta_fx5 (`TPC5 + `CTL_OFFSET, TPC5_wire, index);
push_delta_fx5 (`TPC6 + `CTL_OFFSET, TPC6_wire, index);
push_delta_fx5 (`TNPC1 + `CTL_OFFSET, TNPC1_wire, index);
push_delta_fx5 (`TNPC2 + `CTL_OFFSET, TNPC2_wire, index);
push_delta_fx5 (`TNPC3 + `CTL_OFFSET, TNPC3_wire, index);
push_delta_fx5 (`TNPC4 + `CTL_OFFSET, TNPC4_wire, index);
push_delta_fx5 (`TNPC5 + `CTL_OFFSET, TNPC5_wire, index);
push_delta_fx5 (`TNPC6 + `CTL_OFFSET, TNPC6_wire, index);
push_delta_fx5 (`TSTATE1 + `CTL_OFFSET, TSTATE1_wire, index);
push_delta_fx5 (`TSTATE2 + `CTL_OFFSET, TSTATE2_wire, index);
push_delta_fx5 (`TSTATE3 + `CTL_OFFSET, TSTATE3_wire, index);
push_delta_fx5 (`TSTATE4 + `CTL_OFFSET, TSTATE4_wire, index);
push_delta_fx5 (`TSTATE5 + `CTL_OFFSET, TSTATE5_wire, index);
push_delta_fx5 (`TSTATE6 + `CTL_OFFSET, TSTATE6_wire, index);
push_delta_fx5 (`HTSTATE1 + `CTL_OFFSET, HTSTATE1_wire, index);
push_delta_fx5 (`HTSTATE2 + `CTL_OFFSET, HTSTATE2_wire, index);
push_delta_fx5 (`HTSTATE3 + `CTL_OFFSET, HTSTATE3_wire, index);
push_delta_fx5 (`HTSTATE4 + `CTL_OFFSET, HTSTATE4_wire, index);
push_delta_fx5 (`HTSTATE5 + `CTL_OFFSET, HTSTATE5_wire, index);
push_delta_fx5 (`HTSTATE6 + `CTL_OFFSET, HTSTATE6_wire, index);
push_delta_fx5 (`TT1 + `CTL_OFFSET, TT1_wire, index);
push_delta_fx5 (`TT2 + `CTL_OFFSET, TT2_wire, index);
push_delta_fx5 (`TT3 + `CTL_OFFSET, TT3_wire, index);
push_delta_fx5 (`TT4 + `CTL_OFFSET, TT4_wire, index);
push_delta_fx5 (`TT5 + `CTL_OFFSET, TT5_wire, index);
push_delta_fx5 (`TT6 + `CTL_OFFSET, TT6_wire, index);
//----------------------------------------------------------
// Stage FB of delta pipeline
index = delta_fx5[`NEXT_INDEX];
// Pipeline previous stage
for (i=0; i<=delta_fx5[`NEXT_INDEX]; i=i+1) begin // {
delta_fb[i] <= delta_fx5[i];
if (complete_fx5[`ASI_INDEX]) begin // {
push_delta_fb (`GSR + `CTL_OFFSET,GSR_wire, index);
//----------------------------------------------------------
// Stage FW of delta pipeline
index = delta_fb[`NEXT_INDEX];
// Pipeline previous stage
for (i=0; i<=delta_fb[`NEXT_INDEX]; i=i+1) begin // {
delta_fw[i] <= delta_fb[i];
// Capture CWP_reg for SAVE/RESTORE
delta_fw[`CWP_INDEX] <= CWP_reg;
if (complete_fb[`TLU_INDEX]) begin
if (mytid <= 3) begin // {
for (i=0; i<=31; i=i+1) begin // {
push_delta_fw (i,`IRF7_EXU0[(remap(i,oddwin)+irf_offset)],index);
for (i=0; i<=31; i=i+1) begin // {
push_delta_fw (i,`IRF7_EXU1[(remap(i,oddwin)+irf_offset)],index);
// Update FRF7 - Idivs use W2.
if (complete_fb[`IDIV_INDEX]) begin // {
// IF W1 port is also being written, ignore that address
for (i=0; i<=31; i=i+1) begin // {
if (!((i == frf_w1_skip_addr) && frf_w1_valid_even)) begin // {
frf_tmp = `FRF7_EVEN[(mytid*32)+i];
push_delta_fw (`FP_OFFSET + (i*2), frf_tmp[31:0], index);
if (!((i == frf_w1_skip_addr) && frf_w1_valid_odd)) begin // {
frf_tmp = `FRF7_ODD[(mytid*32)+i];
push_delta_fw (`FP_OFFSET + (i*2)+1,frf_tmp[31:0], index);
//----------------------------------------------------------
// Stage FW1 of delta pipeline
index = delta_fw[`NEXT_INDEX];
// Pipeline previous stage
for (i=0; i<=delta_fw[`NEXT_INDEX]; i=i+1) begin // {
delta_fw1[i] <= delta_fw[i];
// Update FRF7 - FPops use W1 port.
if (fp_complete) begin // {
// IF W2 port is also being written, ignore that address
for (i=0; i<=31; i=i+1) begin // {
if (!((i == frf_w2_skip_addr) && frf_w2_valid_even)) begin // {
frf_tmp = `FRF7_EVEN[(mytid*32)+i];
push_delta_fw1 (`FP_OFFSET + (i*2), frf_tmp[31:0], index);
if (!((i == frf_w2_skip_addr) && frf_w2_valid_odd)) begin // {
frf_tmp = `FRF7_ODD[(mytid*32)+i];
push_delta_fw1 (`FP_OFFSET + (i*2)+1,frf_tmp[31:0], index);
if (complete_fw[`IMUL_INDEX]|complete_fw[`IDIV_INDEX]) begin
push_delta_fw1 (`CCR+`CTL_OFFSET,CCR_reg,index);
push_delta_fw1 (`Y+`CTL_OFFSET,Y_reg,index);
push_delta_fw1 (`CWP+`CTL_OFFSET,CWP_reg,index);
push_delta_fw1 (`CANSAVE+`CTL_OFFSET,CANSAVE_reg,index);
push_delta_fw1 (`CANRESTORE+`CTL_OFFSET,CANRESTORE_reg,index);
push_delta_fw1 (`CLEANWIN+`CTL_OFFSET,CLEANWIN_reg,index);
push_delta_fw1 (`OTHERWIN+`CTL_OFFSET,OTHERWIN_reg,index);
push_delta_fw1 (`WSTATE+`CTL_OFFSET,WSTATE_reg,index);
if (complete_fw[`TLU_INDEX]) begin // {
push_delta_fw1 (`TL + `CTL_OFFSET,TL_reg,index);
push_delta_fw1 (`TPC1 + `CTL_OFFSET, TPC1_wire, index);
push_delta_fw1 (`TPC2 + `CTL_OFFSET, TPC2_wire, index);
push_delta_fw1 (`TPC3 + `CTL_OFFSET, TPC3_wire, index);
push_delta_fw1 (`TPC4 + `CTL_OFFSET, TPC4_wire, index);
push_delta_fw1 (`TPC5 + `CTL_OFFSET, TPC5_wire, index);
push_delta_fw1 (`TPC6 + `CTL_OFFSET, TPC6_wire, index);
push_delta_fw1 (`TNPC1 + `CTL_OFFSET, TNPC1_wire, index);
push_delta_fw1 (`TNPC2 + `CTL_OFFSET, TNPC2_wire, index);
push_delta_fw1 (`TNPC3 + `CTL_OFFSET, TNPC3_wire, index);
push_delta_fw1 (`TNPC4 + `CTL_OFFSET, TNPC4_wire, index);
push_delta_fw1 (`TNPC5 + `CTL_OFFSET, TNPC5_wire, index);
push_delta_fw1 (`TNPC6 + `CTL_OFFSET, TNPC6_wire, index);
push_delta_fw1 (`TSTATE1 + `CTL_OFFSET, TSTATE1_wire, index);
push_delta_fw1 (`TSTATE2 + `CTL_OFFSET, TSTATE2_wire, index);
push_delta_fw1 (`TSTATE3 + `CTL_OFFSET, TSTATE3_wire, index);
push_delta_fw1 (`TSTATE4 + `CTL_OFFSET, TSTATE4_wire, index);
push_delta_fw1 (`TSTATE5 + `CTL_OFFSET, TSTATE5_wire, index);
push_delta_fw1 (`TSTATE6 + `CTL_OFFSET, TSTATE6_wire, index);
push_delta_fw1 (`HTSTATE1 + `CTL_OFFSET, HTSTATE1_wire, index);
push_delta_fw1 (`HTSTATE2 + `CTL_OFFSET, HTSTATE2_wire, index);
push_delta_fw1 (`HTSTATE3 + `CTL_OFFSET, HTSTATE3_wire, index);
push_delta_fw1 (`HTSTATE4 + `CTL_OFFSET, HTSTATE4_wire, index);
push_delta_fw1 (`HTSTATE5 + `CTL_OFFSET, HTSTATE5_wire, index);
push_delta_fw1 (`HTSTATE6 + `CTL_OFFSET, HTSTATE6_wire, index);
push_delta_fw1 (`TT1 + `CTL_OFFSET, TT1_wire, index);
push_delta_fw1 (`TT2 + `CTL_OFFSET, TT2_wire, index);
push_delta_fw1 (`TT3 + `CTL_OFFSET, TT3_wire, index);
push_delta_fw1 (`TT4 + `CTL_OFFSET, TT4_wire, index);
push_delta_fw1 (`TT5 + `CTL_OFFSET, TT5_wire, index);
push_delta_fw1 (`TT6 + `CTL_OFFSET, TT6_wire, index);
//----------------------------------------------------------
// Stage FW2 of delta pipeline
index = delta_fw1[`NEXT_INDEX];
// Pipeline previous stage
for (i=0; i<=delta_fw1[`NEXT_INDEX]; i=i+1) begin // {
delta_fw2[i] <= delta_fw1[i];
delta_fw2[`TIME_INDEX] <= $time;
// Update Registers that may change asynchronously
// If sstep was already sent by another module,
// don't capture until the next sstep
if (complete_fw1 && !`NASTOP.sstep_early[mytnum]) begin // {
if ((complete_fw1[`ASI_INDEX]|complete_fw1[`LSU_INDEX]) & asi_rdwr_hintp)
push_delta_fw2 (`HINTP + `CTL_OFFSET,asi_updated_hintp,index);
push_delta_fw2 (`HINTP + `CTL_OFFSET,HINTP_reg,index);
if ((complete_fw1[`ASI_INDEX]|complete_fw1[`LSU_INDEX]) & asi_rdwr_softint)
push_delta_fw2 (`SOFTINT + `CTL_OFFSET,asi_updated_softint,index);
push_delta_fw2 (`SOFTINT + `CTL_OFFSET,rd_SOFTINT_reg,index);
if (complete_fw1[`IMUL_INDEX] |
complete_fw1[`IDIV_INDEX]) begin // {
if (mytid <= 3) begin // {
for (i=0; i<=31; i=i+1) begin // {
push_delta_fw2 (i,`IRF7_EXU0[(remap(i,oddwin)+irf_offset)],index);
for (i=0; i<=31; i=i+1) begin // {
push_delta_fw2 (i,`IRF7_EXU1[(remap(i,oddwin)+irf_offset)],index);
// Update FRF7 - fdivs and Imuls use W2 port
if (complete_fw1[`IMUL_INDEX] |
complete_fw1[`FDIV_INDEX] ) begin // {
// IF W1 port is also being written, ignore that address
for (i=0; i<=31; i=i+1) begin // {
if (!((i == frf_w1_skip_addr) && frf_w1_valid_even)) begin // {
frf_tmp = `FRF7_EVEN[(mytid*32)+i];
push_delta_fw2 (`FP_OFFSET + (i*2), frf_tmp[31:0], index);
if (!((i == frf_w1_skip_addr) && frf_w1_valid_odd)) begin // {
frf_tmp = `FRF7_ODD[(mytid*32)+i];
push_delta_fw2 (`FP_OFFSET + (i*2)+1,frf_tmp[31:0], index);
if (complete_fw1[`FP_INDEX] |
complete_fw1[`TLU_INDEX] |
complete_fw1[`FDIV_INDEX]) begin
push_delta_fw2 (`FSR+`CTL_OFFSET,FSR_wire,index);
push_delta_fw2 (`I_TAG_ACC+`CTL_OFFSET,itagacc_fw2,index);
push_delta_fw2 (`D_TAG_ACC+`CTL_OFFSET,dtagacc_fw2,index);
push_delta_fw2 (`DSFAR+`CTL_OFFSET,dsfar_fw2,index);
//----------------------------------------------------------
// Stage FW2 of delta pipeline - for signals that change FW+2 !!
index = delta_fw2[`NEXT_INDEX];
// Since FPRS for FPops may have been corrupted by o-o-o loads:
// If fprs_fw2 is != fprs_reg & there are loads in the pipeline
// then assume loads have already updated fprs.
// In that case, create our own fprs_reg by using the valids and
// skip_addr and copy of fprs for this op..
if (complete_fw2[`FP_INDEX] && frf_w1_valid_fw2) begin // {
// o-o-o load has changed fprs already - use dummy
if ((fprs_fw2 != FPRS_reg) && (complete_fw1[`LSU_INDEX] |
complete_fw[`LSU_INDEX] | complete_fb[`LSU_INDEX] |
complete_fx5[`LSU_INDEX] )) begin // {
dummy_fprs = read_prev(`FPRS + `CTL_OFFSET);
dummy_fprs = dummy_fprs |
{1'b0, frf_w1_skip_addr4_fw2, ~frf_w1_skip_addr4_fw2};
push_delta_fw2_async (`FPRS + `CTL_OFFSET,dummy_fprs,index);
// o-o-o load has NOT changed fprs already - use it
push_delta_fw2_async (`FPRS + `CTL_OFFSET,FPRS_reg,index);
// Load FPRS for loads/reads as prev|fprs_fb ..
// since loads may only 'set' bits, not clear ...
else if (complete_fw2[`LSU_INDEX]) begin // {
dummy_fprs = read_prev(`FPRS + `CTL_OFFSET);
dummy_fprs = dummy_fprs | fprs_fw1;
push_delta_fw2_async (`FPRS +`CTL_OFFSET,dummy_fprs,index);
// Load FPRS for store ASI or FDIV
// FDIV can update FPRS on w1 or w2,
// but the pipe is stalled behind it so no o-o-o loads.
else if ((complete_fw2[`ASI_INDEX]) ||
(complete_fw2[`FDIV_INDEX])) begin // {
push_delta_fw2_async (`FPRS + `CTL_OFFSET,FPRS_reg,index);
//----------------------------------------------------------
// Store latest values into delta
index = delta_prev[`NEXT_INDEX];
if (in_wmr & ~`SPC7.rst_wmr_protect) begin // {
push_delta_prev_async ( `PC+`CTL_OFFSET,{16'b0,pc_fw2|1},index);
push_delta_prev_async ( `PC+`CTL_OFFSET,{16'b0,pc_fw2},index);
//----------------------------------------------------------
//----------------------------------------------------------
// Compare with current state and capture if different
if (act_value != read_prev(id)) begin // { // Diff vs prev
calc_cwp(CWP_reg,id,win,type); // special case for 1st stage
write_prev(id,act_value);
delta_fx4[next] <= {type,win,id,act_value};
delta_fx4[next] <= 77'hx;
delta_fx4[`NEXT_INDEX] <= next;
if (`PARGS.axis_debug_on) begin
$display("AXIS: T%0d pc=%h id=%0d type=%0h win=%0h value=%h ts=%0d",
mytnum,PC_reg,id,type,win,act_value,$time);
if (`PARGS.axis_debug_on) begin
$display("AXIS: T%0d pc=%h id=%0d type=%0h win=%0h value=%h ts=%0d",
mytnum,PC_reg,id,type,win,act_value,$time);
//----------------------------------------------------------
// Compare with current state and capture if different
if (act_value != read_prev(id)) begin // { // Diff vs prev
calc_cwp(delta_fx4[`CWP_INDEX],id,win,type);
write_prev(id,act_value);
delta_fx5[next] <= {type,win,id,act_value};
delta_fx5[next] <= 77'hx;
delta_fx5[`NEXT_INDEX] <= next;
if (`PARGS.axis_debug_on) begin
$display("AXIS: T%0d pc=%h id=%0d type=%0h win=%0h value=%h ts=%0d",
mytnum,pc_fx4,id,type,win,act_value,$time);
calc_cwp(cwp_fx4,id,win,type);
if (`PARGS.axis_debug_on) begin
$display("AXIS: T%0d pc=%h id=%0d type=%0h win=%0h value=%h ts=%0d",
mytnum,pc_fx4,id,type,win,act_value,$time);
//----------------------------------------------------------
// Compare with current state and capture if different
if (act_value != read_prev(id)) begin // { // Diff vs prev
calc_cwp(delta_fx5[`CWP_INDEX],id,win,type);
write_prev(id,act_value);
delta_fb[next] <= {type,win,id,act_value};
delta_fb[`NEXT_INDEX] <= next;
if (`PARGS.axis_debug_on) begin
$display("AXIS: T%0d pc=%h id=%0d type=%0h win=%0h value=%h ts=%0d",
mytnum,pc_fx5,id,type,win,act_value,$time);
calc_cwp(cwp_fx5,id,win,type);
if (`PARGS.axis_debug_on) begin
$display("AXIS: T%0d pc=%h id=%0d type=%0h win=%0h value=%h ts=%0d",
mytnum,pc_fx5,id,type,win,act_value,$time);
//----------------------------------------------------------
// Compare with current state and capture if different
if (act_value != read_prev(id)) begin // { // Diff vs prev
calc_cwp(delta_fb[`CWP_INDEX],id,win,type);
write_prev(id,act_value);
delta_fw[next] <= {type,win,id,act_value};
delta_fw[`NEXT_INDEX] <= next;
if (`PARGS.axis_debug_on) begin
$display("AXIS: T%0d pc=%h id=%0d type=%0h win=%0h value=%h ts=%0d",
mytnum,pc_fb,id,type,win,act_value,$time);
calc_cwp(cwp_fb[`CWP_INDEX],id,win,type);
if (`PARGS.axis_debug_on) begin
$display("AXIS: T%0d pc=%h id=%0d type=%0h win=%0h value=%h ts=%0d",
mytnum,pc_fb,id,type,win,act_value,$time);
//----------------------------------------------------------
// Compare with current state and capture if different
if (act_value != read_prev(id)) begin // { // Diff vs prev
calc_cwp(delta_fw[`CWP_INDEX],id,win,type);
write_prev(id,act_value);
delta_fw1[next] <= {type,win,id,act_value};
delta_fw1[next] <= 77'hx;
delta_fw1[`NEXT_INDEX] <= next;
if (`PARGS.axis_debug_on) begin
$display("AXIS: T%0d pc=%h id=%0d type=%0h win=%0h value=%h ts=%0d",
mytnum,pc_fw,id,type,win,act_value,$time);
calc_cwp(cwp_fw,id,win,type);
if (`PARGS.axis_debug_on) begin
$display("AXIS: T%0d pc=%h id=%0d type=%0h win=%0h value=%h ts=%0d",
mytnum,pc_fw,id,type,win,act_value,$time);
//----------------------------------------------------------
// Compare with current state and capture if different
if (act_value != read_prev(id)) begin // { // Diff vs prev
calc_cwp(delta_fw1[`CWP_INDEX],id,win,type);
write_prev(id,act_value);
delta_fw2[next] <= {type,win,id,act_value};
delta_fw2[next] <= 77'hx;
delta_fw2[`NEXT_INDEX] <= next;
if (`PARGS.axis_debug_on) begin
$display("AXIS: T%0d pc=%h id=%0d type=%0h win=%0h value=%h ts=%0d",
mytnum,pc_fw1,id,type,win,act_value,$time);
calc_cwp(cwp_fw1,id,win,type);
if (`PARGS.axis_debug_on) begin
$display("AXIS: T%0d pc=%h id=%0d type=%0h win=%0h value=%h ts=%0d",
mytnum,pc_fw1,id,type,win,act_value,$time);
//----------------------------------------------------------
// Compare with current state and capture if different
// This is for late changing registers
// Use blocking assignments.
task push_delta_fw2_async;
if (act_value != read_prev(id)) begin // { // Diff vs prev
calc_cwp(delta_fw2[`CWP_INDEX],id,win,type);
write_prev_async(id,act_value);
delta_fw2[next] = {type,win,id,act_value};
delta_fw2[`NEXT_INDEX] = next;
if (`PARGS.axis_debug_on) begin
$display("AXIS: T%0d pc=%h id=%0d type=%0h win=%0h value=%h ts=%0d",
mytnum,pc_fw1,id,type,win,act_value,$time);
calc_cwp(cwp_fw2,id,win,type);
if (`PARGS.axis_debug_on) begin
$display("AXIS: T%0d pc=%h id=%0d type=%0h win=%0h value=%h ts=%0d",
mytnum,pc_fw1,id,type,win,act_value,$time);
//----------------------------------------------------------
// Compare with current state and capture if different
// Use blocking assignments so that push_simics will work
task push_delta_prev_async;
if (act_value != read_prev(id)) begin // { // Diff vs prev
calc_cwp(delta_prev[`CWP_INDEX],id,win,type);
write_prev_async(id,act_value);
delta_prev[next] = {type,win,id,act_value};
delta_prev[next] = 77'hx;
delta_prev[`NEXT_INDEX] = next;
if (`PARGS.axis_debug_on) begin
$display("AXIS: T%0d pc=%h id=%0d type=%0h win=%0h value=%h ts=%0d",
mytnum,pc_last,id,type,win,act_value,$time);
if (`PARGS.axis_debug_on) begin
calc_cwp(cwp_last,id,win,type);
$display("AXIS: T%0d pc=%h id=%0d type=%0h win=%0h value=%h ts=%0d",
mytnum,pc_last,id,type,win,act_value,$time);
//----------------------------------------------------------
// prev of delta pipeline
// Pipeline previous stage
for (i=0; i<=delta_fw2[`NEXT_INDEX]; i=i+1) begin // {
delta_prev[i] <= delta_fw2[i];
//----------------------------------------------------------
//----------------------------------------------------------
// Sort delta list in register ID order, then push to simics
// Or print deltas if sas check disabled ..
// Order of registers reported to simics must be:
// Global 0-7 aka prev_reg[0:7]
// Window 8-23 aka prev_reg[8:23]
// Floating 0-63 aka prev_reg[200:263]
// Control 32-143 aka prev_reg[32:143]
act_level = delta_prev[`GL_INDEX]; // GL
time_fw2 = delta_prev[`TIME_INDEX]; // Finish time
for (i=`FIRST_INDEX; i<delta_prev[`NEXT_INDEX]; i=i+1) begin // {
{type,win,regnum,value} = delta_prev[i];
if (regnum<=7) begin // {
if (`PARGS.nas_check_on) begin // {
`ACT_STATUS = $queue(`ACT_QUEUE, `PUSH_Q, mytnum, time_fw2, act_type,
act_level, regnum, value);
else if (`PARGS.show_delta_on) begin // {
`NASTOP.print_delta (mytnum,act_type,win,regnum,value);
else if (regnum<=23) begin // { %o0-%l7, %l0-%l7
if (`PARGS.nas_check_on) begin // {
`ACT_STATUS = $queue(`ACT_QUEUE, `PUSH_Q, mytnum, time_fw2, act_type,
else if (`PARGS.show_delta_on) begin // {
`NASTOP.print_delta (mytnum,act_type,win,regnum,value);
else if (regnum<=31) begin // { %i0-%i7
if (`PARGS.nas_check_on) begin // {
`ACT_STATUS = $queue(`ACT_QUEUE, `PUSH_Q, mytnum, time_fw2, act_type,
win, (regnum-16), value);
else if (`PARGS.show_delta_on) begin // {
`NASTOP.print_delta (mytnum,act_type,win,(regnum-16),value);
else if (regnum<=(64+`FP_OFFSET)) begin // {
if (`PARGS.nas_check_on) begin // {
`ACT_STATUS = $queue(`ACT_QUEUE, `PUSH_Q, mytnum, time_fw2, act_type,
(regnum-`FP_OFFSET), value);
else if (`PARGS.show_delta_on) begin // {
`NASTOP.print_delta (mytnum,act_type,win,(regnum-`FP_OFFSET),value);
else if ((regnum>=(32+`CTL_OFFSET))&(regnum<=(143+`CTL_OFFSET))) begin // {
if (`PARGS.nas_check_on) begin // {
`ACT_STATUS = $queue(`ACT_QUEUE, `PUSH_Q, mytnum, time_fw2, act_type,
(regnum-`CTL_OFFSET), value);
else if (`PARGS.show_delta_on) begin // {
`NASTOP.print_delta (mytnum,act_type,win,(regnum-`CTL_OFFSET),value);
`PR_ERROR ("nas", `ERROR, " - T%0d Bench problem. push_simics has bad regnum", mytnum);
value = delta_prev[`OPCODE_INDEX];
if (`PARGS.nas_check_on) begin // {
`ACT_STATUS = $queue(`ACT_QUEUE, `PUSH_Q, mytnum, time_fw2, act_type,
else if (`PARGS.show_delta_on) begin // {
`NASTOP.print_delta (mytnum,act_type,win,regnum,value);
// Push End of Instruction Delimiter
// The value field for this PUSH equals the PC for this instruction.
// so that printing to the logfile works correctly.
// prev_reg[`PC] = current instruction PC
// delta_reg[`PC] = PC at end of current instruction
pc = delta_prev[`PC_INDEX];
if (`PARGS.nas_check_on) begin // {
`ACT_STATUS = $queue(`ACT_QUEUE, `PUSH_Q, mytnum, time_fw2, act_type,
delta_fw2[`CWP_INDEX], `END_INSTR, pc);
else if (`PARGS.show_delta_on) begin // {
`NASTOP.print_delta (mytnum,act_type,delta_fw2[`CWP_INDEX],`END_INSTR,0);
if (! `PARGS.nas_check_on) begin // {
`PR_NORMAL ("nas", `NORMAL, "@%0d T%0d %h (Unchecked..)",
$time, mytnum, {16'b0,pc});
`TOP.last_act_cycle = `TOP.core_cycle_cnt; //$time;
`TOP.th_last_act_cycle[mytnum] = `TOP.last_act_cycle;
if (! `PARGS.nas_check_on) begin // {
`TOP.last_act_cycle = `TOP.core_cycle_cnt; //$time;
`TOP.th_last_act_cycle[mytnum] = `TOP.last_act_cycle;
//----------------------------------------------------------
// Save current window to previous window, then copy new window to current window
// Save current window to Old window
// Copy New window to current window
//----------------------------------------------------------
// Save current global to previous global, then copy new global to current global
// Save current global to Old global
// Copy New global current global
//----------------------------------------------------------
// Return window number and register type based on cwp and regnum as input
else if (id<=23) begin // {
else if (id<=31) begin // {
else if (id<=(64+`FP_OFFSET)) begin // {
//----------------------------------------------------------
// Check for bad signal values
8'b10000000: ; // good value
`PR_ERROR ("nas", `ERROR, " - T%0d More than one instruction retired in a single cycle for this thread.",
$write("\t\t\t\t Instructions - ");
if (complete_fw2[`EXU_INDEX]) $write("EXU op, ");
if (complete_fw2[`FP_INDEX]) $write("FP op, ");
if (complete_fw2[`LSU_INDEX]) $write("LSU op, ");
if (complete_fw2[`IMUL_INDEX]) $write("IMUL op, ");
if (complete_fw2[`IDIV_INDEX]) $write("IDIV op, ");
if (complete_fw2[`FDIV_INDEX]) $write("FDIV op, ");
if (complete_fw2[`TLU_INDEX]) $write("TLU op, ");
if (complete_fw2[`ASI_INDEX]) $write("ASI op, ");
$write(" complete_fw2 = %b \n",complete_fw2);
// This check only works if diags are written properly.
// For example, if a diag writes to one of these registers using wrpr,
// then this check must be disabled using plusarg.
// CANSAVE + CANRESTORE + OTHERWIN = NWINDOWS-2 (per Sparc V9)
if (`PARGS.win_check_on) begin // {
if (complete_fw2 & ((CANSAVE_reg + CANRESTORE_reg + OTHERWIN_reg) != 6)) begin // {
`PR_ERROR ("nas", `ERROR, "ERROR - T%0d Bad Values for window registers.", mytnum);
`PR_ERROR ("nas", `ERROR, "- CANSAVE = %0d CANRESTORE = %0d OTHERWIN = %0d",
CANSAVE_reg, CANRESTORE_reg,OTHERWIN_reg);
//----------------------------------------------------------
//----------------------------------------------------------
reg [`DELTA_WIDTH:0] temp1, temp2;
last = delta_prev[`NEXT_INDEX]-1;
for (i=`FIRST_INDEX; i <= last; i=i+1) begin // {
for (j=`FIRST_INDEX; j < last; j=j+1) begin // {
temp1 = delta_prev[j]; temp2 = delta_prev[j+1];
if (temp1[76:64] > temp2[76:64]) begin // {
delta_prev[j] = temp2; delta_prev [j+1] = temp1;
//----------------------------------------------------------
//----------------------------------------------------------
// Print one entry in delta_* array
input [`DELTA_WIDTH:0] delta_entry;
reg [(20*8)-1:0] type_str;
reg [(20*8)-1:0] regname;
{type,win,id,act_value} = delta_entry;
`NASTOP.get_regname(mytnum,type_str,win,id,regname);
`PR_NORMAL ("nas", `NORMAL, "type=%0s win=%0d RegID=%0d %0s=%h",
type_str,win,id,regname,act_value);
//----------------------------------------------------------
// Write Value to prev_reg using id as index (non-blocking)
8'd0: prev_reg0 <= value;
8'd1: prev_reg1 <= value;
8'd2: prev_reg2 <= value;
8'd3: prev_reg3 <= value;
8'd4: prev_reg4 <= value;
8'd5: prev_reg5 <= value;
8'd6: prev_reg6 <= value;
8'd7: prev_reg7 <= value;
8'd8: prev_reg8 <= value;
8'd9: prev_reg9 <= value;
8'd10: prev_reg10 <= value;
8'd11: prev_reg11 <= value;
8'd12: prev_reg12 <= value;
8'd13: prev_reg13 <= value;
8'd14: prev_reg14 <= value;
8'd15: prev_reg15 <= value;
8'd16: prev_reg16 <= value;
8'd17: prev_reg17 <= value;
8'd18: prev_reg18 <= value;
8'd19: prev_reg19 <= value;
8'd20: prev_reg20 <= value;
8'd21: prev_reg21 <= value;
8'd22: prev_reg22 <= value;
8'd23: prev_reg23 <= value;
8'd24: prev_reg24 <= value;
8'd25: prev_reg25 <= value;
8'd26: prev_reg26 <= value;
8'd27: prev_reg27 <= value;
8'd28: prev_reg28 <= value;
8'd29: prev_reg29 <= value;
8'd30: prev_reg30 <= value;
8'd31: prev_reg31 <= value;
8'd32: prev_reg32 <= value;
8'd33: prev_reg33 <= value;
8'd34: prev_reg34 <= value;
8'd35: prev_reg35 <= value;
8'd36: prev_reg36 <= value;
8'd37: prev_reg37 <= value;
8'd38: prev_reg38 <= value;
8'd39: prev_reg39 <= value;
8'd40: prev_reg40 <= value;
8'd41: prev_reg41 <= value;
8'd42: prev_reg42 <= value;
8'd43: prev_reg43 <= value;
8'd44: prev_reg44 <= value;
8'd45: prev_reg45 <= value;
8'd46: prev_reg46 <= value;
8'd47: prev_reg47 <= value;
8'd48: prev_reg48 <= value;
8'd49: prev_reg49 <= value;
8'd50: prev_reg50 <= value;
8'd51: prev_reg51 <= value;
8'd52: prev_reg52 <= value;
8'd53: prev_reg53 <= value;
8'd54: prev_reg54 <= value;
8'd55: prev_reg55 <= value;
8'd56: prev_reg56 <= value;
8'd57: prev_reg57 <= value;
8'd58: prev_reg58 <= value;
8'd59: prev_reg59 <= value;
8'd60: prev_reg60 <= value;
8'd61: prev_reg61 <= value;
8'd62: prev_reg62 <= value;
8'd63: prev_reg63 <= value;
8'd64: prev_reg64 <= value;
8'd65: prev_reg65 <= value;
8'd66: prev_reg66 <= value;
8'd67: prev_reg67 <= value;
8'd68: prev_reg68 <= value;
8'd69: prev_reg69 <= value;
8'd70: prev_reg70 <= value;
8'd71: prev_reg71 <= value;
8'd72: prev_reg72 <= value;
8'd73: prev_reg73 <= value;
8'd74: prev_reg74 <= value;
8'd75: prev_reg75 <= value;
8'd76: prev_reg76 <= value;
8'd77: prev_reg77 <= value;
8'd78: prev_reg78 <= value;
8'd79: prev_reg79 <= value;
8'd80: prev_reg80 <= value;
8'd81: prev_reg81 <= value;
8'd82: prev_reg82 <= value;
8'd83: prev_reg83 <= value;
8'd84: prev_reg84 <= value;
8'd85: prev_reg85 <= value;
8'd86: prev_reg86 <= value;
8'd87: prev_reg87 <= value;
8'd88: prev_reg88 <= value;
8'd89: prev_reg89 <= value;
8'd90: prev_reg90 <= value;
8'd91: prev_reg91 <= value;
8'd92: prev_reg92 <= value;
8'd93: prev_reg93 <= value;
8'd94: prev_reg94 <= value;
8'd95: prev_reg95 <= value;
8'd96: prev_reg96 <= value;
8'd97: prev_reg97 <= value;
8'd98: prev_reg98 <= value;
8'd99: prev_reg99 <= value;
8'd100: prev_reg100 <= value;
8'd101: prev_reg101 <= value;
8'd102: prev_reg102 <= value;
8'd103: prev_reg103 <= value;
8'd104: prev_reg104 <= value;
8'd105: prev_reg105 <= value;
8'd106: prev_reg106 <= value;
8'd107: prev_reg107 <= value;
8'd108: prev_reg108 <= value;
8'd109: prev_reg109 <= value;
8'd110: prev_reg110 <= value;
8'd111: prev_reg111 <= value;
8'd112: prev_reg112 <= value;
8'd113: prev_reg113 <= value;
8'd114: prev_reg114 <= value;
8'd115: prev_reg115 <= value;
8'd116: prev_reg116 <= value;
8'd117: prev_reg117 <= value;
8'd118: prev_reg118 <= value;
8'd119: prev_reg119 <= value;
8'd120: prev_reg120 <= value;
8'd121: prev_reg121 <= value;
8'd122: prev_reg122 <= value;
8'd123: prev_reg123 <= value;
8'd124: prev_reg124 <= value;
8'd125: prev_reg125 <= value;
8'd126: prev_reg126 <= value;
8'd127: prev_reg127 <= value;
8'd128: prev_reg128 <= value;
8'd129: prev_reg129 <= value;
8'd130: prev_reg130 <= value;
8'd131: prev_reg131 <= value;
8'd132: prev_reg132 <= value;
8'd133: prev_reg133 <= value;
8'd134: prev_reg134 <= value;
8'd135: prev_reg135 <= value;
8'd136: prev_reg136 <= value;
8'd137: prev_reg137 <= value;
8'd138: prev_reg138 <= value;
8'd139: prev_reg139 <= value;
8'd140: prev_reg140 <= value;
8'd141: prev_reg141 <= value;
8'd142: prev_reg142 <= value;
8'd143: prev_reg143 <= value;
8'd144: prev_reg144 <= value;
8'd145: prev_reg145 <= value;
8'd146: prev_reg146 <= value;
8'd147: prev_reg147 <= value;
8'd148: prev_reg148 <= value;
8'd149: prev_reg149 <= value;
8'd150: prev_reg150 <= value;
8'd151: prev_reg151 <= value;
8'd152: prev_reg152 <= value;
8'd153: prev_reg153 <= value;
8'd154: prev_reg154 <= value;
8'd155: prev_reg155 <= value;
8'd156: prev_reg156 <= value;
8'd157: prev_reg157 <= value;
8'd158: prev_reg158 <= value;
8'd159: prev_reg159 <= value;
8'd160: prev_reg160 <= value;
8'd161: prev_reg161 <= value;
8'd162: prev_reg162 <= value;
8'd163: prev_reg163 <= value;
8'd164: prev_reg164 <= value;
8'd165: prev_reg165 <= value;
8'd166: prev_reg166 <= value;
8'd167: prev_reg167 <= value;
8'd168: prev_reg168 <= value;
8'd169: prev_reg169 <= value;
8'd170: prev_reg170 <= value;
8'd171: prev_reg171 <= value;
8'd172: prev_reg172 <= value;
8'd173: prev_reg173 <= value;
8'd174: prev_reg174 <= value;
8'd175: prev_reg175 <= value;
8'd176: prev_reg176 <= value;
8'd177: prev_reg177 <= value;
8'd178: prev_reg178 <= value;
8'd179: prev_reg179 <= value;
8'd180: prev_reg180 <= value;
8'd181: prev_reg181 <= value;
8'd182: prev_reg182 <= value;
8'd183: prev_reg183 <= value;
8'd184: prev_reg184 <= value;
8'd185: prev_reg185 <= value;
8'd186: prev_reg186 <= value;
8'd187: prev_reg187 <= value;
8'd188: prev_reg188 <= value;
8'd189: prev_reg189 <= value;
8'd190: prev_reg190 <= value;
8'd191: prev_reg191 <= value;
8'd192: prev_reg192 <= value;
8'd193: prev_reg193 <= value;
8'd194: prev_reg194 <= value;
8'd195: prev_reg195 <= value;
8'd196: prev_reg196 <= value;
8'd197: prev_reg197 <= value;
8'd198: prev_reg198 <= value;
8'd199: prev_reg199 <= value;
8'd200: prev_reg200 <= value;
8'd201: prev_reg201 <= value;
8'd202: prev_reg202 <= value;
8'd203: prev_reg203 <= value;
8'd204: prev_reg204 <= value;
8'd205: prev_reg205 <= value;
8'd206: prev_reg206 <= value;
8'd207: prev_reg207 <= value;
8'd208: prev_reg208 <= value;
8'd209: prev_reg209 <= value;
8'd210: prev_reg210 <= value;
8'd211: prev_reg211 <= value;
8'd212: prev_reg212 <= value;
8'd213: prev_reg213 <= value;
8'd214: prev_reg214 <= value;
8'd215: prev_reg215 <= value;
8'd216: prev_reg216 <= value;
8'd217: prev_reg217 <= value;
8'd218: prev_reg218 <= value;
8'd219: prev_reg219 <= value;
8'd220: prev_reg220 <= value;
8'd221: prev_reg221 <= value;
8'd222: prev_reg222 <= value;
8'd223: prev_reg223 <= value;
8'd224: prev_reg224 <= value;
8'd225: prev_reg225 <= value;
8'd226: prev_reg226 <= value;
8'd227: prev_reg227 <= value;
8'd228: prev_reg228 <= value;
8'd229: prev_reg229 <= value;
8'd230: prev_reg230 <= value;
8'd231: prev_reg231 <= value;
8'd232: prev_reg232 <= value;
8'd233: prev_reg233 <= value;
8'd234: prev_reg234 <= value;
8'd235: prev_reg235 <= value;
8'd236: prev_reg236 <= value;
8'd237: prev_reg237 <= value;
8'd238: prev_reg238 <= value;
8'd239: prev_reg239 <= value;
8'd240: prev_reg240 <= value;
8'd241: prev_reg241 <= value;
8'd242: prev_reg242 <= value;
8'd243: prev_reg243 <= value;
8'd244: prev_reg244 <= value;
8'd245: prev_reg245 <= value;
8'd246: prev_reg246 <= value;
8'd247: prev_reg247 <= value;
8'd248: prev_reg248 <= value;
8'd249: prev_reg249 <= value;
8'd250: prev_reg250 <= value;
8'd251: prev_reg251 <= value;
8'd252: prev_reg252 <= value;
8'd253: prev_reg253 <= value;
8'd254: prev_reg254 <= value;
8'd255: prev_reg255 <= value;
//----------------------------------------------------------
// Write Value to prev_reg using id as index (blocking)
8'd10: prev_reg10 = value;
8'd11: prev_reg11 = value;
8'd12: prev_reg12 = value;
8'd13: prev_reg13 = value;
8'd14: prev_reg14 = value;
8'd15: prev_reg15 = value;
8'd16: prev_reg16 = value;
8'd17: prev_reg17 = value;
8'd18: prev_reg18 = value;
8'd19: prev_reg19 = value;
8'd20: prev_reg20 = value;
8'd21: prev_reg21 = value;
8'd22: prev_reg22 = value;
8'd23: prev_reg23 = value;
8'd24: prev_reg24 = value;
8'd25: prev_reg25 = value;
8'd26: prev_reg26 = value;
8'd27: prev_reg27 = value;
8'd28: prev_reg28 = value;
8'd29: prev_reg29 = value;
8'd30: prev_reg30 = value;
8'd31: prev_reg31 = value;
8'd32: prev_reg32 = value;
8'd33: prev_reg33 = value;
8'd34: prev_reg34 = value;
8'd35: prev_reg35 = value;
8'd36: prev_reg36 = value;
8'd37: prev_reg37 = value;
8'd38: prev_reg38 = value;
8'd39: prev_reg39 = value;
8'd40: prev_reg40 = value;
8'd41: prev_reg41 = value;
8'd42: prev_reg42 = value;
8'd43: prev_reg43 = value;
8'd44: prev_reg44 = value;
8'd45: prev_reg45 = value;
8'd46: prev_reg46 = value;
8'd47: prev_reg47 = value;
8'd48: prev_reg48 = value;
8'd49: prev_reg49 = value;
8'd50: prev_reg50 = value;
8'd51: prev_reg51 = value;
8'd52: prev_reg52 = value;
8'd53: prev_reg53 = value;
8'd54: prev_reg54 = value;
8'd55: prev_reg55 = value;
8'd56: prev_reg56 = value;
8'd57: prev_reg57 = value;
8'd58: prev_reg58 = value;
8'd59: prev_reg59 = value;
8'd60: prev_reg60 = value;
8'd61: prev_reg61 = value;
8'd62: prev_reg62 = value;
8'd63: prev_reg63 = value;
8'd64: prev_reg64 = value;
8'd65: prev_reg65 = value;
8'd66: prev_reg66 = value;
8'd67: prev_reg67 = value;
8'd68: prev_reg68 = value;
8'd69: prev_reg69 = value;
8'd70: prev_reg70 = value;
8'd71: prev_reg71 = value;
8'd72: prev_reg72 = value;
8'd73: prev_reg73 = value;
8'd74: prev_reg74 = value;
8'd75: prev_reg75 = value;
8'd76: prev_reg76 = value;
8'd77: prev_reg77 = value;
8'd78: prev_reg78 = value;
8'd79: prev_reg79 = value;
8'd80: prev_reg80 = value;
8'd81: prev_reg81 = value;
8'd82: prev_reg82 = value;
8'd83: prev_reg83 = value;
8'd84: prev_reg84 = value;
8'd85: prev_reg85 = value;
8'd86: prev_reg86 = value;
8'd87: prev_reg87 = value;
8'd88: prev_reg88 = value;
8'd89: prev_reg89 = value;
8'd90: prev_reg90 = value;
8'd91: prev_reg91 = value;
8'd92: prev_reg92 = value;
8'd93: prev_reg93 = value;
8'd94: prev_reg94 = value;
8'd95: prev_reg95 = value;
8'd96: prev_reg96 = value;
8'd97: prev_reg97 = value;
8'd98: prev_reg98 = value;
8'd99: prev_reg99 = value;
8'd100: prev_reg100 = value;
8'd101: prev_reg101 = value;
8'd102: prev_reg102 = value;
8'd103: prev_reg103 = value;
8'd104: prev_reg104 = value;
8'd105: prev_reg105 = value;
8'd106: prev_reg106 = value;
8'd107: prev_reg107 = value;
8'd108: prev_reg108 = value;
8'd109: prev_reg109 = value;
8'd110: prev_reg110 = value;
8'd111: prev_reg111 = value;
8'd112: prev_reg112 = value;
8'd113: prev_reg113 = value;
8'd114: prev_reg114 = value;
8'd115: prev_reg115 = value;
8'd116: prev_reg116 = value;
8'd117: prev_reg117 = value;
8'd118: prev_reg118 = value;
8'd119: prev_reg119 = value;
8'd120: prev_reg120 = value;
8'd121: prev_reg121 = value;
8'd122: prev_reg122 = value;
8'd123: prev_reg123 = value;
8'd124: prev_reg124 = value;
8'd125: prev_reg125 = value;
8'd126: prev_reg126 = value;
8'd127: prev_reg127 = value;
8'd128: prev_reg128 = value;
8'd129: prev_reg129 = value;
8'd130: prev_reg130 = value;
8'd131: prev_reg131 = value;
8'd132: prev_reg132 = value;
8'd133: prev_reg133 = value;
8'd134: prev_reg134 = value;
8'd135: prev_reg135 = value;
8'd136: prev_reg136 = value;
8'd137: prev_reg137 = value;
8'd138: prev_reg138 = value;
8'd139: prev_reg139 = value;
8'd140: prev_reg140 = value;
8'd141: prev_reg141 = value;
8'd142: prev_reg142 = value;
8'd143: prev_reg143 = value;
8'd144: prev_reg144 = value;
8'd145: prev_reg145 = value;
8'd146: prev_reg146 = value;
8'd147: prev_reg147 = value;
8'd148: prev_reg148 = value;
8'd149: prev_reg149 = value;
8'd150: prev_reg150 = value;
8'd151: prev_reg151 = value;
8'd152: prev_reg152 = value;
8'd153: prev_reg153 = value;
8'd154: prev_reg154 = value;
8'd155: prev_reg155 = value;
8'd156: prev_reg156 = value;
8'd157: prev_reg157 = value;
8'd158: prev_reg158 = value;
8'd159: prev_reg159 = value;
8'd160: prev_reg160 = value;
8'd161: prev_reg161 = value;
8'd162: prev_reg162 = value;
8'd163: prev_reg163 = value;
8'd164: prev_reg164 = value;
8'd165: prev_reg165 = value;
8'd166: prev_reg166 = value;
8'd167: prev_reg167 = value;
8'd168: prev_reg168 = value;
8'd169: prev_reg169 = value;
8'd170: prev_reg170 = value;
8'd171: prev_reg171 = value;
8'd172: prev_reg172 = value;
8'd173: prev_reg173 = value;
8'd174: prev_reg174 = value;
8'd175: prev_reg175 = value;
8'd176: prev_reg176 = value;
8'd177: prev_reg177 = value;
8'd178: prev_reg178 = value;
8'd179: prev_reg179 = value;
8'd180: prev_reg180 = value;
8'd181: prev_reg181 = value;
8'd182: prev_reg182 = value;
8'd183: prev_reg183 = value;
8'd184: prev_reg184 = value;
8'd185: prev_reg185 = value;
8'd186: prev_reg186 = value;
8'd187: prev_reg187 = value;
8'd188: prev_reg188 = value;
8'd189: prev_reg189 = value;
8'd190: prev_reg190 = value;
8'd191: prev_reg191 = value;
8'd192: prev_reg192 = value;
8'd193: prev_reg193 = value;
8'd194: prev_reg194 = value;
8'd195: prev_reg195 = value;
8'd196: prev_reg196 = value;
8'd197: prev_reg197 = value;
8'd198: prev_reg198 = value;
8'd199: prev_reg199 = value;
8'd200: prev_reg200 = value;
8'd201: prev_reg201 = value;
8'd202: prev_reg202 = value;
8'd203: prev_reg203 = value;
8'd204: prev_reg204 = value;
8'd205: prev_reg205 = value;
8'd206: prev_reg206 = value;
8'd207: prev_reg207 = value;
8'd208: prev_reg208 = value;
8'd209: prev_reg209 = value;
8'd210: prev_reg210 = value;
8'd211: prev_reg211 = value;
8'd212: prev_reg212 = value;
8'd213: prev_reg213 = value;
8'd214: prev_reg214 = value;
8'd215: prev_reg215 = value;
8'd216: prev_reg216 = value;
8'd217: prev_reg217 = value;
8'd218: prev_reg218 = value;
8'd219: prev_reg219 = value;
8'd220: prev_reg220 = value;
8'd221: prev_reg221 = value;
8'd222: prev_reg222 = value;
8'd223: prev_reg223 = value;
8'd224: prev_reg224 = value;
8'd225: prev_reg225 = value;
8'd226: prev_reg226 = value;
8'd227: prev_reg227 = value;
8'd228: prev_reg228 = value;
8'd229: prev_reg229 = value;
8'd230: prev_reg230 = value;
8'd231: prev_reg231 = value;
8'd232: prev_reg232 = value;
8'd233: prev_reg233 = value;
8'd234: prev_reg234 = value;
8'd235: prev_reg235 = value;
8'd236: prev_reg236 = value;
8'd237: prev_reg237 = value;
8'd238: prev_reg238 = value;
8'd239: prev_reg239 = value;
8'd240: prev_reg240 = value;
8'd241: prev_reg241 = value;
8'd242: prev_reg242 = value;
8'd243: prev_reg243 = value;
8'd244: prev_reg244 = value;
8'd245: prev_reg245 = value;
8'd246: prev_reg246 = value;
8'd247: prev_reg247 = value;
8'd248: prev_reg248 = value;
8'd249: prev_reg249 = value;
8'd250: prev_reg250 = value;
8'd251: prev_reg251 = value;
8'd252: prev_reg252 = value;
8'd253: prev_reg253 = value;
8'd254: prev_reg254 = value;
8'd255: prev_reg255 = value;
//----------------------------------------------------------
// Read value frpm prev_reg using id as index
function [63:0] read_prev;
8'd0: read_prev = prev_reg0;
8'd1: read_prev = prev_reg1;
8'd2: read_prev = prev_reg2;
8'd3: read_prev = prev_reg3;
8'd4: read_prev = prev_reg4;
8'd5: read_prev = prev_reg5;
8'd6: read_prev = prev_reg6;
8'd7: read_prev = prev_reg7;
8'd8: read_prev = prev_reg8;
8'd9: read_prev = prev_reg9;
8'd10: read_prev = prev_reg10;
8'd11: read_prev = prev_reg11;
8'd12: read_prev = prev_reg12;
8'd13: read_prev = prev_reg13;
8'd14: read_prev = prev_reg14;
8'd15: read_prev = prev_reg15;
8'd16: read_prev = prev_reg16;
8'd17: read_prev = prev_reg17;
8'd18: read_prev = prev_reg18;
8'd19: read_prev = prev_reg19;
8'd20: read_prev = prev_reg20;
8'd21: read_prev = prev_reg21;
8'd22: read_prev = prev_reg22;
8'd23: read_prev = prev_reg23;
8'd24: read_prev = prev_reg24;
8'd25: read_prev = prev_reg25;
8'd26: read_prev = prev_reg26;
8'd27: read_prev = prev_reg27;
8'd28: read_prev = prev_reg28;
8'd29: read_prev = prev_reg29;
8'd30: read_prev = prev_reg30;
8'd31: read_prev = prev_reg31;
8'd32: read_prev = prev_reg32;
8'd33: read_prev = prev_reg33;
8'd34: read_prev = prev_reg34;
8'd35: read_prev = prev_reg35;
8'd36: read_prev = prev_reg36;
8'd37: read_prev = prev_reg37;
8'd38: read_prev = prev_reg38;
8'd39: read_prev = prev_reg39;
8'd40: read_prev = prev_reg40;
8'd41: read_prev = prev_reg41;
8'd42: read_prev = prev_reg42;
8'd43: read_prev = prev_reg43;
8'd44: read_prev = prev_reg44;
8'd45: read_prev = prev_reg45;
8'd46: read_prev = prev_reg46;
8'd47: read_prev = prev_reg47;
8'd48: read_prev = prev_reg48;
8'd49: read_prev = prev_reg49;
8'd50: read_prev = prev_reg50;
8'd51: read_prev = prev_reg51;
8'd52: read_prev = prev_reg52;
8'd53: read_prev = prev_reg53;
8'd54: read_prev = prev_reg54;
8'd55: read_prev = prev_reg55;
8'd56: read_prev = prev_reg56;
8'd57: read_prev = prev_reg57;
8'd58: read_prev = prev_reg58;
8'd59: read_prev = prev_reg59;
8'd60: read_prev = prev_reg60;
8'd61: read_prev = prev_reg61;
8'd62: read_prev = prev_reg62;
8'd63: read_prev = prev_reg63;
8'd64: read_prev = prev_reg64;
8'd65: read_prev = prev_reg65;
8'd66: read_prev = prev_reg66;
8'd67: read_prev = prev_reg67;
8'd68: read_prev = prev_reg68;
8'd69: read_prev = prev_reg69;
8'd70: read_prev = prev_reg70;
8'd71: read_prev = prev_reg71;
8'd72: read_prev = prev_reg72;
8'd73: read_prev = prev_reg73;
8'd74: read_prev = prev_reg74;
8'd75: read_prev = prev_reg75;
8'd76: read_prev = prev_reg76;
8'd77: read_prev = prev_reg77;
8'd78: read_prev = prev_reg78;
8'd79: read_prev = prev_reg79;
8'd80: read_prev = prev_reg80;
8'd81: read_prev = prev_reg81;
8'd82: read_prev = prev_reg82;
8'd83: read_prev = prev_reg83;
8'd84: read_prev = prev_reg84;
8'd85: read_prev = prev_reg85;
8'd86: read_prev = prev_reg86;
8'd87: read_prev = prev_reg87;
8'd88: read_prev = prev_reg88;
8'd89: read_prev = prev_reg89;
8'd90: read_prev = prev_reg90;
8'd91: read_prev = prev_reg91;
8'd92: read_prev = prev_reg92;
8'd93: read_prev = prev_reg93;
8'd94: read_prev = prev_reg94;
8'd95: read_prev = prev_reg95;
8'd96: read_prev = prev_reg96;
8'd97: read_prev = prev_reg97;
8'd98: read_prev = prev_reg98;
8'd99: read_prev = prev_reg99;
8'd100: read_prev = prev_reg100;
8'd101: read_prev = prev_reg101;
8'd102: read_prev = prev_reg102;
8'd103: read_prev = prev_reg103;
8'd104: read_prev = prev_reg104;
8'd105: read_prev = prev_reg105;
8'd106: read_prev = prev_reg106;
8'd107: read_prev = prev_reg107;
8'd108: read_prev = prev_reg108;
8'd109: read_prev = prev_reg109;
8'd110: read_prev = prev_reg110;
8'd111: read_prev = prev_reg111;
8'd112: read_prev = prev_reg112;
8'd113: read_prev = prev_reg113;
8'd114: read_prev = prev_reg114;
8'd115: read_prev = prev_reg115;
8'd116: read_prev = prev_reg116;
8'd117: read_prev = prev_reg117;
8'd118: read_prev = prev_reg118;
8'd119: read_prev = prev_reg119;
8'd120: read_prev = prev_reg120;
8'd121: read_prev = prev_reg121;
8'd122: read_prev = prev_reg122;
8'd123: read_prev = prev_reg123;
8'd124: read_prev = prev_reg124;
8'd125: read_prev = prev_reg125;
8'd126: read_prev = prev_reg126;
8'd127: read_prev = prev_reg127;
8'd128: read_prev = prev_reg128;
8'd129: read_prev = prev_reg129;
8'd130: read_prev = prev_reg130;
8'd131: read_prev = prev_reg131;
8'd132: read_prev = prev_reg132;
8'd133: read_prev = prev_reg133;
8'd134: read_prev = prev_reg134;
8'd135: read_prev = prev_reg135;
8'd136: read_prev = prev_reg136;
8'd137: read_prev = prev_reg137;
8'd138: read_prev = prev_reg138;
8'd139: read_prev = prev_reg139;
8'd140: read_prev = prev_reg140;
8'd141: read_prev = prev_reg141;
8'd142: read_prev = prev_reg142;
8'd143: read_prev = prev_reg143;
8'd144: read_prev = prev_reg144;
8'd145: read_prev = prev_reg145;
8'd146: read_prev = prev_reg146;
8'd147: read_prev = prev_reg147;
8'd148: read_prev = prev_reg148;
8'd149: read_prev = prev_reg149;
8'd150: read_prev = prev_reg150;
8'd151: read_prev = prev_reg151;
8'd152: read_prev = prev_reg152;
8'd153: read_prev = prev_reg153;
8'd154: read_prev = prev_reg154;
8'd155: read_prev = prev_reg155;
8'd156: read_prev = prev_reg156;
8'd157: read_prev = prev_reg157;
8'd158: read_prev = prev_reg158;
8'd159: read_prev = prev_reg159;
8'd160: read_prev = prev_reg160;
8'd161: read_prev = prev_reg161;
8'd162: read_prev = prev_reg162;
8'd163: read_prev = prev_reg163;
8'd164: read_prev = prev_reg164;
8'd165: read_prev = prev_reg165;
8'd166: read_prev = prev_reg166;
8'd167: read_prev = prev_reg167;
8'd168: read_prev = prev_reg168;
8'd169: read_prev = prev_reg169;
8'd170: read_prev = prev_reg170;
8'd171: read_prev = prev_reg171;
8'd172: read_prev = prev_reg172;
8'd173: read_prev = prev_reg173;
8'd174: read_prev = prev_reg174;
8'd175: read_prev = prev_reg175;
8'd176: read_prev = prev_reg176;
8'd177: read_prev = prev_reg177;
8'd178: read_prev = prev_reg178;
8'd179: read_prev = prev_reg179;
8'd180: read_prev = prev_reg180;
8'd181: read_prev = prev_reg181;
8'd182: read_prev = prev_reg182;
8'd183: read_prev = prev_reg183;
8'd184: read_prev = prev_reg184;
8'd185: read_prev = prev_reg185;
8'd186: read_prev = prev_reg186;
8'd187: read_prev = prev_reg187;
8'd188: read_prev = prev_reg188;
8'd189: read_prev = prev_reg189;
8'd190: read_prev = prev_reg190;
8'd191: read_prev = prev_reg191;
8'd192: read_prev = prev_reg192;
8'd193: read_prev = prev_reg193;
8'd194: read_prev = prev_reg194;
8'd195: read_prev = prev_reg195;
8'd196: read_prev = prev_reg196;
8'd197: read_prev = prev_reg197;
8'd198: read_prev = prev_reg198;
8'd199: read_prev = prev_reg199;
8'd200: read_prev = prev_reg200;
8'd201: read_prev = prev_reg201;
8'd202: read_prev = prev_reg202;
8'd203: read_prev = prev_reg203;
8'd204: read_prev = prev_reg204;
8'd205: read_prev = prev_reg205;
8'd206: read_prev = prev_reg206;
8'd207: read_prev = prev_reg207;
8'd208: read_prev = prev_reg208;
8'd209: read_prev = prev_reg209;
8'd210: read_prev = prev_reg210;
8'd211: read_prev = prev_reg211;
8'd212: read_prev = prev_reg212;
8'd213: read_prev = prev_reg213;
8'd214: read_prev = prev_reg214;
8'd215: read_prev = prev_reg215;
8'd216: read_prev = prev_reg216;
8'd217: read_prev = prev_reg217;
8'd218: read_prev = prev_reg218;
8'd219: read_prev = prev_reg219;
8'd220: read_prev = prev_reg220;
8'd221: read_prev = prev_reg221;
8'd222: read_prev = prev_reg222;
8'd223: read_prev = prev_reg223;
8'd224: read_prev = prev_reg224;
8'd225: read_prev = prev_reg225;
8'd226: read_prev = prev_reg226;
8'd227: read_prev = prev_reg227;
8'd228: read_prev = prev_reg228;
8'd229: read_prev = prev_reg229;
8'd230: read_prev = prev_reg230;
8'd231: read_prev = prev_reg231;
8'd232: read_prev = prev_reg232;
8'd233: read_prev = prev_reg233;
8'd234: read_prev = prev_reg234;
8'd235: read_prev = prev_reg235;
8'd236: read_prev = prev_reg236;
8'd237: read_prev = prev_reg237;
8'd238: read_prev = prev_reg238;
8'd239: read_prev = prev_reg239;
8'd240: read_prev = prev_reg240;
8'd241: read_prev = prev_reg241;
8'd242: read_prev = prev_reg242;
8'd243: read_prev = prev_reg243;
8'd244: read_prev = prev_reg244;
8'd245: read_prev = prev_reg245;
8'd246: read_prev = prev_reg246;
8'd247: read_prev = prev_reg247;
8'd248: read_prev = prev_reg248;
8'd249: read_prev = prev_reg249;
8'd250: read_prev = prev_reg250;
8'd251: read_prev = prev_reg251;
8'd252: read_prev = prev_reg252;
8'd253: read_prev = prev_reg253;
8'd254: read_prev = prev_reg254;
8'd255: read_prev = prev_reg255;
//----------------------------------------------------------
remap[4] = rd[4] ^ (rd[3] & oddwin);
//----------------------------------------------------------
// Initialize nas_pipe registers
initial begin : INIT_BLOCK
nas_pipe_enable = 1'b1; // Nas_pipe always enables itself
good_trap_detected = 1'b0;
@ (posedge `BENCH_SPC7_GCLK);
`TOP.th_last_act_cycle[mytnum] = 0;
`PR_INFO ("nas", `INFO, "T%0d Init shadow registers.",mytnum);
// POR for control registers
write_prev(`FPRS +`CTL_OFFSET,3'h4);
write_prev(`CLEANWIN +`CTL_OFFSET,3'h7);
write_prev(`CANSAVE +`CTL_OFFSET,3'h6);
write_prev(`FPRS+`CTL_OFFSET,3'h4);
// POR for PSTATE = 0x14 (PEF, PRIV = 1)
write_prev(`PSTATE + `CTL_OFFSET,'h14);
// POR for HPSTATE = 0x4034 (RED, HPRIV = 1)
write_prev(`HPSTATE + `CTL_OFFSET,'h24);
// POR for TL = = 0x6 [MAXTL]
write_prev(`TL + `CTL_OFFSET,'h6);
write_prev(`TT6 + `CTL_OFFSET,'h1);
// POR for GL = MAXGL = 3
write_prev(`GL + `CTL_OFFSET,`POR_GL);
// POR for VER = {003e, 0024, 01, 0036, 07}
write_prev(`VER + `CTL_OFFSET,{32'h003e0024,VER_reg[31:24],24'h030607});
// POR for *_cmpr registers is INT_DIS = 1
write_prev(`TICK_CMPR + `CTL_OFFSET,64'h8000000000000000);
write_prev(`STICK_CMPR + `CTL_OFFSET,64'h8000000000000000);
write_prev(`HSTICK_CMPR + `CTL_OFFSET,64'h8000000000000000);
// Need to define so that 1st instruction will print correctly
write_prev(`PC+`CTL_OFFSET,`POR_PC);
delta_prev[`PC_INDEX] = `BAD_PC;
irf_offset = (mytid%4)*32;
//----------------------------------------------------------
// For WMR, we will set to 0x0, so that initial deltas
// WMR for PSTATE = 0x14 (PEF, PRIV = 1)
// write_prev(`PSTATE + `CTL_OFFSET,'h00);
// WMR for HPSTATE = 0x4034 (RED, HPRIV = 1)
// write_prev(`HPSTATE + `CTL_OFFSET,'h00);
// WMR for TL = = 0x6 [MAXTL]
// write_prev(`TL + `CTL_OFFSET,'h0);
// write_prev(`TT6 + `CTL_OFFSET,'h1);
// WMR for GL = MAXGL = 3
// write_prev(`GL + `CTL_OFFSET,0);
//----------------------------------------------------------
// For POR, we will set to 0x0, so that initial deltas
// and prev state are all consistent with DUT. No values
`PR_ALWAYS ("arg", `ALWAYS,"T%0d Resetting Nas Pipe states for POR ..",mytnum);
delta_fx4[`NEXT_INDEX] <= `FIRST_INDEX;
delta_fx4[`FIRST_INDEX] <= 77'hx;
delta_fx5[`NEXT_INDEX] <= `FIRST_INDEX;
delta_fb[`NEXT_INDEX] <= `FIRST_INDEX;
delta_fw[`NEXT_INDEX] <= `FIRST_INDEX;
delta_fw1[`NEXT_INDEX] <= `FIRST_INDEX;
delta_fw2[`NEXT_INDEX] <= `FIRST_INDEX;
`PR_INFO ("nas", `INFO, "T%0d Init shadow registers.",mytnum);
// POR for control registers
write_prev(`FPRS +`CTL_OFFSET,3'h4);
write_prev(`CLEANWIN +`CTL_OFFSET,3'h7);
write_prev(`CANSAVE +`CTL_OFFSET,3'h6);
write_prev(`FPRS+`CTL_OFFSET,3'h4);
// POR for PSTATE = 0x14 (PEF, PRIV = 1)
write_prev(`PSTATE + `CTL_OFFSET,'h14);
// POR for HPSTATE = 0x4034 (RED, HPRIV = 1)
write_prev(`HPSTATE + `CTL_OFFSET,'h24);
// POR for TL = = 0x6 [MAXTL]
write_prev(`TL + `CTL_OFFSET,'h6);
write_prev(`TT6 + `CTL_OFFSET,'h1);
// POR for GL = MAXGL = 3
write_prev(`GL + `CTL_OFFSET,`POR_GL);
// POR for VER = {003e, 0024, 01, 0036, 07}
write_prev(`VER + `CTL_OFFSET,64'h003e002410030607);
// POR for *_cmpr registers is INT_DIS = 1
write_prev(`TICK_CMPR + `CTL_OFFSET,64'h8000000000000000);
write_prev(`STICK_CMPR + `CTL_OFFSET,64'h8000000000000000);
write_prev(`HSTICK_CMPR + `CTL_OFFSET,64'h8000000000000000);
// Need to define so that 1st instruction will print correctly
write_prev(`PC+`CTL_OFFSET,`POR_PC);
//----------------------------------------------------------
//----------------------------------------------------------
// Watch for Good/Bad trap
wire [5:0] mytnum = (mycid*8)+mytid;
// Delimiter changes whether flat or hierarchical netlist
wire myclk = tb_top.cpu.spc7.gclk;
wire dec_inst_valid_m = mytg ? tb_top.cpu.spc7.dec_inst_valid_m[1] : tb_top.cpu.spc7.dec_inst_valid_m[0];
wire [1:0] dec_tid_m = mytg ? tb_top.cpu.spc7.dec_tid1_m : tb_top.cpu.spc7.dec_tid0_m;
wire dec_flush_b = mytg ? tb_top.cpu.spc7.dec_flush_b[1] : tb_top.cpu.spc7.dec_flush_b[0];
wire tlu_flush_ifu = tb_top.cpu.spc7.tlu_flush_ifu[mytid];
wire [47:0] pc_d = mytg ? {tb_top.cpu.spc7.tlu_pc_1_d[47:2],2'b0} : {tb_top.cpu.spc7.tlu_pc_0_d[47:2],2'b0};
wire [31:0] op_d = mytg ? tb_top.cpu.spc7.dec_inst1_d[31:0] : tb_top.cpu.spc7.dec_inst0_d[31:0];
wire myclk = tb_top.cpu.spc7.gclk;
wire dec_inst_valid_m = mytg ? tb_top.cpu.spc7.dec_inst_valid_m[1] : tb_top.cpu.spc7.dec_inst_valid_m[0];
wire [1:0] dec_tid_m = mytg ? tb_top.cpu.spc7.dec_tid1_m : tb_top.cpu.spc7.dec_tid0_m;
wire dec_flush_b = mytg ? tb_top.cpu.spc7.dec_flush_b[1] : tb_top.cpu.spc7.dec_flush_b[0];
wire tlu_flush_ifu = tb_top.cpu.spc7.tlu_flush_ifu[mytid];
wire [47:0] pc_d = mytg ? {tb_top.cpu.spc7.tlu_pc_1_d[47:2],2'b0} : {tb_top.cpu.spc7.tlu_pc_0_d[47:2],2'b0};
wire [31:0] op_d = mytg ? tb_top.cpu.spc7.dec_inst1_d[31:0] : tb_top.cpu.spc7.dec_inst0_d[31:0];
wire inst_valid_b = dec_inst_valid_b && (dec_tid_b==mytid[1:0]) && !(dec_flush_b || tlu_flush_ifu);
always @ (posedge myclk) begin // {
dec_inst_valid_b <= dec_inst_valid_m;
inst_valid_w <= inst_valid_b;
inst_valid_fx4 <= inst_valid_w;
inst_valid_fx5 <= inst_valid_fx4;
inst_valid_fb <= inst_valid_fx5;
inst_valid_fw <= inst_valid_fb;
inst_valid_fw1 <= inst_valid_fw;
inst_valid_fw2 <= inst_valid_fw1;
if (`PARGS.th_check_enable[mytnum] && nas_pipe_enable) begin // {
if (inst_valid_fw2) begin // {
// Print PC/opcode for debugging
`PR_NORMAL ("nas", `NORMAL, "@%0d #%0d T%0d %h [%h]", $time, inst_count, mytnum, pc_fw2, op_fw2);
inst_count = inst_count + 1;
// End detection for GateSim runs
for (junk=0;junk<`PARGS.bad_trap_count;junk=junk+1) begin // {
if (({16'b0,pc_fw2}&`PC_MASK)===(`PARGS.bad_trap_addr[junk]&`PC_MASK)) begin // {
`PR_ERROR ("nas",`ERROR, "T%0d reached Bad Trap [GATESIM]", mytnum);
for (junk=0;junk<`PARGS.good_trap_count;junk=junk+1) begin // {
if (({16'b0,pc_fw2}&`PC_MASK)===(`PARGS.good_trap_addr[junk]&`PC_MASK)) begin // {
`TOP.finished_tids[mytnum] = 1'b1;
`PARGS.th_check_enable[mytnum] = 1'b0;
`PR_NORMAL ("nas", `NORMAL, "T%0d reached Good Trap. Disabling checking for thread %0d [GATESIM]", mytnum,mytnum);
//----------------------------------------------------------
//----------------------------------------------------------
projects / OpenSPARC-T2-DV / blob