verif/env/config/fpga.config

// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T2 Processor File: fpga.config
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
//
// For the avoidance of doubt, and except that if any non-GPL license
// choice is available it will apply instead, Sun elects to use only
// the General Public License version 2 (GPLv2) at this time for any
// software where a choice of GPL license versions is made
// available with the language indicating that GPLv2 or any later version
// may be used, or where a choice of which version of the GPL is applied is
// otherwise unspecified.
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// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
// CA 95054 USA or visit www.sun.com if you need additional information or
// have any questions.
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// ========== Copyright Header End ============================================
// This config file builds all FPGA models
//////////////////////////////////////////////////////////////////////////////
<fpga_1c8t>

        -model=fpga_1c8t

#ifdef GATESIM
        -flist=$DV_ROOT/design/fpga/gate/fpga_gate_master.flist
        -vcs_build_args=-Marchive=100

#else
        -flist=$DV_ROOT/design/fpga/rtl/fpga_rtl.flist
#endif

        -novera_build
        -nontb_lib

        -vcs_build_args=+v2k
        -vcs_build_args=+vcs+initmem+0
        -vcs_build_args=-nohsopt

        -fast_boot
        -nosas
        -tg_seed=1

        -asm_diag_root=$DV_ROOT/verif/diag/assembly
        -image_diag_root=$DV_ROOT/verif/diag
        -midas_args=-tsbtagfmt=tagtarget
        -midas_args=-cpp_args=-traditional-cpp
        -midas_args=-allow_tsb_conflict
        -midas_args=-DL2_REG_PROG
        -midas_args=-DCMP_THREAD_START=0x1
        -midas_args=-DPART_0_BASE=0
        -midas_args=-DPART_1_BASE=0x20000000
        -midas_args=-DPART_2_BASE=0x30000000
        -midas_args=-DMAIN_BASE_DATA_RA=0x21000000
        -midas_args=-DMAIN_BASE_BSS_RA=0x18030000
        -midas_args=-DMAIN_BASE_TEXT_RA=0x18000000
        -midas_args=-DKERNEL_BASE_TEXT_RA=0x01834000
        -midas_args=-DUSER_HEAP_DATA_RA=0x28020000
        -midas_args=-DKERNEL_BASE_DATA_RA=0x01c34000
        -midas_args=-DPART_0_LINK_AREA_BASE_ADDR=0x2d000000
        -midas_args=-DMAIN_BASE_DATA_VA=0x2a000000

        -vcs_run_args=+GOOD_TRAP=0000083400
        -novera_run
        -post_process_cmd="regreport -1 | tee status.log"


</fpga_1c8t>
//////////////////////////////////////////////////////////////////////////////