verif/env/fc/vera/classes/FC_Utils.vr

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//
// OpenSPARC T2 Processor File: FC_Utils.vr
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#include <vera_defines.vrh>
#include "std_display_defines.vri"
#include <ccxDevices.if.vrh>
#include <ccxDevices.binds.vrh>

#include "globals.vri"

#include "baseParamsClass.vrh"
#include "sparcParams.vrh"
#include "sparcParams.vrh"

#include "baseUtilsClass.vrh"
#include "sparcBenchUtils.vrh"

#include "std_display_class.vrh"
#include "basePktClass.vrh"
#include "cpxPktClass.vrh"
#include "pcxPktClass.vrh"
#include "ccxDevBaseBFM.vrh"
#include "ccxDevMemBFM.vrh"
#include "ccxDevSpcBFM.vrh"
#include "memArray.vrh"
#include "ssi.if.vrh"
#include "ssi.vrh"
#include "FC_Utils.vrh"
#include "ccx_tag_class.vrh"

//#include "verilog_tasks.vri"


#define CLASSNAME FC_Utils
#define CLASSNAMEQ "FC_Utils"

class CLASSNAME extends SparcBenchUtils {

  local string className = "FC_Utils";
  local StandardDisplay dbg;
  local integer clockPeriod;
  SSI   bootrom;
  task new(StandardDisplay dbgHndl, integer clockPeriod = 628);
  task initTB();
}


task CLASSNAME::new(StandardDisplay dbgHndl, integer clockPeriod = 628) {
  super.new (dbgHndl, clockPeriod);
  srandom(gSeed,this);
  this.dbg = dbgHndl;
  void = randomize(); // keep!
}

// useMCUbfms 0=no, 1=yes, 2=monitor
task CLASSNAME::initTB() {

  integer i;
  VeraRandomState rstate;

  // mem array
  gMem = new(0,gDbg,0);

  // basic probes
  gProbesPort = probesBind;

  // Initialize main memory from mem.image
  gMem.loadMem("mem.image");

  bootrom = new(dbg,ncu,ssi);
  @(negedge CLOCK);


  getstate(rstate);


  setstate(rstate);

}