verif/env/fc/vera/classes/utilsClass.vrh

// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T2 Processor File: utilsClass.vrh
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#ifndef INC__TMP_UTILSCLASS_VRH
#define INC__TMP_UTILSCLASS_VRH

typedef class StandardDisplay ;
typedef class SparcBenchUtils;

extern class Utils extends SparcBenchUtils {
  task new (
    StandardDisplay dbgHndl,
    integer clockPeriod = 100
  );
  task initTB(integer useMCUbfms = 0,
              reg useL1Tags = 0,
              reg useL2bfms = 0,
              reg loadOnlyIOmem = 1);

  task resetDut (
  );
  task initDut (integer wait = 0
  );

  task sendIntr(reg [5:0] tid,
                reg [1:0] type,
                reg [5:0] vect,
                integer sendPort = 16);

//task for err injector L2
task l2_trap_count(integer count);


}

#endif