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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / env / fc / vera / interfaces / fc_shadow_scan.if.vrh
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T2 Processor File: fc_shadow_scan.if.vrh
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
//
// For the avoidance of doubt, and except that if any non-GPL license
// choice is available it will apply instead, Sun elects to use only
// the General Public License version 2 (GPLv2) at this time for any
// software where a choice of GPL license versions is made
// available with the language indicating that GPLv2 or any later version
// may be used, or where a choice of which version of the GPL is applied is
// otherwise unspecified.
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
// CA 95054 USA or visit www.sun.com if you need additional information or
// have any questions.
//
// ========== Copyright Header End ============================================
#ifndef INC_FC_SHADOW_SCAN_IF_VRH
#define INC_FC_SHADOW_SCAN_IF_VRH
#include <vera_defines.vrh>
#include "fc_top_defines.vri"
//#include "tcu_top_defines.vri"
#define INPUT_EDGE PSAMPLE
#define INPUT_SKEW #-3
interface fc_shadow_scan_if {
input clk CLOCK verilog_node "`TCU.gclk";
input spc_shadow_scan_en INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_spc_shscan_scan_en";
input [2:0] spc_shadow_scan_id INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_spc_shscanid" ;
input l2t_shadow_scan_en INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_l2t_shscan_scan_en";
input [117:0] spc0_shadow_scan_bits INPUT_EDGE INPUT_SKEW verilog_node "`CPU.spc0.tlu.ssd.shadow_unused[117:0]";
#ifndef RTL_NO_SPC1
input [117:0] spc1_shadow_scan_bits INPUT_EDGE INPUT_SKEW verilog_node "`CPU.spc1.tlu.ssd.shadow_unused[117:0]";
#endif
#ifndef RTL_NO_SPC2
input [117:0] spc2_shadow_scan_bits INPUT_EDGE INPUT_SKEW verilog_node "`CPU.spc2.tlu.ssd.shadow_unused[117:0]";
#endif
#ifndef RTL_NO_SPC3
input [117:0] spc3_shadow_scan_bits INPUT_EDGE INPUT_SKEW verilog_node "`CPU.spc3.tlu.ssd.shadow_unused[117:0]";
#endif
#ifndef RTL_NO_SPC4
input [117:0] spc4_shadow_scan_bits INPUT_EDGE INPUT_SKEW verilog_node "`CPU.spc4.tlu.ssd.shadow_unused[117:0]";
#endif
#ifndef RTL_NO_SPC5
input [117:0] spc5_shadow_scan_bits INPUT_EDGE INPUT_SKEW verilog_node "`CPU.spc5.tlu.ssd.shadow_unused[117:0]";
#endif
#ifndef RTL_NO_SPC6
input [117:0] spc6_shadow_scan_bits INPUT_EDGE INPUT_SKEW verilog_node "`CPU.spc6.tlu.ssd.shadow_unused[117:0]";
#endif
#ifndef RTL_NO_SPC7
input [117:0] spc7_shadow_scan_bits INPUT_EDGE INPUT_SKEW verilog_node "`CPU.spc7.tlu.ssd.shadow_unused[117:0]";
#endif
input [57:0] l2t0_rd_errstate_reg_bits INPUT_EDGE INPUT_SKEW verilog_node "{`CPU.l2t0.shadow_scan.rd_errstate_reg[63:34],`CPU.l2t0.shadow_scan.rd_errstate_reg[27:0]}";
input [47:0] l2t0_not_data_bits INPUT_EDGE INPUT_SKEW verilog_node "`CPU.l2t0.shadow_scan.rd_notdata_reg[51:4]";
input [35:0] l2t0_l2_erraddr_bits INPUT_EDGE INPUT_SKEW verilog_node "`CPU.l2t0.shadow_scan.csr_l2_erraddr_reg[39:4]";
input [57:0] l2t1_rd_errstate_reg_bits INPUT_EDGE INPUT_SKEW verilog_node "{`CPU.l2t1.shadow_scan.rd_errstate_reg[63:34],`CPU.l2t1.shadow_scan.rd_errstate_reg[27:0]}";
input [47:0] l2t1_not_data_bits INPUT_EDGE INPUT_SKEW verilog_node "`CPU.l2t1.shadow_scan.rd_notdata_reg[51:4]";
input [35:0] l2t1_l2_erraddr_bits INPUT_EDGE INPUT_SKEW verilog_node "`CPU.l2t1.shadow_scan.csr_l2_erraddr_reg[39:4]";
input [57:0] l2t2_rd_errstate_reg_bits INPUT_EDGE INPUT_SKEW verilog_node "{`CPU.l2t2.shadow_scan.rd_errstate_reg[63:34],`CPU.l2t2.shadow_scan.rd_errstate_reg[27:0]}";
input [47:0] l2t2_not_data_bits INPUT_EDGE INPUT_SKEW verilog_node "`CPU.l2t2.shadow_scan.rd_notdata_reg[51:4]";
input [35:0] l2t2_l2_erraddr_bits INPUT_EDGE INPUT_SKEW verilog_node "`CPU.l2t2.shadow_scan.csr_l2_erraddr_reg[39:4]";
input [57:0] l2t3_rd_errstate_reg_bits INPUT_EDGE INPUT_SKEW verilog_node "{`CPU.l2t3.shadow_scan.rd_errstate_reg[63:34],`CPU.l2t3.shadow_scan.rd_errstate_reg[27:0]}";
input [47:0] l2t3_not_data_bits INPUT_EDGE INPUT_SKEW verilog_node "`CPU.l2t3.shadow_scan.rd_notdata_reg[51:4]";
input [35:0] l2t3_l2_erraddr_bits INPUT_EDGE INPUT_SKEW verilog_node "`CPU.l2t3.shadow_scan.csr_l2_erraddr_reg[39:4]";
input [57:0] l2t4_rd_errstate_reg_bits INPUT_EDGE INPUT_SKEW verilog_node "{`CPU.l2t4.shadow_scan.rd_errstate_reg[63:34],`CPU.l2t4.shadow_scan.rd_errstate_reg[27:0]}";
input [47:0] l2t4_not_data_bits INPUT_EDGE INPUT_SKEW verilog_node "`CPU.l2t4.shadow_scan.rd_notdata_reg[51:4]";
input [35:0] l2t4_l2_erraddr_bits INPUT_EDGE INPUT_SKEW verilog_node "`CPU.l2t4.shadow_scan.csr_l2_erraddr_reg[39:4]";
input [57:0] l2t5_rd_errstate_reg_bits INPUT_EDGE INPUT_SKEW verilog_node "{`CPU.l2t5.shadow_scan.rd_errstate_reg[63:34],`CPU.l2t5.shadow_scan.rd_errstate_reg[27:0]}";
input [47:0] l2t5_not_data_bits INPUT_EDGE INPUT_SKEW verilog_node "`CPU.l2t5.shadow_scan.rd_notdata_reg[51:4]";
input [35:0] l2t5_l2_erraddr_bits INPUT_EDGE INPUT_SKEW verilog_node "`CPU.l2t5.shadow_scan.csr_l2_erraddr_reg[39:4]";
input [57:0] l2t6_rd_errstate_reg_bits INPUT_EDGE INPUT_SKEW verilog_node "{`CPU.l2t6.shadow_scan.rd_errstate_reg[63:34],`CPU.l2t6.shadow_scan.rd_errstate_reg[27:0]}";
input [47:0] l2t6_not_data_bits INPUT_EDGE INPUT_SKEW verilog_node "`CPU.l2t6.shadow_scan.rd_notdata_reg[51:4]";
input [35:0] l2t6_l2_erraddr_bits INPUT_EDGE INPUT_SKEW verilog_node "`CPU.l2t6.shadow_scan.csr_l2_erraddr_reg[39:4]";
input [57:0] l2t7_rd_errstate_reg_bits INPUT_EDGE INPUT_SKEW verilog_node "{`CPU.l2t7.shadow_scan.rd_errstate_reg[63:34],`CPU.l2t7.shadow_scan.rd_errstate_reg[27:0]}";
input [47:0] l2t7_not_data_bits INPUT_EDGE INPUT_SKEW verilog_node "`CPU.l2t7.shadow_scan.rd_notdata_reg[51:4]";
input [35:0] l2t7_l2_erraddr_bits INPUT_EDGE INPUT_SKEW verilog_node "`CPU.l2t7.shadow_scan.csr_l2_erraddr_reg[39:4]";
}
port fc_shadow_scan__port {
clk;
spc_shadow_scan_en;
spc_shadow_scan_id;
l2t_shadow_scan_en;
spc0_shadow_scan_bits;
#ifndef RTL_NO_SPC1
spc1_shadow_scan_bits;
#endif
#ifndef RTL_NO_SPC2
spc2_shadow_scan_bits;
#endif
#ifndef RTL_NO_SPC3
spc3_shadow_scan_bits;
#endif
#ifndef RTL_NO_SPC4
spc4_shadow_scan_bits;
#endif
#ifndef RTL_NO_SPC5
spc5_shadow_scan_bits;
#endif
#ifndef RTL_NO_SPC6
spc6_shadow_scan_bits;
#endif
#ifndef RTL_NO_SPC7
spc7_shadow_scan_bits;
#endif
l2t0_shadow_scan_bits;
l2t1_shadow_scan_bits;
l2t2_shadow_scan_bits;
l2t3_shadow_scan_bits;
l2t4_shadow_scan_bits;
l2t5_shadow_scan_bits;
l2t6_shadow_scan_bits;
l2t7_shadow_scan_bits;
}
bind fc_shadow_scan__port fc_shadow_scan_bind {
clk fc_shadow_scan_if.clk;
spc_shadow_scan_en fc_shadow_scan_if.spc_shadow_scan_en;
spc_shadow_scan_id fc_shadow_scan_if.spc_shadow_scan_id;
l2t_shadow_scan_en fc_shadow_scan_if.l2t_shadow_scan_en;
spc0_shadow_scan_bits fc_shadow_scan_if.spc0_shadow_scan_bits;
#ifndef RTL_NO_SPC1
spc1_shadow_scan_bits fc_shadow_scan_if .spc1_shadow_scan_bits;
#endif
#ifndef RTL_NO_SPC2
spc2_shadow_scan_bits fc_shadow_scan_if.spc2_shadow_scan_bits;
#endif
#ifndef RTL_NO_SPC3
spc3_shadow_scan_bits fc_shadow_scan_if.spc3_shadow_scan_bits;
#endif
#ifndef RTL_NO_SPC4
spc4_shadow_scan_bits fc_shadow_scan_if.spc4_shadow_scan_bits;
#endif
#ifndef RTL_NO_SPC5
spc5_shadow_scan_bits fc_shadow_scan_if.spc5_shadow_scan_bits;
#endif
#ifndef RTL_NO_SPC6
spc6_shadow_scan_bits fc_shadow_scan_if.spc6_shadow_scan_bits;
#endif
#ifndef RTL_NO_SPC7
spc7_shadow_scan_bits fc_shadow_scan_if.spc7_shadow_scan_bits;
#endif
l2t0_shadow_scan_bits
{
fc_shadow_scan_if.l2t0_rd_errstate_reg_bits,
fc_shadow_scan_if.l2t0_not_data_bits,
fc_shadow_scan_if.l2t0_l2_erraddr_bits
};
l2t1_shadow_scan_bits
{
fc_shadow_scan_if.l2t1_rd_errstate_reg_bits,
fc_shadow_scan_if.l2t1_not_data_bits,
fc_shadow_scan_if.l2t1_l2_erraddr_bits
};
l2t2_shadow_scan_bits
{
fc_shadow_scan_if.l2t2_rd_errstate_reg_bits,
fc_shadow_scan_if.l2t2_not_data_bits,
fc_shadow_scan_if.l2t2_l2_erraddr_bits
};
l2t3_shadow_scan_bits
{
fc_shadow_scan_if.l2t3_rd_errstate_reg_bits,
fc_shadow_scan_if.l2t3_not_data_bits,
fc_shadow_scan_if.l2t3_l2_erraddr_bits
};
l2t4_shadow_scan_bits
{
fc_shadow_scan_if.l2t4_rd_errstate_reg_bits,
fc_shadow_scan_if.l2t4_not_data_bits,
fc_shadow_scan_if.l2t4_l2_erraddr_bits
};
l2t5_shadow_scan_bits
{
fc_shadow_scan_if.l2t5_rd_errstate_reg_bits,
fc_shadow_scan_if.l2t5_not_data_bits,
fc_shadow_scan_if.l2t5_l2_erraddr_bits
};
l2t6_shadow_scan_bits
{
fc_shadow_scan_if.l2t6_rd_errstate_reg_bits,
fc_shadow_scan_if.l2t6_not_data_bits,
fc_shadow_scan_if.l2t6_l2_erraddr_bits
};
l2t7_shadow_scan_bits
{
fc_shadow_scan_if.l2t7_rd_errstate_reg_bits,
fc_shadow_scan_if.l2t7_not_data_bits,
fc_shadow_scan_if.l2t7_l2_erraddr_bits
};
}
#endif
Full OpenSPARC design & verification tarball including full HDL.