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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / env / ilu_peu / soma_fastlink.soma
<soma original.input.version="0.001">
<!--
======================================================================
Copyright 1999-2003 by Denali Software, Inc. All rights reserved.
======================================================================
This SOMA file describes a memory model, using Denali Software's
proprietary SOMA language. By using this SOMA file, you agree to the
following terms. If you do not agree to these terms, you may not use
this SOMA file.
Subject to the restrictions set forth below, Denali Software grants
you a non-exclusive, non-transferable license only to use this SOMA
file to simulate the memory described in it using tools supplied by
Denali Software.
You may not:
(1) Use this SOMA file to create software programs or tools that use
SOMA files as either input or output.
(2) Modify this SOMA file or the SOMA language in any manner.
(3) Use this SOMA file to create other languages for describing
memory models.
(4) Distribute this SOMA file to others.
This SOMA file is based on information received by Denali Software
from third parties. DENALI SOFTWARE PROVIDES THIS SOMA FILE "AS IS"
AND EXPRESSLY DISCLAIMS ALL REPRESENTATIONS, WARRANTIES AND
CONDITIONS, INCLUDING BUT NOT LIMITED TO WARRANTIES AND CONDITIONS OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE AND
NONINFRINGEMENT. DENALI SOFTWARE'S AGGREGATE LIABILITY ARISING FROM
YOUR USE OF THIS SOMA FILE IS LIMITED TO ONE U.S. DOLLAR.
If you have any questions or if you would like to inquire about
obtaining additional or different rights in SOMA files or the SOMA
language, please contact Denali Software, at www.denali.com or at
info@denalisoft.com.
Written on 03 Apr 2003
PureView version: 3.100 $DENALI: /home/scratch/guoqing/work/main/platform/SunOS/denali-->
<part>
<summary>
<class>pcie</class>
</summary>
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<value />
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<value>0</value>
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<value>1</value>
</feature>
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<value>257</value>
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</feature>
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<value>0</value>
</feature>
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<value>0</value>
</feature>
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<value>0</value>
</feature>
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<value>1</value>
</feature>
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<value>0</value>
</feature>
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<value>1</value>
</feature>
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<value>257</value>
</feature>
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<value>1</value>
</feature>
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<value>0</value>
</feature>
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<value>0</value>
</feature>
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<value>0</value>
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<value>1</value>
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<value>0</value>
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</feature>
<feature name="PCIEXvcR6FCNPD">
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<value>0</value>
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<value>1</value>
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<value>0</value>
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<value> 0 1</value>
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<value>0</value>
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<value>1</value>
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<value> 0</value>
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<value> 0</value>
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<value>1</value>
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<value>3</value>
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<value>0</value>
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<value>2</value>
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<value>0</value>
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<value>1</value>
</feature>
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<value>0</value>
</feature>
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<value>0</value>
</feature>
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<value>1</value>
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<value>0</value>
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<value>0</value>
</feature>
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<value>1</value>
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<value>0</value>
</feature>
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<value>0</value>
</feature>
<feature name="AMDsize">
<value>1</value>
</feature>
<feature name="VSaddr">
<value>0</value>
</feature>
<feature name="capVSPtr">
<value>0</value>
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<feature name="VSsize">
<value>4</value>
</feature>
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</feature>
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<value>1</value>
</feature>
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<value>0</value>
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<value>1</value>
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<value>0</value>
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<value>0</value>
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<value>0</value>
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<value>0</value>
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<value>0</value>
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<value>0</value>
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<value>0</value>
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<value>0</value>
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<value>0</value>
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<feature name="numSymbolErrors">
<value>4</value>
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<feature name="skipIntervalMax">
<value>15380</value>
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<feature name="skipIntervalMin">
<value>1180</value>
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<feature name="beaconSymbol">
<value>K28.5+</value>
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<value>2</value>
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<value>0</value>
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<value>0</value>
</feature>
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<value>0</value>
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<value>1</value>
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<feature name="modelTLP">
<value>1</value>
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<value>0</value>
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<value>0</value>
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<value>0</value>
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<value>1</value>
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<value>0</value>
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<value>0</value>
</feature>
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<value>0</value>
</feature>
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<value>0</value>
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<value>1</value>
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<value>1</value>
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<value>0</value>
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<value>1</value>
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<value>1</value>
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<value>0</value>
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<value>1</value>
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<value>0</value>
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<feature name="upstream">
<value>1</value>
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<feature name="hasRCRB">
<value>0</value>
</feature>
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<value>1</value>
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<value>1</value>
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<value>0</value>
</feature>
<feature name="BIST">
<value>0</value>
</feature>
<feature name="Command">
<value>1</value>
</feature>
<feature name="IOspace">
<value>1</value>
</feature>
<feature name="MEMspace">
<value>1</value>
</feature>
<feature name="EnBusMaster">
<value>0</value>
</feature>
<feature name="EnParityError">
<value>0</value>
</feature>
<feature name="EnSERR">
<value>0</value>
</feature>
<feature name="DisINT">
<value>0</value>
</feature>
<feature name="ROMbase">
<value>0</value>
</feature>
<feature name="ROMen">
<value>0</value>
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<feature name="config0">
<value>1</value>
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<value>0</value>
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<value>1</value>
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<value>0</value>
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<value>0</value>
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<value>1</value>
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<value>1</value>
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<value>0</value>
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<value>1</value>
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<value>0</value>
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<value>0</value>
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<value>0</value>
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</feature>
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</feature>
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<value>0</value>
</feature>
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<value>1</value>
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<value>1</value>
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</feature>
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</feature>
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<value>0</value>
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<value>0</value>
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<value>1</value>
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<value>1</value>
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<value>0</value>
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<value>1</value>
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</feature>
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<value>0</value>
</feature>
<feature name="PCIEXvcR3Arb3">
<value>0</value>
</feature>
<feature name="PCIEXvcR3Arb4">
<value>0</value>
</feature>
<feature name="PCIEXvcR3Arb5">
<value>0</value>
</feature>
<feature name="PCIEXvcR3APS">
<value>0</value>
</feature>
<feature name="PCIEXvcR3snoop">
<value>0</value>
</feature>
<feature name="PCIEXvcR3CT">
<value>0</value>
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<feature name="PCIEXvcR4">
<value>1</value>
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<feature name="PCIEXvcR4FC">
<value>1</value>
</feature>
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<value>0</value>
</feature>
<feature name="PCIEXvcR4Arb">
<value>0</value>
</feature>
<feature name="PCIEXvcR4Arb0">
<value>1</value>
</feature>
<feature name="PCIEXvcR4Arb1">
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</feature>
<feature name="PCIEXvcR4Arb2">
<value>0</value>
</feature>
<feature name="PCIEXvcR4Arb3">
<value>0</value>
</feature>
<feature name="PCIEXvcR4Arb4">
<value>0</value>
</feature>
<feature name="PCIEXvcR4Arb5">
<value>0</value>
</feature>
<feature name="PCIEXvcR4APS">
<value>0</value>
</feature>
<feature name="PCIEXvcR4snoop">
<value>0</value>
</feature>
<feature name="PCIEXvcR4CT">
<value>0</value>
</feature>
<feature name="PCIEXvcR5">
<value>1</value>
</feature>
<feature name="PCIEXvcR5FC">
<value>1</value>
</feature>
<feature name="PCIEXvcR5Ca">
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</feature>
<feature name="PCIEXvcR5Arb">
<value>0</value>
</feature>
<feature name="PCIEXvcR5Arb0">
<value>1</value>
</feature>
<feature name="PCIEXvcR5Arb1">
<value>0</value>
</feature>
<feature name="PCIEXvcR5Arb2">
<value>0</value>
</feature>
<feature name="PCIEXvcR5Arb3">
<value>0</value>
</feature>
<feature name="PCIEXvcR5Arb4">
<value>0</value>
</feature>
<feature name="PCIEXvcR5Arb5">
<value>0</value>
</feature>
<feature name="PCIEXvcR5APS">
<value>0</value>
</feature>
<feature name="PCIEXvcR5snoop">
<value>0</value>
</feature>
<feature name="PCIEXvcR5CT">
<value>0</value>
</feature>
<feature name="PCIEXvcR6">
<value>1</value>
</feature>
<feature name="PCIEXvcR6FC">
<value>1</value>
</feature>
<feature name="PCIEXvcR6Ca">
<value>0</value>
</feature>
<feature name="PCIEXvcR6Arb">
<value>0</value>
</feature>
<feature name="PCIEXvcR6Arb0">
<value>1</value>
</feature>
<feature name="PCIEXvcR6Arb1">
<value>0</value>
</feature>
<feature name="PCIEXvcR6Arb2">
<value>0</value>
</feature>
<feature name="PCIEXvcR6Arb3">
<value>0</value>
</feature>
<feature name="PCIEXvcR6Arb4">
<value>0</value>
</feature>
<feature name="PCIEXvcR6Arb5">
<value>0</value>
</feature>
<feature name="PCIEXvcR6APS">
<value>0</value>
</feature>
<feature name="PCIEXvcR6snoop">
<value>0</value>
</feature>
<feature name="PCIEXvcR6CT">
<value>0</value>
</feature>
<feature name="PCIEXvcR7">
<value>1</value>
</feature>
<feature name="PCIEXvcR7FC">
<value>1</value>
</feature>
<feature name="PCIEXvcR7Ca">
<value>0</value>
</feature>
<feature name="PCIEXvcR7Arb">
<value>0</value>
</feature>
<feature name="PCIEXvcR7Arb0">
<value>1</value>
</feature>
<feature name="PCIEXvcR7Arb1">
<value>0</value>
</feature>
<feature name="PCIEXvcR7Arb2">
<value>0</value>
</feature>
<feature name="PCIEXvcR7Arb3">
<value>0</value>
</feature>
<feature name="PCIEXvcR7Arb4">
<value>0</value>
</feature>
<feature name="PCIEXvcR7Arb5">
<value>0</value>
</feature>
<feature name="PCIEXvcR7APS">
<value>0</value>
</feature>
<feature name="PCIEXvcR7snoop">
<value>0</value>
</feature>
<feature name="PCIEXvcR7CT">
<value>0</value>
</feature>
<feature name="pipeDevice">
<value>0</value>
</feature>
<feature name="pipeMacro">
<value>0</value>
</feature>
<feature name="pipe8bit">
<value>1</value>
</feature>
<feature name="pipe16bit">
<value>0</value>
</feature>
<feature name="RCRB">
<value>0</value>
</feature>
<feature name="BARspec">
<value>1</value>
</feature>
<feature name="ROMbase0">
<value>0</value>
</feature>
<feature name="BrSecLat">
<value>1</value>
</feature>
<feature name="BrSLTBurst2">
<value>1</value>
</feature>
<feature name="BrSLT8">
<value>0</value>
</feature>
<feature name="BrSLThardW">
<value>0</value>
</feature>
<feature name="BrSecSt">
<value>0</value>
</feature>
<feature name="BrSecSt66">
<value>0</value>
</feature>
<feature name="BrSecStB2B">
<value>0</value>
</feature>
<feature name="BrSecStDev">
<value>0</value>
</feature>
<feature name="BrSecStDev0">
<value>1</value>
</feature>
<feature name="BrSecStDev1">
<value>0</value>
</feature>
<feature name="BrSecStDev2">
<value>0</value>
</feature>
<feature name="ROMbase1">
<value>0</value>
</feature>
<feature name="BrISA">
<value>0</value>
</feature>
<feature name="BrVGA">
<value>0</value>
</feature>
<feature name="BrVGA16">
<value>0</value>
</feature>
<feature name="BrMasterAbort">
<value>0</value>
</feature>
<feature name="BrFastB2B">
<value>0</value>
</feature>
<feature name="BrSecDCTimer">
<value>0</value>
</feature>
<feature name="BrTimerSerrEn">
<value>0</value>
</feature>
<feature name="PMEsupport">
<value>0</value>
</feature>
<feature name="PMEd0">
<value>1</value>
</feature>
<feature name="PMEd1">
<value>1</value>
</feature>
<feature name="PMEd2">
<value>1</value>
</feature>
<feature name="MSIen">
<value>0</value>
</feature>
<feature name="AGP">
<value>0</value>
</feature>
<feature name="VPD">
<value>0</value>
</feature>
<feature name="SLOT">
<value>0</value>
</feature>
<feature name="HS">
<value>0</value>
</feature>
<feature name="PCIX">
<value>0</value>
</feature>
<feature name="AMD">
<value>0</value>
</feature>
<feature name="VS">
<value>0</value>
</feature>
<feature name="DP">
<value>0</value>
</feature>
<feature name="CRC">
<value>0</value>
</feature>
<feature name="HotPlug">
<value>0</value>
</feature>
<feature name="PCIElcAspmDis">
<value>1</value>
</feature>
<feature name="PCIEXae2UM">
<value>0</value>
</feature>
<feature name="PCIEXae2UMta">
<value>0</value>
</feature>
<feature name="PCIEXae2UMma">
<value>0</value>
</feature>
<feature name="PCIEXae2UMrta">
<value>0</value>
</feature>
<feature name="PCIEXae2UMrma">
<value>1</value>
</feature>
<feature name="PCIEXae2UMue">
<value>1</value>
</feature>
<feature name="PCIEXae2UMucMsg">
<value>0</value>
</feature>
<feature name="PCIEXae2UMucData">
<value>1</value>
</feature>
<feature name="PCIEXae2UMucAttr">
<value>1</value>
</feature>
<feature name="PCIEXae2UMucAddr">
<value>1</value>
</feature>
<feature name="PCIEXae2UMdelay">
<value>1</value>
</feature>
<feature name="PCIEXae2UMperr">
<value>0</value>
</feature>
<feature name="PCIEXae2UMserr">
<value>1</value>
</feature>
<feature name="PCIEXae2UMint">
<value>0</value>
</feature>
<feature name="PCIEXae2US">
<value>0</value>
</feature>
<feature name="PCIEXae2USta">
<value>0</value>
</feature>
<feature name="PCIEXae2USma">
<value>0</value>
</feature>
<feature name="PCIEXae2USrta">
<value>0</value>
</feature>
<feature name="PCIEXae2USrma">
<value>0</value>
</feature>
<feature name="PCIEXae2USue">
<value>0</value>
</feature>
<feature name="PCIEXae2USucMsg">
<value>1</value>
</feature>
<feature name="PCIEXae2USucData">
<value>0</value>
</feature>
<feature name="PCIEXae2USucAttr">
<value>1</value>
</feature>
<feature name="PCIEXae2USucAddr">
<value>1</value>
</feature>
<feature name="PCIEXae2USdelay">
<value>0</value>
</feature>
<feature name="PCIEXae2USperr">
<value>0</value>
</feature>
<feature name="PCIEXae2USserr">
<value>1</value>
</feature>
<feature name="PCIEXae2USint">
<value>0</value>
</feature>
<feature name="reverseLaneNumbers">
<value>0</value>
</feature>
<feature name="skipInterval">
<value>0</value>
</feature>
<feature name="mergeErrMsgs">
<value>0</value>
</feature>
<feature name="disVDMsg0">
<value>0</value>
</feature>
<feature name="disVDMsg1">
<value>0</value>
</feature>
<feature name="disPoisonTX">
<value>0</value>
</feature>
<feature name="AS_EP">
<value>0</value>
</feature>
<feature name="capSLOT1st">
<value>0</value>
</feature>
<feature name="SSID">
<value>0</value>
</feature>
<pin name="TX">
<username>TX</username>
<bits>8</bits>
</pin>
<pin name="TX_">
<username>TX_</username>
<bits>8</bits>
</pin>
<pin name="RX">
<username>RX</username>
<bits>8</bits>
</pin>
<pin name="RX_">
<username>RX_</username>
<bits>8</bits>
</pin>
<pin name="CLK_TX">
<username>CLK_TX</username>
<bits>1</bits>
</pin>
<pin name="CLK_RX">
<username>CLK_RX</username>
<bits>1</bits>
</pin>
<pin name="TxData">
<username>TxData</username>
<bits>8</bits>
</pin>
<pin name="TxDataK">
<username>TxDataK</username>
<bits>1</bits>
</pin>
<pin name="RxData">
<username>RxData</username>
<bits>8</bits>
</pin>
<pin name="RxDataK">
<username>RxDataK</username>
<bits>1</bits>
</pin>
<pin name="PCLK">
<username>PCLK</username>
<bits>1</bits>
</pin>
<pin name="WAKE_">
<username>WAKE_</username>
<bits>1</bits>
</pin>
<pin name="PERST_">
<username>PERST_</username>
<bits>1</bits>
</pin>
<pin name="TxDetectRx">
<username>TxDetectRx</username>
<bits>1</bits>
</pin>
<pin name="TxElecIdle">
<username>TxElecIdle</username>
<bits>1</bits>
</pin>
<pin name="TxCompliance">
<username>TxCompliance</username>
<bits>1</bits>
</pin>
<pin name="RxPolarity">
<username>RxPolarity</username>
<bits>1</bits>
</pin>
<pin name="Reset_">
<username>Reset_</username>
<bits>1</bits>
</pin>
<pin name="PowerDown">
<username>PowerDown</username>
<bits>2</bits>
</pin>
<pin name="RxValid">
<username>RxValid</username>
<bits>1</bits>
</pin>
<pin name="PhyStatus">
<username>PhyStatus</username>
<bits>1</bits>
</pin>
<pin name="RxElecIdle">
<username>RxElecIdle</username>
<bits>1</bits>
</pin>
<pin name="RxStatus">
<username>RxStatus</username>
<bits>3</bits>
</pin>
<feature name="PcieVersion">
<value>1</value>
</feature>
<feature name="Gen1">
<value>1</value>
</feature>
<feature name="PcieSpecVersion">
<value>1</value>
</feature>
<feature name="SpecVersion_1_0a2">
<value>1</value>
</feature>
<feature name="SpecVersion_1_1">
<value>0</value>
</feature>
<feature name="RelativeOrderOnlyInitDllps">
<value>0</value>
</feature>
<feature name="fwdErrMsgEnSerr">
<value>0</value>
</feature>
<feature name="Gen2">
<value>0</value>
</feature>
<feature name="EIisEIES">
<value>0</value>
</feature>
<feature name="minK28_7L0sExit">
<value>4</value>
</feature>
<feature name="maxK28_7L0sExit">
<value>8</value>
</feature>
<feature name="autoChgSpd">
<value>1</value>
</feature>
<feature name="upconfigure">
<value>1</value>
</feature>
<feature name="discardReqFLR">
<value>1</value>
</feature>
<feature name="discardCplFLR">
<value>1</value>
</feature>
<feature name="sendCplFLR">
<value>1</value>
</feature>
<feature name="waitFLR">
<value>0</value>
</feature>
<feature name="brPciBus">
<value>0</value>
</feature>
<feature name="brPciXBus">
<value>1</value>
</feature>
<feature name="EPVF">
<value>0</value>
</feature>
<feature name="RCIEP">
<value>0</value>
</feature>
<feature name="RCEC">
<value>0</value>
</feature>
<feature name="PHY">
<value>0</value>
</feature>
<feature name="intLpinOrPacket">
<value>1</value>
</feature>
<feature name="intLpin">
<value>1</value>
</feature>
<feature name="pipeDIW8G1">
<value>0</value>
</feature>
<feature name="pipeDIW16G1">
<value>1</value>
</feature>
<feature name="pipeDIW8G2">
<value>0</value>
</feature>
<feature name="pipeDIW16G2">
<value>1</value>
</feature>
<feature name="ImTxDeemph">
<value>0</value>
</feature>
<feature name="ImTxMargin">
<value>0</value>
</feature>
<feature name="ImTxSwing">
<value>0</value>
</feature>
<feature name="PL_PHY">
<value>0</value>
</feature>
<feature name="phyLaneCount">
<value>0</value>
</feature>
<feature name="refClkMultiplier">
<value>1</value>
</feature>
<feature name="NFTSWithCommonClock">
<value>1</value>
</feature>
<feature name="NFTSWithoutCommonClock">
<value>4</value>
</feature>
<feature name="diffNFTSGen2">
<value>0</value>
</feature>
<feature name="NFTSWithCommonClockGen2">
<value>1</value>
</feature>
<feature name="NFTSWithoutCommonClockGen2">
<value>4</value>
</feature>
<feature name="useMaxFtsTimeout">
<value>0</value>
</feature>
<feature name="txBitSkewValues">
<value>random</value>
</feature>
<feature name="unknownValue">
<value>0</value>
</feature>
<feature name="unknownValue0">
<value>0</value>
</feature>
<feature name="unknownValue1">
<value>0</value>
</feature>
<feature name="unknownValueZ">
<value>0</value>
</feature>
<feature name="unknownValueX">
<value>1</value>
</feature>
<feature name="unknownTimingWindow">
<value>0</value>
</feature>
<feature name="fifoRxSize">
<value>26</value>
</feature>
<feature name="fifoTxSize">
<value>26</value>
</feature>
<feature name="recoveryFinishesCurrentPkt">
<value>0</value>
</feature>
<feature name="txSymbolSkewValues">
<value>random</value>
</feature>
<feature name="capBeacon">
<value>1</value>
</feature>
<feature name="beaconLanes">
<value>0x1</value>
</feature>
<feature name="capLBmaster">
<value>1</value>
</feature>
<feature name="laneLBSlaveOnly">
<value>0</value>
</feature>
<feature name="capXLink">
<value>0</value>
</feature>
<feature name="capFrameErr">
<value>1</value>
</feature>
<feature name="capSymLossErr">
<value>0</value>
</feature>
<feature name="capLnDeskewErr">
<value>0</value>
</feature>
<feature name="capElasErr">
<value>0</value>
</feature>
<feature name="dis8b10bCfg">
<value>0</value>
</feature>
<feature name="dis8b10bDisabled">
<value>0</value>
</feature>
<feature name="dis8b10bHotReset">
<value>0</value>
</feature>
<feature name="inL0NoEIOS">
<value>0</value>
</feature>
<feature name="ttxLoopbackDelay">
<value>0</value>
</feature>
<feature name="ttxLoopbackUnder">
<value>0</value>
</feature>
<feature name="ttxLoopbackOver">
<value>25</value>
</feature>
<feature name="pollActiveLnCnt">
<value>0</value>
</feature>
<feature name="eiesInterval">
<value>32</value>
</feature>
<feature name="chkRsvDrate">
<value>0</value>
</feature>
<feature name="enPollSpd">
<value>0</value>
</feature>
<feature name="mfEcrcTlp">
<value>0</value>
</feature>
<feature name="turnOffLane">
<value>0</value>
</feature>
<feature name="minPLTlpBytes">
<value>7500</value>
</feature>
<feature name="maxPLTlpBytes">
<value>15000</value>
</feature>
<feature name="addlTS1Cfg">
<value>0</value>
</feature>
<feature name="resetSkpTimerEItx">
<value>0</value>
</feature>
<feature name="resetSkpTimerEIrx">
<value>0</value>
</feature>
<feature name="sameSpeedPowerChg">
<value>1</value>
</feature>
<feature name="multiLinkPerPort">
<value>0</value>
</feature>
<feature name="noPipeP0s">
<value>0</value>
</feature>
<feature name="noPipeP1">
<value>0</value>
</feature>
<feature name="noPipeP2">
<value>0</value>
</feature>
<feature name="pipeP2inL1">
<value>0</value>
</feature>
<feature name="UImargin">
<value>15</value>
</feature>
<feature name="ReEnterRecovery">
<value>0</value>
</feature>
<feature name="assertDisScram">
<value>1</value>
</feature>
<feature name="delayComplSymX1">
<value>0</value>
</feature>
<feature name="suppLowSwing">
<value>0</value>
</feature>
<feature name="deemphasis">
<value>1</value>
</feature>
<feature name="PCIElc2SelDeem">
<value>0</value>
</feature>
<feature name="PCIElc2SelDeemLB">
<value>0</value>
</feature>
<feature name="PCIElc2SelDeemCompl">
<value>0</value>
</feature>
<feature name="useDefaultTxL0sAdjustment">
<value>1</value>
</feature>
<feature name="useDefaultRxL0sAdjustment">
<value>1</value>
</feature>
<feature name="fcTimeout">
<value>0</value>
</feature>
<feature name="fcTimeoutAnyDllp">
<value>0</value>
</feature>
<feature name="TLpmeSize">
<value>32</value>
</feature>
<feature name="TLCRSCnt">
<value>1</value>
</feature>
<feature name="TLTxQDelay">
<value>0</value>
</feature>
<feature name="oneErrPerRxTlp">
<value>0</value>
</feature>
<feature name="accPoisonRX">
<value>0</value>
</feature>
<feature name="accPoisonUR">
<value>0</value>
</feature>
<feature name="noURPoison">
<value>0</value>
</feature>
<feature name="retryNPReq">
<value>0</value>
</feature>
<feature name="implRCMEM">
<value>0</value>
</feature>
<feature name="implRCIO">
<value>0</value>
</feature>
<feature name="pmL1Gap">
<value>4</value>
</feature>
<feature name="pmL1aspmGap">
<value>4</value>
</feature>
<feature name="pmL23Gap">
<value>4</value>
</feature>
<feature name="pmAckGap">
<value>4</value>
</feature>
<feature name="msgSlotPwr">
<value>0</value>
</feature>
<feature name="txPLuse">
<value>1</value>
</feature>
<feature name="txPLuseSelf">
<value>1</value>
</feature>
<feature name="txPLuseMin">
<value>0</value>
</feature>
<feature name="txPLuseMax">
<value>0</value>
</feature>
<feature name="rxPLuse">
<value>1</value>
</feature>
<feature name="rxPLuseSelf">
<value>1</value>
</feature>
<feature name="rxPLuseMin">
<value>0</value>
</feature>
<feature name="rxPLuseMax">
<value>0</value>
</feature>
<feature name="sameSrcOrd">
<value>0</value>
</feature>
<feature name="mfCRS">
<value>1</value>
</feature>
<feature name="bcUnlockMsg">
<value>1</value>
</feature>
<feature name="disBEchk">
<value>0</value>
</feature>
<feature name="dis4Kchk">
<value>0</value>
</feature>
<feature name="disIOchk">
<value>0</value>
</feature>
<feature name="disCFGchk">
<value>0</value>
</feature>
<feature name="disINTXchk">
<value>0</value>
</feature>
<feature name="disRCBchk">
<value>0</value>
</feature>
<feature name="enMFTlpFC">
<value>0</value>
</feature>
<feature name="disINTXRXchk">
<value>0</value>
</feature>
<feature name="disFCMaxchk">
<value>0</value>
</feature>
<feature name="autoMsiMask">
<value>0</value>
</feature>
<feature name="CplMatchAttr">
<value>0</value>
</feature>
<feature name="CplMatchTc">
<value>0</value>
</feature>
<feature name="CplEndMemReq">
<value>1</value>
</feature>
<feature name="splitMemTrans">
<value>0</value>
</feature>
<feature name="iovMaxNumVF">
<value>0</value>
</feature>
<feature name="disP2P">
<value>0</value>
</feature>
<feature name="ImInterruptLine">
<value>1</value>
</feature>
<feature name="ImIOspace">
<value>1</value>
</feature>
<feature name="ImMEMspace">
<value>1</value>
</feature>
<feature name="ImMasEn">
<value>1</value>
</feature>
<feature name="MasEn">
<value>1</value>
</feature>
<feature name="ImDisINT">
<value>1</value>
</feature>
<feature name="ImMwrInv">
<value>1</value>
</feature>
<feature name="ROMen0">
<value>1</value>
</feature>
<feature name="ROMen1">
<value>1</value>
</feature>
<feature name="PMversion">
<value>2</value>
</feature>
<feature name="PMEclk">
<value>0</value>
</feature>
<feature name="PMEnoSoftRst">
<value>0</value>
</feature>
<feature name="B2B3">
<value>0</value>
</feature>
<feature name="BPCCen">
<value>0</value>
</feature>
<feature name="PMEd3cold">
<value>1</value>
</feature>
<feature name="PMEd3hot">
<value>1</value>
</feature>
<feature name="PMEImEn">
<value>1</value>
</feature>
<feature name="MSIPVMen">
<value>0</value>
</feature>
<feature name="MSIX">
<value>0</value>
</feature>
<feature name="MSIXaddr">
<value>0</value>
</feature>
<feature name="capMSIXPtr">
<value>0</value>
</feature>
<feature name="MSIXts">
<value>1</value>
</feature>
<feature name="MSIXtblOS">
<value>0</value>
</feature>
<feature name="MSIXtblBIR">
<value>0</value>
</feature>
<feature name="MSIXpbaOS">
<value>0</value>
</feature>
<feature name="MSIXpbaBIR">
<value>0</value>
</feature>
<feature name="PCIXversion">
<value>0</value>
</feature>
<feature name="PCIX64bit">
<value>0</value>
</feature>
<feature name="PCIX133Cap">
<value>0</value>
</feature>
<feature name="PCIX266Cap">
<value>0</value>
</feature>
<feature name="PCIX533Cap">
<value>0</value>
</feature>
<feature name="PCIXtype0">
<value>1</value>
</feature>
<feature name="PCIXbridge">
<value>0</value>
</feature>
<feature name="PCIXmaxRd">
<value>512</value>
</feature>
<feature name="PCIXmaxSplit">
<value>1</value>
</feature>
<feature name="PCIXmaxCuRd">
<value>1</value>
</feature>
<feature name="PCIXtype1">
<value>0</value>
</feature>
<feature name="PCIXbrFreq">
<value>0</value>
</feature>
<feature name="PCIXbrParity">
<value>0</value>
</feature>
<feature name="PCIXbr">
<value>1</value>
</feature>
<feature name="PCIXbrFN">
<value>0</value>
</feature>
<feature name="PCIXbrDN">
<value>0</value>
</feature>
<feature name="PCIXbrBN">
<value>0</value>
</feature>
<feature name="PCIXbrIdMsg">
<value>0</value>
</feature>
<feature name="PCIXbrSplitCapUp">
<value>0</value>
</feature>
<feature name="PCIXbrSplitCapDn">
<value>0</value>
</feature>
<feature name="PCIErev">
<value>1</value>
</feature>
<feature name="PCIEmsiIntxNum">
<value>0</value>
</feature>
<feature name="PCIEmsixIntxNum">
<value>0</value>
</feature>
<feature name="PCIEtcs">
<value>0</value>
</feature>
<feature name="PCIEdevRole">
<value>0</value>
</feature>
<feature name="PCIEdevFLR">
<value>0</value>
</feature>
<feature name="PCIEdcImRelOrder">
<value>1</value>
</feature>
<feature name="PCIEdcImEtag">
<value>1</value>
</feature>
<feature name="PCIEdcImPF">
<value>1</value>
</feature>
<feature name="PCIEdcImAux">
<value>1</value>
</feature>
<feature name="PCIEdcImNoSnoop">
<value>1</value>
</feature>
<feature name="PCIEdcImMaxPL">
<value>1</value>
</feature>
<feature name="PCIEdcImMaxRead">
<value>1</value>
</feature>
<feature name="PCIEdev2">
<value>0</value>
</feature>
<feature name="PCIEdev2Range">
<value>0</value>
</feature>
<feature name="PCIEdev2RangeA">
<value>0</value>
</feature>
<feature name="PCIEdev2RangeB">
<value>0</value>
</feature>
<feature name="PCIEdev2RangeAB">
<value>0</value>
</feature>
<feature name="PCIEdev2RangeBC">
<value>0</value>
</feature>
<feature name="PCIEdev2RangeABC">
<value>0</value>
</feature>
<feature name="PCIEdev2RangeBCD">
<value>0</value>
</feature>
<feature name="PCIEdev2RangeABCD">
<value>0</value>
</feature>
<feature name="cplRngReq">
<value>0</value>
</feature>
<feature name="cplRngReqNow">
<value>0</value>
</feature>
<feature name="PCIEdev2CplDis">
<value>1</value>
</feature>
<feature name="cplDisReq">
<value>0</value>
</feature>
<feature name="cplDisReqNow">
<value>0</value>
</feature>
<feature name="PCIEariSupp">
<value>0</value>
</feature>
<feature name="PCIEiovSRemuEROM">
<value>0</value>
</feature>
<feature name="PCIEds">
<value>0</value>
</feature>
<feature name="PCIEdsOwnNP">
<value>1</value>
</feature>
<feature name="PCIElkSpd2">
<value>1</value>
</feature>
<feature name="PCIElkBandWidth">
<value>1</value>
</feature>
<feature name="PCIElkL07">
<value>0</value>
</feature>
<feature name="PCIElkClkPowMgmt">
<value>0</value>
</feature>
<feature name="PCIElkDnErrRepCap">
<value>0</value>
</feature>
<feature name="PCIElkDlActRepCap">
<value>0</value>
</feature>
<feature name="PCIElcL0s">
<value>1</value>
</feature>
<feature name="PCIElcClkPowMgmt">
<value>0</value>
</feature>
<feature name="PCIElc2">
<value>1</value>
</feature>
<feature name="PCIElc2TgtSpdImpl">
<value>1</value>
</feature>
<feature name="PCIElc2TgtSpd">
<value>0</value>
</feature>
<feature name="PCIElc2EnCompImpl">
<value>1</value>
</feature>
<feature name="PCIElc2HwAutoSpdDisImpl">
<value>1</value>
</feature>
<feature name="PCIElc2SelDeImpl">
<value>1</value>
</feature>
<feature name="PCIElc2TxMarginImpl">
<value>1</value>
</feature>
<feature name="PCIElc2EnModCompImpl">
<value>1</value>
</feature>
<feature name="PCIElc2CompSOSImpl">
<value>1</value>
</feature>
<feature name="PCIElc2CompDeImpl">
<value>1</value>
</feature>
<feature name="PCIEls2">
<value>1</value>
</feature>
<feature name="PCIEls2CurrDeImpl">
<value>1</value>
</feature>
<feature name="PCIEslPowFaultDet">
<value>1</value>
</feature>
<feature name="PCIEslLock">
<value>0</value>
</feature>
<feature name="PCIEslCmdCplSupp">
<value>0</value>
</feature>
<feature name="PCIEscAIC">
<value>0</value>
</feature>
<feature name="PCIEscAICdef">
<value>3</value>
</feature>
<feature name="PCIEscPIC">
<value>0</value>
</feature>
<feature name="PCIEscPICdef">
<value>3</value>
</feature>
<feature name="PCIEscDLE">
<value>0</value>
</feature>
<feature name="PCIEss">
<value>0</value>
</feature>
<feature name="PCIErcCRS">
<value>0</value>
</feature>
<feature name="PCIErcap">
<value>0</value>
</feature>
<feature name="PCIErcapCRS">
<value>0</value>
</feature>
<feature name="PCIEXaeImpTr">
<value>1</value>
</feature>
<feature name="PCIEXaeImpFC">
<value>1</value>
</feature>
<feature name="PCIEXaeImpCA">
<value>1</value>
</feature>
<feature name="PCIEXaeImpRcvrOvf">
<value>1</value>
</feature>
<feature name="PCIEXaeImpEcrc">
<value>1</value>
</feature>
<feature name="PCIEXaeImpRcvr">
<value>1</value>
</feature>
<feature name="PCIEXaeImpSurpDown">
<value>0</value>
</feature>
<feature name="PCIEXaeUMSurpDown">
<value>0</value>
</feature>
<feature name="PCIEXaeUVSurpDown">
<value>1</value>
</feature>
<feature name="PCIEXaeCMrepANF">
<value>1</value>
</feature>
<feature name="PCIEXmfvc">
<value>0</value>
</feature>
<feature name="PCIEXMFVCaddr">
<value>0</value>
</feature>
<feature name="capMFVCPtr">
<value>0</value>
</feature>
<feature name="PCIEXmfvc1">
<value>0</value>
</feature>
<feature name="PCIEXmfvc1Evc">
<value>0</value>
</feature>
<feature name="PCIEXmfvc1LEvc">
<value>0</value>
</feature>
<feature name="PCIEXmfvc1Arb">
<value>0</value>
</feature>
<feature name="PCIEXmfvc2">
<value>0</value>
</feature>
<feature name="PCIEXmfvc2arb1">
<value>0</value>
</feature>
<feature name="PCIEXmfvc2arb2">
<value>0</value>
</feature>
<feature name="PCIEXmfvc2arb4">
<value>0</value>
</feature>
<feature name="PCIEXmfvc2arb8">
<value>0</value>
</feature>
<feature name="PCIEXmfvcARsel">
<value>0</value>
</feature>
<feature name="PCIEXmfvcARloc">
<value>0</value>
</feature>
<feature name="PCIEXmfvcARtab">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR0">
<value>1</value>
</feature>
<feature name="PCIEXmfvcR0FC">
<value>1</value>
</feature>
<feature name="PCIEXmfvcR0FCPHun">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR0FCPH">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR0FCPDun">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR0FCPD">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR0FCNPHun">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR0FCNPH">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR0FCNPDun">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR0FCNPD">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR0FCCPLHun">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR0FCCPLH">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR0FCCPLDun">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR0FCCPLD">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR0Ca">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR0Arb">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR0Arb0">
<value>1</value>
</feature>
<feature name="PCIEXmfvcR0Arb1">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR0Arb2">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR0Arb3">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR0Arb4">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR0Arb5">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR0time">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR0offset">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR0CT">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR0map">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR0sel">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR0tab">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR1">
<value>1</value>
</feature>
<feature name="PCIEXmfvcR1FC">
<value>1</value>
</feature>
<feature name="PCIEXmfvcR1FCPHun">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR1FCPH">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR1FCPDun">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR1FCPD">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR1FCNPHun">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR1FCNPH">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR1FCNPDun">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR1FCNPD">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR1FCCPLHun">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR1FCCPLH">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR1FCCPLDun">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR1FCCPLD">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR1Ca">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR1Arb">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR1Arb0">
<value>1</value>
</feature>
<feature name="PCIEXmfvcR1Arb1">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR1Arb2">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR1Arb3">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR1Arb4">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR1Arb5">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR1time">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR1offset">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR1CT">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR1map">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR1sel">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR1vcID">
<value>1</value>
</feature>
<feature name="PCIEXmfvcR1tab">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR2">
<value>1</value>
</feature>
<feature name="PCIEXmfvcR2FC">
<value>1</value>
</feature>
<feature name="PCIEXmfvcR2FCPHun">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR2FCPH">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR2FCPDun">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR2FCPD">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR2FCNPHun">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR2FCNPH">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR2FCNPDun">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR2FCNPD">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR2FCCPLHun">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR2FCCPLH">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR2FCCPLDun">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR2FCCPLD">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR2Ca">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR2Arb">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR2Arb0">
<value>1</value>
</feature>
<feature name="PCIEXmfvcR2Arb1">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR2Arb2">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR2Arb3">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR2Arb4">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR2Arb5">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR2time">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR2offset">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR2CT">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR2map">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR2sel">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR2vcID">
<value>1</value>
</feature>
<feature name="PCIEXmfvcR2tab">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR3">
<value>1</value>
</feature>
<feature name="PCIEXmfvcR3FC">
<value>1</value>
</feature>
<feature name="PCIEXmfvcR3FCPHun">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR3FCPH">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR3FCPDun">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR3FCPD">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR3FCNPHun">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR3FCNPH">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR3FCNPDun">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR3FCNPD">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR3FCCPLHun">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR3FCCPLH">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR3FCCPLDun">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR3FCCPLD">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR3Ca">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR3Arb">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR3Arb0">
<value>1</value>
</feature>
<feature name="PCIEXmfvcR3Arb1">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR3Arb2">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR3Arb3">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR3Arb4">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR3Arb5">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR3time">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR3offset">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR3CT">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR3map">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR3sel">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR3vcID">
<value>1</value>
</feature>
<feature name="PCIEXmfvcR3tab">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR4">
<value>1</value>
</feature>
<feature name="PCIEXmfvcR4FC">
<value>1</value>
</feature>
<feature name="PCIEXmfvcR4FCPHun">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR4FCPH">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR4FCPDun">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR4FCPD">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR4FCNPHun">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR4FCNPH">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR4FCNPDun">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR4FCNPD">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR4FCCPLHun">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR4FCCPLH">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR4FCCPLDun">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR4FCCPLD">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR4Ca">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR4Arb">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR4Arb0">
<value>1</value>
</feature>
<feature name="PCIEXmfvcR4Arb1">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR4Arb2">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR4Arb3">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR4Arb4">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR4Arb5">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR4time">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR4offset">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR4CT">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR4map">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR4sel">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR4vcID">
<value>1</value>
</feature>
<feature name="PCIEXmfvcR4tab">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR5">
<value>1</value>
</feature>
<feature name="PCIEXmfvcR5FC">
<value>1</value>
</feature>
<feature name="PCIEXmfvcR5FCPHun">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR5FCPH">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR5FCPDun">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR5FCPD">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR5FCNPHun">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR5FCNPH">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR5FCNPDun">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR5FCNPD">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR5FCCPLHun">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR5FCCPLH">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR5FCCPLDun">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR5FCCPLD">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR5Ca">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR5Arb">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR5Arb0">
<value>1</value>
</feature>
<feature name="PCIEXmfvcR5Arb1">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR5Arb2">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR5Arb3">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR5Arb4">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR5Arb5">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR5time">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR5offset">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR5CT">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR5map">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR5sel">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR5vcID">
<value>1</value>
</feature>
<feature name="PCIEXmfvcR5tab">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR6">
<value>1</value>
</feature>
<feature name="PCIEXmfvcR6FC">
<value>1</value>
</feature>
<feature name="PCIEXmfvcR6FCPHun">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR6FCPH">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR6FCPDun">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR6FCPD">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR6FCNPHun">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR6FCNPH">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR6FCNPDun">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR6FCNPD">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR6FCCPLHun">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR6FCCPLH">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR6FCCPLDun">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR6FCCPLD">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR6Ca">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR6Arb">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR6Arb0">
<value>1</value>
</feature>
<feature name="PCIEXmfvcR6Arb1">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR6Arb2">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR6Arb3">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR6Arb4">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR6Arb5">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR6time">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR6offset">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR6CT">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR6map">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR6sel">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR6vcID">
<value>1</value>
</feature>
<feature name="PCIEXmfvcR6tab">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR7">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR7FC">
<value>1</value>
</feature>
<feature name="PCIEXmfvcR7FCPHun">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR7FCPH">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR7FCPDun">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR7FCPD">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR7FCNPHun">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR7FCNPH">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR7FCNPDun">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR7FCNPD">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR7FCCPLHun">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR7FCCPLH">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR7FCCPLDun">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR7FCCPLD">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR7Ca">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR7Arb">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR7Arb0">
<value>1</value>
</feature>
<feature name="PCIEXmfvcR7Arb1">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR7Arb2">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR7Arb3">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR7Arb4">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR7Arb5">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR7time">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR7offset">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR7CT">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR7map">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR7sel">
<value>0</value>
</feature>
<feature name="PCIEXmfvcR7vcID">
<value>1</value>
</feature>
<feature name="PCIEXmfvcR7tab">
<value>0</value>
</feature>
<feature name="PCIEXrclk">
<value>0</value>
</feature>
<feature name="PCIEXRCLKaddr">
<value>0</value>
</feature>
<feature name="capRCLKPtr">
<value>0</value>
</feature>
<feature name="PCIEXrclkType">
<value>1</value>
</feature>
<feature name="PCIEXrclkTypeCfg">
<value>1</value>
</feature>
<feature name="PCIEXrclkTypeMem">
<value>0</value>
</feature>
<feature name="PCIEXrclkTypeLK">
<value>0</value>
</feature>
<feature name="PCIEXrclkNumLK">
<value>1</value>
</feature>
<feature name="PCIEXrclkCompID">
<value>1</value>
</feature>
<feature name="PCIEXrclkPortNum">
<value>0</value>
</feature>
<feature name="PCIEXrclkLK0">
<value>1</value>
</feature>
<feature name="PCIEXrclkLK0Valid">
<value>1</value>
</feature>
<feature name="PCIEXrclkLK0Type">
<value>1</value>
</feature>
<feature name="PCIEXrclkLK0RCRB">
<value>0</value>
</feature>
<feature name="PCIEXrclkLK0CompID">
<value>1</value>
</feature>
<feature name="PCIEXrclkLK0PortNum">
<value>0</value>
</feature>
<feature name="PCIEXrclkLK0AddrLow">
<value>0</value>
</feature>
<feature name="PCIEXrclkLK0AddrHigh">
<value>0</value>
</feature>
<feature name="PCIEXrclkLKOther">
<value>0</value>
</feature>
<feature name="PCIEXrclc">
<value>0</value>
</feature>
<feature name="PCIEXRCLCaddr">
<value>0</value>
</feature>
<feature name="capRCLCPtr">
<value>0</value>
</feature>
<feature name="PCIEXrclcWidth">
<value>1</value>
</feature>
<feature name="PCIEXrclcAspm">
<value>1</value>
</feature>
<feature name="PCIEXrclcL0s">
<value>1</value>
</feature>
<feature name="PCIEXrclcL1">
<value>1</value>
</feature>
<feature name="PCIEXrclcL0sExit">
<value>1</value>
</feature>
<feature name="PCIEXrclcL0sExit0">
<value>1</value>
</feature>
<feature name="PCIEXrclcL0sExit1">
<value>0</value>
</feature>
<feature name="PCIEXrclcL0sExit2">
<value>0</value>
</feature>
<feature name="PCIEXrclcL0sExit3">
<value>0</value>
</feature>
<feature name="PCIEXrclcL0sExit4">
<value>0</value>
</feature>
<feature name="PCIEXrclcL0sExit5">
<value>0</value>
</feature>
<feature name="PCIEXrclcL0sExit6">
<value>0</value>
</feature>
<feature name="PCIEXrclcL0sExit7">
<value>0</value>
</feature>
<feature name="PCIEXrclcL1Exit">
<value>1</value>
</feature>
<feature name="PCIEXrclcL1Exit0">
<value>1</value>
</feature>
<feature name="PCIEXrclcL1Exit1">
<value>0</value>
</feature>
<feature name="PCIEXrclcL1Exit2">
<value>0</value>
</feature>
<feature name="PCIEXrclcL1Exit3">
<value>0</value>
</feature>
<feature name="PCIEXrclcL1Exit4">
<value>0</value>
</feature>
<feature name="PCIEXrclcL1Exit5">
<value>0</value>
</feature>
<feature name="PCIEXrclcL1Exit6">
<value>0</value>
</feature>
<feature name="PCIEXrclcL1Exit7">
<value>0</value>
</feature>
<feature name="PCIEXrcec">
<value>0</value>
</feature>
<feature name="PCIEXRCECaddr">
<value>0</value>
</feature>
<feature name="capRCECPtr">
<value>0</value>
</feature>
<feature name="PCIEXrcecMap">
<value>0</value>
</feature>
<feature name="PCIEXRCRB">
<value>0</value>
</feature>
<feature name="PCIEXRCRBaddr">
<value>0</value>
</feature>
<feature name="capRCRBPtr">
<value>0</value>
</feature>
<feature name="PCIEXvcR0FCPHun">
<value>0</value>
</feature>
<feature name="PCIEXvcR0FCPDun">
<value>0</value>
</feature>
<feature name="PCIEXvcR0FCNPHun">
<value>0</value>
</feature>
<feature name="PCIEXvcR0FCNPDun">
<value>0</value>
</feature>
<feature name="PCIEXvcR0FCCPLHun">
<value>0</value>
</feature>
<feature name="PCIEXvcR0FCCPLDun">
<value>0</value>
</feature>
<feature name="PCIEXvcR0offset">
<value>0</value>
</feature>
<feature name="PCIEXvcR0pend">
<value>0</value>
</feature>
<feature name="PCIEXvcR1FCPHun">
<value>0</value>
</feature>
<feature name="PCIEXvcR1FCPDun">
<value>0</value>
</feature>
<feature name="PCIEXvcR1FCNPHun">
<value>0</value>
</feature>
<feature name="PCIEXvcR1FCNPDun">
<value>0</value>
</feature>
<feature name="PCIEXvcR1FCCPLHun">
<value>0</value>
</feature>
<feature name="PCIEXvcR1FCCPLDun">
<value>0</value>
</feature>
<feature name="PCIEXvcR1offset">
<value>0</value>
</feature>
<feature name="PCIEXvcR2FCPHun">
<value>0</value>
</feature>
<feature name="PCIEXvcR2FCPDun">
<value>0</value>
</feature>
<feature name="PCIEXvcR2FCNPHun">
<value>0</value>
</feature>
<feature name="PCIEXvcR2FCNPDun">
<value>0</value>
</feature>
<feature name="PCIEXvcR2FCCPLHun">
<value>0</value>
</feature>
<feature name="PCIEXvcR2FCCPLDun">
<value>0</value>
</feature>
<feature name="PCIEXvcR2offset">
<value>0</value>
</feature>
<feature name="PCIEXvcR3FCPHun">
<value>0</value>
</feature>
<feature name="PCIEXvcR3FCPDun">
<value>0</value>
</feature>
<feature name="PCIEXvcR3FCNPHun">
<value>0</value>
</feature>
<feature name="PCIEXvcR3FCNPDun">
<value>0</value>
</feature>
<feature name="PCIEXvcR3FCCPLHun">
<value>0</value>
</feature>
<feature name="PCIEXvcR3FCCPLDun">
<value>0</value>
</feature>
<feature name="PCIEXvcR3offset">
<value>0</value>
</feature>
<feature name="PCIEXvcR4FCPHun">
<value>0</value>
</feature>
<feature name="PCIEXvcR4FCPDun">
<value>0</value>
</feature>
<feature name="PCIEXvcR4FCNPHun">
<value>0</value>
</feature>
<feature name="PCIEXvcR4FCNPDun">
<value>0</value>
</feature>
<feature name="PCIEXvcR4FCCPLHun">
<value>0</value>
</feature>
<feature name="PCIEXvcR4FCCPLDun">
<value>0</value>
</feature>
<feature name="PCIEXvcR4offset">
<value>0</value>
</feature>
<feature name="PCIEXvcR5FCPHun">
<value>0</value>
</feature>
<feature name="PCIEXvcR5FCPDun">
<value>0</value>
</feature>
<feature name="PCIEXvcR5FCNPHun">
<value>0</value>
</feature>
<feature name="PCIEXvcR5FCNPDun">
<value>0</value>
</feature>
<feature name="PCIEXvcR5FCCPLHun">
<value>0</value>
</feature>
<feature name="PCIEXvcR5FCCPLDun">
<value>0</value>
</feature>
<feature name="PCIEXvcR5offset">
<value>0</value>
</feature>
<feature name="PCIEXvcR6FCPHun">
<value>0</value>
</feature>
<feature name="PCIEXvcR6FCPDun">
<value>0</value>
</feature>
<feature name="PCIEXvcR6FCNPHun">
<value>0</value>
</feature>
<feature name="PCIEXvcR6FCNPDun">
<value>0</value>
</feature>
<feature name="PCIEXvcR6FCCPLHun">
<value>0</value>
</feature>
<feature name="PCIEXvcR6FCCPLDun">
<value>0</value>
</feature>
<feature name="PCIEXvcR6offset">
<value>0</value>
</feature>
<feature name="PCIEXvcR7FCPHun">
<value>0</value>
</feature>
<feature name="PCIEXvcR7FCPDun">
<value>0</value>
</feature>
<feature name="PCIEXvcR7FCNPHun">
<value>0</value>
</feature>
<feature name="PCIEXvcR7FCNPDun">
<value>0</value>
</feature>
<feature name="PCIEXvcR7FCCPLHun">
<value>0</value>
</feature>
<feature name="PCIEXvcR7FCCPLDun">
<value>0</value>
</feature>
<feature name="PCIEXvcR7offset">
<value>0</value>
</feature>
<feature name="PCIEXpbDarr">
<value>0</value>
</feature>
<feature name="PCIEXvsec">
<value>0</value>
</feature>
<feature name="PCIEXvsecDef">
<value />
</feature>
<feature name="Ats">
<value>0</value>
</feature>
<feature name="AtsITag">
<value>0</value>
</feature>
<feature name="AtsITagGlobal">
<value>0</value>
</feature>
<feature name="AtsITagPerDevice">
<value>0</value>
</feature>
<feature name="AtsStu">
<value>0</value>
</feature>
<feature name="AtsCap">
<value>0</value>
</feature>
<feature name="AtsAddr">
<value>0</value>
</feature>
<feature name="AtsNextPtr">
<value>0</value>
</feature>
<feature name="AtsInvQDepth">
<value>0</value>
</feature>
<feature name="PCIEACS">
<value>0</value>
</feature>
<feature name="PCIEACSaddr">
<value>0</value>
</feature>
<feature name="capACSPtr">
<value>0</value>
</feature>
<feature name="PCIEACSver">
<value>1</value>
</feature>
<feature name="PCIEACSsrcValid">
<value>1</value>
</feature>
<feature name="PCIEACStranBlock">
<value>1</value>
</feature>
<feature name="PCIEACSp2pReqRedirect">
<value>1</value>
</feature>
<feature name="PCIEACSp2pCplRedirect">
<value>1</value>
</feature>
<feature name="PCIEACSupForward">
<value>1</value>
</feature>
<feature name="PCIEACSp2pEctrl">
<value>1</value>
</feature>
<feature name="PCIEACSdirTranP2p">
<value>1</value>
</feature>
<feature name="PCIEACSEctrlSize">
<value>1</value>
</feature>
<feature name="PCIEariCap">
<value>0</value>
</feature>
<feature name="PCIEariAddr">
<value>0</value>
</feature>
<feature name="PCIEariPtr">
<value>0</value>
</feature>
<feature name="PCIEariVer">
<value>1</value>
</feature>
<feature name="PCIEariMFVCcap">
<value>0</value>
</feature>
<feature name="PCIEariACScap">
<value>0</value>
</feature>
<feature name="PCIEariNextFunc">
<value>0</value>
</feature>
<feature name="PCIEiovSRcap">
<value>0</value>
</feature>
<feature name="PCIEiovSRaddr">
<value>0</value>
</feature>
<feature name="PCIEiovSRptr">
<value>0</value>
</feature>
<feature name="PCIEiovSRver">
<value>1</value>
</feature>
<feature name="PCIEiovSRmigCap">
<value>0</value>
</feature>
<feature name="PCIEiovSRinitialVF">
<value>0</value>
</feature>
<feature name="PCIEiovSRtotalVF">
<value>0</value>
</feature>
<feature name="PCIEiovSRfuncDepLink">
<value>0</value>
</feature>
<feature name="PCIEiovSRVFoffset">
<value>0</value>
</feature>
<feature name="PCIEiovSRVFstride">
<value>1</value>
</feature>
<feature name="PCIEiovSRVFdeviceID">
<value>0</value>
</feature>
<feature name="PCIEiovSRpageSize">
<value>0</value>
</feature>
<feature name="PCIEiovSRmig">
<value>0</value>
</feature>
<feature name="PCIEiovSRmigOffset">
<value>0</value>
</feature>
<feature name="PCIEiovSRmigBIR">
<value>0</value>
</feature>
<feature name="PCIEiovSRbar0impl">
<value>0</value>
</feature>
<feature name="PCIEiovSRbar0width">
<value>32</value>
</feature>
<feature name="PCIEiovSRbar0size">
<value>12</value>
</feature>
<feature name="PCIEiovSRbar0Pref">
<value>0</value>
</feature>
<feature name="PCIEiovSRbar1impl">
<value>0</value>
</feature>
<feature name="PCIEiovSRbar1width">
<value>32</value>
</feature>
<feature name="PCIEiovSRbar1size">
<value>12</value>
</feature>
<feature name="PCIEiovSRbar1Pref">
<value>0</value>
</feature>
<feature name="PCIEiovSRbar2impl">
<value>0</value>
</feature>
<feature name="PCIEiovSRbar2width">
<value>32</value>
</feature>
<feature name="PCIEiovSRbar2size">
<value>12</value>
</feature>
<feature name="PCIEiovSRbar2Pref">
<value>0</value>
</feature>
<feature name="PCIEiovSRbar3impl">
<value>0</value>
</feature>
<feature name="PCIEiovSRbar3width">
<value>32</value>
</feature>
<feature name="PCIEiovSRbar3size">
<value>12</value>
</feature>
<feature name="PCIEiovSRbar3Pref">
<value>0</value>
</feature>
<feature name="PCIEiovSRbar4impl">
<value>0</value>
</feature>
<feature name="PCIEiovSRbar4width">
<value>32</value>
</feature>
<feature name="PCIEiovSRbar4size">
<value>12</value>
</feature>
<feature name="PCIEiovSRbar4Pref">
<value>0</value>
</feature>
<feature name="PCIEiovSRbar5impl">
<value>0</value>
</feature>
<feature name="PCIEiovSRbar5width">
<value>32</value>
</feature>
<feature name="PCIEiovSRbar5size">
<value>12</value>
</feature>
<feature name="PCIEiovSRbar5Pref">
<value>0</value>
</feature>
<pin name="Rate">
<username>Rate</username>
<bits>1</bits>
</pin>
<pin name="TxDeemph">
<username>TxDeemph</username>
<bits>1</bits>
</pin>
<pin name="TxMargin">
<username>TxMargin</username>
<bits>3</bits>
</pin>
<pin name="TxSwing">
<username>TxSwing</username>
<bits>1</bits>
</pin>
</functionality>
<timing>
<timing.set default="yes" name="default">
<timing.parm name="ttoPollSpeed">
<value>400.12 ps</value>
</timing.parm>
<timing.parm name="ttoCfgLnWaitUp">
<value>2 ms</value>
</timing.parm>
<timing.parm name="ttoCfgLnWaitDn">
<value>2 ms</value>
</timing.parm>
<timing.parm name="ttoPollConfig">
<value>48 ms</value>
</timing.parm>
<timing.parm name="ttoPollActive">
<value>2 us</value>
</timing.parm>
<timing.parm name="ttoDetectQuiet">
<value>400 ns</value>
</timing.parm>
<timing.parm name="ttoDetectActive">
<value>200 ns</value>
</timing.parm>
<timing.parm name="ttoCfgLkStartDn">
<value>24 ms</value>
</timing.parm>
<timing.parm name="ttoCfgLkStartUp">
<value>24 ms</value>
</timing.parm>
<timing.parm name="ttoCfgCompDn">
<value>2 ms</value>
</timing.parm>
<timing.parm name="ttoCfgCompUp">
<value>24 ms</value>
</timing.parm>
<timing.parm name="ttoCfgLkAcceptDn">
<value>2 ms</value>
</timing.parm>
<timing.parm name="ttoCfgLkAcceptUp">
<value>2 ms</value>
</timing.parm>
<timing.parm name="ttoCfgIdle">
<value>2 ms</value>
</timing.parm>
<timing.parm name="ttoRcvrCfg">
<value>48 ms</value>
</timing.parm>
<timing.parm name="ttoRcvrLock">
<value>24 ms</value>
</timing.parm>
<timing.parm name="ttoRcvrIdle">
<value>2 ms</value>
</timing.parm>
<timing.parm name="ttoDisabled">
<value>2 ms</value>
</timing.parm>
<timing.parm name="ttoHotReset">
<value>2 ms</value>
</timing.parm>
<timing.parm name="ttoLoopback">
<value>2 ms</value>
</timing.parm>
<timing.parm name="ttoTLCpl">
<value>5000 ns</value>
</timing.parm>
<timing.parm name="ttxUImin">
<value>399.88 ps</value>
</timing.parm>
<timing.parm name="ttxUImax">
<value>400.12 ps</value>
</timing.parm>
<timing.parm name="ttxIDLEmin">
<value>50 clk</value>
</timing.parm>
<timing.parm name="ttxSetToIDLEmax">
<value>20 clk</value>
</timing.parm>
<timing.parm name="ttxLaneSKEWmax">
<value>1300 ps</value>
</timing.parm>
<timing.parm name="ttxCxLKmin">
<value>0 ms</value>
</timing.parm>
<timing.parm name="ttxCxLKmax">
<value>1 ms</value>
</timing.parm>
<timing.parm name="trxUImin">
<value>399.88 ps</value>
</timing.parm>
<timing.parm name="trxUImax">
<value>400.12 ps</value>
</timing.parm>
<timing.parm name="trxSetToDetectmax">
<value>10 ms</value>
</timing.parm>
<timing.parm name="trxTotalSKEWmax">
<value>20 ns</value>
</timing.parm>
<timing.parm name="ttoFcInitRollover" enabled="no" />
<timing.parm name="ttxIdleToDiff" enabled="no" />
<timing.parm name="ttoResetTOCfg" enabled="no">
<value>100 ms</value>
</timing.parm>
<timing.parm name="ttoResetTODetect" enabled="no">
<value>20 ms</value>
</timing.parm>
<timing.parm name="ttoLoopbackEntry" enabled="no">
<value>100 ms</value>
</timing.parm>
<timing.parm name="ttoLoopbackEntry2Active" enabled="no">
<value>2 ms</value>
</timing.parm>
<timing.parm name="ttoLoopbackEntryEIMaster" enabled="no">
<value>2 ms</value>
</timing.parm>
<timing.parm name="ttoLoopbackEntryEISlave" enabled="no">
<value>1 ms</value>
</timing.parm>
<timing.parm name="ttoTLCplRx" enabled="no">
<value>0 us</value>
</timing.parm>
<timing.parm name="ttoFCmin" enabled="no">
<value>200 us</value>
</timing.parm>
<timing.parm name="ttoFCmax" enabled="no">
<value>300 us</value>
</timing.parm>
<timing.parm name="ttoPMEmin" enabled="no">
<value>95 ms</value>
</timing.parm>
<timing.parm name="ttoPMEmax" enabled="no">
<value>150 ms</value>
</timing.parm>
<timing.parm name="ttoL0smax" enabled="no">
<value>7 us</value>
</timing.parm>
<timing.parm name="ttoL0smin" enabled="no">
<value>7 us</value>
</timing.parm>
<timing.parm name="ttoL1min" enabled="no">
<value>0 us</value>
</timing.parm>
<timing.parm name="ttoL1max" enabled="no">
<value>0 us</value>
</timing.parm>
<timing.parm name="ttoL1aspmmin" enabled="no">
<value>20 us</value>
</timing.parm>
<timing.parm name="ttoL1aspmmax" enabled="no">
<value>20 us</value>
</timing.parm>
<timing.parm name="ttoTurnOffmax" enabled="no">
<value>20 us</value>
</timing.parm>
<timing.parm name="ttoPMmax" enabled="no">
<value>1 s</value>
</timing.parm>
<timing.parm name="ttoD3hot2D0max" enabled="no">
<value>10 ms</value>
</timing.parm>
<timing.parm name="ttoPMHSmax" enabled="no">
<value>10 ms</value>
</timing.parm>
<timing.parm name="ttoCRSmax" enabled="no">
<value>400 ps</value>
</timing.parm>
<timing.parm name="ttoSysInit" enabled="no">
<value>0 ms</value>
</timing.parm>
<timing.parm name="ttoPReqAccLimit" enabled="no">
<value>10 us</value>
</timing.parm>
<timing.parm name="ttoHPCmdMax" enabled="no">
<value>1 s</value>
</timing.parm>
<timing.parm name="ttoHPCmdMin" enabled="no">
<value>50 ns</value>
</timing.parm>
<timing.parm name="ttoPCLKmarginMax" enabled="no">
<value>100 ps</value>
</timing.parm>
<timing.parm name="ttoInferEIRcvrCfg2_5" enabled="no">
<value>1280 clk</value>
</timing.parm>
<timing.parm name="ttoInferEIRcvrCfg5_0" enabled="no">
<value>1280 clk</value>
</timing.parm>
<timing.parm name="ttoInferEISpeed2_5" enabled="no">
<value>1280 clk</value>
</timing.parm>
<timing.parm name="ttoInferEISpeed5_0" enabled="no">
<value>1280 clk</value>
</timing.parm>
<timing.parm name="ttoInferEIExitSpeed2_5" enabled="no">
<value>2000 clk</value>
</timing.parm>
<timing.parm name="ttoInferEIExitSpeed5_0" enabled="no">
<value>16000 clk</value>
</timing.parm>
<timing.parm name="ttoInL1N2_5Min" enabled="no">
<value>40 ns</value>
</timing.parm>
<timing.parm name="ttoRecSpeedSuccTxEiMin" enabled="no">
<value>2000 clk</value>
</timing.parm>
<timing.parm name="ttoRecSpeedTxEiMin" enabled="no">
<value>6 us</value>
</timing.parm>
<timing.parm name="ttoRecSpeedTxEiMax" enabled="no">
<value>1 ms</value>
</timing.parm>
<timing.parm name="ttoRecSpeed" enabled="no">
<value>48 ms</value>
</timing.parm>
<timing.parm name="ttoPollCompTxEiMin" enabled="no">
<value>1 ms</value>
</timing.parm>
<timing.parm name="ttoPollCompTxEiMax" enabled="no">
<value>2 ms</value>
</timing.parm>
<timing.parm name="ttoUpconfig" enabled="no">
<value>1 ms</value>
</timing.parm>
<timing.parm name="ttoFLRmax" enabled="no">
<value>100 ms</value>
</timing.parm>
<timing.parm name="ttoFLRmin" enabled="no">
<value>100 ms</value>
</timing.parm>
<timing.parm name="ttoFLRInit" enabled="no">
<value>0 ms</value>
</timing.parm>
<timing.parm name="ttoIOVinit" enabled="no">
<value>0 ms</value>
</timing.parm>
<timing.parm name="ttxIdleToValid" enabled="no">
<value>20 clk</value>
</timing.parm>
<timing.parm name="ttxReceiverDetect" enabled="no">
<value>0 clk</value>
</timing.parm>
<timing.parm name="ttxFCmin" enabled="no">
<value>30 us</value>
</timing.parm>
<timing.parm name="ttxFCmax" enabled="no">
<value>45 us</value>
</timing.parm>
<timing.parm name="ttxFCESmin" enabled="no">
<value>120 us</value>
</timing.parm>
<timing.parm name="ttxFCESmax" enabled="no">
<value>180 us</value>
</timing.parm>
<timing.parm name="ttxFCL1exitMax" enabled="no">
<value>1 us</value>
</timing.parm>
<timing.parm name="ttxTurnOffMin" enabled="no">
<value>1 ms</value>
</timing.parm>
<timing.parm name="ttxTurnOffMax" enabled="no">
<value>10 ms</value>
</timing.parm>
<timing.parm name="ttxPwrOffMin" enabled="no">
<value>100 ns</value>
</timing.parm>
<timing.parm name="ttx2L1aspmMin" enabled="no">
<value>10 us</value>
</timing.parm>
<timing.parm name="ttx2L1aspmUpMin" enabled="no">
<value>9.5 us</value>
</timing.parm>
<timing.parm name="ttxReadyMax" enabled="no">
<value>0 ns</value>
</timing.parm>
<timing.parm name="ttxPcie2UImin" enabled="no">
<value>199.94 ps</value>
</timing.parm>
<timing.parm name="ttxPcie2UImax" enabled="no">
<value>200.06 ps</value>
</timing.parm>
<timing.parm name="ttxG2DetectQuietMin" enabled="no">
<value>1 ms</value>
</timing.parm>
<timing.parm name="trxPcie2UImin" enabled="no">
<value>199.94 ps</value>
</timing.parm>
<timing.parm name="trxPcie2UImax" enabled="no">
<value>200.06 ps</value>
</timing.parm>
<timing.parm name="trxInferEImax" enabled="no">
<value>128 us</value>
</timing.parm>
<timing.parm name="trxInferClkEIsuccmax" enabled="no">
<value>1280 clk</value>
</timing.parm>
<timing.parm name="trxInferClkEImax" enabled="no">
<value>16000 clk</value>
</timing.parm>
<timing.parm name="ttxPhyLatency" enabled="no">
<value>1 clk</value>
</timing.parm>
<timing.parm name="trxPhyLatency" enabled="no">
<value>1 clk</value>
</timing.parm>
<timing.parm name="ttxBeaconMax" enabled="no">
<value>10 ns</value>
</timing.parm>
<timing.parm name="ttxBeaconMin" enabled="no">
<value>1 ns</value>
</timing.parm>
<timing.parm name="trxBeaconMax" enabled="no">
<value>10 ns</value>
</timing.parm>
<timing.parm name="trxBeaconMin" enabled="no">
<value>0 ns</value>
</timing.parm>
<timing.parm name="trxElecIdleMax" enabled="no">
<value>10 ns</value>
</timing.parm>
<timing.parm name="trxElecIdleMin" enabled="no">
<value>1 ns</value>
</timing.parm>
<timing.parm name="ttxDetectRxMax" enabled="no">
<value>10 ns</value>
</timing.parm>
<timing.parm name="ttxDetectRxMin" enabled="no">
<value>1 ns</value>
</timing.parm>
<timing.parm name="trxPhyLockMax" enabled="no">
<value>1 us</value>
</timing.parm>
<timing.parm name="trxPhyLockMin" enabled="no">
<value>0 us</value>
</timing.parm>
<timing.parm name="ttxSymLockSkipSet" enabled="no">
<value>0 clk</value>
</timing.parm>
<timing.parm name="tP0ToP0sMax" enabled="no">
<value>0 clk</value>
</timing.parm>
<timing.parm name="tP0ToP0sMin" enabled="no">
<value>0 clk</value>
</timing.parm>
<timing.parm name="tP0ToP1Max" enabled="no">
<value>0 clk</value>
</timing.parm>
<timing.parm name="tP0ToP1Min" enabled="no">
<value>0 clk</value>
</timing.parm>
<timing.parm name="tP0ToP2Max" enabled="no">
<value>0 clk</value>
</timing.parm>
<timing.parm name="tP0ToP2Min" enabled="no">
<value>0 clk</value>
</timing.parm>
<timing.parm name="tP0sToP0Max" enabled="no">
<value>0 clk</value>
</timing.parm>
<timing.parm name="tP0sToP0Min" enabled="no">
<value>0 clk</value>
</timing.parm>
<timing.parm name="tP1ToP0Max" enabled="no">
<value>0 clk</value>
</timing.parm>
<timing.parm name="tP1ToP0Min" enabled="no">
<value>0 clk</value>
</timing.parm>
<timing.parm name="tP2ToP1Max" enabled="no">
<value>10 ns</value>
</timing.parm>
<timing.parm name="tP2ToP1Min" enabled="no">
<value>1 ns</value>
</timing.parm>
<timing.parm name="tP2ShutdownMax" enabled="no">
<value>100 ns</value>
</timing.parm>
<timing.parm name="tP2ShutdownMin" enabled="no">
<value>1 ns</value>
</timing.parm>
<timing.parm name="tP1StartupMax" enabled="no">
<value>100 ns</value>
</timing.parm>
<timing.parm name="tP1StartupMin" enabled="no">
<value>1 ns</value>
</timing.parm>
<timing.parm name="tResetToReadyMax" enabled="no">
<value>100 ns</value>
</timing.parm>
<timing.parm name="tResetToReadyMin" enabled="no">
<value>1 ns</value>
</timing.parm>
<timing.parm name="ttxPCLKToDataValidMax" enabled="no">
<value>1 ns</value>
</timing.parm>
<timing.parm name="ttxPCLKToDataValidMin" enabled="no">
<value>0 ns</value>
</timing.parm>
<timing.parm name="trxPCLKSetupMax" enabled="no">
<value>1 ns</value>
</timing.parm>
<timing.parm name="trxPCLKHoldMin" enabled="no">
<value>0 ns</value>
</timing.parm>
<timing.parm name="ttxResetToOutputMax" enabled="no">
<value>1 ns</value>
</timing.parm>
<timing.parm name="ttxResetToOutputMin" enabled="no">
<value>0 ns</value>
</timing.parm>
<timing.parm name="ttxAsyncPhyStatusMax" enabled="no">
<value>1 ns</value>
</timing.parm>
<timing.parm name="ttxAsyncPhyStatusMin" enabled="no">
<value>0 ns</value>
</timing.parm>
<timing.parm name="ttxDataRateChangeMin" enabled="no">
<value>4 ns</value>
</timing.parm>
<timing.parm name="ttxDataRateChange2Min" enabled="no">
<value>4 ns</value>
</timing.parm>
</timing.set>
</timing>
</part>
</soma>
Full OpenSPARC design & verification tarball including full HDL.