verif/env/ilu_peu/vera/csrtool/csr_define.vri

// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T2 Processor File: csr_define.vri
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// ========== Copyright Header End ============================================
#ifndef CSR_DEFINE
#define CSR_DEFINE

#define FIRE_CSRBUS_DATA_WIDTH  64
#define FIRE_CSRBUS_ADDR_WIDTH  27

//----- Source bus encodings
#define FIRE_CSRBUS_SRC_BUS_ENC_JTAG    2'b00
#define FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW        2'b01
#define FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED 2'b10
#define FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST        2'b11

#define BOOLEAN bit

#define ZEROS 64'b0

#define CSR_CHECK_DISABLED 0
#define CSR_CHECK_ENABLED  1


#define CSR_ALL_OUTPUT_MSG_DISABLED             0
#define CSR_ERROR_MSG_ONLY_ENABLED              1
#define CSR_WARNING_MSG_ENABLED                 2
#define CSR_COLLECTION_LEVEL_MSG_ENABLED        3
#define CSR_ACCESSOR_LEVEL_MSG_ENABLED          4
#define CSR_ALL_OUTPUT_MSG_ENABLED              5

#define CSR_SUCCESSFUL_RETURN_CODE              0
#define CSR_MISMATCH_RETURN_CODE                1

#define ADDR_OFFSET_WIDTH                       64
#define MODE_WIDTH                              64

#define NO_ACCESS                               0
#define READ_ACCESS                             1
#define FULL_ACCESS                             3

//access mode bits
#define ZERO_TIME_ACCESS                        0
#define CSR_DIAG_MODE                           1
#endif