Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / env / ios / vera / ras / include / ios_rasmon.if.vrhpal
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//
// OpenSPARC T2 Processor File: ios_rasmon.if.vrhpal
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#ifndef INC__IOS_RASMON_IF_VRH
#define INC__IOS_RASMON_IF_VRH
#include "top_defines.vrh"
interface sio_niu_err_mon {
input clk CLOCK verilog_node "`CPU.sio.iol2clk";
input req PSAMPLE #-3 verilog_node "`CPU.sio_niu_hdr_vld";
input [127:0] data PSAMPLE #-3 verilog_node "`CPU.sio_niu_data";
input [7:0] parity PSAMPLE #-3 verilog_node "`CPU.sio_niu_parity";
input ctag_ce PSAMPLE #-3 verilog_node "`CPU.niu_ncu_ctag_ce";
input ctag_ue PSAMPLE #-3 verilog_node "`CPU.niu_ncu_ctag_ue";
input d_pe PSAMPLE #-3 verilog_node "`CPU.niu_ncu_d_pe";
}
interface sio_dmu_err_mon {
input clk CLOCK verilog_node "`CPU.sio.iol2clk";
input req PSAMPLE #-3 verilog_node "`CPU.sio_dmu_hdr_vld";
input [127:0] data PSAMPLE #-3 verilog_node "`CPU.sio_dmu_data";
input [7:0] parity PSAMPLE #-3 verilog_node "`CPU.sio_dmu_parity";
input ctag_ce PSAMPLE #-3 verilog_node "`CPU.dmu_ncu_ctag_ce";
input ctag_ue PSAMPLE #-3 verilog_node "`CPU.dmu_ncu_ctag_ue";
input d_pe PSAMPLE #-3 verilog_node "`CPU.dmu_ncu_d_pe";
}
interface ncu_cpx_err_mon {
input clk CLOCK verilog_node "`NCU.l2clk";
input [7:0] req PSAMPLE #-3 verilog_node "`NCU.ncu_cpx_req_cq";
input [145:0] data PSAMPLE #-3 verilog_node "`NCU.ncu_cpx_data_ca";
}
#endif