verif/env/ios/vera/ras/include/ios_rasmon_ports_binds.vrhpal

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//
// OpenSPARC T2 Processor File: ios_rasmon_ports_binds.vrhpal
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#ifndef INC__IOS_RASMON_PORTS_BINDS_VRH
#define INC__IOS_RASMON_PORTS_BINDS_VRH

port sioniu_errmon_port {
        clk;
        req;
        data;
        parity;
        ctag_ce;
        ctag_ue;
        d_pe;
}

bind sioniu_errmon_port sioniu_errmon_bind {
        clk             sio_niu_err_mon.clk;
        req             sio_niu_err_mon.req;
        data            sio_niu_err_mon.data;
        parity          sio_niu_err_mon.parity;
        ctag_ce         sio_niu_err_mon.ctag_ce;
        ctag_ue         sio_niu_err_mon.ctag_ue;
        d_pe            sio_niu_err_mon.d_pe;
}

port siodmu_errmon_port {
        clk;
        req;
        data;
        parity;
        ctag_ce;
        ctag_ue;
        d_pe;
}

bind siodmu_errmon_port siodmu_errmon_bind {
        clk             sio_dmu_err_mon.clk;
        req             sio_dmu_err_mon.req;
        data            sio_dmu_err_mon.data;
        parity          sio_dmu_err_mon.parity;
        ctag_ce         sio_dmu_err_mon.ctag_ce;
        ctag_ue         sio_dmu_err_mon.ctag_ue;
        d_pe            sio_dmu_err_mon.d_pe;
}

port ncucpx_errmon_port {
        clk;
        req;
        data;
}

bind ncucpx_errmon_port ncucpx_errmon_bind {
        clk             ncu_cpx_err_mon.clk;
        req             ncu_cpx_err_mon.req;
        data            ncu_cpx_err_mon.data;
}

#endif