verif/env/niu/rxc_sat/vera/monitor/include/control_fifo_mon.vri

// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T2 Processor File: control_fifo_mon.vri
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
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// ========== Copyright Header End ============================================
#ifndef __CONTROL_FIFO_MON_VRI__
#define __CONTROL_FIFO_MON_VRI__

#include "neptune_defines.vri"
#define RXC_CK_IN_TIMING PSAMPLE #-1
#define RXC_CK_OUT_TIMING PHOLD #0
#define RXC_CK_CLK_TIMING  CLOCK

#ifdef MAC_SAT
#else
#ifdef NIU_GATE
interface dmc_zcp_port0_if{
  input [129:0] control_fifo_data               RXC_CK_IN_TIMING verilog_node TOP.cpu.rtx.zcp_dmc_dat0";
  input         control_fifo_ful_pkt            RXC_CK_IN_TIMING verilog_node TOP.cpu.rtx.zcp_dmc_ful_pkt0";
  //input               control_fifo_empty              RXC_CK_IN_TIMING verilog_node RXC_DUV_PATH.zcp_dmc_emp0";
  input         control_fifo_err                RXC_CK_IN_TIMING verilog_node TOP.cpu.rtx.zcp_dmc_dat_err0";
  input         control_fifo_ack                RXC_CK_IN_TIMING verilog_node TOP.cpu.rtx.zcp_dmc_ack0";

  output        control_fifo_req                RXC_CK_OUT_TIMING verilog_node TOP.cpu.rtx.dmc_zcp_req0";

  input         clk                             RXC_CK_CLK_TIMING verilog_node TOP.cpu.rtx.iol2clk";
}

interface dmc_zcp_port1_if{
  input [129:0] control_fifo_data               RXC_CK_IN_TIMING verilog_node TOP.cpu.rtx.zcp_dmc_dat1";
  input         control_fifo_ful_pkt            RXC_CK_IN_TIMING verilog_node TOP.cpu.rtx.zcp_dmc_ful_pkt1";
  //input               control_fifo_empty              RXC_CK_IN_TIMING verilog_node RXC_DUV_PATH.zcp_dmc_emp1";
  input         control_fifo_err                RXC_CK_IN_TIMING verilog_node TOP.cpu.rtx.zcp_dmc_dat_err1";
  input         control_fifo_ack                RXC_CK_IN_TIMING verilog_node TOP.cpu.rtx.zcp_dmc_ack1";

  output        control_fifo_req                RXC_CK_OUT_TIMING verilog_node TOP.cpu.rtx.dmc_zcp_req1";

  input         clk                             RXC_CK_CLK_TIMING verilog_node TOP.cpu.rtx.iol2clk";
}
#else
interface dmc_zcp_port0_if{
  input [129:0] control_fifo_data               RXC_CK_IN_TIMING verilog_node RXC_DUV_PATH.zcp_dmc_dat0";
  input         control_fifo_ful_pkt            RXC_CK_IN_TIMING verilog_node RXC_DUV_PATH.zcp_dmc_ful_pkt0";
//input         control_fifo_empty              RXC_CK_IN_TIMING verilog_node RXC_DUV_PATH.zcp_dmc_emp0";
  input         control_fifo_err                RXC_CK_IN_TIMING verilog_node RXC_DUV_PATH.zcp_dmc_dat_err0";
  input         control_fifo_ack                RXC_CK_IN_TIMING verilog_node RXC_DUV_PATH.zcp_dmc_ack0";

  output        control_fifo_req                RXC_CK_OUT_TIMING verilog_node RXC_DUV_PATH.dmc_zcp_req0";

  input         clk                             RXC_CK_CLK_TIMING verilog_node RXC_DUV_PATH.niu_clk";
}

interface dmc_zcp_port1_if{
  input [129:0] control_fifo_data               RXC_CK_IN_TIMING verilog_node RXC_DUV_PATH.zcp_dmc_dat1";
  input         control_fifo_ful_pkt            RXC_CK_IN_TIMING verilog_node RXC_DUV_PATH.zcp_dmc_ful_pkt1";
//input         control_fifo_empty              RXC_CK_IN_TIMING verilog_node RXC_DUV_PATH.zcp_dmc_emp1";
  input         control_fifo_err                RXC_CK_IN_TIMING verilog_node RXC_DUV_PATH.zcp_dmc_dat_err1";
  input         control_fifo_ack                RXC_CK_IN_TIMING verilog_node RXC_DUV_PATH.zcp_dmc_ack1";

  output        control_fifo_req                RXC_CK_OUT_TIMING verilog_node RXC_DUV_PATH.dmc_zcp_req1";

  input         clk                             RXC_CK_CLK_TIMING verilog_node RXC_DUV_PATH.niu_clk";
}
#endif

#endif

#ifdef MAC_SAT
#else
port dmc_zcp_drv_port{
  control_fifo_data;
  control_fifo_ful_pkt;
//control_fifo_empty;
  control_fifo_err;
  control_fifo_ack;
  control_fifo_req;
  clk;
}
#endif

#ifdef MAC_SAT
#else
bind dmc_zcp_drv_port dmc_zcp_drv0{
        control_fifo_data               dmc_zcp_port0_if.control_fifo_data;
        control_fifo_ful_pkt            dmc_zcp_port0_if.control_fifo_ful_pkt;
        //control_fifo_empty            dmc_zcp_port0_if.control_fifo_empty;
        control_fifo_err                dmc_zcp_port0_if.control_fifo_err;
        control_fifo_ack                dmc_zcp_port0_if.control_fifo_ack;
        control_fifo_req                dmc_zcp_port0_if.control_fifo_req;
        clk                             dmc_zcp_port0_if.clk;
}

bind dmc_zcp_drv_port dmc_zcp_drv1{
        control_fifo_data               dmc_zcp_port1_if.control_fifo_data;
        control_fifo_ful_pkt            dmc_zcp_port1_if.control_fifo_ful_pkt;
        //control_fifo_empty            dmc_zcp_port1_if.control_fifo_empty;
        control_fifo_err                dmc_zcp_port1_if.control_fifo_err;
        control_fifo_ack                dmc_zcp_port1_if.control_fifo_ack;
        control_fifo_req                dmc_zcp_port1_if.control_fifo_req;
        clk                             dmc_zcp_port1_if.clk;
}

#endif
#endif