verif/env/niu/vera/niu_pio/txc_util.vr

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//
// OpenSPARC T2 Processor File: txc_util.vr
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
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#include <vera_defines.vrh>
#include "txc_memory_map.vri"
#include "dmc_memory_map.vri"
#include "mac_defines.vri"
#include "pio_driver.vrh"
//#include "ncu_stub.vrh"
// extern Cncu_stub ncu_driver;
extern niu_gen_pio gen_pio_drv;

class txc_util_class {

        task new( ) {
        }

        task txc_init ((bit [63:0] data = 64'h1f));
        task write_train_vec(bit [31:0] data);
        task write_tdmc_train_vec(bit [31:0] data);
        task write_txc_dbgsel(bit [5:0] data);
        task write_tdmc_dbgsel(bit [5:0] data);
}


task txc_util_class::txc_init((bit [63:0] data = 64'h1f)) {

    bit [39:0] address;
    bit [63:0] w_data;
    bit [63:0] r_data;


// For DMA0


// Initialize DRR MAX BurstValue

        address = TXC_FZC_BASE + TXC_CONTROL;
        // w_data = 64'h1f; // Enable MAC All Ports and TXC
        w_data = data; // Enable MAC All Ports and TXC
        // ncu_driver.write_data(address,w_data);
        gen_pio_drv.pio_wr(address,w_data);
        printf(" Done with TXC_INIT \n");


}

task txc_util_class::write_train_vec(bit [31:0] data) {

   bit [39:0] address;
   bit [63:0] w_data;
   bit [63:0] r_data;

   w_data = {32'h0,data};

   address = TXC_FZC_BASE + TXC_TRAINING;
   gen_pio_drv.pio_wr(address,w_data);

   repeat (10) @(posedge CLOCK);

   address = TXC_FZC_BASE + TXC_TRAINING;
   gen_pio_drv.pio_rd(address,r_data);

}

task txc_util_class::write_tdmc_train_vec(bit [31:0] data) {

   bit [39:0] address;
   bit [63:0] w_data;
   bit [63:0] r_data;

   w_data = {32'h0,data};

   address = TDMC_TRAIN_VEC;
   gen_pio_drv.pio_wr(address,w_data);

   repeat (10) @(posedge CLOCK);

   address = TDMC_TRAIN_VEC;
   gen_pio_drv.pio_rd(address,r_data);

}


task txc_util_class::write_txc_dbgsel(bit [5:0] data) {

   bit [39:0] address;
   bit [63:0] w_data;
   bit [63:0] r_data;

   w_data = {58'h0,data};
   address = TXC_FZC_BASE + TXC_DEBUG_SELECT;
   gen_pio_drv.pio_wr(address,w_data);

   repeat (10) @(posedge CLOCK);

   address = TXC_FZC_BASE + TXC_DEBUG_SELECT;
   gen_pio_drv.pio_rd(address,r_data);
}

task txc_util_class::write_tdmc_dbgsel(bit [5:0] data) {

   bit [39:0] address;
   bit [63:0] w_data;
   bit [63:0] r_data;

   w_data = {58'h0,data};
   address = TDMC_DBG_SEL;
   gen_pio_drv.pio_wr(address,w_data);

   repeat (10) @(posedge CLOCK);

   address = TDMC_DBG_SEL;
   gen_pio_drv.pio_rd(address,r_data);
}