verif/env/niu/vera/niu_utils/include/niu_reset_port.vri

// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T2 Processor File: niu_reset_port.vri
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#define OUTPUT_EDGE PHOLD
#define INPUT_EDGE PSAMPLE #-1
#define OUTPUT_SKEW #1
#include "neptune_defines.vri"


interface niu_reset_if {
   #ifdef NIU_GATE
   input  clock CLOCK verilog_node NIU_DUV_PATH.rdp.iol2clk";
   #else
   input  clock CLOCK verilog_node NIU_DUV_PATH.rdp.niu_pio.niu_clk";
   #endif
   output niu_reset_l OUTPUT_EDGE OUTPUT_SKEW  verilog_node NIU_DUV_PATH.rdp.rst_por_";

}


port reset_port {
  clock;
  niu_reset_l;
}


bind reset_port reset_bind {

   clock niu_reset_if.clock;
   niu_reset_l niu_reset_if.niu_reset_l;

}