verif/env/niu/vera/smx_drv/include/meta_vco.vri

// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T2 Processor File: meta_vco.vri
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
//
// For the avoidance of doubt, and except that if any non-GPL license
// choice is available it will apply instead, Sun elects to use only
// the General Public License version 2 (GPLv2) at this time for any
// software where a choice of GPL license versions is made
// available with the language indicating that GPLv2 or any later version
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// otherwise unspecified.
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// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
// CA 95054 USA or visit www.sun.com if you need additional information or
// have any questions.
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// ========== Copyright Header End ============================================
coverage_group meta_write_cov
{
  sample_event = wait_var(write_info_cov_en);

  sample write_info_cov.wr_command {
    state wr_posted(0:255)
      if (write_info_cov.wr_command[5] == 1'b1);

    state wr_nonposted(0:255)
      if (write_info_cov.wr_command[5] == 1'b0);

    state wr_ordered(0:255)
      if (write_info_cov.wr_command[4] == 1'b1);

    state wr_nonordered(0:255)
      if (write_info_cov.wr_command[4] == 1'b0);

    state wr_64bit_addr(0:255)
      if (write_info_cov.wr_command[3] == 1'b1);

    state wr_32bit_addr(0:255)
      if (write_info_cov.wr_command[3] == 1'b0);
    bad_state wr_invalid_cmd(0:255)
      if (write_info_cov.wr_command[2:0] != 3'b001);
  }

  sample write_info_cov.wr_address_low {
    m_state wr_address_low(0:15);
  }

  sample write_info_cov.wr_length_low {
    m_state wr_length_low(0:15);

    state wr_length_even(0:15)
      if (write_info_cov.wr_length_low[0] == 1'b0);

    state wr_length_odd(0:15)
      if (write_info_cov.wr_length_low[0] == 1'b1);
  }

  sample write_info_cov.wr_dma_num {
    m_state wr_dma_num(0:31);
  }

  sample write_info_cov.wr_port_num {
    m_state wr_port_num(0:3);
  }

  sample write_info_cov.wr_transid {
    m_state wr_transid(0:63);
  }

  sample write_info_cov.wr_client_id {
    state wr_client_id0(1<<0);
    state wr_client_id1(1<<1);
    state wr_client_id2(1<<2);
    state wr_client_id3(1<<3);
    state wr_client_id4(1<<4);
    state wr_client_id5(1<<5);
    state wr_client_id6(1<<6);
    state wr_client_id7(1<<7);
  }

  sample write_info_cov.wr_first_byte_en {
    state wr_first_byte_enable01((1<< 1)-1); // 0000_0000_0000_0001
    state wr_first_byte_enable02((1<< 2)-1); // 0000_0000_0000_0011
    state wr_first_byte_enable03((1<< 3)-1); // 0000_0000_0000_0111
    state wr_first_byte_enable04((1<< 4)-1); // 0000_0000_0000_1111
    state wr_first_byte_enable05((1<< 5)-1); // 0000_0000_0001_1111
    state wr_first_byte_enable06((1<< 6)-1); // 0000_0000_0011_1111
    state wr_first_byte_enable07((1<< 7)-1); // 0000_0000_0111_1111
    state wr_first_byte_enable08((1<< 8)-1); // 0000_0000_1111_1111
    state wr_first_byte_enable09((1<< 9)-1); // 0000_0001_1111_1111
    state wr_first_byte_enable10((1<<10)-1); // 0000_0011_1111_1111
    state wr_first_byte_enable11((1<<11)-1); // 0000_0111_1111_1111
    state wr_first_byte_enable12((1<<12)-1); // 0000_1111_1111_1111
    state wr_first_byte_enable13((1<<13)-1); // 0001_1111_1111_1111
    state wr_first_byte_enable14((1<<14)-1); // 0011_1111_1111_1111
    state wr_first_byte_enable15((1<<15)-1); // 0111_1111_1111_1111
    state wr_first_byte_enable16((1<<16)-1); // 1111_1111_1111_1111
  }

  sample write_info_cov.wr_last_byte_en {
    bad_state wr_last_byte_enable_bad(0);   // 0000_0000_0000_0000
    state wr_last_byte_enable01((1<< 1)-1); // 0000_0000_0000_0001
    state wr_last_byte_enable02((1<< 2)-1); // 0000_0000_0000_0011
    state wr_last_byte_enable03((1<< 3)-1); // 0000_0000_0000_0111
    state wr_last_byte_enable04((1<< 4)-1); // 0000_0000_0000_1111
    state wr_last_byte_enable05((1<< 5)-1); // 0000_0000_0001_1111
    state wr_last_byte_enable06((1<< 6)-1); // 0000_0000_0011_1111
    state wr_last_byte_enable07((1<< 7)-1); // 0000_0000_0111_1111
    state wr_last_byte_enable08((1<< 8)-1); // 0000_0000_1111_1111
    state wr_last_byte_enable09((1<< 9)-1); // 0000_0001_1111_1111
    state wr_last_byte_enable10((1<<10)-1); // 0000_0011_1111_1111
    state wr_last_byte_enable11((1<<11)-1); // 0000_0111_1111_1111
    state wr_last_byte_enable12((1<<12)-1); // 0000_1111_1111_1111
    state wr_last_byte_enable13((1<<13)-1); // 0001_1111_1111_1111
    state wr_last_byte_enable14((1<<14)-1); // 0011_1111_1111_1111
    state wr_last_byte_enable15((1<<15)-1); // 0111_1111_1111_1111
    state wr_last_byte_enable16((1<<16)-1); // 1111_1111_1111_1111
  }

  sample write_info_cov.latency_wr_req_prev {
    state wr_req_b2b(0);

    state wr_req_not_b2b(0:1024)
      if (write_info_cov.latency_wr_req_prev > 0);
  }

  sample write_info_cov.latency_wr_req_accept {
    state wr_req_latency_fast(1);
    state wr_req_latency_best(2);
    state wr_req_latency_medium(3:9);
    state wr_req_latency_slow(10:100);
    state wr_req_latency_very_slow(101:1000);
  }

  sample write_info_cov.latency_wr_data_req {
    state wr_data_req_latency_fast(1);
    state wr_data_req_latency_best(2);
    state wr_data_req_latency_medium(3:9);
    state wr_data_req_latency_slow(10:100);
    state wr_data_req_latency_very_slow(101:1000);
  }

  sample write_info_cov.latency_wr_data_valid {
    state wr_data_valid_latency_fast(1:3);
    state wr_data_valid_latency_best(4);
    state wr_data_valid_latency_medium(5:9);
    state wr_data_valid_latency_slow(10:100);
    state wr_data_valid_latency_very_slow(101:1000);
  }

  sample write_info_cov.has_read_bubble {
    state has_read_bubble_true(1);
    state has_read_bubble_false(0);
  }
}

coverage_group meta_read_cov
{
  sample_event = wait_var(read_info_cov_en);

  sample read_info_cov.rd_command {
    state rd_ordered(0:255)
      if (read_info_cov.rd_command[4] == 1'b1);

    state rd_nonordered(0:255)
      if (read_info_cov.rd_command[4] == 1'b0);

    state rd_64bit_addr(0:255)
      if (read_info_cov.rd_command[3] == 1'b1);

    state rd_32bit_addr(0:255)
      if (read_info_cov.rd_command[3] == 1'b0);

    bad_state rd_invalid_cmd(0:255)
      if (read_info_cov.rd_command[2:0] != 3'b000);
  }

  sample read_info_cov.rd_address_low {
    m_state rd_address_low(0:15);
  }

  sample read_info_cov.rd_length_low {
    m_state rd_length_low(0:15);

    state rd_length_even(0:15)
      if (read_info_cov.rd_length_low[0] == 1'b0);

    state rd_length_odd(0:15)
      if (read_info_cov.rd_length_low[0] == 1'b1);
  }

  sample read_info_cov.rd_dma_num {
    m_state rd_dma_num(0:31);
  }

  sample read_info_cov.rd_port_num {
    m_state rd_port_num(0:3);
  }

  sample read_info_cov.rd_transid {
    m_state rd_transid(0:63);
  }

  sample read_info_cov.rd_client_id {
    state rd_client_id0(1<<0);
    state rd_client_id1(1<<1);
    state rd_client_id2(1<<2);
    state rd_client_id3(1<<3);
    state rd_client_id4(1<<4);
    state rd_client_id5(1<<5);
    state rd_client_id6(1<<6);
    state rd_client_id7(1<<7);
  }

  sample read_info_cov.latency_rd_req_prev {
    state rd_req_b2b(0);

    state rd_req_not_b2b(0:1024)
      if (read_info_cov.latency_rd_req_prev > 0);
  }

  sample read_info_cov.latency_rd_req_accept {
    state rd_req_latency_fast(1);
    state rd_req_latency_best(2);
    state rd_req_latency_medium(3:9);
    state rd_req_latency_slow(10:100);
    state rd_req_latency_very_slow(101:1000);
  }
}

coverage_group meta_resp_cov
{
  sample_event = wait_var(resp_info_cov_en);

  sample resp_info_cov.rp_command {
    state resp_cmd_cpl_with_data(0:255)
      if (resp_info_cov.rp_command[2:0] ==3'b101);

    state resp_cmd_cpl_without_data(0:255)
      if (resp_info_cov.rp_command[2:0] ==3'b110);

  //state resp_cmd_err_code(0:255); // review: Need error codes
  }

  sample resp_info_cov.rp_timeout {
    state resp_no_timeout(0);
    state resp_timeout(1);
  }

  sample resp_info_cov.rp_segment {
    state resp_not_segmented(0);
    state resp_segmented(1);
  }

  sample resp_info_cov.rp_has_resp_bubble {
    state resp_no_bubble(0);
    state resp_with_bubble(1);
  }

  sample resp_info_cov.rp_address_low {
    m_state rp_address_low(0:15);
  }

  sample resp_info_cov.rp_length_low {
    m_state rp_length_low(0:15);

    state rp_length_even(0:15)
      if (resp_info_cov.rp_length_low[0] == 1'b0);

    state rp_length_odd(0:15)
      if (resp_info_cov.rp_length_low[0] == 1'b1);
  }

  sample resp_info_cov.rp_dma_num {
    m_state rp_dma_num(0:31);
  }

  sample resp_info_cov.rp_port_num {
    m_state rp_port_num(0:3);
  }

  sample resp_info_cov.rp_transid {
    m_state rp_transid(0:63);
  }

  sample resp_info_cov.rp_client_id {
    state rp_client_id0(1<<0);
    state rp_client_id1(1<<1);
    state rp_client_id2(1<<2);
    state rp_client_id3(1<<3);
    state rp_client_id4(1<<4);
    state rp_client_id5(1<<5);
    state rp_client_id6(1<<6);
    state rp_client_id7(1<<7);
  }

  sample resp_info_cov.rp_first_byte_en {
    state rp_first_byte_enable_1_01(1<< 0); // 0000_0000_0000_0001
    state rp_first_byte_enable_1_02(1<< 1); // 0000_0000_0000_0010
    state rp_first_byte_enable_1_03(1<< 2); //
    state rp_first_byte_enable_1_04(1<< 3); //
    state rp_first_byte_enable_1_05(1<< 4); //
    state rp_first_byte_enable_1_06(1<< 5); //
    state rp_first_byte_enable_1_07(1<< 6); //
    state rp_first_byte_enable_1_08(1<< 7); //
    state rp_first_byte_enable_1_09(1<< 8); //         etc
    state rp_first_byte_enable_1_10(1<< 9); //
    state rp_first_byte_enable_1_11(1<<10); //
    state rp_first_byte_enable_1_12(1<<11); //
    state rp_first_byte_enable_1_13(1<<12); //
    state rp_first_byte_enable_1_14(1<<13); //
    state rp_first_byte_enable_1_15(1<<14); //
    state rp_first_byte_enable_1_16(1<<15); //

    state rp_first_byte_enable_2_01(3<< 0); // 0000_0000_0000_0011
    state rp_first_byte_enable_2_02(3<< 1); // 0000_0000_0000_0110
    state rp_first_byte_enable_2_03(3<< 2); //
    state rp_first_byte_enable_2_04(3<< 3); //
    state rp_first_byte_enable_2_05(3<< 4); //
    state rp_first_byte_enable_2_06(3<< 5); //
    state rp_first_byte_enable_2_07(3<< 6); //
    state rp_first_byte_enable_2_08(3<< 7); //
    state rp_first_byte_enable_2_09(3<< 8); //
    state rp_first_byte_enable_2_10(3<< 9); //
    state rp_first_byte_enable_2_11(3<<10); //
    state rp_first_byte_enable_2_12(3<<11); //
    state rp_first_byte_enable_2_13(3<<12); //
    state rp_first_byte_enable_2_14(3<<13); //
    state rp_first_byte_enable_2_15(3<<14); // 1100_0000_0000_0000

    state rp_first_byte_enable_3_01(7<< 0); // 0000_0000_0000_0111
    state rp_first_byte_enable_3_02(7<< 1); // 0000_0000_0000_1110
    state rp_first_byte_enable_3_03(7<< 2); //
    state rp_first_byte_enable_3_04(7<< 3); //
    state rp_first_byte_enable_3_05(7<< 4); //
    state rp_first_byte_enable_3_06(7<< 5); //
    state rp_first_byte_enable_3_07(7<< 6); //
    state rp_first_byte_enable_3_08(7<< 7); //
    state rp_first_byte_enable_3_09(7<< 8); //
    state rp_first_byte_enable_3_10(7<< 9); //
    state rp_first_byte_enable_3_11(7<<10); //
    state rp_first_byte_enable_3_12(7<<11); //
    state rp_first_byte_enable_3_13(7<<12); //
    state rp_first_byte_enable_3_14(7<<13); // 1110_0000_0000_0000
  }

  sample resp_info_cov.latency_resp_prev {
    state resp_not_b2b(1:1000);
    state resp_b2b(1);
  }

  sample resp_info_cov.latency_resp_accept {
    state resp_accept_latency_fast(1);
    state resp_accept_latency_best(2);
    state resp_accept_latency_medium(3:9);
    state resp_accept_latency_slow(10:100);
    state resp_accept_latency_very_slow(101:1000);
  }

  sample resp_info_cov.latency_resp_data_valid {
    state resp_data_valid_latency_best(1);
    state resp_data_valid_latency_medium(2:9);
    state resp_data_valid_latency_slow(10:100);
    state resp_data_valid_latency_very_slow(101:1000);
  }
}

// End