verif/env/niu/vera/smx_drv/include/smx_drv_ports.if.vri

// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T2 Processor File: smx_drv_ports.if.vri
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
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// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
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// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
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// choice is available it will apply instead, Sun elects to use only
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// ========== Copyright Header End ============================================
#define SMX_CK_IN_TIMING PSAMPLE #-1
#define SMX_CK_OUT_TIMING PHOLD #1
#define SMX_CK_CLK_TIMING  CLOCK
#include "neptune_defines.vri"

#define META_PATH NIU_DUV_PATH.tds

/*
interface dmc_send_q_if {

// Send Queue releated Signals
  input [7:0]   dmc_smx_cmd_req SMX_CK_IN_TIMING ;
  input [63:0]  dmc_smx_address SMX_CK_IN_TIMING ;
  input [5:0]   dmc_smx_transid SMX_CK_IN_TIMING;
  input [15:0]  dmc_smx_length SMX_CK_IN_TIMING;
  input         dmc_smx_valid SMX_CK_IN_TIMING;

  output        smx_dmc_grant SMX_CK_OUT_TIMING;
  output        smx_dmc_xfer_data_req SMX_CK_OUT_TIMING;

  input         dmc_smx_xfer_data_ack SMX_CK_IN_TIMING;
  input [4:0]   dmc_smx_xfer_status SMX_CK_IN_TIMING;
  input [127:0] dmc_smx_data SMX_CK_IN_TIMING;

  input         clk SMX_CK_CLK_TIMING;


}

interface dmc_receive_q_if {

// Receive Queue related Signals

  output [7:0]   smx_dmc_cmd_req SMX_CK_OUT_TIMING ;
  output [63:0]  smx_dmc_address SMX_CK_OUT_TIMING ;
  output [5:0]   smx_dmc_transid SMX_CK_OUT_TIMING;
  output [15:0]  smx_dmc_length SMX_CK_OUT_TIMING;
  output         smx_dmc_valid SMX_CK_OUT_TIMING;

  input         dmc_smx_grant SMX_CK_IN_TIMING;
  input         dmc_smx_xfer_data_req SMX_CK_IN_TIMING;

  output        smx_dmc_xfer_data_ack SMX_CK_OUT_TIMING;
  output [4:0]   smx_dmc_xfer_status SMX_CK_OUT_TIMING;
  output [127:0] smx_dmc_data SMX_CK_OUT_TIMING;

  input         clk SMX_CK_CLK_TIMING;


}

*/

#ifdef NIU_GATE

interface dmc_txc_sb_if {
// TX-SMX - Sideband Signals

  input clk SMX_CK_CLK_TIMING verilog_node META_PATH.iol2clk";

  input [1:0] dmc_smx_tx_port_num SMX_CK_IN_TIMING verilog_node META_PATH.dmc_smx_port_num";
  input [4:0] dmc_smx_tx_dma_num SMX_CK_IN_TIMING verilog_node META_PATH.dmc_smx_dma_num";
  output [1:0] smx_dmc_tx_port_num SMX_CK_OUT_TIMING verilog_node META_PATH.smx_dmc_port_num";
  output [4:0] smx_dmc_tx_dma_num SMX_CK_OUT_TIMING verilog_node META_PATH.smx_dmc_dma_num";

}

#else

interface dmc_txc_sb_if {
// TX-SMX - Sideband Signals

  input clk SMX_CK_CLK_TIMING verilog_node META_PATH.niu_smx.niu_clk";

  input [1:0] dmc_smx_tx_port_num SMX_CK_IN_TIMING verilog_node META_PATH.dmc_smx_port_num";
  input [4:0] dmc_smx_tx_dma_num SMX_CK_IN_TIMING verilog_node META_PATH.dmc_smx_dma_num";
  output [1:0] smx_dmc_tx_port_num SMX_CK_OUT_TIMING verilog_node META_PATH.smx_dmc_port_num";
  output [4:0] smx_dmc_tx_dma_num SMX_CK_OUT_TIMING verilog_node META_PATH.smx_dmc_dma_num";

}

#endif

interface dmc_send_q_if {

// Send Queue releated Signals
  input [7:0]   dmc_smx_cmd_req SMX_CK_IN_TIMING verilog_node META_PATH.dmc_smx_cmd_req" ;
  input [63:0]  dmc_smx_address SMX_CK_IN_TIMING verilog_node META_PATH.dmc_smx_address";
  // input [5:0]   dmc_smx_transid SMX_CK_IN_TIMING verilog_node "neptune_tb_top.dmc_smx_transid";
  input [5:0]   dmc_smx_transid SMX_CK_IN_TIMING verilog_node META_PATH.dmc_smx_transID";
  input [15:0]  dmc_smx_length SMX_CK_IN_TIMING  verilog_node META_PATH.dmc_smx_length";
  input         dmc_smx_valid SMX_CK_IN_TIMING   verilog_node META_PATH.dmc_smx_valid";

  output        smx_dmc_grant SMX_CK_OUT_TIMING  verilog_node META_PATH.smx_dmc_grant";
  output        smx_dmc_xfer_data_req SMX_CK_OUT_TIMING verilog_node META_PATH.smx_dmc_xfer_data_req" ;

  input         dmc_smx_xfer_data_ack SMX_CK_IN_TIMING verilog_node META_PATH.dmc_smx_xfer_data_ack" ;
  input [4:0]   dmc_smx_xfer_status SMX_CK_IN_TIMING  verilog_node META_PATH.dmc_smx_xfer_status" ;
  input [127:0] dmc_smx_data SMX_CK_IN_TIMING verilog_node META_PATH.dmc_smx_data"  ;

  input         clk SMX_CK_CLK_TIMING  verilog_node META_PATH.clk";


}

interface dmc_receive_q_if {

// Receive Queue related Signals

  output [7:0]   smx_dmc_cmd_req SMX_CK_OUT_TIMING verilog_node META_PATH.smx_dmc_cmd_req" ;
  output [63:0]  smx_dmc_address SMX_CK_OUT_TIMING verilog_node META_PATH.smx_dmc_address" ;
  // output [5:0]   smx_dmc_transid SMX_CK_OUT_TIMING verilog_node "neptune_tb_top.smx_dmc_transid" ;
  output [5:0]   smx_dmc_transid SMX_CK_OUT_TIMING verilog_node META_PATH.smx_dmc_transID" ;
  output [15:0]  smx_dmc_length SMX_CK_OUT_TIMING verilog_node META_PATH.smx_dmc_length" ;
  output         smx_dmc_valid SMX_CK_OUT_TIMING  verilog_node META_PATH.smx_dmc_valid" ;

  input         dmc_smx_grant SMX_CK_IN_TIMING verilog_node META_PATH.dmc_smx_grant"  ;
  input         dmc_smx_xfer_data_req SMX_CK_IN_TIMING verilog_node META_PATH.dmc_smx_xfer_data_req";

  output        smx_dmc_xfer_data_ack SMX_CK_OUT_TIMING verilog_node META_PATH.smx_dmc_xfer_data_ack" ;
  output [4:0]   smx_dmc_xfer_status SMX_CK_OUT_TIMING  verilog_node META_PATH.smx_dmc_xfer_status" ;
  output [127:0] smx_dmc_data SMX_CK_OUT_TIMING verilog_node META_PATH.smx_dmc_data" ;

#ifdef NIU_GATE
  input         clk SMX_CK_CLK_TIMING verilog_node META_PATH.iol2clk" ;
#else
  input         clk SMX_CK_CLK_TIMING verilog_node META_PATH.smx.niu_clk" ;
#endif


}


port dmc_send_port {

        clk;
        s_cmd_req;
        s_address;
        s_transid;
        s_length;
        s_valid;
        s_grant;
        s_data_req;
        s_data_ack;
        s_status;
        s_data;


}
port dmc_receive_port {

        clk;
        r_cmd_req;
        r_address;
        r_transid;
        r_length;
        r_valid;
        r_grant;
        r_data_req;
        r_data_ack;
        r_status;
        r_data;

}

port smx_tx_sb_ports {

        clk;
        dmctx_port_num;
        dmctx_dma_num;
        txdmc_port_num;
        txdmc_dma_num;

}

bind smx_tx_sb_ports tx_sb_pbind {
      clk dmc_txc_sb_if.clk;
      txdmc_port_num dmc_txc_sb_if.dmc_smx_tx_port_num;
      txdmc_dma_num dmc_txc_sb_if.dmc_smx_tx_dma_num;
      dmctx_port_num dmc_txc_sb_if.smx_dmc_tx_port_num;
      dmctx_dma_num dmc_txc_sb_if.smx_dmc_tx_dma_num;
}

bind dmc_send_port dmc_send_pbind {


        clk             dmc_send_q_if.clk;
        s_cmd_req       dmc_send_q_if.dmc_smx_cmd_req;
        s_address       dmc_send_q_if.dmc_smx_address;
        s_transid       dmc_send_q_if.dmc_smx_transid;
        s_length        dmc_send_q_if.dmc_smx_length;
        s_valid         dmc_send_q_if.dmc_smx_valid;
        s_grant         dmc_send_q_if.smx_dmc_grant;
        s_data_req      dmc_send_q_if.smx_dmc_xfer_data_req;
        s_data_ack      dmc_send_q_if.dmc_smx_xfer_data_ack;
        s_status        dmc_send_q_if.dmc_smx_xfer_status;
        s_data          dmc_send_q_if.dmc_smx_data;
}


bind dmc_receive_port dmc_receive_pbind {


        clk             dmc_receive_q_if.clk;
        r_cmd_req       dmc_receive_q_if.smx_dmc_cmd_req;
        r_address       dmc_receive_q_if.smx_dmc_address;
        r_transid       dmc_receive_q_if.smx_dmc_transid;
        r_length        dmc_receive_q_if.smx_dmc_length;
        r_valid         dmc_receive_q_if.smx_dmc_valid;
        r_grant         dmc_receive_q_if.dmc_smx_grant;
        r_data_req      dmc_receive_q_if.dmc_smx_xfer_data_req;
        r_data_ack      dmc_receive_q_if.smx_dmc_xfer_data_ack;
        r_status        dmc_receive_q_if.smx_dmc_xfer_status;
        r_data          dmc_receive_q_if.smx_dmc_data;
}